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Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_119 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_119( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_107 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_107(); // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = 9'h100; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = 3'h4; // @[rawFloatFromRecFN.scala:52:28]
wire [1:0] _rawIn_isSpecial_T = 2'h2; // @[rawFloatFromRecFN.scala:53:28]
wire [9:0] rawIn_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [9:0] _rawIn_out_sExp_T = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [1:0] _rawIn_out_sig_T_1 = 2'h1; // @[rawFloatFromRecFN.scala:61:32]
wire [22:0] _rawIn_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49]
wire [24:0] rawIn_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [24:0] _rawIn_out_sig_T_3 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire rawIn_isZero = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}]
wire rawIn_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}]
wire rawIn_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}]
wire rawIn_isInf = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}]
wire rawIn_isZero_0 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}]
wire _rawIn_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}]
wire _rawIn_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}]
wire _rawIn_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}]
wire _rawIn_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}]
wire _io_exceptionFlags_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}]
wire _io_exceptionFlags_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}]
wire [4:0] io_exceptionFlags = 5'h0; // @[RecFNToRecFN.scala:44:5, :48:16, :65:54]
wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RecFNToRecFN.scala:44:5, :48:16, :65:54]
wire io_detectTininess = 1'h1; // @[rawFloatFromRecFN.scala:55:23, :57:36, :59:25, :61:35]
wire rawIn_sign = 1'h1; // @[rawFloatFromRecFN.scala:55:23, :57:36, :59:25, :61:35]
wire _rawIn_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:55:23, :57:36, :59:25, :61:35]
wire _rawIn_out_sign_T = 1'h1; // @[rawFloatFromRecFN.scala:55:23, :57:36, :59:25, :61:35]
wire _rawIn_out_sig_T = 1'h1; // @[rawFloatFromRecFN.scala:55:23, :57:36, :59:25, :61:35]
wire _io_exceptionFlags_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:55:23, :57:36, :59:25, :61:35]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] io_in = 33'h180000000; // @[RecFNToRecFN.scala:44:5, :48:16, :64:35]
wire [32:0] io_out = 33'h180000000; // @[RecFNToRecFN.scala:44:5, :48:16, :64:35]
wire [32:0] _io_out_T = 33'h180000000; // @[RecFNToRecFN.scala:44:5, :48:16, :64:35]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_71 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}}
wire next_state : UInt
wire next_uopc : UInt
wire next_lrs1_rtype : UInt
wire next_lrs2_rtype : UInt
regreset state : UInt<2>, clock, reset, UInt<2>(0h0)
regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0)
connect p1_poisoned, UInt<1>(0h0)
connect p2_poisoned, UInt<1>(0h0)
node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate slot_uop_uop.debug_tsrc
invalidate slot_uop_uop.debug_fsrc
invalidate slot_uop_uop.bp_xcpt_if
invalidate slot_uop_uop.bp_debug_if
invalidate slot_uop_uop.xcpt_ma_if
invalidate slot_uop_uop.xcpt_ae_if
invalidate slot_uop_uop.xcpt_pf_if
invalidate slot_uop_uop.fp_single
invalidate slot_uop_uop.fp_val
invalidate slot_uop_uop.frs3_en
invalidate slot_uop_uop.lrs2_rtype
invalidate slot_uop_uop.lrs1_rtype
invalidate slot_uop_uop.dst_rtype
invalidate slot_uop_uop.ldst_val
invalidate slot_uop_uop.lrs3
invalidate slot_uop_uop.lrs2
invalidate slot_uop_uop.lrs1
invalidate slot_uop_uop.ldst
invalidate slot_uop_uop.ldst_is_rs1
invalidate slot_uop_uop.flush_on_commit
invalidate slot_uop_uop.is_unique
invalidate slot_uop_uop.is_sys_pc2epc
invalidate slot_uop_uop.uses_stq
invalidate slot_uop_uop.uses_ldq
invalidate slot_uop_uop.is_amo
invalidate slot_uop_uop.is_fencei
invalidate slot_uop_uop.is_fence
invalidate slot_uop_uop.mem_signed
invalidate slot_uop_uop.mem_size
invalidate slot_uop_uop.mem_cmd
invalidate slot_uop_uop.bypassable
invalidate slot_uop_uop.exc_cause
invalidate slot_uop_uop.exception
invalidate slot_uop_uop.stale_pdst
invalidate slot_uop_uop.ppred_busy
invalidate slot_uop_uop.prs3_busy
invalidate slot_uop_uop.prs2_busy
invalidate slot_uop_uop.prs1_busy
invalidate slot_uop_uop.ppred
invalidate slot_uop_uop.prs3
invalidate slot_uop_uop.prs2
invalidate slot_uop_uop.prs1
invalidate slot_uop_uop.pdst
invalidate slot_uop_uop.rxq_idx
invalidate slot_uop_uop.stq_idx
invalidate slot_uop_uop.ldq_idx
invalidate slot_uop_uop.rob_idx
invalidate slot_uop_uop.csr_addr
invalidate slot_uop_uop.imm_packed
invalidate slot_uop_uop.taken
invalidate slot_uop_uop.pc_lob
invalidate slot_uop_uop.edge_inst
invalidate slot_uop_uop.ftq_idx
invalidate slot_uop_uop.br_tag
invalidate slot_uop_uop.br_mask
invalidate slot_uop_uop.is_sfb
invalidate slot_uop_uop.is_jal
invalidate slot_uop_uop.is_jalr
invalidate slot_uop_uop.is_br
invalidate slot_uop_uop.iw_p2_poisoned
invalidate slot_uop_uop.iw_p1_poisoned
invalidate slot_uop_uop.iw_state
invalidate slot_uop_uop.ctrl.is_std
invalidate slot_uop_uop.ctrl.is_sta
invalidate slot_uop_uop.ctrl.is_load
invalidate slot_uop_uop.ctrl.csr_cmd
invalidate slot_uop_uop.ctrl.fcn_dw
invalidate slot_uop_uop.ctrl.op_fcn
invalidate slot_uop_uop.ctrl.imm_sel
invalidate slot_uop_uop.ctrl.op2_sel
invalidate slot_uop_uop.ctrl.op1_sel
invalidate slot_uop_uop.ctrl.br_type
invalidate slot_uop_uop.fu_code
invalidate slot_uop_uop.iq_type
invalidate slot_uop_uop.debug_pc
invalidate slot_uop_uop.is_rvc
invalidate slot_uop_uop.debug_inst
invalidate slot_uop_uop.inst
invalidate slot_uop_uop.uopc
connect slot_uop_uop.uopc, UInt<7>(0h0)
connect slot_uop_uop.bypassable, UInt<1>(0h0)
connect slot_uop_uop.fp_val, UInt<1>(0h0)
connect slot_uop_uop.uses_stq, UInt<1>(0h0)
connect slot_uop_uop.uses_ldq, UInt<1>(0h0)
connect slot_uop_uop.pdst, UInt<1>(0h0)
connect slot_uop_uop.dst_rtype, UInt<2>(0h2)
wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate slot_uop_cs.is_std
invalidate slot_uop_cs.is_sta
invalidate slot_uop_cs.is_load
invalidate slot_uop_cs.csr_cmd
invalidate slot_uop_cs.fcn_dw
invalidate slot_uop_cs.op_fcn
invalidate slot_uop_cs.imm_sel
invalidate slot_uop_cs.op2_sel
invalidate slot_uop_cs.op1_sel
invalidate slot_uop_cs.br_type
connect slot_uop_cs.br_type, UInt<4>(0h0)
connect slot_uop_cs.csr_cmd, UInt<3>(0h0)
connect slot_uop_cs.is_load, UInt<1>(0h0)
connect slot_uop_cs.is_sta, UInt<1>(0h0)
connect slot_uop_cs.is_std, UInt<1>(0h0)
connect slot_uop_uop.ctrl, slot_uop_cs
regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop
node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
when io.kill :
connect state, UInt<2>(0h0)
else :
when io.in_uop.valid :
connect state, io.in_uop.bits.iw_state
else :
when io.clear :
connect state, UInt<2>(0h0)
else :
connect state, next_state
connect next_state, state
connect next_uopc, slot_uop.uopc
connect next_lrs1_rtype, slot_uop.lrs1_rtype
connect next_lrs2_rtype, slot_uop.lrs2_rtype
when io.kill :
connect next_state, UInt<2>(0h0)
else :
node _T = eq(state, UInt<2>(0h1))
node _T_1 = and(io.grant, _T)
node _T_2 = eq(state, UInt<2>(0h2))
node _T_3 = and(io.grant, _T_2)
node _T_4 = and(_T_3, p1)
node _T_5 = and(_T_4, p2)
node _T_6 = and(_T_5, ppred)
node _T_7 = or(_T_1, _T_6)
when _T_7 :
node _T_8 = or(p1_poisoned, p2_poisoned)
node _T_9 = and(io.ldspec_miss, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
connect next_state, UInt<2>(0h0)
else :
node _T_11 = eq(state, UInt<2>(0h2))
node _T_12 = and(io.grant, _T_11)
when _T_12 :
node _T_13 = or(p1_poisoned, p2_poisoned)
node _T_14 = and(io.ldspec_miss, _T_13)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
connect next_state, UInt<2>(0h1)
when p1 :
connect slot_uop.uopc, UInt<7>(0h3)
connect next_uopc, UInt<7>(0h3)
connect slot_uop.lrs1_rtype, UInt<2>(0h2)
connect next_lrs1_rtype, UInt<2>(0h2)
else :
connect slot_uop.lrs2_rtype, UInt<2>(0h2)
connect next_lrs2_rtype, UInt<2>(0h2)
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T_16 = eq(state, UInt<2>(0h0))
node _T_17 = or(_T_16, io.clear)
node _T_18 = or(_T_17, io.kill)
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
node _T_21 = eq(_T_18, UInt<1>(0h0))
when _T_21 :
printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf
assert(clock, _T_18, UInt<1>(0h1), "") : assert
wire next_p1 : UInt<1>
connect next_p1, p1
wire next_p2 : UInt<1>
connect next_p2, p2
wire next_p3 : UInt<1>
connect next_p3, p3
wire next_ppred : UInt<1>
connect next_ppred, ppred
when io.in_uop.valid :
node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0))
connect p1, _p1_T
node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0))
connect p2, _p2_T
node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0))
connect p3, _p3_T
node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0))
connect ppred, _ppred_T
node _T_22 = and(io.ldspec_miss, next_p1_poisoned)
when _T_22 :
node _T_23 = neq(next_uop.prs1, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1
assert(clock, _T_23, UInt<1>(0h1), "") : assert_1
connect p1, UInt<1>(0h0)
node _T_27 = and(io.ldspec_miss, next_p2_poisoned)
when _T_27 :
node _T_28 = neq(next_uop.prs2, UInt<1>(0h0))
node _T_29 = asUInt(reset)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
node _T_31 = eq(_T_28, UInt<1>(0h0))
when _T_31 :
printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2
assert(clock, _T_28, UInt<1>(0h1), "") : assert_2
connect p2, UInt<1>(0h0)
node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1)
node _T_33 = and(io.wakeup_ports[0].valid, _T_32)
when _T_33 :
connect p1, UInt<1>(0h1)
node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2)
node _T_35 = and(io.wakeup_ports[0].valid, _T_34)
when _T_35 :
connect p2, UInt<1>(0h1)
node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3)
node _T_37 = and(io.wakeup_ports[0].valid, _T_36)
when _T_37 :
connect p3, UInt<1>(0h1)
node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1)
node _T_39 = and(io.wakeup_ports[1].valid, _T_38)
when _T_39 :
connect p1, UInt<1>(0h1)
node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2)
node _T_41 = and(io.wakeup_ports[1].valid, _T_40)
when _T_41 :
connect p2, UInt<1>(0h1)
node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3)
node _T_43 = and(io.wakeup_ports[1].valid, _T_42)
when _T_43 :
connect p3, UInt<1>(0h1)
node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1)
node _T_45 = and(io.wakeup_ports[2].valid, _T_44)
when _T_45 :
connect p1, UInt<1>(0h1)
node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2)
node _T_47 = and(io.wakeup_ports[2].valid, _T_46)
when _T_47 :
connect p2, UInt<1>(0h1)
node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3)
node _T_49 = and(io.wakeup_ports[2].valid, _T_48)
when _T_49 :
connect p3, UInt<1>(0h1)
node _T_50 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs1)
node _T_51 = and(io.wakeup_ports[3].valid, _T_50)
when _T_51 :
connect p1, UInt<1>(0h1)
node _T_52 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs2)
node _T_53 = and(io.wakeup_ports[3].valid, _T_52)
when _T_53 :
connect p2, UInt<1>(0h1)
node _T_54 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs3)
node _T_55 = and(io.wakeup_ports[3].valid, _T_54)
when _T_55 :
connect p3, UInt<1>(0h1)
node _T_56 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs1)
node _T_57 = and(io.wakeup_ports[4].valid, _T_56)
when _T_57 :
connect p1, UInt<1>(0h1)
node _T_58 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs2)
node _T_59 = and(io.wakeup_ports[4].valid, _T_58)
when _T_59 :
connect p2, UInt<1>(0h1)
node _T_60 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs3)
node _T_61 = and(io.wakeup_ports[4].valid, _T_60)
when _T_61 :
connect p3, UInt<1>(0h1)
node _T_62 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs1)
node _T_63 = and(io.wakeup_ports[5].valid, _T_62)
when _T_63 :
connect p1, UInt<1>(0h1)
node _T_64 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs2)
node _T_65 = and(io.wakeup_ports[5].valid, _T_64)
when _T_65 :
connect p2, UInt<1>(0h1)
node _T_66 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs3)
node _T_67 = and(io.wakeup_ports[5].valid, _T_66)
when _T_67 :
connect p3, UInt<1>(0h1)
node _T_68 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs1)
node _T_69 = and(io.wakeup_ports[6].valid, _T_68)
when _T_69 :
connect p1, UInt<1>(0h1)
node _T_70 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs2)
node _T_71 = and(io.wakeup_ports[6].valid, _T_70)
when _T_71 :
connect p2, UInt<1>(0h1)
node _T_72 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs3)
node _T_73 = and(io.wakeup_ports[6].valid, _T_72)
when _T_73 :
connect p3, UInt<1>(0h1)
node _T_74 = eq(io.pred_wakeup_port.bits, next_uop.ppred)
node _T_75 = and(io.pred_wakeup_port.valid, _T_74)
when _T_75 :
connect ppred, UInt<1>(0h1)
node _T_76 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0))
node _T_77 = and(io.spec_ld_wakeup[0].valid, _T_76)
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3
assert(clock, _T_78, UInt<1>(0h1), "") : assert_3
node _T_82 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1)
node _T_83 = and(io.spec_ld_wakeup[0].valid, _T_82)
node _T_84 = eq(next_uop.lrs1_rtype, UInt<2>(0h0))
node _T_85 = and(_T_83, _T_84)
when _T_85 :
connect p1, UInt<1>(0h1)
connect p1_poisoned, UInt<1>(0h1)
node _T_86 = eq(next_p1_poisoned, UInt<1>(0h0))
node _T_87 = asUInt(reset)
node _T_88 = eq(_T_87, UInt<1>(0h0))
when _T_88 :
node _T_89 = eq(_T_86, UInt<1>(0h0))
when _T_89 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4
assert(clock, _T_86, UInt<1>(0h1), "") : assert_4
node _T_90 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2)
node _T_91 = and(io.spec_ld_wakeup[0].valid, _T_90)
node _T_92 = eq(next_uop.lrs2_rtype, UInt<2>(0h0))
node _T_93 = and(_T_91, _T_92)
when _T_93 :
connect p2, UInt<1>(0h1)
connect p2_poisoned, UInt<1>(0h1)
node _T_94 = eq(next_p2_poisoned, UInt<1>(0h0))
node _T_95 = asUInt(reset)
node _T_96 = eq(_T_95, UInt<1>(0h0))
when _T_96 :
node _T_97 = eq(_T_94, UInt<1>(0h0))
when _T_97 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5
assert(clock, _T_94, UInt<1>(0h1), "") : assert_5
node _next_br_mask_T = not(io.brupdate.b1.resolve_mask)
node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T)
node _T_98 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _T_99 = neq(_T_98, UInt<1>(0h0))
when _T_99 :
connect next_state, UInt<2>(0h0)
node _T_100 = eq(io.in_uop.valid, UInt<1>(0h0))
when _T_100 :
connect slot_uop.br_mask, next_br_mask
node _io_request_T = neq(state, UInt<2>(0h0))
node _io_request_T_1 = and(_io_request_T, p1)
node _io_request_T_2 = and(_io_request_T_1, p2)
node _io_request_T_3 = and(_io_request_T_2, p3)
node _io_request_T_4 = and(_io_request_T_3, ppred)
node _io_request_T_5 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5)
connect io.request, _io_request_T_6
node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal)
node high_priority = or(_high_priority_T, slot_uop.is_jalr)
node _io_request_hp_T = and(io.request, high_priority)
connect io.request_hp, _io_request_hp_T
node _T_101 = eq(state, UInt<2>(0h1))
when _T_101 :
node _io_request_T_7 = and(p1, p2)
node _io_request_T_8 = and(_io_request_T_7, p3)
node _io_request_T_9 = and(_io_request_T_8, ppred)
node _io_request_T_10 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10)
connect io.request, _io_request_T_11
else :
node _T_102 = eq(state, UInt<2>(0h2))
when _T_102 :
node _io_request_T_12 = or(p1, p2)
node _io_request_T_13 = and(_io_request_T_12, ppred)
node _io_request_T_14 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14)
connect io.request, _io_request_T_15
else :
connect io.request, UInt<1>(0h0)
node _io_valid_T = neq(state, UInt<2>(0h0))
connect io.valid, _io_valid_T
connect io.uop, slot_uop
connect io.uop.iw_p1_poisoned, p1_poisoned
connect io.uop.iw_p2_poisoned, p2_poisoned
node _may_vacate_T = eq(state, UInt<2>(0h1))
node _may_vacate_T_1 = eq(state, UInt<2>(0h2))
node _may_vacate_T_2 = and(_may_vacate_T_1, p1)
node _may_vacate_T_3 = and(_may_vacate_T_2, p2)
node _may_vacate_T_4 = and(_may_vacate_T_3, ppred)
node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4)
node may_vacate = and(io.grant, _may_vacate_T_5)
node _squash_grant_T = or(p1_poisoned, p2_poisoned)
node squash_grant = and(io.ldspec_miss, _squash_grant_T)
node _io_will_be_valid_T = neq(state, UInt<2>(0h0))
node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0))
node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1)
node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0))
node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3)
connect io.will_be_valid, _io_will_be_valid_T_4
connect io.out_uop, slot_uop
connect io.out_uop.iw_state, next_state
connect io.out_uop.uopc, next_uopc
connect io.out_uop.lrs1_rtype, next_lrs1_rtype
connect io.out_uop.lrs2_rtype, next_lrs2_rtype
connect io.out_uop.br_mask, next_br_mask
node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0))
connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T
node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0))
connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T
node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0))
connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T
node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0))
connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T
connect io.out_uop.iw_p1_poisoned, p1_poisoned
connect io.out_uop.iw_p2_poisoned, p2_poisoned
node _T_103 = eq(state, UInt<2>(0h2))
when _T_103 :
node _T_104 = and(p1, p2)
node _T_105 = and(_T_104, ppred)
when _T_105 :
skip
else :
node _T_106 = and(p1, ppred)
when _T_106 :
connect io.uop.uopc, slot_uop.uopc
connect io.uop.lrs2_rtype, UInt<2>(0h2)
else :
node _T_107 = and(p2, ppred)
when _T_107 :
connect io.uop.uopc, UInt<7>(0h3)
connect io.uop.lrs1_rtype, UInt<2>(0h2)
connect io.debug.p1, p1
connect io.debug.p2, p2
connect io.debug.p3, p3
connect io.debug.ppred, ppred
connect io.debug.state, state | module IssueSlot_71( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_ldspec_miss, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14]
input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ppred = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ppred = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ppred = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] next_uop_ppred = 5'h0; // @[issue-slot.scala:103:21]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy = 1'h0; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy = 1'h0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy = 1'h0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy = 1'h0; // @[issue-slot.scala:69:7]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire next_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:103:21]
wire next_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:103:21]
wire next_uop_prs3_busy = 1'h0; // @[issue-slot.scala:103:21]
wire next_uop_ppred_busy = 1'h0; // @[issue-slot.scala:103:21]
wire _p3_T = 1'h1; // @[issue-slot.scala:171:11]
wire _ppred_T = 1'h1; // @[issue-slot.scala:172:14]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [15:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg p1_poisoned; // @[issue-slot.scala:95:28]
assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
reg p2_poisoned; // @[issue-slot.scala:96:28]
assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
wire next_p1_poisoned = ~io_in_uop_valid_0 & p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29]
wire next_p2_poisoned = ~io_in_uop_valid_0 & p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :99:29, :100:29]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}]
wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18]
wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23]
assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17]
assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11]
wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11]
wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24]
wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24]
wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27]
wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_41 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_49
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_41( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_49 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_34 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_EntryData_34( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_g, // @[package.scala:268:18]
output io_y_ae, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c, // @[package.scala:268:18]
output io_y_fragmented_superpage // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_g = io_y_g_0; // @[package.scala:267:30]
assign io_y_ae = io_y_ae_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_7 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 3)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<2>(0h3))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 2, 0)
node _source_ok_T_31 = shr(io.in.a.bits.source, 3)
node _source_ok_T_32 = eq(_source_ok_T_31, UInt<2>(0h2))
node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<3>(0h7))
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 2, 0)
node _source_ok_T_37 = shr(io.in.a.bits.source, 3)
node _source_ok_T_38 = eq(_source_ok_T_37, UInt<4>(0h8))
node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39)
node _source_ok_T_41 = leq(source_ok_uncommonBits_6, UInt<3>(0h4))
node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41)
node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE : UInt<1>[11]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_36
connect _source_ok_WIRE[7], _source_ok_T_42
connect _source_ok_WIRE[8], _source_ok_T_43
connect _source_ok_WIRE[9], _source_ok_T_44
connect _source_ok_WIRE[10], _source_ok_T_45
node _source_ok_T_46 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[2])
node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[3])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[4])
node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[5])
node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[6])
node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[7])
node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[8])
node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[9])
node source_ok = or(_source_ok_T_54, _source_ok_WIRE[10])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0)
node _T_64 = shr(io.in.a.bits.source, 3)
node _T_65 = eq(_T_64, UInt<2>(0h3))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<3>(0h7))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0)
node _T_77 = shr(io.in.a.bits.source, 3)
node _T_78 = eq(_T_77, UInt<2>(0h2))
node _T_79 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_80 = and(_T_78, _T_79)
node _T_81 = leq(uncommonBits_5, UInt<3>(0h7))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(_T_82, UInt<1>(0h0))
node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = or(_T_83, _T_88)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0)
node _T_90 = shr(io.in.a.bits.source, 3)
node _T_91 = eq(_T_90, UInt<4>(0h8))
node _T_92 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_93 = and(_T_91, _T_92)
node _T_94 = leq(uncommonBits_6, UInt<3>(0h4))
node _T_95 = and(_T_93, _T_94)
node _T_96 = eq(_T_95, UInt<1>(0h0))
node _T_97 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_98 = cvt(_T_97)
node _T_99 = and(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = asSInt(_T_99)
node _T_101 = eq(_T_100, asSInt(UInt<1>(0h0)))
node _T_102 = or(_T_96, _T_101)
node _T_103 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_106 = cvt(_T_105)
node _T_107 = and(_T_106, asSInt(UInt<1>(0h0)))
node _T_108 = asSInt(_T_107)
node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0)))
node _T_110 = or(_T_104, _T_109)
node _T_111 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_112 = eq(_T_111, UInt<1>(0h0))
node _T_113 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_114 = cvt(_T_113)
node _T_115 = and(_T_114, asSInt(UInt<1>(0h0)))
node _T_116 = asSInt(_T_115)
node _T_117 = eq(_T_116, asSInt(UInt<1>(0h0)))
node _T_118 = or(_T_112, _T_117)
node _T_119 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_120 = eq(_T_119, UInt<1>(0h0))
node _T_121 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_122 = cvt(_T_121)
node _T_123 = and(_T_122, asSInt(UInt<1>(0h0)))
node _T_124 = asSInt(_T_123)
node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0)))
node _T_126 = or(_T_120, _T_125)
node _T_127 = and(_T_11, _T_24)
node _T_128 = and(_T_127, _T_37)
node _T_129 = and(_T_128, _T_50)
node _T_130 = and(_T_129, _T_63)
node _T_131 = and(_T_130, _T_76)
node _T_132 = and(_T_131, _T_89)
node _T_133 = and(_T_132, _T_102)
node _T_134 = and(_T_133, _T_110)
node _T_135 = and(_T_134, _T_118)
node _T_136 = and(_T_135, _T_126)
node _T_137 = asUInt(reset)
node _T_138 = eq(_T_137, UInt<1>(0h0))
when _T_138 :
node _T_139 = eq(_T_136, UInt<1>(0h0))
when _T_139 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_136, UInt<1>(0h1), "") : assert_1
node _T_140 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_140 :
node _T_141 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_142 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_143 = and(_T_141, _T_142)
node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_145 = shr(io.in.a.bits.source, 2)
node _T_146 = eq(_T_145, UInt<1>(0h0))
node _T_147 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_148 = and(_T_146, _T_147)
node _T_149 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_150 = and(_T_148, _T_149)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_151 = shr(io.in.a.bits.source, 2)
node _T_152 = eq(_T_151, UInt<1>(0h1))
node _T_153 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_154 = and(_T_152, _T_153)
node _T_155 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_156 = and(_T_154, _T_155)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_157 = shr(io.in.a.bits.source, 2)
node _T_158 = eq(_T_157, UInt<2>(0h2))
node _T_159 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_160 = and(_T_158, _T_159)
node _T_161 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_162 = and(_T_160, _T_161)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_163 = shr(io.in.a.bits.source, 2)
node _T_164 = eq(_T_163, UInt<2>(0h3))
node _T_165 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_166 = and(_T_164, _T_165)
node _T_167 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_168 = and(_T_166, _T_167)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0)
node _T_169 = shr(io.in.a.bits.source, 3)
node _T_170 = eq(_T_169, UInt<2>(0h3))
node _T_171 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_172 = and(_T_170, _T_171)
node _T_173 = leq(uncommonBits_11, UInt<3>(0h7))
node _T_174 = and(_T_172, _T_173)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0)
node _T_175 = shr(io.in.a.bits.source, 3)
node _T_176 = eq(_T_175, UInt<2>(0h2))
node _T_177 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_178 = and(_T_176, _T_177)
node _T_179 = leq(uncommonBits_12, UInt<3>(0h7))
node _T_180 = and(_T_178, _T_179)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0)
node _T_181 = shr(io.in.a.bits.source, 3)
node _T_182 = eq(_T_181, UInt<4>(0h8))
node _T_183 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_184 = and(_T_182, _T_183)
node _T_185 = leq(uncommonBits_13, UInt<3>(0h4))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_188 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_189 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_190 = or(_T_144, _T_150)
node _T_191 = or(_T_190, _T_156)
node _T_192 = or(_T_191, _T_162)
node _T_193 = or(_T_192, _T_168)
node _T_194 = or(_T_193, _T_174)
node _T_195 = or(_T_194, _T_180)
node _T_196 = or(_T_195, _T_186)
node _T_197 = or(_T_196, _T_187)
node _T_198 = or(_T_197, _T_188)
node _T_199 = or(_T_198, _T_189)
node _T_200 = and(_T_143, _T_199)
node _T_201 = or(UInt<1>(0h0), _T_200)
node _T_202 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_203 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_204 = cvt(_T_203)
node _T_205 = and(_T_204, asSInt(UInt<13>(0h1000)))
node _T_206 = asSInt(_T_205)
node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0)))
node _T_208 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_209 = cvt(_T_208)
node _T_210 = and(_T_209, asSInt(UInt<13>(0h1000)))
node _T_211 = asSInt(_T_210)
node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0)))
node _T_213 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_214 = cvt(_T_213)
node _T_215 = and(_T_214, asSInt(UInt<13>(0h1000)))
node _T_216 = asSInt(_T_215)
node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0)))
node _T_218 = or(_T_207, _T_212)
node _T_219 = or(_T_218, _T_217)
node _T_220 = and(_T_202, _T_219)
node _T_221 = or(UInt<1>(0h0), _T_220)
node _T_222 = and(_T_201, _T_221)
node _T_223 = asUInt(reset)
node _T_224 = eq(_T_223, UInt<1>(0h0))
when _T_224 :
node _T_225 = eq(_T_222, UInt<1>(0h0))
when _T_225 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_222, UInt<1>(0h1), "") : assert_2
node _T_226 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_227 = shr(io.in.a.bits.source, 2)
node _T_228 = eq(_T_227, UInt<1>(0h0))
node _T_229 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_230 = and(_T_228, _T_229)
node _T_231 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_232 = and(_T_230, _T_231)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_233 = shr(io.in.a.bits.source, 2)
node _T_234 = eq(_T_233, UInt<1>(0h1))
node _T_235 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_236 = and(_T_234, _T_235)
node _T_237 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_238 = and(_T_236, _T_237)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_239 = shr(io.in.a.bits.source, 2)
node _T_240 = eq(_T_239, UInt<2>(0h2))
node _T_241 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_242 = and(_T_240, _T_241)
node _T_243 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_244 = and(_T_242, _T_243)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_245 = shr(io.in.a.bits.source, 2)
node _T_246 = eq(_T_245, UInt<2>(0h3))
node _T_247 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_248 = and(_T_246, _T_247)
node _T_249 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 2, 0)
node _T_251 = shr(io.in.a.bits.source, 3)
node _T_252 = eq(_T_251, UInt<2>(0h3))
node _T_253 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_254 = and(_T_252, _T_253)
node _T_255 = leq(uncommonBits_18, UInt<3>(0h7))
node _T_256 = and(_T_254, _T_255)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0)
node _T_257 = shr(io.in.a.bits.source, 3)
node _T_258 = eq(_T_257, UInt<2>(0h2))
node _T_259 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_260 = and(_T_258, _T_259)
node _T_261 = leq(uncommonBits_19, UInt<3>(0h7))
node _T_262 = and(_T_260, _T_261)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 2, 0)
node _T_263 = shr(io.in.a.bits.source, 3)
node _T_264 = eq(_T_263, UInt<4>(0h8))
node _T_265 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_266 = and(_T_264, _T_265)
node _T_267 = leq(uncommonBits_20, UInt<3>(0h4))
node _T_268 = and(_T_266, _T_267)
node _T_269 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_270 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_271 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _WIRE : UInt<1>[11]
connect _WIRE[0], _T_226
connect _WIRE[1], _T_232
connect _WIRE[2], _T_238
connect _WIRE[3], _T_244
connect _WIRE[4], _T_250
connect _WIRE[5], _T_256
connect _WIRE[6], _T_262
connect _WIRE[7], _T_268
connect _WIRE[8], _T_269
connect _WIRE[9], _T_270
connect _WIRE[10], _T_271
node _T_272 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_273 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_274 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_275 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_276 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_277 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_278 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_279 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_280 = mux(_WIRE[7], _T_272, UInt<1>(0h0))
node _T_281 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_282 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_283 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_284 = or(_T_273, _T_274)
node _T_285 = or(_T_284, _T_275)
node _T_286 = or(_T_285, _T_276)
node _T_287 = or(_T_286, _T_277)
node _T_288 = or(_T_287, _T_278)
node _T_289 = or(_T_288, _T_279)
node _T_290 = or(_T_289, _T_280)
node _T_291 = or(_T_290, _T_281)
node _T_292 = or(_T_291, _T_282)
node _T_293 = or(_T_292, _T_283)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_293
node _T_294 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_295 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_296 = and(_T_294, _T_295)
node _T_297 = or(UInt<1>(0h0), _T_296)
node _T_298 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_299 = cvt(_T_298)
node _T_300 = and(_T_299, asSInt(UInt<13>(0h1000)))
node _T_301 = asSInt(_T_300)
node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0)))
node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_304 = cvt(_T_303)
node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000)))
node _T_306 = asSInt(_T_305)
node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0)))
node _T_308 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_309 = cvt(_T_308)
node _T_310 = and(_T_309, asSInt(UInt<13>(0h1000)))
node _T_311 = asSInt(_T_310)
node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0)))
node _T_313 = or(_T_302, _T_307)
node _T_314 = or(_T_313, _T_312)
node _T_315 = and(_T_297, _T_314)
node _T_316 = or(UInt<1>(0h0), _T_315)
node _T_317 = and(_WIRE_1, _T_316)
node _T_318 = asUInt(reset)
node _T_319 = eq(_T_318, UInt<1>(0h0))
when _T_319 :
node _T_320 = eq(_T_317, UInt<1>(0h0))
when _T_320 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_317, UInt<1>(0h1), "") : assert_3
node _T_321 = asUInt(reset)
node _T_322 = eq(_T_321, UInt<1>(0h0))
when _T_322 :
node _T_323 = eq(source_ok, UInt<1>(0h0))
when _T_323 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_324 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_325 = asUInt(reset)
node _T_326 = eq(_T_325, UInt<1>(0h0))
when _T_326 :
node _T_327 = eq(_T_324, UInt<1>(0h0))
when _T_327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_324, UInt<1>(0h1), "") : assert_5
node _T_328 = asUInt(reset)
node _T_329 = eq(_T_328, UInt<1>(0h0))
when _T_329 :
node _T_330 = eq(is_aligned, UInt<1>(0h0))
when _T_330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_331 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_332 = asUInt(reset)
node _T_333 = eq(_T_332, UInt<1>(0h0))
when _T_333 :
node _T_334 = eq(_T_331, UInt<1>(0h0))
when _T_334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_331, UInt<1>(0h1), "") : assert_7
node _T_335 = not(io.in.a.bits.mask)
node _T_336 = eq(_T_335, UInt<1>(0h0))
node _T_337 = asUInt(reset)
node _T_338 = eq(_T_337, UInt<1>(0h0))
when _T_338 :
node _T_339 = eq(_T_336, UInt<1>(0h0))
when _T_339 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_336, UInt<1>(0h1), "") : assert_8
node _T_340 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_T_340, UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_340, UInt<1>(0h1), "") : assert_9
node _T_344 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_344 :
node _T_345 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_346 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_347 = and(_T_345, _T_346)
node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_349 = shr(io.in.a.bits.source, 2)
node _T_350 = eq(_T_349, UInt<1>(0h0))
node _T_351 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_352 = and(_T_350, _T_351)
node _T_353 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_354 = and(_T_352, _T_353)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_355 = shr(io.in.a.bits.source, 2)
node _T_356 = eq(_T_355, UInt<1>(0h1))
node _T_357 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_358 = and(_T_356, _T_357)
node _T_359 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_360 = and(_T_358, _T_359)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_361 = shr(io.in.a.bits.source, 2)
node _T_362 = eq(_T_361, UInt<2>(0h2))
node _T_363 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_364 = and(_T_362, _T_363)
node _T_365 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_366 = and(_T_364, _T_365)
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_367 = shr(io.in.a.bits.source, 2)
node _T_368 = eq(_T_367, UInt<2>(0h3))
node _T_369 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_370 = and(_T_368, _T_369)
node _T_371 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_372 = and(_T_370, _T_371)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 2, 0)
node _T_373 = shr(io.in.a.bits.source, 3)
node _T_374 = eq(_T_373, UInt<2>(0h3))
node _T_375 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_376 = and(_T_374, _T_375)
node _T_377 = leq(uncommonBits_25, UInt<3>(0h7))
node _T_378 = and(_T_376, _T_377)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 2, 0)
node _T_379 = shr(io.in.a.bits.source, 3)
node _T_380 = eq(_T_379, UInt<2>(0h2))
node _T_381 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_382 = and(_T_380, _T_381)
node _T_383 = leq(uncommonBits_26, UInt<3>(0h7))
node _T_384 = and(_T_382, _T_383)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 2, 0)
node _T_385 = shr(io.in.a.bits.source, 3)
node _T_386 = eq(_T_385, UInt<4>(0h8))
node _T_387 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_388 = and(_T_386, _T_387)
node _T_389 = leq(uncommonBits_27, UInt<3>(0h4))
node _T_390 = and(_T_388, _T_389)
node _T_391 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_392 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_393 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_394 = or(_T_348, _T_354)
node _T_395 = or(_T_394, _T_360)
node _T_396 = or(_T_395, _T_366)
node _T_397 = or(_T_396, _T_372)
node _T_398 = or(_T_397, _T_378)
node _T_399 = or(_T_398, _T_384)
node _T_400 = or(_T_399, _T_390)
node _T_401 = or(_T_400, _T_391)
node _T_402 = or(_T_401, _T_392)
node _T_403 = or(_T_402, _T_393)
node _T_404 = and(_T_347, _T_403)
node _T_405 = or(UInt<1>(0h0), _T_404)
node _T_406 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_407 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_408 = cvt(_T_407)
node _T_409 = and(_T_408, asSInt(UInt<13>(0h1000)))
node _T_410 = asSInt(_T_409)
node _T_411 = eq(_T_410, asSInt(UInt<1>(0h0)))
node _T_412 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_413 = cvt(_T_412)
node _T_414 = and(_T_413, asSInt(UInt<13>(0h1000)))
node _T_415 = asSInt(_T_414)
node _T_416 = eq(_T_415, asSInt(UInt<1>(0h0)))
node _T_417 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_418 = cvt(_T_417)
node _T_419 = and(_T_418, asSInt(UInt<13>(0h1000)))
node _T_420 = asSInt(_T_419)
node _T_421 = eq(_T_420, asSInt(UInt<1>(0h0)))
node _T_422 = or(_T_411, _T_416)
node _T_423 = or(_T_422, _T_421)
node _T_424 = and(_T_406, _T_423)
node _T_425 = or(UInt<1>(0h0), _T_424)
node _T_426 = and(_T_405, _T_425)
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(_T_426, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_426, UInt<1>(0h1), "") : assert_10
node _T_430 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_431 = shr(io.in.a.bits.source, 2)
node _T_432 = eq(_T_431, UInt<1>(0h0))
node _T_433 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_434 = and(_T_432, _T_433)
node _T_435 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_436 = and(_T_434, _T_435)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_437 = shr(io.in.a.bits.source, 2)
node _T_438 = eq(_T_437, UInt<1>(0h1))
node _T_439 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_440 = and(_T_438, _T_439)
node _T_441 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_442 = and(_T_440, _T_441)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_443 = shr(io.in.a.bits.source, 2)
node _T_444 = eq(_T_443, UInt<2>(0h2))
node _T_445 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_446 = and(_T_444, _T_445)
node _T_447 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_448 = and(_T_446, _T_447)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_449 = shr(io.in.a.bits.source, 2)
node _T_450 = eq(_T_449, UInt<2>(0h3))
node _T_451 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_452 = and(_T_450, _T_451)
node _T_453 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_454 = and(_T_452, _T_453)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 2, 0)
node _T_455 = shr(io.in.a.bits.source, 3)
node _T_456 = eq(_T_455, UInt<2>(0h3))
node _T_457 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_458 = and(_T_456, _T_457)
node _T_459 = leq(uncommonBits_32, UInt<3>(0h7))
node _T_460 = and(_T_458, _T_459)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 2, 0)
node _T_461 = shr(io.in.a.bits.source, 3)
node _T_462 = eq(_T_461, UInt<2>(0h2))
node _T_463 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_464 = and(_T_462, _T_463)
node _T_465 = leq(uncommonBits_33, UInt<3>(0h7))
node _T_466 = and(_T_464, _T_465)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0)
node _T_467 = shr(io.in.a.bits.source, 3)
node _T_468 = eq(_T_467, UInt<4>(0h8))
node _T_469 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_470 = and(_T_468, _T_469)
node _T_471 = leq(uncommonBits_34, UInt<3>(0h4))
node _T_472 = and(_T_470, _T_471)
node _T_473 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_474 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_475 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _WIRE_2 : UInt<1>[11]
connect _WIRE_2[0], _T_430
connect _WIRE_2[1], _T_436
connect _WIRE_2[2], _T_442
connect _WIRE_2[3], _T_448
connect _WIRE_2[4], _T_454
connect _WIRE_2[5], _T_460
connect _WIRE_2[6], _T_466
connect _WIRE_2[7], _T_472
connect _WIRE_2[8], _T_473
connect _WIRE_2[9], _T_474
connect _WIRE_2[10], _T_475
node _T_476 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_477 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_478 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_479 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_480 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_481 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_482 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_483 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_484 = mux(_WIRE_2[7], _T_476, UInt<1>(0h0))
node _T_485 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_486 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_487 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_488 = or(_T_477, _T_478)
node _T_489 = or(_T_488, _T_479)
node _T_490 = or(_T_489, _T_480)
node _T_491 = or(_T_490, _T_481)
node _T_492 = or(_T_491, _T_482)
node _T_493 = or(_T_492, _T_483)
node _T_494 = or(_T_493, _T_484)
node _T_495 = or(_T_494, _T_485)
node _T_496 = or(_T_495, _T_486)
node _T_497 = or(_T_496, _T_487)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_497
node _T_498 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_499 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_500 = and(_T_498, _T_499)
node _T_501 = or(UInt<1>(0h0), _T_500)
node _T_502 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_503 = cvt(_T_502)
node _T_504 = and(_T_503, asSInt(UInt<13>(0h1000)))
node _T_505 = asSInt(_T_504)
node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0)))
node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_508 = cvt(_T_507)
node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000)))
node _T_510 = asSInt(_T_509)
node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0)))
node _T_512 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_513 = cvt(_T_512)
node _T_514 = and(_T_513, asSInt(UInt<13>(0h1000)))
node _T_515 = asSInt(_T_514)
node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0)))
node _T_517 = or(_T_506, _T_511)
node _T_518 = or(_T_517, _T_516)
node _T_519 = and(_T_501, _T_518)
node _T_520 = or(UInt<1>(0h0), _T_519)
node _T_521 = and(_WIRE_3, _T_520)
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_521, UInt<1>(0h1), "") : assert_11
node _T_525 = asUInt(reset)
node _T_526 = eq(_T_525, UInt<1>(0h0))
when _T_526 :
node _T_527 = eq(source_ok, UInt<1>(0h0))
when _T_527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_528 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_529 = asUInt(reset)
node _T_530 = eq(_T_529, UInt<1>(0h0))
when _T_530 :
node _T_531 = eq(_T_528, UInt<1>(0h0))
when _T_531 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_528, UInt<1>(0h1), "") : assert_13
node _T_532 = asUInt(reset)
node _T_533 = eq(_T_532, UInt<1>(0h0))
when _T_533 :
node _T_534 = eq(is_aligned, UInt<1>(0h0))
when _T_534 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_535 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_536 = asUInt(reset)
node _T_537 = eq(_T_536, UInt<1>(0h0))
when _T_537 :
node _T_538 = eq(_T_535, UInt<1>(0h0))
when _T_538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_535, UInt<1>(0h1), "") : assert_15
node _T_539 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_540 = asUInt(reset)
node _T_541 = eq(_T_540, UInt<1>(0h0))
when _T_541 :
node _T_542 = eq(_T_539, UInt<1>(0h0))
when _T_542 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_539, UInt<1>(0h1), "") : assert_16
node _T_543 = not(io.in.a.bits.mask)
node _T_544 = eq(_T_543, UInt<1>(0h0))
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_544, UInt<1>(0h1), "") : assert_17
node _T_548 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_548, UInt<1>(0h1), "") : assert_18
node _T_552 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_552 :
node _T_553 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_554 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_555 = and(_T_553, _T_554)
node _T_556 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_557 = shr(io.in.a.bits.source, 2)
node _T_558 = eq(_T_557, UInt<1>(0h0))
node _T_559 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_560 = and(_T_558, _T_559)
node _T_561 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_562 = and(_T_560, _T_561)
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_563 = shr(io.in.a.bits.source, 2)
node _T_564 = eq(_T_563, UInt<1>(0h1))
node _T_565 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_566 = and(_T_564, _T_565)
node _T_567 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_568 = and(_T_566, _T_567)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_569 = shr(io.in.a.bits.source, 2)
node _T_570 = eq(_T_569, UInt<2>(0h2))
node _T_571 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_572 = and(_T_570, _T_571)
node _T_573 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_574 = and(_T_572, _T_573)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_575 = shr(io.in.a.bits.source, 2)
node _T_576 = eq(_T_575, UInt<2>(0h3))
node _T_577 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_578 = and(_T_576, _T_577)
node _T_579 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_580 = and(_T_578, _T_579)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0)
node _T_581 = shr(io.in.a.bits.source, 3)
node _T_582 = eq(_T_581, UInt<2>(0h3))
node _T_583 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_584 = and(_T_582, _T_583)
node _T_585 = leq(uncommonBits_39, UInt<3>(0h7))
node _T_586 = and(_T_584, _T_585)
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 2, 0)
node _T_587 = shr(io.in.a.bits.source, 3)
node _T_588 = eq(_T_587, UInt<2>(0h2))
node _T_589 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_590 = and(_T_588, _T_589)
node _T_591 = leq(uncommonBits_40, UInt<3>(0h7))
node _T_592 = and(_T_590, _T_591)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 2, 0)
node _T_593 = shr(io.in.a.bits.source, 3)
node _T_594 = eq(_T_593, UInt<4>(0h8))
node _T_595 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_596 = and(_T_594, _T_595)
node _T_597 = leq(uncommonBits_41, UInt<3>(0h4))
node _T_598 = and(_T_596, _T_597)
node _T_599 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_600 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_601 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_602 = or(_T_556, _T_562)
node _T_603 = or(_T_602, _T_568)
node _T_604 = or(_T_603, _T_574)
node _T_605 = or(_T_604, _T_580)
node _T_606 = or(_T_605, _T_586)
node _T_607 = or(_T_606, _T_592)
node _T_608 = or(_T_607, _T_598)
node _T_609 = or(_T_608, _T_599)
node _T_610 = or(_T_609, _T_600)
node _T_611 = or(_T_610, _T_601)
node _T_612 = and(_T_555, _T_611)
node _T_613 = or(UInt<1>(0h0), _T_612)
node _T_614 = asUInt(reset)
node _T_615 = eq(_T_614, UInt<1>(0h0))
when _T_615 :
node _T_616 = eq(_T_613, UInt<1>(0h0))
when _T_616 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_613, UInt<1>(0h1), "") : assert_19
node _T_617 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_618 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_619 = and(_T_617, _T_618)
node _T_620 = or(UInt<1>(0h0), _T_619)
node _T_621 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_622 = cvt(_T_621)
node _T_623 = and(_T_622, asSInt(UInt<13>(0h1000)))
node _T_624 = asSInt(_T_623)
node _T_625 = eq(_T_624, asSInt(UInt<1>(0h0)))
node _T_626 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_627 = cvt(_T_626)
node _T_628 = and(_T_627, asSInt(UInt<13>(0h1000)))
node _T_629 = asSInt(_T_628)
node _T_630 = eq(_T_629, asSInt(UInt<1>(0h0)))
node _T_631 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_632 = cvt(_T_631)
node _T_633 = and(_T_632, asSInt(UInt<13>(0h1000)))
node _T_634 = asSInt(_T_633)
node _T_635 = eq(_T_634, asSInt(UInt<1>(0h0)))
node _T_636 = or(_T_625, _T_630)
node _T_637 = or(_T_636, _T_635)
node _T_638 = and(_T_620, _T_637)
node _T_639 = or(UInt<1>(0h0), _T_638)
node _T_640 = asUInt(reset)
node _T_641 = eq(_T_640, UInt<1>(0h0))
when _T_641 :
node _T_642 = eq(_T_639, UInt<1>(0h0))
when _T_642 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_639, UInt<1>(0h1), "") : assert_20
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(source_ok, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_646 = asUInt(reset)
node _T_647 = eq(_T_646, UInt<1>(0h0))
when _T_647 :
node _T_648 = eq(is_aligned, UInt<1>(0h0))
when _T_648 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_649 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_650 = asUInt(reset)
node _T_651 = eq(_T_650, UInt<1>(0h0))
when _T_651 :
node _T_652 = eq(_T_649, UInt<1>(0h0))
when _T_652 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_649, UInt<1>(0h1), "") : assert_23
node _T_653 = eq(io.in.a.bits.mask, mask)
node _T_654 = asUInt(reset)
node _T_655 = eq(_T_654, UInt<1>(0h0))
when _T_655 :
node _T_656 = eq(_T_653, UInt<1>(0h0))
when _T_656 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_653, UInt<1>(0h1), "") : assert_24
node _T_657 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_658 = asUInt(reset)
node _T_659 = eq(_T_658, UInt<1>(0h0))
when _T_659 :
node _T_660 = eq(_T_657, UInt<1>(0h0))
when _T_660 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_657, UInt<1>(0h1), "") : assert_25
node _T_661 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_661 :
node _T_662 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_663 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_664 = and(_T_662, _T_663)
node _T_665 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_666 = shr(io.in.a.bits.source, 2)
node _T_667 = eq(_T_666, UInt<1>(0h0))
node _T_668 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_669 = and(_T_667, _T_668)
node _T_670 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_671 = and(_T_669, _T_670)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_672 = shr(io.in.a.bits.source, 2)
node _T_673 = eq(_T_672, UInt<1>(0h1))
node _T_674 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_675 = and(_T_673, _T_674)
node _T_676 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_677 = and(_T_675, _T_676)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_678 = shr(io.in.a.bits.source, 2)
node _T_679 = eq(_T_678, UInt<2>(0h2))
node _T_680 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_681 = and(_T_679, _T_680)
node _T_682 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_683 = and(_T_681, _T_682)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_684 = shr(io.in.a.bits.source, 2)
node _T_685 = eq(_T_684, UInt<2>(0h3))
node _T_686 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_687 = and(_T_685, _T_686)
node _T_688 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_689 = and(_T_687, _T_688)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 2, 0)
node _T_690 = shr(io.in.a.bits.source, 3)
node _T_691 = eq(_T_690, UInt<2>(0h3))
node _T_692 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_693 = and(_T_691, _T_692)
node _T_694 = leq(uncommonBits_46, UInt<3>(0h7))
node _T_695 = and(_T_693, _T_694)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 2, 0)
node _T_696 = shr(io.in.a.bits.source, 3)
node _T_697 = eq(_T_696, UInt<2>(0h2))
node _T_698 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_699 = and(_T_697, _T_698)
node _T_700 = leq(uncommonBits_47, UInt<3>(0h7))
node _T_701 = and(_T_699, _T_700)
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 2, 0)
node _T_702 = shr(io.in.a.bits.source, 3)
node _T_703 = eq(_T_702, UInt<4>(0h8))
node _T_704 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_705 = and(_T_703, _T_704)
node _T_706 = leq(uncommonBits_48, UInt<3>(0h4))
node _T_707 = and(_T_705, _T_706)
node _T_708 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_709 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_710 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_711 = or(_T_665, _T_671)
node _T_712 = or(_T_711, _T_677)
node _T_713 = or(_T_712, _T_683)
node _T_714 = or(_T_713, _T_689)
node _T_715 = or(_T_714, _T_695)
node _T_716 = or(_T_715, _T_701)
node _T_717 = or(_T_716, _T_707)
node _T_718 = or(_T_717, _T_708)
node _T_719 = or(_T_718, _T_709)
node _T_720 = or(_T_719, _T_710)
node _T_721 = and(_T_664, _T_720)
node _T_722 = or(UInt<1>(0h0), _T_721)
node _T_723 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_724 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_725 = and(_T_723, _T_724)
node _T_726 = or(UInt<1>(0h0), _T_725)
node _T_727 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_728 = cvt(_T_727)
node _T_729 = and(_T_728, asSInt(UInt<13>(0h1000)))
node _T_730 = asSInt(_T_729)
node _T_731 = eq(_T_730, asSInt(UInt<1>(0h0)))
node _T_732 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_733 = cvt(_T_732)
node _T_734 = and(_T_733, asSInt(UInt<13>(0h1000)))
node _T_735 = asSInt(_T_734)
node _T_736 = eq(_T_735, asSInt(UInt<1>(0h0)))
node _T_737 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_738 = cvt(_T_737)
node _T_739 = and(_T_738, asSInt(UInt<13>(0h1000)))
node _T_740 = asSInt(_T_739)
node _T_741 = eq(_T_740, asSInt(UInt<1>(0h0)))
node _T_742 = or(_T_731, _T_736)
node _T_743 = or(_T_742, _T_741)
node _T_744 = and(_T_726, _T_743)
node _T_745 = or(UInt<1>(0h0), _T_744)
node _T_746 = and(_T_722, _T_745)
node _T_747 = asUInt(reset)
node _T_748 = eq(_T_747, UInt<1>(0h0))
when _T_748 :
node _T_749 = eq(_T_746, UInt<1>(0h0))
when _T_749 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_746, UInt<1>(0h1), "") : assert_26
node _T_750 = asUInt(reset)
node _T_751 = eq(_T_750, UInt<1>(0h0))
when _T_751 :
node _T_752 = eq(source_ok, UInt<1>(0h0))
when _T_752 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_753 = asUInt(reset)
node _T_754 = eq(_T_753, UInt<1>(0h0))
when _T_754 :
node _T_755 = eq(is_aligned, UInt<1>(0h0))
when _T_755 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_756 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_757 = asUInt(reset)
node _T_758 = eq(_T_757, UInt<1>(0h0))
when _T_758 :
node _T_759 = eq(_T_756, UInt<1>(0h0))
when _T_759 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_756, UInt<1>(0h1), "") : assert_29
node _T_760 = eq(io.in.a.bits.mask, mask)
node _T_761 = asUInt(reset)
node _T_762 = eq(_T_761, UInt<1>(0h0))
when _T_762 :
node _T_763 = eq(_T_760, UInt<1>(0h0))
when _T_763 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_760, UInt<1>(0h1), "") : assert_30
node _T_764 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_764 :
node _T_765 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_766 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_767 = and(_T_765, _T_766)
node _T_768 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_769 = shr(io.in.a.bits.source, 2)
node _T_770 = eq(_T_769, UInt<1>(0h0))
node _T_771 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_772 = and(_T_770, _T_771)
node _T_773 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_774 = and(_T_772, _T_773)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_775 = shr(io.in.a.bits.source, 2)
node _T_776 = eq(_T_775, UInt<1>(0h1))
node _T_777 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_778 = and(_T_776, _T_777)
node _T_779 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_780 = and(_T_778, _T_779)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_781 = shr(io.in.a.bits.source, 2)
node _T_782 = eq(_T_781, UInt<2>(0h2))
node _T_783 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_784 = and(_T_782, _T_783)
node _T_785 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_786 = and(_T_784, _T_785)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0)
node _T_787 = shr(io.in.a.bits.source, 2)
node _T_788 = eq(_T_787, UInt<2>(0h3))
node _T_789 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_790 = and(_T_788, _T_789)
node _T_791 = leq(uncommonBits_52, UInt<2>(0h3))
node _T_792 = and(_T_790, _T_791)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 2, 0)
node _T_793 = shr(io.in.a.bits.source, 3)
node _T_794 = eq(_T_793, UInt<2>(0h3))
node _T_795 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_796 = and(_T_794, _T_795)
node _T_797 = leq(uncommonBits_53, UInt<3>(0h7))
node _T_798 = and(_T_796, _T_797)
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0)
node _T_799 = shr(io.in.a.bits.source, 3)
node _T_800 = eq(_T_799, UInt<2>(0h2))
node _T_801 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_802 = and(_T_800, _T_801)
node _T_803 = leq(uncommonBits_54, UInt<3>(0h7))
node _T_804 = and(_T_802, _T_803)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 2, 0)
node _T_805 = shr(io.in.a.bits.source, 3)
node _T_806 = eq(_T_805, UInt<4>(0h8))
node _T_807 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_808 = and(_T_806, _T_807)
node _T_809 = leq(uncommonBits_55, UInt<3>(0h4))
node _T_810 = and(_T_808, _T_809)
node _T_811 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_812 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_813 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_814 = or(_T_768, _T_774)
node _T_815 = or(_T_814, _T_780)
node _T_816 = or(_T_815, _T_786)
node _T_817 = or(_T_816, _T_792)
node _T_818 = or(_T_817, _T_798)
node _T_819 = or(_T_818, _T_804)
node _T_820 = or(_T_819, _T_810)
node _T_821 = or(_T_820, _T_811)
node _T_822 = or(_T_821, _T_812)
node _T_823 = or(_T_822, _T_813)
node _T_824 = and(_T_767, _T_823)
node _T_825 = or(UInt<1>(0h0), _T_824)
node _T_826 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_827 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_828 = and(_T_826, _T_827)
node _T_829 = or(UInt<1>(0h0), _T_828)
node _T_830 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_831 = cvt(_T_830)
node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000)))
node _T_833 = asSInt(_T_832)
node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0)))
node _T_835 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_836 = cvt(_T_835)
node _T_837 = and(_T_836, asSInt(UInt<13>(0h1000)))
node _T_838 = asSInt(_T_837)
node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0)))
node _T_840 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_841 = cvt(_T_840)
node _T_842 = and(_T_841, asSInt(UInt<13>(0h1000)))
node _T_843 = asSInt(_T_842)
node _T_844 = eq(_T_843, asSInt(UInt<1>(0h0)))
node _T_845 = or(_T_834, _T_839)
node _T_846 = or(_T_845, _T_844)
node _T_847 = and(_T_829, _T_846)
node _T_848 = or(UInt<1>(0h0), _T_847)
node _T_849 = and(_T_825, _T_848)
node _T_850 = asUInt(reset)
node _T_851 = eq(_T_850, UInt<1>(0h0))
when _T_851 :
node _T_852 = eq(_T_849, UInt<1>(0h0))
when _T_852 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_849, UInt<1>(0h1), "") : assert_31
node _T_853 = asUInt(reset)
node _T_854 = eq(_T_853, UInt<1>(0h0))
when _T_854 :
node _T_855 = eq(source_ok, UInt<1>(0h0))
when _T_855 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_856 = asUInt(reset)
node _T_857 = eq(_T_856, UInt<1>(0h0))
when _T_857 :
node _T_858 = eq(is_aligned, UInt<1>(0h0))
when _T_858 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_859 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(_T_859, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_859, UInt<1>(0h1), "") : assert_34
node _T_863 = not(mask)
node _T_864 = and(io.in.a.bits.mask, _T_863)
node _T_865 = eq(_T_864, UInt<1>(0h0))
node _T_866 = asUInt(reset)
node _T_867 = eq(_T_866, UInt<1>(0h0))
when _T_867 :
node _T_868 = eq(_T_865, UInt<1>(0h0))
when _T_868 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_865, UInt<1>(0h1), "") : assert_35
node _T_869 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_869 :
node _T_870 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_871 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_872 = and(_T_870, _T_871)
node _T_873 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_874 = shr(io.in.a.bits.source, 2)
node _T_875 = eq(_T_874, UInt<1>(0h0))
node _T_876 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_877 = and(_T_875, _T_876)
node _T_878 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_879 = and(_T_877, _T_878)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_880 = shr(io.in.a.bits.source, 2)
node _T_881 = eq(_T_880, UInt<1>(0h1))
node _T_882 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_883 = and(_T_881, _T_882)
node _T_884 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_885 = and(_T_883, _T_884)
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0)
node _T_886 = shr(io.in.a.bits.source, 2)
node _T_887 = eq(_T_886, UInt<2>(0h2))
node _T_888 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_889 = and(_T_887, _T_888)
node _T_890 = leq(uncommonBits_58, UInt<2>(0h3))
node _T_891 = and(_T_889, _T_890)
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0)
node _T_892 = shr(io.in.a.bits.source, 2)
node _T_893 = eq(_T_892, UInt<2>(0h3))
node _T_894 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_895 = and(_T_893, _T_894)
node _T_896 = leq(uncommonBits_59, UInt<2>(0h3))
node _T_897 = and(_T_895, _T_896)
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 2, 0)
node _T_898 = shr(io.in.a.bits.source, 3)
node _T_899 = eq(_T_898, UInt<2>(0h3))
node _T_900 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_901 = and(_T_899, _T_900)
node _T_902 = leq(uncommonBits_60, UInt<3>(0h7))
node _T_903 = and(_T_901, _T_902)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 2, 0)
node _T_904 = shr(io.in.a.bits.source, 3)
node _T_905 = eq(_T_904, UInt<2>(0h2))
node _T_906 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_907 = and(_T_905, _T_906)
node _T_908 = leq(uncommonBits_61, UInt<3>(0h7))
node _T_909 = and(_T_907, _T_908)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 2, 0)
node _T_910 = shr(io.in.a.bits.source, 3)
node _T_911 = eq(_T_910, UInt<4>(0h8))
node _T_912 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_913 = and(_T_911, _T_912)
node _T_914 = leq(uncommonBits_62, UInt<3>(0h4))
node _T_915 = and(_T_913, _T_914)
node _T_916 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_917 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_918 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_919 = or(_T_873, _T_879)
node _T_920 = or(_T_919, _T_885)
node _T_921 = or(_T_920, _T_891)
node _T_922 = or(_T_921, _T_897)
node _T_923 = or(_T_922, _T_903)
node _T_924 = or(_T_923, _T_909)
node _T_925 = or(_T_924, _T_915)
node _T_926 = or(_T_925, _T_916)
node _T_927 = or(_T_926, _T_917)
node _T_928 = or(_T_927, _T_918)
node _T_929 = and(_T_872, _T_928)
node _T_930 = or(UInt<1>(0h0), _T_929)
node _T_931 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_932 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_933 = and(_T_931, _T_932)
node _T_934 = or(UInt<1>(0h0), _T_933)
node _T_935 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_936 = cvt(_T_935)
node _T_937 = and(_T_936, asSInt(UInt<13>(0h1000)))
node _T_938 = asSInt(_T_937)
node _T_939 = eq(_T_938, asSInt(UInt<1>(0h0)))
node _T_940 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_941 = cvt(_T_940)
node _T_942 = and(_T_941, asSInt(UInt<13>(0h1000)))
node _T_943 = asSInt(_T_942)
node _T_944 = eq(_T_943, asSInt(UInt<1>(0h0)))
node _T_945 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_946 = cvt(_T_945)
node _T_947 = and(_T_946, asSInt(UInt<13>(0h1000)))
node _T_948 = asSInt(_T_947)
node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0)))
node _T_950 = or(_T_939, _T_944)
node _T_951 = or(_T_950, _T_949)
node _T_952 = and(_T_934, _T_951)
node _T_953 = or(UInt<1>(0h0), _T_952)
node _T_954 = and(_T_930, _T_953)
node _T_955 = asUInt(reset)
node _T_956 = eq(_T_955, UInt<1>(0h0))
when _T_956 :
node _T_957 = eq(_T_954, UInt<1>(0h0))
when _T_957 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_954, UInt<1>(0h1), "") : assert_36
node _T_958 = asUInt(reset)
node _T_959 = eq(_T_958, UInt<1>(0h0))
when _T_959 :
node _T_960 = eq(source_ok, UInt<1>(0h0))
when _T_960 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_961 = asUInt(reset)
node _T_962 = eq(_T_961, UInt<1>(0h0))
when _T_962 :
node _T_963 = eq(is_aligned, UInt<1>(0h0))
when _T_963 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_964 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_965 = asUInt(reset)
node _T_966 = eq(_T_965, UInt<1>(0h0))
when _T_966 :
node _T_967 = eq(_T_964, UInt<1>(0h0))
when _T_967 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_964, UInt<1>(0h1), "") : assert_39
node _T_968 = eq(io.in.a.bits.mask, mask)
node _T_969 = asUInt(reset)
node _T_970 = eq(_T_969, UInt<1>(0h0))
when _T_970 :
node _T_971 = eq(_T_968, UInt<1>(0h0))
when _T_971 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_968, UInt<1>(0h1), "") : assert_40
node _T_972 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_972 :
node _T_973 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_974 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_975 = and(_T_973, _T_974)
node _T_976 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_977 = shr(io.in.a.bits.source, 2)
node _T_978 = eq(_T_977, UInt<1>(0h0))
node _T_979 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_980 = and(_T_978, _T_979)
node _T_981 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_982 = and(_T_980, _T_981)
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0)
node _T_983 = shr(io.in.a.bits.source, 2)
node _T_984 = eq(_T_983, UInt<1>(0h1))
node _T_985 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_986 = and(_T_984, _T_985)
node _T_987 = leq(uncommonBits_64, UInt<2>(0h3))
node _T_988 = and(_T_986, _T_987)
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0)
node _T_989 = shr(io.in.a.bits.source, 2)
node _T_990 = eq(_T_989, UInt<2>(0h2))
node _T_991 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_992 = and(_T_990, _T_991)
node _T_993 = leq(uncommonBits_65, UInt<2>(0h3))
node _T_994 = and(_T_992, _T_993)
node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0)
node _T_995 = shr(io.in.a.bits.source, 2)
node _T_996 = eq(_T_995, UInt<2>(0h3))
node _T_997 = leq(UInt<1>(0h0), uncommonBits_66)
node _T_998 = and(_T_996, _T_997)
node _T_999 = leq(uncommonBits_66, UInt<2>(0h3))
node _T_1000 = and(_T_998, _T_999)
node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_67 = bits(_uncommonBits_T_67, 2, 0)
node _T_1001 = shr(io.in.a.bits.source, 3)
node _T_1002 = eq(_T_1001, UInt<2>(0h3))
node _T_1003 = leq(UInt<1>(0h0), uncommonBits_67)
node _T_1004 = and(_T_1002, _T_1003)
node _T_1005 = leq(uncommonBits_67, UInt<3>(0h7))
node _T_1006 = and(_T_1004, _T_1005)
node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_68 = bits(_uncommonBits_T_68, 2, 0)
node _T_1007 = shr(io.in.a.bits.source, 3)
node _T_1008 = eq(_T_1007, UInt<2>(0h2))
node _T_1009 = leq(UInt<1>(0h0), uncommonBits_68)
node _T_1010 = and(_T_1008, _T_1009)
node _T_1011 = leq(uncommonBits_68, UInt<3>(0h7))
node _T_1012 = and(_T_1010, _T_1011)
node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_69 = bits(_uncommonBits_T_69, 2, 0)
node _T_1013 = shr(io.in.a.bits.source, 3)
node _T_1014 = eq(_T_1013, UInt<4>(0h8))
node _T_1015 = leq(UInt<1>(0h0), uncommonBits_69)
node _T_1016 = and(_T_1014, _T_1015)
node _T_1017 = leq(uncommonBits_69, UInt<3>(0h4))
node _T_1018 = and(_T_1016, _T_1017)
node _T_1019 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_1020 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_1021 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_1022 = or(_T_976, _T_982)
node _T_1023 = or(_T_1022, _T_988)
node _T_1024 = or(_T_1023, _T_994)
node _T_1025 = or(_T_1024, _T_1000)
node _T_1026 = or(_T_1025, _T_1006)
node _T_1027 = or(_T_1026, _T_1012)
node _T_1028 = or(_T_1027, _T_1018)
node _T_1029 = or(_T_1028, _T_1019)
node _T_1030 = or(_T_1029, _T_1020)
node _T_1031 = or(_T_1030, _T_1021)
node _T_1032 = and(_T_975, _T_1031)
node _T_1033 = or(UInt<1>(0h0), _T_1032)
node _T_1034 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1035 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1036 = and(_T_1034, _T_1035)
node _T_1037 = or(UInt<1>(0h0), _T_1036)
node _T_1038 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1039 = cvt(_T_1038)
node _T_1040 = and(_T_1039, asSInt(UInt<13>(0h1000)))
node _T_1041 = asSInt(_T_1040)
node _T_1042 = eq(_T_1041, asSInt(UInt<1>(0h0)))
node _T_1043 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_1044 = cvt(_T_1043)
node _T_1045 = and(_T_1044, asSInt(UInt<13>(0h1000)))
node _T_1046 = asSInt(_T_1045)
node _T_1047 = eq(_T_1046, asSInt(UInt<1>(0h0)))
node _T_1048 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1049 = cvt(_T_1048)
node _T_1050 = and(_T_1049, asSInt(UInt<13>(0h1000)))
node _T_1051 = asSInt(_T_1050)
node _T_1052 = eq(_T_1051, asSInt(UInt<1>(0h0)))
node _T_1053 = or(_T_1042, _T_1047)
node _T_1054 = or(_T_1053, _T_1052)
node _T_1055 = and(_T_1037, _T_1054)
node _T_1056 = or(UInt<1>(0h0), _T_1055)
node _T_1057 = and(_T_1033, _T_1056)
node _T_1058 = asUInt(reset)
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
when _T_1059 :
node _T_1060 = eq(_T_1057, UInt<1>(0h0))
when _T_1060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1057, UInt<1>(0h1), "") : assert_41
node _T_1061 = asUInt(reset)
node _T_1062 = eq(_T_1061, UInt<1>(0h0))
when _T_1062 :
node _T_1063 = eq(source_ok, UInt<1>(0h0))
when _T_1063 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1064 = asUInt(reset)
node _T_1065 = eq(_T_1064, UInt<1>(0h0))
when _T_1065 :
node _T_1066 = eq(is_aligned, UInt<1>(0h0))
when _T_1066 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1067 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1068 = asUInt(reset)
node _T_1069 = eq(_T_1068, UInt<1>(0h0))
when _T_1069 :
node _T_1070 = eq(_T_1067, UInt<1>(0h0))
when _T_1070 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1067, UInt<1>(0h1), "") : assert_44
node _T_1071 = eq(io.in.a.bits.mask, mask)
node _T_1072 = asUInt(reset)
node _T_1073 = eq(_T_1072, UInt<1>(0h0))
when _T_1073 :
node _T_1074 = eq(_T_1071, UInt<1>(0h0))
when _T_1074 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1071, UInt<1>(0h1), "") : assert_45
node _T_1075 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1075 :
node _T_1076 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1077 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1078 = and(_T_1076, _T_1077)
node _T_1079 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0)
node _T_1080 = shr(io.in.a.bits.source, 2)
node _T_1081 = eq(_T_1080, UInt<1>(0h0))
node _T_1082 = leq(UInt<1>(0h0), uncommonBits_70)
node _T_1083 = and(_T_1081, _T_1082)
node _T_1084 = leq(uncommonBits_70, UInt<2>(0h3))
node _T_1085 = and(_T_1083, _T_1084)
node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0)
node _T_1086 = shr(io.in.a.bits.source, 2)
node _T_1087 = eq(_T_1086, UInt<1>(0h1))
node _T_1088 = leq(UInt<1>(0h0), uncommonBits_71)
node _T_1089 = and(_T_1087, _T_1088)
node _T_1090 = leq(uncommonBits_71, UInt<2>(0h3))
node _T_1091 = and(_T_1089, _T_1090)
node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0)
node _T_1092 = shr(io.in.a.bits.source, 2)
node _T_1093 = eq(_T_1092, UInt<2>(0h2))
node _T_1094 = leq(UInt<1>(0h0), uncommonBits_72)
node _T_1095 = and(_T_1093, _T_1094)
node _T_1096 = leq(uncommonBits_72, UInt<2>(0h3))
node _T_1097 = and(_T_1095, _T_1096)
node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0)
node _T_1098 = shr(io.in.a.bits.source, 2)
node _T_1099 = eq(_T_1098, UInt<2>(0h3))
node _T_1100 = leq(UInt<1>(0h0), uncommonBits_73)
node _T_1101 = and(_T_1099, _T_1100)
node _T_1102 = leq(uncommonBits_73, UInt<2>(0h3))
node _T_1103 = and(_T_1101, _T_1102)
node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_74 = bits(_uncommonBits_T_74, 2, 0)
node _T_1104 = shr(io.in.a.bits.source, 3)
node _T_1105 = eq(_T_1104, UInt<2>(0h3))
node _T_1106 = leq(UInt<1>(0h0), uncommonBits_74)
node _T_1107 = and(_T_1105, _T_1106)
node _T_1108 = leq(uncommonBits_74, UInt<3>(0h7))
node _T_1109 = and(_T_1107, _T_1108)
node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_75 = bits(_uncommonBits_T_75, 2, 0)
node _T_1110 = shr(io.in.a.bits.source, 3)
node _T_1111 = eq(_T_1110, UInt<2>(0h2))
node _T_1112 = leq(UInt<1>(0h0), uncommonBits_75)
node _T_1113 = and(_T_1111, _T_1112)
node _T_1114 = leq(uncommonBits_75, UInt<3>(0h7))
node _T_1115 = and(_T_1113, _T_1114)
node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_76 = bits(_uncommonBits_T_76, 2, 0)
node _T_1116 = shr(io.in.a.bits.source, 3)
node _T_1117 = eq(_T_1116, UInt<4>(0h8))
node _T_1118 = leq(UInt<1>(0h0), uncommonBits_76)
node _T_1119 = and(_T_1117, _T_1118)
node _T_1120 = leq(uncommonBits_76, UInt<3>(0h4))
node _T_1121 = and(_T_1119, _T_1120)
node _T_1122 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_1123 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_1124 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_1125 = or(_T_1079, _T_1085)
node _T_1126 = or(_T_1125, _T_1091)
node _T_1127 = or(_T_1126, _T_1097)
node _T_1128 = or(_T_1127, _T_1103)
node _T_1129 = or(_T_1128, _T_1109)
node _T_1130 = or(_T_1129, _T_1115)
node _T_1131 = or(_T_1130, _T_1121)
node _T_1132 = or(_T_1131, _T_1122)
node _T_1133 = or(_T_1132, _T_1123)
node _T_1134 = or(_T_1133, _T_1124)
node _T_1135 = and(_T_1078, _T_1134)
node _T_1136 = or(UInt<1>(0h0), _T_1135)
node _T_1137 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1138 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1139 = cvt(_T_1138)
node _T_1140 = and(_T_1139, asSInt(UInt<13>(0h1000)))
node _T_1141 = asSInt(_T_1140)
node _T_1142 = eq(_T_1141, asSInt(UInt<1>(0h0)))
node _T_1143 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_1144 = cvt(_T_1143)
node _T_1145 = and(_T_1144, asSInt(UInt<13>(0h1000)))
node _T_1146 = asSInt(_T_1145)
node _T_1147 = eq(_T_1146, asSInt(UInt<1>(0h0)))
node _T_1148 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1149 = cvt(_T_1148)
node _T_1150 = and(_T_1149, asSInt(UInt<13>(0h1000)))
node _T_1151 = asSInt(_T_1150)
node _T_1152 = eq(_T_1151, asSInt(UInt<1>(0h0)))
node _T_1153 = or(_T_1142, _T_1147)
node _T_1154 = or(_T_1153, _T_1152)
node _T_1155 = and(_T_1137, _T_1154)
node _T_1156 = or(UInt<1>(0h0), _T_1155)
node _T_1157 = and(_T_1136, _T_1156)
node _T_1158 = asUInt(reset)
node _T_1159 = eq(_T_1158, UInt<1>(0h0))
when _T_1159 :
node _T_1160 = eq(_T_1157, UInt<1>(0h0))
when _T_1160 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1157, UInt<1>(0h1), "") : assert_46
node _T_1161 = asUInt(reset)
node _T_1162 = eq(_T_1161, UInt<1>(0h0))
when _T_1162 :
node _T_1163 = eq(source_ok, UInt<1>(0h0))
when _T_1163 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1164 = asUInt(reset)
node _T_1165 = eq(_T_1164, UInt<1>(0h0))
when _T_1165 :
node _T_1166 = eq(is_aligned, UInt<1>(0h0))
when _T_1166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1167 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1168 = asUInt(reset)
node _T_1169 = eq(_T_1168, UInt<1>(0h0))
when _T_1169 :
node _T_1170 = eq(_T_1167, UInt<1>(0h0))
when _T_1170 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1167, UInt<1>(0h1), "") : assert_49
node _T_1171 = eq(io.in.a.bits.mask, mask)
node _T_1172 = asUInt(reset)
node _T_1173 = eq(_T_1172, UInt<1>(0h0))
when _T_1173 :
node _T_1174 = eq(_T_1171, UInt<1>(0h0))
when _T_1174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1171, UInt<1>(0h1), "") : assert_50
node _T_1175 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1176 = asUInt(reset)
node _T_1177 = eq(_T_1176, UInt<1>(0h0))
when _T_1177 :
node _T_1178 = eq(_T_1175, UInt<1>(0h0))
when _T_1178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1175, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1179 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1180 = asUInt(reset)
node _T_1181 = eq(_T_1180, UInt<1>(0h0))
when _T_1181 :
node _T_1182 = eq(_T_1179, UInt<1>(0h0))
when _T_1182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1179, UInt<1>(0h1), "") : assert_52
node _source_ok_T_55 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_56 = shr(io.in.d.bits.source, 2)
node _source_ok_T_57 = eq(_source_ok_T_56, UInt<1>(0h0))
node _source_ok_T_58 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58)
node _source_ok_T_60 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_62 = shr(io.in.d.bits.source, 2)
node _source_ok_T_63 = eq(_source_ok_T_62, UInt<1>(0h1))
node _source_ok_T_64 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64)
node _source_ok_T_66 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_68 = shr(io.in.d.bits.source, 2)
node _source_ok_T_69 = eq(_source_ok_T_68, UInt<2>(0h2))
node _source_ok_T_70 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70)
node _source_ok_T_72 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72)
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0)
node _source_ok_T_74 = shr(io.in.d.bits.source, 2)
node _source_ok_T_75 = eq(_source_ok_T_74, UInt<2>(0h3))
node _source_ok_T_76 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_77 = and(_source_ok_T_75, _source_ok_T_76)
node _source_ok_T_78 = leq(source_ok_uncommonBits_10, UInt<2>(0h3))
node _source_ok_T_79 = and(_source_ok_T_77, _source_ok_T_78)
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 2, 0)
node _source_ok_T_80 = shr(io.in.d.bits.source, 3)
node _source_ok_T_81 = eq(_source_ok_T_80, UInt<2>(0h3))
node _source_ok_T_82 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_83 = and(_source_ok_T_81, _source_ok_T_82)
node _source_ok_T_84 = leq(source_ok_uncommonBits_11, UInt<3>(0h7))
node _source_ok_T_85 = and(_source_ok_T_83, _source_ok_T_84)
node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 2, 0)
node _source_ok_T_86 = shr(io.in.d.bits.source, 3)
node _source_ok_T_87 = eq(_source_ok_T_86, UInt<2>(0h2))
node _source_ok_T_88 = leq(UInt<1>(0h0), source_ok_uncommonBits_12)
node _source_ok_T_89 = and(_source_ok_T_87, _source_ok_T_88)
node _source_ok_T_90 = leq(source_ok_uncommonBits_12, UInt<3>(0h7))
node _source_ok_T_91 = and(_source_ok_T_89, _source_ok_T_90)
node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 2, 0)
node _source_ok_T_92 = shr(io.in.d.bits.source, 3)
node _source_ok_T_93 = eq(_source_ok_T_92, UInt<4>(0h8))
node _source_ok_T_94 = leq(UInt<1>(0h0), source_ok_uncommonBits_13)
node _source_ok_T_95 = and(_source_ok_T_93, _source_ok_T_94)
node _source_ok_T_96 = leq(source_ok_uncommonBits_13, UInt<3>(0h4))
node _source_ok_T_97 = and(_source_ok_T_95, _source_ok_T_96)
node _source_ok_T_98 = eq(io.in.d.bits.source, UInt<7>(0h45))
node _source_ok_T_99 = eq(io.in.d.bits.source, UInt<7>(0h48))
node _source_ok_T_100 = eq(io.in.d.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE_1 : UInt<1>[11]
connect _source_ok_WIRE_1[0], _source_ok_T_55
connect _source_ok_WIRE_1[1], _source_ok_T_61
connect _source_ok_WIRE_1[2], _source_ok_T_67
connect _source_ok_WIRE_1[3], _source_ok_T_73
connect _source_ok_WIRE_1[4], _source_ok_T_79
connect _source_ok_WIRE_1[5], _source_ok_T_85
connect _source_ok_WIRE_1[6], _source_ok_T_91
connect _source_ok_WIRE_1[7], _source_ok_T_97
connect _source_ok_WIRE_1[8], _source_ok_T_98
connect _source_ok_WIRE_1[9], _source_ok_T_99
connect _source_ok_WIRE_1[10], _source_ok_T_100
node _source_ok_T_101 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_102 = or(_source_ok_T_101, _source_ok_WIRE_1[2])
node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[3])
node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[4])
node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[5])
node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[6])
node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[7])
node _source_ok_T_108 = or(_source_ok_T_107, _source_ok_WIRE_1[8])
node _source_ok_T_109 = or(_source_ok_T_108, _source_ok_WIRE_1[9])
node source_ok_1 = or(_source_ok_T_109, _source_ok_WIRE_1[10])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1183 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1183 :
node _T_1184 = asUInt(reset)
node _T_1185 = eq(_T_1184, UInt<1>(0h0))
when _T_1185 :
node _T_1186 = eq(source_ok_1, UInt<1>(0h0))
when _T_1186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1187 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1188 = asUInt(reset)
node _T_1189 = eq(_T_1188, UInt<1>(0h0))
when _T_1189 :
node _T_1190 = eq(_T_1187, UInt<1>(0h0))
when _T_1190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1187, UInt<1>(0h1), "") : assert_54
node _T_1191 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1192 = asUInt(reset)
node _T_1193 = eq(_T_1192, UInt<1>(0h0))
when _T_1193 :
node _T_1194 = eq(_T_1191, UInt<1>(0h0))
when _T_1194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1191, UInt<1>(0h1), "") : assert_55
node _T_1195 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1196 = asUInt(reset)
node _T_1197 = eq(_T_1196, UInt<1>(0h0))
when _T_1197 :
node _T_1198 = eq(_T_1195, UInt<1>(0h0))
when _T_1198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1195, UInt<1>(0h1), "") : assert_56
node _T_1199 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1200 = asUInt(reset)
node _T_1201 = eq(_T_1200, UInt<1>(0h0))
when _T_1201 :
node _T_1202 = eq(_T_1199, UInt<1>(0h0))
when _T_1202 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1199, UInt<1>(0h1), "") : assert_57
node _T_1203 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1203 :
node _T_1204 = asUInt(reset)
node _T_1205 = eq(_T_1204, UInt<1>(0h0))
when _T_1205 :
node _T_1206 = eq(source_ok_1, UInt<1>(0h0))
when _T_1206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1207 = asUInt(reset)
node _T_1208 = eq(_T_1207, UInt<1>(0h0))
when _T_1208 :
node _T_1209 = eq(sink_ok, UInt<1>(0h0))
when _T_1209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1210 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1211 = asUInt(reset)
node _T_1212 = eq(_T_1211, UInt<1>(0h0))
when _T_1212 :
node _T_1213 = eq(_T_1210, UInt<1>(0h0))
when _T_1213 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1210, UInt<1>(0h1), "") : assert_60
node _T_1214 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1215 = asUInt(reset)
node _T_1216 = eq(_T_1215, UInt<1>(0h0))
when _T_1216 :
node _T_1217 = eq(_T_1214, UInt<1>(0h0))
when _T_1217 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1214, UInt<1>(0h1), "") : assert_61
node _T_1218 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1219 = asUInt(reset)
node _T_1220 = eq(_T_1219, UInt<1>(0h0))
when _T_1220 :
node _T_1221 = eq(_T_1218, UInt<1>(0h0))
when _T_1221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1218, UInt<1>(0h1), "") : assert_62
node _T_1222 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1223 = asUInt(reset)
node _T_1224 = eq(_T_1223, UInt<1>(0h0))
when _T_1224 :
node _T_1225 = eq(_T_1222, UInt<1>(0h0))
when _T_1225 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1222, UInt<1>(0h1), "") : assert_63
node _T_1226 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1227 = or(UInt<1>(0h0), _T_1226)
node _T_1228 = asUInt(reset)
node _T_1229 = eq(_T_1228, UInt<1>(0h0))
when _T_1229 :
node _T_1230 = eq(_T_1227, UInt<1>(0h0))
when _T_1230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1227, UInt<1>(0h1), "") : assert_64
node _T_1231 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1231 :
node _T_1232 = asUInt(reset)
node _T_1233 = eq(_T_1232, UInt<1>(0h0))
when _T_1233 :
node _T_1234 = eq(source_ok_1, UInt<1>(0h0))
when _T_1234 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1235 = asUInt(reset)
node _T_1236 = eq(_T_1235, UInt<1>(0h0))
when _T_1236 :
node _T_1237 = eq(sink_ok, UInt<1>(0h0))
when _T_1237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1238 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1239 = asUInt(reset)
node _T_1240 = eq(_T_1239, UInt<1>(0h0))
when _T_1240 :
node _T_1241 = eq(_T_1238, UInt<1>(0h0))
when _T_1241 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1238, UInt<1>(0h1), "") : assert_67
node _T_1242 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1243 = asUInt(reset)
node _T_1244 = eq(_T_1243, UInt<1>(0h0))
when _T_1244 :
node _T_1245 = eq(_T_1242, UInt<1>(0h0))
when _T_1245 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1242, UInt<1>(0h1), "") : assert_68
node _T_1246 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1247 = asUInt(reset)
node _T_1248 = eq(_T_1247, UInt<1>(0h0))
when _T_1248 :
node _T_1249 = eq(_T_1246, UInt<1>(0h0))
when _T_1249 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1246, UInt<1>(0h1), "") : assert_69
node _T_1250 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1251 = or(_T_1250, io.in.d.bits.corrupt)
node _T_1252 = asUInt(reset)
node _T_1253 = eq(_T_1252, UInt<1>(0h0))
when _T_1253 :
node _T_1254 = eq(_T_1251, UInt<1>(0h0))
when _T_1254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1251, UInt<1>(0h1), "") : assert_70
node _T_1255 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1256 = or(UInt<1>(0h0), _T_1255)
node _T_1257 = asUInt(reset)
node _T_1258 = eq(_T_1257, UInt<1>(0h0))
when _T_1258 :
node _T_1259 = eq(_T_1256, UInt<1>(0h0))
when _T_1259 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1256, UInt<1>(0h1), "") : assert_71
node _T_1260 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1260 :
node _T_1261 = asUInt(reset)
node _T_1262 = eq(_T_1261, UInt<1>(0h0))
when _T_1262 :
node _T_1263 = eq(source_ok_1, UInt<1>(0h0))
when _T_1263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1264 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1265 = asUInt(reset)
node _T_1266 = eq(_T_1265, UInt<1>(0h0))
when _T_1266 :
node _T_1267 = eq(_T_1264, UInt<1>(0h0))
when _T_1267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1264, UInt<1>(0h1), "") : assert_73
node _T_1268 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1269 = asUInt(reset)
node _T_1270 = eq(_T_1269, UInt<1>(0h0))
when _T_1270 :
node _T_1271 = eq(_T_1268, UInt<1>(0h0))
when _T_1271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1268, UInt<1>(0h1), "") : assert_74
node _T_1272 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1273 = or(UInt<1>(0h0), _T_1272)
node _T_1274 = asUInt(reset)
node _T_1275 = eq(_T_1274, UInt<1>(0h0))
when _T_1275 :
node _T_1276 = eq(_T_1273, UInt<1>(0h0))
when _T_1276 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1273, UInt<1>(0h1), "") : assert_75
node _T_1277 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1277 :
node _T_1278 = asUInt(reset)
node _T_1279 = eq(_T_1278, UInt<1>(0h0))
when _T_1279 :
node _T_1280 = eq(source_ok_1, UInt<1>(0h0))
when _T_1280 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1281 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1282 = asUInt(reset)
node _T_1283 = eq(_T_1282, UInt<1>(0h0))
when _T_1283 :
node _T_1284 = eq(_T_1281, UInt<1>(0h0))
when _T_1284 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1281, UInt<1>(0h1), "") : assert_77
node _T_1285 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1286 = or(_T_1285, io.in.d.bits.corrupt)
node _T_1287 = asUInt(reset)
node _T_1288 = eq(_T_1287, UInt<1>(0h0))
when _T_1288 :
node _T_1289 = eq(_T_1286, UInt<1>(0h0))
when _T_1289 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1286, UInt<1>(0h1), "") : assert_78
node _T_1290 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1291 = or(UInt<1>(0h0), _T_1290)
node _T_1292 = asUInt(reset)
node _T_1293 = eq(_T_1292, UInt<1>(0h0))
when _T_1293 :
node _T_1294 = eq(_T_1291, UInt<1>(0h0))
when _T_1294 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1291, UInt<1>(0h1), "") : assert_79
node _T_1295 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1295 :
node _T_1296 = asUInt(reset)
node _T_1297 = eq(_T_1296, UInt<1>(0h0))
when _T_1297 :
node _T_1298 = eq(source_ok_1, UInt<1>(0h0))
when _T_1298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1299 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1300 = asUInt(reset)
node _T_1301 = eq(_T_1300, UInt<1>(0h0))
when _T_1301 :
node _T_1302 = eq(_T_1299, UInt<1>(0h0))
when _T_1302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1299, UInt<1>(0h1), "") : assert_81
node _T_1303 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1304 = asUInt(reset)
node _T_1305 = eq(_T_1304, UInt<1>(0h0))
when _T_1305 :
node _T_1306 = eq(_T_1303, UInt<1>(0h0))
when _T_1306 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1303, UInt<1>(0h1), "") : assert_82
node _T_1307 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1308 = or(UInt<1>(0h0), _T_1307)
node _T_1309 = asUInt(reset)
node _T_1310 = eq(_T_1309, UInt<1>(0h0))
when _T_1310 :
node _T_1311 = eq(_T_1308, UInt<1>(0h0))
when _T_1311 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1308, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<8>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1312 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1313 = asUInt(reset)
node _T_1314 = eq(_T_1313, UInt<1>(0h0))
when _T_1314 :
node _T_1315 = eq(_T_1312, UInt<1>(0h0))
when _T_1315 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1312, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<8>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1316 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1317 = asUInt(reset)
node _T_1318 = eq(_T_1317, UInt<1>(0h0))
when _T_1318 :
node _T_1319 = eq(_T_1316, UInt<1>(0h0))
when _T_1319 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1316, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1320 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1321 = asUInt(reset)
node _T_1322 = eq(_T_1321, UInt<1>(0h0))
when _T_1322 :
node _T_1323 = eq(_T_1320, UInt<1>(0h0))
when _T_1323 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1320, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1324 = eq(a_first, UInt<1>(0h0))
node _T_1325 = and(io.in.a.valid, _T_1324)
when _T_1325 :
node _T_1326 = eq(io.in.a.bits.opcode, opcode)
node _T_1327 = asUInt(reset)
node _T_1328 = eq(_T_1327, UInt<1>(0h0))
when _T_1328 :
node _T_1329 = eq(_T_1326, UInt<1>(0h0))
when _T_1329 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1326, UInt<1>(0h1), "") : assert_87
node _T_1330 = eq(io.in.a.bits.param, param)
node _T_1331 = asUInt(reset)
node _T_1332 = eq(_T_1331, UInt<1>(0h0))
when _T_1332 :
node _T_1333 = eq(_T_1330, UInt<1>(0h0))
when _T_1333 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1330, UInt<1>(0h1), "") : assert_88
node _T_1334 = eq(io.in.a.bits.size, size)
node _T_1335 = asUInt(reset)
node _T_1336 = eq(_T_1335, UInt<1>(0h0))
when _T_1336 :
node _T_1337 = eq(_T_1334, UInt<1>(0h0))
when _T_1337 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1334, UInt<1>(0h1), "") : assert_89
node _T_1338 = eq(io.in.a.bits.source, source)
node _T_1339 = asUInt(reset)
node _T_1340 = eq(_T_1339, UInt<1>(0h0))
when _T_1340 :
node _T_1341 = eq(_T_1338, UInt<1>(0h0))
when _T_1341 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1338, UInt<1>(0h1), "") : assert_90
node _T_1342 = eq(io.in.a.bits.address, address)
node _T_1343 = asUInt(reset)
node _T_1344 = eq(_T_1343, UInt<1>(0h0))
when _T_1344 :
node _T_1345 = eq(_T_1342, UInt<1>(0h0))
when _T_1345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1342, UInt<1>(0h1), "") : assert_91
node _T_1346 = and(io.in.a.ready, io.in.a.valid)
node _T_1347 = and(_T_1346, a_first)
when _T_1347 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1348 = eq(d_first, UInt<1>(0h0))
node _T_1349 = and(io.in.d.valid, _T_1348)
when _T_1349 :
node _T_1350 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1351 = asUInt(reset)
node _T_1352 = eq(_T_1351, UInt<1>(0h0))
when _T_1352 :
node _T_1353 = eq(_T_1350, UInt<1>(0h0))
when _T_1353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1350, UInt<1>(0h1), "") : assert_92
node _T_1354 = eq(io.in.d.bits.param, param_1)
node _T_1355 = asUInt(reset)
node _T_1356 = eq(_T_1355, UInt<1>(0h0))
when _T_1356 :
node _T_1357 = eq(_T_1354, UInt<1>(0h0))
when _T_1357 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1354, UInt<1>(0h1), "") : assert_93
node _T_1358 = eq(io.in.d.bits.size, size_1)
node _T_1359 = asUInt(reset)
node _T_1360 = eq(_T_1359, UInt<1>(0h0))
when _T_1360 :
node _T_1361 = eq(_T_1358, UInt<1>(0h0))
when _T_1361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1358, UInt<1>(0h1), "") : assert_94
node _T_1362 = eq(io.in.d.bits.source, source_1)
node _T_1363 = asUInt(reset)
node _T_1364 = eq(_T_1363, UInt<1>(0h0))
when _T_1364 :
node _T_1365 = eq(_T_1362, UInt<1>(0h0))
when _T_1365 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1362, UInt<1>(0h1), "") : assert_95
node _T_1366 = eq(io.in.d.bits.sink, sink)
node _T_1367 = asUInt(reset)
node _T_1368 = eq(_T_1367, UInt<1>(0h0))
when _T_1368 :
node _T_1369 = eq(_T_1366, UInt<1>(0h0))
when _T_1369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1366, UInt<1>(0h1), "") : assert_96
node _T_1370 = eq(io.in.d.bits.denied, denied)
node _T_1371 = asUInt(reset)
node _T_1372 = eq(_T_1371, UInt<1>(0h0))
when _T_1372 :
node _T_1373 = eq(_T_1370, UInt<1>(0h0))
when _T_1373 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1370, UInt<1>(0h1), "") : assert_97
node _T_1374 = and(io.in.d.ready, io.in.d.valid)
node _T_1375 = and(_T_1374, d_first)
when _T_1375 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<129>
connect a_set, UInt<129>(0h0)
wire a_set_wo_ready : UInt<129>
connect a_set_wo_ready, UInt<129>(0h0)
wire a_opcodes_set : UInt<516>
connect a_opcodes_set, UInt<516>(0h0)
wire a_sizes_set : UInt<516>
connect a_sizes_set, UInt<516>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1376 = and(io.in.a.valid, a_first_1)
node _T_1377 = and(_T_1376, UInt<1>(0h1))
when _T_1377 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1378 = and(io.in.a.ready, io.in.a.valid)
node _T_1379 = and(_T_1378, a_first_1)
node _T_1380 = and(_T_1379, UInt<1>(0h1))
when _T_1380 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1381 = dshr(inflight, io.in.a.bits.source)
node _T_1382 = bits(_T_1381, 0, 0)
node _T_1383 = eq(_T_1382, UInt<1>(0h0))
node _T_1384 = asUInt(reset)
node _T_1385 = eq(_T_1384, UInt<1>(0h0))
when _T_1385 :
node _T_1386 = eq(_T_1383, UInt<1>(0h0))
when _T_1386 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1383, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<129>
connect d_clr, UInt<129>(0h0)
wire d_clr_wo_ready : UInt<129>
connect d_clr_wo_ready, UInt<129>(0h0)
wire d_opcodes_clr : UInt<516>
connect d_opcodes_clr, UInt<516>(0h0)
wire d_sizes_clr : UInt<516>
connect d_sizes_clr, UInt<516>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1387 = and(io.in.d.valid, d_first_1)
node _T_1388 = and(_T_1387, UInt<1>(0h1))
node _T_1389 = eq(d_release_ack, UInt<1>(0h0))
node _T_1390 = and(_T_1388, _T_1389)
when _T_1390 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1391 = and(io.in.d.ready, io.in.d.valid)
node _T_1392 = and(_T_1391, d_first_1)
node _T_1393 = and(_T_1392, UInt<1>(0h1))
node _T_1394 = eq(d_release_ack, UInt<1>(0h0))
node _T_1395 = and(_T_1393, _T_1394)
when _T_1395 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1396 = and(io.in.d.valid, d_first_1)
node _T_1397 = and(_T_1396, UInt<1>(0h1))
node _T_1398 = eq(d_release_ack, UInt<1>(0h0))
node _T_1399 = and(_T_1397, _T_1398)
when _T_1399 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1400 = dshr(inflight, io.in.d.bits.source)
node _T_1401 = bits(_T_1400, 0, 0)
node _T_1402 = or(_T_1401, same_cycle_resp)
node _T_1403 = asUInt(reset)
node _T_1404 = eq(_T_1403, UInt<1>(0h0))
when _T_1404 :
node _T_1405 = eq(_T_1402, UInt<1>(0h0))
when _T_1405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1402, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1406 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1407 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1408 = or(_T_1406, _T_1407)
node _T_1409 = asUInt(reset)
node _T_1410 = eq(_T_1409, UInt<1>(0h0))
when _T_1410 :
node _T_1411 = eq(_T_1408, UInt<1>(0h0))
when _T_1411 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1408, UInt<1>(0h1), "") : assert_100
node _T_1412 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1413 = asUInt(reset)
node _T_1414 = eq(_T_1413, UInt<1>(0h0))
when _T_1414 :
node _T_1415 = eq(_T_1412, UInt<1>(0h0))
when _T_1415 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1412, UInt<1>(0h1), "") : assert_101
else :
node _T_1416 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1417 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1418 = or(_T_1416, _T_1417)
node _T_1419 = asUInt(reset)
node _T_1420 = eq(_T_1419, UInt<1>(0h0))
when _T_1420 :
node _T_1421 = eq(_T_1418, UInt<1>(0h0))
when _T_1421 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1418, UInt<1>(0h1), "") : assert_102
node _T_1422 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1423 = asUInt(reset)
node _T_1424 = eq(_T_1423, UInt<1>(0h0))
when _T_1424 :
node _T_1425 = eq(_T_1422, UInt<1>(0h0))
when _T_1425 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1422, UInt<1>(0h1), "") : assert_103
node _T_1426 = and(io.in.d.valid, d_first_1)
node _T_1427 = and(_T_1426, a_first_1)
node _T_1428 = and(_T_1427, io.in.a.valid)
node _T_1429 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1430 = and(_T_1428, _T_1429)
node _T_1431 = eq(d_release_ack, UInt<1>(0h0))
node _T_1432 = and(_T_1430, _T_1431)
when _T_1432 :
node _T_1433 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1434 = or(_T_1433, io.in.a.ready)
node _T_1435 = asUInt(reset)
node _T_1436 = eq(_T_1435, UInt<1>(0h0))
when _T_1436 :
node _T_1437 = eq(_T_1434, UInt<1>(0h0))
when _T_1437 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1434, UInt<1>(0h1), "") : assert_104
node _T_1438 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1439 = orr(a_set_wo_ready)
node _T_1440 = eq(_T_1439, UInt<1>(0h0))
node _T_1441 = or(_T_1438, _T_1440)
node _T_1442 = asUInt(reset)
node _T_1443 = eq(_T_1442, UInt<1>(0h0))
when _T_1443 :
node _T_1444 = eq(_T_1441, UInt<1>(0h0))
when _T_1444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1441, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_14
node _T_1445 = orr(inflight)
node _T_1446 = eq(_T_1445, UInt<1>(0h0))
node _T_1447 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1448 = or(_T_1446, _T_1447)
node _T_1449 = lt(watchdog, plusarg_reader.out)
node _T_1450 = or(_T_1448, _T_1449)
node _T_1451 = asUInt(reset)
node _T_1452 = eq(_T_1451, UInt<1>(0h0))
when _T_1452 :
node _T_1453 = eq(_T_1450, UInt<1>(0h0))
when _T_1453 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1450, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1454 = and(io.in.a.ready, io.in.a.valid)
node _T_1455 = and(io.in.d.ready, io.in.d.valid)
node _T_1456 = or(_T_1454, _T_1455)
when _T_1456 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<8>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<129>
connect c_set, UInt<129>(0h0)
wire c_set_wo_ready : UInt<129>
connect c_set_wo_ready, UInt<129>(0h0)
wire c_opcodes_set : UInt<516>
connect c_opcodes_set, UInt<516>(0h0)
wire c_sizes_set : UInt<516>
connect c_sizes_set, UInt<516>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<8>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1457 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<8>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1458 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1459 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1460 = and(_T_1458, _T_1459)
node _T_1461 = and(_T_1457, _T_1460)
when _T_1461 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<8>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1462 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1463 = and(_T_1462, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<8>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1464 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1465 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1466 = and(_T_1464, _T_1465)
node _T_1467 = and(_T_1463, _T_1466)
when _T_1467 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<8>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1468 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1469 = bits(_T_1468, 0, 0)
node _T_1470 = eq(_T_1469, UInt<1>(0h0))
node _T_1471 = asUInt(reset)
node _T_1472 = eq(_T_1471, UInt<1>(0h0))
when _T_1472 :
node _T_1473 = eq(_T_1470, UInt<1>(0h0))
when _T_1473 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1470, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<129>
connect d_clr_1, UInt<129>(0h0)
wire d_clr_wo_ready_1 : UInt<129>
connect d_clr_wo_ready_1, UInt<129>(0h0)
wire d_opcodes_clr_1 : UInt<516>
connect d_opcodes_clr_1, UInt<516>(0h0)
wire d_sizes_clr_1 : UInt<516>
connect d_sizes_clr_1, UInt<516>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1474 = and(io.in.d.valid, d_first_2)
node _T_1475 = and(_T_1474, UInt<1>(0h1))
node _T_1476 = and(_T_1475, d_release_ack_1)
when _T_1476 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1477 = and(io.in.d.ready, io.in.d.valid)
node _T_1478 = and(_T_1477, d_first_2)
node _T_1479 = and(_T_1478, UInt<1>(0h1))
node _T_1480 = and(_T_1479, d_release_ack_1)
when _T_1480 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1481 = and(io.in.d.valid, d_first_2)
node _T_1482 = and(_T_1481, UInt<1>(0h1))
node _T_1483 = and(_T_1482, d_release_ack_1)
when _T_1483 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1484 = dshr(inflight_1, io.in.d.bits.source)
node _T_1485 = bits(_T_1484, 0, 0)
node _T_1486 = or(_T_1485, same_cycle_resp_1)
node _T_1487 = asUInt(reset)
node _T_1488 = eq(_T_1487, UInt<1>(0h0))
when _T_1488 :
node _T_1489 = eq(_T_1486, UInt<1>(0h0))
when _T_1489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1486, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<8>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1490 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1491 = asUInt(reset)
node _T_1492 = eq(_T_1491, UInt<1>(0h0))
when _T_1492 :
node _T_1493 = eq(_T_1490, UInt<1>(0h0))
when _T_1493 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1490, UInt<1>(0h1), "") : assert_109
else :
node _T_1494 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1495 = asUInt(reset)
node _T_1496 = eq(_T_1495, UInt<1>(0h0))
when _T_1496 :
node _T_1497 = eq(_T_1494, UInt<1>(0h0))
when _T_1497 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1494, UInt<1>(0h1), "") : assert_110
node _T_1498 = and(io.in.d.valid, d_first_2)
node _T_1499 = and(_T_1498, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<8>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1500 = and(_T_1499, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<8>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1501 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1502 = and(_T_1500, _T_1501)
node _T_1503 = and(_T_1502, d_release_ack_1)
node _T_1504 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1505 = and(_T_1503, _T_1504)
when _T_1505 :
node _T_1506 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<29>(0h0)
connect _WIRE_26.bits.source, UInt<8>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1507 = or(_T_1506, _WIRE_27.ready)
node _T_1508 = asUInt(reset)
node _T_1509 = eq(_T_1508, UInt<1>(0h0))
when _T_1509 :
node _T_1510 = eq(_T_1507, UInt<1>(0h0))
when _T_1510 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1507, UInt<1>(0h1), "") : assert_111
node _T_1511 = orr(c_set_wo_ready)
when _T_1511 :
node _T_1512 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1513 = asUInt(reset)
node _T_1514 = eq(_T_1513, UInt<1>(0h0))
when _T_1514 :
node _T_1515 = eq(_T_1512, UInt<1>(0h0))
when _T_1515 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1512, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_15
node _T_1516 = orr(inflight_1)
node _T_1517 = eq(_T_1516, UInt<1>(0h0))
node _T_1518 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1519 = or(_T_1517, _T_1518)
node _T_1520 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1521 = or(_T_1519, _T_1520)
node _T_1522 = asUInt(reset)
node _T_1523 = eq(_T_1522, UInt<1>(0h0))
when _T_1523 :
node _T_1524 = eq(_T_1521, UInt<1>(0h0))
when _T_1524 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:44)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1521, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<8>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1525 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1526 = and(io.in.d.ready, io.in.d.valid)
node _T_1527 = or(_T_1525, _T_1526)
when _T_1527 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_7( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_70 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_72 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_76 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_78 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_82 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_84 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_88 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_90 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_94 = 1'h1; // @[Parameters.scala:56:32]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54]
wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52]
wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79]
wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35]
wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35]
wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34]
wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34]
wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34]
wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 6'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 6'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 6'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 6'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_31 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_37 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_38 = _source_ok_T_37 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_41 = source_ok_uncommonBits_6 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_42 = _source_ok_T_40 & _source_ok_T_41; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31]
wire _source_ok_T_43 = io_in_a_bits_source_0 == 8'h45; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_43; // @[Parameters.scala:1138:31]
wire _source_ok_T_44 = io_in_a_bits_source_0 == 8'h48; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_44; // @[Parameters.scala:1138:31]
wire _source_ok_T_45 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_45; // @[Parameters.scala:1138:31]
wire _source_ok_T_46 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_54 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_20 = _uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_26 = _uncommonBits_T_26[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_27 = _uncommonBits_T_27[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_32 = _uncommonBits_T_32[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_33 = _uncommonBits_T_33[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_55 = _uncommonBits_T_55[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_60 = _uncommonBits_T_60[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_61 = _uncommonBits_T_61[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_62 = _uncommonBits_T_62[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_67 = _uncommonBits_T_67[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_68 = _uncommonBits_T_68[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_75 = _uncommonBits_T_75[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_76 = _uncommonBits_T_76[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_55 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_55; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_56 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_62 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_68 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_74 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_57 = _source_ok_T_56 == 6'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_61; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_63 = _source_ok_T_62 == 6'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_67; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_69 = _source_ok_T_68 == 6'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_71 = _source_ok_T_69; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_73 = _source_ok_T_71; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_73; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_75 = _source_ok_T_74 == 6'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_77 = _source_ok_T_75; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_79 = _source_ok_T_77; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_79; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_80 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_86 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_92 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_81 = _source_ok_T_80 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_83 = _source_ok_T_81; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_85 = _source_ok_T_83; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_85; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_87 = _source_ok_T_86 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_89 = _source_ok_T_87; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_91 = _source_ok_T_89; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_91; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_93 = _source_ok_T_92 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_95 = _source_ok_T_93; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_96 = source_ok_uncommonBits_13 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_97 = _source_ok_T_95 & _source_ok_T_96; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_7 = _source_ok_T_97; // @[Parameters.scala:1138:31]
wire _source_ok_T_98 = io_in_d_bits_source_0 == 8'h45; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_98; // @[Parameters.scala:1138:31]
wire _source_ok_T_99 = io_in_d_bits_source_0 == 8'h48; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_99; // @[Parameters.scala:1138:31]
wire _source_ok_T_100 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_100; // @[Parameters.scala:1138:31]
wire _source_ok_T_101 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_102 = _source_ok_T_101 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_104 = _source_ok_T_103 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_105 = _source_ok_T_104 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_106 = _source_ok_T_105 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_107 = _source_ok_T_106 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_108 = _source_ok_T_107 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_109 = _source_ok_T_108 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_109 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1454 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1454; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1454; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1527 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1527; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1527; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1527; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [128:0] inflight; // @[Monitor.scala:614:27]
reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [515:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [128:0] a_set; // @[Monitor.scala:626:34]
wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [515:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [255:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1380 = _T_1454 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1380 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1380 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1380 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1380 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1380 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [128:0] d_clr; // @[Monitor.scala:664:34]
wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1426 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1426 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1395 = _T_1527 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1395 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1395 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1395 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [515:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [128:0] inflight_1; // @[Monitor.scala:726:35]
wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [128:0] d_clr_1; // @[Monitor.scala:774:34]
wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1498 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1498 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1480 = _T_1527 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1480 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1480 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1480 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113]
wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue_2 :
input clock : Clock
input reset : Reset
output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<4>}
cmem ram : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>} [15]
wire _valids_WIRE : UInt<1>[15]
connect _valids_WIRE[0], UInt<1>(0h0)
connect _valids_WIRE[1], UInt<1>(0h0)
connect _valids_WIRE[2], UInt<1>(0h0)
connect _valids_WIRE[3], UInt<1>(0h0)
connect _valids_WIRE[4], UInt<1>(0h0)
connect _valids_WIRE[5], UInt<1>(0h0)
connect _valids_WIRE[6], UInt<1>(0h0)
connect _valids_WIRE[7], UInt<1>(0h0)
connect _valids_WIRE[8], UInt<1>(0h0)
connect _valids_WIRE[9], UInt<1>(0h0)
connect _valids_WIRE[10], UInt<1>(0h0)
connect _valids_WIRE[11], UInt<1>(0h0)
connect _valids_WIRE[12], UInt<1>(0h0)
connect _valids_WIRE[13], UInt<1>(0h0)
connect _valids_WIRE[14], UInt<1>(0h0)
regreset valids : UInt<1>[15], clock, reset, _valids_WIRE
reg uops : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[15], clock
regreset enq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0)
regreset deq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0)
regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0)
node ptr_match = eq(enq_ptr_value, deq_ptr_value)
node _io_empty_T = eq(maybe_full, UInt<1>(0h0))
node _io_empty_T_1 = and(ptr_match, _io_empty_T)
connect io.empty, _io_empty_T_1
node full = and(ptr_match, maybe_full)
node _do_enq_T = and(io.enq.ready, io.enq.valid)
node _do_enq_T_1 = and(io.brupdate.b1.mispredict_mask, io.enq.bits.uop.br_mask)
node _do_enq_T_2 = neq(_do_enq_T_1, UInt<1>(0h0))
node _do_enq_T_3 = or(_do_enq_T_2, UInt<1>(0h0))
node _do_enq_T_4 = eq(_do_enq_T_3, UInt<1>(0h0))
node _do_enq_T_5 = and(_do_enq_T, _do_enq_T_4)
node _do_enq_T_6 = and(io.flush, io.enq.bits.uop.uses_ldq)
node _do_enq_T_7 = eq(_do_enq_T_6, UInt<1>(0h0))
node _do_enq_T_8 = and(_do_enq_T_5, _do_enq_T_7)
wire do_enq : UInt<1>
connect do_enq, _do_enq_T_8
node _do_deq_T = eq(valids[deq_ptr_value], UInt<1>(0h0))
node _do_deq_T_1 = or(io.deq.ready, _do_deq_T)
node _do_deq_T_2 = eq(io.empty, UInt<1>(0h0))
node _do_deq_T_3 = and(_do_deq_T_1, _do_deq_T_2)
wire do_deq : UInt<1>
connect do_deq, _do_deq_T_3
node _valids_0_T = and(io.brupdate.b1.mispredict_mask, uops[0].br_mask)
node _valids_0_T_1 = neq(_valids_0_T, UInt<1>(0h0))
node _valids_0_T_2 = or(_valids_0_T_1, UInt<1>(0h0))
node _valids_0_T_3 = eq(_valids_0_T_2, UInt<1>(0h0))
node _valids_0_T_4 = and(valids[0], _valids_0_T_3)
node _valids_0_T_5 = and(io.flush, uops[0].uses_ldq)
node _valids_0_T_6 = eq(_valids_0_T_5, UInt<1>(0h0))
node _valids_0_T_7 = and(_valids_0_T_4, _valids_0_T_6)
connect valids[0], _valids_0_T_7
when valids[0] :
node _uops_0_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_0_br_mask_T_1 = and(uops[0].br_mask, _uops_0_br_mask_T)
connect uops[0].br_mask, _uops_0_br_mask_T_1
node _valids_1_T = and(io.brupdate.b1.mispredict_mask, uops[1].br_mask)
node _valids_1_T_1 = neq(_valids_1_T, UInt<1>(0h0))
node _valids_1_T_2 = or(_valids_1_T_1, UInt<1>(0h0))
node _valids_1_T_3 = eq(_valids_1_T_2, UInt<1>(0h0))
node _valids_1_T_4 = and(valids[1], _valids_1_T_3)
node _valids_1_T_5 = and(io.flush, uops[1].uses_ldq)
node _valids_1_T_6 = eq(_valids_1_T_5, UInt<1>(0h0))
node _valids_1_T_7 = and(_valids_1_T_4, _valids_1_T_6)
connect valids[1], _valids_1_T_7
when valids[1] :
node _uops_1_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_1_br_mask_T_1 = and(uops[1].br_mask, _uops_1_br_mask_T)
connect uops[1].br_mask, _uops_1_br_mask_T_1
node _valids_2_T = and(io.brupdate.b1.mispredict_mask, uops[2].br_mask)
node _valids_2_T_1 = neq(_valids_2_T, UInt<1>(0h0))
node _valids_2_T_2 = or(_valids_2_T_1, UInt<1>(0h0))
node _valids_2_T_3 = eq(_valids_2_T_2, UInt<1>(0h0))
node _valids_2_T_4 = and(valids[2], _valids_2_T_3)
node _valids_2_T_5 = and(io.flush, uops[2].uses_ldq)
node _valids_2_T_6 = eq(_valids_2_T_5, UInt<1>(0h0))
node _valids_2_T_7 = and(_valids_2_T_4, _valids_2_T_6)
connect valids[2], _valids_2_T_7
when valids[2] :
node _uops_2_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_2_br_mask_T_1 = and(uops[2].br_mask, _uops_2_br_mask_T)
connect uops[2].br_mask, _uops_2_br_mask_T_1
node _valids_3_T = and(io.brupdate.b1.mispredict_mask, uops[3].br_mask)
node _valids_3_T_1 = neq(_valids_3_T, UInt<1>(0h0))
node _valids_3_T_2 = or(_valids_3_T_1, UInt<1>(0h0))
node _valids_3_T_3 = eq(_valids_3_T_2, UInt<1>(0h0))
node _valids_3_T_4 = and(valids[3], _valids_3_T_3)
node _valids_3_T_5 = and(io.flush, uops[3].uses_ldq)
node _valids_3_T_6 = eq(_valids_3_T_5, UInt<1>(0h0))
node _valids_3_T_7 = and(_valids_3_T_4, _valids_3_T_6)
connect valids[3], _valids_3_T_7
when valids[3] :
node _uops_3_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_3_br_mask_T_1 = and(uops[3].br_mask, _uops_3_br_mask_T)
connect uops[3].br_mask, _uops_3_br_mask_T_1
node _valids_4_T = and(io.brupdate.b1.mispredict_mask, uops[4].br_mask)
node _valids_4_T_1 = neq(_valids_4_T, UInt<1>(0h0))
node _valids_4_T_2 = or(_valids_4_T_1, UInt<1>(0h0))
node _valids_4_T_3 = eq(_valids_4_T_2, UInt<1>(0h0))
node _valids_4_T_4 = and(valids[4], _valids_4_T_3)
node _valids_4_T_5 = and(io.flush, uops[4].uses_ldq)
node _valids_4_T_6 = eq(_valids_4_T_5, UInt<1>(0h0))
node _valids_4_T_7 = and(_valids_4_T_4, _valids_4_T_6)
connect valids[4], _valids_4_T_7
when valids[4] :
node _uops_4_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_4_br_mask_T_1 = and(uops[4].br_mask, _uops_4_br_mask_T)
connect uops[4].br_mask, _uops_4_br_mask_T_1
node _valids_5_T = and(io.brupdate.b1.mispredict_mask, uops[5].br_mask)
node _valids_5_T_1 = neq(_valids_5_T, UInt<1>(0h0))
node _valids_5_T_2 = or(_valids_5_T_1, UInt<1>(0h0))
node _valids_5_T_3 = eq(_valids_5_T_2, UInt<1>(0h0))
node _valids_5_T_4 = and(valids[5], _valids_5_T_3)
node _valids_5_T_5 = and(io.flush, uops[5].uses_ldq)
node _valids_5_T_6 = eq(_valids_5_T_5, UInt<1>(0h0))
node _valids_5_T_7 = and(_valids_5_T_4, _valids_5_T_6)
connect valids[5], _valids_5_T_7
when valids[5] :
node _uops_5_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_5_br_mask_T_1 = and(uops[5].br_mask, _uops_5_br_mask_T)
connect uops[5].br_mask, _uops_5_br_mask_T_1
node _valids_6_T = and(io.brupdate.b1.mispredict_mask, uops[6].br_mask)
node _valids_6_T_1 = neq(_valids_6_T, UInt<1>(0h0))
node _valids_6_T_2 = or(_valids_6_T_1, UInt<1>(0h0))
node _valids_6_T_3 = eq(_valids_6_T_2, UInt<1>(0h0))
node _valids_6_T_4 = and(valids[6], _valids_6_T_3)
node _valids_6_T_5 = and(io.flush, uops[6].uses_ldq)
node _valids_6_T_6 = eq(_valids_6_T_5, UInt<1>(0h0))
node _valids_6_T_7 = and(_valids_6_T_4, _valids_6_T_6)
connect valids[6], _valids_6_T_7
when valids[6] :
node _uops_6_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_6_br_mask_T_1 = and(uops[6].br_mask, _uops_6_br_mask_T)
connect uops[6].br_mask, _uops_6_br_mask_T_1
node _valids_7_T = and(io.brupdate.b1.mispredict_mask, uops[7].br_mask)
node _valids_7_T_1 = neq(_valids_7_T, UInt<1>(0h0))
node _valids_7_T_2 = or(_valids_7_T_1, UInt<1>(0h0))
node _valids_7_T_3 = eq(_valids_7_T_2, UInt<1>(0h0))
node _valids_7_T_4 = and(valids[7], _valids_7_T_3)
node _valids_7_T_5 = and(io.flush, uops[7].uses_ldq)
node _valids_7_T_6 = eq(_valids_7_T_5, UInt<1>(0h0))
node _valids_7_T_7 = and(_valids_7_T_4, _valids_7_T_6)
connect valids[7], _valids_7_T_7
when valids[7] :
node _uops_7_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_7_br_mask_T_1 = and(uops[7].br_mask, _uops_7_br_mask_T)
connect uops[7].br_mask, _uops_7_br_mask_T_1
node _valids_8_T = and(io.brupdate.b1.mispredict_mask, uops[8].br_mask)
node _valids_8_T_1 = neq(_valids_8_T, UInt<1>(0h0))
node _valids_8_T_2 = or(_valids_8_T_1, UInt<1>(0h0))
node _valids_8_T_3 = eq(_valids_8_T_2, UInt<1>(0h0))
node _valids_8_T_4 = and(valids[8], _valids_8_T_3)
node _valids_8_T_5 = and(io.flush, uops[8].uses_ldq)
node _valids_8_T_6 = eq(_valids_8_T_5, UInt<1>(0h0))
node _valids_8_T_7 = and(_valids_8_T_4, _valids_8_T_6)
connect valids[8], _valids_8_T_7
when valids[8] :
node _uops_8_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_8_br_mask_T_1 = and(uops[8].br_mask, _uops_8_br_mask_T)
connect uops[8].br_mask, _uops_8_br_mask_T_1
node _valids_9_T = and(io.brupdate.b1.mispredict_mask, uops[9].br_mask)
node _valids_9_T_1 = neq(_valids_9_T, UInt<1>(0h0))
node _valids_9_T_2 = or(_valids_9_T_1, UInt<1>(0h0))
node _valids_9_T_3 = eq(_valids_9_T_2, UInt<1>(0h0))
node _valids_9_T_4 = and(valids[9], _valids_9_T_3)
node _valids_9_T_5 = and(io.flush, uops[9].uses_ldq)
node _valids_9_T_6 = eq(_valids_9_T_5, UInt<1>(0h0))
node _valids_9_T_7 = and(_valids_9_T_4, _valids_9_T_6)
connect valids[9], _valids_9_T_7
when valids[9] :
node _uops_9_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_9_br_mask_T_1 = and(uops[9].br_mask, _uops_9_br_mask_T)
connect uops[9].br_mask, _uops_9_br_mask_T_1
node _valids_10_T = and(io.brupdate.b1.mispredict_mask, uops[10].br_mask)
node _valids_10_T_1 = neq(_valids_10_T, UInt<1>(0h0))
node _valids_10_T_2 = or(_valids_10_T_1, UInt<1>(0h0))
node _valids_10_T_3 = eq(_valids_10_T_2, UInt<1>(0h0))
node _valids_10_T_4 = and(valids[10], _valids_10_T_3)
node _valids_10_T_5 = and(io.flush, uops[10].uses_ldq)
node _valids_10_T_6 = eq(_valids_10_T_5, UInt<1>(0h0))
node _valids_10_T_7 = and(_valids_10_T_4, _valids_10_T_6)
connect valids[10], _valids_10_T_7
when valids[10] :
node _uops_10_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_10_br_mask_T_1 = and(uops[10].br_mask, _uops_10_br_mask_T)
connect uops[10].br_mask, _uops_10_br_mask_T_1
node _valids_11_T = and(io.brupdate.b1.mispredict_mask, uops[11].br_mask)
node _valids_11_T_1 = neq(_valids_11_T, UInt<1>(0h0))
node _valids_11_T_2 = or(_valids_11_T_1, UInt<1>(0h0))
node _valids_11_T_3 = eq(_valids_11_T_2, UInt<1>(0h0))
node _valids_11_T_4 = and(valids[11], _valids_11_T_3)
node _valids_11_T_5 = and(io.flush, uops[11].uses_ldq)
node _valids_11_T_6 = eq(_valids_11_T_5, UInt<1>(0h0))
node _valids_11_T_7 = and(_valids_11_T_4, _valids_11_T_6)
connect valids[11], _valids_11_T_7
when valids[11] :
node _uops_11_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_11_br_mask_T_1 = and(uops[11].br_mask, _uops_11_br_mask_T)
connect uops[11].br_mask, _uops_11_br_mask_T_1
node _valids_12_T = and(io.brupdate.b1.mispredict_mask, uops[12].br_mask)
node _valids_12_T_1 = neq(_valids_12_T, UInt<1>(0h0))
node _valids_12_T_2 = or(_valids_12_T_1, UInt<1>(0h0))
node _valids_12_T_3 = eq(_valids_12_T_2, UInt<1>(0h0))
node _valids_12_T_4 = and(valids[12], _valids_12_T_3)
node _valids_12_T_5 = and(io.flush, uops[12].uses_ldq)
node _valids_12_T_6 = eq(_valids_12_T_5, UInt<1>(0h0))
node _valids_12_T_7 = and(_valids_12_T_4, _valids_12_T_6)
connect valids[12], _valids_12_T_7
when valids[12] :
node _uops_12_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_12_br_mask_T_1 = and(uops[12].br_mask, _uops_12_br_mask_T)
connect uops[12].br_mask, _uops_12_br_mask_T_1
node _valids_13_T = and(io.brupdate.b1.mispredict_mask, uops[13].br_mask)
node _valids_13_T_1 = neq(_valids_13_T, UInt<1>(0h0))
node _valids_13_T_2 = or(_valids_13_T_1, UInt<1>(0h0))
node _valids_13_T_3 = eq(_valids_13_T_2, UInt<1>(0h0))
node _valids_13_T_4 = and(valids[13], _valids_13_T_3)
node _valids_13_T_5 = and(io.flush, uops[13].uses_ldq)
node _valids_13_T_6 = eq(_valids_13_T_5, UInt<1>(0h0))
node _valids_13_T_7 = and(_valids_13_T_4, _valids_13_T_6)
connect valids[13], _valids_13_T_7
when valids[13] :
node _uops_13_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_13_br_mask_T_1 = and(uops[13].br_mask, _uops_13_br_mask_T)
connect uops[13].br_mask, _uops_13_br_mask_T_1
node _valids_14_T = and(io.brupdate.b1.mispredict_mask, uops[14].br_mask)
node _valids_14_T_1 = neq(_valids_14_T, UInt<1>(0h0))
node _valids_14_T_2 = or(_valids_14_T_1, UInt<1>(0h0))
node _valids_14_T_3 = eq(_valids_14_T_2, UInt<1>(0h0))
node _valids_14_T_4 = and(valids[14], _valids_14_T_3)
node _valids_14_T_5 = and(io.flush, uops[14].uses_ldq)
node _valids_14_T_6 = eq(_valids_14_T_5, UInt<1>(0h0))
node _valids_14_T_7 = and(_valids_14_T_4, _valids_14_T_6)
connect valids[14], _valids_14_T_7
when valids[14] :
node _uops_14_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_14_br_mask_T_1 = and(uops[14].br_mask, _uops_14_br_mask_T)
connect uops[14].br_mask, _uops_14_br_mask_T_1
when do_enq :
infer mport MPORT = ram[enq_ptr_value], clock
connect MPORT, io.enq.bits
connect valids[enq_ptr_value], UInt<1>(0h1)
connect uops[enq_ptr_value], io.enq.bits.uop
node _uops_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_br_mask_T_1 = and(io.enq.bits.uop.br_mask, _uops_br_mask_T)
connect uops[enq_ptr_value].br_mask, _uops_br_mask_T_1
node wrap = eq(enq_ptr_value, UInt<4>(0he))
node _value_T = add(enq_ptr_value, UInt<1>(0h1))
node _value_T_1 = tail(_value_T, 1)
connect enq_ptr_value, _value_T_1
when wrap :
connect enq_ptr_value, UInt<1>(0h0)
when do_deq :
connect valids[deq_ptr_value], UInt<1>(0h0)
node wrap_1 = eq(deq_ptr_value, UInt<4>(0he))
node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1))
node _value_T_3 = tail(_value_T_2, 1)
connect deq_ptr_value, _value_T_3
when wrap_1 :
connect deq_ptr_value, UInt<1>(0h0)
node _T = neq(do_enq, do_deq)
when _T :
connect maybe_full, do_enq
node _io_enq_ready_T = eq(full, UInt<1>(0h0))
connect io.enq.ready, _io_enq_ready_T
wire out : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}
infer mport out_MPORT = ram[deq_ptr_value], clock
connect out, out_MPORT
connect out.uop, uops[deq_ptr_value]
node _io_deq_valid_T = eq(io.empty, UInt<1>(0h0))
node _io_deq_valid_T_1 = and(_io_deq_valid_T, valids[deq_ptr_value])
connect io.deq.valid, _io_deq_valid_T_1
connect io.deq.bits, out
node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value)
node ptr_diff = tail(_ptr_diff_T, 1)
node _io_count_T = mux(maybe_full, UInt<4>(0hf), UInt<1>(0h0))
node _io_count_T_1 = gt(deq_ptr_value, enq_ptr_value)
node _io_count_T_2 = add(UInt<4>(0hf), ptr_diff)
node _io_count_T_3 = tail(_io_count_T_2, 1)
node _io_count_T_4 = mux(_io_count_T_1, _io_count_T_3, ptr_diff)
node _io_count_T_5 = mux(ptr_match, _io_count_T, _io_count_T_4)
connect io.count, _io_count_T_5 | module BranchKillableQueue_2( // @[util.scala:458:7]
input clock, // @[util.scala:458:7]
input reset, // @[util.scala:458:7]
output io_enq_ready, // @[util.scala:463:14]
input io_enq_valid, // @[util.scala:463:14]
input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14]
input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14]
input io_enq_bits_uop_is_rvc, // @[util.scala:463:14]
input [39:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14]
input [15:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14]
input io_enq_bits_uop_is_sfb, // @[util.scala:463:14]
input io_enq_bits_uop_is_fence, // @[util.scala:463:14]
input io_enq_bits_uop_is_fencei, // @[util.scala:463:14]
input io_enq_bits_uop_is_sfence, // @[util.scala:463:14]
input io_enq_bits_uop_is_amo, // @[util.scala:463:14]
input io_enq_bits_uop_is_eret, // @[util.scala:463:14]
input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14]
input io_enq_bits_uop_is_rocc, // @[util.scala:463:14]
input io_enq_bits_uop_is_mov, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14]
input io_enq_bits_uop_edge_inst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14]
input io_enq_bits_uop_taken, // @[util.scala:463:14]
input io_enq_bits_uop_imm_rename, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14]
input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_pdst, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_prs1, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_prs2, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_prs3, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_ppred, // @[util.scala:463:14]
input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14]
input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14]
input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14]
input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14]
input io_enq_bits_uop_exception, // @[util.scala:463:14]
input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14]
input io_enq_bits_uop_mem_signed, // @[util.scala:463:14]
input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14]
input io_enq_bits_uop_uses_stq, // @[util.scala:463:14]
input io_enq_bits_uop_is_unique, // @[util.scala:463:14]
input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14]
input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14]
input io_enq_bits_uop_frs3_en, // @[util.scala:463:14]
input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14]
input io_enq_bits_uop_fp_val, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14]
input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14]
input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14]
input [39:0] io_enq_bits_addr, // @[util.scala:463:14]
input [63:0] io_enq_bits_data, // @[util.scala:463:14]
input io_enq_bits_is_hella, // @[util.scala:463:14]
input io_enq_bits_tag_match, // @[util.scala:463:14]
input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:463:14]
input [19:0] io_enq_bits_old_meta_tag, // @[util.scala:463:14]
input [7:0] io_enq_bits_way_en, // @[util.scala:463:14]
input [4:0] io_enq_bits_sdq_id, // @[util.scala:463:14]
input io_deq_ready, // @[util.scala:463:14]
output io_deq_valid, // @[util.scala:463:14]
output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14]
output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14]
output io_deq_bits_uop_is_rvc, // @[util.scala:463:14]
output [39:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14]
output [15:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14]
output io_deq_bits_uop_is_sfb, // @[util.scala:463:14]
output io_deq_bits_uop_is_fence, // @[util.scala:463:14]
output io_deq_bits_uop_is_fencei, // @[util.scala:463:14]
output io_deq_bits_uop_is_sfence, // @[util.scala:463:14]
output io_deq_bits_uop_is_amo, // @[util.scala:463:14]
output io_deq_bits_uop_is_eret, // @[util.scala:463:14]
output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14]
output io_deq_bits_uop_is_rocc, // @[util.scala:463:14]
output io_deq_bits_uop_is_mov, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14]
output io_deq_bits_uop_edge_inst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14]
output io_deq_bits_uop_taken, // @[util.scala:463:14]
output io_deq_bits_uop_imm_rename, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14]
output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_pdst, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_prs1, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_prs2, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_prs3, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_ppred, // @[util.scala:463:14]
output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14]
output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14]
output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14]
output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14]
output io_deq_bits_uop_exception, // @[util.scala:463:14]
output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14]
output io_deq_bits_uop_mem_signed, // @[util.scala:463:14]
output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14]
output io_deq_bits_uop_uses_stq, // @[util.scala:463:14]
output io_deq_bits_uop_is_unique, // @[util.scala:463:14]
output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14]
output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14]
output io_deq_bits_uop_frs3_en, // @[util.scala:463:14]
output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14]
output io_deq_bits_uop_fp_val, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14]
output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14]
output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14]
output [39:0] io_deq_bits_addr, // @[util.scala:463:14]
output [63:0] io_deq_bits_data, // @[util.scala:463:14]
output io_deq_bits_is_hella, // @[util.scala:463:14]
output io_deq_bits_tag_match, // @[util.scala:463:14]
output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:463:14]
output [19:0] io_deq_bits_old_meta_tag, // @[util.scala:463:14]
output [7:0] io_deq_bits_way_en, // @[util.scala:463:14]
output [4:0] io_deq_bits_sdq_id, // @[util.scala:463:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[util.scala:463:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[util.scala:463:14]
input [31:0] io_brupdate_b2_uop_inst, // @[util.scala:463:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_rvc, // @[util.scala:463:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_0, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_1, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_2, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_3, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_0, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_1, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_2, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_3, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_4, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_5, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_6, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_7, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_8, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_9, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_issued, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[util.scala:463:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[util.scala:463:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[util.scala:463:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_sfb, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_fence, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_fencei, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_sfence, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_amo, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_eret, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_rocc, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_mov, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[util.scala:463:14]
input io_brupdate_b2_uop_edge_inst, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[util.scala:463:14]
input io_brupdate_b2_uop_taken, // @[util.scala:463:14]
input io_brupdate_b2_uop_imm_rename, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[util.scala:463:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[util.scala:463:14]
input io_brupdate_b2_uop_prs1_busy, // @[util.scala:463:14]
input io_brupdate_b2_uop_prs2_busy, // @[util.scala:463:14]
input io_brupdate_b2_uop_prs3_busy, // @[util.scala:463:14]
input io_brupdate_b2_uop_ppred_busy, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[util.scala:463:14]
input io_brupdate_b2_uop_exception, // @[util.scala:463:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[util.scala:463:14]
input io_brupdate_b2_uop_mem_signed, // @[util.scala:463:14]
input io_brupdate_b2_uop_uses_ldq, // @[util.scala:463:14]
input io_brupdate_b2_uop_uses_stq, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_unique, // @[util.scala:463:14]
input io_brupdate_b2_uop_flush_on_commit, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[util.scala:463:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[util.scala:463:14]
input io_brupdate_b2_uop_frs3_en, // @[util.scala:463:14]
input io_brupdate_b2_uop_fcn_dw, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_val, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[util.scala:463:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_bp_debug_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[util.scala:463:14]
input io_brupdate_b2_mispredict, // @[util.scala:463:14]
input io_brupdate_b2_taken, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_cfi_type, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_pc_sel, // @[util.scala:463:14]
input [39:0] io_brupdate_b2_jalr_target, // @[util.scala:463:14]
input [20:0] io_brupdate_b2_target_offset, // @[util.scala:463:14]
input io_flush, // @[util.scala:463:14]
output io_empty, // @[util.scala:463:14]
output [3:0] io_count // @[util.scala:463:14]
);
wire [140:0] _ram_ext_R0_data; // @[util.scala:503:22]
wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7]
wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7]
wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7]
wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7]
wire [39:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7]
wire [15:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7]
wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7]
wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7]
wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7]
wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7]
wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7]
wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7]
wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7]
wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7]
wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7]
wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7]
wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7]
wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7]
wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7]
wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7]
wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7]
wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7]
wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7]
wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7]
wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7]
wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7]
wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7]
wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7]
wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7]
wire [39:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:458:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7]
wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:458:7]
wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:458:7]
wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:458:7]
wire [19:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:458:7]
wire [7:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:458:7]
wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:458:7]
wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[util.scala:458:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[util.scala:458:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[util.scala:458:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[util.scala:458:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[util.scala:458:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[util.scala:458:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[util.scala:458:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[util.scala:458:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[util.scala:458:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[util.scala:458:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[util.scala:458:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[util.scala:458:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[util.scala:458:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[util.scala:458:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[util.scala:458:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[util.scala:458:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[util.scala:458:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[util.scala:458:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[util.scala:458:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[util.scala:458:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[util.scala:458:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[util.scala:458:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[util.scala:458:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[util.scala:458:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[util.scala:458:7]
wire io_flush_0 = io_flush; // @[util.scala:458:7]
wire _valids_WIRE_0 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_1 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_2 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_3 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_4 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_5 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_6 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_7 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_8 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_9 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_10 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_11 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_12 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_13 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_14 = 1'h0; // @[util.scala:504:34]
wire _io_enq_ready_T; // @[util.scala:543:21]
wire _io_deq_valid_T_1; // @[util.scala:548:42]
wire [31:0] out_uop_inst; // @[util.scala:545:19]
wire [31:0] out_uop_debug_inst; // @[util.scala:545:19]
wire out_uop_is_rvc; // @[util.scala:545:19]
wire [39:0] out_uop_debug_pc; // @[util.scala:545:19]
wire out_uop_iq_type_0; // @[util.scala:545:19]
wire out_uop_iq_type_1; // @[util.scala:545:19]
wire out_uop_iq_type_2; // @[util.scala:545:19]
wire out_uop_iq_type_3; // @[util.scala:545:19]
wire out_uop_fu_code_0; // @[util.scala:545:19]
wire out_uop_fu_code_1; // @[util.scala:545:19]
wire out_uop_fu_code_2; // @[util.scala:545:19]
wire out_uop_fu_code_3; // @[util.scala:545:19]
wire out_uop_fu_code_4; // @[util.scala:545:19]
wire out_uop_fu_code_5; // @[util.scala:545:19]
wire out_uop_fu_code_6; // @[util.scala:545:19]
wire out_uop_fu_code_7; // @[util.scala:545:19]
wire out_uop_fu_code_8; // @[util.scala:545:19]
wire out_uop_fu_code_9; // @[util.scala:545:19]
wire out_uop_iw_issued; // @[util.scala:545:19]
wire out_uop_iw_issued_partial_agen; // @[util.scala:545:19]
wire out_uop_iw_issued_partial_dgen; // @[util.scala:545:19]
wire [2:0] out_uop_iw_p1_speculative_child; // @[util.scala:545:19]
wire [2:0] out_uop_iw_p2_speculative_child; // @[util.scala:545:19]
wire out_uop_iw_p1_bypass_hint; // @[util.scala:545:19]
wire out_uop_iw_p2_bypass_hint; // @[util.scala:545:19]
wire out_uop_iw_p3_bypass_hint; // @[util.scala:545:19]
wire [2:0] out_uop_dis_col_sel; // @[util.scala:545:19]
wire [15:0] out_uop_br_mask; // @[util.scala:545:19]
wire [3:0] out_uop_br_tag; // @[util.scala:545:19]
wire [3:0] out_uop_br_type; // @[util.scala:545:19]
wire out_uop_is_sfb; // @[util.scala:545:19]
wire out_uop_is_fence; // @[util.scala:545:19]
wire out_uop_is_fencei; // @[util.scala:545:19]
wire out_uop_is_sfence; // @[util.scala:545:19]
wire out_uop_is_amo; // @[util.scala:545:19]
wire out_uop_is_eret; // @[util.scala:545:19]
wire out_uop_is_sys_pc2epc; // @[util.scala:545:19]
wire out_uop_is_rocc; // @[util.scala:545:19]
wire out_uop_is_mov; // @[util.scala:545:19]
wire [4:0] out_uop_ftq_idx; // @[util.scala:545:19]
wire out_uop_edge_inst; // @[util.scala:545:19]
wire [5:0] out_uop_pc_lob; // @[util.scala:545:19]
wire out_uop_taken; // @[util.scala:545:19]
wire out_uop_imm_rename; // @[util.scala:545:19]
wire [2:0] out_uop_imm_sel; // @[util.scala:545:19]
wire [4:0] out_uop_pimm; // @[util.scala:545:19]
wire [19:0] out_uop_imm_packed; // @[util.scala:545:19]
wire [1:0] out_uop_op1_sel; // @[util.scala:545:19]
wire [2:0] out_uop_op2_sel; // @[util.scala:545:19]
wire out_uop_fp_ctrl_ldst; // @[util.scala:545:19]
wire out_uop_fp_ctrl_wen; // @[util.scala:545:19]
wire out_uop_fp_ctrl_ren1; // @[util.scala:545:19]
wire out_uop_fp_ctrl_ren2; // @[util.scala:545:19]
wire out_uop_fp_ctrl_ren3; // @[util.scala:545:19]
wire out_uop_fp_ctrl_swap12; // @[util.scala:545:19]
wire out_uop_fp_ctrl_swap23; // @[util.scala:545:19]
wire [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:545:19]
wire [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:545:19]
wire out_uop_fp_ctrl_fromint; // @[util.scala:545:19]
wire out_uop_fp_ctrl_toint; // @[util.scala:545:19]
wire out_uop_fp_ctrl_fastpipe; // @[util.scala:545:19]
wire out_uop_fp_ctrl_fma; // @[util.scala:545:19]
wire out_uop_fp_ctrl_div; // @[util.scala:545:19]
wire out_uop_fp_ctrl_sqrt; // @[util.scala:545:19]
wire out_uop_fp_ctrl_wflags; // @[util.scala:545:19]
wire out_uop_fp_ctrl_vec; // @[util.scala:545:19]
wire [6:0] out_uop_rob_idx; // @[util.scala:545:19]
wire [4:0] out_uop_ldq_idx; // @[util.scala:545:19]
wire [4:0] out_uop_stq_idx; // @[util.scala:545:19]
wire [1:0] out_uop_rxq_idx; // @[util.scala:545:19]
wire [6:0] out_uop_pdst; // @[util.scala:545:19]
wire [6:0] out_uop_prs1; // @[util.scala:545:19]
wire [6:0] out_uop_prs2; // @[util.scala:545:19]
wire [6:0] out_uop_prs3; // @[util.scala:545:19]
wire [4:0] out_uop_ppred; // @[util.scala:545:19]
wire out_uop_prs1_busy; // @[util.scala:545:19]
wire out_uop_prs2_busy; // @[util.scala:545:19]
wire out_uop_prs3_busy; // @[util.scala:545:19]
wire out_uop_ppred_busy; // @[util.scala:545:19]
wire [6:0] out_uop_stale_pdst; // @[util.scala:545:19]
wire out_uop_exception; // @[util.scala:545:19]
wire [63:0] out_uop_exc_cause; // @[util.scala:545:19]
wire [4:0] out_uop_mem_cmd; // @[util.scala:545:19]
wire [1:0] out_uop_mem_size; // @[util.scala:545:19]
wire out_uop_mem_signed; // @[util.scala:545:19]
wire out_uop_uses_ldq; // @[util.scala:545:19]
wire out_uop_uses_stq; // @[util.scala:545:19]
wire out_uop_is_unique; // @[util.scala:545:19]
wire out_uop_flush_on_commit; // @[util.scala:545:19]
wire [2:0] out_uop_csr_cmd; // @[util.scala:545:19]
wire out_uop_ldst_is_rs1; // @[util.scala:545:19]
wire [5:0] out_uop_ldst; // @[util.scala:545:19]
wire [5:0] out_uop_lrs1; // @[util.scala:545:19]
wire [5:0] out_uop_lrs2; // @[util.scala:545:19]
wire [5:0] out_uop_lrs3; // @[util.scala:545:19]
wire [1:0] out_uop_dst_rtype; // @[util.scala:545:19]
wire [1:0] out_uop_lrs1_rtype; // @[util.scala:545:19]
wire [1:0] out_uop_lrs2_rtype; // @[util.scala:545:19]
wire out_uop_frs3_en; // @[util.scala:545:19]
wire out_uop_fcn_dw; // @[util.scala:545:19]
wire [4:0] out_uop_fcn_op; // @[util.scala:545:19]
wire out_uop_fp_val; // @[util.scala:545:19]
wire [2:0] out_uop_fp_rm; // @[util.scala:545:19]
wire [1:0] out_uop_fp_typ; // @[util.scala:545:19]
wire out_uop_xcpt_pf_if; // @[util.scala:545:19]
wire out_uop_xcpt_ae_if; // @[util.scala:545:19]
wire out_uop_xcpt_ma_if; // @[util.scala:545:19]
wire out_uop_bp_debug_if; // @[util.scala:545:19]
wire out_uop_bp_xcpt_if; // @[util.scala:545:19]
wire [2:0] out_uop_debug_fsrc; // @[util.scala:545:19]
wire [2:0] out_uop_debug_tsrc; // @[util.scala:545:19]
wire [39:0] out_addr; // @[util.scala:545:19]
wire [63:0] out_data; // @[util.scala:545:19]
wire out_is_hella; // @[util.scala:545:19]
wire out_tag_match; // @[util.scala:545:19]
wire [1:0] out_old_meta_coh_state; // @[util.scala:545:19]
wire [19:0] out_old_meta_tag; // @[util.scala:545:19]
wire [7:0] out_way_en; // @[util.scala:545:19]
wire [4:0] out_sdq_id; // @[util.scala:545:19]
wire _io_empty_T_1; // @[util.scala:512:27]
wire [3:0] _io_count_T_5; // @[util.scala:556:22]
wire io_enq_ready_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7]
wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7]
wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7]
wire [39:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7]
wire [15:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7]
wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7]
wire io_deq_bits_uop_taken_0; // @[util.scala:458:7]
wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7]
wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_exception_0; // @[util.scala:458:7]
wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7]
wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7]
wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7]
wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7]
wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7]
wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7]
wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7]
wire [19:0] io_deq_bits_old_meta_tag_0; // @[util.scala:458:7]
wire [39:0] io_deq_bits_addr_0; // @[util.scala:458:7]
wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7]
wire io_deq_bits_is_hella_0; // @[util.scala:458:7]
wire io_deq_bits_tag_match_0; // @[util.scala:458:7]
wire [7:0] io_deq_bits_way_en_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:458:7]
wire io_deq_valid_0; // @[util.scala:458:7]
wire io_empty_0; // @[util.scala:458:7]
wire [3:0] io_count_0; // @[util.scala:458:7]
assign out_addr = _ram_ext_R0_data[39:0]; // @[util.scala:503:22, :545:19]
assign out_data = _ram_ext_R0_data[103:40]; // @[util.scala:503:22, :545:19]
assign out_is_hella = _ram_ext_R0_data[104]; // @[util.scala:503:22, :545:19]
assign out_tag_match = _ram_ext_R0_data[105]; // @[util.scala:503:22, :545:19]
assign out_old_meta_coh_state = _ram_ext_R0_data[107:106]; // @[util.scala:503:22, :545:19]
assign out_old_meta_tag = _ram_ext_R0_data[127:108]; // @[util.scala:503:22, :545:19]
assign out_way_en = _ram_ext_R0_data[135:128]; // @[util.scala:503:22, :545:19]
assign out_sdq_id = _ram_ext_R0_data[140:136]; // @[util.scala:503:22, :545:19]
reg valids_0; // @[util.scala:504:26]
reg valids_1; // @[util.scala:504:26]
reg valids_2; // @[util.scala:504:26]
reg valids_3; // @[util.scala:504:26]
reg valids_4; // @[util.scala:504:26]
reg valids_5; // @[util.scala:504:26]
reg valids_6; // @[util.scala:504:26]
reg valids_7; // @[util.scala:504:26]
reg valids_8; // @[util.scala:504:26]
reg valids_9; // @[util.scala:504:26]
reg valids_10; // @[util.scala:504:26]
reg valids_11; // @[util.scala:504:26]
reg valids_12; // @[util.scala:504:26]
reg valids_13; // @[util.scala:504:26]
reg valids_14; // @[util.scala:504:26]
reg [31:0] uops_0_inst; // @[util.scala:505:22]
reg [31:0] uops_0_debug_inst; // @[util.scala:505:22]
reg uops_0_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_0_debug_pc; // @[util.scala:505:22]
reg uops_0_iq_type_0; // @[util.scala:505:22]
reg uops_0_iq_type_1; // @[util.scala:505:22]
reg uops_0_iq_type_2; // @[util.scala:505:22]
reg uops_0_iq_type_3; // @[util.scala:505:22]
reg uops_0_fu_code_0; // @[util.scala:505:22]
reg uops_0_fu_code_1; // @[util.scala:505:22]
reg uops_0_fu_code_2; // @[util.scala:505:22]
reg uops_0_fu_code_3; // @[util.scala:505:22]
reg uops_0_fu_code_4; // @[util.scala:505:22]
reg uops_0_fu_code_5; // @[util.scala:505:22]
reg uops_0_fu_code_6; // @[util.scala:505:22]
reg uops_0_fu_code_7; // @[util.scala:505:22]
reg uops_0_fu_code_8; // @[util.scala:505:22]
reg uops_0_fu_code_9; // @[util.scala:505:22]
reg uops_0_iw_issued; // @[util.scala:505:22]
reg uops_0_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_0_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_0_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_0_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_0_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_0_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_0_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_0_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_0_br_mask; // @[util.scala:505:22]
reg [3:0] uops_0_br_tag; // @[util.scala:505:22]
reg [3:0] uops_0_br_type; // @[util.scala:505:22]
reg uops_0_is_sfb; // @[util.scala:505:22]
reg uops_0_is_fence; // @[util.scala:505:22]
reg uops_0_is_fencei; // @[util.scala:505:22]
reg uops_0_is_sfence; // @[util.scala:505:22]
reg uops_0_is_amo; // @[util.scala:505:22]
reg uops_0_is_eret; // @[util.scala:505:22]
reg uops_0_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_0_is_rocc; // @[util.scala:505:22]
reg uops_0_is_mov; // @[util.scala:505:22]
reg [4:0] uops_0_ftq_idx; // @[util.scala:505:22]
reg uops_0_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_0_pc_lob; // @[util.scala:505:22]
reg uops_0_taken; // @[util.scala:505:22]
reg uops_0_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_0_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_0_pimm; // @[util.scala:505:22]
reg [19:0] uops_0_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_0_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_0_op2_sel; // @[util.scala:505:22]
reg uops_0_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_0_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_0_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_0_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_0_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_0_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_0_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_0_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_0_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_0_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_0_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_0_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_0_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_0_fp_ctrl_div; // @[util.scala:505:22]
reg uops_0_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_0_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_0_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_0_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_0_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_0_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_0_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_0_pdst; // @[util.scala:505:22]
reg [6:0] uops_0_prs1; // @[util.scala:505:22]
reg [6:0] uops_0_prs2; // @[util.scala:505:22]
reg [6:0] uops_0_prs3; // @[util.scala:505:22]
reg [4:0] uops_0_ppred; // @[util.scala:505:22]
reg uops_0_prs1_busy; // @[util.scala:505:22]
reg uops_0_prs2_busy; // @[util.scala:505:22]
reg uops_0_prs3_busy; // @[util.scala:505:22]
reg uops_0_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_0_stale_pdst; // @[util.scala:505:22]
reg uops_0_exception; // @[util.scala:505:22]
reg [63:0] uops_0_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_0_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_0_mem_size; // @[util.scala:505:22]
reg uops_0_mem_signed; // @[util.scala:505:22]
reg uops_0_uses_ldq; // @[util.scala:505:22]
reg uops_0_uses_stq; // @[util.scala:505:22]
reg uops_0_is_unique; // @[util.scala:505:22]
reg uops_0_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_0_csr_cmd; // @[util.scala:505:22]
reg uops_0_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_0_ldst; // @[util.scala:505:22]
reg [5:0] uops_0_lrs1; // @[util.scala:505:22]
reg [5:0] uops_0_lrs2; // @[util.scala:505:22]
reg [5:0] uops_0_lrs3; // @[util.scala:505:22]
reg [1:0] uops_0_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_0_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_0_lrs2_rtype; // @[util.scala:505:22]
reg uops_0_frs3_en; // @[util.scala:505:22]
reg uops_0_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_0_fcn_op; // @[util.scala:505:22]
reg uops_0_fp_val; // @[util.scala:505:22]
reg [2:0] uops_0_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_0_fp_typ; // @[util.scala:505:22]
reg uops_0_xcpt_pf_if; // @[util.scala:505:22]
reg uops_0_xcpt_ae_if; // @[util.scala:505:22]
reg uops_0_xcpt_ma_if; // @[util.scala:505:22]
reg uops_0_bp_debug_if; // @[util.scala:505:22]
reg uops_0_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_0_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_0_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_1_inst; // @[util.scala:505:22]
reg [31:0] uops_1_debug_inst; // @[util.scala:505:22]
reg uops_1_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_1_debug_pc; // @[util.scala:505:22]
reg uops_1_iq_type_0; // @[util.scala:505:22]
reg uops_1_iq_type_1; // @[util.scala:505:22]
reg uops_1_iq_type_2; // @[util.scala:505:22]
reg uops_1_iq_type_3; // @[util.scala:505:22]
reg uops_1_fu_code_0; // @[util.scala:505:22]
reg uops_1_fu_code_1; // @[util.scala:505:22]
reg uops_1_fu_code_2; // @[util.scala:505:22]
reg uops_1_fu_code_3; // @[util.scala:505:22]
reg uops_1_fu_code_4; // @[util.scala:505:22]
reg uops_1_fu_code_5; // @[util.scala:505:22]
reg uops_1_fu_code_6; // @[util.scala:505:22]
reg uops_1_fu_code_7; // @[util.scala:505:22]
reg uops_1_fu_code_8; // @[util.scala:505:22]
reg uops_1_fu_code_9; // @[util.scala:505:22]
reg uops_1_iw_issued; // @[util.scala:505:22]
reg uops_1_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_1_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_1_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_1_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_1_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_1_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_1_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_1_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_1_br_mask; // @[util.scala:505:22]
reg [3:0] uops_1_br_tag; // @[util.scala:505:22]
reg [3:0] uops_1_br_type; // @[util.scala:505:22]
reg uops_1_is_sfb; // @[util.scala:505:22]
reg uops_1_is_fence; // @[util.scala:505:22]
reg uops_1_is_fencei; // @[util.scala:505:22]
reg uops_1_is_sfence; // @[util.scala:505:22]
reg uops_1_is_amo; // @[util.scala:505:22]
reg uops_1_is_eret; // @[util.scala:505:22]
reg uops_1_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_1_is_rocc; // @[util.scala:505:22]
reg uops_1_is_mov; // @[util.scala:505:22]
reg [4:0] uops_1_ftq_idx; // @[util.scala:505:22]
reg uops_1_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_1_pc_lob; // @[util.scala:505:22]
reg uops_1_taken; // @[util.scala:505:22]
reg uops_1_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_1_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_1_pimm; // @[util.scala:505:22]
reg [19:0] uops_1_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_1_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_1_op2_sel; // @[util.scala:505:22]
reg uops_1_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_1_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_1_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_1_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_1_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_1_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_1_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_1_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_1_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_1_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_1_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_1_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_1_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_1_fp_ctrl_div; // @[util.scala:505:22]
reg uops_1_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_1_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_1_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_1_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_1_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_1_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_1_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_1_pdst; // @[util.scala:505:22]
reg [6:0] uops_1_prs1; // @[util.scala:505:22]
reg [6:0] uops_1_prs2; // @[util.scala:505:22]
reg [6:0] uops_1_prs3; // @[util.scala:505:22]
reg [4:0] uops_1_ppred; // @[util.scala:505:22]
reg uops_1_prs1_busy; // @[util.scala:505:22]
reg uops_1_prs2_busy; // @[util.scala:505:22]
reg uops_1_prs3_busy; // @[util.scala:505:22]
reg uops_1_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_1_stale_pdst; // @[util.scala:505:22]
reg uops_1_exception; // @[util.scala:505:22]
reg [63:0] uops_1_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_1_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_1_mem_size; // @[util.scala:505:22]
reg uops_1_mem_signed; // @[util.scala:505:22]
reg uops_1_uses_ldq; // @[util.scala:505:22]
reg uops_1_uses_stq; // @[util.scala:505:22]
reg uops_1_is_unique; // @[util.scala:505:22]
reg uops_1_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_1_csr_cmd; // @[util.scala:505:22]
reg uops_1_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_1_ldst; // @[util.scala:505:22]
reg [5:0] uops_1_lrs1; // @[util.scala:505:22]
reg [5:0] uops_1_lrs2; // @[util.scala:505:22]
reg [5:0] uops_1_lrs3; // @[util.scala:505:22]
reg [1:0] uops_1_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_1_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_1_lrs2_rtype; // @[util.scala:505:22]
reg uops_1_frs3_en; // @[util.scala:505:22]
reg uops_1_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_1_fcn_op; // @[util.scala:505:22]
reg uops_1_fp_val; // @[util.scala:505:22]
reg [2:0] uops_1_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_1_fp_typ; // @[util.scala:505:22]
reg uops_1_xcpt_pf_if; // @[util.scala:505:22]
reg uops_1_xcpt_ae_if; // @[util.scala:505:22]
reg uops_1_xcpt_ma_if; // @[util.scala:505:22]
reg uops_1_bp_debug_if; // @[util.scala:505:22]
reg uops_1_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_1_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_1_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_2_inst; // @[util.scala:505:22]
reg [31:0] uops_2_debug_inst; // @[util.scala:505:22]
reg uops_2_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_2_debug_pc; // @[util.scala:505:22]
reg uops_2_iq_type_0; // @[util.scala:505:22]
reg uops_2_iq_type_1; // @[util.scala:505:22]
reg uops_2_iq_type_2; // @[util.scala:505:22]
reg uops_2_iq_type_3; // @[util.scala:505:22]
reg uops_2_fu_code_0; // @[util.scala:505:22]
reg uops_2_fu_code_1; // @[util.scala:505:22]
reg uops_2_fu_code_2; // @[util.scala:505:22]
reg uops_2_fu_code_3; // @[util.scala:505:22]
reg uops_2_fu_code_4; // @[util.scala:505:22]
reg uops_2_fu_code_5; // @[util.scala:505:22]
reg uops_2_fu_code_6; // @[util.scala:505:22]
reg uops_2_fu_code_7; // @[util.scala:505:22]
reg uops_2_fu_code_8; // @[util.scala:505:22]
reg uops_2_fu_code_9; // @[util.scala:505:22]
reg uops_2_iw_issued; // @[util.scala:505:22]
reg uops_2_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_2_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_2_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_2_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_2_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_2_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_2_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_2_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_2_br_mask; // @[util.scala:505:22]
reg [3:0] uops_2_br_tag; // @[util.scala:505:22]
reg [3:0] uops_2_br_type; // @[util.scala:505:22]
reg uops_2_is_sfb; // @[util.scala:505:22]
reg uops_2_is_fence; // @[util.scala:505:22]
reg uops_2_is_fencei; // @[util.scala:505:22]
reg uops_2_is_sfence; // @[util.scala:505:22]
reg uops_2_is_amo; // @[util.scala:505:22]
reg uops_2_is_eret; // @[util.scala:505:22]
reg uops_2_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_2_is_rocc; // @[util.scala:505:22]
reg uops_2_is_mov; // @[util.scala:505:22]
reg [4:0] uops_2_ftq_idx; // @[util.scala:505:22]
reg uops_2_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_2_pc_lob; // @[util.scala:505:22]
reg uops_2_taken; // @[util.scala:505:22]
reg uops_2_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_2_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_2_pimm; // @[util.scala:505:22]
reg [19:0] uops_2_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_2_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_2_op2_sel; // @[util.scala:505:22]
reg uops_2_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_2_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_2_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_2_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_2_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_2_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_2_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_2_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_2_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_2_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_2_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_2_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_2_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_2_fp_ctrl_div; // @[util.scala:505:22]
reg uops_2_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_2_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_2_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_2_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_2_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_2_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_2_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_2_pdst; // @[util.scala:505:22]
reg [6:0] uops_2_prs1; // @[util.scala:505:22]
reg [6:0] uops_2_prs2; // @[util.scala:505:22]
reg [6:0] uops_2_prs3; // @[util.scala:505:22]
reg [4:0] uops_2_ppred; // @[util.scala:505:22]
reg uops_2_prs1_busy; // @[util.scala:505:22]
reg uops_2_prs2_busy; // @[util.scala:505:22]
reg uops_2_prs3_busy; // @[util.scala:505:22]
reg uops_2_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_2_stale_pdst; // @[util.scala:505:22]
reg uops_2_exception; // @[util.scala:505:22]
reg [63:0] uops_2_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_2_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_2_mem_size; // @[util.scala:505:22]
reg uops_2_mem_signed; // @[util.scala:505:22]
reg uops_2_uses_ldq; // @[util.scala:505:22]
reg uops_2_uses_stq; // @[util.scala:505:22]
reg uops_2_is_unique; // @[util.scala:505:22]
reg uops_2_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_2_csr_cmd; // @[util.scala:505:22]
reg uops_2_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_2_ldst; // @[util.scala:505:22]
reg [5:0] uops_2_lrs1; // @[util.scala:505:22]
reg [5:0] uops_2_lrs2; // @[util.scala:505:22]
reg [5:0] uops_2_lrs3; // @[util.scala:505:22]
reg [1:0] uops_2_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_2_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_2_lrs2_rtype; // @[util.scala:505:22]
reg uops_2_frs3_en; // @[util.scala:505:22]
reg uops_2_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_2_fcn_op; // @[util.scala:505:22]
reg uops_2_fp_val; // @[util.scala:505:22]
reg [2:0] uops_2_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_2_fp_typ; // @[util.scala:505:22]
reg uops_2_xcpt_pf_if; // @[util.scala:505:22]
reg uops_2_xcpt_ae_if; // @[util.scala:505:22]
reg uops_2_xcpt_ma_if; // @[util.scala:505:22]
reg uops_2_bp_debug_if; // @[util.scala:505:22]
reg uops_2_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_2_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_2_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_3_inst; // @[util.scala:505:22]
reg [31:0] uops_3_debug_inst; // @[util.scala:505:22]
reg uops_3_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_3_debug_pc; // @[util.scala:505:22]
reg uops_3_iq_type_0; // @[util.scala:505:22]
reg uops_3_iq_type_1; // @[util.scala:505:22]
reg uops_3_iq_type_2; // @[util.scala:505:22]
reg uops_3_iq_type_3; // @[util.scala:505:22]
reg uops_3_fu_code_0; // @[util.scala:505:22]
reg uops_3_fu_code_1; // @[util.scala:505:22]
reg uops_3_fu_code_2; // @[util.scala:505:22]
reg uops_3_fu_code_3; // @[util.scala:505:22]
reg uops_3_fu_code_4; // @[util.scala:505:22]
reg uops_3_fu_code_5; // @[util.scala:505:22]
reg uops_3_fu_code_6; // @[util.scala:505:22]
reg uops_3_fu_code_7; // @[util.scala:505:22]
reg uops_3_fu_code_8; // @[util.scala:505:22]
reg uops_3_fu_code_9; // @[util.scala:505:22]
reg uops_3_iw_issued; // @[util.scala:505:22]
reg uops_3_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_3_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_3_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_3_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_3_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_3_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_3_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_3_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_3_br_mask; // @[util.scala:505:22]
reg [3:0] uops_3_br_tag; // @[util.scala:505:22]
reg [3:0] uops_3_br_type; // @[util.scala:505:22]
reg uops_3_is_sfb; // @[util.scala:505:22]
reg uops_3_is_fence; // @[util.scala:505:22]
reg uops_3_is_fencei; // @[util.scala:505:22]
reg uops_3_is_sfence; // @[util.scala:505:22]
reg uops_3_is_amo; // @[util.scala:505:22]
reg uops_3_is_eret; // @[util.scala:505:22]
reg uops_3_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_3_is_rocc; // @[util.scala:505:22]
reg uops_3_is_mov; // @[util.scala:505:22]
reg [4:0] uops_3_ftq_idx; // @[util.scala:505:22]
reg uops_3_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_3_pc_lob; // @[util.scala:505:22]
reg uops_3_taken; // @[util.scala:505:22]
reg uops_3_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_3_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_3_pimm; // @[util.scala:505:22]
reg [19:0] uops_3_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_3_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_3_op2_sel; // @[util.scala:505:22]
reg uops_3_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_3_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_3_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_3_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_3_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_3_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_3_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_3_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_3_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_3_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_3_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_3_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_3_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_3_fp_ctrl_div; // @[util.scala:505:22]
reg uops_3_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_3_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_3_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_3_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_3_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_3_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_3_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_3_pdst; // @[util.scala:505:22]
reg [6:0] uops_3_prs1; // @[util.scala:505:22]
reg [6:0] uops_3_prs2; // @[util.scala:505:22]
reg [6:0] uops_3_prs3; // @[util.scala:505:22]
reg [4:0] uops_3_ppred; // @[util.scala:505:22]
reg uops_3_prs1_busy; // @[util.scala:505:22]
reg uops_3_prs2_busy; // @[util.scala:505:22]
reg uops_3_prs3_busy; // @[util.scala:505:22]
reg uops_3_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_3_stale_pdst; // @[util.scala:505:22]
reg uops_3_exception; // @[util.scala:505:22]
reg [63:0] uops_3_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_3_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_3_mem_size; // @[util.scala:505:22]
reg uops_3_mem_signed; // @[util.scala:505:22]
reg uops_3_uses_ldq; // @[util.scala:505:22]
reg uops_3_uses_stq; // @[util.scala:505:22]
reg uops_3_is_unique; // @[util.scala:505:22]
reg uops_3_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_3_csr_cmd; // @[util.scala:505:22]
reg uops_3_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_3_ldst; // @[util.scala:505:22]
reg [5:0] uops_3_lrs1; // @[util.scala:505:22]
reg [5:0] uops_3_lrs2; // @[util.scala:505:22]
reg [5:0] uops_3_lrs3; // @[util.scala:505:22]
reg [1:0] uops_3_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_3_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_3_lrs2_rtype; // @[util.scala:505:22]
reg uops_3_frs3_en; // @[util.scala:505:22]
reg uops_3_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_3_fcn_op; // @[util.scala:505:22]
reg uops_3_fp_val; // @[util.scala:505:22]
reg [2:0] uops_3_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_3_fp_typ; // @[util.scala:505:22]
reg uops_3_xcpt_pf_if; // @[util.scala:505:22]
reg uops_3_xcpt_ae_if; // @[util.scala:505:22]
reg uops_3_xcpt_ma_if; // @[util.scala:505:22]
reg uops_3_bp_debug_if; // @[util.scala:505:22]
reg uops_3_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_3_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_3_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_4_inst; // @[util.scala:505:22]
reg [31:0] uops_4_debug_inst; // @[util.scala:505:22]
reg uops_4_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_4_debug_pc; // @[util.scala:505:22]
reg uops_4_iq_type_0; // @[util.scala:505:22]
reg uops_4_iq_type_1; // @[util.scala:505:22]
reg uops_4_iq_type_2; // @[util.scala:505:22]
reg uops_4_iq_type_3; // @[util.scala:505:22]
reg uops_4_fu_code_0; // @[util.scala:505:22]
reg uops_4_fu_code_1; // @[util.scala:505:22]
reg uops_4_fu_code_2; // @[util.scala:505:22]
reg uops_4_fu_code_3; // @[util.scala:505:22]
reg uops_4_fu_code_4; // @[util.scala:505:22]
reg uops_4_fu_code_5; // @[util.scala:505:22]
reg uops_4_fu_code_6; // @[util.scala:505:22]
reg uops_4_fu_code_7; // @[util.scala:505:22]
reg uops_4_fu_code_8; // @[util.scala:505:22]
reg uops_4_fu_code_9; // @[util.scala:505:22]
reg uops_4_iw_issued; // @[util.scala:505:22]
reg uops_4_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_4_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_4_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_4_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_4_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_4_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_4_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_4_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_4_br_mask; // @[util.scala:505:22]
reg [3:0] uops_4_br_tag; // @[util.scala:505:22]
reg [3:0] uops_4_br_type; // @[util.scala:505:22]
reg uops_4_is_sfb; // @[util.scala:505:22]
reg uops_4_is_fence; // @[util.scala:505:22]
reg uops_4_is_fencei; // @[util.scala:505:22]
reg uops_4_is_sfence; // @[util.scala:505:22]
reg uops_4_is_amo; // @[util.scala:505:22]
reg uops_4_is_eret; // @[util.scala:505:22]
reg uops_4_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_4_is_rocc; // @[util.scala:505:22]
reg uops_4_is_mov; // @[util.scala:505:22]
reg [4:0] uops_4_ftq_idx; // @[util.scala:505:22]
reg uops_4_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_4_pc_lob; // @[util.scala:505:22]
reg uops_4_taken; // @[util.scala:505:22]
reg uops_4_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_4_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_4_pimm; // @[util.scala:505:22]
reg [19:0] uops_4_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_4_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_4_op2_sel; // @[util.scala:505:22]
reg uops_4_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_4_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_4_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_4_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_4_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_4_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_4_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_4_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_4_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_4_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_4_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_4_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_4_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_4_fp_ctrl_div; // @[util.scala:505:22]
reg uops_4_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_4_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_4_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_4_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_4_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_4_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_4_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_4_pdst; // @[util.scala:505:22]
reg [6:0] uops_4_prs1; // @[util.scala:505:22]
reg [6:0] uops_4_prs2; // @[util.scala:505:22]
reg [6:0] uops_4_prs3; // @[util.scala:505:22]
reg [4:0] uops_4_ppred; // @[util.scala:505:22]
reg uops_4_prs1_busy; // @[util.scala:505:22]
reg uops_4_prs2_busy; // @[util.scala:505:22]
reg uops_4_prs3_busy; // @[util.scala:505:22]
reg uops_4_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_4_stale_pdst; // @[util.scala:505:22]
reg uops_4_exception; // @[util.scala:505:22]
reg [63:0] uops_4_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_4_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_4_mem_size; // @[util.scala:505:22]
reg uops_4_mem_signed; // @[util.scala:505:22]
reg uops_4_uses_ldq; // @[util.scala:505:22]
reg uops_4_uses_stq; // @[util.scala:505:22]
reg uops_4_is_unique; // @[util.scala:505:22]
reg uops_4_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_4_csr_cmd; // @[util.scala:505:22]
reg uops_4_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_4_ldst; // @[util.scala:505:22]
reg [5:0] uops_4_lrs1; // @[util.scala:505:22]
reg [5:0] uops_4_lrs2; // @[util.scala:505:22]
reg [5:0] uops_4_lrs3; // @[util.scala:505:22]
reg [1:0] uops_4_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_4_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_4_lrs2_rtype; // @[util.scala:505:22]
reg uops_4_frs3_en; // @[util.scala:505:22]
reg uops_4_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_4_fcn_op; // @[util.scala:505:22]
reg uops_4_fp_val; // @[util.scala:505:22]
reg [2:0] uops_4_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_4_fp_typ; // @[util.scala:505:22]
reg uops_4_xcpt_pf_if; // @[util.scala:505:22]
reg uops_4_xcpt_ae_if; // @[util.scala:505:22]
reg uops_4_xcpt_ma_if; // @[util.scala:505:22]
reg uops_4_bp_debug_if; // @[util.scala:505:22]
reg uops_4_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_4_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_4_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_5_inst; // @[util.scala:505:22]
reg [31:0] uops_5_debug_inst; // @[util.scala:505:22]
reg uops_5_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_5_debug_pc; // @[util.scala:505:22]
reg uops_5_iq_type_0; // @[util.scala:505:22]
reg uops_5_iq_type_1; // @[util.scala:505:22]
reg uops_5_iq_type_2; // @[util.scala:505:22]
reg uops_5_iq_type_3; // @[util.scala:505:22]
reg uops_5_fu_code_0; // @[util.scala:505:22]
reg uops_5_fu_code_1; // @[util.scala:505:22]
reg uops_5_fu_code_2; // @[util.scala:505:22]
reg uops_5_fu_code_3; // @[util.scala:505:22]
reg uops_5_fu_code_4; // @[util.scala:505:22]
reg uops_5_fu_code_5; // @[util.scala:505:22]
reg uops_5_fu_code_6; // @[util.scala:505:22]
reg uops_5_fu_code_7; // @[util.scala:505:22]
reg uops_5_fu_code_8; // @[util.scala:505:22]
reg uops_5_fu_code_9; // @[util.scala:505:22]
reg uops_5_iw_issued; // @[util.scala:505:22]
reg uops_5_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_5_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_5_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_5_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_5_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_5_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_5_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_5_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_5_br_mask; // @[util.scala:505:22]
reg [3:0] uops_5_br_tag; // @[util.scala:505:22]
reg [3:0] uops_5_br_type; // @[util.scala:505:22]
reg uops_5_is_sfb; // @[util.scala:505:22]
reg uops_5_is_fence; // @[util.scala:505:22]
reg uops_5_is_fencei; // @[util.scala:505:22]
reg uops_5_is_sfence; // @[util.scala:505:22]
reg uops_5_is_amo; // @[util.scala:505:22]
reg uops_5_is_eret; // @[util.scala:505:22]
reg uops_5_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_5_is_rocc; // @[util.scala:505:22]
reg uops_5_is_mov; // @[util.scala:505:22]
reg [4:0] uops_5_ftq_idx; // @[util.scala:505:22]
reg uops_5_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_5_pc_lob; // @[util.scala:505:22]
reg uops_5_taken; // @[util.scala:505:22]
reg uops_5_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_5_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_5_pimm; // @[util.scala:505:22]
reg [19:0] uops_5_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_5_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_5_op2_sel; // @[util.scala:505:22]
reg uops_5_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_5_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_5_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_5_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_5_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_5_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_5_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_5_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_5_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_5_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_5_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_5_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_5_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_5_fp_ctrl_div; // @[util.scala:505:22]
reg uops_5_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_5_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_5_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_5_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_5_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_5_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_5_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_5_pdst; // @[util.scala:505:22]
reg [6:0] uops_5_prs1; // @[util.scala:505:22]
reg [6:0] uops_5_prs2; // @[util.scala:505:22]
reg [6:0] uops_5_prs3; // @[util.scala:505:22]
reg [4:0] uops_5_ppred; // @[util.scala:505:22]
reg uops_5_prs1_busy; // @[util.scala:505:22]
reg uops_5_prs2_busy; // @[util.scala:505:22]
reg uops_5_prs3_busy; // @[util.scala:505:22]
reg uops_5_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_5_stale_pdst; // @[util.scala:505:22]
reg uops_5_exception; // @[util.scala:505:22]
reg [63:0] uops_5_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_5_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_5_mem_size; // @[util.scala:505:22]
reg uops_5_mem_signed; // @[util.scala:505:22]
reg uops_5_uses_ldq; // @[util.scala:505:22]
reg uops_5_uses_stq; // @[util.scala:505:22]
reg uops_5_is_unique; // @[util.scala:505:22]
reg uops_5_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_5_csr_cmd; // @[util.scala:505:22]
reg uops_5_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_5_ldst; // @[util.scala:505:22]
reg [5:0] uops_5_lrs1; // @[util.scala:505:22]
reg [5:0] uops_5_lrs2; // @[util.scala:505:22]
reg [5:0] uops_5_lrs3; // @[util.scala:505:22]
reg [1:0] uops_5_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_5_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_5_lrs2_rtype; // @[util.scala:505:22]
reg uops_5_frs3_en; // @[util.scala:505:22]
reg uops_5_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_5_fcn_op; // @[util.scala:505:22]
reg uops_5_fp_val; // @[util.scala:505:22]
reg [2:0] uops_5_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_5_fp_typ; // @[util.scala:505:22]
reg uops_5_xcpt_pf_if; // @[util.scala:505:22]
reg uops_5_xcpt_ae_if; // @[util.scala:505:22]
reg uops_5_xcpt_ma_if; // @[util.scala:505:22]
reg uops_5_bp_debug_if; // @[util.scala:505:22]
reg uops_5_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_5_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_5_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_6_inst; // @[util.scala:505:22]
reg [31:0] uops_6_debug_inst; // @[util.scala:505:22]
reg uops_6_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_6_debug_pc; // @[util.scala:505:22]
reg uops_6_iq_type_0; // @[util.scala:505:22]
reg uops_6_iq_type_1; // @[util.scala:505:22]
reg uops_6_iq_type_2; // @[util.scala:505:22]
reg uops_6_iq_type_3; // @[util.scala:505:22]
reg uops_6_fu_code_0; // @[util.scala:505:22]
reg uops_6_fu_code_1; // @[util.scala:505:22]
reg uops_6_fu_code_2; // @[util.scala:505:22]
reg uops_6_fu_code_3; // @[util.scala:505:22]
reg uops_6_fu_code_4; // @[util.scala:505:22]
reg uops_6_fu_code_5; // @[util.scala:505:22]
reg uops_6_fu_code_6; // @[util.scala:505:22]
reg uops_6_fu_code_7; // @[util.scala:505:22]
reg uops_6_fu_code_8; // @[util.scala:505:22]
reg uops_6_fu_code_9; // @[util.scala:505:22]
reg uops_6_iw_issued; // @[util.scala:505:22]
reg uops_6_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_6_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_6_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_6_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_6_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_6_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_6_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_6_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_6_br_mask; // @[util.scala:505:22]
reg [3:0] uops_6_br_tag; // @[util.scala:505:22]
reg [3:0] uops_6_br_type; // @[util.scala:505:22]
reg uops_6_is_sfb; // @[util.scala:505:22]
reg uops_6_is_fence; // @[util.scala:505:22]
reg uops_6_is_fencei; // @[util.scala:505:22]
reg uops_6_is_sfence; // @[util.scala:505:22]
reg uops_6_is_amo; // @[util.scala:505:22]
reg uops_6_is_eret; // @[util.scala:505:22]
reg uops_6_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_6_is_rocc; // @[util.scala:505:22]
reg uops_6_is_mov; // @[util.scala:505:22]
reg [4:0] uops_6_ftq_idx; // @[util.scala:505:22]
reg uops_6_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_6_pc_lob; // @[util.scala:505:22]
reg uops_6_taken; // @[util.scala:505:22]
reg uops_6_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_6_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_6_pimm; // @[util.scala:505:22]
reg [19:0] uops_6_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_6_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_6_op2_sel; // @[util.scala:505:22]
reg uops_6_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_6_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_6_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_6_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_6_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_6_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_6_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_6_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_6_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_6_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_6_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_6_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_6_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_6_fp_ctrl_div; // @[util.scala:505:22]
reg uops_6_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_6_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_6_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_6_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_6_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_6_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_6_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_6_pdst; // @[util.scala:505:22]
reg [6:0] uops_6_prs1; // @[util.scala:505:22]
reg [6:0] uops_6_prs2; // @[util.scala:505:22]
reg [6:0] uops_6_prs3; // @[util.scala:505:22]
reg [4:0] uops_6_ppred; // @[util.scala:505:22]
reg uops_6_prs1_busy; // @[util.scala:505:22]
reg uops_6_prs2_busy; // @[util.scala:505:22]
reg uops_6_prs3_busy; // @[util.scala:505:22]
reg uops_6_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_6_stale_pdst; // @[util.scala:505:22]
reg uops_6_exception; // @[util.scala:505:22]
reg [63:0] uops_6_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_6_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_6_mem_size; // @[util.scala:505:22]
reg uops_6_mem_signed; // @[util.scala:505:22]
reg uops_6_uses_ldq; // @[util.scala:505:22]
reg uops_6_uses_stq; // @[util.scala:505:22]
reg uops_6_is_unique; // @[util.scala:505:22]
reg uops_6_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_6_csr_cmd; // @[util.scala:505:22]
reg uops_6_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_6_ldst; // @[util.scala:505:22]
reg [5:0] uops_6_lrs1; // @[util.scala:505:22]
reg [5:0] uops_6_lrs2; // @[util.scala:505:22]
reg [5:0] uops_6_lrs3; // @[util.scala:505:22]
reg [1:0] uops_6_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_6_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_6_lrs2_rtype; // @[util.scala:505:22]
reg uops_6_frs3_en; // @[util.scala:505:22]
reg uops_6_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_6_fcn_op; // @[util.scala:505:22]
reg uops_6_fp_val; // @[util.scala:505:22]
reg [2:0] uops_6_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_6_fp_typ; // @[util.scala:505:22]
reg uops_6_xcpt_pf_if; // @[util.scala:505:22]
reg uops_6_xcpt_ae_if; // @[util.scala:505:22]
reg uops_6_xcpt_ma_if; // @[util.scala:505:22]
reg uops_6_bp_debug_if; // @[util.scala:505:22]
reg uops_6_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_6_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_6_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_7_inst; // @[util.scala:505:22]
reg [31:0] uops_7_debug_inst; // @[util.scala:505:22]
reg uops_7_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_7_debug_pc; // @[util.scala:505:22]
reg uops_7_iq_type_0; // @[util.scala:505:22]
reg uops_7_iq_type_1; // @[util.scala:505:22]
reg uops_7_iq_type_2; // @[util.scala:505:22]
reg uops_7_iq_type_3; // @[util.scala:505:22]
reg uops_7_fu_code_0; // @[util.scala:505:22]
reg uops_7_fu_code_1; // @[util.scala:505:22]
reg uops_7_fu_code_2; // @[util.scala:505:22]
reg uops_7_fu_code_3; // @[util.scala:505:22]
reg uops_7_fu_code_4; // @[util.scala:505:22]
reg uops_7_fu_code_5; // @[util.scala:505:22]
reg uops_7_fu_code_6; // @[util.scala:505:22]
reg uops_7_fu_code_7; // @[util.scala:505:22]
reg uops_7_fu_code_8; // @[util.scala:505:22]
reg uops_7_fu_code_9; // @[util.scala:505:22]
reg uops_7_iw_issued; // @[util.scala:505:22]
reg uops_7_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_7_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_7_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_7_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_7_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_7_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_7_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_7_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_7_br_mask; // @[util.scala:505:22]
reg [3:0] uops_7_br_tag; // @[util.scala:505:22]
reg [3:0] uops_7_br_type; // @[util.scala:505:22]
reg uops_7_is_sfb; // @[util.scala:505:22]
reg uops_7_is_fence; // @[util.scala:505:22]
reg uops_7_is_fencei; // @[util.scala:505:22]
reg uops_7_is_sfence; // @[util.scala:505:22]
reg uops_7_is_amo; // @[util.scala:505:22]
reg uops_7_is_eret; // @[util.scala:505:22]
reg uops_7_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_7_is_rocc; // @[util.scala:505:22]
reg uops_7_is_mov; // @[util.scala:505:22]
reg [4:0] uops_7_ftq_idx; // @[util.scala:505:22]
reg uops_7_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_7_pc_lob; // @[util.scala:505:22]
reg uops_7_taken; // @[util.scala:505:22]
reg uops_7_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_7_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_7_pimm; // @[util.scala:505:22]
reg [19:0] uops_7_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_7_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_7_op2_sel; // @[util.scala:505:22]
reg uops_7_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_7_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_7_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_7_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_7_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_7_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_7_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_7_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_7_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_7_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_7_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_7_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_7_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_7_fp_ctrl_div; // @[util.scala:505:22]
reg uops_7_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_7_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_7_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_7_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_7_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_7_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_7_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_7_pdst; // @[util.scala:505:22]
reg [6:0] uops_7_prs1; // @[util.scala:505:22]
reg [6:0] uops_7_prs2; // @[util.scala:505:22]
reg [6:0] uops_7_prs3; // @[util.scala:505:22]
reg [4:0] uops_7_ppred; // @[util.scala:505:22]
reg uops_7_prs1_busy; // @[util.scala:505:22]
reg uops_7_prs2_busy; // @[util.scala:505:22]
reg uops_7_prs3_busy; // @[util.scala:505:22]
reg uops_7_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_7_stale_pdst; // @[util.scala:505:22]
reg uops_7_exception; // @[util.scala:505:22]
reg [63:0] uops_7_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_7_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_7_mem_size; // @[util.scala:505:22]
reg uops_7_mem_signed; // @[util.scala:505:22]
reg uops_7_uses_ldq; // @[util.scala:505:22]
reg uops_7_uses_stq; // @[util.scala:505:22]
reg uops_7_is_unique; // @[util.scala:505:22]
reg uops_7_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_7_csr_cmd; // @[util.scala:505:22]
reg uops_7_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_7_ldst; // @[util.scala:505:22]
reg [5:0] uops_7_lrs1; // @[util.scala:505:22]
reg [5:0] uops_7_lrs2; // @[util.scala:505:22]
reg [5:0] uops_7_lrs3; // @[util.scala:505:22]
reg [1:0] uops_7_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_7_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_7_lrs2_rtype; // @[util.scala:505:22]
reg uops_7_frs3_en; // @[util.scala:505:22]
reg uops_7_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_7_fcn_op; // @[util.scala:505:22]
reg uops_7_fp_val; // @[util.scala:505:22]
reg [2:0] uops_7_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_7_fp_typ; // @[util.scala:505:22]
reg uops_7_xcpt_pf_if; // @[util.scala:505:22]
reg uops_7_xcpt_ae_if; // @[util.scala:505:22]
reg uops_7_xcpt_ma_if; // @[util.scala:505:22]
reg uops_7_bp_debug_if; // @[util.scala:505:22]
reg uops_7_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_7_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_7_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_8_inst; // @[util.scala:505:22]
reg [31:0] uops_8_debug_inst; // @[util.scala:505:22]
reg uops_8_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_8_debug_pc; // @[util.scala:505:22]
reg uops_8_iq_type_0; // @[util.scala:505:22]
reg uops_8_iq_type_1; // @[util.scala:505:22]
reg uops_8_iq_type_2; // @[util.scala:505:22]
reg uops_8_iq_type_3; // @[util.scala:505:22]
reg uops_8_fu_code_0; // @[util.scala:505:22]
reg uops_8_fu_code_1; // @[util.scala:505:22]
reg uops_8_fu_code_2; // @[util.scala:505:22]
reg uops_8_fu_code_3; // @[util.scala:505:22]
reg uops_8_fu_code_4; // @[util.scala:505:22]
reg uops_8_fu_code_5; // @[util.scala:505:22]
reg uops_8_fu_code_6; // @[util.scala:505:22]
reg uops_8_fu_code_7; // @[util.scala:505:22]
reg uops_8_fu_code_8; // @[util.scala:505:22]
reg uops_8_fu_code_9; // @[util.scala:505:22]
reg uops_8_iw_issued; // @[util.scala:505:22]
reg uops_8_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_8_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_8_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_8_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_8_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_8_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_8_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_8_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_8_br_mask; // @[util.scala:505:22]
reg [3:0] uops_8_br_tag; // @[util.scala:505:22]
reg [3:0] uops_8_br_type; // @[util.scala:505:22]
reg uops_8_is_sfb; // @[util.scala:505:22]
reg uops_8_is_fence; // @[util.scala:505:22]
reg uops_8_is_fencei; // @[util.scala:505:22]
reg uops_8_is_sfence; // @[util.scala:505:22]
reg uops_8_is_amo; // @[util.scala:505:22]
reg uops_8_is_eret; // @[util.scala:505:22]
reg uops_8_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_8_is_rocc; // @[util.scala:505:22]
reg uops_8_is_mov; // @[util.scala:505:22]
reg [4:0] uops_8_ftq_idx; // @[util.scala:505:22]
reg uops_8_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_8_pc_lob; // @[util.scala:505:22]
reg uops_8_taken; // @[util.scala:505:22]
reg uops_8_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_8_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_8_pimm; // @[util.scala:505:22]
reg [19:0] uops_8_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_8_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_8_op2_sel; // @[util.scala:505:22]
reg uops_8_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_8_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_8_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_8_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_8_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_8_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_8_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_8_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_8_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_8_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_8_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_8_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_8_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_8_fp_ctrl_div; // @[util.scala:505:22]
reg uops_8_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_8_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_8_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_8_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_8_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_8_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_8_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_8_pdst; // @[util.scala:505:22]
reg [6:0] uops_8_prs1; // @[util.scala:505:22]
reg [6:0] uops_8_prs2; // @[util.scala:505:22]
reg [6:0] uops_8_prs3; // @[util.scala:505:22]
reg [4:0] uops_8_ppred; // @[util.scala:505:22]
reg uops_8_prs1_busy; // @[util.scala:505:22]
reg uops_8_prs2_busy; // @[util.scala:505:22]
reg uops_8_prs3_busy; // @[util.scala:505:22]
reg uops_8_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_8_stale_pdst; // @[util.scala:505:22]
reg uops_8_exception; // @[util.scala:505:22]
reg [63:0] uops_8_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_8_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_8_mem_size; // @[util.scala:505:22]
reg uops_8_mem_signed; // @[util.scala:505:22]
reg uops_8_uses_ldq; // @[util.scala:505:22]
reg uops_8_uses_stq; // @[util.scala:505:22]
reg uops_8_is_unique; // @[util.scala:505:22]
reg uops_8_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_8_csr_cmd; // @[util.scala:505:22]
reg uops_8_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_8_ldst; // @[util.scala:505:22]
reg [5:0] uops_8_lrs1; // @[util.scala:505:22]
reg [5:0] uops_8_lrs2; // @[util.scala:505:22]
reg [5:0] uops_8_lrs3; // @[util.scala:505:22]
reg [1:0] uops_8_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_8_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_8_lrs2_rtype; // @[util.scala:505:22]
reg uops_8_frs3_en; // @[util.scala:505:22]
reg uops_8_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_8_fcn_op; // @[util.scala:505:22]
reg uops_8_fp_val; // @[util.scala:505:22]
reg [2:0] uops_8_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_8_fp_typ; // @[util.scala:505:22]
reg uops_8_xcpt_pf_if; // @[util.scala:505:22]
reg uops_8_xcpt_ae_if; // @[util.scala:505:22]
reg uops_8_xcpt_ma_if; // @[util.scala:505:22]
reg uops_8_bp_debug_if; // @[util.scala:505:22]
reg uops_8_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_8_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_8_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_9_inst; // @[util.scala:505:22]
reg [31:0] uops_9_debug_inst; // @[util.scala:505:22]
reg uops_9_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_9_debug_pc; // @[util.scala:505:22]
reg uops_9_iq_type_0; // @[util.scala:505:22]
reg uops_9_iq_type_1; // @[util.scala:505:22]
reg uops_9_iq_type_2; // @[util.scala:505:22]
reg uops_9_iq_type_3; // @[util.scala:505:22]
reg uops_9_fu_code_0; // @[util.scala:505:22]
reg uops_9_fu_code_1; // @[util.scala:505:22]
reg uops_9_fu_code_2; // @[util.scala:505:22]
reg uops_9_fu_code_3; // @[util.scala:505:22]
reg uops_9_fu_code_4; // @[util.scala:505:22]
reg uops_9_fu_code_5; // @[util.scala:505:22]
reg uops_9_fu_code_6; // @[util.scala:505:22]
reg uops_9_fu_code_7; // @[util.scala:505:22]
reg uops_9_fu_code_8; // @[util.scala:505:22]
reg uops_9_fu_code_9; // @[util.scala:505:22]
reg uops_9_iw_issued; // @[util.scala:505:22]
reg uops_9_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_9_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_9_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_9_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_9_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_9_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_9_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_9_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_9_br_mask; // @[util.scala:505:22]
reg [3:0] uops_9_br_tag; // @[util.scala:505:22]
reg [3:0] uops_9_br_type; // @[util.scala:505:22]
reg uops_9_is_sfb; // @[util.scala:505:22]
reg uops_9_is_fence; // @[util.scala:505:22]
reg uops_9_is_fencei; // @[util.scala:505:22]
reg uops_9_is_sfence; // @[util.scala:505:22]
reg uops_9_is_amo; // @[util.scala:505:22]
reg uops_9_is_eret; // @[util.scala:505:22]
reg uops_9_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_9_is_rocc; // @[util.scala:505:22]
reg uops_9_is_mov; // @[util.scala:505:22]
reg [4:0] uops_9_ftq_idx; // @[util.scala:505:22]
reg uops_9_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_9_pc_lob; // @[util.scala:505:22]
reg uops_9_taken; // @[util.scala:505:22]
reg uops_9_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_9_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_9_pimm; // @[util.scala:505:22]
reg [19:0] uops_9_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_9_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_9_op2_sel; // @[util.scala:505:22]
reg uops_9_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_9_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_9_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_9_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_9_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_9_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_9_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_9_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_9_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_9_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_9_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_9_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_9_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_9_fp_ctrl_div; // @[util.scala:505:22]
reg uops_9_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_9_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_9_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_9_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_9_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_9_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_9_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_9_pdst; // @[util.scala:505:22]
reg [6:0] uops_9_prs1; // @[util.scala:505:22]
reg [6:0] uops_9_prs2; // @[util.scala:505:22]
reg [6:0] uops_9_prs3; // @[util.scala:505:22]
reg [4:0] uops_9_ppred; // @[util.scala:505:22]
reg uops_9_prs1_busy; // @[util.scala:505:22]
reg uops_9_prs2_busy; // @[util.scala:505:22]
reg uops_9_prs3_busy; // @[util.scala:505:22]
reg uops_9_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_9_stale_pdst; // @[util.scala:505:22]
reg uops_9_exception; // @[util.scala:505:22]
reg [63:0] uops_9_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_9_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_9_mem_size; // @[util.scala:505:22]
reg uops_9_mem_signed; // @[util.scala:505:22]
reg uops_9_uses_ldq; // @[util.scala:505:22]
reg uops_9_uses_stq; // @[util.scala:505:22]
reg uops_9_is_unique; // @[util.scala:505:22]
reg uops_9_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_9_csr_cmd; // @[util.scala:505:22]
reg uops_9_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_9_ldst; // @[util.scala:505:22]
reg [5:0] uops_9_lrs1; // @[util.scala:505:22]
reg [5:0] uops_9_lrs2; // @[util.scala:505:22]
reg [5:0] uops_9_lrs3; // @[util.scala:505:22]
reg [1:0] uops_9_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_9_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_9_lrs2_rtype; // @[util.scala:505:22]
reg uops_9_frs3_en; // @[util.scala:505:22]
reg uops_9_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_9_fcn_op; // @[util.scala:505:22]
reg uops_9_fp_val; // @[util.scala:505:22]
reg [2:0] uops_9_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_9_fp_typ; // @[util.scala:505:22]
reg uops_9_xcpt_pf_if; // @[util.scala:505:22]
reg uops_9_xcpt_ae_if; // @[util.scala:505:22]
reg uops_9_xcpt_ma_if; // @[util.scala:505:22]
reg uops_9_bp_debug_if; // @[util.scala:505:22]
reg uops_9_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_9_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_9_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_10_inst; // @[util.scala:505:22]
reg [31:0] uops_10_debug_inst; // @[util.scala:505:22]
reg uops_10_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_10_debug_pc; // @[util.scala:505:22]
reg uops_10_iq_type_0; // @[util.scala:505:22]
reg uops_10_iq_type_1; // @[util.scala:505:22]
reg uops_10_iq_type_2; // @[util.scala:505:22]
reg uops_10_iq_type_3; // @[util.scala:505:22]
reg uops_10_fu_code_0; // @[util.scala:505:22]
reg uops_10_fu_code_1; // @[util.scala:505:22]
reg uops_10_fu_code_2; // @[util.scala:505:22]
reg uops_10_fu_code_3; // @[util.scala:505:22]
reg uops_10_fu_code_4; // @[util.scala:505:22]
reg uops_10_fu_code_5; // @[util.scala:505:22]
reg uops_10_fu_code_6; // @[util.scala:505:22]
reg uops_10_fu_code_7; // @[util.scala:505:22]
reg uops_10_fu_code_8; // @[util.scala:505:22]
reg uops_10_fu_code_9; // @[util.scala:505:22]
reg uops_10_iw_issued; // @[util.scala:505:22]
reg uops_10_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_10_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_10_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_10_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_10_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_10_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_10_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_10_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_10_br_mask; // @[util.scala:505:22]
reg [3:0] uops_10_br_tag; // @[util.scala:505:22]
reg [3:0] uops_10_br_type; // @[util.scala:505:22]
reg uops_10_is_sfb; // @[util.scala:505:22]
reg uops_10_is_fence; // @[util.scala:505:22]
reg uops_10_is_fencei; // @[util.scala:505:22]
reg uops_10_is_sfence; // @[util.scala:505:22]
reg uops_10_is_amo; // @[util.scala:505:22]
reg uops_10_is_eret; // @[util.scala:505:22]
reg uops_10_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_10_is_rocc; // @[util.scala:505:22]
reg uops_10_is_mov; // @[util.scala:505:22]
reg [4:0] uops_10_ftq_idx; // @[util.scala:505:22]
reg uops_10_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_10_pc_lob; // @[util.scala:505:22]
reg uops_10_taken; // @[util.scala:505:22]
reg uops_10_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_10_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_10_pimm; // @[util.scala:505:22]
reg [19:0] uops_10_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_10_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_10_op2_sel; // @[util.scala:505:22]
reg uops_10_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_10_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_10_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_10_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_10_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_10_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_10_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_10_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_10_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_10_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_10_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_10_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_10_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_10_fp_ctrl_div; // @[util.scala:505:22]
reg uops_10_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_10_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_10_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_10_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_10_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_10_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_10_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_10_pdst; // @[util.scala:505:22]
reg [6:0] uops_10_prs1; // @[util.scala:505:22]
reg [6:0] uops_10_prs2; // @[util.scala:505:22]
reg [6:0] uops_10_prs3; // @[util.scala:505:22]
reg [4:0] uops_10_ppred; // @[util.scala:505:22]
reg uops_10_prs1_busy; // @[util.scala:505:22]
reg uops_10_prs2_busy; // @[util.scala:505:22]
reg uops_10_prs3_busy; // @[util.scala:505:22]
reg uops_10_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_10_stale_pdst; // @[util.scala:505:22]
reg uops_10_exception; // @[util.scala:505:22]
reg [63:0] uops_10_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_10_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_10_mem_size; // @[util.scala:505:22]
reg uops_10_mem_signed; // @[util.scala:505:22]
reg uops_10_uses_ldq; // @[util.scala:505:22]
reg uops_10_uses_stq; // @[util.scala:505:22]
reg uops_10_is_unique; // @[util.scala:505:22]
reg uops_10_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_10_csr_cmd; // @[util.scala:505:22]
reg uops_10_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_10_ldst; // @[util.scala:505:22]
reg [5:0] uops_10_lrs1; // @[util.scala:505:22]
reg [5:0] uops_10_lrs2; // @[util.scala:505:22]
reg [5:0] uops_10_lrs3; // @[util.scala:505:22]
reg [1:0] uops_10_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_10_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_10_lrs2_rtype; // @[util.scala:505:22]
reg uops_10_frs3_en; // @[util.scala:505:22]
reg uops_10_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_10_fcn_op; // @[util.scala:505:22]
reg uops_10_fp_val; // @[util.scala:505:22]
reg [2:0] uops_10_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_10_fp_typ; // @[util.scala:505:22]
reg uops_10_xcpt_pf_if; // @[util.scala:505:22]
reg uops_10_xcpt_ae_if; // @[util.scala:505:22]
reg uops_10_xcpt_ma_if; // @[util.scala:505:22]
reg uops_10_bp_debug_if; // @[util.scala:505:22]
reg uops_10_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_10_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_10_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_11_inst; // @[util.scala:505:22]
reg [31:0] uops_11_debug_inst; // @[util.scala:505:22]
reg uops_11_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_11_debug_pc; // @[util.scala:505:22]
reg uops_11_iq_type_0; // @[util.scala:505:22]
reg uops_11_iq_type_1; // @[util.scala:505:22]
reg uops_11_iq_type_2; // @[util.scala:505:22]
reg uops_11_iq_type_3; // @[util.scala:505:22]
reg uops_11_fu_code_0; // @[util.scala:505:22]
reg uops_11_fu_code_1; // @[util.scala:505:22]
reg uops_11_fu_code_2; // @[util.scala:505:22]
reg uops_11_fu_code_3; // @[util.scala:505:22]
reg uops_11_fu_code_4; // @[util.scala:505:22]
reg uops_11_fu_code_5; // @[util.scala:505:22]
reg uops_11_fu_code_6; // @[util.scala:505:22]
reg uops_11_fu_code_7; // @[util.scala:505:22]
reg uops_11_fu_code_8; // @[util.scala:505:22]
reg uops_11_fu_code_9; // @[util.scala:505:22]
reg uops_11_iw_issued; // @[util.scala:505:22]
reg uops_11_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_11_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_11_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_11_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_11_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_11_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_11_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_11_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_11_br_mask; // @[util.scala:505:22]
reg [3:0] uops_11_br_tag; // @[util.scala:505:22]
reg [3:0] uops_11_br_type; // @[util.scala:505:22]
reg uops_11_is_sfb; // @[util.scala:505:22]
reg uops_11_is_fence; // @[util.scala:505:22]
reg uops_11_is_fencei; // @[util.scala:505:22]
reg uops_11_is_sfence; // @[util.scala:505:22]
reg uops_11_is_amo; // @[util.scala:505:22]
reg uops_11_is_eret; // @[util.scala:505:22]
reg uops_11_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_11_is_rocc; // @[util.scala:505:22]
reg uops_11_is_mov; // @[util.scala:505:22]
reg [4:0] uops_11_ftq_idx; // @[util.scala:505:22]
reg uops_11_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_11_pc_lob; // @[util.scala:505:22]
reg uops_11_taken; // @[util.scala:505:22]
reg uops_11_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_11_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_11_pimm; // @[util.scala:505:22]
reg [19:0] uops_11_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_11_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_11_op2_sel; // @[util.scala:505:22]
reg uops_11_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_11_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_11_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_11_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_11_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_11_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_11_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_11_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_11_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_11_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_11_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_11_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_11_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_11_fp_ctrl_div; // @[util.scala:505:22]
reg uops_11_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_11_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_11_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_11_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_11_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_11_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_11_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_11_pdst; // @[util.scala:505:22]
reg [6:0] uops_11_prs1; // @[util.scala:505:22]
reg [6:0] uops_11_prs2; // @[util.scala:505:22]
reg [6:0] uops_11_prs3; // @[util.scala:505:22]
reg [4:0] uops_11_ppred; // @[util.scala:505:22]
reg uops_11_prs1_busy; // @[util.scala:505:22]
reg uops_11_prs2_busy; // @[util.scala:505:22]
reg uops_11_prs3_busy; // @[util.scala:505:22]
reg uops_11_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_11_stale_pdst; // @[util.scala:505:22]
reg uops_11_exception; // @[util.scala:505:22]
reg [63:0] uops_11_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_11_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_11_mem_size; // @[util.scala:505:22]
reg uops_11_mem_signed; // @[util.scala:505:22]
reg uops_11_uses_ldq; // @[util.scala:505:22]
reg uops_11_uses_stq; // @[util.scala:505:22]
reg uops_11_is_unique; // @[util.scala:505:22]
reg uops_11_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_11_csr_cmd; // @[util.scala:505:22]
reg uops_11_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_11_ldst; // @[util.scala:505:22]
reg [5:0] uops_11_lrs1; // @[util.scala:505:22]
reg [5:0] uops_11_lrs2; // @[util.scala:505:22]
reg [5:0] uops_11_lrs3; // @[util.scala:505:22]
reg [1:0] uops_11_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_11_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_11_lrs2_rtype; // @[util.scala:505:22]
reg uops_11_frs3_en; // @[util.scala:505:22]
reg uops_11_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_11_fcn_op; // @[util.scala:505:22]
reg uops_11_fp_val; // @[util.scala:505:22]
reg [2:0] uops_11_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_11_fp_typ; // @[util.scala:505:22]
reg uops_11_xcpt_pf_if; // @[util.scala:505:22]
reg uops_11_xcpt_ae_if; // @[util.scala:505:22]
reg uops_11_xcpt_ma_if; // @[util.scala:505:22]
reg uops_11_bp_debug_if; // @[util.scala:505:22]
reg uops_11_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_11_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_11_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_12_inst; // @[util.scala:505:22]
reg [31:0] uops_12_debug_inst; // @[util.scala:505:22]
reg uops_12_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_12_debug_pc; // @[util.scala:505:22]
reg uops_12_iq_type_0; // @[util.scala:505:22]
reg uops_12_iq_type_1; // @[util.scala:505:22]
reg uops_12_iq_type_2; // @[util.scala:505:22]
reg uops_12_iq_type_3; // @[util.scala:505:22]
reg uops_12_fu_code_0; // @[util.scala:505:22]
reg uops_12_fu_code_1; // @[util.scala:505:22]
reg uops_12_fu_code_2; // @[util.scala:505:22]
reg uops_12_fu_code_3; // @[util.scala:505:22]
reg uops_12_fu_code_4; // @[util.scala:505:22]
reg uops_12_fu_code_5; // @[util.scala:505:22]
reg uops_12_fu_code_6; // @[util.scala:505:22]
reg uops_12_fu_code_7; // @[util.scala:505:22]
reg uops_12_fu_code_8; // @[util.scala:505:22]
reg uops_12_fu_code_9; // @[util.scala:505:22]
reg uops_12_iw_issued; // @[util.scala:505:22]
reg uops_12_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_12_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_12_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_12_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_12_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_12_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_12_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_12_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_12_br_mask; // @[util.scala:505:22]
reg [3:0] uops_12_br_tag; // @[util.scala:505:22]
reg [3:0] uops_12_br_type; // @[util.scala:505:22]
reg uops_12_is_sfb; // @[util.scala:505:22]
reg uops_12_is_fence; // @[util.scala:505:22]
reg uops_12_is_fencei; // @[util.scala:505:22]
reg uops_12_is_sfence; // @[util.scala:505:22]
reg uops_12_is_amo; // @[util.scala:505:22]
reg uops_12_is_eret; // @[util.scala:505:22]
reg uops_12_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_12_is_rocc; // @[util.scala:505:22]
reg uops_12_is_mov; // @[util.scala:505:22]
reg [4:0] uops_12_ftq_idx; // @[util.scala:505:22]
reg uops_12_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_12_pc_lob; // @[util.scala:505:22]
reg uops_12_taken; // @[util.scala:505:22]
reg uops_12_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_12_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_12_pimm; // @[util.scala:505:22]
reg [19:0] uops_12_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_12_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_12_op2_sel; // @[util.scala:505:22]
reg uops_12_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_12_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_12_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_12_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_12_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_12_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_12_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_12_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_12_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_12_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_12_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_12_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_12_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_12_fp_ctrl_div; // @[util.scala:505:22]
reg uops_12_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_12_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_12_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_12_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_12_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_12_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_12_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_12_pdst; // @[util.scala:505:22]
reg [6:0] uops_12_prs1; // @[util.scala:505:22]
reg [6:0] uops_12_prs2; // @[util.scala:505:22]
reg [6:0] uops_12_prs3; // @[util.scala:505:22]
reg [4:0] uops_12_ppred; // @[util.scala:505:22]
reg uops_12_prs1_busy; // @[util.scala:505:22]
reg uops_12_prs2_busy; // @[util.scala:505:22]
reg uops_12_prs3_busy; // @[util.scala:505:22]
reg uops_12_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_12_stale_pdst; // @[util.scala:505:22]
reg uops_12_exception; // @[util.scala:505:22]
reg [63:0] uops_12_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_12_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_12_mem_size; // @[util.scala:505:22]
reg uops_12_mem_signed; // @[util.scala:505:22]
reg uops_12_uses_ldq; // @[util.scala:505:22]
reg uops_12_uses_stq; // @[util.scala:505:22]
reg uops_12_is_unique; // @[util.scala:505:22]
reg uops_12_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_12_csr_cmd; // @[util.scala:505:22]
reg uops_12_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_12_ldst; // @[util.scala:505:22]
reg [5:0] uops_12_lrs1; // @[util.scala:505:22]
reg [5:0] uops_12_lrs2; // @[util.scala:505:22]
reg [5:0] uops_12_lrs3; // @[util.scala:505:22]
reg [1:0] uops_12_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_12_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_12_lrs2_rtype; // @[util.scala:505:22]
reg uops_12_frs3_en; // @[util.scala:505:22]
reg uops_12_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_12_fcn_op; // @[util.scala:505:22]
reg uops_12_fp_val; // @[util.scala:505:22]
reg [2:0] uops_12_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_12_fp_typ; // @[util.scala:505:22]
reg uops_12_xcpt_pf_if; // @[util.scala:505:22]
reg uops_12_xcpt_ae_if; // @[util.scala:505:22]
reg uops_12_xcpt_ma_if; // @[util.scala:505:22]
reg uops_12_bp_debug_if; // @[util.scala:505:22]
reg uops_12_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_12_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_12_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_13_inst; // @[util.scala:505:22]
reg [31:0] uops_13_debug_inst; // @[util.scala:505:22]
reg uops_13_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_13_debug_pc; // @[util.scala:505:22]
reg uops_13_iq_type_0; // @[util.scala:505:22]
reg uops_13_iq_type_1; // @[util.scala:505:22]
reg uops_13_iq_type_2; // @[util.scala:505:22]
reg uops_13_iq_type_3; // @[util.scala:505:22]
reg uops_13_fu_code_0; // @[util.scala:505:22]
reg uops_13_fu_code_1; // @[util.scala:505:22]
reg uops_13_fu_code_2; // @[util.scala:505:22]
reg uops_13_fu_code_3; // @[util.scala:505:22]
reg uops_13_fu_code_4; // @[util.scala:505:22]
reg uops_13_fu_code_5; // @[util.scala:505:22]
reg uops_13_fu_code_6; // @[util.scala:505:22]
reg uops_13_fu_code_7; // @[util.scala:505:22]
reg uops_13_fu_code_8; // @[util.scala:505:22]
reg uops_13_fu_code_9; // @[util.scala:505:22]
reg uops_13_iw_issued; // @[util.scala:505:22]
reg uops_13_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_13_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_13_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_13_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_13_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_13_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_13_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_13_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_13_br_mask; // @[util.scala:505:22]
reg [3:0] uops_13_br_tag; // @[util.scala:505:22]
reg [3:0] uops_13_br_type; // @[util.scala:505:22]
reg uops_13_is_sfb; // @[util.scala:505:22]
reg uops_13_is_fence; // @[util.scala:505:22]
reg uops_13_is_fencei; // @[util.scala:505:22]
reg uops_13_is_sfence; // @[util.scala:505:22]
reg uops_13_is_amo; // @[util.scala:505:22]
reg uops_13_is_eret; // @[util.scala:505:22]
reg uops_13_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_13_is_rocc; // @[util.scala:505:22]
reg uops_13_is_mov; // @[util.scala:505:22]
reg [4:0] uops_13_ftq_idx; // @[util.scala:505:22]
reg uops_13_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_13_pc_lob; // @[util.scala:505:22]
reg uops_13_taken; // @[util.scala:505:22]
reg uops_13_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_13_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_13_pimm; // @[util.scala:505:22]
reg [19:0] uops_13_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_13_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_13_op2_sel; // @[util.scala:505:22]
reg uops_13_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_13_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_13_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_13_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_13_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_13_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_13_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_13_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_13_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_13_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_13_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_13_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_13_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_13_fp_ctrl_div; // @[util.scala:505:22]
reg uops_13_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_13_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_13_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_13_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_13_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_13_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_13_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_13_pdst; // @[util.scala:505:22]
reg [6:0] uops_13_prs1; // @[util.scala:505:22]
reg [6:0] uops_13_prs2; // @[util.scala:505:22]
reg [6:0] uops_13_prs3; // @[util.scala:505:22]
reg [4:0] uops_13_ppred; // @[util.scala:505:22]
reg uops_13_prs1_busy; // @[util.scala:505:22]
reg uops_13_prs2_busy; // @[util.scala:505:22]
reg uops_13_prs3_busy; // @[util.scala:505:22]
reg uops_13_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_13_stale_pdst; // @[util.scala:505:22]
reg uops_13_exception; // @[util.scala:505:22]
reg [63:0] uops_13_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_13_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_13_mem_size; // @[util.scala:505:22]
reg uops_13_mem_signed; // @[util.scala:505:22]
reg uops_13_uses_ldq; // @[util.scala:505:22]
reg uops_13_uses_stq; // @[util.scala:505:22]
reg uops_13_is_unique; // @[util.scala:505:22]
reg uops_13_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_13_csr_cmd; // @[util.scala:505:22]
reg uops_13_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_13_ldst; // @[util.scala:505:22]
reg [5:0] uops_13_lrs1; // @[util.scala:505:22]
reg [5:0] uops_13_lrs2; // @[util.scala:505:22]
reg [5:0] uops_13_lrs3; // @[util.scala:505:22]
reg [1:0] uops_13_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_13_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_13_lrs2_rtype; // @[util.scala:505:22]
reg uops_13_frs3_en; // @[util.scala:505:22]
reg uops_13_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_13_fcn_op; // @[util.scala:505:22]
reg uops_13_fp_val; // @[util.scala:505:22]
reg [2:0] uops_13_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_13_fp_typ; // @[util.scala:505:22]
reg uops_13_xcpt_pf_if; // @[util.scala:505:22]
reg uops_13_xcpt_ae_if; // @[util.scala:505:22]
reg uops_13_xcpt_ma_if; // @[util.scala:505:22]
reg uops_13_bp_debug_if; // @[util.scala:505:22]
reg uops_13_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_13_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_13_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_14_inst; // @[util.scala:505:22]
reg [31:0] uops_14_debug_inst; // @[util.scala:505:22]
reg uops_14_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_14_debug_pc; // @[util.scala:505:22]
reg uops_14_iq_type_0; // @[util.scala:505:22]
reg uops_14_iq_type_1; // @[util.scala:505:22]
reg uops_14_iq_type_2; // @[util.scala:505:22]
reg uops_14_iq_type_3; // @[util.scala:505:22]
reg uops_14_fu_code_0; // @[util.scala:505:22]
reg uops_14_fu_code_1; // @[util.scala:505:22]
reg uops_14_fu_code_2; // @[util.scala:505:22]
reg uops_14_fu_code_3; // @[util.scala:505:22]
reg uops_14_fu_code_4; // @[util.scala:505:22]
reg uops_14_fu_code_5; // @[util.scala:505:22]
reg uops_14_fu_code_6; // @[util.scala:505:22]
reg uops_14_fu_code_7; // @[util.scala:505:22]
reg uops_14_fu_code_8; // @[util.scala:505:22]
reg uops_14_fu_code_9; // @[util.scala:505:22]
reg uops_14_iw_issued; // @[util.scala:505:22]
reg uops_14_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_14_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [2:0] uops_14_iw_p1_speculative_child; // @[util.scala:505:22]
reg [2:0] uops_14_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_14_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_14_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_14_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [2:0] uops_14_dis_col_sel; // @[util.scala:505:22]
reg [15:0] uops_14_br_mask; // @[util.scala:505:22]
reg [3:0] uops_14_br_tag; // @[util.scala:505:22]
reg [3:0] uops_14_br_type; // @[util.scala:505:22]
reg uops_14_is_sfb; // @[util.scala:505:22]
reg uops_14_is_fence; // @[util.scala:505:22]
reg uops_14_is_fencei; // @[util.scala:505:22]
reg uops_14_is_sfence; // @[util.scala:505:22]
reg uops_14_is_amo; // @[util.scala:505:22]
reg uops_14_is_eret; // @[util.scala:505:22]
reg uops_14_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_14_is_rocc; // @[util.scala:505:22]
reg uops_14_is_mov; // @[util.scala:505:22]
reg [4:0] uops_14_ftq_idx; // @[util.scala:505:22]
reg uops_14_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_14_pc_lob; // @[util.scala:505:22]
reg uops_14_taken; // @[util.scala:505:22]
reg uops_14_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_14_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_14_pimm; // @[util.scala:505:22]
reg [19:0] uops_14_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_14_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_14_op2_sel; // @[util.scala:505:22]
reg uops_14_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_14_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_14_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_14_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_14_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_14_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_14_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_14_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_14_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_14_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_14_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_14_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_14_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_14_fp_ctrl_div; // @[util.scala:505:22]
reg uops_14_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_14_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_14_fp_ctrl_vec; // @[util.scala:505:22]
reg [6:0] uops_14_rob_idx; // @[util.scala:505:22]
reg [4:0] uops_14_ldq_idx; // @[util.scala:505:22]
reg [4:0] uops_14_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_14_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_14_pdst; // @[util.scala:505:22]
reg [6:0] uops_14_prs1; // @[util.scala:505:22]
reg [6:0] uops_14_prs2; // @[util.scala:505:22]
reg [6:0] uops_14_prs3; // @[util.scala:505:22]
reg [4:0] uops_14_ppred; // @[util.scala:505:22]
reg uops_14_prs1_busy; // @[util.scala:505:22]
reg uops_14_prs2_busy; // @[util.scala:505:22]
reg uops_14_prs3_busy; // @[util.scala:505:22]
reg uops_14_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_14_stale_pdst; // @[util.scala:505:22]
reg uops_14_exception; // @[util.scala:505:22]
reg [63:0] uops_14_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_14_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_14_mem_size; // @[util.scala:505:22]
reg uops_14_mem_signed; // @[util.scala:505:22]
reg uops_14_uses_ldq; // @[util.scala:505:22]
reg uops_14_uses_stq; // @[util.scala:505:22]
reg uops_14_is_unique; // @[util.scala:505:22]
reg uops_14_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_14_csr_cmd; // @[util.scala:505:22]
reg uops_14_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_14_ldst; // @[util.scala:505:22]
reg [5:0] uops_14_lrs1; // @[util.scala:505:22]
reg [5:0] uops_14_lrs2; // @[util.scala:505:22]
reg [5:0] uops_14_lrs3; // @[util.scala:505:22]
reg [1:0] uops_14_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_14_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_14_lrs2_rtype; // @[util.scala:505:22]
reg uops_14_frs3_en; // @[util.scala:505:22]
reg uops_14_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_14_fcn_op; // @[util.scala:505:22]
reg uops_14_fp_val; // @[util.scala:505:22]
reg [2:0] uops_14_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_14_fp_typ; // @[util.scala:505:22]
reg uops_14_xcpt_pf_if; // @[util.scala:505:22]
reg uops_14_xcpt_ae_if; // @[util.scala:505:22]
reg uops_14_xcpt_ma_if; // @[util.scala:505:22]
reg uops_14_bp_debug_if; // @[util.scala:505:22]
reg uops_14_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_14_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_14_debug_tsrc; // @[util.scala:505:22]
reg [3:0] enq_ptr_value; // @[Counter.scala:61:40]
reg [3:0] deq_ptr_value; // @[Counter.scala:61:40]
reg maybe_full; // @[util.scala:509:29]
wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40]
wire _io_empty_T = ~maybe_full; // @[util.scala:509:29, :512:30]
assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:511:35, :512:{27,30}]
assign io_empty_0 = _io_empty_T_1; // @[util.scala:458:7, :512:27]
wire full = ptr_match & maybe_full; // @[util.scala:509:29, :511:35, :513:26]
wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35]
wire [15:0] _do_enq_T_1 = io_brupdate_b1_mispredict_mask_0 & io_enq_bits_uop_br_mask_0; // @[util.scala:126:51, :458:7]
wire _do_enq_T_2 = |_do_enq_T_1; // @[util.scala:126:{51,59}]
wire _do_enq_T_3 = _do_enq_T_2; // @[util.scala:61:61, :126:59]
wire _do_enq_T_4 = ~_do_enq_T_3; // @[util.scala:61:61, :514:42]
wire _do_enq_T_5 = _do_enq_T & _do_enq_T_4; // @[Decoupled.scala:51:35]
wire _do_enq_T_6 = io_flush_0 & io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :514:113]
wire _do_enq_T_7 = ~_do_enq_T_6; // @[util.scala:514:{102,113}]
wire _do_enq_T_8 = _do_enq_T_5 & _do_enq_T_7; // @[util.scala:514:{39,99,102}]
wire do_enq = _do_enq_T_8; // @[util.scala:514:{26,99}]
wire [15:0] _GEN = {{valids_0}, {valids_14}, {valids_13}, {valids_12}, {valids_11}, {valids_10}, {valids_9}, {valids_8}, {valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:504:26, :515:44]
wire _GEN_0 = _GEN[deq_ptr_value]; // @[Counter.scala:61:40]
wire _do_deq_T = ~_GEN_0; // @[util.scala:515:44]
wire _do_deq_T_1 = io_deq_ready_0 | _do_deq_T; // @[util.scala:458:7, :515:{41,44}]
wire _do_deq_T_2 = ~io_empty_0; // @[util.scala:458:7, :515:71]
wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:515:{41,68,71}]
wire do_deq = _do_deq_T_3; // @[util.scala:515:{26,68}]
wire [15:0] _valids_0_T = io_brupdate_b1_mispredict_mask_0 & uops_0_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_0_T_1 = |_valids_0_T; // @[util.scala:126:{51,59}]
wire _valids_0_T_2 = _valids_0_T_1; // @[util.scala:61:61, :126:59]
wire _valids_0_T_3 = ~_valids_0_T_2; // @[util.scala:61:61, :520:34]
wire _valids_0_T_4 = valids_0 & _valids_0_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_0_T_5 = io_flush_0 & uops_0_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_0_T_6 = ~_valids_0_T_5; // @[util.scala:520:{83,94}]
wire _valids_0_T_7 = _valids_0_T_4 & _valids_0_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_0_br_mask_T_1 = uops_0_br_mask & _uops_0_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_1_T = io_brupdate_b1_mispredict_mask_0 & uops_1_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_1_T_1 = |_valids_1_T; // @[util.scala:126:{51,59}]
wire _valids_1_T_2 = _valids_1_T_1; // @[util.scala:61:61, :126:59]
wire _valids_1_T_3 = ~_valids_1_T_2; // @[util.scala:61:61, :520:34]
wire _valids_1_T_4 = valids_1 & _valids_1_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_1_T_5 = io_flush_0 & uops_1_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_1_T_6 = ~_valids_1_T_5; // @[util.scala:520:{83,94}]
wire _valids_1_T_7 = _valids_1_T_4 & _valids_1_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_1_br_mask_T_1 = uops_1_br_mask & _uops_1_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_2_T = io_brupdate_b1_mispredict_mask_0 & uops_2_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_2_T_1 = |_valids_2_T; // @[util.scala:126:{51,59}]
wire _valids_2_T_2 = _valids_2_T_1; // @[util.scala:61:61, :126:59]
wire _valids_2_T_3 = ~_valids_2_T_2; // @[util.scala:61:61, :520:34]
wire _valids_2_T_4 = valids_2 & _valids_2_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_2_T_5 = io_flush_0 & uops_2_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_2_T_6 = ~_valids_2_T_5; // @[util.scala:520:{83,94}]
wire _valids_2_T_7 = _valids_2_T_4 & _valids_2_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_2_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_2_br_mask_T_1 = uops_2_br_mask & _uops_2_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_3_T = io_brupdate_b1_mispredict_mask_0 & uops_3_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_3_T_1 = |_valids_3_T; // @[util.scala:126:{51,59}]
wire _valids_3_T_2 = _valids_3_T_1; // @[util.scala:61:61, :126:59]
wire _valids_3_T_3 = ~_valids_3_T_2; // @[util.scala:61:61, :520:34]
wire _valids_3_T_4 = valids_3 & _valids_3_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_3_T_5 = io_flush_0 & uops_3_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_3_T_6 = ~_valids_3_T_5; // @[util.scala:520:{83,94}]
wire _valids_3_T_7 = _valids_3_T_4 & _valids_3_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_3_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_3_br_mask_T_1 = uops_3_br_mask & _uops_3_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_4_T = io_brupdate_b1_mispredict_mask_0 & uops_4_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_4_T_1 = |_valids_4_T; // @[util.scala:126:{51,59}]
wire _valids_4_T_2 = _valids_4_T_1; // @[util.scala:61:61, :126:59]
wire _valids_4_T_3 = ~_valids_4_T_2; // @[util.scala:61:61, :520:34]
wire _valids_4_T_4 = valids_4 & _valids_4_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_4_T_5 = io_flush_0 & uops_4_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_4_T_6 = ~_valids_4_T_5; // @[util.scala:520:{83,94}]
wire _valids_4_T_7 = _valids_4_T_4 & _valids_4_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_4_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_4_br_mask_T_1 = uops_4_br_mask & _uops_4_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_5_T = io_brupdate_b1_mispredict_mask_0 & uops_5_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_5_T_1 = |_valids_5_T; // @[util.scala:126:{51,59}]
wire _valids_5_T_2 = _valids_5_T_1; // @[util.scala:61:61, :126:59]
wire _valids_5_T_3 = ~_valids_5_T_2; // @[util.scala:61:61, :520:34]
wire _valids_5_T_4 = valids_5 & _valids_5_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_5_T_5 = io_flush_0 & uops_5_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_5_T_6 = ~_valids_5_T_5; // @[util.scala:520:{83,94}]
wire _valids_5_T_7 = _valids_5_T_4 & _valids_5_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_5_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_5_br_mask_T_1 = uops_5_br_mask & _uops_5_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_6_T = io_brupdate_b1_mispredict_mask_0 & uops_6_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_6_T_1 = |_valids_6_T; // @[util.scala:126:{51,59}]
wire _valids_6_T_2 = _valids_6_T_1; // @[util.scala:61:61, :126:59]
wire _valids_6_T_3 = ~_valids_6_T_2; // @[util.scala:61:61, :520:34]
wire _valids_6_T_4 = valids_6 & _valids_6_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_6_T_5 = io_flush_0 & uops_6_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_6_T_6 = ~_valids_6_T_5; // @[util.scala:520:{83,94}]
wire _valids_6_T_7 = _valids_6_T_4 & _valids_6_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_6_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_6_br_mask_T_1 = uops_6_br_mask & _uops_6_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_7_T = io_brupdate_b1_mispredict_mask_0 & uops_7_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_7_T_1 = |_valids_7_T; // @[util.scala:126:{51,59}]
wire _valids_7_T_2 = _valids_7_T_1; // @[util.scala:61:61, :126:59]
wire _valids_7_T_3 = ~_valids_7_T_2; // @[util.scala:61:61, :520:34]
wire _valids_7_T_4 = valids_7 & _valids_7_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_7_T_5 = io_flush_0 & uops_7_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_7_T_6 = ~_valids_7_T_5; // @[util.scala:520:{83,94}]
wire _valids_7_T_7 = _valids_7_T_4 & _valids_7_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_7_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_7_br_mask_T_1 = uops_7_br_mask & _uops_7_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_8_T = io_brupdate_b1_mispredict_mask_0 & uops_8_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_8_T_1 = |_valids_8_T; // @[util.scala:126:{51,59}]
wire _valids_8_T_2 = _valids_8_T_1; // @[util.scala:61:61, :126:59]
wire _valids_8_T_3 = ~_valids_8_T_2; // @[util.scala:61:61, :520:34]
wire _valids_8_T_4 = valids_8 & _valids_8_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_8_T_5 = io_flush_0 & uops_8_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_8_T_6 = ~_valids_8_T_5; // @[util.scala:520:{83,94}]
wire _valids_8_T_7 = _valids_8_T_4 & _valids_8_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_8_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_8_br_mask_T_1 = uops_8_br_mask & _uops_8_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_9_T = io_brupdate_b1_mispredict_mask_0 & uops_9_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_9_T_1 = |_valids_9_T; // @[util.scala:126:{51,59}]
wire _valids_9_T_2 = _valids_9_T_1; // @[util.scala:61:61, :126:59]
wire _valids_9_T_3 = ~_valids_9_T_2; // @[util.scala:61:61, :520:34]
wire _valids_9_T_4 = valids_9 & _valids_9_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_9_T_5 = io_flush_0 & uops_9_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_9_T_6 = ~_valids_9_T_5; // @[util.scala:520:{83,94}]
wire _valids_9_T_7 = _valids_9_T_4 & _valids_9_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_9_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_9_br_mask_T_1 = uops_9_br_mask & _uops_9_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_10_T = io_brupdate_b1_mispredict_mask_0 & uops_10_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_10_T_1 = |_valids_10_T; // @[util.scala:126:{51,59}]
wire _valids_10_T_2 = _valids_10_T_1; // @[util.scala:61:61, :126:59]
wire _valids_10_T_3 = ~_valids_10_T_2; // @[util.scala:61:61, :520:34]
wire _valids_10_T_4 = valids_10 & _valids_10_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_10_T_5 = io_flush_0 & uops_10_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_10_T_6 = ~_valids_10_T_5; // @[util.scala:520:{83,94}]
wire _valids_10_T_7 = _valids_10_T_4 & _valids_10_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_10_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_10_br_mask_T_1 = uops_10_br_mask & _uops_10_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_11_T = io_brupdate_b1_mispredict_mask_0 & uops_11_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_11_T_1 = |_valids_11_T; // @[util.scala:126:{51,59}]
wire _valids_11_T_2 = _valids_11_T_1; // @[util.scala:61:61, :126:59]
wire _valids_11_T_3 = ~_valids_11_T_2; // @[util.scala:61:61, :520:34]
wire _valids_11_T_4 = valids_11 & _valids_11_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_11_T_5 = io_flush_0 & uops_11_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_11_T_6 = ~_valids_11_T_5; // @[util.scala:520:{83,94}]
wire _valids_11_T_7 = _valids_11_T_4 & _valids_11_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_11_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_11_br_mask_T_1 = uops_11_br_mask & _uops_11_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_12_T = io_brupdate_b1_mispredict_mask_0 & uops_12_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_12_T_1 = |_valids_12_T; // @[util.scala:126:{51,59}]
wire _valids_12_T_2 = _valids_12_T_1; // @[util.scala:61:61, :126:59]
wire _valids_12_T_3 = ~_valids_12_T_2; // @[util.scala:61:61, :520:34]
wire _valids_12_T_4 = valids_12 & _valids_12_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_12_T_5 = io_flush_0 & uops_12_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_12_T_6 = ~_valids_12_T_5; // @[util.scala:520:{83,94}]
wire _valids_12_T_7 = _valids_12_T_4 & _valids_12_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_12_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_12_br_mask_T_1 = uops_12_br_mask & _uops_12_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_13_T = io_brupdate_b1_mispredict_mask_0 & uops_13_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_13_T_1 = |_valids_13_T; // @[util.scala:126:{51,59}]
wire _valids_13_T_2 = _valids_13_T_1; // @[util.scala:61:61, :126:59]
wire _valids_13_T_3 = ~_valids_13_T_2; // @[util.scala:61:61, :520:34]
wire _valids_13_T_4 = valids_13 & _valids_13_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_13_T_5 = io_flush_0 & uops_13_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_13_T_6 = ~_valids_13_T_5; // @[util.scala:520:{83,94}]
wire _valids_13_T_7 = _valids_13_T_4 & _valids_13_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_13_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_13_br_mask_T_1 = uops_13_br_mask & _uops_13_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [15:0] _valids_14_T = io_brupdate_b1_mispredict_mask_0 & uops_14_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_14_T_1 = |_valids_14_T; // @[util.scala:126:{51,59}]
wire _valids_14_T_2 = _valids_14_T_1; // @[util.scala:61:61, :126:59]
wire _valids_14_T_3 = ~_valids_14_T_2; // @[util.scala:61:61, :520:34]
wire _valids_14_T_4 = valids_14 & _valids_14_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_14_T_5 = io_flush_0 & uops_14_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_14_T_6 = ~_valids_14_T_5; // @[util.scala:520:{83,94}]
wire _valids_14_T_7 = _valids_14_T_4 & _valids_14_T_6; // @[util.scala:520:{31,80,83}]
wire [15:0] _uops_14_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [15:0] _uops_14_br_mask_T_1 = uops_14_br_mask & _uops_14_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire wrap = enq_ptr_value == 4'hE; // @[Counter.scala:61:40, :73:24]
wire [15:0] _uops_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23, :458:7]
wire [15:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0 & _uops_br_mask_T; // @[util.scala:93:{25,27}, :458:7]
wire [4:0] _GEN_1 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24]
wire [4:0] _value_T = _GEN_1 + 5'h1; // @[Counter.scala:77:24]
wire [3:0] _value_T_1 = _value_T[3:0]; // @[Counter.scala:77:24]
wire wrap_1 = deq_ptr_value == 4'hE; // @[Counter.scala:61:40, :73:24]
wire [4:0] _GEN_2 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24]
wire [4:0] _value_T_2 = _GEN_2 + 5'h1; // @[Counter.scala:77:24]
wire [3:0] _value_T_3 = _value_T_2[3:0]; // @[Counter.scala:77:24]
assign _io_enq_ready_T = ~full; // @[util.scala:513:26, :543:21]
assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:458:7, :543:21]
assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_addr_0 = out_addr; // @[util.scala:458:7, :545:19]
assign io_deq_bits_data_0 = out_data; // @[util.scala:458:7, :545:19]
assign io_deq_bits_is_hella_0 = out_is_hella; // @[util.scala:458:7, :545:19]
assign io_deq_bits_tag_match_0 = out_tag_match; // @[util.scala:458:7, :545:19]
assign io_deq_bits_old_meta_coh_state_0 = out_old_meta_coh_state; // @[util.scala:458:7, :545:19]
assign io_deq_bits_old_meta_tag_0 = out_old_meta_tag; // @[util.scala:458:7, :545:19]
assign io_deq_bits_way_en_0 = out_way_en; // @[util.scala:458:7, :545:19]
assign io_deq_bits_sdq_id_0 = out_sdq_id; // @[util.scala:458:7, :545:19]
wire [15:0][31:0] _GEN_3 = {{uops_0_inst}, {uops_14_inst}, {uops_13_inst}, {uops_12_inst}, {uops_11_inst}, {uops_10_inst}, {uops_9_inst}, {uops_8_inst}, {uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:505:22, :547:21]
assign out_uop_inst = _GEN_3[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][31:0] _GEN_4 = {{uops_0_debug_inst}, {uops_14_debug_inst}, {uops_13_debug_inst}, {uops_12_debug_inst}, {uops_11_debug_inst}, {uops_10_debug_inst}, {uops_9_debug_inst}, {uops_8_debug_inst}, {uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:505:22, :547:21]
assign out_uop_debug_inst = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_5 = {{uops_0_is_rvc}, {uops_14_is_rvc}, {uops_13_is_rvc}, {uops_12_is_rvc}, {uops_11_is_rvc}, {uops_10_is_rvc}, {uops_9_is_rvc}, {uops_8_is_rvc}, {uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_rvc = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][39:0] _GEN_6 = {{uops_0_debug_pc}, {uops_14_debug_pc}, {uops_13_debug_pc}, {uops_12_debug_pc}, {uops_11_debug_pc}, {uops_10_debug_pc}, {uops_9_debug_pc}, {uops_8_debug_pc}, {uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:505:22, :547:21]
assign out_uop_debug_pc = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_7 = {{uops_0_iq_type_0}, {uops_14_iq_type_0}, {uops_13_iq_type_0}, {uops_12_iq_type_0}, {uops_11_iq_type_0}, {uops_10_iq_type_0}, {uops_9_iq_type_0}, {uops_8_iq_type_0}, {uops_7_iq_type_0}, {uops_6_iq_type_0}, {uops_5_iq_type_0}, {uops_4_iq_type_0}, {uops_3_iq_type_0}, {uops_2_iq_type_0}, {uops_1_iq_type_0}, {uops_0_iq_type_0}}; // @[util.scala:505:22, :547:21]
assign out_uop_iq_type_0 = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_8 = {{uops_0_iq_type_1}, {uops_14_iq_type_1}, {uops_13_iq_type_1}, {uops_12_iq_type_1}, {uops_11_iq_type_1}, {uops_10_iq_type_1}, {uops_9_iq_type_1}, {uops_8_iq_type_1}, {uops_7_iq_type_1}, {uops_6_iq_type_1}, {uops_5_iq_type_1}, {uops_4_iq_type_1}, {uops_3_iq_type_1}, {uops_2_iq_type_1}, {uops_1_iq_type_1}, {uops_0_iq_type_1}}; // @[util.scala:505:22, :547:21]
assign out_uop_iq_type_1 = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_9 = {{uops_0_iq_type_2}, {uops_14_iq_type_2}, {uops_13_iq_type_2}, {uops_12_iq_type_2}, {uops_11_iq_type_2}, {uops_10_iq_type_2}, {uops_9_iq_type_2}, {uops_8_iq_type_2}, {uops_7_iq_type_2}, {uops_6_iq_type_2}, {uops_5_iq_type_2}, {uops_4_iq_type_2}, {uops_3_iq_type_2}, {uops_2_iq_type_2}, {uops_1_iq_type_2}, {uops_0_iq_type_2}}; // @[util.scala:505:22, :547:21]
assign out_uop_iq_type_2 = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_10 = {{uops_0_iq_type_3}, {uops_14_iq_type_3}, {uops_13_iq_type_3}, {uops_12_iq_type_3}, {uops_11_iq_type_3}, {uops_10_iq_type_3}, {uops_9_iq_type_3}, {uops_8_iq_type_3}, {uops_7_iq_type_3}, {uops_6_iq_type_3}, {uops_5_iq_type_3}, {uops_4_iq_type_3}, {uops_3_iq_type_3}, {uops_2_iq_type_3}, {uops_1_iq_type_3}, {uops_0_iq_type_3}}; // @[util.scala:505:22, :547:21]
assign out_uop_iq_type_3 = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_11 = {{uops_0_fu_code_0}, {uops_14_fu_code_0}, {uops_13_fu_code_0}, {uops_12_fu_code_0}, {uops_11_fu_code_0}, {uops_10_fu_code_0}, {uops_9_fu_code_0}, {uops_8_fu_code_0}, {uops_7_fu_code_0}, {uops_6_fu_code_0}, {uops_5_fu_code_0}, {uops_4_fu_code_0}, {uops_3_fu_code_0}, {uops_2_fu_code_0}, {uops_1_fu_code_0}, {uops_0_fu_code_0}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_0 = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_12 = {{uops_0_fu_code_1}, {uops_14_fu_code_1}, {uops_13_fu_code_1}, {uops_12_fu_code_1}, {uops_11_fu_code_1}, {uops_10_fu_code_1}, {uops_9_fu_code_1}, {uops_8_fu_code_1}, {uops_7_fu_code_1}, {uops_6_fu_code_1}, {uops_5_fu_code_1}, {uops_4_fu_code_1}, {uops_3_fu_code_1}, {uops_2_fu_code_1}, {uops_1_fu_code_1}, {uops_0_fu_code_1}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_1 = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_13 = {{uops_0_fu_code_2}, {uops_14_fu_code_2}, {uops_13_fu_code_2}, {uops_12_fu_code_2}, {uops_11_fu_code_2}, {uops_10_fu_code_2}, {uops_9_fu_code_2}, {uops_8_fu_code_2}, {uops_7_fu_code_2}, {uops_6_fu_code_2}, {uops_5_fu_code_2}, {uops_4_fu_code_2}, {uops_3_fu_code_2}, {uops_2_fu_code_2}, {uops_1_fu_code_2}, {uops_0_fu_code_2}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_2 = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_14 = {{uops_0_fu_code_3}, {uops_14_fu_code_3}, {uops_13_fu_code_3}, {uops_12_fu_code_3}, {uops_11_fu_code_3}, {uops_10_fu_code_3}, {uops_9_fu_code_3}, {uops_8_fu_code_3}, {uops_7_fu_code_3}, {uops_6_fu_code_3}, {uops_5_fu_code_3}, {uops_4_fu_code_3}, {uops_3_fu_code_3}, {uops_2_fu_code_3}, {uops_1_fu_code_3}, {uops_0_fu_code_3}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_3 = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_15 = {{uops_0_fu_code_4}, {uops_14_fu_code_4}, {uops_13_fu_code_4}, {uops_12_fu_code_4}, {uops_11_fu_code_4}, {uops_10_fu_code_4}, {uops_9_fu_code_4}, {uops_8_fu_code_4}, {uops_7_fu_code_4}, {uops_6_fu_code_4}, {uops_5_fu_code_4}, {uops_4_fu_code_4}, {uops_3_fu_code_4}, {uops_2_fu_code_4}, {uops_1_fu_code_4}, {uops_0_fu_code_4}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_4 = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_16 = {{uops_0_fu_code_5}, {uops_14_fu_code_5}, {uops_13_fu_code_5}, {uops_12_fu_code_5}, {uops_11_fu_code_5}, {uops_10_fu_code_5}, {uops_9_fu_code_5}, {uops_8_fu_code_5}, {uops_7_fu_code_5}, {uops_6_fu_code_5}, {uops_5_fu_code_5}, {uops_4_fu_code_5}, {uops_3_fu_code_5}, {uops_2_fu_code_5}, {uops_1_fu_code_5}, {uops_0_fu_code_5}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_5 = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_17 = {{uops_0_fu_code_6}, {uops_14_fu_code_6}, {uops_13_fu_code_6}, {uops_12_fu_code_6}, {uops_11_fu_code_6}, {uops_10_fu_code_6}, {uops_9_fu_code_6}, {uops_8_fu_code_6}, {uops_7_fu_code_6}, {uops_6_fu_code_6}, {uops_5_fu_code_6}, {uops_4_fu_code_6}, {uops_3_fu_code_6}, {uops_2_fu_code_6}, {uops_1_fu_code_6}, {uops_0_fu_code_6}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_6 = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_18 = {{uops_0_fu_code_7}, {uops_14_fu_code_7}, {uops_13_fu_code_7}, {uops_12_fu_code_7}, {uops_11_fu_code_7}, {uops_10_fu_code_7}, {uops_9_fu_code_7}, {uops_8_fu_code_7}, {uops_7_fu_code_7}, {uops_6_fu_code_7}, {uops_5_fu_code_7}, {uops_4_fu_code_7}, {uops_3_fu_code_7}, {uops_2_fu_code_7}, {uops_1_fu_code_7}, {uops_0_fu_code_7}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_7 = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_19 = {{uops_0_fu_code_8}, {uops_14_fu_code_8}, {uops_13_fu_code_8}, {uops_12_fu_code_8}, {uops_11_fu_code_8}, {uops_10_fu_code_8}, {uops_9_fu_code_8}, {uops_8_fu_code_8}, {uops_7_fu_code_8}, {uops_6_fu_code_8}, {uops_5_fu_code_8}, {uops_4_fu_code_8}, {uops_3_fu_code_8}, {uops_2_fu_code_8}, {uops_1_fu_code_8}, {uops_0_fu_code_8}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_8 = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_20 = {{uops_0_fu_code_9}, {uops_14_fu_code_9}, {uops_13_fu_code_9}, {uops_12_fu_code_9}, {uops_11_fu_code_9}, {uops_10_fu_code_9}, {uops_9_fu_code_9}, {uops_8_fu_code_9}, {uops_7_fu_code_9}, {uops_6_fu_code_9}, {uops_5_fu_code_9}, {uops_4_fu_code_9}, {uops_3_fu_code_9}, {uops_2_fu_code_9}, {uops_1_fu_code_9}, {uops_0_fu_code_9}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_9 = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_21 = {{uops_0_iw_issued}, {uops_14_iw_issued}, {uops_13_iw_issued}, {uops_12_iw_issued}, {uops_11_iw_issued}, {uops_10_iw_issued}, {uops_9_iw_issued}, {uops_8_iw_issued}, {uops_7_iw_issued}, {uops_6_iw_issued}, {uops_5_iw_issued}, {uops_4_iw_issued}, {uops_3_iw_issued}, {uops_2_iw_issued}, {uops_1_iw_issued}, {uops_0_iw_issued}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_issued = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_22 = {{uops_0_iw_issued_partial_agen}, {uops_14_iw_issued_partial_agen}, {uops_13_iw_issued_partial_agen}, {uops_12_iw_issued_partial_agen}, {uops_11_iw_issued_partial_agen}, {uops_10_iw_issued_partial_agen}, {uops_9_iw_issued_partial_agen}, {uops_8_iw_issued_partial_agen}, {uops_7_iw_issued_partial_agen}, {uops_6_iw_issued_partial_agen}, {uops_5_iw_issued_partial_agen}, {uops_4_iw_issued_partial_agen}, {uops_3_iw_issued_partial_agen}, {uops_2_iw_issued_partial_agen}, {uops_1_iw_issued_partial_agen}, {uops_0_iw_issued_partial_agen}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_issued_partial_agen = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_23 = {{uops_0_iw_issued_partial_dgen}, {uops_14_iw_issued_partial_dgen}, {uops_13_iw_issued_partial_dgen}, {uops_12_iw_issued_partial_dgen}, {uops_11_iw_issued_partial_dgen}, {uops_10_iw_issued_partial_dgen}, {uops_9_iw_issued_partial_dgen}, {uops_8_iw_issued_partial_dgen}, {uops_7_iw_issued_partial_dgen}, {uops_6_iw_issued_partial_dgen}, {uops_5_iw_issued_partial_dgen}, {uops_4_iw_issued_partial_dgen}, {uops_3_iw_issued_partial_dgen}, {uops_2_iw_issued_partial_dgen}, {uops_1_iw_issued_partial_dgen}, {uops_0_iw_issued_partial_dgen}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_issued_partial_dgen = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_24 = {{uops_0_iw_p1_speculative_child}, {uops_14_iw_p1_speculative_child}, {uops_13_iw_p1_speculative_child}, {uops_12_iw_p1_speculative_child}, {uops_11_iw_p1_speculative_child}, {uops_10_iw_p1_speculative_child}, {uops_9_iw_p1_speculative_child}, {uops_8_iw_p1_speculative_child}, {uops_7_iw_p1_speculative_child}, {uops_6_iw_p1_speculative_child}, {uops_5_iw_p1_speculative_child}, {uops_4_iw_p1_speculative_child}, {uops_3_iw_p1_speculative_child}, {uops_2_iw_p1_speculative_child}, {uops_1_iw_p1_speculative_child}, {uops_0_iw_p1_speculative_child}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p1_speculative_child = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_25 = {{uops_0_iw_p2_speculative_child}, {uops_14_iw_p2_speculative_child}, {uops_13_iw_p2_speculative_child}, {uops_12_iw_p2_speculative_child}, {uops_11_iw_p2_speculative_child}, {uops_10_iw_p2_speculative_child}, {uops_9_iw_p2_speculative_child}, {uops_8_iw_p2_speculative_child}, {uops_7_iw_p2_speculative_child}, {uops_6_iw_p2_speculative_child}, {uops_5_iw_p2_speculative_child}, {uops_4_iw_p2_speculative_child}, {uops_3_iw_p2_speculative_child}, {uops_2_iw_p2_speculative_child}, {uops_1_iw_p2_speculative_child}, {uops_0_iw_p2_speculative_child}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p2_speculative_child = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_26 = {{uops_0_iw_p1_bypass_hint}, {uops_14_iw_p1_bypass_hint}, {uops_13_iw_p1_bypass_hint}, {uops_12_iw_p1_bypass_hint}, {uops_11_iw_p1_bypass_hint}, {uops_10_iw_p1_bypass_hint}, {uops_9_iw_p1_bypass_hint}, {uops_8_iw_p1_bypass_hint}, {uops_7_iw_p1_bypass_hint}, {uops_6_iw_p1_bypass_hint}, {uops_5_iw_p1_bypass_hint}, {uops_4_iw_p1_bypass_hint}, {uops_3_iw_p1_bypass_hint}, {uops_2_iw_p1_bypass_hint}, {uops_1_iw_p1_bypass_hint}, {uops_0_iw_p1_bypass_hint}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p1_bypass_hint = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_27 = {{uops_0_iw_p2_bypass_hint}, {uops_14_iw_p2_bypass_hint}, {uops_13_iw_p2_bypass_hint}, {uops_12_iw_p2_bypass_hint}, {uops_11_iw_p2_bypass_hint}, {uops_10_iw_p2_bypass_hint}, {uops_9_iw_p2_bypass_hint}, {uops_8_iw_p2_bypass_hint}, {uops_7_iw_p2_bypass_hint}, {uops_6_iw_p2_bypass_hint}, {uops_5_iw_p2_bypass_hint}, {uops_4_iw_p2_bypass_hint}, {uops_3_iw_p2_bypass_hint}, {uops_2_iw_p2_bypass_hint}, {uops_1_iw_p2_bypass_hint}, {uops_0_iw_p2_bypass_hint}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p2_bypass_hint = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_28 = {{uops_0_iw_p3_bypass_hint}, {uops_14_iw_p3_bypass_hint}, {uops_13_iw_p3_bypass_hint}, {uops_12_iw_p3_bypass_hint}, {uops_11_iw_p3_bypass_hint}, {uops_10_iw_p3_bypass_hint}, {uops_9_iw_p3_bypass_hint}, {uops_8_iw_p3_bypass_hint}, {uops_7_iw_p3_bypass_hint}, {uops_6_iw_p3_bypass_hint}, {uops_5_iw_p3_bypass_hint}, {uops_4_iw_p3_bypass_hint}, {uops_3_iw_p3_bypass_hint}, {uops_2_iw_p3_bypass_hint}, {uops_1_iw_p3_bypass_hint}, {uops_0_iw_p3_bypass_hint}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p3_bypass_hint = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_29 = {{uops_0_dis_col_sel}, {uops_14_dis_col_sel}, {uops_13_dis_col_sel}, {uops_12_dis_col_sel}, {uops_11_dis_col_sel}, {uops_10_dis_col_sel}, {uops_9_dis_col_sel}, {uops_8_dis_col_sel}, {uops_7_dis_col_sel}, {uops_6_dis_col_sel}, {uops_5_dis_col_sel}, {uops_4_dis_col_sel}, {uops_3_dis_col_sel}, {uops_2_dis_col_sel}, {uops_1_dis_col_sel}, {uops_0_dis_col_sel}}; // @[util.scala:505:22, :547:21]
assign out_uop_dis_col_sel = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][15:0] _GEN_30 = {{uops_0_br_mask}, {uops_14_br_mask}, {uops_13_br_mask}, {uops_12_br_mask}, {uops_11_br_mask}, {uops_10_br_mask}, {uops_9_br_mask}, {uops_8_br_mask}, {uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:505:22, :547:21]
assign out_uop_br_mask = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_31 = {{uops_0_br_tag}, {uops_14_br_tag}, {uops_13_br_tag}, {uops_12_br_tag}, {uops_11_br_tag}, {uops_10_br_tag}, {uops_9_br_tag}, {uops_8_br_tag}, {uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:505:22, :547:21]
assign out_uop_br_tag = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_32 = {{uops_0_br_type}, {uops_14_br_type}, {uops_13_br_type}, {uops_12_br_type}, {uops_11_br_type}, {uops_10_br_type}, {uops_9_br_type}, {uops_8_br_type}, {uops_7_br_type}, {uops_6_br_type}, {uops_5_br_type}, {uops_4_br_type}, {uops_3_br_type}, {uops_2_br_type}, {uops_1_br_type}, {uops_0_br_type}}; // @[util.scala:505:22, :547:21]
assign out_uop_br_type = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_33 = {{uops_0_is_sfb}, {uops_14_is_sfb}, {uops_13_is_sfb}, {uops_12_is_sfb}, {uops_11_is_sfb}, {uops_10_is_sfb}, {uops_9_is_sfb}, {uops_8_is_sfb}, {uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_sfb = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_34 = {{uops_0_is_fence}, {uops_14_is_fence}, {uops_13_is_fence}, {uops_12_is_fence}, {uops_11_is_fence}, {uops_10_is_fence}, {uops_9_is_fence}, {uops_8_is_fence}, {uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_fence = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_35 = {{uops_0_is_fencei}, {uops_14_is_fencei}, {uops_13_is_fencei}, {uops_12_is_fencei}, {uops_11_is_fencei}, {uops_10_is_fencei}, {uops_9_is_fencei}, {uops_8_is_fencei}, {uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_fencei = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_36 = {{uops_0_is_sfence}, {uops_14_is_sfence}, {uops_13_is_sfence}, {uops_12_is_sfence}, {uops_11_is_sfence}, {uops_10_is_sfence}, {uops_9_is_sfence}, {uops_8_is_sfence}, {uops_7_is_sfence}, {uops_6_is_sfence}, {uops_5_is_sfence}, {uops_4_is_sfence}, {uops_3_is_sfence}, {uops_2_is_sfence}, {uops_1_is_sfence}, {uops_0_is_sfence}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_sfence = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_37 = {{uops_0_is_amo}, {uops_14_is_amo}, {uops_13_is_amo}, {uops_12_is_amo}, {uops_11_is_amo}, {uops_10_is_amo}, {uops_9_is_amo}, {uops_8_is_amo}, {uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_amo = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_38 = {{uops_0_is_eret}, {uops_14_is_eret}, {uops_13_is_eret}, {uops_12_is_eret}, {uops_11_is_eret}, {uops_10_is_eret}, {uops_9_is_eret}, {uops_8_is_eret}, {uops_7_is_eret}, {uops_6_is_eret}, {uops_5_is_eret}, {uops_4_is_eret}, {uops_3_is_eret}, {uops_2_is_eret}, {uops_1_is_eret}, {uops_0_is_eret}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_eret = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_39 = {{uops_0_is_sys_pc2epc}, {uops_14_is_sys_pc2epc}, {uops_13_is_sys_pc2epc}, {uops_12_is_sys_pc2epc}, {uops_11_is_sys_pc2epc}, {uops_10_is_sys_pc2epc}, {uops_9_is_sys_pc2epc}, {uops_8_is_sys_pc2epc}, {uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_sys_pc2epc = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_40 = {{uops_0_is_rocc}, {uops_14_is_rocc}, {uops_13_is_rocc}, {uops_12_is_rocc}, {uops_11_is_rocc}, {uops_10_is_rocc}, {uops_9_is_rocc}, {uops_8_is_rocc}, {uops_7_is_rocc}, {uops_6_is_rocc}, {uops_5_is_rocc}, {uops_4_is_rocc}, {uops_3_is_rocc}, {uops_2_is_rocc}, {uops_1_is_rocc}, {uops_0_is_rocc}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_rocc = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_41 = {{uops_0_is_mov}, {uops_14_is_mov}, {uops_13_is_mov}, {uops_12_is_mov}, {uops_11_is_mov}, {uops_10_is_mov}, {uops_9_is_mov}, {uops_8_is_mov}, {uops_7_is_mov}, {uops_6_is_mov}, {uops_5_is_mov}, {uops_4_is_mov}, {uops_3_is_mov}, {uops_2_is_mov}, {uops_1_is_mov}, {uops_0_is_mov}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_mov = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_42 = {{uops_0_ftq_idx}, {uops_14_ftq_idx}, {uops_13_ftq_idx}, {uops_12_ftq_idx}, {uops_11_ftq_idx}, {uops_10_ftq_idx}, {uops_9_ftq_idx}, {uops_8_ftq_idx}, {uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_ftq_idx = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_43 = {{uops_0_edge_inst}, {uops_14_edge_inst}, {uops_13_edge_inst}, {uops_12_edge_inst}, {uops_11_edge_inst}, {uops_10_edge_inst}, {uops_9_edge_inst}, {uops_8_edge_inst}, {uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:505:22, :547:21]
assign out_uop_edge_inst = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_44 = {{uops_0_pc_lob}, {uops_14_pc_lob}, {uops_13_pc_lob}, {uops_12_pc_lob}, {uops_11_pc_lob}, {uops_10_pc_lob}, {uops_9_pc_lob}, {uops_8_pc_lob}, {uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:505:22, :547:21]
assign out_uop_pc_lob = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_45 = {{uops_0_taken}, {uops_14_taken}, {uops_13_taken}, {uops_12_taken}, {uops_11_taken}, {uops_10_taken}, {uops_9_taken}, {uops_8_taken}, {uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:505:22, :547:21]
assign out_uop_taken = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_46 = {{uops_0_imm_rename}, {uops_14_imm_rename}, {uops_13_imm_rename}, {uops_12_imm_rename}, {uops_11_imm_rename}, {uops_10_imm_rename}, {uops_9_imm_rename}, {uops_8_imm_rename}, {uops_7_imm_rename}, {uops_6_imm_rename}, {uops_5_imm_rename}, {uops_4_imm_rename}, {uops_3_imm_rename}, {uops_2_imm_rename}, {uops_1_imm_rename}, {uops_0_imm_rename}}; // @[util.scala:505:22, :547:21]
assign out_uop_imm_rename = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_47 = {{uops_0_imm_sel}, {uops_14_imm_sel}, {uops_13_imm_sel}, {uops_12_imm_sel}, {uops_11_imm_sel}, {uops_10_imm_sel}, {uops_9_imm_sel}, {uops_8_imm_sel}, {uops_7_imm_sel}, {uops_6_imm_sel}, {uops_5_imm_sel}, {uops_4_imm_sel}, {uops_3_imm_sel}, {uops_2_imm_sel}, {uops_1_imm_sel}, {uops_0_imm_sel}}; // @[util.scala:505:22, :547:21]
assign out_uop_imm_sel = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_48 = {{uops_0_pimm}, {uops_14_pimm}, {uops_13_pimm}, {uops_12_pimm}, {uops_11_pimm}, {uops_10_pimm}, {uops_9_pimm}, {uops_8_pimm}, {uops_7_pimm}, {uops_6_pimm}, {uops_5_pimm}, {uops_4_pimm}, {uops_3_pimm}, {uops_2_pimm}, {uops_1_pimm}, {uops_0_pimm}}; // @[util.scala:505:22, :547:21]
assign out_uop_pimm = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][19:0] _GEN_49 = {{uops_0_imm_packed}, {uops_14_imm_packed}, {uops_13_imm_packed}, {uops_12_imm_packed}, {uops_11_imm_packed}, {uops_10_imm_packed}, {uops_9_imm_packed}, {uops_8_imm_packed}, {uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:505:22, :547:21]
assign out_uop_imm_packed = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_50 = {{uops_0_op1_sel}, {uops_14_op1_sel}, {uops_13_op1_sel}, {uops_12_op1_sel}, {uops_11_op1_sel}, {uops_10_op1_sel}, {uops_9_op1_sel}, {uops_8_op1_sel}, {uops_7_op1_sel}, {uops_6_op1_sel}, {uops_5_op1_sel}, {uops_4_op1_sel}, {uops_3_op1_sel}, {uops_2_op1_sel}, {uops_1_op1_sel}, {uops_0_op1_sel}}; // @[util.scala:505:22, :547:21]
assign out_uop_op1_sel = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_51 = {{uops_0_op2_sel}, {uops_14_op2_sel}, {uops_13_op2_sel}, {uops_12_op2_sel}, {uops_11_op2_sel}, {uops_10_op2_sel}, {uops_9_op2_sel}, {uops_8_op2_sel}, {uops_7_op2_sel}, {uops_6_op2_sel}, {uops_5_op2_sel}, {uops_4_op2_sel}, {uops_3_op2_sel}, {uops_2_op2_sel}, {uops_1_op2_sel}, {uops_0_op2_sel}}; // @[util.scala:505:22, :547:21]
assign out_uop_op2_sel = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_52 = {{uops_0_fp_ctrl_ldst}, {uops_14_fp_ctrl_ldst}, {uops_13_fp_ctrl_ldst}, {uops_12_fp_ctrl_ldst}, {uops_11_fp_ctrl_ldst}, {uops_10_fp_ctrl_ldst}, {uops_9_fp_ctrl_ldst}, {uops_8_fp_ctrl_ldst}, {uops_7_fp_ctrl_ldst}, {uops_6_fp_ctrl_ldst}, {uops_5_fp_ctrl_ldst}, {uops_4_fp_ctrl_ldst}, {uops_3_fp_ctrl_ldst}, {uops_2_fp_ctrl_ldst}, {uops_1_fp_ctrl_ldst}, {uops_0_fp_ctrl_ldst}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_ldst = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_53 = {{uops_0_fp_ctrl_wen}, {uops_14_fp_ctrl_wen}, {uops_13_fp_ctrl_wen}, {uops_12_fp_ctrl_wen}, {uops_11_fp_ctrl_wen}, {uops_10_fp_ctrl_wen}, {uops_9_fp_ctrl_wen}, {uops_8_fp_ctrl_wen}, {uops_7_fp_ctrl_wen}, {uops_6_fp_ctrl_wen}, {uops_5_fp_ctrl_wen}, {uops_4_fp_ctrl_wen}, {uops_3_fp_ctrl_wen}, {uops_2_fp_ctrl_wen}, {uops_1_fp_ctrl_wen}, {uops_0_fp_ctrl_wen}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_wen = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_54 = {{uops_0_fp_ctrl_ren1}, {uops_14_fp_ctrl_ren1}, {uops_13_fp_ctrl_ren1}, {uops_12_fp_ctrl_ren1}, {uops_11_fp_ctrl_ren1}, {uops_10_fp_ctrl_ren1}, {uops_9_fp_ctrl_ren1}, {uops_8_fp_ctrl_ren1}, {uops_7_fp_ctrl_ren1}, {uops_6_fp_ctrl_ren1}, {uops_5_fp_ctrl_ren1}, {uops_4_fp_ctrl_ren1}, {uops_3_fp_ctrl_ren1}, {uops_2_fp_ctrl_ren1}, {uops_1_fp_ctrl_ren1}, {uops_0_fp_ctrl_ren1}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_ren1 = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_55 = {{uops_0_fp_ctrl_ren2}, {uops_14_fp_ctrl_ren2}, {uops_13_fp_ctrl_ren2}, {uops_12_fp_ctrl_ren2}, {uops_11_fp_ctrl_ren2}, {uops_10_fp_ctrl_ren2}, {uops_9_fp_ctrl_ren2}, {uops_8_fp_ctrl_ren2}, {uops_7_fp_ctrl_ren2}, {uops_6_fp_ctrl_ren2}, {uops_5_fp_ctrl_ren2}, {uops_4_fp_ctrl_ren2}, {uops_3_fp_ctrl_ren2}, {uops_2_fp_ctrl_ren2}, {uops_1_fp_ctrl_ren2}, {uops_0_fp_ctrl_ren2}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_ren2 = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_56 = {{uops_0_fp_ctrl_ren3}, {uops_14_fp_ctrl_ren3}, {uops_13_fp_ctrl_ren3}, {uops_12_fp_ctrl_ren3}, {uops_11_fp_ctrl_ren3}, {uops_10_fp_ctrl_ren3}, {uops_9_fp_ctrl_ren3}, {uops_8_fp_ctrl_ren3}, {uops_7_fp_ctrl_ren3}, {uops_6_fp_ctrl_ren3}, {uops_5_fp_ctrl_ren3}, {uops_4_fp_ctrl_ren3}, {uops_3_fp_ctrl_ren3}, {uops_2_fp_ctrl_ren3}, {uops_1_fp_ctrl_ren3}, {uops_0_fp_ctrl_ren3}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_ren3 = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_57 = {{uops_0_fp_ctrl_swap12}, {uops_14_fp_ctrl_swap12}, {uops_13_fp_ctrl_swap12}, {uops_12_fp_ctrl_swap12}, {uops_11_fp_ctrl_swap12}, {uops_10_fp_ctrl_swap12}, {uops_9_fp_ctrl_swap12}, {uops_8_fp_ctrl_swap12}, {uops_7_fp_ctrl_swap12}, {uops_6_fp_ctrl_swap12}, {uops_5_fp_ctrl_swap12}, {uops_4_fp_ctrl_swap12}, {uops_3_fp_ctrl_swap12}, {uops_2_fp_ctrl_swap12}, {uops_1_fp_ctrl_swap12}, {uops_0_fp_ctrl_swap12}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_swap12 = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_58 = {{uops_0_fp_ctrl_swap23}, {uops_14_fp_ctrl_swap23}, {uops_13_fp_ctrl_swap23}, {uops_12_fp_ctrl_swap23}, {uops_11_fp_ctrl_swap23}, {uops_10_fp_ctrl_swap23}, {uops_9_fp_ctrl_swap23}, {uops_8_fp_ctrl_swap23}, {uops_7_fp_ctrl_swap23}, {uops_6_fp_ctrl_swap23}, {uops_5_fp_ctrl_swap23}, {uops_4_fp_ctrl_swap23}, {uops_3_fp_ctrl_swap23}, {uops_2_fp_ctrl_swap23}, {uops_1_fp_ctrl_swap23}, {uops_0_fp_ctrl_swap23}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_swap23 = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_59 = {{uops_0_fp_ctrl_typeTagIn}, {uops_14_fp_ctrl_typeTagIn}, {uops_13_fp_ctrl_typeTagIn}, {uops_12_fp_ctrl_typeTagIn}, {uops_11_fp_ctrl_typeTagIn}, {uops_10_fp_ctrl_typeTagIn}, {uops_9_fp_ctrl_typeTagIn}, {uops_8_fp_ctrl_typeTagIn}, {uops_7_fp_ctrl_typeTagIn}, {uops_6_fp_ctrl_typeTagIn}, {uops_5_fp_ctrl_typeTagIn}, {uops_4_fp_ctrl_typeTagIn}, {uops_3_fp_ctrl_typeTagIn}, {uops_2_fp_ctrl_typeTagIn}, {uops_1_fp_ctrl_typeTagIn}, {uops_0_fp_ctrl_typeTagIn}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_typeTagIn = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_60 = {{uops_0_fp_ctrl_typeTagOut}, {uops_14_fp_ctrl_typeTagOut}, {uops_13_fp_ctrl_typeTagOut}, {uops_12_fp_ctrl_typeTagOut}, {uops_11_fp_ctrl_typeTagOut}, {uops_10_fp_ctrl_typeTagOut}, {uops_9_fp_ctrl_typeTagOut}, {uops_8_fp_ctrl_typeTagOut}, {uops_7_fp_ctrl_typeTagOut}, {uops_6_fp_ctrl_typeTagOut}, {uops_5_fp_ctrl_typeTagOut}, {uops_4_fp_ctrl_typeTagOut}, {uops_3_fp_ctrl_typeTagOut}, {uops_2_fp_ctrl_typeTagOut}, {uops_1_fp_ctrl_typeTagOut}, {uops_0_fp_ctrl_typeTagOut}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_typeTagOut = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_61 = {{uops_0_fp_ctrl_fromint}, {uops_14_fp_ctrl_fromint}, {uops_13_fp_ctrl_fromint}, {uops_12_fp_ctrl_fromint}, {uops_11_fp_ctrl_fromint}, {uops_10_fp_ctrl_fromint}, {uops_9_fp_ctrl_fromint}, {uops_8_fp_ctrl_fromint}, {uops_7_fp_ctrl_fromint}, {uops_6_fp_ctrl_fromint}, {uops_5_fp_ctrl_fromint}, {uops_4_fp_ctrl_fromint}, {uops_3_fp_ctrl_fromint}, {uops_2_fp_ctrl_fromint}, {uops_1_fp_ctrl_fromint}, {uops_0_fp_ctrl_fromint}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_fromint = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_62 = {{uops_0_fp_ctrl_toint}, {uops_14_fp_ctrl_toint}, {uops_13_fp_ctrl_toint}, {uops_12_fp_ctrl_toint}, {uops_11_fp_ctrl_toint}, {uops_10_fp_ctrl_toint}, {uops_9_fp_ctrl_toint}, {uops_8_fp_ctrl_toint}, {uops_7_fp_ctrl_toint}, {uops_6_fp_ctrl_toint}, {uops_5_fp_ctrl_toint}, {uops_4_fp_ctrl_toint}, {uops_3_fp_ctrl_toint}, {uops_2_fp_ctrl_toint}, {uops_1_fp_ctrl_toint}, {uops_0_fp_ctrl_toint}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_toint = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_63 = {{uops_0_fp_ctrl_fastpipe}, {uops_14_fp_ctrl_fastpipe}, {uops_13_fp_ctrl_fastpipe}, {uops_12_fp_ctrl_fastpipe}, {uops_11_fp_ctrl_fastpipe}, {uops_10_fp_ctrl_fastpipe}, {uops_9_fp_ctrl_fastpipe}, {uops_8_fp_ctrl_fastpipe}, {uops_7_fp_ctrl_fastpipe}, {uops_6_fp_ctrl_fastpipe}, {uops_5_fp_ctrl_fastpipe}, {uops_4_fp_ctrl_fastpipe}, {uops_3_fp_ctrl_fastpipe}, {uops_2_fp_ctrl_fastpipe}, {uops_1_fp_ctrl_fastpipe}, {uops_0_fp_ctrl_fastpipe}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_fastpipe = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_64 = {{uops_0_fp_ctrl_fma}, {uops_14_fp_ctrl_fma}, {uops_13_fp_ctrl_fma}, {uops_12_fp_ctrl_fma}, {uops_11_fp_ctrl_fma}, {uops_10_fp_ctrl_fma}, {uops_9_fp_ctrl_fma}, {uops_8_fp_ctrl_fma}, {uops_7_fp_ctrl_fma}, {uops_6_fp_ctrl_fma}, {uops_5_fp_ctrl_fma}, {uops_4_fp_ctrl_fma}, {uops_3_fp_ctrl_fma}, {uops_2_fp_ctrl_fma}, {uops_1_fp_ctrl_fma}, {uops_0_fp_ctrl_fma}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_fma = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_65 = {{uops_0_fp_ctrl_div}, {uops_14_fp_ctrl_div}, {uops_13_fp_ctrl_div}, {uops_12_fp_ctrl_div}, {uops_11_fp_ctrl_div}, {uops_10_fp_ctrl_div}, {uops_9_fp_ctrl_div}, {uops_8_fp_ctrl_div}, {uops_7_fp_ctrl_div}, {uops_6_fp_ctrl_div}, {uops_5_fp_ctrl_div}, {uops_4_fp_ctrl_div}, {uops_3_fp_ctrl_div}, {uops_2_fp_ctrl_div}, {uops_1_fp_ctrl_div}, {uops_0_fp_ctrl_div}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_div = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_66 = {{uops_0_fp_ctrl_sqrt}, {uops_14_fp_ctrl_sqrt}, {uops_13_fp_ctrl_sqrt}, {uops_12_fp_ctrl_sqrt}, {uops_11_fp_ctrl_sqrt}, {uops_10_fp_ctrl_sqrt}, {uops_9_fp_ctrl_sqrt}, {uops_8_fp_ctrl_sqrt}, {uops_7_fp_ctrl_sqrt}, {uops_6_fp_ctrl_sqrt}, {uops_5_fp_ctrl_sqrt}, {uops_4_fp_ctrl_sqrt}, {uops_3_fp_ctrl_sqrt}, {uops_2_fp_ctrl_sqrt}, {uops_1_fp_ctrl_sqrt}, {uops_0_fp_ctrl_sqrt}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_sqrt = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_67 = {{uops_0_fp_ctrl_wflags}, {uops_14_fp_ctrl_wflags}, {uops_13_fp_ctrl_wflags}, {uops_12_fp_ctrl_wflags}, {uops_11_fp_ctrl_wflags}, {uops_10_fp_ctrl_wflags}, {uops_9_fp_ctrl_wflags}, {uops_8_fp_ctrl_wflags}, {uops_7_fp_ctrl_wflags}, {uops_6_fp_ctrl_wflags}, {uops_5_fp_ctrl_wflags}, {uops_4_fp_ctrl_wflags}, {uops_3_fp_ctrl_wflags}, {uops_2_fp_ctrl_wflags}, {uops_1_fp_ctrl_wflags}, {uops_0_fp_ctrl_wflags}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_wflags = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_68 = {{uops_0_fp_ctrl_vec}, {uops_14_fp_ctrl_vec}, {uops_13_fp_ctrl_vec}, {uops_12_fp_ctrl_vec}, {uops_11_fp_ctrl_vec}, {uops_10_fp_ctrl_vec}, {uops_9_fp_ctrl_vec}, {uops_8_fp_ctrl_vec}, {uops_7_fp_ctrl_vec}, {uops_6_fp_ctrl_vec}, {uops_5_fp_ctrl_vec}, {uops_4_fp_ctrl_vec}, {uops_3_fp_ctrl_vec}, {uops_2_fp_ctrl_vec}, {uops_1_fp_ctrl_vec}, {uops_0_fp_ctrl_vec}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_vec = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_69 = {{uops_0_rob_idx}, {uops_14_rob_idx}, {uops_13_rob_idx}, {uops_12_rob_idx}, {uops_11_rob_idx}, {uops_10_rob_idx}, {uops_9_rob_idx}, {uops_8_rob_idx}, {uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_rob_idx = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_70 = {{uops_0_ldq_idx}, {uops_14_ldq_idx}, {uops_13_ldq_idx}, {uops_12_ldq_idx}, {uops_11_ldq_idx}, {uops_10_ldq_idx}, {uops_9_ldq_idx}, {uops_8_ldq_idx}, {uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_ldq_idx = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_71 = {{uops_0_stq_idx}, {uops_14_stq_idx}, {uops_13_stq_idx}, {uops_12_stq_idx}, {uops_11_stq_idx}, {uops_10_stq_idx}, {uops_9_stq_idx}, {uops_8_stq_idx}, {uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_stq_idx = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_72 = {{uops_0_rxq_idx}, {uops_14_rxq_idx}, {uops_13_rxq_idx}, {uops_12_rxq_idx}, {uops_11_rxq_idx}, {uops_10_rxq_idx}, {uops_9_rxq_idx}, {uops_8_rxq_idx}, {uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_rxq_idx = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_73 = {{uops_0_pdst}, {uops_14_pdst}, {uops_13_pdst}, {uops_12_pdst}, {uops_11_pdst}, {uops_10_pdst}, {uops_9_pdst}, {uops_8_pdst}, {uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:505:22, :547:21]
assign out_uop_pdst = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_74 = {{uops_0_prs1}, {uops_14_prs1}, {uops_13_prs1}, {uops_12_prs1}, {uops_11_prs1}, {uops_10_prs1}, {uops_9_prs1}, {uops_8_prs1}, {uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs1 = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_75 = {{uops_0_prs2}, {uops_14_prs2}, {uops_13_prs2}, {uops_12_prs2}, {uops_11_prs2}, {uops_10_prs2}, {uops_9_prs2}, {uops_8_prs2}, {uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs2 = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_76 = {{uops_0_prs3}, {uops_14_prs3}, {uops_13_prs3}, {uops_12_prs3}, {uops_11_prs3}, {uops_10_prs3}, {uops_9_prs3}, {uops_8_prs3}, {uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs3 = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_77 = {{uops_0_ppred}, {uops_14_ppred}, {uops_13_ppred}, {uops_12_ppred}, {uops_11_ppred}, {uops_10_ppred}, {uops_9_ppred}, {uops_8_ppred}, {uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:505:22, :547:21]
assign out_uop_ppred = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_78 = {{uops_0_prs1_busy}, {uops_14_prs1_busy}, {uops_13_prs1_busy}, {uops_12_prs1_busy}, {uops_11_prs1_busy}, {uops_10_prs1_busy}, {uops_9_prs1_busy}, {uops_8_prs1_busy}, {uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs1_busy = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_79 = {{uops_0_prs2_busy}, {uops_14_prs2_busy}, {uops_13_prs2_busy}, {uops_12_prs2_busy}, {uops_11_prs2_busy}, {uops_10_prs2_busy}, {uops_9_prs2_busy}, {uops_8_prs2_busy}, {uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs2_busy = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_80 = {{uops_0_prs3_busy}, {uops_14_prs3_busy}, {uops_13_prs3_busy}, {uops_12_prs3_busy}, {uops_11_prs3_busy}, {uops_10_prs3_busy}, {uops_9_prs3_busy}, {uops_8_prs3_busy}, {uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs3_busy = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_81 = {{uops_0_ppred_busy}, {uops_14_ppred_busy}, {uops_13_ppred_busy}, {uops_12_ppred_busy}, {uops_11_ppred_busy}, {uops_10_ppred_busy}, {uops_9_ppred_busy}, {uops_8_ppred_busy}, {uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:505:22, :547:21]
assign out_uop_ppred_busy = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_82 = {{uops_0_stale_pdst}, {uops_14_stale_pdst}, {uops_13_stale_pdst}, {uops_12_stale_pdst}, {uops_11_stale_pdst}, {uops_10_stale_pdst}, {uops_9_stale_pdst}, {uops_8_stale_pdst}, {uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:505:22, :547:21]
assign out_uop_stale_pdst = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_83 = {{uops_0_exception}, {uops_14_exception}, {uops_13_exception}, {uops_12_exception}, {uops_11_exception}, {uops_10_exception}, {uops_9_exception}, {uops_8_exception}, {uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:505:22, :547:21]
assign out_uop_exception = _GEN_83[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][63:0] _GEN_84 = {{uops_0_exc_cause}, {uops_14_exc_cause}, {uops_13_exc_cause}, {uops_12_exc_cause}, {uops_11_exc_cause}, {uops_10_exc_cause}, {uops_9_exc_cause}, {uops_8_exc_cause}, {uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:505:22, :547:21]
assign out_uop_exc_cause = _GEN_84[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_85 = {{uops_0_mem_cmd}, {uops_14_mem_cmd}, {uops_13_mem_cmd}, {uops_12_mem_cmd}, {uops_11_mem_cmd}, {uops_10_mem_cmd}, {uops_9_mem_cmd}, {uops_8_mem_cmd}, {uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:505:22, :547:21]
assign out_uop_mem_cmd = _GEN_85[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_86 = {{uops_0_mem_size}, {uops_14_mem_size}, {uops_13_mem_size}, {uops_12_mem_size}, {uops_11_mem_size}, {uops_10_mem_size}, {uops_9_mem_size}, {uops_8_mem_size}, {uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:505:22, :547:21]
assign out_uop_mem_size = _GEN_86[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_87 = {{uops_0_mem_signed}, {uops_14_mem_signed}, {uops_13_mem_signed}, {uops_12_mem_signed}, {uops_11_mem_signed}, {uops_10_mem_signed}, {uops_9_mem_signed}, {uops_8_mem_signed}, {uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:505:22, :547:21]
assign out_uop_mem_signed = _GEN_87[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_88 = {{uops_0_uses_ldq}, {uops_14_uses_ldq}, {uops_13_uses_ldq}, {uops_12_uses_ldq}, {uops_11_uses_ldq}, {uops_10_uses_ldq}, {uops_9_uses_ldq}, {uops_8_uses_ldq}, {uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:505:22, :547:21]
assign out_uop_uses_ldq = _GEN_88[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_89 = {{uops_0_uses_stq}, {uops_14_uses_stq}, {uops_13_uses_stq}, {uops_12_uses_stq}, {uops_11_uses_stq}, {uops_10_uses_stq}, {uops_9_uses_stq}, {uops_8_uses_stq}, {uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:505:22, :547:21]
assign out_uop_uses_stq = _GEN_89[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_90 = {{uops_0_is_unique}, {uops_14_is_unique}, {uops_13_is_unique}, {uops_12_is_unique}, {uops_11_is_unique}, {uops_10_is_unique}, {uops_9_is_unique}, {uops_8_is_unique}, {uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_unique = _GEN_90[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_91 = {{uops_0_flush_on_commit}, {uops_14_flush_on_commit}, {uops_13_flush_on_commit}, {uops_12_flush_on_commit}, {uops_11_flush_on_commit}, {uops_10_flush_on_commit}, {uops_9_flush_on_commit}, {uops_8_flush_on_commit}, {uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:505:22, :547:21]
assign out_uop_flush_on_commit = _GEN_91[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_92 = {{uops_0_csr_cmd}, {uops_14_csr_cmd}, {uops_13_csr_cmd}, {uops_12_csr_cmd}, {uops_11_csr_cmd}, {uops_10_csr_cmd}, {uops_9_csr_cmd}, {uops_8_csr_cmd}, {uops_7_csr_cmd}, {uops_6_csr_cmd}, {uops_5_csr_cmd}, {uops_4_csr_cmd}, {uops_3_csr_cmd}, {uops_2_csr_cmd}, {uops_1_csr_cmd}, {uops_0_csr_cmd}}; // @[util.scala:505:22, :547:21]
assign out_uop_csr_cmd = _GEN_92[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_93 = {{uops_0_ldst_is_rs1}, {uops_14_ldst_is_rs1}, {uops_13_ldst_is_rs1}, {uops_12_ldst_is_rs1}, {uops_11_ldst_is_rs1}, {uops_10_ldst_is_rs1}, {uops_9_ldst_is_rs1}, {uops_8_ldst_is_rs1}, {uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:505:22, :547:21]
assign out_uop_ldst_is_rs1 = _GEN_93[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_94 = {{uops_0_ldst}, {uops_14_ldst}, {uops_13_ldst}, {uops_12_ldst}, {uops_11_ldst}, {uops_10_ldst}, {uops_9_ldst}, {uops_8_ldst}, {uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:505:22, :547:21]
assign out_uop_ldst = _GEN_94[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_95 = {{uops_0_lrs1}, {uops_14_lrs1}, {uops_13_lrs1}, {uops_12_lrs1}, {uops_11_lrs1}, {uops_10_lrs1}, {uops_9_lrs1}, {uops_8_lrs1}, {uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs1 = _GEN_95[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_96 = {{uops_0_lrs2}, {uops_14_lrs2}, {uops_13_lrs2}, {uops_12_lrs2}, {uops_11_lrs2}, {uops_10_lrs2}, {uops_9_lrs2}, {uops_8_lrs2}, {uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs2 = _GEN_96[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_97 = {{uops_0_lrs3}, {uops_14_lrs3}, {uops_13_lrs3}, {uops_12_lrs3}, {uops_11_lrs3}, {uops_10_lrs3}, {uops_9_lrs3}, {uops_8_lrs3}, {uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs3 = _GEN_97[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_98 = {{uops_0_dst_rtype}, {uops_14_dst_rtype}, {uops_13_dst_rtype}, {uops_12_dst_rtype}, {uops_11_dst_rtype}, {uops_10_dst_rtype}, {uops_9_dst_rtype}, {uops_8_dst_rtype}, {uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:505:22, :547:21]
assign out_uop_dst_rtype = _GEN_98[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_99 = {{uops_0_lrs1_rtype}, {uops_14_lrs1_rtype}, {uops_13_lrs1_rtype}, {uops_12_lrs1_rtype}, {uops_11_lrs1_rtype}, {uops_10_lrs1_rtype}, {uops_9_lrs1_rtype}, {uops_8_lrs1_rtype}, {uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs1_rtype = _GEN_99[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_100 = {{uops_0_lrs2_rtype}, {uops_14_lrs2_rtype}, {uops_13_lrs2_rtype}, {uops_12_lrs2_rtype}, {uops_11_lrs2_rtype}, {uops_10_lrs2_rtype}, {uops_9_lrs2_rtype}, {uops_8_lrs2_rtype}, {uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs2_rtype = _GEN_100[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_101 = {{uops_0_frs3_en}, {uops_14_frs3_en}, {uops_13_frs3_en}, {uops_12_frs3_en}, {uops_11_frs3_en}, {uops_10_frs3_en}, {uops_9_frs3_en}, {uops_8_frs3_en}, {uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:505:22, :547:21]
assign out_uop_frs3_en = _GEN_101[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_102 = {{uops_0_fcn_dw}, {uops_14_fcn_dw}, {uops_13_fcn_dw}, {uops_12_fcn_dw}, {uops_11_fcn_dw}, {uops_10_fcn_dw}, {uops_9_fcn_dw}, {uops_8_fcn_dw}, {uops_7_fcn_dw}, {uops_6_fcn_dw}, {uops_5_fcn_dw}, {uops_4_fcn_dw}, {uops_3_fcn_dw}, {uops_2_fcn_dw}, {uops_1_fcn_dw}, {uops_0_fcn_dw}}; // @[util.scala:505:22, :547:21]
assign out_uop_fcn_dw = _GEN_102[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_103 = {{uops_0_fcn_op}, {uops_14_fcn_op}, {uops_13_fcn_op}, {uops_12_fcn_op}, {uops_11_fcn_op}, {uops_10_fcn_op}, {uops_9_fcn_op}, {uops_8_fcn_op}, {uops_7_fcn_op}, {uops_6_fcn_op}, {uops_5_fcn_op}, {uops_4_fcn_op}, {uops_3_fcn_op}, {uops_2_fcn_op}, {uops_1_fcn_op}, {uops_0_fcn_op}}; // @[util.scala:505:22, :547:21]
assign out_uop_fcn_op = _GEN_103[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_104 = {{uops_0_fp_val}, {uops_14_fp_val}, {uops_13_fp_val}, {uops_12_fp_val}, {uops_11_fp_val}, {uops_10_fp_val}, {uops_9_fp_val}, {uops_8_fp_val}, {uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_val = _GEN_104[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_105 = {{uops_0_fp_rm}, {uops_14_fp_rm}, {uops_13_fp_rm}, {uops_12_fp_rm}, {uops_11_fp_rm}, {uops_10_fp_rm}, {uops_9_fp_rm}, {uops_8_fp_rm}, {uops_7_fp_rm}, {uops_6_fp_rm}, {uops_5_fp_rm}, {uops_4_fp_rm}, {uops_3_fp_rm}, {uops_2_fp_rm}, {uops_1_fp_rm}, {uops_0_fp_rm}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_rm = _GEN_105[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_106 = {{uops_0_fp_typ}, {uops_14_fp_typ}, {uops_13_fp_typ}, {uops_12_fp_typ}, {uops_11_fp_typ}, {uops_10_fp_typ}, {uops_9_fp_typ}, {uops_8_fp_typ}, {uops_7_fp_typ}, {uops_6_fp_typ}, {uops_5_fp_typ}, {uops_4_fp_typ}, {uops_3_fp_typ}, {uops_2_fp_typ}, {uops_1_fp_typ}, {uops_0_fp_typ}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_typ = _GEN_106[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_107 = {{uops_0_xcpt_pf_if}, {uops_14_xcpt_pf_if}, {uops_13_xcpt_pf_if}, {uops_12_xcpt_pf_if}, {uops_11_xcpt_pf_if}, {uops_10_xcpt_pf_if}, {uops_9_xcpt_pf_if}, {uops_8_xcpt_pf_if}, {uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_xcpt_pf_if = _GEN_107[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_108 = {{uops_0_xcpt_ae_if}, {uops_14_xcpt_ae_if}, {uops_13_xcpt_ae_if}, {uops_12_xcpt_ae_if}, {uops_11_xcpt_ae_if}, {uops_10_xcpt_ae_if}, {uops_9_xcpt_ae_if}, {uops_8_xcpt_ae_if}, {uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_xcpt_ae_if = _GEN_108[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_109 = {{uops_0_xcpt_ma_if}, {uops_14_xcpt_ma_if}, {uops_13_xcpt_ma_if}, {uops_12_xcpt_ma_if}, {uops_11_xcpt_ma_if}, {uops_10_xcpt_ma_if}, {uops_9_xcpt_ma_if}, {uops_8_xcpt_ma_if}, {uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_xcpt_ma_if = _GEN_109[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_110 = {{uops_0_bp_debug_if}, {uops_14_bp_debug_if}, {uops_13_bp_debug_if}, {uops_12_bp_debug_if}, {uops_11_bp_debug_if}, {uops_10_bp_debug_if}, {uops_9_bp_debug_if}, {uops_8_bp_debug_if}, {uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_bp_debug_if = _GEN_110[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_111 = {{uops_0_bp_xcpt_if}, {uops_14_bp_xcpt_if}, {uops_13_bp_xcpt_if}, {uops_12_bp_xcpt_if}, {uops_11_bp_xcpt_if}, {uops_10_bp_xcpt_if}, {uops_9_bp_xcpt_if}, {uops_8_bp_xcpt_if}, {uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_bp_xcpt_if = _GEN_111[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_112 = {{uops_0_debug_fsrc}, {uops_14_debug_fsrc}, {uops_13_debug_fsrc}, {uops_12_debug_fsrc}, {uops_11_debug_fsrc}, {uops_10_debug_fsrc}, {uops_9_debug_fsrc}, {uops_8_debug_fsrc}, {uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:505:22, :547:21]
assign out_uop_debug_fsrc = _GEN_112[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_113 = {{uops_0_debug_tsrc}, {uops_14_debug_tsrc}, {uops_13_debug_tsrc}, {uops_12_debug_tsrc}, {uops_11_debug_tsrc}, {uops_10_debug_tsrc}, {uops_9_debug_tsrc}, {uops_8_debug_tsrc}, {uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:505:22, :547:21]
assign out_uop_debug_tsrc = _GEN_113[deq_ptr_value]; // @[Counter.scala:61:40]
wire _io_deq_valid_T = ~io_empty_0; // @[util.scala:458:7, :515:71, :548:32]
assign _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_0; // @[util.scala:515:44, :548:{32,42}]
assign io_deq_valid_0 = _io_deq_valid_T_1; // @[util.scala:458:7, :548:42]
wire [4:0] _ptr_diff_T = _GEN_1 - _GEN_2; // @[Counter.scala:77:24]
wire [3:0] ptr_diff = _ptr_diff_T[3:0]; // @[util.scala:551:34]
wire [3:0] _io_count_T = {4{maybe_full}}; // @[util.scala:509:29, :557:12]
wire _io_count_T_1 = deq_ptr_value > enq_ptr_value; // @[Counter.scala:61:40]
wire [4:0] _io_count_T_2 = {1'h0, ptr_diff} + 5'hF; // @[util.scala:551:34, :560:26]
wire [3:0] _io_count_T_3 = _io_count_T_2[3:0]; // @[util.scala:560:26]
wire [3:0] _io_count_T_4 = _io_count_T_1 ? _io_count_T_3 : ptr_diff; // @[util.scala:551:34, :559:{12,27}, :560:26]
assign _io_count_T_5 = ptr_match ? _io_count_T : _io_count_T_4; // @[util.scala:511:35, :556:22, :557:12, :559:12]
assign io_count_0 = _io_count_T_5; // @[util.scala:458:7, :556:22]
wire _GEN_114 = enq_ptr_value == 4'h0; // @[Counter.scala:61:40]
wire _GEN_115 = do_enq & _GEN_114; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_116 = enq_ptr_value == 4'h1; // @[Counter.scala:61:40]
wire _GEN_117 = do_enq & _GEN_116; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_118 = enq_ptr_value == 4'h2; // @[Counter.scala:61:40]
wire _GEN_119 = do_enq & _GEN_118; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_120 = enq_ptr_value == 4'h3; // @[Counter.scala:61:40]
wire _GEN_121 = do_enq & _GEN_120; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_122 = enq_ptr_value == 4'h4; // @[Counter.scala:61:40]
wire _GEN_123 = do_enq & _GEN_122; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_124 = enq_ptr_value == 4'h5; // @[Counter.scala:61:40]
wire _GEN_125 = do_enq & _GEN_124; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_126 = enq_ptr_value == 4'h6; // @[Counter.scala:61:40]
wire _GEN_127 = do_enq & _GEN_126; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_128 = enq_ptr_value == 4'h7; // @[Counter.scala:61:40]
wire _GEN_129 = do_enq & _GEN_128; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_130 = enq_ptr_value == 4'h8; // @[Counter.scala:61:40]
wire _GEN_131 = do_enq & _GEN_130; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_132 = enq_ptr_value == 4'h9; // @[Counter.scala:61:40]
wire _GEN_133 = do_enq & _GEN_132; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_134 = enq_ptr_value == 4'hA; // @[Counter.scala:61:40]
wire _GEN_135 = do_enq & _GEN_134; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_136 = enq_ptr_value == 4'hB; // @[Counter.scala:61:40]
wire _GEN_137 = do_enq & _GEN_136; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_138 = enq_ptr_value == 4'hC; // @[Counter.scala:61:40]
wire _GEN_139 = do_enq & _GEN_138; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_140 = enq_ptr_value == 4'hD; // @[Counter.scala:61:40]
wire _GEN_141 = do_enq & _GEN_140; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_142 = do_enq & wrap; // @[Counter.scala:73:24]
always @(posedge clock) begin // @[util.scala:458:7]
if (reset) begin // @[util.scala:458:7]
valids_0 <= 1'h0; // @[util.scala:504:26]
valids_1 <= 1'h0; // @[util.scala:504:26]
valids_2 <= 1'h0; // @[util.scala:504:26]
valids_3 <= 1'h0; // @[util.scala:504:26]
valids_4 <= 1'h0; // @[util.scala:504:26]
valids_5 <= 1'h0; // @[util.scala:504:26]
valids_6 <= 1'h0; // @[util.scala:504:26]
valids_7 <= 1'h0; // @[util.scala:504:26]
valids_8 <= 1'h0; // @[util.scala:504:26]
valids_9 <= 1'h0; // @[util.scala:504:26]
valids_10 <= 1'h0; // @[util.scala:504:26]
valids_11 <= 1'h0; // @[util.scala:504:26]
valids_12 <= 1'h0; // @[util.scala:504:26]
valids_13 <= 1'h0; // @[util.scala:504:26]
valids_14 <= 1'h0; // @[util.scala:504:26]
enq_ptr_value <= 4'h0; // @[Counter.scala:61:40]
deq_ptr_value <= 4'h0; // @[Counter.scala:61:40]
maybe_full <= 1'h0; // @[util.scala:509:29]
end
else begin // @[util.scala:458:7]
valids_0 <= ~(do_deq & deq_ptr_value == 4'h0) & (_GEN_115 | _valids_0_T_7); // @[Counter.scala:61:40]
valids_1 <= ~(do_deq & deq_ptr_value == 4'h1) & (_GEN_117 | _valids_1_T_7); // @[Counter.scala:61:40]
valids_2 <= ~(do_deq & deq_ptr_value == 4'h2) & (_GEN_119 | _valids_2_T_7); // @[Counter.scala:61:40]
valids_3 <= ~(do_deq & deq_ptr_value == 4'h3) & (_GEN_121 | _valids_3_T_7); // @[Counter.scala:61:40]
valids_4 <= ~(do_deq & deq_ptr_value == 4'h4) & (_GEN_123 | _valids_4_T_7); // @[Counter.scala:61:40]
valids_5 <= ~(do_deq & deq_ptr_value == 4'h5) & (_GEN_125 | _valids_5_T_7); // @[Counter.scala:61:40]
valids_6 <= ~(do_deq & deq_ptr_value == 4'h6) & (_GEN_127 | _valids_6_T_7); // @[Counter.scala:61:40]
valids_7 <= ~(do_deq & deq_ptr_value == 4'h7) & (_GEN_129 | _valids_7_T_7); // @[Counter.scala:61:40]
valids_8 <= ~(do_deq & deq_ptr_value == 4'h8) & (_GEN_131 | _valids_8_T_7); // @[Counter.scala:61:40]
valids_9 <= ~(do_deq & deq_ptr_value == 4'h9) & (_GEN_133 | _valids_9_T_7); // @[Counter.scala:61:40]
valids_10 <= ~(do_deq & deq_ptr_value == 4'hA) & (_GEN_135 | _valids_10_T_7); // @[Counter.scala:61:40]
valids_11 <= ~(do_deq & deq_ptr_value == 4'hB) & (_GEN_137 | _valids_11_T_7); // @[Counter.scala:61:40]
valids_12 <= ~(do_deq & deq_ptr_value == 4'hC) & (_GEN_139 | _valids_12_T_7); // @[Counter.scala:61:40]
valids_13 <= ~(do_deq & deq_ptr_value == 4'hD) & (_GEN_141 | _valids_13_T_7); // @[Counter.scala:61:40]
valids_14 <= ~(do_deq & wrap_1) & (_GEN_142 | _valids_14_T_7); // @[Counter.scala:73:24]
if (do_enq) // @[util.scala:514:26]
enq_ptr_value <= wrap ? 4'h0 : _value_T_1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}]
if (do_deq) // @[util.scala:515:26]
deq_ptr_value <= wrap_1 ? 4'h0 : _value_T_3; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}]
if (~(do_enq == do_deq)) // @[util.scala:509:29, :514:26, :515:26, :539:{18,30}, :540:18]
maybe_full <= do_enq; // @[util.scala:509:29, :514:26]
end
if (_GEN_115) begin // @[util.scala:520:18, :526:19, :528:35]
uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_0_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_0_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_0_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_0_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_0_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_0_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_0_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_0_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_0_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_0_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_0_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_0_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_0_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_0_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_0_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_0_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_0_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_0_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_0_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_0_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_0_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_0_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_0_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_114) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_0) // @[util.scala:504:26]
uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_117) begin // @[util.scala:520:18, :526:19, :528:35]
uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_1_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_1_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_1_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_1_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_1_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_1_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_1_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_1_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_1_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_1_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_1_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_1_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_1_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_1_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_1_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_1_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_1_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_1_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_1_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_1_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_1_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_1_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_1_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_116) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_1) // @[util.scala:504:26]
uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_119) begin // @[util.scala:520:18, :526:19, :528:35]
uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_2_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_2_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_2_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_2_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_2_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_2_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_2_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_2_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_2_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_2_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_2_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_2_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_2_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_2_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_2_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_2_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_2_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_2_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_2_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_2_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_2_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_2_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_2_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_118) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_2) // @[util.scala:504:26]
uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_121) begin // @[util.scala:520:18, :526:19, :528:35]
uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_3_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_3_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_3_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_3_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_3_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_3_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_3_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_3_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_3_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_3_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_3_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_3_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_3_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_3_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_3_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_3_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_3_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_3_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_3_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_3_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_3_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_3_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_3_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_120) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_3) // @[util.scala:504:26]
uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_123) begin // @[util.scala:520:18, :526:19, :528:35]
uops_4_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_4_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_4_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_4_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_4_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_4_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_4_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_4_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_4_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_4_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_4_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_4_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_4_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_4_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_4_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_4_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_4_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_4_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_4_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_4_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_4_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_4_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_4_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_4_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_4_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_4_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_4_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_4_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_4_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_4_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_4_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_4_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_4_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_4_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_4_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_4_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_4_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_4_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_4_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_4_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_4_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_4_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_4_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_4_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_4_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_4_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_4_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_4_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_4_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_4_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_4_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_4_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_4_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_4_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_4_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_4_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_4_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_4_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_4_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_4_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_122) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_4_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_4) // @[util.scala:504:26]
uops_4_br_mask <= _uops_4_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_125) begin // @[util.scala:520:18, :526:19, :528:35]
uops_5_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_5_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_5_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_5_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_5_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_5_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_5_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_5_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_5_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_5_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_5_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_5_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_5_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_5_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_5_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_5_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_5_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_5_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_5_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_5_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_5_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_5_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_5_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_5_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_5_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_5_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_5_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_5_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_5_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_5_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_5_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_5_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_5_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_5_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_5_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_5_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_5_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_5_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_5_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_5_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_5_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_5_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_5_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_5_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_5_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_5_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_5_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_5_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_5_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_5_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_5_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_5_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_5_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_5_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_5_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_5_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_5_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_5_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_5_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_5_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_124) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_5_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_5) // @[util.scala:504:26]
uops_5_br_mask <= _uops_5_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_127) begin // @[util.scala:520:18, :526:19, :528:35]
uops_6_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_6_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_6_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_6_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_6_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_6_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_6_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_6_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_6_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_6_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_6_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_6_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_6_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_6_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_6_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_6_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_6_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_6_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_6_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_6_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_6_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_6_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_6_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_6_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_6_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_6_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_6_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_6_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_6_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_6_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_6_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_6_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_6_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_6_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_6_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_6_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_6_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_6_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_6_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_6_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_6_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_6_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_6_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_6_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_6_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_6_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_6_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_6_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_6_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_6_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_6_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_6_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_6_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_6_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_6_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_6_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_6_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_6_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_6_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_6_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_126) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_6_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_6) // @[util.scala:504:26]
uops_6_br_mask <= _uops_6_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_129) begin // @[util.scala:520:18, :526:19, :528:35]
uops_7_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_7_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_7_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_7_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_7_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_7_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_7_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_7_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_7_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_7_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_7_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_7_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_7_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_7_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_7_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_7_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_7_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_7_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_7_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_7_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_7_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_7_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_7_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_7_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_7_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_7_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_7_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_7_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_7_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_7_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_7_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_7_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_7_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_7_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_7_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_7_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_7_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_7_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_7_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_7_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_7_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_7_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_7_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_7_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_7_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_7_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_7_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_7_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_7_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_7_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_7_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_7_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_7_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_7_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_7_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_7_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_7_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_7_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_7_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_7_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_128) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_7_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_7) // @[util.scala:504:26]
uops_7_br_mask <= _uops_7_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_131) begin // @[util.scala:520:18, :526:19, :528:35]
uops_8_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_8_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_8_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_8_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_8_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_8_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_8_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_8_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_8_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_8_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_8_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_8_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_8_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_8_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_8_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_8_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_8_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_8_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_8_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_8_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_8_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_8_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_8_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_8_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_8_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_8_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_8_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_8_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_8_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_8_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_8_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_8_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_8_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_8_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_8_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_8_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_8_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_8_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_8_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_8_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_8_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_8_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_8_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_8_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_8_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_8_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_8_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_8_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_8_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_8_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_8_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_8_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_8_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_8_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_8_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_8_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_8_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_8_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_8_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_8_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_8_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_8_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_8_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_8_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_8_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_8_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_8_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_8_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_8_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_8_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_8_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_8_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_8_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_8_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_8_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_8_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_8_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_8_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_8_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_8_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_8_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_8_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_8_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_130) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_8_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_8) // @[util.scala:504:26]
uops_8_br_mask <= _uops_8_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_133) begin // @[util.scala:520:18, :526:19, :528:35]
uops_9_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_9_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_9_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_9_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_9_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_9_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_9_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_9_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_9_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_9_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_9_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_9_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_9_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_9_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_9_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_9_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_9_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_9_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_9_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_9_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_9_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_9_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_9_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_9_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_9_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_9_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_9_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_9_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_9_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_9_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_9_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_9_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_9_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_9_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_9_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_9_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_9_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_9_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_9_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_9_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_9_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_9_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_9_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_9_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_9_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_9_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_9_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_9_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_9_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_9_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_9_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_9_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_9_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_9_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_9_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_9_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_9_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_9_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_9_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_9_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_9_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_9_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_9_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_9_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_9_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_9_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_9_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_9_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_9_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_9_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_9_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_9_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_9_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_9_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_9_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_9_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_9_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_9_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_9_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_9_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_9_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_9_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_9_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_132) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_9_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_9) // @[util.scala:504:26]
uops_9_br_mask <= _uops_9_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_135) begin // @[util.scala:520:18, :526:19, :528:35]
uops_10_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_10_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_10_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_10_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_10_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_10_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_10_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_10_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_10_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_10_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_10_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_10_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_10_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_10_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_10_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_10_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_10_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_10_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_10_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_10_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_10_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_10_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_10_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_10_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_10_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_10_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_10_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_10_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_10_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_10_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_10_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_10_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_10_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_10_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_10_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_10_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_10_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_10_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_10_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_10_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_10_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_10_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_10_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_10_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_10_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_10_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_10_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_10_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_10_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_10_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_10_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_10_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_10_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_10_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_10_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_10_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_10_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_10_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_10_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_10_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_10_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_10_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_10_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_10_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_10_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_10_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_10_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_10_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_10_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_10_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_10_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_10_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_10_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_10_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_10_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_10_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_10_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_10_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_10_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_10_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_10_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_10_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_10_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_10_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_10_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_10_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_10_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_10_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_10_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_10_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_10_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_10_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_10_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_10_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_134) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_10_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_10) // @[util.scala:504:26]
uops_10_br_mask <= _uops_10_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_137) begin // @[util.scala:520:18, :526:19, :528:35]
uops_11_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_11_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_11_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_11_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_11_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_11_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_11_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_11_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_11_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_11_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_11_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_11_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_11_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_11_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_11_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_11_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_11_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_11_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_11_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_11_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_11_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_11_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_11_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_11_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_11_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_11_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_11_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_11_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_11_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_11_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_11_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_11_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_11_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_11_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_11_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_11_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_11_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_11_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_11_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_11_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_11_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_11_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_11_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_11_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_11_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_11_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_11_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_11_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_11_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_11_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_11_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_11_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_11_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_11_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_11_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_11_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_11_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_11_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_11_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_11_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_11_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_11_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_11_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_11_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_11_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_11_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_11_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_11_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_11_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_11_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_11_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_11_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_11_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_11_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_11_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_11_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_11_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_11_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_11_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_11_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_11_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_11_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_11_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_11_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_11_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_11_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_11_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_11_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_11_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_11_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_11_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_11_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_11_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_11_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_136) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_11_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_11) // @[util.scala:504:26]
uops_11_br_mask <= _uops_11_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_139) begin // @[util.scala:520:18, :526:19, :528:35]
uops_12_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_12_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_12_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_12_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_12_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_12_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_12_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_12_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_12_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_12_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_12_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_12_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_12_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_12_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_12_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_12_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_12_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_12_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_12_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_12_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_12_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_12_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_12_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_12_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_12_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_12_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_12_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_12_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_12_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_12_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_12_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_12_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_12_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_12_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_12_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_12_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_12_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_12_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_12_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_12_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_12_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_12_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_12_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_12_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_12_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_12_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_12_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_12_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_12_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_12_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_12_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_12_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_12_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_12_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_12_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_12_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_12_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_12_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_12_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_12_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_12_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_12_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_12_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_12_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_12_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_12_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_12_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_12_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_12_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_12_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_12_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_12_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_12_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_12_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_12_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_12_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_12_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_12_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_12_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_12_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_12_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_12_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_12_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_12_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_12_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_12_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_12_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_12_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_12_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_12_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_12_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_12_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_12_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_12_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_138) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_12_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_12) // @[util.scala:504:26]
uops_12_br_mask <= _uops_12_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_141) begin // @[util.scala:520:18, :526:19, :528:35]
uops_13_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_13_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_13_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_13_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_13_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_13_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_13_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_13_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_13_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_13_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_13_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_13_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_13_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_13_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_13_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_13_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_13_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_13_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_13_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_13_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_13_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_13_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_13_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_13_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_13_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_13_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_13_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_13_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_13_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_13_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_13_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_13_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_13_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_13_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_13_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_13_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_13_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_13_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_13_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_13_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_13_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_13_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_13_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_13_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_13_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_13_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_13_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_13_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_13_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_13_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_13_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_13_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_13_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_13_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_13_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_13_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_13_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_13_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_13_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_13_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_13_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_13_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_13_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_13_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_13_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_13_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_13_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_13_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_13_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_13_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_13_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_13_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_13_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_13_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_13_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_13_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_13_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_13_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_13_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_13_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_13_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_13_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_13_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_13_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_13_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_13_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_13_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_13_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_13_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_13_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_13_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_13_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_13_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_13_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_140) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_13_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_13) // @[util.scala:504:26]
uops_13_br_mask <= _uops_13_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_142) begin // @[util.scala:520:18, :526:19, :528:35]
uops_14_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_14_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_14_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_14_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_14_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_14_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_14_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_14_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_14_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_14_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_14_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_14_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_14_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_14_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_14_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_14_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_14_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_14_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_14_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_14_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_14_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_14_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_14_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_14_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_14_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_14_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_14_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_14_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_14_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_14_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_14_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_14_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_14_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_14_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_14_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_14_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_14_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_14_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_14_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_14_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_14_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_14_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_14_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_14_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_14_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_14_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_14_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_14_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_14_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_14_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_14_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_14_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_14_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_14_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_14_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_14_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_14_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_14_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_14_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_14_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_14_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_14_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_14_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_14_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_14_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_14_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_14_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_14_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_14_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_14_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_14_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_14_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_14_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_14_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_14_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_14_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_14_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_14_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_14_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_14_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_14_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_14_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_14_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_14_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_14_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_14_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_14_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_14_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_14_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_14_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_14_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_14_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_14_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_14_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & wrap) // @[Counter.scala:73:24]
uops_14_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_14) // @[util.scala:504:26]
uops_14_br_mask <= _uops_14_br_mask_T_1; // @[util.scala:97:21, :505:22]
always @(posedge)
ram_15x141 ram_ext ( // @[util.scala:503:22]
.R0_addr (deq_ptr_value), // @[Counter.scala:61:40]
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_ram_ext_R0_data),
.W0_addr (enq_ptr_value), // @[Counter.scala:61:40]
.W0_en (do_enq), // @[util.scala:514:26]
.W0_clk (clock),
.W0_data ({io_enq_bits_sdq_id_0, io_enq_bits_way_en_0, io_enq_bits_old_meta_tag_0, io_enq_bits_old_meta_coh_state_0, io_enq_bits_tag_match_0, io_enq_bits_is_hella_0, io_enq_bits_data_0, io_enq_bits_addr_0}) // @[util.scala:458:7, :503:22]
); // @[util.scala:503:22]
assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7]
assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7]
assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7]
assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7]
assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7]
assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7]
assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7]
assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7]
assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7]
assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7]
assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7]
assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:458:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7]
assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:458:7]
assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:458:7]
assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7]
assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:458:7]
assign io_deq_bits_way_en = io_deq_bits_way_en_0; // @[util.scala:458:7]
assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:458:7]
assign io_empty = io_empty_0; // @[util.scala:458:7]
assign io_count = io_count_0; // @[util.scala:458:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ForwardingAgeLogic :
input clock : Clock
input reset : Reset
output io : { flip matches : UInt<16>, flip youngest : UInt<4>, found : UInt<1>, found_idx : UInt<4>}
wire age_mask : UInt<1>[16]
connect age_mask[0], UInt<1>(0h1)
node _T = geq(UInt<1>(0h0), io.youngest)
when _T :
connect age_mask[0], UInt<1>(0h0)
connect age_mask[1], UInt<1>(0h1)
node _T_1 = geq(UInt<1>(0h1), io.youngest)
when _T_1 :
connect age_mask[1], UInt<1>(0h0)
connect age_mask[2], UInt<1>(0h1)
node _T_2 = geq(UInt<2>(0h2), io.youngest)
when _T_2 :
connect age_mask[2], UInt<1>(0h0)
connect age_mask[3], UInt<1>(0h1)
node _T_3 = geq(UInt<2>(0h3), io.youngest)
when _T_3 :
connect age_mask[3], UInt<1>(0h0)
connect age_mask[4], UInt<1>(0h1)
node _T_4 = geq(UInt<3>(0h4), io.youngest)
when _T_4 :
connect age_mask[4], UInt<1>(0h0)
connect age_mask[5], UInt<1>(0h1)
node _T_5 = geq(UInt<3>(0h5), io.youngest)
when _T_5 :
connect age_mask[5], UInt<1>(0h0)
connect age_mask[6], UInt<1>(0h1)
node _T_6 = geq(UInt<3>(0h6), io.youngest)
when _T_6 :
connect age_mask[6], UInt<1>(0h0)
connect age_mask[7], UInt<1>(0h1)
node _T_7 = geq(UInt<3>(0h7), io.youngest)
when _T_7 :
connect age_mask[7], UInt<1>(0h0)
connect age_mask[8], UInt<1>(0h1)
node _T_8 = geq(UInt<4>(0h8), io.youngest)
when _T_8 :
connect age_mask[8], UInt<1>(0h0)
connect age_mask[9], UInt<1>(0h1)
node _T_9 = geq(UInt<4>(0h9), io.youngest)
when _T_9 :
connect age_mask[9], UInt<1>(0h0)
connect age_mask[10], UInt<1>(0h1)
node _T_10 = geq(UInt<4>(0ha), io.youngest)
when _T_10 :
connect age_mask[10], UInt<1>(0h0)
connect age_mask[11], UInt<1>(0h1)
node _T_11 = geq(UInt<4>(0hb), io.youngest)
when _T_11 :
connect age_mask[11], UInt<1>(0h0)
connect age_mask[12], UInt<1>(0h1)
node _T_12 = geq(UInt<4>(0hc), io.youngest)
when _T_12 :
connect age_mask[12], UInt<1>(0h0)
connect age_mask[13], UInt<1>(0h1)
node _T_13 = geq(UInt<4>(0hd), io.youngest)
when _T_13 :
connect age_mask[13], UInt<1>(0h0)
connect age_mask[14], UInt<1>(0h1)
node _T_14 = geq(UInt<4>(0he), io.youngest)
when _T_14 :
connect age_mask[14], UInt<1>(0h0)
connect age_mask[15], UInt<1>(0h1)
node _T_15 = geq(UInt<4>(0hf), io.youngest)
when _T_15 :
connect age_mask[15], UInt<1>(0h0)
wire matches : UInt<32>
node matches_lo_lo_lo = cat(age_mask[1], age_mask[0])
node matches_lo_lo_hi = cat(age_mask[3], age_mask[2])
node matches_lo_lo = cat(matches_lo_lo_hi, matches_lo_lo_lo)
node matches_lo_hi_lo = cat(age_mask[5], age_mask[4])
node matches_lo_hi_hi = cat(age_mask[7], age_mask[6])
node matches_lo_hi = cat(matches_lo_hi_hi, matches_lo_hi_lo)
node matches_lo = cat(matches_lo_hi, matches_lo_lo)
node matches_hi_lo_lo = cat(age_mask[9], age_mask[8])
node matches_hi_lo_hi = cat(age_mask[11], age_mask[10])
node matches_hi_lo = cat(matches_hi_lo_hi, matches_hi_lo_lo)
node matches_hi_hi_lo = cat(age_mask[13], age_mask[12])
node matches_hi_hi_hi = cat(age_mask[15], age_mask[14])
node matches_hi_hi = cat(matches_hi_hi_hi, matches_hi_hi_lo)
node matches_hi = cat(matches_hi_hi, matches_hi_lo)
node _matches_T = cat(matches_hi, matches_lo)
node _matches_T_1 = and(io.matches, _matches_T)
node _matches_T_2 = cat(_matches_T_1, io.matches)
connect matches, _matches_T_2
reg found_match : UInt<1>, clock
reg found_idx : UInt<4>, clock
connect found_match, UInt<1>(0h0)
connect found_idx, UInt<1>(0h0)
connect io.found_idx, found_idx
connect io.found, found_match
node _T_16 = bits(matches, 0, 0)
when _T_16 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<1>(0h0)
node _T_17 = bits(matches, 1, 1)
when _T_17 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<1>(0h1)
node _T_18 = bits(matches, 2, 2)
when _T_18 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<2>(0h2)
node _T_19 = bits(matches, 3, 3)
when _T_19 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<2>(0h3)
node _T_20 = bits(matches, 4, 4)
when _T_20 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<3>(0h4)
node _T_21 = bits(matches, 5, 5)
when _T_21 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<3>(0h5)
node _T_22 = bits(matches, 6, 6)
when _T_22 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<3>(0h6)
node _T_23 = bits(matches, 7, 7)
when _T_23 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<3>(0h7)
node _T_24 = bits(matches, 8, 8)
when _T_24 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0h8)
node _T_25 = bits(matches, 9, 9)
when _T_25 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0h9)
node _T_26 = bits(matches, 10, 10)
when _T_26 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0ha)
node _T_27 = bits(matches, 11, 11)
when _T_27 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0hb)
node _T_28 = bits(matches, 12, 12)
when _T_28 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0hc)
node _T_29 = bits(matches, 13, 13)
when _T_29 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0hd)
node _T_30 = bits(matches, 14, 14)
when _T_30 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0he)
node _T_31 = bits(matches, 15, 15)
when _T_31 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0hf)
node _T_32 = bits(matches, 16, 16)
when _T_32 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<1>(0h0)
node _T_33 = bits(matches, 17, 17)
when _T_33 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<1>(0h1)
node _T_34 = bits(matches, 18, 18)
when _T_34 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<2>(0h2)
node _T_35 = bits(matches, 19, 19)
when _T_35 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<2>(0h3)
node _T_36 = bits(matches, 20, 20)
when _T_36 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<3>(0h4)
node _T_37 = bits(matches, 21, 21)
when _T_37 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<3>(0h5)
node _T_38 = bits(matches, 22, 22)
when _T_38 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<3>(0h6)
node _T_39 = bits(matches, 23, 23)
when _T_39 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<3>(0h7)
node _T_40 = bits(matches, 24, 24)
when _T_40 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0h8)
node _T_41 = bits(matches, 25, 25)
when _T_41 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0h9)
node _T_42 = bits(matches, 26, 26)
when _T_42 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0ha)
node _T_43 = bits(matches, 27, 27)
when _T_43 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0hb)
node _T_44 = bits(matches, 28, 28)
when _T_44 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0hc)
node _T_45 = bits(matches, 29, 29)
when _T_45 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0hd)
node _T_46 = bits(matches, 30, 30)
when _T_46 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0he)
node _T_47 = bits(matches, 31, 31)
when _T_47 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0hf) | module ForwardingAgeLogic( // @[lsu.scala:1972:7]
input clock, // @[lsu.scala:1972:7]
input reset, // @[lsu.scala:1972:7]
input [15:0] io_matches, // @[lsu.scala:1974:14]
input [3:0] io_youngest, // @[lsu.scala:1974:14]
output io_found, // @[lsu.scala:1974:14]
output [3:0] io_found_idx // @[lsu.scala:1974:14]
);
wire [15:0] io_matches_0 = io_matches; // @[lsu.scala:1972:7]
wire [3:0] io_youngest_0 = io_youngest; // @[lsu.scala:1972:7]
wire age_mask_15 = 1'h0; // @[lsu.scala:1985:22]
wire io_found_0; // @[lsu.scala:1972:7]
wire [3:0] io_found_idx_0; // @[lsu.scala:1972:7]
wire age_mask_0; // @[lsu.scala:1985:22]
wire age_mask_1; // @[lsu.scala:1985:22]
wire age_mask_2; // @[lsu.scala:1985:22]
wire age_mask_3; // @[lsu.scala:1985:22]
wire age_mask_4; // @[lsu.scala:1985:22]
wire age_mask_5; // @[lsu.scala:1985:22]
wire age_mask_6; // @[lsu.scala:1985:22]
wire age_mask_7; // @[lsu.scala:1985:22]
wire age_mask_8; // @[lsu.scala:1985:22]
wire age_mask_9; // @[lsu.scala:1985:22]
wire age_mask_10; // @[lsu.scala:1985:22]
wire age_mask_11; // @[lsu.scala:1985:22]
wire age_mask_12; // @[lsu.scala:1985:22]
wire age_mask_13; // @[lsu.scala:1985:22]
wire age_mask_14; // @[lsu.scala:1985:22]
assign age_mask_0 = |io_youngest_0; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_1 = |(io_youngest_0[3:1]); // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_2 = io_youngest_0 > 4'h2; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_3 = |(io_youngest_0[3:2]); // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_4 = io_youngest_0 > 4'h4; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_5 = io_youngest_0 > 4'h5; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_6 = io_youngest_0 > 4'h6; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_7 = io_youngest_0[3]; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_8 = io_youngest_0 > 4'h8; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_9 = io_youngest_0 > 4'h9; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_10 = io_youngest_0 > 4'hA; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_11 = io_youngest_0 > 4'hB; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_12 = io_youngest_0 > 4'hC; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_13 = io_youngest_0 > 4'hD; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_14 = &io_youngest_0; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
wire [31:0] _matches_T_2; // @[lsu.scala:1997:17]
wire [31:0] matches_0; // @[lsu.scala:1996:21]
wire [1:0] matches_lo_lo_lo = {age_mask_1, age_mask_0}; // @[lsu.scala:1985:22, :1997:40]
wire [1:0] matches_lo_lo_hi = {age_mask_3, age_mask_2}; // @[lsu.scala:1985:22, :1997:40]
wire [3:0] matches_lo_lo = {matches_lo_lo_hi, matches_lo_lo_lo}; // @[lsu.scala:1997:40]
wire [1:0] matches_lo_hi_lo = {age_mask_5, age_mask_4}; // @[lsu.scala:1985:22, :1997:40]
wire [1:0] matches_lo_hi_hi = {age_mask_7, age_mask_6}; // @[lsu.scala:1985:22, :1997:40]
wire [3:0] matches_lo_hi = {matches_lo_hi_hi, matches_lo_hi_lo}; // @[lsu.scala:1997:40]
wire [7:0] matches_lo = {matches_lo_hi, matches_lo_lo}; // @[lsu.scala:1997:40]
wire [1:0] matches_hi_lo_lo = {age_mask_9, age_mask_8}; // @[lsu.scala:1985:22, :1997:40]
wire [1:0] matches_hi_lo_hi = {age_mask_11, age_mask_10}; // @[lsu.scala:1985:22, :1997:40]
wire [3:0] matches_hi_lo = {matches_hi_lo_hi, matches_hi_lo_lo}; // @[lsu.scala:1997:40]
wire [1:0] matches_hi_hi_lo = {age_mask_13, age_mask_12}; // @[lsu.scala:1985:22, :1997:40]
wire [1:0] matches_hi_hi_hi = {1'h0, age_mask_14}; // @[lsu.scala:1985:22, :1997:40]
wire [3:0] matches_hi_hi = {matches_hi_hi_hi, matches_hi_hi_lo}; // @[lsu.scala:1997:40]
wire [7:0] matches_hi = {matches_hi_hi, matches_hi_lo}; // @[lsu.scala:1997:40]
wire [15:0] _matches_T = {matches_hi, matches_lo}; // @[lsu.scala:1997:40]
wire [15:0] _matches_T_1 = io_matches_0 & _matches_T; // @[lsu.scala:1972:7, :1997:{29,40}]
assign _matches_T_2 = {_matches_T_1, io_matches_0}; // @[lsu.scala:1972:7, :1997:{17,29}]
assign matches_0 = _matches_T_2; // @[lsu.scala:1996:21, :1997:17]
reg found_match; // @[lsu.scala:2000:24]
assign io_found_0 = found_match; // @[lsu.scala:1972:7, :2000:24]
reg [3:0] found_idx; // @[lsu.scala:2001:22]
assign io_found_idx_0 = found_idx; // @[lsu.scala:1972:7, :2001:22]
always @(posedge clock) begin // @[lsu.scala:1972:7]
found_match <= |matches_0; // @[lsu.scala:1996:21, :2000:24, :2012:7, :2013:22]
found_idx <= matches_0[31] ? 4'hF : matches_0[30] ? 4'hE : matches_0[29] ? 4'hD : matches_0[28] ? 4'hC : matches_0[27] ? 4'hB : matches_0[26] ? 4'hA : matches_0[25] ? 4'h9 : matches_0[24] ? 4'h8 : matches_0[23] ? 4'h7 : matches_0[22] ? 4'h6 : matches_0[21] ? 4'h5 : matches_0[20] ? 4'h4 : matches_0[19] ? 4'h3 : matches_0[18] ? 4'h2 : matches_0[17] ? 4'h1 : matches_0[16] ? 4'h0 : matches_0[15] ? 4'hF : matches_0[14] ? 4'hE : matches_0[13] ? 4'hD : matches_0[12] ? 4'hC : matches_0[11] ? 4'hB : matches_0[10] ? 4'hA : matches_0[9] ? 4'h9 : matches_0[8] ? 4'h8 : matches_0[7] ? 4'h7 : matches_0[6] ? 4'h6 : matches_0[5] ? 4'h5 : matches_0[4] ? 4'h4 : matches_0[3] ? 4'h3 : matches_0[2] ? 4'h2 : {3'h0, matches_0[1]}; // @[lsu.scala:1988:17, :1989:15, :1990:5, :1991:19, :1996:21, :2001:22, :2011:20, :2012:7, :2014:20]
always @(posedge)
assign io_found = io_found_0; // @[lsu.scala:1972:7]
assign io_found_idx = io_found_idx_0; // @[lsu.scala:1972:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_9 :
output io : { flip in : UInt<65>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 63, 52)
node _rawIn_isZero_T = bits(rawIn_exp, 11, 9)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 11, 10)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 9, 9)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 9, 9)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 64, 64)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 51, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie11_is53_oe8_os24_4
node _roundAnyRawFNToRecFN_io_invalidExc_T = bits(rawIn.sig, 51, 51)
node _roundAnyRawFNToRecFN_io_invalidExc_T_1 = eq(_roundAnyRawFNToRecFN_io_invalidExc_T, UInt<1>(0h0))
node _roundAnyRawFNToRecFN_io_invalidExc_T_2 = and(rawIn.isNaN, _roundAnyRawFNToRecFN_io_invalidExc_T_1)
connect roundAnyRawFNToRecFN.io.invalidExc, _roundAnyRawFNToRecFN_io_invalidExc_T_2
connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundAnyRawFNToRecFN.io.in.sig, rawIn.sig
connect roundAnyRawFNToRecFN.io.in.sExp, rawIn.sExp
connect roundAnyRawFNToRecFN.io.in.sign, rawIn.sign
connect roundAnyRawFNToRecFN.io.in.isZero, rawIn.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, rawIn.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, rawIn.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module RecFNToRecFN_9( // @[RecFNToRecFN.scala:44:5]
input [64:0] io_in, // @[RecFNToRecFN.scala:48:16]
input [2:0] io_roundingMode, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out, // @[RecFNToRecFN.scala:48:16]
output [4:0] io_exceptionFlags // @[RecFNToRecFN.scala:48:16]
);
wire [64:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16, :72:19]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags_0; // @[RecFNToRecFN.scala:44:5]
wire [11:0] rawIn_exp = io_in_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _rawIn_out_sig_T_2 = io_in_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _roundAnyRawFNToRecFN_io_invalidExc_T = rawIn_sig[51]; // @[rawFloatFromRecFN.scala:55:23]
wire _roundAnyRawFNToRecFN_io_invalidExc_T_1 = ~_roundAnyRawFNToRecFN_io_invalidExc_T; // @[common.scala:82:{49,56}]
wire _roundAnyRawFNToRecFN_io_invalidExc_T_2 = rawIn_isNaN & _roundAnyRawFNToRecFN_io_invalidExc_T_1; // @[rawFloatFromRecFN.scala:55:23]
RoundAnyRawFNToRecFN_ie11_is53_oe8_os24_4 roundAnyRawFNToRecFN ( // @[RecFNToRecFN.scala:72:19]
.io_invalidExc (_roundAnyRawFNToRecFN_io_invalidExc_T_2), // @[common.scala:82:46]
.io_in_isNaN (rawIn_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_in_isInf (rawIn_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_in_isZero (rawIn_isZero_0), // @[rawFloatFromRecFN.scala:55:23]
.io_in_sign (rawIn_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_in_sExp (rawIn_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_in_sig (rawIn_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_roundingMode (io_roundingMode_0), // @[RecFNToRecFN.scala:44:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RecFNToRecFN.scala:72:19]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_229 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_485
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_229( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_485 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_sbus_to_bus_named_cbus :
input clock : Clock
input reset : Reset
output auto : { flip widget_anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}, bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
inst widget of TLWidthWidget16
connect widget.clock, clock
connect widget.reset, reset
wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate bus_xingOut.d.bits.corrupt
invalidate bus_xingOut.d.bits.data
invalidate bus_xingOut.d.bits.denied
invalidate bus_xingOut.d.bits.sink
invalidate bus_xingOut.d.bits.source
invalidate bus_xingOut.d.bits.size
invalidate bus_xingOut.d.bits.param
invalidate bus_xingOut.d.bits.opcode
invalidate bus_xingOut.d.valid
invalidate bus_xingOut.d.ready
invalidate bus_xingOut.a.bits.corrupt
invalidate bus_xingOut.a.bits.data
invalidate bus_xingOut.a.bits.mask
invalidate bus_xingOut.a.bits.address
invalidate bus_xingOut.a.bits.source
invalidate bus_xingOut.a.bits.size
invalidate bus_xingOut.a.bits.param
invalidate bus_xingOut.a.bits.opcode
invalidate bus_xingOut.a.valid
invalidate bus_xingOut.a.ready
wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate bus_xingIn.d.bits.corrupt
invalidate bus_xingIn.d.bits.data
invalidate bus_xingIn.d.bits.denied
invalidate bus_xingIn.d.bits.sink
invalidate bus_xingIn.d.bits.source
invalidate bus_xingIn.d.bits.size
invalidate bus_xingIn.d.bits.param
invalidate bus_xingIn.d.bits.opcode
invalidate bus_xingIn.d.valid
invalidate bus_xingIn.d.ready
invalidate bus_xingIn.a.bits.corrupt
invalidate bus_xingIn.a.bits.data
invalidate bus_xingIn.a.bits.mask
invalidate bus_xingIn.a.bits.address
invalidate bus_xingIn.a.bits.source
invalidate bus_xingIn.a.bits.size
invalidate bus_xingIn.a.bits.param
invalidate bus_xingIn.a.bits.opcode
invalidate bus_xingIn.a.valid
invalidate bus_xingIn.a.ready
connect bus_xingOut, bus_xingIn
connect widget.auto.anon_out.d, bus_xingIn.d
connect bus_xingIn.a.bits, widget.auto.anon_out.a.bits
connect bus_xingIn.a.valid, widget.auto.anon_out.a.valid
connect widget.auto.anon_out.a.ready, bus_xingIn.a.ready
connect auto.bus_xing_out, bus_xingOut
connect widget.auto.anon_in, auto.widget_anon_in
extmodule plusarg_reader_6 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_7 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( // @[LazyModuleImp.scala:138:7]
input clock, // @[LazyModuleImp.scala:138:7]
input reset, // @[LazyModuleImp.scala:138:7]
output auto_widget_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_widget_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_widget_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_widget_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_widget_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_widget_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_widget_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_widget_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_widget_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_widget_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_widget_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_widget_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_widget_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_widget_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_widget_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_widget_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_widget_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_widget_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_widget_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_widget_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_bus_xing_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_widget_anon_in_a_valid_0 = auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_widget_anon_in_a_bits_opcode_0 = auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_widget_anon_in_a_bits_param_0 = auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_widget_anon_in_a_bits_size_0 = auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [6:0] auto_widget_anon_in_a_bits_source_0 = auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [28:0] auto_widget_anon_in_a_bits_address_0 = auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [15:0] auto_widget_anon_in_a_bits_mask_0 = auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [127:0] auto_widget_anon_in_a_bits_data_0 = auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_in_a_bits_corrupt_0 = auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_in_d_ready_0 = auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire auto_bus_xing_out_a_ready_0 = auto_bus_xing_out_a_ready; // @[LazyModuleImp.scala:138:7]
wire auto_bus_xing_out_d_valid_0 = auto_bus_xing_out_d_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_bus_xing_out_d_bits_opcode_0 = auto_bus_xing_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_bus_xing_out_d_bits_param_0 = auto_bus_xing_out_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_bus_xing_out_d_bits_size_0 = auto_bus_xing_out_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [6:0] auto_bus_xing_out_d_bits_source_0 = auto_bus_xing_out_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire auto_bus_xing_out_d_bits_sink_0 = auto_bus_xing_out_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire auto_bus_xing_out_d_bits_denied_0 = auto_bus_xing_out_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_bus_xing_out_d_bits_data_0 = auto_bus_xing_out_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_bus_xing_out_d_bits_corrupt_0 = auto_bus_xing_out_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire bus_xingOut_a_ready = auto_bus_xing_out_a_ready_0; // @[MixedNode.scala:542:17]
wire bus_xingOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17]
wire bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire bus_xingOut_d_ready; // @[MixedNode.scala:542:17]
wire bus_xingOut_d_valid = auto_bus_xing_out_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] bus_xingOut_d_bits_opcode = auto_bus_xing_out_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] bus_xingOut_d_bits_param = auto_bus_xing_out_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] bus_xingOut_d_bits_size = auto_bus_xing_out_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [6:0] bus_xingOut_d_bits_source = auto_bus_xing_out_d_bits_source_0; // @[MixedNode.scala:542:17]
wire bus_xingOut_d_bits_sink = auto_bus_xing_out_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire bus_xingOut_d_bits_denied = auto_bus_xing_out_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] bus_xingOut_d_bits_data = auto_bus_xing_out_d_bits_data_0; // @[MixedNode.scala:542:17]
wire bus_xingOut_d_bits_corrupt = auto_bus_xing_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire auto_widget_anon_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_widget_anon_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_widget_anon_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_widget_anon_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [6:0] auto_widget_anon_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7]
wire [127:0] auto_widget_anon_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_bus_xing_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_bus_xing_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_bus_xing_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [6:0] auto_bus_xing_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire [28:0] auto_bus_xing_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_bus_xing_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_bus_xing_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_bus_xing_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_bus_xing_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
wire auto_bus_xing_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
wire bus_xingIn_a_ready = bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire bus_xingIn_a_valid; // @[MixedNode.scala:551:17]
assign auto_bus_xing_out_a_valid_0 = bus_xingOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] bus_xingIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_bus_xing_out_a_bits_opcode_0 = bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] bus_xingIn_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_bus_xing_out_a_bits_param_0 = bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] bus_xingIn_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_bus_xing_out_a_bits_size_0 = bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] bus_xingIn_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_bus_xing_out_a_bits_source_0 = bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] bus_xingIn_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_bus_xing_out_a_bits_address_0 = bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] bus_xingIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_bus_xing_out_a_bits_mask_0 = bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] bus_xingIn_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_bus_xing_out_a_bits_data_0 = bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17]
wire bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_bus_xing_out_a_bits_corrupt_0 = bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire bus_xingIn_d_ready; // @[MixedNode.scala:551:17]
assign auto_bus_xing_out_d_ready_0 = bus_xingOut_d_ready; // @[MixedNode.scala:542:17]
wire bus_xingIn_d_valid = bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] bus_xingIn_d_bits_opcode = bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] bus_xingIn_d_bits_param = bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] bus_xingIn_d_bits_size = bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [6:0] bus_xingIn_d_bits_source = bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire bus_xingIn_d_bits_sink = bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire bus_xingIn_d_bits_denied = bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] bus_xingIn_d_bits_data = bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire bus_xingIn_d_bits_corrupt = bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_valid = bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_opcode = bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_param = bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_size = bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_source = bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_address = bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_mask = bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_data = bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_corrupt = bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_d_ready = bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
TLWidthWidget16 widget ( // @[WidthWidget.scala:230:28]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (auto_widget_anon_in_a_ready_0),
.auto_anon_in_a_valid (auto_widget_anon_in_a_valid_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_a_bits_opcode (auto_widget_anon_in_a_bits_opcode_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_a_bits_param (auto_widget_anon_in_a_bits_param_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_a_bits_size (auto_widget_anon_in_a_bits_size_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_a_bits_source (auto_widget_anon_in_a_bits_source_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_a_bits_address (auto_widget_anon_in_a_bits_address_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_a_bits_mask (auto_widget_anon_in_a_bits_mask_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_a_bits_data (auto_widget_anon_in_a_bits_data_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_a_bits_corrupt (auto_widget_anon_in_a_bits_corrupt_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_d_ready (auto_widget_anon_in_d_ready_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_d_valid (auto_widget_anon_in_d_valid_0),
.auto_anon_in_d_bits_opcode (auto_widget_anon_in_d_bits_opcode_0),
.auto_anon_in_d_bits_param (auto_widget_anon_in_d_bits_param_0),
.auto_anon_in_d_bits_size (auto_widget_anon_in_d_bits_size_0),
.auto_anon_in_d_bits_source (auto_widget_anon_in_d_bits_source_0),
.auto_anon_in_d_bits_sink (auto_widget_anon_in_d_bits_sink_0),
.auto_anon_in_d_bits_denied (auto_widget_anon_in_d_bits_denied_0),
.auto_anon_in_d_bits_data (auto_widget_anon_in_d_bits_data_0),
.auto_anon_in_d_bits_corrupt (auto_widget_anon_in_d_bits_corrupt_0),
.auto_anon_out_a_ready (bus_xingIn_a_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_a_valid (bus_xingIn_a_valid),
.auto_anon_out_a_bits_opcode (bus_xingIn_a_bits_opcode),
.auto_anon_out_a_bits_param (bus_xingIn_a_bits_param),
.auto_anon_out_a_bits_size (bus_xingIn_a_bits_size),
.auto_anon_out_a_bits_source (bus_xingIn_a_bits_source),
.auto_anon_out_a_bits_address (bus_xingIn_a_bits_address),
.auto_anon_out_a_bits_mask (bus_xingIn_a_bits_mask),
.auto_anon_out_a_bits_data (bus_xingIn_a_bits_data),
.auto_anon_out_a_bits_corrupt (bus_xingIn_a_bits_corrupt),
.auto_anon_out_d_ready (bus_xingIn_d_ready),
.auto_anon_out_d_valid (bus_xingIn_d_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_opcode (bus_xingIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_param (bus_xingIn_d_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_size (bus_xingIn_d_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_source (bus_xingIn_d_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_sink (bus_xingIn_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_denied (bus_xingIn_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_data (bus_xingIn_d_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_corrupt (bus_xingIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[WidthWidget.scala:230:28]
assign auto_widget_anon_in_a_ready = auto_widget_anon_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_valid = auto_widget_anon_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_opcode = auto_widget_anon_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_param = auto_widget_anon_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_size = auto_widget_anon_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_source = auto_widget_anon_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_sink = auto_widget_anon_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_denied = auto_widget_anon_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_data = auto_widget_anon_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_corrupt = auto_widget_anon_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_bus_xing_out_a_valid = auto_bus_xing_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_bus_xing_out_a_bits_opcode = auto_bus_xing_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_bus_xing_out_a_bits_param = auto_bus_xing_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
assign auto_bus_xing_out_a_bits_size = auto_bus_xing_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_bus_xing_out_a_bits_source = auto_bus_xing_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_bus_xing_out_a_bits_address = auto_bus_xing_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
assign auto_bus_xing_out_a_bits_mask = auto_bus_xing_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
assign auto_bus_xing_out_a_bits_data = auto_bus_xing_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_bus_xing_out_a_bits_corrupt = auto_bus_xing_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_bus_xing_out_d_ready = auto_bus_xing_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_75 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_75
connect io_out_source_valid.clock, clock
connect io_out_source_valid.reset, reset
connect io_out_source_valid.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_75( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_75 io_out_source_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module CompareRecFN_16 :
output io : { flip a : UInt<65>, flip b : UInt<65>, flip signaling : UInt<1>, lt : UInt<1>, eq : UInt<1>, gt : UInt<1>, exceptionFlags : UInt<5>}
node rawA_exp = bits(io.a, 63, 52)
node _rawA_isZero_T = bits(rawA_exp, 11, 9)
node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0))
node _rawA_isSpecial_T = bits(rawA_exp, 11, 10)
node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3))
wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _rawA_out_isNaN_T = bits(rawA_exp, 9, 9)
node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T)
connect rawA.isNaN, _rawA_out_isNaN_T_1
node _rawA_out_isInf_T = bits(rawA_exp, 9, 9)
node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0))
node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1)
connect rawA.isInf, _rawA_out_isInf_T_2
connect rawA.isZero, rawA_isZero
node _rawA_out_sign_T = bits(io.a, 64, 64)
connect rawA.sign, _rawA_out_sign_T
node _rawA_out_sExp_T = cvt(rawA_exp)
connect rawA.sExp, _rawA_out_sExp_T
node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0))
node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T)
node _rawA_out_sig_T_2 = bits(io.a, 51, 0)
node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2)
connect rawA.sig, _rawA_out_sig_T_3
node rawB_exp = bits(io.b, 63, 52)
node _rawB_isZero_T = bits(rawB_exp, 11, 9)
node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0))
node _rawB_isSpecial_T = bits(rawB_exp, 11, 10)
node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3))
wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _rawB_out_isNaN_T = bits(rawB_exp, 9, 9)
node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T)
connect rawB.isNaN, _rawB_out_isNaN_T_1
node _rawB_out_isInf_T = bits(rawB_exp, 9, 9)
node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0))
node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1)
connect rawB.isInf, _rawB_out_isInf_T_2
connect rawB.isZero, rawB_isZero
node _rawB_out_sign_T = bits(io.b, 64, 64)
connect rawB.sign, _rawB_out_sign_T
node _rawB_out_sExp_T = cvt(rawB_exp)
connect rawB.sExp, _rawB_out_sExp_T
node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0))
node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T)
node _rawB_out_sig_T_2 = bits(io.b, 51, 0)
node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2)
connect rawB.sig, _rawB_out_sig_T_3
node _ordered_T = eq(rawA.isNaN, UInt<1>(0h0))
node _ordered_T_1 = eq(rawB.isNaN, UInt<1>(0h0))
node ordered = and(_ordered_T, _ordered_T_1)
node bothInfs = and(rawA.isInf, rawB.isInf)
node bothZeros = and(rawA.isZero, rawB.isZero)
node eqExps = eq(rawA.sExp, rawB.sExp)
node _common_ltMags_T = lt(rawA.sExp, rawB.sExp)
node _common_ltMags_T_1 = lt(rawA.sig, rawB.sig)
node _common_ltMags_T_2 = and(eqExps, _common_ltMags_T_1)
node common_ltMags = or(_common_ltMags_T, _common_ltMags_T_2)
node _common_eqMags_T = eq(rawA.sig, rawB.sig)
node common_eqMags = and(eqExps, _common_eqMags_T)
node _ordered_lt_T = eq(bothZeros, UInt<1>(0h0))
node _ordered_lt_T_1 = eq(rawB.sign, UInt<1>(0h0))
node _ordered_lt_T_2 = and(rawA.sign, _ordered_lt_T_1)
node _ordered_lt_T_3 = eq(bothInfs, UInt<1>(0h0))
node _ordered_lt_T_4 = eq(common_ltMags, UInt<1>(0h0))
node _ordered_lt_T_5 = and(rawA.sign, _ordered_lt_T_4)
node _ordered_lt_T_6 = eq(common_eqMags, UInt<1>(0h0))
node _ordered_lt_T_7 = and(_ordered_lt_T_5, _ordered_lt_T_6)
node _ordered_lt_T_8 = eq(rawB.sign, UInt<1>(0h0))
node _ordered_lt_T_9 = and(_ordered_lt_T_8, common_ltMags)
node _ordered_lt_T_10 = or(_ordered_lt_T_7, _ordered_lt_T_9)
node _ordered_lt_T_11 = and(_ordered_lt_T_3, _ordered_lt_T_10)
node _ordered_lt_T_12 = or(_ordered_lt_T_2, _ordered_lt_T_11)
node ordered_lt = and(_ordered_lt_T, _ordered_lt_T_12)
node _ordered_eq_T = eq(rawA.sign, rawB.sign)
node _ordered_eq_T_1 = or(bothInfs, common_eqMags)
node _ordered_eq_T_2 = and(_ordered_eq_T, _ordered_eq_T_1)
node ordered_eq = or(bothZeros, _ordered_eq_T_2)
node _invalid_T = bits(rawA.sig, 51, 51)
node _invalid_T_1 = eq(_invalid_T, UInt<1>(0h0))
node _invalid_T_2 = and(rawA.isNaN, _invalid_T_1)
node _invalid_T_3 = bits(rawB.sig, 51, 51)
node _invalid_T_4 = eq(_invalid_T_3, UInt<1>(0h0))
node _invalid_T_5 = and(rawB.isNaN, _invalid_T_4)
node _invalid_T_6 = or(_invalid_T_2, _invalid_T_5)
node _invalid_T_7 = eq(ordered, UInt<1>(0h0))
node _invalid_T_8 = and(io.signaling, _invalid_T_7)
node invalid = or(_invalid_T_6, _invalid_T_8)
node _io_lt_T = and(ordered, ordered_lt)
connect io.lt, _io_lt_T
node _io_eq_T = and(ordered, ordered_eq)
connect io.eq, _io_eq_T
node _io_gt_T = eq(ordered_lt, UInt<1>(0h0))
node _io_gt_T_1 = and(ordered, _io_gt_T)
node _io_gt_T_2 = eq(ordered_eq, UInt<1>(0h0))
node _io_gt_T_3 = and(_io_gt_T_1, _io_gt_T_2)
connect io.gt, _io_gt_T_3
node _io_exceptionFlags_T = cat(invalid, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T | module CompareRecFN_16( // @[CompareRecFN.scala:42:7]
input [64:0] io_a, // @[CompareRecFN.scala:44:16]
input [64:0] io_b, // @[CompareRecFN.scala:44:16]
input io_signaling, // @[CompareRecFN.scala:44:16]
output io_lt, // @[CompareRecFN.scala:44:16]
output io_eq, // @[CompareRecFN.scala:44:16]
output [4:0] io_exceptionFlags // @[CompareRecFN.scala:44:16]
);
wire [64:0] io_a_0 = io_a; // @[CompareRecFN.scala:42:7]
wire [64:0] io_b_0 = io_b; // @[CompareRecFN.scala:42:7]
wire io_signaling_0 = io_signaling; // @[CompareRecFN.scala:42:7]
wire _io_lt_T; // @[CompareRecFN.scala:78:22]
wire _io_eq_T; // @[CompareRecFN.scala:79:22]
wire _io_gt_T_3; // @[CompareRecFN.scala:80:38]
wire [4:0] _io_exceptionFlags_T; // @[CompareRecFN.scala:81:34]
wire io_lt_0; // @[CompareRecFN.scala:42:7]
wire io_eq_0; // @[CompareRecFN.scala:42:7]
wire io_gt; // @[CompareRecFN.scala:42:7]
wire [4:0] io_exceptionFlags_0; // @[CompareRecFN.scala:42:7]
wire [11:0] rawA_exp = io_a_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = rawA_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawA_isZero = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawA_isZero_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawA_isSpecial_T = rawA_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = rawA_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawA_out_isInf_T = rawA_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawA_out_sign_T = io_a_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawA_out_sig_T = ~rawA_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _rawA_out_sig_T_2 = io_a_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [11:0] rawB_exp = io_b_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = rawB_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawB_isZero = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawB_isZero_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawB_isSpecial_T = rawB_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = rawB_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawB_out_isInf_T = rawB_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawB_out_sign_T = io_b_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawB_out_sig_T = ~rawB_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _rawB_out_sig_T_2 = io_b_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _ordered_T = ~rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire _ordered_T_1 = ~rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire ordered = _ordered_T & _ordered_T_1; // @[CompareRecFN.scala:57:{19,32,35}]
wire bothInfs = rawA_isInf & rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire bothZeros = rawA_isZero_0 & rawB_isZero_0; // @[rawFloatFromRecFN.scala:55:23]
wire eqExps = rawA_sExp == rawB_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire _common_ltMags_T = $signed(rawA_sExp) < $signed(rawB_sExp); // @[rawFloatFromRecFN.scala:55:23]
wire _common_ltMags_T_1 = rawA_sig < rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _common_ltMags_T_2 = eqExps & _common_ltMags_T_1; // @[CompareRecFN.scala:60:29, :62:{44,57}]
wire common_ltMags = _common_ltMags_T | _common_ltMags_T_2; // @[CompareRecFN.scala:62:{20,33,44}]
wire _common_eqMags_T = rawA_sig == rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire common_eqMags = eqExps & _common_eqMags_T; // @[CompareRecFN.scala:60:29, :63:{32,45}]
wire _ordered_lt_T = ~bothZeros; // @[CompareRecFN.scala:59:33, :66:9]
wire _ordered_lt_T_1 = ~rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _ordered_lt_T_2 = rawA_sign & _ordered_lt_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _ordered_lt_T_3 = ~bothInfs; // @[CompareRecFN.scala:58:33, :68:19]
wire _ordered_lt_T_4 = ~common_ltMags; // @[CompareRecFN.scala:62:33, :69:38]
wire _ordered_lt_T_5 = rawA_sign & _ordered_lt_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire _ordered_lt_T_6 = ~common_eqMags; // @[CompareRecFN.scala:63:32, :69:57]
wire _ordered_lt_T_7 = _ordered_lt_T_5 & _ordered_lt_T_6; // @[CompareRecFN.scala:69:{35,54,57}]
wire _ordered_lt_T_8 = ~rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _ordered_lt_T_9 = _ordered_lt_T_8 & common_ltMags; // @[CompareRecFN.scala:62:33, :70:{29,41}]
wire _ordered_lt_T_10 = _ordered_lt_T_7 | _ordered_lt_T_9; // @[CompareRecFN.scala:69:{54,74}, :70:41]
wire _ordered_lt_T_11 = _ordered_lt_T_3 & _ordered_lt_T_10; // @[CompareRecFN.scala:68:{19,30}, :69:74]
wire _ordered_lt_T_12 = _ordered_lt_T_2 | _ordered_lt_T_11; // @[CompareRecFN.scala:67:{25,41}, :68:30]
wire ordered_lt = _ordered_lt_T & _ordered_lt_T_12; // @[CompareRecFN.scala:66:{9,21}, :67:41]
wire _ordered_eq_T = rawA_sign == rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _ordered_eq_T_1 = bothInfs | common_eqMags; // @[CompareRecFN.scala:58:33, :63:32, :72:62]
wire _ordered_eq_T_2 = _ordered_eq_T & _ordered_eq_T_1; // @[CompareRecFN.scala:72:{34,49,62}]
wire ordered_eq = bothZeros | _ordered_eq_T_2; // @[CompareRecFN.scala:59:33, :72:{19,49}]
wire _invalid_T = rawA_sig[51]; // @[rawFloatFromRecFN.scala:55:23]
wire _invalid_T_1 = ~_invalid_T; // @[common.scala:82:{49,56}]
wire _invalid_T_2 = rawA_isNaN & _invalid_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _invalid_T_3 = rawB_sig[51]; // @[rawFloatFromRecFN.scala:55:23]
wire _invalid_T_4 = ~_invalid_T_3; // @[common.scala:82:{49,56}]
wire _invalid_T_5 = rawB_isNaN & _invalid_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire _invalid_T_6 = _invalid_T_2 | _invalid_T_5; // @[common.scala:82:46]
wire _invalid_T_7 = ~ordered; // @[CompareRecFN.scala:57:32, :76:30]
wire _invalid_T_8 = io_signaling_0 & _invalid_T_7; // @[CompareRecFN.scala:42:7, :76:{27,30}]
wire invalid = _invalid_T_6 | _invalid_T_8; // @[CompareRecFN.scala:75:{32,58}, :76:27]
assign _io_lt_T = ordered & ordered_lt; // @[CompareRecFN.scala:57:32, :66:21, :78:22]
assign io_lt_0 = _io_lt_T; // @[CompareRecFN.scala:42:7, :78:22]
assign _io_eq_T = ordered & ordered_eq; // @[CompareRecFN.scala:57:32, :72:19, :79:22]
assign io_eq_0 = _io_eq_T; // @[CompareRecFN.scala:42:7, :79:22]
wire _io_gt_T = ~ordered_lt; // @[CompareRecFN.scala:66:21, :80:25]
wire _io_gt_T_1 = ordered & _io_gt_T; // @[CompareRecFN.scala:57:32, :80:{22,25}]
wire _io_gt_T_2 = ~ordered_eq; // @[CompareRecFN.scala:72:19, :80:41]
assign _io_gt_T_3 = _io_gt_T_1 & _io_gt_T_2; // @[CompareRecFN.scala:80:{22,38,41}]
assign io_gt = _io_gt_T_3; // @[CompareRecFN.scala:42:7, :80:38]
assign _io_exceptionFlags_T = {invalid, 4'h0}; // @[CompareRecFN.scala:75:58, :81:34]
assign io_exceptionFlags_0 = _io_exceptionFlags_T; // @[CompareRecFN.scala:42:7, :81:34]
assign io_lt = io_lt_0; // @[CompareRecFN.scala:42:7]
assign io_eq = io_eq_0; // @[CompareRecFN.scala:42:7]
assign io_exceptionFlags = io_exceptionFlags_0; // @[CompareRecFN.scala:42:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MSHR_6 :
input clock : Clock
input reset : Reset
output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<4>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<8>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}}
regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock
regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock
when meta_valid :
node _T = eq(meta.state, UInt<2>(0h0))
when _T :
node _T_1 = orr(meta.clients)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _T_6 = eq(meta.dirty, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = eq(meta.state, UInt<2>(0h1))
when _T_10 :
node _T_11 = eq(meta.dirty, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = eq(meta.state, UInt<2>(0h2))
when _T_15 :
node _T_16 = orr(meta.clients)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = sub(meta.clients, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = and(meta.clients, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4
assert(clock, _T_23, UInt<1>(0h1), "") : assert_4
node _T_27 = eq(meta.state, UInt<2>(0h3))
when _T_27 :
skip
regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1)
reg sink : UInt<3>, clock
reg gotT : UInt<1>, clock
reg bad_grant : UInt<1>, clock
reg probes_done : UInt<1>, clock
reg probes_toN : UInt<1>, clock
reg probes_noT : UInt<1>, clock
node _T_28 = neq(meta.state, UInt<2>(0h0))
node _T_29 = and(meta_valid, _T_28)
node _T_30 = eq(io.nestedwb.set, request.set)
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.nestedwb.tag, meta.tag)
node _T_33 = and(_T_31, _T_32)
when _T_33 :
when io.nestedwb.b_clr_dirty :
connect meta.dirty, UInt<1>(0h0)
when io.nestedwb.c_set_dirty :
connect meta.dirty, UInt<1>(0h1)
when io.nestedwb.b_toB :
connect meta.state, UInt<2>(0h1)
when io.nestedwb.b_toN :
connect meta.hit, UInt<1>(0h0)
connect io.status.valid, request_valid
connect io.status.bits.set, request.set
connect io.status.bits.tag, request.tag
connect io.status.bits.way, meta.way
node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0))
node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0))
node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2)
node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4)
node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6)
node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7)
connect io.status.bits.blockB, _io_status_bits_blockB_T_8
node _io_status_bits_nestB_T = and(meta_valid, w_releaseack)
node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast)
node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast)
node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3)
connect io.status.bits.nestB, _io_status_bits_nestB_T_4
node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0))
connect io.status.bits.blockC, _io_status_bits_blockC_T
node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1)
node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3)
node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4)
connect io.status.bits.nestC, _io_status_bits_nestC_T_5
node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0))
node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5
assert(clock, _T_36, UInt<1>(0h1), "") : assert_5
node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0))
node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0))
node _T_42 = or(_T_40, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6
assert(clock, _T_42, UInt<1>(0h1), "") : assert_6
node _no_wait_T = and(w_rprobeacklast, w_releaseack)
node _no_wait_T_1 = and(_no_wait_T, w_grantlast)
node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast)
node no_wait = and(_no_wait_T_2, w_grantack)
node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0))
node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release)
node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe)
connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2
node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1)
connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2
node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst)
node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst)
node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3)
connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4
node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0))
node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack)
node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant)
connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2
node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0))
node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst)
connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1
node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0))
node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack)
connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1
node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst)
node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait)
node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3)
connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4
connect io.schedule.bits.reload, no_wait
node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid)
node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid)
node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid)
node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid)
node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid)
node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid)
connect io.schedule.valid, _io_schedule_valid_T_5
when io.schedule.ready :
connect s_rprobe, UInt<1>(0h1)
when w_rprobeackfirst :
connect s_release, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
node _T_46 = and(s_release, s_pprobe)
when _T_46 :
connect s_acquire, UInt<1>(0h1)
when w_releaseack :
connect s_flush, UInt<1>(0h1)
when w_pprobeackfirst :
connect s_probeack, UInt<1>(0h1)
when w_grantfirst :
connect s_grantack, UInt<1>(0h1)
node _T_47 = and(w_pprobeack, w_grant)
when _T_47 :
connect s_execute, UInt<1>(0h1)
when no_wait :
connect s_writeback, UInt<1>(0h1)
when no_wait :
connect request_valid, UInt<1>(0h0)
connect meta_valid, UInt<1>(0h0)
wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}
connect final_meta_writeback, meta
node req_clientBit = eq(request.source, UInt<8>(0ha0))
node _req_needT_T = bits(request.opcode, 2, 2)
node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0))
node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5))
node _req_needT_T_3 = eq(request.param, UInt<1>(0h1))
node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3)
node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4)
node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6))
node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7))
node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7)
node _req_needT_T_9 = neq(request.param, UInt<2>(0h0))
node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9)
node req_needT = or(_req_needT_T_5, _req_needT_T_10)
node _req_acquire_T = eq(request.opcode, UInt<3>(0h6))
node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7))
node req_acquire = or(_req_acquire_T, _req_acquire_T_1)
node _meta_no_clients_T = orr(meta.clients)
node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0))
node _req_promoteT_T = eq(meta.state, UInt<2>(0h3))
node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T)
node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT)
node req_promoteT = and(req_acquire, _req_promoteT_T_2)
node _T_48 = and(request.prio[2], UInt<1>(0h1))
when _T_48 :
node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0)
node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1
node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3))
node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2))
node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1)
node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state)
connect final_meta_writeback.state, _final_meta_writeback_state_T_3
node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1))
node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2))
node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1)
node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5))
node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3)
node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5)
node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7
connect final_meta_writeback.hit, UInt<1>(0h1)
else :
node _T_49 = and(request.control, UInt<1>(0h1))
when _T_49 :
when meta.hit :
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
node _final_meta_writeback_clients_T_8 = not(probes_toN)
node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9
connect final_meta_writeback.hit, UInt<1>(0h0)
else :
node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty)
node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2)
node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0))
node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5
node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0))
node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1))
node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire)
node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state)
node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1))
node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state)
node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11)
node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state)
node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13)
node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15)
node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16)
connect final_meta_writeback.state, _final_meta_writeback_state_T_17
node _final_meta_writeback_clients_T_10 = not(probes_toN)
node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10)
node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0))
node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14
connect final_meta_writeback.tag, request.tag
connect final_meta_writeback.hit, UInt<1>(0h1)
when bad_grant :
when meta.hit :
node _T_50 = eq(meta_valid, UInt<1>(0h0))
node _T_51 = eq(meta.state, UInt<2>(0h1))
node _T_52 = or(_T_50, _T_51)
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7
assert(clock, _T_52, UInt<1>(0h1), "") : assert_7
connect final_meta_writeback.hit, UInt<1>(0h1)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h1)
node _final_meta_writeback_clients_T_15 = not(probes_toN)
node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16
else :
connect final_meta_writeback.hit, UInt<1>(0h0)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
connect final_meta_writeback.clients, UInt<1>(0h0)
wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}
connect invalid.dirty, UInt<1>(0h0)
connect invalid.state, UInt<2>(0h0)
connect invalid.clients, UInt<1>(0h0)
connect invalid.tag, UInt<1>(0h0)
node _honour_BtoT_T = and(meta.clients, req_clientBit)
node _honour_BtoT_T_1 = orr(_honour_BtoT_T)
node honour_BtoT = and(meta.hit, _honour_BtoT_T_1)
node _excluded_client_T = and(meta.hit, request.prio[0])
node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6))
node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7))
node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2)
node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4))
node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4)
node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5))
node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0))
node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7)
node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8)
node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0))
connect io.schedule.bits.a.bits.tag, request.tag
connect io.schedule.bits.a.bits.set, request.set
node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0))
connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1
node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6))
node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7))
node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2)
node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4)
connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5
connect io.schedule.bits.a.bits.source, UInt<1>(0h0)
node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1)
node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2)
connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3
node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag)
connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1
connect io.schedule.bits.b.bits.set, request.set
node _io_schedule_bits_b_bits_clients_T = not(excluded_client)
node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T)
connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1
node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6))
connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T
node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1))
node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1))
connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1
connect io.schedule.bits.c.bits.source, UInt<1>(0h0)
connect io.schedule.bits.c.bits.tag, meta.tag
connect io.schedule.bits.c.bits.set, request.set
connect io.schedule.bits.c.bits.way, meta.way
connect io.schedule.bits.c.bits.dirty, meta.dirty
connect io.schedule.bits.d.bits.set, request.set
connect io.schedule.bits.d.bits.put, request.put
connect io.schedule.bits.d.bits.offset, request.offset
connect io.schedule.bits.d.bits.tag, request.tag
connect io.schedule.bits.d.bits.source, request.source
connect io.schedule.bits.d.bits.size, request.size
connect io.schedule.bits.d.bits.param, request.param
connect io.schedule.bits.d.bits.opcode, request.opcode
connect io.schedule.bits.d.bits.control, request.control
connect io.schedule.bits.d.bits.prio, request.prio
node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0))
node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0))
node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param)
node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param)
node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param)
node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4)
node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param)
node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6)
node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8)
connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9
connect io.schedule.bits.d.bits.sink, UInt<1>(0h0)
connect io.schedule.bits.d.bits.way, meta.way
connect io.schedule.bits.d.bits.bad, bad_grant
connect io.schedule.bits.e.bits.sink, sink
connect io.schedule.bits.x.bits.fail, UInt<1>(0h0)
connect io.schedule.bits.dir.bits.set, request.set
connect io.schedule.bits.dir.bits.way, meta.way
node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0))
wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}
connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag
connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients
connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state
connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty
node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE)
connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1
node _evict_T = eq(meta.hit, UInt<1>(0h0))
wire evict : UInt
connect evict, UInt<1>(0h0)
node evict_c = orr(meta.clients)
node _evict_T_1 = eq(UInt<2>(0h1), meta.state)
when _evict_T_1 :
node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1))
connect evict, _evict_out_T
else :
node _evict_T_2 = eq(UInt<2>(0h2), meta.state)
when _evict_T_2 :
node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect evict, _evict_out_T_1
else :
node _evict_T_3 = eq(UInt<2>(0h3), meta.state)
when _evict_T_3 :
node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3)
connect evict, _evict_out_T_4
else :
node _evict_T_4 = eq(UInt<2>(0h0), meta.state)
when _evict_T_4 :
connect evict, UInt<4>(0h8)
node _evict_T_5 = eq(_evict_T, UInt<1>(0h0))
when _evict_T_5 :
connect evict, UInt<4>(0h8)
wire before : UInt
connect before, UInt<1>(0h0)
node before_c = orr(meta.clients)
node _before_T = eq(UInt<2>(0h1), meta.state)
when _before_T :
node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1))
connect before, _before_out_T
else :
node _before_T_1 = eq(UInt<2>(0h2), meta.state)
when _before_T_1 :
node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect before, _before_out_T_1
else :
node _before_T_2 = eq(UInt<2>(0h3), meta.state)
when _before_T_2 :
node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3)
connect before, _before_out_T_4
else :
node _before_T_3 = eq(UInt<2>(0h0), meta.state)
when _before_T_3 :
connect before, UInt<4>(0h8)
node _before_T_4 = eq(meta.hit, UInt<1>(0h0))
when _before_T_4 :
connect before, UInt<4>(0h8)
wire after : UInt
connect after, UInt<1>(0h0)
node after_c = orr(final_meta_writeback.clients)
node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _after_T :
node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1))
connect after, _after_out_T
else :
node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _after_T_1 :
node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect after, _after_out_T_1
else :
node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _after_T_2 :
node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3)
connect after, _after_out_T_4
else :
node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _after_T_3 :
connect after, UInt<4>(0h8)
node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _after_T_4 :
connect after, UInt<4>(0h8)
node _T_56 = eq(s_release, UInt<1>(0h0))
node _T_57 = and(_T_56, w_rprobeackfirst)
node _T_58 = and(_T_57, io.schedule.ready)
when _T_58 :
node _T_59 = eq(evict, UInt<1>(0h1))
node _T_60 = eq(_T_59, UInt<1>(0h0))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8
assert(clock, _T_60, UInt<1>(0h1), "") : assert_8
node _T_64 = eq(before, UInt<1>(0h1))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(evict, UInt<1>(0h0))
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10
assert(clock, _T_70, UInt<1>(0h1), "") : assert_10
node _T_74 = eq(before, UInt<1>(0h0))
node _T_75 = eq(_T_74, UInt<1>(0h0))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11
assert(clock, _T_75, UInt<1>(0h1), "") : assert_11
node _T_79 = eq(evict, UInt<3>(0h7))
node _T_80 = eq(before, UInt<3>(0h7))
node _T_81 = eq(evict, UInt<3>(0h5))
node _T_82 = eq(before, UInt<3>(0h5))
node _T_83 = eq(evict, UInt<3>(0h4))
node _T_84 = eq(before, UInt<3>(0h4))
node _T_85 = eq(evict, UInt<3>(0h6))
node _T_86 = eq(before, UInt<3>(0h6))
node _T_87 = eq(evict, UInt<2>(0h3))
node _T_88 = eq(before, UInt<2>(0h3))
node _T_89 = eq(evict, UInt<2>(0h2))
node _T_90 = eq(before, UInt<2>(0h2))
node _T_91 = eq(s_writeback, UInt<1>(0h0))
node _T_92 = and(_T_91, no_wait)
node _T_93 = and(_T_92, io.schedule.ready)
when _T_93 :
node _T_94 = eq(before, UInt<4>(0h8))
node _T_95 = eq(after, UInt<1>(0h1))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12
assert(clock, _T_97, UInt<1>(0h1), "") : assert_12
node _T_101 = eq(before, UInt<4>(0h8))
node _T_102 = eq(after, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13
assert(clock, _T_104, UInt<1>(0h1), "") : assert_13
node _T_108 = eq(before, UInt<4>(0h8))
node _T_109 = eq(after, UInt<3>(0h7))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(before, UInt<4>(0h8))
node _T_112 = eq(after, UInt<3>(0h5))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(_T_113, UInt<1>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14
assert(clock, _T_114, UInt<1>(0h1), "") : assert_14
node _T_118 = eq(before, UInt<4>(0h8))
node _T_119 = eq(after, UInt<3>(0h4))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15
assert(clock, _T_121, UInt<1>(0h1), "") : assert_15
node _T_125 = eq(before, UInt<4>(0h8))
node _T_126 = eq(after, UInt<3>(0h6))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(before, UInt<4>(0h8))
node _T_129 = eq(after, UInt<2>(0h3))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(before, UInt<4>(0h8))
node _T_132 = eq(after, UInt<2>(0h2))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16
assert(clock, _T_134, UInt<1>(0h1), "") : assert_16
node _T_138 = eq(before, UInt<1>(0h1))
node _T_139 = eq(after, UInt<4>(0h8))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(_T_140, UInt<1>(0h0))
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17
assert(clock, _T_141, UInt<1>(0h1), "") : assert_17
node _T_145 = eq(before, UInt<1>(0h1))
node _T_146 = eq(after, UInt<1>(0h0))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(_T_147, UInt<1>(0h0))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18
assert(clock, _T_148, UInt<1>(0h1), "") : assert_18
node _T_152 = eq(before, UInt<1>(0h1))
node _T_153 = eq(after, UInt<3>(0h7))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(_T_154, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19
assert(clock, _T_155, UInt<1>(0h1), "") : assert_19
node _T_159 = eq(before, UInt<1>(0h1))
node _T_160 = eq(after, UInt<3>(0h5))
node _T_161 = and(_T_159, _T_160)
node _T_162 = eq(_T_161, UInt<1>(0h0))
node _T_163 = asUInt(reset)
node _T_164 = eq(_T_163, UInt<1>(0h0))
when _T_164 :
node _T_165 = eq(_T_162, UInt<1>(0h0))
when _T_165 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20
assert(clock, _T_162, UInt<1>(0h1), "") : assert_20
node _T_166 = eq(before, UInt<1>(0h1))
node _T_167 = eq(after, UInt<3>(0h4))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21
assert(clock, _T_169, UInt<1>(0h1), "") : assert_21
node _T_173 = eq(before, UInt<1>(0h1))
node _T_174 = eq(after, UInt<3>(0h6))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(_T_175, UInt<1>(0h0))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22
assert(clock, _T_176, UInt<1>(0h1), "") : assert_22
node _T_180 = eq(before, UInt<1>(0h1))
node _T_181 = eq(after, UInt<2>(0h3))
node _T_182 = and(_T_180, _T_181)
node _T_183 = eq(_T_182, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(before, UInt<1>(0h1))
node _T_188 = eq(after, UInt<2>(0h2))
node _T_189 = and(_T_187, _T_188)
node _T_190 = eq(_T_189, UInt<1>(0h0))
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(_T_190, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24
assert(clock, _T_190, UInt<1>(0h1), "") : assert_24
node _T_194 = eq(before, UInt<1>(0h0))
node _T_195 = eq(after, UInt<4>(0h8))
node _T_196 = and(_T_194, _T_195)
node _T_197 = eq(_T_196, UInt<1>(0h0))
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25
assert(clock, _T_197, UInt<1>(0h1), "") : assert_25
node _T_201 = eq(before, UInt<1>(0h0))
node _T_202 = eq(after, UInt<1>(0h1))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(_T_204, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26
assert(clock, _T_204, UInt<1>(0h1), "") : assert_26
node _T_208 = eq(before, UInt<1>(0h0))
node _T_209 = eq(after, UInt<3>(0h7))
node _T_210 = and(_T_208, _T_209)
node _T_211 = eq(_T_210, UInt<1>(0h0))
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27
assert(clock, _T_211, UInt<1>(0h1), "") : assert_27
node _T_215 = eq(before, UInt<1>(0h0))
node _T_216 = eq(after, UInt<3>(0h5))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(_T_217, UInt<1>(0h0))
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28
assert(clock, _T_218, UInt<1>(0h1), "") : assert_28
node _T_222 = eq(before, UInt<1>(0h0))
node _T_223 = eq(after, UInt<3>(0h6))
node _T_224 = and(_T_222, _T_223)
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29
assert(clock, _T_225, UInt<1>(0h1), "") : assert_29
node _T_229 = eq(before, UInt<1>(0h0))
node _T_230 = eq(after, UInt<3>(0h4))
node _T_231 = and(_T_229, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(before, UInt<1>(0h0))
node _T_237 = eq(after, UInt<2>(0h3))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31
assert(clock, _T_239, UInt<1>(0h1), "") : assert_31
node _T_243 = eq(before, UInt<1>(0h0))
node _T_244 = eq(after, UInt<2>(0h2))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(_T_245, UInt<1>(0h0))
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32
assert(clock, _T_246, UInt<1>(0h1), "") : assert_32
node _T_250 = eq(before, UInt<3>(0h7))
node _T_251 = eq(after, UInt<4>(0h8))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33
assert(clock, _T_253, UInt<1>(0h1), "") : assert_33
node _T_257 = eq(before, UInt<3>(0h7))
node _T_258 = eq(after, UInt<1>(0h1))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(_T_259, UInt<1>(0h0))
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34
assert(clock, _T_260, UInt<1>(0h1), "") : assert_34
node _T_264 = eq(before, UInt<3>(0h7))
node _T_265 = eq(after, UInt<1>(0h0))
node _T_266 = and(_T_264, _T_265)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35
assert(clock, _T_267, UInt<1>(0h1), "") : assert_35
node _T_271 = eq(before, UInt<3>(0h7))
node _T_272 = eq(after, UInt<3>(0h5))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(_T_273, UInt<1>(0h0))
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36
assert(clock, _T_274, UInt<1>(0h1), "") : assert_36
node _T_278 = eq(before, UInt<3>(0h7))
node _T_279 = eq(after, UInt<3>(0h6))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(before, UInt<3>(0h7))
node _T_282 = eq(after, UInt<3>(0h4))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37
assert(clock, _T_284, UInt<1>(0h1), "") : assert_37
node _T_288 = eq(before, UInt<3>(0h7))
node _T_289 = eq(after, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(before, UInt<3>(0h7))
node _T_292 = eq(after, UInt<2>(0h2))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(_T_293, UInt<1>(0h0))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38
assert(clock, _T_294, UInt<1>(0h1), "") : assert_38
node _T_298 = eq(before, UInt<3>(0h5))
node _T_299 = eq(after, UInt<4>(0h8))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(_T_300, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39
assert(clock, _T_301, UInt<1>(0h1), "") : assert_39
node _T_305 = eq(before, UInt<3>(0h5))
node _T_306 = eq(after, UInt<1>(0h1))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(_T_307, UInt<1>(0h0))
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40
assert(clock, _T_308, UInt<1>(0h1), "") : assert_40
node _T_312 = eq(before, UInt<3>(0h5))
node _T_313 = eq(after, UInt<1>(0h0))
node _T_314 = and(_T_312, _T_313)
node _T_315 = eq(_T_314, UInt<1>(0h0))
node _T_316 = asUInt(reset)
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(_T_315, UInt<1>(0h0))
when _T_318 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41
assert(clock, _T_315, UInt<1>(0h1), "") : assert_41
node _T_319 = eq(before, UInt<3>(0h5))
node _T_320 = eq(after, UInt<3>(0h7))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(before, UInt<3>(0h5))
node _T_323 = eq(after, UInt<3>(0h6))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(before, UInt<3>(0h5))
node _T_326 = eq(after, UInt<3>(0h4))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(_T_327, UInt<1>(0h0))
node _T_329 = asUInt(reset)
node _T_330 = eq(_T_329, UInt<1>(0h0))
when _T_330 :
node _T_331 = eq(_T_328, UInt<1>(0h0))
when _T_331 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42
assert(clock, _T_328, UInt<1>(0h1), "") : assert_42
node _T_332 = eq(before, UInt<3>(0h5))
node _T_333 = eq(after, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(before, UInt<3>(0h5))
node _T_336 = eq(after, UInt<2>(0h2))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(_T_337, UInt<1>(0h0))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43
assert(clock, _T_338, UInt<1>(0h1), "") : assert_43
node _T_342 = eq(before, UInt<3>(0h6))
node _T_343 = eq(after, UInt<4>(0h8))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(_T_344, UInt<1>(0h0))
node _T_346 = asUInt(reset)
node _T_347 = eq(_T_346, UInt<1>(0h0))
when _T_347 :
node _T_348 = eq(_T_345, UInt<1>(0h0))
when _T_348 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44
assert(clock, _T_345, UInt<1>(0h1), "") : assert_44
node _T_349 = eq(before, UInt<3>(0h6))
node _T_350 = eq(after, UInt<1>(0h1))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(_T_351, UInt<1>(0h0))
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(_T_352, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45
assert(clock, _T_352, UInt<1>(0h1), "") : assert_45
node _T_356 = eq(before, UInt<3>(0h6))
node _T_357 = eq(after, UInt<1>(0h0))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(_T_358, UInt<1>(0h0))
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(_T_359, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46
assert(clock, _T_359, UInt<1>(0h1), "") : assert_46
node _T_363 = eq(before, UInt<3>(0h6))
node _T_364 = eq(after, UInt<3>(0h7))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47
assert(clock, _T_366, UInt<1>(0h1), "") : assert_47
node _T_370 = eq(before, UInt<3>(0h6))
node _T_371 = eq(after, UInt<3>(0h5))
node _T_372 = and(_T_370, _T_371)
node _T_373 = eq(_T_372, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48
assert(clock, _T_373, UInt<1>(0h1), "") : assert_48
node _T_377 = eq(before, UInt<3>(0h6))
node _T_378 = eq(after, UInt<3>(0h4))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(_T_379, UInt<1>(0h0))
node _T_381 = asUInt(reset)
node _T_382 = eq(_T_381, UInt<1>(0h0))
when _T_382 :
node _T_383 = eq(_T_380, UInt<1>(0h0))
when _T_383 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49
assert(clock, _T_380, UInt<1>(0h1), "") : assert_49
node _T_384 = eq(before, UInt<3>(0h6))
node _T_385 = eq(after, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(_T_386, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50
assert(clock, _T_387, UInt<1>(0h1), "") : assert_50
node _T_391 = eq(before, UInt<3>(0h6))
node _T_392 = eq(after, UInt<2>(0h2))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(before, UInt<3>(0h4))
node _T_395 = eq(after, UInt<4>(0h8))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51
assert(clock, _T_397, UInt<1>(0h1), "") : assert_51
node _T_401 = eq(before, UInt<3>(0h4))
node _T_402 = eq(after, UInt<1>(0h1))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(_T_403, UInt<1>(0h0))
node _T_405 = asUInt(reset)
node _T_406 = eq(_T_405, UInt<1>(0h0))
when _T_406 :
node _T_407 = eq(_T_404, UInt<1>(0h0))
when _T_407 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52
assert(clock, _T_404, UInt<1>(0h1), "") : assert_52
node _T_408 = eq(before, UInt<3>(0h4))
node _T_409 = eq(after, UInt<1>(0h0))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(_T_410, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53
assert(clock, _T_411, UInt<1>(0h1), "") : assert_53
node _T_415 = eq(before, UInt<3>(0h4))
node _T_416 = eq(after, UInt<3>(0h7))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(_T_417, UInt<1>(0h0))
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54
assert(clock, _T_418, UInt<1>(0h1), "") : assert_54
node _T_422 = eq(before, UInt<3>(0h4))
node _T_423 = eq(after, UInt<3>(0h5))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(_T_424, UInt<1>(0h0))
node _T_426 = asUInt(reset)
node _T_427 = eq(_T_426, UInt<1>(0h0))
when _T_427 :
node _T_428 = eq(_T_425, UInt<1>(0h0))
when _T_428 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55
assert(clock, _T_425, UInt<1>(0h1), "") : assert_55
node _T_429 = eq(before, UInt<3>(0h4))
node _T_430 = eq(after, UInt<3>(0h6))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(before, UInt<3>(0h4))
node _T_433 = eq(after, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(_T_434, UInt<1>(0h0))
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56
assert(clock, _T_435, UInt<1>(0h1), "") : assert_56
node _T_439 = eq(before, UInt<3>(0h4))
node _T_440 = eq(after, UInt<2>(0h2))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(before, UInt<2>(0h3))
node _T_443 = eq(after, UInt<4>(0h8))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(_T_444, UInt<1>(0h0))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57
assert(clock, _T_445, UInt<1>(0h1), "") : assert_57
node _T_449 = eq(before, UInt<2>(0h3))
node _T_450 = eq(after, UInt<1>(0h1))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(_T_451, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58
assert(clock, _T_452, UInt<1>(0h1), "") : assert_58
node _T_456 = eq(before, UInt<2>(0h3))
node _T_457 = eq(after, UInt<1>(0h0))
node _T_458 = and(_T_456, _T_457)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59
assert(clock, _T_459, UInt<1>(0h1), "") : assert_59
node _T_463 = eq(before, UInt<2>(0h3))
node _T_464 = eq(after, UInt<3>(0h7))
node _T_465 = and(_T_463, _T_464)
node _T_466 = eq(before, UInt<2>(0h3))
node _T_467 = eq(after, UInt<3>(0h5))
node _T_468 = and(_T_466, _T_467)
node _T_469 = eq(before, UInt<2>(0h3))
node _T_470 = eq(after, UInt<3>(0h6))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(before, UInt<2>(0h3))
node _T_473 = eq(after, UInt<3>(0h4))
node _T_474 = and(_T_472, _T_473)
node _T_475 = eq(before, UInt<2>(0h3))
node _T_476 = eq(after, UInt<2>(0h2))
node _T_477 = and(_T_475, _T_476)
node _T_478 = eq(before, UInt<2>(0h2))
node _T_479 = eq(after, UInt<4>(0h8))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60
assert(clock, _T_481, UInt<1>(0h1), "") : assert_60
node _T_485 = eq(before, UInt<2>(0h2))
node _T_486 = eq(after, UInt<1>(0h1))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(_T_487, UInt<1>(0h0))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61
assert(clock, _T_488, UInt<1>(0h1), "") : assert_61
node _T_492 = eq(before, UInt<2>(0h2))
node _T_493 = eq(after, UInt<1>(0h0))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(_T_494, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62
assert(clock, _T_495, UInt<1>(0h1), "") : assert_62
node _T_499 = eq(before, UInt<2>(0h2))
node _T_500 = eq(after, UInt<3>(0h7))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(_T_501, UInt<1>(0h0))
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63
assert(clock, _T_502, UInt<1>(0h1), "") : assert_63
node _T_506 = eq(before, UInt<2>(0h2))
node _T_507 = eq(after, UInt<3>(0h5))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(_T_508, UInt<1>(0h0))
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64
assert(clock, _T_509, UInt<1>(0h1), "") : assert_64
node _T_513 = eq(before, UInt<2>(0h2))
node _T_514 = eq(after, UInt<3>(0h6))
node _T_515 = and(_T_513, _T_514)
node _T_516 = eq(before, UInt<2>(0h2))
node _T_517 = eq(after, UInt<3>(0h4))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(before, UInt<2>(0h2))
node _T_520 = eq(after, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _T_522 = eq(_T_521, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65
assert(clock, _T_522, UInt<1>(0h1), "") : assert_65
node probe_bit = eq(io.sinkc.bits.source, UInt<8>(0ha0))
node _last_probe_T = or(probes_done, probe_bit)
node _last_probe_T_1 = not(excluded_client)
node _last_probe_T_2 = and(meta.clients, _last_probe_T_1)
node last_probe = eq(_last_probe_T, _last_probe_T_2)
node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1))
node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2))
node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1)
node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5))
node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3)
when io.sinkc.valid :
node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_527 = and(probe_toN, _T_526)
node _T_528 = eq(probe_toN, UInt<1>(0h0))
node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_530 = and(_T_528, _T_529)
node _probes_done_T = or(probes_done, probe_bit)
connect probes_done, _probes_done_T
node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0))
node _probes_toN_T_1 = or(probes_toN, _probes_toN_T)
connect probes_toN, _probes_toN_T_1
node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3))
node _probes_noT_T_1 = or(probes_noT, _probes_noT_T)
connect probes_noT, _probes_noT_T_1
node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe)
connect w_rprobeackfirst, _w_rprobeackfirst_T
node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T)
connect w_rprobeacklast, _w_rprobeacklast_T_1
node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe)
connect w_pprobeackfirst, _w_pprobeackfirst_T
node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T)
connect w_pprobeacklast, _w_pprobeacklast_T_1
node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0))
node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T)
node set_pprobeack = and(last_probe, _set_pprobeack_T_1)
node _w_pprobeack_T = or(w_pprobeack, set_pprobeack)
connect w_pprobeack, _w_pprobeack_T
node _T_531 = eq(set_pprobeack, UInt<1>(0h0))
node _T_532 = and(_T_531, w_rprobeackfirst)
node _T_533 = and(set_pprobeack, w_rprobeackfirst)
node _T_534 = neq(meta.state, UInt<2>(0h0))
node _T_535 = eq(io.sinkc.bits.tag, meta.tag)
node _T_536 = and(_T_534, _T_535)
node _T_537 = and(_T_536, io.sinkc.bits.data)
when _T_537 :
connect meta.dirty, UInt<1>(0h1)
when io.sinkd.valid :
node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4))
node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_540 = or(_T_538, _T_539)
when _T_540 :
connect sink, io.sinkd.bits.sink
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, io.sinkd.bits.last
connect bad_grant, io.sinkd.bits.denied
node _w_grant_T = eq(request.offset, UInt<1>(0h0))
node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last)
connect w_grant, _w_grant_T_1
node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_542 = eq(request.offset, UInt<1>(0h0))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_545 = neq(request.offset, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0))
connect gotT, _gotT_T
else :
node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6))
when _T_547 :
connect w_releaseack, UInt<1>(0h1)
when io.sinke.valid :
connect w_grantack, UInt<1>(0h1)
wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}
connect allocate_as_full.set, io.allocate.bits.set
connect allocate_as_full.put, io.allocate.bits.put
connect allocate_as_full.offset, io.allocate.bits.offset
connect allocate_as_full.tag, io.allocate.bits.tag
connect allocate_as_full.source, io.allocate.bits.source
connect allocate_as_full.size, io.allocate.bits.size
connect allocate_as_full.param, io.allocate.bits.param
connect allocate_as_full.opcode, io.allocate.bits.opcode
connect allocate_as_full.control, io.allocate.bits.control
connect allocate_as_full.prio, io.allocate.bits.prio
node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat)
node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits)
node new_request = mux(io.allocate.valid, allocate_as_full, request)
node _new_needT_T = bits(new_request.opcode, 2, 2)
node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0))
node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5))
node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1))
node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3)
node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4)
node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6))
node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7))
node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7)
node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0))
node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9)
node new_needT = or(_new_needT_T_5, _new_needT_T_10)
node new_clientBit = eq(new_request.source, UInt<8>(0ha0))
node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6))
node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7))
node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1)
node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4))
node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3)
node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5))
node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0))
node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6)
node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0))
wire prior : UInt
connect prior, UInt<1>(0h0)
node prior_c = orr(final_meta_writeback.clients)
node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _prior_T :
node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1))
connect prior, _prior_out_T
else :
node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _prior_T_1 :
node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect prior, _prior_out_T_1
else :
node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _prior_T_2 :
node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3)
connect prior, _prior_out_T_4
else :
node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _prior_T_3 :
connect prior, UInt<4>(0h8)
node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _prior_T_4 :
connect prior, UInt<4>(0h8)
node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat)
when _T_548 :
node _T_549 = eq(prior, UInt<4>(0h8))
node _T_550 = eq(prior, UInt<1>(0h1))
node _T_551 = eq(_T_550, UInt<1>(0h0))
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66
assert(clock, _T_551, UInt<1>(0h1), "") : assert_66
node _T_555 = eq(prior, UInt<1>(0h0))
node _T_556 = eq(_T_555, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67
assert(clock, _T_556, UInt<1>(0h1), "") : assert_67
node _T_560 = eq(prior, UInt<3>(0h7))
node _T_561 = eq(prior, UInt<3>(0h5))
node _T_562 = eq(prior, UInt<3>(0h4))
node _T_563 = eq(prior, UInt<3>(0h6))
node _T_564 = eq(prior, UInt<2>(0h3))
node _T_565 = eq(prior, UInt<2>(0h2))
when io.allocate.valid :
node _T_566 = eq(request_valid, UInt<1>(0h0))
node _T_567 = and(io.schedule.ready, io.schedule.valid)
node _T_568 = and(no_wait, _T_567)
node _T_569 = or(_T_566, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68
assert(clock, _T_569, UInt<1>(0h1), "") : assert_68
connect request_valid, UInt<1>(0h1)
connect request.set, io.allocate.bits.set
connect request.put, io.allocate.bits.put
connect request.offset, io.allocate.bits.offset
connect request.tag, io.allocate.bits.tag
connect request.source, io.allocate.bits.source
connect request.size, io.allocate.bits.size
connect request.param, io.allocate.bits.param
connect request.opcode, io.allocate.bits.opcode
connect request.control, io.allocate.bits.control
connect request.prio, io.allocate.bits.prio
node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat)
node _T_574 = or(io.directory.valid, _T_573)
when _T_574 :
connect meta_valid, UInt<1>(0h1)
connect meta, new_meta
connect probes_done, UInt<1>(0h0)
connect probes_toN, UInt<1>(0h0)
connect probes_noT, UInt<1>(0h0)
connect gotT, UInt<1>(0h0)
connect bad_grant, UInt<1>(0h0)
connect s_rprobe, UInt<1>(0h1)
connect w_rprobeackfirst, UInt<1>(0h1)
connect w_rprobeacklast, UInt<1>(0h1)
connect s_release, UInt<1>(0h1)
connect w_releaseack, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
connect s_acquire, UInt<1>(0h1)
connect s_flush, UInt<1>(0h1)
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, UInt<1>(0h1)
connect w_grant, UInt<1>(0h1)
connect w_pprobeackfirst, UInt<1>(0h1)
connect w_pprobeacklast, UInt<1>(0h1)
connect w_pprobeack, UInt<1>(0h1)
connect s_probeack, UInt<1>(0h1)
connect s_grantack, UInt<1>(0h1)
connect s_execute, UInt<1>(0h1)
connect w_grantack, UInt<1>(0h1)
connect s_writeback, UInt<1>(0h1)
node _T_575 = and(new_request.prio[2], UInt<1>(0h1))
when _T_575 :
connect s_execute, UInt<1>(0h0)
node _T_576 = bits(new_request.opcode, 0, 0)
node _T_577 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_578 = and(_T_576, _T_577)
when _T_578 :
connect s_writeback, UInt<1>(0h0)
node _T_579 = eq(new_request.param, UInt<3>(0h0))
node _T_580 = eq(new_request.param, UInt<3>(0h4))
node _T_581 = or(_T_579, _T_580)
node _T_582 = eq(new_meta.state, UInt<2>(0h2))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
connect s_writeback, UInt<1>(0h0)
node _T_584 = eq(new_request.param, UInt<3>(0h1))
node _T_585 = eq(new_request.param, UInt<3>(0h2))
node _T_586 = or(_T_584, _T_585)
node _T_587 = eq(new_request.param, UInt<3>(0h5))
node _T_588 = or(_T_586, _T_587)
node _T_589 = and(new_meta.clients, new_clientBit)
node _T_590 = neq(_T_589, UInt<1>(0h0))
node _T_591 = and(_T_588, _T_590)
when _T_591 :
connect s_writeback, UInt<1>(0h0)
node _T_592 = asUInt(reset)
node _T_593 = eq(_T_592, UInt<1>(0h0))
when _T_593 :
node _T_594 = eq(new_meta.hit, UInt<1>(0h0))
when _T_594 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69
assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69
else :
node _T_595 = and(new_request.control, UInt<1>(0h1))
when _T_595 :
connect s_flush, UInt<1>(0h0)
when new_meta.hit :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_596 = neq(new_meta.clients, UInt<1>(0h0))
node _T_597 = and(UInt<1>(0h1), _T_596)
when _T_597 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
else :
connect s_execute, UInt<1>(0h0)
node _T_598 = eq(new_meta.hit, UInt<1>(0h0))
node _T_599 = neq(new_meta.state, UInt<2>(0h0))
node _T_600 = and(_T_598, _T_599)
when _T_600 :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_601 = neq(new_meta.clients, UInt<1>(0h0))
node _T_602 = and(UInt<1>(0h1), _T_601)
when _T_602 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
node _T_603 = eq(new_meta.hit, UInt<1>(0h0))
node _T_604 = eq(new_meta.state, UInt<2>(0h1))
node _T_605 = and(_T_604, new_needT)
node _T_606 = or(_T_603, _T_605)
when _T_606 :
connect s_acquire, UInt<1>(0h0)
connect w_grantfirst, UInt<1>(0h0)
connect w_grantlast, UInt<1>(0h0)
connect w_grant, UInt<1>(0h0)
connect s_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_607 = eq(new_meta.state, UInt<2>(0h2))
node _T_608 = or(new_needT, _T_607)
node _T_609 = and(new_meta.hit, _T_608)
node _T_610 = not(new_skipProbe)
node _T_611 = and(new_meta.clients, _T_610)
node _T_612 = neq(_T_611, UInt<1>(0h0))
node _T_613 = and(_T_609, _T_612)
node _T_614 = and(UInt<1>(0h1), _T_613)
when _T_614 :
connect s_pprobe, UInt<1>(0h0)
connect w_pprobeackfirst, UInt<1>(0h0)
connect w_pprobeacklast, UInt<1>(0h0)
connect w_pprobeack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_615 = eq(new_request.opcode, UInt<3>(0h6))
node _T_616 = eq(new_request.opcode, UInt<3>(0h7))
node _T_617 = or(_T_615, _T_616)
when _T_617 :
connect w_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_618 = bits(new_request.opcode, 2, 2)
node _T_619 = eq(_T_618, UInt<1>(0h0))
node _T_620 = and(_T_619, new_meta.hit)
node _T_621 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_622 = and(_T_620, _T_621)
when _T_622 :
connect s_writeback, UInt<1>(0h0) | module MSHR_6( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [7:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [9:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [2:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [7:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [7:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [7:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [7:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [7:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [7:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [7:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [12:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [9:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
reg [12:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [2:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire req_clientBit = request_source == 8'hA0; // @[Parameters.scala:46:9]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire probe_bit = io_sinkc_bits_source_0 == 8'hA0; // @[Parameters.scala:46:9]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [7:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire new_clientBit = new_request_source == 8'hA0; // @[Parameters.scala:46:9]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to this FIRRTL code module TLWidthWidget1 :
input clock : Clock
input reset : Reset
output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
inst monitor of TLMonitor_16
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in
node _hasData_opdata_T = bits(anonIn.a.bits.opcode, 2, 2)
node hasData = eq(_hasData_opdata_T, UInt<1>(0h0))
node _limit_T = dshl(UInt<3>(0h7), anonIn.a.bits.size)
node _limit_T_1 = bits(_limit_T, 2, 0)
node _limit_T_2 = not(_limit_T_1)
node limit = shr(_limit_T_2, 0)
regreset count : UInt<3>, clock, reset, UInt<3>(0h0)
node first = eq(count, UInt<1>(0h0))
node _last_T = eq(count, limit)
node _last_T_1 = eq(hasData, UInt<1>(0h0))
node last = or(_last_T, _last_T_1)
node _enable_T = xor(count, UInt<1>(0h0))
node _enable_T_1 = and(_enable_T, limit)
node _enable_T_2 = orr(_enable_T_1)
node enable_0 = eq(_enable_T_2, UInt<1>(0h0))
node _enable_T_3 = xor(count, UInt<1>(0h1))
node _enable_T_4 = and(_enable_T_3, limit)
node _enable_T_5 = orr(_enable_T_4)
node enable_1 = eq(_enable_T_5, UInt<1>(0h0))
node _enable_T_6 = xor(count, UInt<2>(0h2))
node _enable_T_7 = and(_enable_T_6, limit)
node _enable_T_8 = orr(_enable_T_7)
node enable_2 = eq(_enable_T_8, UInt<1>(0h0))
node _enable_T_9 = xor(count, UInt<2>(0h3))
node _enable_T_10 = and(_enable_T_9, limit)
node _enable_T_11 = orr(_enable_T_10)
node enable_3 = eq(_enable_T_11, UInt<1>(0h0))
node _enable_T_12 = xor(count, UInt<3>(0h4))
node _enable_T_13 = and(_enable_T_12, limit)
node _enable_T_14 = orr(_enable_T_13)
node enable_4 = eq(_enable_T_14, UInt<1>(0h0))
node _enable_T_15 = xor(count, UInt<3>(0h5))
node _enable_T_16 = and(_enable_T_15, limit)
node _enable_T_17 = orr(_enable_T_16)
node enable_5 = eq(_enable_T_17, UInt<1>(0h0))
node _enable_T_18 = xor(count, UInt<3>(0h6))
node _enable_T_19 = and(_enable_T_18, limit)
node _enable_T_20 = orr(_enable_T_19)
node enable_6 = eq(_enable_T_20, UInt<1>(0h0))
node _enable_T_21 = xor(count, UInt<3>(0h7))
node _enable_T_22 = and(_enable_T_21, limit)
node _enable_T_23 = orr(_enable_T_22)
node enable_7 = eq(_enable_T_23, UInt<1>(0h0))
regreset corrupt_reg : UInt<1>, clock, reset, UInt<1>(0h0)
node corrupt_out = or(anonIn.a.bits.corrupt, corrupt_reg)
node _T = and(anonIn.a.ready, anonIn.a.valid)
when _T :
node _count_T = add(count, UInt<1>(0h1))
node _count_T_1 = tail(_count_T, 1)
connect count, _count_T_1
connect corrupt_reg, corrupt_out
when last :
connect count, UInt<1>(0h0)
connect corrupt_reg, UInt<1>(0h0)
node _anonIn_a_ready_T = eq(last, UInt<1>(0h0))
node _anonIn_a_ready_T_1 = or(anonOut.a.ready, _anonIn_a_ready_T)
connect anonIn.a.ready, _anonIn_a_ready_T_1
node _anonOut_a_valid_T = and(anonIn.a.valid, last)
connect anonOut.a.valid, _anonOut_a_valid_T
connect anonOut.a.bits, anonIn.a.bits
regreset anonOut_a_bits_data_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0)
node _anonOut_a_bits_data_masked_enable_T = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_data_masked_enable_0 = or(enable_0, _anonOut_a_bits_data_masked_enable_T)
node _anonOut_a_bits_data_masked_enable_T_1 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_data_masked_enable_1 = or(enable_1, _anonOut_a_bits_data_masked_enable_T_1)
node _anonOut_a_bits_data_masked_enable_T_2 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_data_masked_enable_2 = or(enable_2, _anonOut_a_bits_data_masked_enable_T_2)
node _anonOut_a_bits_data_masked_enable_T_3 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_data_masked_enable_3 = or(enable_3, _anonOut_a_bits_data_masked_enable_T_3)
node _anonOut_a_bits_data_masked_enable_T_4 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_data_masked_enable_4 = or(enable_4, _anonOut_a_bits_data_masked_enable_T_4)
node _anonOut_a_bits_data_masked_enable_T_5 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_data_masked_enable_5 = or(enable_5, _anonOut_a_bits_data_masked_enable_T_5)
node _anonOut_a_bits_data_masked_enable_T_6 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_data_masked_enable_6 = or(enable_6, _anonOut_a_bits_data_masked_enable_T_6)
node _anonOut_a_bits_data_masked_enable_T_7 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_data_masked_enable_7 = or(enable_7, _anonOut_a_bits_data_masked_enable_T_7)
wire anonOut_a_bits_data_odata_0 : UInt
connect anonOut_a_bits_data_odata_0, anonIn.a.bits.data
wire anonOut_a_bits_data_odata_1 : UInt
connect anonOut_a_bits_data_odata_1, anonIn.a.bits.data
wire anonOut_a_bits_data_odata_2 : UInt
connect anonOut_a_bits_data_odata_2, anonIn.a.bits.data
wire anonOut_a_bits_data_odata_3 : UInt
connect anonOut_a_bits_data_odata_3, anonIn.a.bits.data
wire anonOut_a_bits_data_odata_4 : UInt
connect anonOut_a_bits_data_odata_4, anonIn.a.bits.data
wire anonOut_a_bits_data_odata_5 : UInt
connect anonOut_a_bits_data_odata_5, anonIn.a.bits.data
wire anonOut_a_bits_data_odata_6 : UInt
connect anonOut_a_bits_data_odata_6, anonIn.a.bits.data
wire anonOut_a_bits_data_odata_7 : UInt
connect anonOut_a_bits_data_odata_7, anonIn.a.bits.data
reg anonOut_a_bits_data_rdata : UInt<8>[7], clock
node anonOut_a_bits_data_mdata_0 = mux(anonOut_a_bits_data_masked_enable_0, anonOut_a_bits_data_odata_0, anonOut_a_bits_data_rdata[0])
node anonOut_a_bits_data_mdata_1 = mux(anonOut_a_bits_data_masked_enable_1, anonOut_a_bits_data_odata_1, anonOut_a_bits_data_rdata[1])
node anonOut_a_bits_data_mdata_2 = mux(anonOut_a_bits_data_masked_enable_2, anonOut_a_bits_data_odata_2, anonOut_a_bits_data_rdata[2])
node anonOut_a_bits_data_mdata_3 = mux(anonOut_a_bits_data_masked_enable_3, anonOut_a_bits_data_odata_3, anonOut_a_bits_data_rdata[3])
node anonOut_a_bits_data_mdata_4 = mux(anonOut_a_bits_data_masked_enable_4, anonOut_a_bits_data_odata_4, anonOut_a_bits_data_rdata[4])
node anonOut_a_bits_data_mdata_5 = mux(anonOut_a_bits_data_masked_enable_5, anonOut_a_bits_data_odata_5, anonOut_a_bits_data_rdata[5])
node anonOut_a_bits_data_mdata_6 = mux(anonOut_a_bits_data_masked_enable_6, anonOut_a_bits_data_odata_6, anonOut_a_bits_data_rdata[6])
node anonOut_a_bits_data_mdata_7 = mux(anonOut_a_bits_data_masked_enable_7, anonOut_a_bits_data_odata_7, anonIn.a.bits.data)
node _anonOut_a_bits_data_T = and(anonIn.a.ready, anonIn.a.valid)
node _anonOut_a_bits_data_T_1 = eq(last, UInt<1>(0h0))
node _anonOut_a_bits_data_T_2 = and(_anonOut_a_bits_data_T, _anonOut_a_bits_data_T_1)
when _anonOut_a_bits_data_T_2 :
connect anonOut_a_bits_data_rdata_written_once, UInt<1>(0h1)
connect anonOut_a_bits_data_rdata[0], anonOut_a_bits_data_mdata_0
connect anonOut_a_bits_data_rdata[1], anonOut_a_bits_data_mdata_1
connect anonOut_a_bits_data_rdata[2], anonOut_a_bits_data_mdata_2
connect anonOut_a_bits_data_rdata[3], anonOut_a_bits_data_mdata_3
connect anonOut_a_bits_data_rdata[4], anonOut_a_bits_data_mdata_4
connect anonOut_a_bits_data_rdata[5], anonOut_a_bits_data_mdata_5
connect anonOut_a_bits_data_rdata[6], anonOut_a_bits_data_mdata_6
node anonOut_a_bits_data_lo_lo = cat(anonOut_a_bits_data_mdata_1, anonOut_a_bits_data_mdata_0)
node anonOut_a_bits_data_lo_hi = cat(anonOut_a_bits_data_mdata_3, anonOut_a_bits_data_mdata_2)
node anonOut_a_bits_data_lo = cat(anonOut_a_bits_data_lo_hi, anonOut_a_bits_data_lo_lo)
node anonOut_a_bits_data_hi_lo = cat(anonOut_a_bits_data_mdata_5, anonOut_a_bits_data_mdata_4)
node anonOut_a_bits_data_hi_hi = cat(anonOut_a_bits_data_mdata_7, anonOut_a_bits_data_mdata_6)
node anonOut_a_bits_data_hi = cat(anonOut_a_bits_data_hi_hi, anonOut_a_bits_data_hi_lo)
node _anonOut_a_bits_data_T_3 = cat(anonOut_a_bits_data_hi, anonOut_a_bits_data_lo)
connect anonOut.a.bits.data, _anonOut_a_bits_data_T_3
connect anonOut.a.bits.corrupt, corrupt_out
node _anonOut_a_bits_mask_sizeOH_T = or(anonOut.a.bits.size, UInt<3>(0h0))
node anonOut_a_bits_mask_sizeOH_shiftAmount = bits(_anonOut_a_bits_mask_sizeOH_T, 1, 0)
node _anonOut_a_bits_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), anonOut_a_bits_mask_sizeOH_shiftAmount)
node _anonOut_a_bits_mask_sizeOH_T_2 = bits(_anonOut_a_bits_mask_sizeOH_T_1, 2, 0)
node anonOut_a_bits_mask_sizeOH = or(_anonOut_a_bits_mask_sizeOH_T_2, UInt<1>(0h1))
node anonOut_a_bits_mask_sub_sub_sub_0_1 = geq(anonOut.a.bits.size, UInt<2>(0h3))
node anonOut_a_bits_mask_sub_sub_size = bits(anonOut_a_bits_mask_sizeOH, 2, 2)
node anonOut_a_bits_mask_sub_sub_bit = bits(anonOut.a.bits.address, 2, 2)
node anonOut_a_bits_mask_sub_sub_nbit = eq(anonOut_a_bits_mask_sub_sub_bit, UInt<1>(0h0))
node anonOut_a_bits_mask_sub_sub_0_2 = and(UInt<1>(0h1), anonOut_a_bits_mask_sub_sub_nbit)
node _anonOut_a_bits_mask_sub_sub_acc_T = and(anonOut_a_bits_mask_sub_sub_size, anonOut_a_bits_mask_sub_sub_0_2)
node anonOut_a_bits_mask_sub_sub_0_1 = or(anonOut_a_bits_mask_sub_sub_sub_0_1, _anonOut_a_bits_mask_sub_sub_acc_T)
node anonOut_a_bits_mask_sub_sub_1_2 = and(UInt<1>(0h1), anonOut_a_bits_mask_sub_sub_bit)
node _anonOut_a_bits_mask_sub_sub_acc_T_1 = and(anonOut_a_bits_mask_sub_sub_size, anonOut_a_bits_mask_sub_sub_1_2)
node anonOut_a_bits_mask_sub_sub_1_1 = or(anonOut_a_bits_mask_sub_sub_sub_0_1, _anonOut_a_bits_mask_sub_sub_acc_T_1)
node anonOut_a_bits_mask_sub_size = bits(anonOut_a_bits_mask_sizeOH, 1, 1)
node anonOut_a_bits_mask_sub_bit = bits(anonOut.a.bits.address, 1, 1)
node anonOut_a_bits_mask_sub_nbit = eq(anonOut_a_bits_mask_sub_bit, UInt<1>(0h0))
node anonOut_a_bits_mask_sub_0_2 = and(anonOut_a_bits_mask_sub_sub_0_2, anonOut_a_bits_mask_sub_nbit)
node _anonOut_a_bits_mask_sub_acc_T = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_0_2)
node anonOut_a_bits_mask_sub_0_1 = or(anonOut_a_bits_mask_sub_sub_0_1, _anonOut_a_bits_mask_sub_acc_T)
node anonOut_a_bits_mask_sub_1_2 = and(anonOut_a_bits_mask_sub_sub_0_2, anonOut_a_bits_mask_sub_bit)
node _anonOut_a_bits_mask_sub_acc_T_1 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_1_2)
node anonOut_a_bits_mask_sub_1_1 = or(anonOut_a_bits_mask_sub_sub_0_1, _anonOut_a_bits_mask_sub_acc_T_1)
node anonOut_a_bits_mask_sub_2_2 = and(anonOut_a_bits_mask_sub_sub_1_2, anonOut_a_bits_mask_sub_nbit)
node _anonOut_a_bits_mask_sub_acc_T_2 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_2_2)
node anonOut_a_bits_mask_sub_2_1 = or(anonOut_a_bits_mask_sub_sub_1_1, _anonOut_a_bits_mask_sub_acc_T_2)
node anonOut_a_bits_mask_sub_3_2 = and(anonOut_a_bits_mask_sub_sub_1_2, anonOut_a_bits_mask_sub_bit)
node _anonOut_a_bits_mask_sub_acc_T_3 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_3_2)
node anonOut_a_bits_mask_sub_3_1 = or(anonOut_a_bits_mask_sub_sub_1_1, _anonOut_a_bits_mask_sub_acc_T_3)
node anonOut_a_bits_mask_size = bits(anonOut_a_bits_mask_sizeOH, 0, 0)
node anonOut_a_bits_mask_bit = bits(anonOut.a.bits.address, 0, 0)
node anonOut_a_bits_mask_nbit = eq(anonOut_a_bits_mask_bit, UInt<1>(0h0))
node anonOut_a_bits_mask_eq = and(anonOut_a_bits_mask_sub_0_2, anonOut_a_bits_mask_nbit)
node _anonOut_a_bits_mask_acc_T = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq)
node anonOut_a_bits_mask_acc = or(anonOut_a_bits_mask_sub_0_1, _anonOut_a_bits_mask_acc_T)
node anonOut_a_bits_mask_eq_1 = and(anonOut_a_bits_mask_sub_0_2, anonOut_a_bits_mask_bit)
node _anonOut_a_bits_mask_acc_T_1 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_1)
node anonOut_a_bits_mask_acc_1 = or(anonOut_a_bits_mask_sub_0_1, _anonOut_a_bits_mask_acc_T_1)
node anonOut_a_bits_mask_eq_2 = and(anonOut_a_bits_mask_sub_1_2, anonOut_a_bits_mask_nbit)
node _anonOut_a_bits_mask_acc_T_2 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_2)
node anonOut_a_bits_mask_acc_2 = or(anonOut_a_bits_mask_sub_1_1, _anonOut_a_bits_mask_acc_T_2)
node anonOut_a_bits_mask_eq_3 = and(anonOut_a_bits_mask_sub_1_2, anonOut_a_bits_mask_bit)
node _anonOut_a_bits_mask_acc_T_3 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_3)
node anonOut_a_bits_mask_acc_3 = or(anonOut_a_bits_mask_sub_1_1, _anonOut_a_bits_mask_acc_T_3)
node anonOut_a_bits_mask_eq_4 = and(anonOut_a_bits_mask_sub_2_2, anonOut_a_bits_mask_nbit)
node _anonOut_a_bits_mask_acc_T_4 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_4)
node anonOut_a_bits_mask_acc_4 = or(anonOut_a_bits_mask_sub_2_1, _anonOut_a_bits_mask_acc_T_4)
node anonOut_a_bits_mask_eq_5 = and(anonOut_a_bits_mask_sub_2_2, anonOut_a_bits_mask_bit)
node _anonOut_a_bits_mask_acc_T_5 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_5)
node anonOut_a_bits_mask_acc_5 = or(anonOut_a_bits_mask_sub_2_1, _anonOut_a_bits_mask_acc_T_5)
node anonOut_a_bits_mask_eq_6 = and(anonOut_a_bits_mask_sub_3_2, anonOut_a_bits_mask_nbit)
node _anonOut_a_bits_mask_acc_T_6 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_6)
node anonOut_a_bits_mask_acc_6 = or(anonOut_a_bits_mask_sub_3_1, _anonOut_a_bits_mask_acc_T_6)
node anonOut_a_bits_mask_eq_7 = and(anonOut_a_bits_mask_sub_3_2, anonOut_a_bits_mask_bit)
node _anonOut_a_bits_mask_acc_T_7 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_7)
node anonOut_a_bits_mask_acc_7 = or(anonOut_a_bits_mask_sub_3_1, _anonOut_a_bits_mask_acc_T_7)
node anonOut_a_bits_mask_lo_lo = cat(anonOut_a_bits_mask_acc_1, anonOut_a_bits_mask_acc)
node anonOut_a_bits_mask_lo_hi = cat(anonOut_a_bits_mask_acc_3, anonOut_a_bits_mask_acc_2)
node anonOut_a_bits_mask_lo = cat(anonOut_a_bits_mask_lo_hi, anonOut_a_bits_mask_lo_lo)
node anonOut_a_bits_mask_hi_lo = cat(anonOut_a_bits_mask_acc_5, anonOut_a_bits_mask_acc_4)
node anonOut_a_bits_mask_hi_hi = cat(anonOut_a_bits_mask_acc_7, anonOut_a_bits_mask_acc_6)
node anonOut_a_bits_mask_hi = cat(anonOut_a_bits_mask_hi_hi, anonOut_a_bits_mask_hi_lo)
node _anonOut_a_bits_mask_T = cat(anonOut_a_bits_mask_hi, anonOut_a_bits_mask_lo)
regreset anonOut_a_bits_mask_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0)
node _anonOut_a_bits_mask_masked_enable_T = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_mask_masked_enable_0 = or(enable_0, _anonOut_a_bits_mask_masked_enable_T)
node _anonOut_a_bits_mask_masked_enable_T_1 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_mask_masked_enable_1 = or(enable_1, _anonOut_a_bits_mask_masked_enable_T_1)
node _anonOut_a_bits_mask_masked_enable_T_2 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_mask_masked_enable_2 = or(enable_2, _anonOut_a_bits_mask_masked_enable_T_2)
node _anonOut_a_bits_mask_masked_enable_T_3 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_mask_masked_enable_3 = or(enable_3, _anonOut_a_bits_mask_masked_enable_T_3)
node _anonOut_a_bits_mask_masked_enable_T_4 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_mask_masked_enable_4 = or(enable_4, _anonOut_a_bits_mask_masked_enable_T_4)
node _anonOut_a_bits_mask_masked_enable_T_5 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_mask_masked_enable_5 = or(enable_5, _anonOut_a_bits_mask_masked_enable_T_5)
node _anonOut_a_bits_mask_masked_enable_T_6 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_mask_masked_enable_6 = or(enable_6, _anonOut_a_bits_mask_masked_enable_T_6)
node _anonOut_a_bits_mask_masked_enable_T_7 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_mask_masked_enable_7 = or(enable_7, _anonOut_a_bits_mask_masked_enable_T_7)
wire anonOut_a_bits_mask_odata_0 : UInt
connect anonOut_a_bits_mask_odata_0, anonIn.a.bits.mask
wire anonOut_a_bits_mask_odata_1 : UInt
connect anonOut_a_bits_mask_odata_1, anonIn.a.bits.mask
wire anonOut_a_bits_mask_odata_2 : UInt
connect anonOut_a_bits_mask_odata_2, anonIn.a.bits.mask
wire anonOut_a_bits_mask_odata_3 : UInt
connect anonOut_a_bits_mask_odata_3, anonIn.a.bits.mask
wire anonOut_a_bits_mask_odata_4 : UInt
connect anonOut_a_bits_mask_odata_4, anonIn.a.bits.mask
wire anonOut_a_bits_mask_odata_5 : UInt
connect anonOut_a_bits_mask_odata_5, anonIn.a.bits.mask
wire anonOut_a_bits_mask_odata_6 : UInt
connect anonOut_a_bits_mask_odata_6, anonIn.a.bits.mask
wire anonOut_a_bits_mask_odata_7 : UInt
connect anonOut_a_bits_mask_odata_7, anonIn.a.bits.mask
reg anonOut_a_bits_mask_rdata : UInt<1>[7], clock
node anonOut_a_bits_mask_mdata_0 = mux(anonOut_a_bits_mask_masked_enable_0, anonOut_a_bits_mask_odata_0, anonOut_a_bits_mask_rdata[0])
node anonOut_a_bits_mask_mdata_1 = mux(anonOut_a_bits_mask_masked_enable_1, anonOut_a_bits_mask_odata_1, anonOut_a_bits_mask_rdata[1])
node anonOut_a_bits_mask_mdata_2 = mux(anonOut_a_bits_mask_masked_enable_2, anonOut_a_bits_mask_odata_2, anonOut_a_bits_mask_rdata[2])
node anonOut_a_bits_mask_mdata_3 = mux(anonOut_a_bits_mask_masked_enable_3, anonOut_a_bits_mask_odata_3, anonOut_a_bits_mask_rdata[3])
node anonOut_a_bits_mask_mdata_4 = mux(anonOut_a_bits_mask_masked_enable_4, anonOut_a_bits_mask_odata_4, anonOut_a_bits_mask_rdata[4])
node anonOut_a_bits_mask_mdata_5 = mux(anonOut_a_bits_mask_masked_enable_5, anonOut_a_bits_mask_odata_5, anonOut_a_bits_mask_rdata[5])
node anonOut_a_bits_mask_mdata_6 = mux(anonOut_a_bits_mask_masked_enable_6, anonOut_a_bits_mask_odata_6, anonOut_a_bits_mask_rdata[6])
node anonOut_a_bits_mask_mdata_7 = mux(anonOut_a_bits_mask_masked_enable_7, anonOut_a_bits_mask_odata_7, anonIn.a.bits.mask)
node _anonOut_a_bits_mask_T_1 = and(anonIn.a.ready, anonIn.a.valid)
node _anonOut_a_bits_mask_T_2 = eq(last, UInt<1>(0h0))
node _anonOut_a_bits_mask_T_3 = and(_anonOut_a_bits_mask_T_1, _anonOut_a_bits_mask_T_2)
when _anonOut_a_bits_mask_T_3 :
connect anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h1)
connect anonOut_a_bits_mask_rdata[0], anonOut_a_bits_mask_mdata_0
connect anonOut_a_bits_mask_rdata[1], anonOut_a_bits_mask_mdata_1
connect anonOut_a_bits_mask_rdata[2], anonOut_a_bits_mask_mdata_2
connect anonOut_a_bits_mask_rdata[3], anonOut_a_bits_mask_mdata_3
connect anonOut_a_bits_mask_rdata[4], anonOut_a_bits_mask_mdata_4
connect anonOut_a_bits_mask_rdata[5], anonOut_a_bits_mask_mdata_5
connect anonOut_a_bits_mask_rdata[6], anonOut_a_bits_mask_mdata_6
node anonOut_a_bits_mask_lo_lo_1 = cat(anonOut_a_bits_mask_mdata_1, anonOut_a_bits_mask_mdata_0)
node anonOut_a_bits_mask_lo_hi_1 = cat(anonOut_a_bits_mask_mdata_3, anonOut_a_bits_mask_mdata_2)
node anonOut_a_bits_mask_lo_1 = cat(anonOut_a_bits_mask_lo_hi_1, anonOut_a_bits_mask_lo_lo_1)
node anonOut_a_bits_mask_hi_lo_1 = cat(anonOut_a_bits_mask_mdata_5, anonOut_a_bits_mask_mdata_4)
node anonOut_a_bits_mask_hi_hi_1 = cat(anonOut_a_bits_mask_mdata_7, anonOut_a_bits_mask_mdata_6)
node anonOut_a_bits_mask_hi_1 = cat(anonOut_a_bits_mask_hi_hi_1, anonOut_a_bits_mask_hi_lo_1)
node _anonOut_a_bits_mask_T_4 = cat(anonOut_a_bits_mask_hi_1, anonOut_a_bits_mask_lo_1)
node _anonOut_a_bits_mask_T_5 = not(UInt<8>(0h0))
node _anonOut_a_bits_mask_T_6 = mux(hasData, _anonOut_a_bits_mask_T_4, _anonOut_a_bits_mask_T_5)
node _anonOut_a_bits_mask_T_7 = and(_anonOut_a_bits_mask_T, _anonOut_a_bits_mask_T_6)
connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T_7
wire repeat : UInt<1>
inst repeated_repeater of Repeater_TLBundleD_a32d64s1k3z4u
connect repeated_repeater.clock, clock
connect repeated_repeater.reset, reset
connect repeated_repeater.io.repeat, repeat
connect repeated_repeater.io.enq, anonOut.d
wire cated : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect cated.bits, repeated_repeater.io.deq.bits
connect cated.valid, repeated_repeater.io.deq.valid
connect repeated_repeater.io.deq.ready, cated.ready
node _cated_bits_data_T = bits(repeated_repeater.io.deq.bits.data, 63, 8)
node _cated_bits_data_T_1 = bits(anonOut.d.bits.data, 7, 0)
node _cated_bits_data_T_2 = cat(_cated_bits_data_T, _cated_bits_data_T_1)
connect cated.bits.data, _cated_bits_data_T_2
node repeat_hasData = bits(cated.bits.opcode, 0, 0)
node _repeat_limit_T = dshl(UInt<3>(0h7), cated.bits.size)
node _repeat_limit_T_1 = bits(_repeat_limit_T, 2, 0)
node _repeat_limit_T_2 = not(_repeat_limit_T_1)
node repeat_limit = shr(_repeat_limit_T_2, 0)
regreset repeat_count : UInt<3>, clock, reset, UInt<3>(0h0)
node repeat_first = eq(repeat_count, UInt<1>(0h0))
node _repeat_last_T = eq(repeat_count, repeat_limit)
node _repeat_last_T_1 = eq(repeat_hasData, UInt<1>(0h0))
node repeat_last = or(_repeat_last_T, _repeat_last_T_1)
node _repeat_T = and(anonIn.d.ready, anonIn.d.valid)
when _repeat_T :
node _repeat_count_T = add(repeat_count, UInt<1>(0h1))
node _repeat_count_T_1 = tail(_repeat_count_T, 1)
connect repeat_count, _repeat_count_T_1
when repeat_last :
connect repeat_count, UInt<1>(0h0)
reg repeat_sel_sel_sources : UInt<3>[1], clock
node repeat_sel_sel_a_sel = bits(anonIn.a.bits.address, 2, 0)
node _repeat_sel_sel_T = and(anonIn.a.ready, anonIn.a.valid)
when _repeat_sel_sel_T :
connect repeat_sel_sel_sources[0], repeat_sel_sel_a_sel
node _repeat_sel_sel_bypass_T = eq(anonIn.a.bits.source, UInt<0>(0h0))
node repeat_sel_sel_bypass = and(anonIn.a.valid, _repeat_sel_sel_bypass_T)
reg repeat_sel_hold_r : UInt<3>, clock
when repeat_first :
connect repeat_sel_hold_r, repeat_sel_sel_sources[0]
node repeat_sel_hold = mux(repeat_first, repeat_sel_sel_sources[0], repeat_sel_hold_r)
node _repeat_sel_T = not(repeat_limit)
node repeat_sel = and(repeat_sel_hold, _repeat_sel_T)
node repeat_index = or(repeat_sel, repeat_count)
connect anonIn.d.bits.corrupt, cated.bits.corrupt
connect anonIn.d.bits.data, cated.bits.data
connect anonIn.d.bits.denied, cated.bits.denied
connect anonIn.d.bits.sink, cated.bits.sink
connect anonIn.d.bits.source, cated.bits.source
connect anonIn.d.bits.size, cated.bits.size
connect anonIn.d.bits.param, cated.bits.param
connect anonIn.d.bits.opcode, cated.bits.opcode
connect anonIn.d.valid, cated.valid
connect cated.ready, anonIn.d.ready
node _repeat_anonIn_d_bits_data_mux_T = bits(cated.bits.data, 7, 0)
node _repeat_anonIn_d_bits_data_mux_T_1 = bits(cated.bits.data, 15, 8)
node _repeat_anonIn_d_bits_data_mux_T_2 = bits(cated.bits.data, 23, 16)
node _repeat_anonIn_d_bits_data_mux_T_3 = bits(cated.bits.data, 31, 24)
node _repeat_anonIn_d_bits_data_mux_T_4 = bits(cated.bits.data, 39, 32)
node _repeat_anonIn_d_bits_data_mux_T_5 = bits(cated.bits.data, 47, 40)
node _repeat_anonIn_d_bits_data_mux_T_6 = bits(cated.bits.data, 55, 48)
node _repeat_anonIn_d_bits_data_mux_T_7 = bits(cated.bits.data, 63, 56)
wire repeat_anonIn_d_bits_data_mux : UInt<8>[8]
connect repeat_anonIn_d_bits_data_mux[0], _repeat_anonIn_d_bits_data_mux_T
connect repeat_anonIn_d_bits_data_mux[1], _repeat_anonIn_d_bits_data_mux_T_1
connect repeat_anonIn_d_bits_data_mux[2], _repeat_anonIn_d_bits_data_mux_T_2
connect repeat_anonIn_d_bits_data_mux[3], _repeat_anonIn_d_bits_data_mux_T_3
connect repeat_anonIn_d_bits_data_mux[4], _repeat_anonIn_d_bits_data_mux_T_4
connect repeat_anonIn_d_bits_data_mux[5], _repeat_anonIn_d_bits_data_mux_T_5
connect repeat_anonIn_d_bits_data_mux[6], _repeat_anonIn_d_bits_data_mux_T_6
connect repeat_anonIn_d_bits_data_mux[7], _repeat_anonIn_d_bits_data_mux_T_7
connect anonIn.d.bits.data, repeat_anonIn_d_bits_data_mux[repeat_index]
node _repeat_T_1 = eq(repeat_last, UInt<1>(0h0))
connect repeat, _repeat_T_1
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<8>(0h0)
connect _WIRE.bits.mask, UInt<1>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<8>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_4.bits.sink, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_10.bits.sink, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0) | module TLWidthWidget1( // @[WidthWidget.scala:27:9]
input clock, // @[WidthWidget.scala:27:9]
input reset, // @[WidthWidget.scala:27:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire [63:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26]
wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [7:0] _anonOut_a_bits_mask_T_5 = 8'hFF; // @[WidthWidget.scala:85:119]
wire auto_anon_in_a_bits_mask = 1'h1; // @[WidthWidget.scala:27:9]
wire anonIn_a_bits_mask = 1'h1; // @[MixedNode.scala:551:17]
wire anonOut_a_bits_mask_odata_0 = 1'h1; // @[WidthWidget.scala:65:47]
wire anonOut_a_bits_mask_odata_1 = 1'h1; // @[WidthWidget.scala:65:47]
wire anonOut_a_bits_mask_odata_2 = 1'h1; // @[WidthWidget.scala:65:47]
wire anonOut_a_bits_mask_odata_3 = 1'h1; // @[WidthWidget.scala:65:47]
wire anonOut_a_bits_mask_odata_4 = 1'h1; // @[WidthWidget.scala:65:47]
wire anonOut_a_bits_mask_odata_5 = 1'h1; // @[WidthWidget.scala:65:47]
wire anonOut_a_bits_mask_odata_6 = 1'h1; // @[WidthWidget.scala:65:47]
wire anonOut_a_bits_mask_odata_7 = 1'h1; // @[WidthWidget.scala:65:47]
wire anonOut_a_bits_mask_mdata_7 = 1'h1; // @[WidthWidget.scala:68:88]
wire _repeat_sel_sel_bypass_T = 1'h1; // @[WidthWidget.scala:200:53]
wire [2:0] auto_anon_in_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] anonIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] anonOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17]
wire auto_anon_in_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire anonOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire cated_bits_source = 1'h0; // @[WidthWidget.scala:161:25]
wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9]
wire [7:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9]
wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [7:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9]
wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9]
wire [7:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9]
wire [7:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9]
wire [63:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9]
wire _anonIn_a_ready_T_1; // @[WidthWidget.scala:76:29]
assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9]
wire repeat_sel_sel_bypass = anonIn_a_valid; // @[WidthWidget.scala:200:33]
assign anonOut_a_bits_opcode = anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_size = anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_address = anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] anonOut_a_bits_data_odata_0 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47]
wire [7:0] anonOut_a_bits_data_odata_1 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47]
wire [7:0] anonOut_a_bits_data_odata_2 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47]
wire [7:0] anonOut_a_bits_data_odata_3 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47]
wire [7:0] anonOut_a_bits_data_odata_4 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47]
wire [7:0] anonOut_a_bits_data_odata_5 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47]
wire [7:0] anonOut_a_bits_data_odata_6 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47]
wire [7:0] anonOut_a_bits_data_odata_7 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47]
wire cated_ready = anonIn_d_ready; // @[WidthWidget.scala:161:25]
wire cated_valid; // @[WidthWidget.scala:161:25]
assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25]
assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] cated_bits_param; // @[WidthWidget.scala:161:25]
assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25]
assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] cated_bits_sink; // @[WidthWidget.scala:161:25]
assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
wire cated_bits_denied; // @[WidthWidget.scala:161:25]
assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
wire cated_bits_corrupt; // @[WidthWidget.scala:161:25]
assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire _anonOut_a_valid_T; // @[WidthWidget.scala:77:29]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] _anonOut_a_bits_mask_sizeOH_T = anonOut_a_bits_size; // @[Misc.scala:202:34]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] _anonOut_a_bits_mask_T_7; // @[WidthWidget.scala:85:88]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] _anonOut_a_bits_data_T_3; // @[WidthWidget.scala:73:12]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
wire corrupt_out; // @[WidthWidget.scala:47:36]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9]
wire _hasData_opdata_T = anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire hasData = ~_hasData_opdata_T; // @[Edges.scala:92:{28,37}]
wire [17:0] _limit_T = 18'h7 << anonIn_a_bits_size; // @[package.scala:243:71]
wire [2:0] _limit_T_1 = _limit_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}]
wire [2:0] limit = _limit_T_2; // @[package.scala:243:46]
reg [2:0] count; // @[WidthWidget.scala:40:27]
wire [2:0] _enable_T = count; // @[WidthWidget.scala:40:27, :43:56]
wire first = count == 3'h0; // @[WidthWidget.scala:40:27, :41:26]
wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26]
wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39]
wire last = _last_T | _last_T_1; // @[WidthWidget.scala:42:{26,36,39}]
wire [2:0] _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_2 = |_enable_T_1; // @[WidthWidget.scala:43:{63,72}]
wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}]
wire [2:0] _enable_T_3 = {count[2:1], ~(count[0])}; // @[WidthWidget.scala:40:27, :43:56]
wire [2:0] _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_5 = |_enable_T_4; // @[WidthWidget.scala:43:{63,72}]
wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}]
wire [2:0] _enable_T_6 = {count[2], count[1:0] ^ 2'h2}; // @[WidthWidget.scala:40:27, :43:56]
wire [2:0] _enable_T_7 = _enable_T_6 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_8 = |_enable_T_7; // @[WidthWidget.scala:43:{63,72}]
wire enable_2 = ~_enable_T_8; // @[WidthWidget.scala:43:{47,72}]
wire [2:0] _enable_T_9 = {count[2], ~(count[1:0])}; // @[WidthWidget.scala:40:27, :43:56]
wire [2:0] _enable_T_10 = _enable_T_9 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_11 = |_enable_T_10; // @[WidthWidget.scala:43:{63,72}]
wire enable_3 = ~_enable_T_11; // @[WidthWidget.scala:43:{47,72}]
wire [2:0] _enable_T_12 = count ^ 3'h4; // @[WidthWidget.scala:40:27, :43:56]
wire [2:0] _enable_T_13 = _enable_T_12 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_14 = |_enable_T_13; // @[WidthWidget.scala:43:{63,72}]
wire enable_4 = ~_enable_T_14; // @[WidthWidget.scala:43:{47,72}]
wire [2:0] _enable_T_15 = count ^ 3'h5; // @[WidthWidget.scala:40:27, :43:56]
wire [2:0] _enable_T_16 = _enable_T_15 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_17 = |_enable_T_16; // @[WidthWidget.scala:43:{63,72}]
wire enable_5 = ~_enable_T_17; // @[WidthWidget.scala:43:{47,72}]
wire [2:0] _enable_T_18 = count ^ 3'h6; // @[WidthWidget.scala:40:27, :43:56]
wire [2:0] _enable_T_19 = _enable_T_18 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_20 = |_enable_T_19; // @[WidthWidget.scala:43:{63,72}]
wire enable_6 = ~_enable_T_20; // @[WidthWidget.scala:43:{47,72}]
wire [2:0] _enable_T_21 = ~count; // @[WidthWidget.scala:40:27, :43:56]
wire [2:0] _enable_T_22 = _enable_T_21 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_23 = |_enable_T_22; // @[WidthWidget.scala:43:{63,72}]
wire enable_7 = ~_enable_T_23; // @[WidthWidget.scala:43:{47,72}]
reg corrupt_reg; // @[WidthWidget.scala:45:32]
assign corrupt_out = corrupt_reg; // @[WidthWidget.scala:45:32, :47:36]
assign anonOut_a_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36]
wire _T = anonIn_a_ready & anonIn_a_valid; // @[Decoupled.scala:51:35]
wire _anonOut_a_bits_data_T; // @[Decoupled.scala:51:35]
assign _anonOut_a_bits_data_T = _T; // @[Decoupled.scala:51:35]
wire _anonOut_a_bits_mask_T_1; // @[Decoupled.scala:51:35]
assign _anonOut_a_bits_mask_T_1 = _T; // @[Decoupled.scala:51:35]
wire _repeat_sel_sel_T; // @[Decoupled.scala:51:35]
assign _repeat_sel_sel_T = _T; // @[Decoupled.scala:51:35]
wire [3:0] _count_T = {1'h0, count} + 4'h1; // @[WidthWidget.scala:40:27, :50:24]
wire [2:0] _count_T_1 = _count_T[2:0]; // @[WidthWidget.scala:50:24]
wire _anonIn_a_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32]
assign _anonIn_a_ready_T_1 = anonOut_a_ready | _anonIn_a_ready_T; // @[WidthWidget.scala:76:{29,32}]
assign anonIn_a_ready = _anonIn_a_ready_T_1; // @[WidthWidget.scala:76:29]
assign _anonOut_a_valid_T = anonIn_a_valid & last; // @[WidthWidget.scala:42:36, :77:29]
assign anonOut_a_valid = _anonOut_a_valid_T; // @[WidthWidget.scala:77:29]
reg anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41]
wire _anonOut_a_bits_data_masked_enable_T = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonOut_a_bits_data_masked_enable_0 = enable_0 | _anonOut_a_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonOut_a_bits_data_masked_enable_T_1 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonOut_a_bits_data_masked_enable_1 = enable_1 | _anonOut_a_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonOut_a_bits_data_masked_enable_T_2 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonOut_a_bits_data_masked_enable_2 = enable_2 | _anonOut_a_bits_data_masked_enable_T_2; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonOut_a_bits_data_masked_enable_T_3 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonOut_a_bits_data_masked_enable_3 = enable_3 | _anonOut_a_bits_data_masked_enable_T_3; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonOut_a_bits_data_masked_enable_T_4 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonOut_a_bits_data_masked_enable_4 = enable_4 | _anonOut_a_bits_data_masked_enable_T_4; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonOut_a_bits_data_masked_enable_T_5 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonOut_a_bits_data_masked_enable_5 = enable_5 | _anonOut_a_bits_data_masked_enable_T_5; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonOut_a_bits_data_masked_enable_T_6 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonOut_a_bits_data_masked_enable_6 = enable_6 | _anonOut_a_bits_data_masked_enable_T_6; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonOut_a_bits_data_masked_enable_T_7 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonOut_a_bits_data_masked_enable_7 = enable_7 | _anonOut_a_bits_data_masked_enable_T_7; // @[WidthWidget.scala:43:47, :63:{42,45}]
reg [7:0] anonOut_a_bits_data_rdata_0; // @[WidthWidget.scala:66:24]
reg [7:0] anonOut_a_bits_data_rdata_1; // @[WidthWidget.scala:66:24]
reg [7:0] anonOut_a_bits_data_rdata_2; // @[WidthWidget.scala:66:24]
reg [7:0] anonOut_a_bits_data_rdata_3; // @[WidthWidget.scala:66:24]
reg [7:0] anonOut_a_bits_data_rdata_4; // @[WidthWidget.scala:66:24]
reg [7:0] anonOut_a_bits_data_rdata_5; // @[WidthWidget.scala:66:24]
reg [7:0] anonOut_a_bits_data_rdata_6; // @[WidthWidget.scala:66:24]
wire [7:0] anonOut_a_bits_data_mdata_0 = anonOut_a_bits_data_masked_enable_0 ? anonOut_a_bits_data_odata_0 : anonOut_a_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [7:0] anonOut_a_bits_data_mdata_1 = anonOut_a_bits_data_masked_enable_1 ? anonOut_a_bits_data_odata_1 : anonOut_a_bits_data_rdata_1; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [7:0] anonOut_a_bits_data_mdata_2 = anonOut_a_bits_data_masked_enable_2 ? anonOut_a_bits_data_odata_2 : anonOut_a_bits_data_rdata_2; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [7:0] anonOut_a_bits_data_mdata_3 = anonOut_a_bits_data_masked_enable_3 ? anonOut_a_bits_data_odata_3 : anonOut_a_bits_data_rdata_3; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [7:0] anonOut_a_bits_data_mdata_4 = anonOut_a_bits_data_masked_enable_4 ? anonOut_a_bits_data_odata_4 : anonOut_a_bits_data_rdata_4; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [7:0] anonOut_a_bits_data_mdata_5 = anonOut_a_bits_data_masked_enable_5 ? anonOut_a_bits_data_odata_5 : anonOut_a_bits_data_rdata_5; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [7:0] anonOut_a_bits_data_mdata_6 = anonOut_a_bits_data_masked_enable_6 ? anonOut_a_bits_data_odata_6 : anonOut_a_bits_data_rdata_6; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [7:0] anonOut_a_bits_data_mdata_7 = anonOut_a_bits_data_masked_enable_7 ? anonOut_a_bits_data_odata_7 : anonIn_a_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88]
wire _anonOut_a_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32]
wire _anonOut_a_bits_data_T_2 = _anonOut_a_bits_data_T & _anonOut_a_bits_data_T_1; // @[Decoupled.scala:51:35]
wire [15:0] anonOut_a_bits_data_lo_lo = {anonOut_a_bits_data_mdata_1, anonOut_a_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12]
wire [15:0] anonOut_a_bits_data_lo_hi = {anonOut_a_bits_data_mdata_3, anonOut_a_bits_data_mdata_2}; // @[WidthWidget.scala:68:88, :73:12]
wire [31:0] anonOut_a_bits_data_lo = {anonOut_a_bits_data_lo_hi, anonOut_a_bits_data_lo_lo}; // @[WidthWidget.scala:73:12]
wire [15:0] anonOut_a_bits_data_hi_lo = {anonOut_a_bits_data_mdata_5, anonOut_a_bits_data_mdata_4}; // @[WidthWidget.scala:68:88, :73:12]
wire [15:0] anonOut_a_bits_data_hi_hi = {anonOut_a_bits_data_mdata_7, anonOut_a_bits_data_mdata_6}; // @[WidthWidget.scala:68:88, :73:12]
wire [31:0] anonOut_a_bits_data_hi = {anonOut_a_bits_data_hi_hi, anonOut_a_bits_data_hi_lo}; // @[WidthWidget.scala:73:12]
assign _anonOut_a_bits_data_T_3 = {anonOut_a_bits_data_hi, anonOut_a_bits_data_lo}; // @[WidthWidget.scala:73:12]
assign anonOut_a_bits_data = _anonOut_a_bits_data_T_3; // @[WidthWidget.scala:73:12]
wire [1:0] anonOut_a_bits_mask_sizeOH_shiftAmount = _anonOut_a_bits_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _anonOut_a_bits_mask_sizeOH_T_1 = 4'h1 << anonOut_a_bits_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _anonOut_a_bits_mask_sizeOH_T_2 = _anonOut_a_bits_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] anonOut_a_bits_mask_sizeOH = {_anonOut_a_bits_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire anonOut_a_bits_mask_sub_sub_sub_0_1 = anonOut_a_bits_size > 4'h2; // @[Misc.scala:206:21]
wire anonOut_a_bits_mask_sub_sub_size = anonOut_a_bits_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire anonOut_a_bits_mask_sub_sub_bit = anonOut_a_bits_address[2]; // @[Misc.scala:210:26]
wire anonOut_a_bits_mask_sub_sub_1_2 = anonOut_a_bits_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire anonOut_a_bits_mask_sub_sub_nbit = ~anonOut_a_bits_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire anonOut_a_bits_mask_sub_sub_0_2 = anonOut_a_bits_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_sub_sub_acc_T = anonOut_a_bits_mask_sub_sub_size & anonOut_a_bits_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_sub_sub_0_1 = anonOut_a_bits_mask_sub_sub_sub_0_1 | _anonOut_a_bits_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _anonOut_a_bits_mask_sub_sub_acc_T_1 = anonOut_a_bits_mask_sub_sub_size & anonOut_a_bits_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_sub_sub_1_1 = anonOut_a_bits_mask_sub_sub_sub_0_1 | _anonOut_a_bits_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire anonOut_a_bits_mask_sub_size = anonOut_a_bits_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire anonOut_a_bits_mask_sub_bit = anonOut_a_bits_address[1]; // @[Misc.scala:210:26]
wire anonOut_a_bits_mask_sub_nbit = ~anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire anonOut_a_bits_mask_sub_0_2 = anonOut_a_bits_mask_sub_sub_0_2 & anonOut_a_bits_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_sub_acc_T = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_sub_0_1 = anonOut_a_bits_mask_sub_sub_0_1 | _anonOut_a_bits_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_sub_1_2 = anonOut_a_bits_mask_sub_sub_0_2 & anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _anonOut_a_bits_mask_sub_acc_T_1 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_sub_1_1 = anonOut_a_bits_mask_sub_sub_0_1 | _anonOut_a_bits_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_sub_2_2 = anonOut_a_bits_mask_sub_sub_1_2 & anonOut_a_bits_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_sub_acc_T_2 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_sub_2_1 = anonOut_a_bits_mask_sub_sub_1_1 | _anonOut_a_bits_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_sub_3_2 = anonOut_a_bits_mask_sub_sub_1_2 & anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _anonOut_a_bits_mask_sub_acc_T_3 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_sub_3_1 = anonOut_a_bits_mask_sub_sub_1_1 | _anonOut_a_bits_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_size = anonOut_a_bits_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire anonOut_a_bits_mask_bit = anonOut_a_bits_address[0]; // @[Misc.scala:210:26]
wire anonOut_a_bits_mask_nbit = ~anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :211:20]
wire anonOut_a_bits_mask_eq = anonOut_a_bits_mask_sub_0_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_acc_T = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc = anonOut_a_bits_mask_sub_0_1 | _anonOut_a_bits_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_1 = anonOut_a_bits_mask_sub_0_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _anonOut_a_bits_mask_acc_T_1 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_1 = anonOut_a_bits_mask_sub_0_1 | _anonOut_a_bits_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_2 = anonOut_a_bits_mask_sub_1_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_acc_T_2 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_2 = anonOut_a_bits_mask_sub_1_1 | _anonOut_a_bits_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_3 = anonOut_a_bits_mask_sub_1_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _anonOut_a_bits_mask_acc_T_3 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_3 = anonOut_a_bits_mask_sub_1_1 | _anonOut_a_bits_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_4 = anonOut_a_bits_mask_sub_2_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_acc_T_4 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_4 = anonOut_a_bits_mask_sub_2_1 | _anonOut_a_bits_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_5 = anonOut_a_bits_mask_sub_2_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _anonOut_a_bits_mask_acc_T_5 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_5 = anonOut_a_bits_mask_sub_2_1 | _anonOut_a_bits_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_6 = anonOut_a_bits_mask_sub_3_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_acc_T_6 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_6 = anonOut_a_bits_mask_sub_3_1 | _anonOut_a_bits_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_7 = anonOut_a_bits_mask_sub_3_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _anonOut_a_bits_mask_acc_T_7 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_7 = anonOut_a_bits_mask_sub_3_1 | _anonOut_a_bits_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] anonOut_a_bits_mask_lo_lo = {anonOut_a_bits_mask_acc_1, anonOut_a_bits_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] anonOut_a_bits_mask_lo_hi = {anonOut_a_bits_mask_acc_3, anonOut_a_bits_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] anonOut_a_bits_mask_lo = {anonOut_a_bits_mask_lo_hi, anonOut_a_bits_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] anonOut_a_bits_mask_hi_lo = {anonOut_a_bits_mask_acc_5, anonOut_a_bits_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] anonOut_a_bits_mask_hi_hi = {anonOut_a_bits_mask_acc_7, anonOut_a_bits_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] anonOut_a_bits_mask_hi = {anonOut_a_bits_mask_hi_hi, anonOut_a_bits_mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] _anonOut_a_bits_mask_T = {anonOut_a_bits_mask_hi, anonOut_a_bits_mask_lo}; // @[Misc.scala:222:10]
reg anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41]
wire _anonOut_a_bits_mask_masked_enable_T = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonOut_a_bits_mask_masked_enable_0 = enable_0 | _anonOut_a_bits_mask_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonOut_a_bits_mask_masked_enable_T_1 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonOut_a_bits_mask_masked_enable_1 = enable_1 | _anonOut_a_bits_mask_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonOut_a_bits_mask_masked_enable_T_2 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonOut_a_bits_mask_masked_enable_2 = enable_2 | _anonOut_a_bits_mask_masked_enable_T_2; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonOut_a_bits_mask_masked_enable_T_3 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonOut_a_bits_mask_masked_enable_3 = enable_3 | _anonOut_a_bits_mask_masked_enable_T_3; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonOut_a_bits_mask_masked_enable_T_4 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonOut_a_bits_mask_masked_enable_4 = enable_4 | _anonOut_a_bits_mask_masked_enable_T_4; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonOut_a_bits_mask_masked_enable_T_5 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonOut_a_bits_mask_masked_enable_5 = enable_5 | _anonOut_a_bits_mask_masked_enable_T_5; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonOut_a_bits_mask_masked_enable_T_6 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonOut_a_bits_mask_masked_enable_6 = enable_6 | _anonOut_a_bits_mask_masked_enable_T_6; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonOut_a_bits_mask_masked_enable_T_7 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonOut_a_bits_mask_masked_enable_7 = enable_7 | _anonOut_a_bits_mask_masked_enable_T_7; // @[WidthWidget.scala:43:47, :63:{42,45}]
reg anonOut_a_bits_mask_rdata_0; // @[WidthWidget.scala:66:24]
reg anonOut_a_bits_mask_rdata_1; // @[WidthWidget.scala:66:24]
reg anonOut_a_bits_mask_rdata_2; // @[WidthWidget.scala:66:24]
reg anonOut_a_bits_mask_rdata_3; // @[WidthWidget.scala:66:24]
reg anonOut_a_bits_mask_rdata_4; // @[WidthWidget.scala:66:24]
reg anonOut_a_bits_mask_rdata_5; // @[WidthWidget.scala:66:24]
reg anonOut_a_bits_mask_rdata_6; // @[WidthWidget.scala:66:24]
wire anonOut_a_bits_mask_mdata_0 = anonOut_a_bits_mask_masked_enable_0 | anonOut_a_bits_mask_rdata_0; // @[WidthWidget.scala:63:42, :66:24, :68:88]
wire anonOut_a_bits_mask_mdata_1 = anonOut_a_bits_mask_masked_enable_1 | anonOut_a_bits_mask_rdata_1; // @[WidthWidget.scala:63:42, :66:24, :68:88]
wire anonOut_a_bits_mask_mdata_2 = anonOut_a_bits_mask_masked_enable_2 | anonOut_a_bits_mask_rdata_2; // @[WidthWidget.scala:63:42, :66:24, :68:88]
wire anonOut_a_bits_mask_mdata_3 = anonOut_a_bits_mask_masked_enable_3 | anonOut_a_bits_mask_rdata_3; // @[WidthWidget.scala:63:42, :66:24, :68:88]
wire anonOut_a_bits_mask_mdata_4 = anonOut_a_bits_mask_masked_enable_4 | anonOut_a_bits_mask_rdata_4; // @[WidthWidget.scala:63:42, :66:24, :68:88]
wire anonOut_a_bits_mask_mdata_5 = anonOut_a_bits_mask_masked_enable_5 | anonOut_a_bits_mask_rdata_5; // @[WidthWidget.scala:63:42, :66:24, :68:88]
wire anonOut_a_bits_mask_mdata_6 = anonOut_a_bits_mask_masked_enable_6 | anonOut_a_bits_mask_rdata_6; // @[WidthWidget.scala:63:42, :66:24, :68:88]
wire _anonOut_a_bits_mask_T_2 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32]
wire _anonOut_a_bits_mask_T_3 = _anonOut_a_bits_mask_T_1 & _anonOut_a_bits_mask_T_2; // @[Decoupled.scala:51:35]
wire [1:0] anonOut_a_bits_mask_lo_lo_1 = {anonOut_a_bits_mask_mdata_1, anonOut_a_bits_mask_mdata_0}; // @[WidthWidget.scala:68:88, :73:12]
wire [1:0] anonOut_a_bits_mask_lo_hi_1 = {anonOut_a_bits_mask_mdata_3, anonOut_a_bits_mask_mdata_2}; // @[WidthWidget.scala:68:88, :73:12]
wire [3:0] anonOut_a_bits_mask_lo_1 = {anonOut_a_bits_mask_lo_hi_1, anonOut_a_bits_mask_lo_lo_1}; // @[WidthWidget.scala:73:12]
wire [1:0] anonOut_a_bits_mask_hi_lo_1 = {anonOut_a_bits_mask_mdata_5, anonOut_a_bits_mask_mdata_4}; // @[WidthWidget.scala:68:88, :73:12]
wire [1:0] anonOut_a_bits_mask_hi_hi_1 = {1'h1, anonOut_a_bits_mask_mdata_6}; // @[WidthWidget.scala:68:88, :73:12]
wire [3:0] anonOut_a_bits_mask_hi_1 = {anonOut_a_bits_mask_hi_hi_1, anonOut_a_bits_mask_hi_lo_1}; // @[WidthWidget.scala:73:12]
wire [7:0] _anonOut_a_bits_mask_T_4 = {anonOut_a_bits_mask_hi_1, anonOut_a_bits_mask_lo_1}; // @[WidthWidget.scala:73:12]
wire [7:0] _anonOut_a_bits_mask_T_6 = hasData ? _anonOut_a_bits_mask_T_4 : 8'hFF; // @[WidthWidget.scala:73:12, :85:93]
assign _anonOut_a_bits_mask_T_7 = _anonOut_a_bits_mask_T & _anonOut_a_bits_mask_T_6; // @[Misc.scala:222:10]
assign anonOut_a_bits_mask = _anonOut_a_bits_mask_T_7; // @[WidthWidget.scala:85:88]
wire _repeat_T_1; // @[WidthWidget.scala:148:7]
wire repeat_0; // @[WidthWidget.scala:159:26]
assign anonIn_d_valid = cated_valid; // @[WidthWidget.scala:161:25]
assign anonIn_d_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25]
assign anonIn_d_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25]
assign anonIn_d_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25]
assign anonIn_d_bits_sink = cated_bits_sink; // @[WidthWidget.scala:161:25]
assign anonIn_d_bits_denied = cated_bits_denied; // @[WidthWidget.scala:161:25]
wire [63:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39]
assign anonIn_d_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25]
wire [63:0] cated_bits_data; // @[WidthWidget.scala:161:25]
wire [55:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[63:8]; // @[Repeater.scala:36:26]
wire [7:0] _cated_bits_data_T_1 = anonOut_d_bits_data[7:0]; // @[WidthWidget.scala:165:31]
assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31]
assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39]
wire repeat_hasData = cated_bits_opcode[0]; // @[WidthWidget.scala:161:25]
wire [17:0] _repeat_limit_T = 18'h7 << cated_bits_size; // @[package.scala:243:71]
wire [2:0] _repeat_limit_T_1 = _repeat_limit_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}]
wire [2:0] repeat_limit = _repeat_limit_T_2; // @[package.scala:243:46]
reg [2:0] repeat_count; // @[WidthWidget.scala:105:26]
wire repeat_first = repeat_count == 3'h0; // @[WidthWidget.scala:105:26, :106:25]
wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25]
wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38]
wire repeat_last = _repeat_last_T | _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}]
wire _repeat_T = anonIn_d_ready & anonIn_d_valid; // @[Decoupled.scala:51:35]
wire [3:0] _repeat_count_T = {1'h0, repeat_count} + 4'h1; // @[WidthWidget.scala:105:26, :110:24]
wire [2:0] _repeat_count_T_1 = _repeat_count_T[2:0]; // @[WidthWidget.scala:110:24]
reg [2:0] repeat_sel_sel_sources_0; // @[WidthWidget.scala:187:27]
wire [2:0] repeat_sel_sel_a_sel = anonIn_a_bits_address[2:0]; // @[WidthWidget.scala:188:38]
reg [2:0] repeat_sel_hold_r; // @[WidthWidget.scala:121:47]
wire [2:0] repeat_sel_hold = repeat_first ? repeat_sel_sel_sources_0 : repeat_sel_hold_r; // @[WidthWidget.scala:106:25, :121:{25,47}, :187:27]
wire [2:0] _repeat_sel_T = ~repeat_limit; // @[WidthWidget.scala:103:47, :122:18]
wire [2:0] repeat_sel = repeat_sel_hold & _repeat_sel_T; // @[WidthWidget.scala:121:25, :122:{16,18}]
wire [2:0] repeat_index = repeat_sel | repeat_count; // @[WidthWidget.scala:105:26, :122:16, :126:24]
wire [7:0] _repeat_anonIn_d_bits_data_mux_T = cated_bits_data[7:0]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonIn_d_bits_data_mux_0 = _repeat_anonIn_d_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}]
wire [7:0] _repeat_anonIn_d_bits_data_mux_T_1 = cated_bits_data[15:8]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonIn_d_bits_data_mux_1 = _repeat_anonIn_d_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}]
wire [7:0] _repeat_anonIn_d_bits_data_mux_T_2 = cated_bits_data[23:16]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonIn_d_bits_data_mux_2 = _repeat_anonIn_d_bits_data_mux_T_2; // @[WidthWidget.scala:128:{43,55}]
wire [7:0] _repeat_anonIn_d_bits_data_mux_T_3 = cated_bits_data[31:24]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonIn_d_bits_data_mux_3 = _repeat_anonIn_d_bits_data_mux_T_3; // @[WidthWidget.scala:128:{43,55}]
wire [7:0] _repeat_anonIn_d_bits_data_mux_T_4 = cated_bits_data[39:32]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonIn_d_bits_data_mux_4 = _repeat_anonIn_d_bits_data_mux_T_4; // @[WidthWidget.scala:128:{43,55}]
wire [7:0] _repeat_anonIn_d_bits_data_mux_T_5 = cated_bits_data[47:40]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonIn_d_bits_data_mux_5 = _repeat_anonIn_d_bits_data_mux_T_5; // @[WidthWidget.scala:128:{43,55}]
wire [7:0] _repeat_anonIn_d_bits_data_mux_T_6 = cated_bits_data[55:48]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonIn_d_bits_data_mux_6 = _repeat_anonIn_d_bits_data_mux_T_6; // @[WidthWidget.scala:128:{43,55}]
wire [7:0] _repeat_anonIn_d_bits_data_mux_T_7 = cated_bits_data[63:56]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonIn_d_bits_data_mux_7 = _repeat_anonIn_d_bits_data_mux_T_7; // @[WidthWidget.scala:128:{43,55}]
wire [7:0][7:0] _GEN = {{repeat_anonIn_d_bits_data_mux_7}, {repeat_anonIn_d_bits_data_mux_6}, {repeat_anonIn_d_bits_data_mux_5}, {repeat_anonIn_d_bits_data_mux_4}, {repeat_anonIn_d_bits_data_mux_3}, {repeat_anonIn_d_bits_data_mux_2}, {repeat_anonIn_d_bits_data_mux_1}, {repeat_anonIn_d_bits_data_mux_0}}; // @[WidthWidget.scala:128:43, :137:30]
assign anonIn_d_bits_data = _GEN[repeat_index]; // @[WidthWidget.scala:126:24, :137:30]
assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7]
assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26]
always @(posedge clock) begin // @[WidthWidget.scala:27:9]
if (reset) begin // @[WidthWidget.scala:27:9]
count <= 3'h0; // @[WidthWidget.scala:40:27]
corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32]
anonOut_a_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41]
anonOut_a_bits_mask_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41]
repeat_count <= 3'h0; // @[WidthWidget.scala:105:26]
end
else begin // @[WidthWidget.scala:27:9]
if (_T) begin // @[Decoupled.scala:51:35]
count <= last ? 3'h0 : _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17]
corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :51:21, :52:21, :54:23]
end
anonOut_a_bits_data_rdata_written_once <= _anonOut_a_bits_data_T_2 | anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30]
anonOut_a_bits_mask_rdata_written_once <= _anonOut_a_bits_mask_T_3 | anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30]
if (_repeat_T) // @[Decoupled.scala:51:35]
repeat_count <= repeat_last ? 3'h0 : _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}]
end
if (_anonOut_a_bits_data_T_2) begin // @[WidthWidget.scala:69:23]
anonOut_a_bits_data_rdata_0 <= anonOut_a_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88]
anonOut_a_bits_data_rdata_1 <= anonOut_a_bits_data_mdata_1; // @[WidthWidget.scala:66:24, :68:88]
anonOut_a_bits_data_rdata_2 <= anonOut_a_bits_data_mdata_2; // @[WidthWidget.scala:66:24, :68:88]
anonOut_a_bits_data_rdata_3 <= anonOut_a_bits_data_mdata_3; // @[WidthWidget.scala:66:24, :68:88]
anonOut_a_bits_data_rdata_4 <= anonOut_a_bits_data_mdata_4; // @[WidthWidget.scala:66:24, :68:88]
anonOut_a_bits_data_rdata_5 <= anonOut_a_bits_data_mdata_5; // @[WidthWidget.scala:66:24, :68:88]
anonOut_a_bits_data_rdata_6 <= anonOut_a_bits_data_mdata_6; // @[WidthWidget.scala:66:24, :68:88]
end
if (_anonOut_a_bits_mask_T_3) begin // @[WidthWidget.scala:69:23]
anonOut_a_bits_mask_rdata_0 <= anonOut_a_bits_mask_mdata_0; // @[WidthWidget.scala:66:24, :68:88]
anonOut_a_bits_mask_rdata_1 <= anonOut_a_bits_mask_mdata_1; // @[WidthWidget.scala:66:24, :68:88]
anonOut_a_bits_mask_rdata_2 <= anonOut_a_bits_mask_mdata_2; // @[WidthWidget.scala:66:24, :68:88]
anonOut_a_bits_mask_rdata_3 <= anonOut_a_bits_mask_mdata_3; // @[WidthWidget.scala:66:24, :68:88]
anonOut_a_bits_mask_rdata_4 <= anonOut_a_bits_mask_mdata_4; // @[WidthWidget.scala:66:24, :68:88]
anonOut_a_bits_mask_rdata_5 <= anonOut_a_bits_mask_mdata_5; // @[WidthWidget.scala:66:24, :68:88]
anonOut_a_bits_mask_rdata_6 <= anonOut_a_bits_mask_mdata_6; // @[WidthWidget.scala:66:24, :68:88]
end
if (_repeat_sel_sel_T) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_0 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (repeat_first) // @[WidthWidget.scala:106:25]
repeat_sel_hold_r <= repeat_sel_sel_sources_0; // @[WidthWidget.scala:121:47, :187:27]
always @(posedge)
TLMonitor_16 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Repeater_TLBundleD_a32d64s1k3z4u repeated_repeater ( // @[Repeater.scala:36:26]
.clock (clock),
.reset (reset),
.io_repeat (repeat_0), // @[WidthWidget.scala:159:26]
.io_enq_ready (anonOut_d_ready),
.io_enq_valid (anonOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (anonOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (anonOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (anonOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (anonOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (anonOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (anonOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (anonOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25]
.io_deq_valid (cated_valid),
.io_deq_bits_opcode (cated_bits_opcode),
.io_deq_bits_param (cated_bits_param),
.io_deq_bits_size (cated_bits_size),
.io_deq_bits_sink (cated_bits_sink),
.io_deq_bits_denied (cated_bits_denied),
.io_deq_bits_data (_repeated_repeater_io_deq_bits_data),
.io_deq_bits_corrupt (cated_bits_corrupt)
); // @[Repeater.scala:36:26]
assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_153 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_174
connect io_out_source_valid_1.clock, clock
connect io_out_source_valid_1.reset, reset
connect io_out_source_valid_1.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid_1.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_153( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_174 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Timer_1 :
input clock : Clock
input reset : Reset
output io : { flip start : { valid : UInt<1>, bits : UInt<3>}, flip stop : { valid : UInt<1>, bits : UInt<3>}, timeout : { valid : UInt<1>, bits : UInt<3>}}
wire _inflight_WIRE : UInt<1>[8]
connect _inflight_WIRE[0], UInt<1>(0h0)
connect _inflight_WIRE[1], UInt<1>(0h0)
connect _inflight_WIRE[2], UInt<1>(0h0)
connect _inflight_WIRE[3], UInt<1>(0h0)
connect _inflight_WIRE[4], UInt<1>(0h0)
connect _inflight_WIRE[5], UInt<1>(0h0)
connect _inflight_WIRE[6], UInt<1>(0h0)
connect _inflight_WIRE[7], UInt<1>(0h0)
regreset inflight : UInt<1>[8], clock, reset, _inflight_WIRE
reg countdown : UInt<13>, clock
node _active_T = or(inflight[0], inflight[1])
node _active_T_1 = or(_active_T, inflight[2])
node _active_T_2 = or(_active_T_1, inflight[3])
node _active_T_3 = or(_active_T_2, inflight[4])
node _active_T_4 = or(_active_T_3, inflight[5])
node _active_T_5 = or(_active_T_4, inflight[6])
node active = or(_active_T_5, inflight[7])
when active :
node _countdown_T = sub(countdown, UInt<1>(0h1))
node _countdown_T_1 = tail(_countdown_T, 1)
connect countdown, _countdown_T_1
when io.start.valid :
connect inflight[io.start.bits], UInt<1>(0h1)
connect countdown, UInt<13>(0h1fff)
when io.stop.valid :
connect inflight[io.stop.bits], UInt<1>(0h0)
node _io_timeout_valid_T = eq(countdown, UInt<1>(0h0))
node _io_timeout_valid_T_1 = and(_io_timeout_valid_T, active)
connect io.timeout.valid, _io_timeout_valid_T_1
node _io_timeout_bits_T = mux(inflight[6], UInt<3>(0h6), UInt<3>(0h7))
node _io_timeout_bits_T_1 = mux(inflight[5], UInt<3>(0h5), _io_timeout_bits_T)
node _io_timeout_bits_T_2 = mux(inflight[4], UInt<3>(0h4), _io_timeout_bits_T_1)
node _io_timeout_bits_T_3 = mux(inflight[3], UInt<2>(0h3), _io_timeout_bits_T_2)
node _io_timeout_bits_T_4 = mux(inflight[2], UInt<2>(0h2), _io_timeout_bits_T_3)
node _io_timeout_bits_T_5 = mux(inflight[1], UInt<1>(0h1), _io_timeout_bits_T_4)
node _io_timeout_bits_T_6 = mux(inflight[0], UInt<1>(0h0), _io_timeout_bits_T_5)
connect io.timeout.bits, _io_timeout_bits_T_6
node _T = eq(io.stop.valid, UInt<1>(0h0))
node _T_1 = or(_T, inflight[io.stop.bits])
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed: Timer stop for transaction that's not inflight\n at Timer.scala:36 assert(!io.stop.valid || inflight(io.stop.bits),\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert | module Timer_1( // @[Timer.scala:13:7]
input clock, // @[Timer.scala:13:7]
input reset, // @[Timer.scala:13:7]
input io_start_valid, // @[Timer.scala:14:14]
input [2:0] io_start_bits, // @[Timer.scala:14:14]
input io_stop_valid, // @[Timer.scala:14:14]
input [2:0] io_stop_bits, // @[Timer.scala:14:14]
output io_timeout_valid // @[Timer.scala:14:14]
);
wire io_start_valid_0 = io_start_valid; // @[Timer.scala:13:7]
wire [2:0] io_start_bits_0 = io_start_bits; // @[Timer.scala:13:7]
wire io_stop_valid_0 = io_stop_valid; // @[Timer.scala:13:7]
wire [2:0] io_stop_bits_0 = io_stop_bits; // @[Timer.scala:13:7]
wire _inflight_WIRE_0 = 1'h0; // @[Timer.scala:20:33]
wire _inflight_WIRE_1 = 1'h0; // @[Timer.scala:20:33]
wire _inflight_WIRE_2 = 1'h0; // @[Timer.scala:20:33]
wire _inflight_WIRE_3 = 1'h0; // @[Timer.scala:20:33]
wire _inflight_WIRE_4 = 1'h0; // @[Timer.scala:20:33]
wire _inflight_WIRE_5 = 1'h0; // @[Timer.scala:20:33]
wire _inflight_WIRE_6 = 1'h0; // @[Timer.scala:20:33]
wire _inflight_WIRE_7 = 1'h0; // @[Timer.scala:20:33]
wire _io_timeout_valid_T_1; // @[Timer.scala:33:41]
wire [2:0] _io_timeout_bits_T_6; // @[Mux.scala:50:70]
wire io_timeout_valid_0; // @[Timer.scala:13:7]
wire [2:0] io_timeout_bits; // @[Timer.scala:13:7]
reg inflight_0; // @[Timer.scala:20:25]
reg inflight_1; // @[Timer.scala:20:25]
reg inflight_2; // @[Timer.scala:20:25]
reg inflight_3; // @[Timer.scala:20:25]
reg inflight_4; // @[Timer.scala:20:25]
reg inflight_5; // @[Timer.scala:20:25]
reg inflight_6; // @[Timer.scala:20:25]
reg inflight_7; // @[Timer.scala:20:25]
reg [12:0] countdown; // @[Timer.scala:21:22]
wire _active_T = inflight_0 | inflight_1; // @[Timer.scala:20:25, :22:34]
wire _active_T_1 = _active_T | inflight_2; // @[Timer.scala:20:25, :22:34]
wire _active_T_2 = _active_T_1 | inflight_3; // @[Timer.scala:20:25, :22:34]
wire _active_T_3 = _active_T_2 | inflight_4; // @[Timer.scala:20:25, :22:34]
wire _active_T_4 = _active_T_3 | inflight_5; // @[Timer.scala:20:25, :22:34]
wire _active_T_5 = _active_T_4 | inflight_6; // @[Timer.scala:20:25, :22:34]
wire active = _active_T_5 | inflight_7; // @[Timer.scala:20:25, :22:34]
wire [13:0] _countdown_T = {1'h0, countdown} - 14'h1; // @[Timer.scala:21:22, :24:42]
wire [12:0] _countdown_T_1 = _countdown_T[12:0]; // @[Timer.scala:24:42]
wire _io_timeout_valid_T = countdown == 13'h0; // @[Timer.scala:21:22, :33:33]
assign _io_timeout_valid_T_1 = _io_timeout_valid_T & active; // @[Timer.scala:22:34, :33:{33,41}]
assign io_timeout_valid_0 = _io_timeout_valid_T_1; // @[Timer.scala:13:7, :33:41]
wire [2:0] _io_timeout_bits_T = {2'h3, ~inflight_6}; // @[Mux.scala:50:70]
wire [2:0] _io_timeout_bits_T_1 = inflight_5 ? 3'h5 : _io_timeout_bits_T; // @[Mux.scala:50:70]
wire [2:0] _io_timeout_bits_T_2 = inflight_4 ? 3'h4 : _io_timeout_bits_T_1; // @[Mux.scala:50:70]
wire [2:0] _io_timeout_bits_T_3 = inflight_3 ? 3'h3 : _io_timeout_bits_T_2; // @[Mux.scala:50:70]
wire [2:0] _io_timeout_bits_T_4 = inflight_2 ? 3'h2 : _io_timeout_bits_T_3; // @[Mux.scala:50:70]
wire [2:0] _io_timeout_bits_T_5 = inflight_1 ? 3'h1 : _io_timeout_bits_T_4; // @[Mux.scala:50:70]
assign _io_timeout_bits_T_6 = inflight_0 ? 3'h0 : _io_timeout_bits_T_5; // @[Mux.scala:50:70]
assign io_timeout_bits = _io_timeout_bits_T_6; // @[Mux.scala:50:70] |
Generate the Verilog code corresponding to this FIRRTL code module LoopBranchPredictorColumn_8 :
input clock : Clock
input reset : Reset
output io : { flip f2_req_valid : UInt<1>, flip f2_req_idx : UInt, flip f3_req_fire : UInt<1>, flip f3_pred_in : UInt<1>, f3_pred : UInt<1>, f3_meta : { s_cnt : UInt<10>}, flip update_mispredict : UInt<1>, flip update_repair : UInt<1>, flip update_idx : UInt, flip update_resolve_dir : UInt<1>, flip update_meta : { s_cnt : UInt<10>}}
regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1)
regreset reset_idx : UInt<4>, clock, reset, UInt<4>(0h0)
node _reset_idx_T = add(reset_idx, doing_reset)
node _reset_idx_T_1 = tail(_reset_idx_T, 1)
connect reset_idx, _reset_idx_T_1
node _T = eq(reset_idx, UInt<4>(0hf))
when _T :
connect doing_reset, UInt<1>(0h0)
reg entries : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}[16], clock
node _f2_entry_T = or(io.f2_req_idx, UInt<4>(0h0))
node _f2_entry_T_1 = bits(_f2_entry_T, 3, 0)
wire f2_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}
connect f2_entry, entries[_f2_entry_T_1]
node _T_1 = eq(io.update_idx, io.f2_req_idx)
node _T_2 = and(io.update_repair, _T_1)
when _T_2 :
connect f2_entry.s_cnt, io.update_meta.s_cnt
else :
node _T_3 = eq(io.update_idx, io.f2_req_idx)
node _T_4 = and(io.update_mispredict, _T_3)
when _T_4 :
connect f2_entry.s_cnt, UInt<1>(0h0)
reg f3_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock
connect f3_entry, f2_entry
reg f3_scnt_REG : UInt, clock
connect f3_scnt_REG, io.f2_req_idx
node _f3_scnt_T = eq(io.update_idx, f3_scnt_REG)
node _f3_scnt_T_1 = and(io.update_repair, _f3_scnt_T)
node f3_scnt = mux(_f3_scnt_T_1, io.update_meta.s_cnt, f3_entry.s_cnt)
node _f3_tag_T = bits(io.f2_req_idx, 13, 4)
reg f3_tag : UInt, clock
connect f3_tag, _f3_tag_T
connect io.f3_pred, io.f3_pred_in
connect io.f3_meta.s_cnt, f3_scnt
node _T_5 = eq(f3_entry.tag, f3_tag)
when _T_5 :
node _T_6 = eq(f3_scnt, f3_entry.p_cnt)
node _T_7 = eq(f3_entry.conf, UInt<3>(0h7))
node _T_8 = and(_T_6, _T_7)
when _T_8 :
node _io_f3_pred_T = eq(io.f3_pred_in, UInt<1>(0h0))
connect io.f3_pred, _io_f3_pred_T
reg f4_fire : UInt<1>, clock
connect f4_fire, io.f3_req_fire
reg f4_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock
connect f4_entry, f3_entry
reg f4_tag : UInt, clock
connect f4_tag, f3_tag
reg f4_scnt : UInt, clock
connect f4_scnt, f3_scnt
reg f4_idx_REG : UInt, clock
connect f4_idx_REG, io.f2_req_idx
reg f4_idx : UInt, clock
connect f4_idx, f4_idx_REG
when f4_fire :
node _T_9 = eq(f4_entry.tag, f4_tag)
when _T_9 :
node _T_10 = eq(f4_scnt, f4_entry.p_cnt)
node _T_11 = eq(f4_entry.conf, UInt<3>(0h7))
node _T_12 = and(_T_10, _T_11)
when _T_12 :
node _T_13 = or(f4_idx, UInt<4>(0h0))
node _T_14 = bits(_T_13, 3, 0)
connect entries[_T_14].age, UInt<3>(0h7)
node _T_15 = or(f4_idx, UInt<4>(0h0))
node _T_16 = bits(_T_15, 3, 0)
connect entries[_T_16].s_cnt, UInt<1>(0h0)
else :
node _T_17 = or(f4_idx, UInt<4>(0h0))
node _T_18 = bits(_T_17, 3, 0)
node _entries_s_cnt_T = add(f4_scnt, UInt<1>(0h1))
node _entries_s_cnt_T_1 = tail(_entries_s_cnt_T, 1)
connect entries[_T_18].s_cnt, _entries_s_cnt_T_1
node _T_19 = or(f4_idx, UInt<4>(0h0))
node _T_20 = bits(_T_19, 3, 0)
node _entries_age_T = eq(f4_entry.age, UInt<3>(0h7))
node _entries_age_T_1 = add(f4_entry.age, UInt<1>(0h1))
node _entries_age_T_2 = tail(_entries_age_T_1, 1)
node _entries_age_T_3 = mux(_entries_age_T, UInt<3>(0h7), _entries_age_T_2)
connect entries[_T_20].age, _entries_age_T_3
node _entry_T = or(io.update_idx, UInt<4>(0h0))
node _entry_T_1 = bits(_entry_T, 3, 0)
node tag = bits(io.update_idx, 13, 4)
node tag_match = eq(entries[_entry_T_1].tag, tag)
node ctr_match = eq(entries[_entry_T_1].p_cnt, io.update_meta.s_cnt)
wire wentry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}
connect wentry, entries[_entry_T_1]
node _T_21 = eq(doing_reset, UInt<1>(0h0))
node _T_22 = and(io.update_mispredict, _T_21)
when _T_22 :
node _T_23 = eq(entries[_entry_T_1].conf, UInt<3>(0h7))
node _T_24 = and(_T_23, tag_match)
when _T_24 :
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.conf, UInt<1>(0h0)
else :
node _T_25 = eq(entries[_entry_T_1].conf, UInt<3>(0h7))
node _T_26 = eq(tag_match, UInt<1>(0h0))
node _T_27 = and(_T_25, _T_26)
when _T_27 :
skip
else :
node _T_28 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_29 = and(_T_28, tag_match)
node _T_30 = and(_T_29, ctr_match)
when _T_30 :
node _wentry_conf_T = add(entries[_entry_T_1].conf, UInt<1>(0h1))
node _wentry_conf_T_1 = tail(_wentry_conf_T, 1)
connect wentry.conf, _wentry_conf_T_1
connect wentry.s_cnt, UInt<1>(0h0)
else :
node _T_31 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_32 = and(_T_31, tag_match)
node _T_33 = eq(ctr_match, UInt<1>(0h0))
node _T_34 = and(_T_32, _T_33)
when _T_34 :
connect wentry.conf, UInt<1>(0h0)
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.p_cnt, io.update_meta.s_cnt
else :
node _T_35 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_36 = eq(tag_match, UInt<1>(0h0))
node _T_37 = and(_T_35, _T_36)
node _T_38 = eq(entries[_entry_T_1].age, UInt<1>(0h0))
node _T_39 = and(_T_37, _T_38)
when _T_39 :
connect wentry.tag, tag
connect wentry.conf, UInt<1>(0h1)
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.p_cnt, io.update_meta.s_cnt
else :
node _T_40 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_41 = eq(tag_match, UInt<1>(0h0))
node _T_42 = and(_T_40, _T_41)
node _T_43 = neq(entries[_entry_T_1].age, UInt<1>(0h0))
node _T_44 = and(_T_42, _T_43)
when _T_44 :
node _wentry_age_T = sub(entries[_entry_T_1].age, UInt<1>(0h1))
node _wentry_age_T_1 = tail(_wentry_age_T, 1)
connect wentry.age, _wentry_age_T_1
else :
node _T_45 = eq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_46 = and(_T_45, tag_match)
node _T_47 = and(_T_46, ctr_match)
when _T_47 :
connect wentry.conf, UInt<1>(0h1)
connect wentry.age, UInt<3>(0h7)
connect wentry.s_cnt, UInt<1>(0h0)
else :
node _T_48 = eq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_49 = and(_T_48, tag_match)
node _T_50 = eq(ctr_match, UInt<1>(0h0))
node _T_51 = and(_T_49, _T_50)
when _T_51 :
connect wentry.p_cnt, io.update_meta.s_cnt
connect wentry.age, UInt<3>(0h7)
connect wentry.s_cnt, UInt<1>(0h0)
else :
node _T_52 = eq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_53 = eq(tag_match, UInt<1>(0h0))
node _T_54 = and(_T_52, _T_53)
when _T_54 :
connect wentry.tag, tag
connect wentry.conf, UInt<1>(0h1)
connect wentry.age, UInt<3>(0h7)
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.p_cnt, io.update_meta.s_cnt
node _T_55 = or(io.update_idx, UInt<4>(0h0))
node _T_56 = bits(_T_55, 3, 0)
connect entries[_T_56], wentry
else :
node _T_57 = eq(doing_reset, UInt<1>(0h0))
node _T_58 = and(io.update_repair, _T_57)
when _T_58 :
node _T_59 = eq(io.update_idx, f4_idx)
node _T_60 = and(f4_fire, _T_59)
node _T_61 = eq(_T_60, UInt<1>(0h0))
node _T_62 = and(tag_match, _T_61)
when _T_62 :
connect wentry.s_cnt, io.update_meta.s_cnt
node _T_63 = or(io.update_idx, UInt<4>(0h0))
node _T_64 = bits(_T_63, 3, 0)
connect entries[_T_64], wentry
when doing_reset :
wire _entries_WIRE : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}
connect _entries_WIRE.s_cnt, UInt<10>(0h0)
connect _entries_WIRE.p_cnt, UInt<10>(0h0)
connect _entries_WIRE.age, UInt<3>(0h0)
connect _entries_WIRE.conf, UInt<3>(0h0)
connect _entries_WIRE.tag, UInt<10>(0h0)
connect entries[reset_idx], _entries_WIRE | module LoopBranchPredictorColumn_8( // @[loop.scala:39:9]
input clock, // @[loop.scala:39:9]
input reset, // @[loop.scala:39:9]
input io_f2_req_valid, // @[loop.scala:43:16]
input [35:0] io_f2_req_idx, // @[loop.scala:43:16]
input io_f3_req_fire, // @[loop.scala:43:16]
input io_f3_pred_in, // @[loop.scala:43:16]
output io_f3_pred, // @[loop.scala:43:16]
output [9:0] io_f3_meta_s_cnt, // @[loop.scala:43:16]
input io_update_mispredict, // @[loop.scala:43:16]
input io_update_repair, // @[loop.scala:43:16]
input [35:0] io_update_idx, // @[loop.scala:43:16]
input io_update_resolve_dir, // @[loop.scala:43:16]
input [9:0] io_update_meta_s_cnt // @[loop.scala:43:16]
);
wire io_f2_req_valid_0 = io_f2_req_valid; // @[loop.scala:39:9]
wire [35:0] io_f2_req_idx_0 = io_f2_req_idx; // @[loop.scala:39:9]
wire io_f3_req_fire_0 = io_f3_req_fire; // @[loop.scala:39:9]
wire io_f3_pred_in_0 = io_f3_pred_in; // @[loop.scala:39:9]
wire io_update_mispredict_0 = io_update_mispredict; // @[loop.scala:39:9]
wire io_update_repair_0 = io_update_repair; // @[loop.scala:39:9]
wire [35:0] io_update_idx_0 = io_update_idx; // @[loop.scala:39:9]
wire io_update_resolve_dir_0 = io_update_resolve_dir; // @[loop.scala:39:9]
wire [9:0] io_update_meta_s_cnt_0 = io_update_meta_s_cnt; // @[loop.scala:39:9]
wire [2:0] _entries_WIRE_conf = 3'h0; // @[loop.scala:176:43]
wire [2:0] _entries_WIRE_age = 3'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_tag = 10'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_p_cnt = 10'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_s_cnt = 10'h0; // @[loop.scala:176:43]
wire [35:0] _f2_entry_T = io_f2_req_idx_0; // @[loop.scala:39:9]
wire [9:0] f3_scnt; // @[loop.scala:73:23]
wire [35:0] _entry_T = io_update_idx_0; // @[loop.scala:39:9]
wire [9:0] io_f3_meta_s_cnt_0; // @[loop.scala:39:9]
wire io_f3_pred_0; // @[loop.scala:39:9]
reg doing_reset; // @[loop.scala:59:30]
reg [3:0] reset_idx; // @[loop.scala:60:28]
wire [4:0] _reset_idx_T = {1'h0, reset_idx} + {4'h0, doing_reset}; // @[loop.scala:59:30, :60:28, :61:28]
wire [3:0] _reset_idx_T_1 = _reset_idx_T[3:0]; // @[loop.scala:61:28]
reg [9:0] entries_0_tag; // @[loop.scala:65:22]
reg [2:0] entries_0_conf; // @[loop.scala:65:22]
reg [2:0] entries_0_age; // @[loop.scala:65:22]
reg [9:0] entries_0_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_0_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_1_tag; // @[loop.scala:65:22]
reg [2:0] entries_1_conf; // @[loop.scala:65:22]
reg [2:0] entries_1_age; // @[loop.scala:65:22]
reg [9:0] entries_1_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_1_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_2_tag; // @[loop.scala:65:22]
reg [2:0] entries_2_conf; // @[loop.scala:65:22]
reg [2:0] entries_2_age; // @[loop.scala:65:22]
reg [9:0] entries_2_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_2_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_3_tag; // @[loop.scala:65:22]
reg [2:0] entries_3_conf; // @[loop.scala:65:22]
reg [2:0] entries_3_age; // @[loop.scala:65:22]
reg [9:0] entries_3_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_3_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_4_tag; // @[loop.scala:65:22]
reg [2:0] entries_4_conf; // @[loop.scala:65:22]
reg [2:0] entries_4_age; // @[loop.scala:65:22]
reg [9:0] entries_4_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_4_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_5_tag; // @[loop.scala:65:22]
reg [2:0] entries_5_conf; // @[loop.scala:65:22]
reg [2:0] entries_5_age; // @[loop.scala:65:22]
reg [9:0] entries_5_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_5_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_6_tag; // @[loop.scala:65:22]
reg [2:0] entries_6_conf; // @[loop.scala:65:22]
reg [2:0] entries_6_age; // @[loop.scala:65:22]
reg [9:0] entries_6_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_6_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_7_tag; // @[loop.scala:65:22]
reg [2:0] entries_7_conf; // @[loop.scala:65:22]
reg [2:0] entries_7_age; // @[loop.scala:65:22]
reg [9:0] entries_7_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_7_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_8_tag; // @[loop.scala:65:22]
reg [2:0] entries_8_conf; // @[loop.scala:65:22]
reg [2:0] entries_8_age; // @[loop.scala:65:22]
reg [9:0] entries_8_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_8_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_9_tag; // @[loop.scala:65:22]
reg [2:0] entries_9_conf; // @[loop.scala:65:22]
reg [2:0] entries_9_age; // @[loop.scala:65:22]
reg [9:0] entries_9_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_9_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_10_tag; // @[loop.scala:65:22]
reg [2:0] entries_10_conf; // @[loop.scala:65:22]
reg [2:0] entries_10_age; // @[loop.scala:65:22]
reg [9:0] entries_10_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_10_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_11_tag; // @[loop.scala:65:22]
reg [2:0] entries_11_conf; // @[loop.scala:65:22]
reg [2:0] entries_11_age; // @[loop.scala:65:22]
reg [9:0] entries_11_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_11_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_12_tag; // @[loop.scala:65:22]
reg [2:0] entries_12_conf; // @[loop.scala:65:22]
reg [2:0] entries_12_age; // @[loop.scala:65:22]
reg [9:0] entries_12_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_12_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_13_tag; // @[loop.scala:65:22]
reg [2:0] entries_13_conf; // @[loop.scala:65:22]
reg [2:0] entries_13_age; // @[loop.scala:65:22]
reg [9:0] entries_13_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_13_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_14_tag; // @[loop.scala:65:22]
reg [2:0] entries_14_conf; // @[loop.scala:65:22]
reg [2:0] entries_14_age; // @[loop.scala:65:22]
reg [9:0] entries_14_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_14_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_15_tag; // @[loop.scala:65:22]
reg [2:0] entries_15_conf; // @[loop.scala:65:22]
reg [2:0] entries_15_age; // @[loop.scala:65:22]
reg [9:0] entries_15_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_15_s_cnt; // @[loop.scala:65:22]
wire [3:0] _f2_entry_T_1 = _f2_entry_T[3:0];
wire [9:0] f2_entry_tag; // @[loop.scala:66:28]
wire [2:0] f2_entry_conf; // @[loop.scala:66:28]
wire [2:0] f2_entry_age; // @[loop.scala:66:28]
wire [9:0] f2_entry_p_cnt; // @[loop.scala:66:28]
wire [9:0] f2_entry_s_cnt; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN = {{entries_15_tag}, {entries_14_tag}, {entries_13_tag}, {entries_12_tag}, {entries_11_tag}, {entries_10_tag}, {entries_9_tag}, {entries_8_tag}, {entries_7_tag}, {entries_6_tag}, {entries_5_tag}, {entries_4_tag}, {entries_3_tag}, {entries_2_tag}, {entries_1_tag}, {entries_0_tag}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_tag = _GEN[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][2:0] _GEN_0 = {{entries_15_conf}, {entries_14_conf}, {entries_13_conf}, {entries_12_conf}, {entries_11_conf}, {entries_10_conf}, {entries_9_conf}, {entries_8_conf}, {entries_7_conf}, {entries_6_conf}, {entries_5_conf}, {entries_4_conf}, {entries_3_conf}, {entries_2_conf}, {entries_1_conf}, {entries_0_conf}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_conf = _GEN_0[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][2:0] _GEN_1 = {{entries_15_age}, {entries_14_age}, {entries_13_age}, {entries_12_age}, {entries_11_age}, {entries_10_age}, {entries_9_age}, {entries_8_age}, {entries_7_age}, {entries_6_age}, {entries_5_age}, {entries_4_age}, {entries_3_age}, {entries_2_age}, {entries_1_age}, {entries_0_age}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_age = _GEN_1[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN_2 = {{entries_15_p_cnt}, {entries_14_p_cnt}, {entries_13_p_cnt}, {entries_12_p_cnt}, {entries_11_p_cnt}, {entries_10_p_cnt}, {entries_9_p_cnt}, {entries_8_p_cnt}, {entries_7_p_cnt}, {entries_6_p_cnt}, {entries_5_p_cnt}, {entries_4_p_cnt}, {entries_3_p_cnt}, {entries_2_p_cnt}, {entries_1_p_cnt}, {entries_0_p_cnt}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_p_cnt = _GEN_2[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN_3 = {{entries_15_s_cnt}, {entries_14_s_cnt}, {entries_13_s_cnt}, {entries_12_s_cnt}, {entries_11_s_cnt}, {entries_10_s_cnt}, {entries_9_s_cnt}, {entries_8_s_cnt}, {entries_7_s_cnt}, {entries_6_s_cnt}, {entries_5_s_cnt}, {entries_4_s_cnt}, {entries_3_s_cnt}, {entries_2_s_cnt}, {entries_1_s_cnt}, {entries_0_s_cnt}}; // @[loop.scala:65:22, :66:28]
wire _T_3 = io_update_idx_0 == io_f2_req_idx_0; // @[loop.scala:39:9, :67:45]
assign f2_entry_s_cnt = io_update_repair_0 & _T_3 ? io_update_meta_s_cnt_0 : io_update_mispredict_0 & _T_3 ? 10'h0 : _GEN_3[_f2_entry_T_1]; // @[loop.scala:39:9, :66:28, :67:{28,45,64}, :68:22, :69:{39,75}, :70:22]
reg [9:0] f3_entry_tag; // @[loop.scala:72:27]
reg [2:0] f3_entry_conf; // @[loop.scala:72:27]
reg [2:0] f3_entry_age; // @[loop.scala:72:27]
reg [9:0] f3_entry_p_cnt; // @[loop.scala:72:27]
reg [9:0] f3_entry_s_cnt; // @[loop.scala:72:27]
reg [35:0] f3_scnt_REG; // @[loop.scala:73:69]
wire _f3_scnt_T = io_update_idx_0 == f3_scnt_REG; // @[loop.scala:39:9, :73:{58,69}]
wire _f3_scnt_T_1 = io_update_repair_0 & _f3_scnt_T; // @[loop.scala:39:9, :73:{41,58}]
assign f3_scnt = _f3_scnt_T_1 ? io_update_meta_s_cnt_0 : f3_entry_s_cnt; // @[loop.scala:39:9, :72:27, :73:{23,41}]
assign io_f3_meta_s_cnt_0 = f3_scnt; // @[loop.scala:39:9, :73:23]
wire [9:0] _f3_tag_T = io_f2_req_idx_0[13:4]; // @[loop.scala:39:9, :76:41]
reg [9:0] f3_tag; // @[loop.scala:76:27]
wire _io_f3_pred_T = ~io_f3_pred_in_0; // @[loop.scala:39:9, :83:23]
assign io_f3_pred_0 = f3_entry_tag == f3_tag & f3_scnt == f3_entry_p_cnt & (&f3_entry_conf) ? _io_f3_pred_T : io_f3_pred_in_0; // @[loop.scala:39:9, :72:27, :73:23, :76:27, :78:16, :81:{24,36}, :82:{21,40,57,66}, :83:{20,23}]
reg f4_fire; // @[loop.scala:88:27]
reg [9:0] f4_entry_tag; // @[loop.scala:89:27]
reg [2:0] f4_entry_conf; // @[loop.scala:89:27]
reg [2:0] f4_entry_age; // @[loop.scala:89:27]
reg [9:0] f4_entry_p_cnt; // @[loop.scala:89:27]
reg [9:0] f4_entry_s_cnt; // @[loop.scala:89:27]
reg [9:0] f4_tag; // @[loop.scala:90:27]
reg [9:0] f4_scnt; // @[loop.scala:91:27]
reg [35:0] f4_idx_REG; // @[loop.scala:92:35]
reg [35:0] f4_idx; // @[loop.scala:92:27]
wire [10:0] _entries_s_cnt_T = {1'h0, f4_scnt} + 11'h1; // @[loop.scala:91:27, :101:44]
wire [9:0] _entries_s_cnt_T_1 = _entries_s_cnt_T[9:0]; // @[loop.scala:101:44]
wire _entries_age_T = &f4_entry_age; // @[loop.scala:89:27, :102:53]
wire [3:0] _entries_age_T_1 = {1'h0, f4_entry_age} + 4'h1; // @[loop.scala:89:27, :102:80]
wire [2:0] _entries_age_T_2 = _entries_age_T_1[2:0]; // @[loop.scala:102:80]
wire [2:0] _entries_age_T_3 = _entries_age_T ? 3'h7 : _entries_age_T_2; // @[loop.scala:102:{39,53,80}]
wire [3:0] _entry_T_1 = _entry_T[3:0];
wire [9:0] tag = io_update_idx_0[13:4]; // @[loop.scala:39:9, :109:28]
wire tag_match = _GEN[_entry_T_1] == tag; // @[loop.scala:66:28, :109:28, :110:31]
wire ctr_match = _GEN_2[_entry_T_1] == io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :111:33]
wire [9:0] wentry_tag; // @[loop.scala:112:26]
wire [2:0] wentry_conf; // @[loop.scala:112:26]
wire [2:0] wentry_age; // @[loop.scala:112:26]
wire [9:0] wentry_p_cnt; // @[loop.scala:112:26]
wire [9:0] wentry_s_cnt; // @[loop.scala:112:26]
wire _T_22 = io_update_mispredict_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:{32,35}]
wire _T_24 = (&_GEN_0[_entry_T_1]) & tag_match; // @[loop.scala:66:28, :110:31, :117:{24,32}]
wire _T_27 = (&_GEN_0[_entry_T_1]) & ~tag_match; // @[loop.scala:66:28, :110:31, :117:24, :122:{39,42}]
wire _T_30 = (|_GEN_0[_entry_T_1]) & tag_match & ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:{31,39,52}]
wire [3:0] _wentry_conf_T = {1'h0, _GEN_0[_entry_T_1]} + 4'h1; // @[loop.scala:66:28, :102:80, :110:31, :126:36]
wire [2:0] _wentry_conf_T_1 = _wentry_conf_T[2:0]; // @[loop.scala:126:36]
wire _T_34 = (|_GEN_0[_entry_T_1]) & tag_match & ~ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:31, :130:{39,52,55}]
wire _T_39 = (|_GEN_0[_entry_T_1]) & ~tag_match & _GEN_1[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :122:42, :125:31, :136:{39,53,66}]
wire _T_44 = (|_GEN_0[_entry_T_1]) & ~tag_match & (|_GEN_1[_entry_T_1]); // @[loop.scala:66:28, :110:31, :122:42, :125:31, :143:{39,53,66}]
wire [3:0] _wentry_age_T = {1'h0, _GEN_1[_entry_T_1]} - 4'h1; // @[loop.scala:66:28, :110:31, :144:33]
wire [2:0] _wentry_age_T_1 = _wentry_age_T[2:0]; // @[loop.scala:144:33]
wire _T_52 = _GEN_0[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :147:31]
wire _T_47 = _T_52 & tag_match & ctr_match; // @[loop.scala:110:31, :111:33, :147:{31,39,52}]
wire _T_51 = _T_52 & tag_match & ~ctr_match; // @[loop.scala:110:31, :111:33, :130:55, :147:31, :153:{39,52}]
wire _T_54 = _T_52 & ~tag_match; // @[loop.scala:110:31, :122:42, :147:31, :159:39]
wire _GEN_4 = _T_47 | _T_51; // @[loop.scala:112:26, :147:{39,52,66}, :153:{39,52,67}, :159:54]
wire _GEN_5 = _T_30 | _T_34; // @[loop.scala:112:26, :125:{39,52,66}, :130:{39,52,67}, :136:75]
assign wentry_tag = ~_T_22 | _T_24 | _T_27 | _GEN_5 | ~(_T_39 | ~(_T_44 | _GEN_4 | ~_T_54)) ? _GEN[_entry_T_1] : tag; // @[loop.scala:66:28, :109:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:66, :130:67, :136:{39,53,75}, :137:22, :143:{39,53,75}, :147:66, :153:67, :159:{39,54}]
assign wentry_conf = _T_22 ? (_T_24 ? 3'h0 : _T_27 ? _GEN_0[_entry_T_1] : _T_30 ? _wentry_conf_T_1 : _T_34 ? 3'h0 : _T_39 | ~(_T_44 | ~(_T_47 | ~(_T_51 | ~_T_54))) ? 3'h1 : _GEN_0[_entry_T_1]) : _GEN_0[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :119:22, :122:{39,54}, :125:{39,52,66}, :126:{22,36}, :130:{39,52,67}, :131:22, :136:{39,53,75}, :138:22, :143:{39,53,75}, :147:{39,52,66}, :148:22, :153:{39,52,67}, :159:{39,54}]
wire _GEN_6 = _T_51 | _T_54; // @[loop.scala:112:26, :153:{39,52,67}, :155:22, :159:{39,54}, :162:22]
wire _GEN_7 = _T_34 | _T_39; // @[loop.scala:112:26, :130:{39,52,67}, :136:{39,53,75}, :143:75]
assign wentry_age = ~_T_22 | _T_24 | _T_27 | _T_30 | _GEN_7 ? _GEN_1[_entry_T_1] : _T_44 ? _wentry_age_T_1 : _T_47 | _GEN_6 ? 3'h7 : _GEN_1[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :136:75, :143:{39,53,75}, :144:{20,33}, :147:{39,52,66}, :149:22, :153:67, :155:22, :159:54, :162:22]
assign wentry_p_cnt = ~_T_22 | _T_24 | _T_27 | _T_30 | ~(_GEN_7 | ~(_T_44 | _T_47 | ~_GEN_6)) ? _GEN_2[_entry_T_1] : io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :133:22, :136:75, :140:22, :143:{39,53,75}, :147:{39,52,66}, :153:67, :155:22, :159:54, :162:22]
wire _T_58 = io_update_repair_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:35, :168:35]
wire _T_62 = tag_match & ~(f4_fire & io_update_idx_0 == f4_idx); // @[loop.scala:39:9, :88:27, :92:27, :110:31, :169:{23,26,36,53}]
assign wentry_s_cnt = _T_22 ? (_T_24 | ~(_T_27 | ~(_GEN_5 | _T_39 | ~(_T_44 | ~(_GEN_4 | _T_54)))) ? 10'h0 : _GEN_3[_entry_T_1]) : _T_58 & _T_62 ? io_update_meta_s_cnt_0 : _GEN_3[_entry_T_1]; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :118:22, :122:{39,54}, :125:66, :127:22, :130:67, :132:22, :136:{39,53,75}, :139:22, :143:{39,53,75}, :147:66, :150:22, :153:67, :156:22, :159:{39,54}, :163:22, :168:{35,52}, :169:{23,66}, :170:22]
wire _T_12 = f4_scnt == f4_entry_p_cnt & (&f4_entry_conf); // @[loop.scala:89:27, :91:27, :97:{23,42,59}]
wire _GEN_8 = f4_fire & f4_entry_tag == f4_tag; // @[loop.scala:65:22, :88:27, :89:27, :90:27, :95:20, :96:{26,38}, :97:68]
always @(posedge clock) begin // @[loop.scala:39:9]
if (reset) begin // @[loop.scala:39:9]
doing_reset <= 1'h1; // @[loop.scala:59:30]
reset_idx <= 4'h0; // @[loop.scala:60:28]
end
else begin // @[loop.scala:39:9]
doing_reset <= reset_idx != 4'hF & doing_reset; // @[loop.scala:59:30, :60:28, :62:{21,38,52}]
reset_idx <= _reset_idx_T_1; // @[loop.scala:60:28, :61:28]
end
if (doing_reset & reset_idx == 4'h0) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_0_tag <= 10'h0; // @[loop.scala:65:22]
entries_0_conf <= 3'h0; // @[loop.scala:65:22]
entries_0_age <= 3'h0; // @[loop.scala:65:22]
entries_0_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h0 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h0) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_0_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_0_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_0_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_0_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_0_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :98:33]
entries_0_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :99:33]
entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :102:33]
entries_0_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :101:33]
entries_0_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h1) begin // @[loop.scala:59:30, :60:28, :102:80, :114:49, :175:24, :176:26]
entries_1_tag <= 10'h0; // @[loop.scala:65:22]
entries_1_conf <= 3'h0; // @[loop.scala:65:22]
entries_1_age <= 3'h0; // @[loop.scala:65:22]
entries_1_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h1 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h1) begin // @[loop.scala:39:9, :65:22, :95:20, :102:80, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_1_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_1_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_1_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_1_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_1_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :98:33, :102:80]
entries_1_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :99:33, :102:80]
entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :102:{33,80}]
entries_1_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :101:33, :102:80]
entries_1_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h2) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_2_tag <= 10'h0; // @[loop.scala:65:22]
entries_2_conf <= 3'h0; // @[loop.scala:65:22]
entries_2_age <= 3'h0; // @[loop.scala:65:22]
entries_2_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h2 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h2) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_2_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_2_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_2_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_2_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_2_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :98:33]
entries_2_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :99:33]
entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :102:33]
entries_2_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :101:33]
entries_2_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h3) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_3_tag <= 10'h0; // @[loop.scala:65:22]
entries_3_conf <= 3'h0; // @[loop.scala:65:22]
entries_3_age <= 3'h0; // @[loop.scala:65:22]
entries_3_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h3 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h3) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_3_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_3_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_3_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_3_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_3_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :98:33]
entries_3_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :99:33]
entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :102:33]
entries_3_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :101:33]
entries_3_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h4) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_4_tag <= 10'h0; // @[loop.scala:65:22]
entries_4_conf <= 3'h0; // @[loop.scala:65:22]
entries_4_age <= 3'h0; // @[loop.scala:65:22]
entries_4_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h4 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h4) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_4_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_4_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_4_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_4_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_4_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :98:33]
entries_4_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :99:33]
entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :102:33]
entries_4_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :101:33]
entries_4_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h5) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_5_tag <= 10'h0; // @[loop.scala:65:22]
entries_5_conf <= 3'h0; // @[loop.scala:65:22]
entries_5_age <= 3'h0; // @[loop.scala:65:22]
entries_5_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h5 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h5) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_5_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_5_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_5_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_5_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_5_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :98:33]
entries_5_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :99:33]
entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :102:33]
entries_5_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :101:33]
entries_5_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h6) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_6_tag <= 10'h0; // @[loop.scala:65:22]
entries_6_conf <= 3'h0; // @[loop.scala:65:22]
entries_6_age <= 3'h0; // @[loop.scala:65:22]
entries_6_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h6 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h6) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_6_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_6_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_6_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_6_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_6_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :98:33]
entries_6_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :99:33]
entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :102:33]
entries_6_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :101:33]
entries_6_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h7) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_7_tag <= 10'h0; // @[loop.scala:65:22]
entries_7_conf <= 3'h0; // @[loop.scala:65:22]
entries_7_age <= 3'h0; // @[loop.scala:65:22]
entries_7_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h7 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h7) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_7_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_7_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_7_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_7_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_7_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :98:33]
entries_7_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :99:33]
entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :102:33]
entries_7_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :101:33]
entries_7_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h8) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_8_tag <= 10'h0; // @[loop.scala:65:22]
entries_8_conf <= 3'h0; // @[loop.scala:65:22]
entries_8_age <= 3'h0; // @[loop.scala:65:22]
entries_8_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h8 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h8) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_8_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_8_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_8_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_8_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_8_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :98:33]
entries_8_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :99:33]
entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :102:33]
entries_8_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :101:33]
entries_8_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h9) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_9_tag <= 10'h0; // @[loop.scala:65:22]
entries_9_conf <= 3'h0; // @[loop.scala:65:22]
entries_9_age <= 3'h0; // @[loop.scala:65:22]
entries_9_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h9 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h9) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_9_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_9_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_9_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_9_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_9_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :98:33]
entries_9_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :99:33]
entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :102:33]
entries_9_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :101:33]
entries_9_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hA) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_10_tag <= 10'h0; // @[loop.scala:65:22]
entries_10_conf <= 3'h0; // @[loop.scala:65:22]
entries_10_age <= 3'h0; // @[loop.scala:65:22]
entries_10_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hA : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hA) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_10_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_10_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_10_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_10_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_10_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :98:33]
entries_10_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :99:33]
entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :102:33]
entries_10_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :101:33]
entries_10_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hB) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_11_tag <= 10'h0; // @[loop.scala:65:22]
entries_11_conf <= 3'h0; // @[loop.scala:65:22]
entries_11_age <= 3'h0; // @[loop.scala:65:22]
entries_11_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hB : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hB) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_11_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_11_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_11_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_11_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_11_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :98:33]
entries_11_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :99:33]
entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :102:33]
entries_11_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :101:33]
entries_11_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hC) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_12_tag <= 10'h0; // @[loop.scala:65:22]
entries_12_conf <= 3'h0; // @[loop.scala:65:22]
entries_12_age <= 3'h0; // @[loop.scala:65:22]
entries_12_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hC : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hC) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_12_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_12_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_12_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_12_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_12_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :98:33]
entries_12_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :99:33]
entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :102:33]
entries_12_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :101:33]
entries_12_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hD) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_13_tag <= 10'h0; // @[loop.scala:65:22]
entries_13_conf <= 3'h0; // @[loop.scala:65:22]
entries_13_age <= 3'h0; // @[loop.scala:65:22]
entries_13_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hD : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hD) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_13_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_13_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_13_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_13_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_13_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :98:33]
entries_13_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :99:33]
entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :102:33]
entries_13_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :101:33]
entries_13_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hE) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_14_tag <= 10'h0; // @[loop.scala:65:22]
entries_14_conf <= 3'h0; // @[loop.scala:65:22]
entries_14_age <= 3'h0; // @[loop.scala:65:22]
entries_14_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hE : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hE) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_14_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_14_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_14_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_14_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_14_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :98:33]
entries_14_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :99:33]
entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :102:33]
entries_14_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :101:33]
entries_14_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & (&reset_idx)) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_15_tag <= 10'h0; // @[loop.scala:65:22]
entries_15_conf <= 3'h0; // @[loop.scala:65:22]
entries_15_age <= 3'h0; // @[loop.scala:65:22]
entries_15_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? (&(io_update_idx_0[3:0])) : _T_58 & _T_62 & (&(io_update_idx_0[3:0]))) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_15_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_15_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_15_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_15_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_15_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :98:33]
entries_15_age <= 3'h7; // @[loop.scala:65:22]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :99:33]
entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :102:33]
entries_15_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :101:33]
entries_15_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
f3_entry_tag <= f2_entry_tag; // @[loop.scala:66:28, :72:27]
f3_entry_conf <= f2_entry_conf; // @[loop.scala:66:28, :72:27]
f3_entry_age <= f2_entry_age; // @[loop.scala:66:28, :72:27]
f3_entry_p_cnt <= f2_entry_p_cnt; // @[loop.scala:66:28, :72:27]
f3_entry_s_cnt <= f2_entry_s_cnt; // @[loop.scala:66:28, :72:27]
f3_scnt_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :73:69]
f3_tag <= _f3_tag_T; // @[loop.scala:76:{27,41}]
f4_fire <= io_f3_req_fire_0; // @[loop.scala:39:9, :88:27]
f4_entry_tag <= f3_entry_tag; // @[loop.scala:72:27, :89:27]
f4_entry_conf <= f3_entry_conf; // @[loop.scala:72:27, :89:27]
f4_entry_age <= f3_entry_age; // @[loop.scala:72:27, :89:27]
f4_entry_p_cnt <= f3_entry_p_cnt; // @[loop.scala:72:27, :89:27]
f4_entry_s_cnt <= f3_entry_s_cnt; // @[loop.scala:72:27, :89:27]
f4_tag <= f3_tag; // @[loop.scala:76:27, :90:27]
f4_scnt <= f3_scnt; // @[loop.scala:73:23, :91:27]
f4_idx_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :92:35]
f4_idx <= f4_idx_REG; // @[loop.scala:92:{27,35}]
always @(posedge)
assign io_f3_pred = io_f3_pred_0; // @[loop.scala:39:9]
assign io_f3_meta_s_cnt = io_f3_meta_s_cnt_0; // @[loop.scala:39:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLNoC_2_router_9ClockSinkDomain :
output auto : { routers_debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, routers_source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, routers_source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, routers_source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip routers_dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip routers_dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip routers_dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst routers of Router_56
connect routers.clock, childClock
connect routers.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
connect clockNodeIn, auto.clock_in
connect routers.auto.dest_nodes_in_0, auto.routers_dest_nodes_in_0
connect routers.auto.dest_nodes_in_1, auto.routers_dest_nodes_in_1
connect routers.auto.dest_nodes_in_2, auto.routers_dest_nodes_in_2
connect routers.auto.source_nodes_out_0.vc_free, auto.routers_source_nodes_out_0.vc_free
connect routers.auto.source_nodes_out_0.credit_return, auto.routers_source_nodes_out_0.credit_return
connect auto.routers_source_nodes_out_0.flit, routers.auto.source_nodes_out_0.flit
connect routers.auto.source_nodes_out_1.vc_free, auto.routers_source_nodes_out_1.vc_free
connect routers.auto.source_nodes_out_1.credit_return, auto.routers_source_nodes_out_1.credit_return
connect auto.routers_source_nodes_out_1.flit, routers.auto.source_nodes_out_1.flit
connect routers.auto.source_nodes_out_2.vc_free, auto.routers_source_nodes_out_2.vc_free
connect routers.auto.source_nodes_out_2.credit_return, auto.routers_source_nodes_out_2.credit_return
connect auto.routers_source_nodes_out_2.flit, routers.auto.source_nodes_out_2.flit
connect auto.routers_debug_out, routers.auto.debug_out
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset | module TLNoC_2_router_9ClockSinkDomain( // @[ClockDomain.scala:14:9]
output [3:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_routers_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_routers_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_routers_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_routers_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_routers_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_routers_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_routers_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_routers_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_routers_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_routers_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_routers_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_routers_dest_nodes_in_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
Router_56 routers ( // @[NoC.scala:67:22]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0),
.auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1),
.auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2),
.auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0),
.auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1),
.auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2),
.auto_source_nodes_out_2_flit_0_valid (auto_routers_source_nodes_out_2_flit_0_valid),
.auto_source_nodes_out_2_flit_0_bits_head (auto_routers_source_nodes_out_2_flit_0_bits_head),
.auto_source_nodes_out_2_flit_0_bits_tail (auto_routers_source_nodes_out_2_flit_0_bits_tail),
.auto_source_nodes_out_2_flit_0_bits_payload (auto_routers_source_nodes_out_2_flit_0_bits_payload),
.auto_source_nodes_out_2_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_2_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_2_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_2_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_2_credit_return (auto_routers_source_nodes_out_2_credit_return),
.auto_source_nodes_out_2_vc_free (auto_routers_source_nodes_out_2_vc_free),
.auto_source_nodes_out_1_flit_0_valid (auto_routers_source_nodes_out_1_flit_0_valid),
.auto_source_nodes_out_1_flit_0_bits_head (auto_routers_source_nodes_out_1_flit_0_bits_head),
.auto_source_nodes_out_1_flit_0_bits_tail (auto_routers_source_nodes_out_1_flit_0_bits_tail),
.auto_source_nodes_out_1_flit_0_bits_payload (auto_routers_source_nodes_out_1_flit_0_bits_payload),
.auto_source_nodes_out_1_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_1_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_1_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_1_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_1_credit_return (auto_routers_source_nodes_out_1_credit_return),
.auto_source_nodes_out_1_vc_free (auto_routers_source_nodes_out_1_vc_free),
.auto_source_nodes_out_0_flit_0_valid (auto_routers_source_nodes_out_0_flit_0_valid),
.auto_source_nodes_out_0_flit_0_bits_head (auto_routers_source_nodes_out_0_flit_0_bits_head),
.auto_source_nodes_out_0_flit_0_bits_tail (auto_routers_source_nodes_out_0_flit_0_bits_tail),
.auto_source_nodes_out_0_flit_0_bits_payload (auto_routers_source_nodes_out_0_flit_0_bits_payload),
.auto_source_nodes_out_0_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_0_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_0_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_0_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_0_credit_return (auto_routers_source_nodes_out_0_credit_return),
.auto_source_nodes_out_0_vc_free (auto_routers_source_nodes_out_0_vc_free),
.auto_dest_nodes_in_2_flit_0_valid (auto_routers_dest_nodes_in_2_flit_0_valid),
.auto_dest_nodes_in_2_flit_0_bits_head (auto_routers_dest_nodes_in_2_flit_0_bits_head),
.auto_dest_nodes_in_2_flit_0_bits_tail (auto_routers_dest_nodes_in_2_flit_0_bits_tail),
.auto_dest_nodes_in_2_flit_0_bits_payload (auto_routers_dest_nodes_in_2_flit_0_bits_payload),
.auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_2_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_2_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_2_credit_return (auto_routers_dest_nodes_in_2_credit_return),
.auto_dest_nodes_in_2_vc_free (auto_routers_dest_nodes_in_2_vc_free),
.auto_dest_nodes_in_1_flit_0_valid (auto_routers_dest_nodes_in_1_flit_0_valid),
.auto_dest_nodes_in_1_flit_0_bits_head (auto_routers_dest_nodes_in_1_flit_0_bits_head),
.auto_dest_nodes_in_1_flit_0_bits_tail (auto_routers_dest_nodes_in_1_flit_0_bits_tail),
.auto_dest_nodes_in_1_flit_0_bits_payload (auto_routers_dest_nodes_in_1_flit_0_bits_payload),
.auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_1_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_1_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_1_credit_return (auto_routers_dest_nodes_in_1_credit_return),
.auto_dest_nodes_in_1_vc_free (auto_routers_dest_nodes_in_1_vc_free),
.auto_dest_nodes_in_0_flit_0_valid (auto_routers_dest_nodes_in_0_flit_0_valid),
.auto_dest_nodes_in_0_flit_0_bits_head (auto_routers_dest_nodes_in_0_flit_0_bits_head),
.auto_dest_nodes_in_0_flit_0_bits_tail (auto_routers_dest_nodes_in_0_flit_0_bits_tail),
.auto_dest_nodes_in_0_flit_0_bits_payload (auto_routers_dest_nodes_in_0_flit_0_bits_payload),
.auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_0_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_0_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_0_credit_return (auto_routers_dest_nodes_in_0_credit_return),
.auto_dest_nodes_in_0_vc_free (auto_routers_dest_nodes_in_0_vc_free)
); // @[NoC.scala:67:22]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_22 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_22( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_cbus_in_i2_o1_a29d64s8k1z4u :
input clock : Clock
input reset : Reset
output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_1.d.bits.corrupt
invalidate anonIn_1.d.bits.data
invalidate anonIn_1.d.bits.denied
invalidate anonIn_1.d.bits.sink
invalidate anonIn_1.d.bits.source
invalidate anonIn_1.d.bits.size
invalidate anonIn_1.d.bits.param
invalidate anonIn_1.d.bits.opcode
invalidate anonIn_1.d.valid
invalidate anonIn_1.d.ready
invalidate anonIn_1.a.bits.corrupt
invalidate anonIn_1.a.bits.data
invalidate anonIn_1.a.bits.mask
invalidate anonIn_1.a.bits.address
invalidate anonIn_1.a.bits.source
invalidate anonIn_1.a.bits.size
invalidate anonIn_1.a.bits.param
invalidate anonIn_1.a.bits.opcode
invalidate anonIn_1.a.valid
invalidate anonIn_1.a.ready
inst monitor of TLMonitor_27
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
inst monitor_1 of TLMonitor_28
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt
connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data
connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied
connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink
connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source
connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size
connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param
connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode
connect monitor_1.io.in.d.valid, anonIn_1.d.valid
connect monitor_1.io.in.d.ready, anonIn_1.d.ready
connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt
connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data
connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask
connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address
connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source
connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size
connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param
connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode
connect monitor_1.io.in.a.valid, anonIn_1.a.valid
connect monitor_1.io.in.a.ready, anonIn_1.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in_0
connect anonIn_1, auto.anon_in_1
wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[2]
connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt
connect in[0].a.bits.data, anonIn.a.bits.data
connect in[0].a.bits.mask, anonIn.a.bits.mask
connect in[0].a.bits.address, anonIn.a.bits.address
connect in[0].a.bits.source, anonIn.a.bits.source
connect in[0].a.bits.size, anonIn.a.bits.size
connect in[0].a.bits.param, anonIn.a.bits.param
connect in[0].a.bits.opcode, anonIn.a.bits.opcode
connect in[0].a.valid, anonIn.a.valid
connect anonIn.a.ready, in[0].a.ready
node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0))
connect in[0].a.bits.source, _in_0_a_bits_source_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<29>(0h0)
connect _WIRE.bits.source, UInt<8>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
invalidate _WIRE_1.bits.corrupt
invalidate _WIRE_1.bits.data
invalidate _WIRE_1.bits.mask
invalidate _WIRE_1.bits.address
invalidate _WIRE_1.bits.source
invalidate _WIRE_1.bits.size
invalidate _WIRE_1.bits.param
invalidate _WIRE_1.bits.opcode
invalidate _WIRE_1.valid
invalidate _WIRE_1.ready
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.mask, UInt<8>(0h0)
connect _WIRE_2.bits.address, UInt<29>(0h0)
connect _WIRE_2.bits.source, UInt<7>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<2>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
invalidate _WIRE_3.bits.corrupt
invalidate _WIRE_3.bits.data
invalidate _WIRE_3.bits.mask
invalidate _WIRE_3.bits.address
invalidate _WIRE_3.bits.source
invalidate _WIRE_3.bits.size
invalidate _WIRE_3.bits.param
invalidate _WIRE_3.bits.opcode
invalidate _WIRE_3.valid
invalidate _WIRE_3.ready
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<8>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.valid, UInt<1>(0h0)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<29>(0h0)
connect _WIRE_8.bits.source, UInt<8>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
invalidate _WIRE_9.bits.corrupt
invalidate _WIRE_9.bits.data
invalidate _WIRE_9.bits.address
invalidate _WIRE_9.bits.source
invalidate _WIRE_9.bits.size
invalidate _WIRE_9.bits.param
invalidate _WIRE_9.bits.opcode
invalidate _WIRE_9.valid
invalidate _WIRE_9.ready
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
invalidate _WIRE_11.bits.corrupt
invalidate _WIRE_11.bits.data
invalidate _WIRE_11.bits.address
invalidate _WIRE_11.bits.source
invalidate _WIRE_11.bits.size
invalidate _WIRE_11.bits.param
invalidate _WIRE_11.bits.opcode
invalidate _WIRE_11.valid
invalidate _WIRE_11.ready
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<8>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
connect _WIRE_13.valid, UInt<1>(0h0)
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
connect _WIRE_15.ready, UInt<1>(0h1)
connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt
connect anonIn.d.bits.data, in[0].d.bits.data
connect anonIn.d.bits.denied, in[0].d.bits.denied
connect anonIn.d.bits.sink, in[0].d.bits.sink
connect anonIn.d.bits.source, in[0].d.bits.source
connect anonIn.d.bits.size, in[0].d.bits.size
connect anonIn.d.bits.param, in[0].d.bits.param
connect anonIn.d.bits.opcode, in[0].d.bits.opcode
connect anonIn.d.valid, in[0].d.valid
connect in[0].d.ready, anonIn.d.ready
node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 6, 0)
connect anonIn.d.bits.source, _anonIn_d_bits_source_T
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_16.bits.sink, UInt<1>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
invalidate _WIRE_17.bits.sink
invalidate _WIRE_17.valid
invalidate _WIRE_17.ready
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_18.bits.sink, UInt<1>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
invalidate _WIRE_19.bits.sink
invalidate _WIRE_19.valid
invalidate _WIRE_19.ready
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_20.bits.sink, UInt<1>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
connect _WIRE_21.valid, UInt<1>(0h0)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_22.bits.sink, UInt<1>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
connect _WIRE_23.ready, UInt<1>(0h1)
connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt
connect in[1].a.bits.data, anonIn_1.a.bits.data
connect in[1].a.bits.mask, anonIn_1.a.bits.mask
connect in[1].a.bits.address, anonIn_1.a.bits.address
connect in[1].a.bits.source, anonIn_1.a.bits.source
connect in[1].a.bits.size, anonIn_1.a.bits.size
connect in[1].a.bits.param, anonIn_1.a.bits.param
connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode
connect in[1].a.valid, anonIn_1.a.valid
connect anonIn_1.a.ready, in[1].a.ready
node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<8>(0h80))
connect in[1].a.bits.source, _in_1_a_bits_source_T
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.mask, UInt<8>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<8>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<2>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
invalidate _WIRE_25.bits.corrupt
invalidate _WIRE_25.bits.data
invalidate _WIRE_25.bits.mask
invalidate _WIRE_25.bits.address
invalidate _WIRE_25.bits.source
invalidate _WIRE_25.bits.size
invalidate _WIRE_25.bits.param
invalidate _WIRE_25.bits.opcode
invalidate _WIRE_25.valid
invalidate _WIRE_25.ready
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.mask, UInt<8>(0h0)
connect _WIRE_26.bits.address, UInt<29>(0h0)
connect _WIRE_26.bits.source, UInt<1>(0h0)
connect _WIRE_26.bits.size, UInt<4>(0h0)
connect _WIRE_26.bits.param, UInt<2>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
invalidate _WIRE_27.bits.corrupt
invalidate _WIRE_27.bits.data
invalidate _WIRE_27.bits.mask
invalidate _WIRE_27.bits.address
invalidate _WIRE_27.bits.source
invalidate _WIRE_27.bits.size
invalidate _WIRE_27.bits.param
invalidate _WIRE_27.bits.opcode
invalidate _WIRE_27.valid
invalidate _WIRE_27.ready
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.mask, UInt<8>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<8>(0h0)
connect _WIRE_28.bits.size, UInt<4>(0h0)
connect _WIRE_28.bits.param, UInt<2>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
connect _WIRE_29.ready, UInt<1>(0h1)
wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_30.bits.corrupt, UInt<1>(0h0)
connect _WIRE_30.bits.data, UInt<64>(0h0)
connect _WIRE_30.bits.mask, UInt<8>(0h0)
connect _WIRE_30.bits.address, UInt<29>(0h0)
connect _WIRE_30.bits.source, UInt<1>(0h0)
connect _WIRE_30.bits.size, UInt<4>(0h0)
connect _WIRE_30.bits.param, UInt<2>(0h0)
connect _WIRE_30.bits.opcode, UInt<3>(0h0)
connect _WIRE_30.valid, UInt<1>(0h0)
connect _WIRE_30.ready, UInt<1>(0h0)
wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_31.bits, _WIRE_30.bits
connect _WIRE_31.valid, _WIRE_30.valid
connect _WIRE_31.ready, _WIRE_30.ready
connect _WIRE_31.valid, UInt<1>(0h0)
wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_32.bits.corrupt, UInt<1>(0h0)
connect _WIRE_32.bits.data, UInt<64>(0h0)
connect _WIRE_32.bits.address, UInt<29>(0h0)
connect _WIRE_32.bits.source, UInt<8>(0h0)
connect _WIRE_32.bits.size, UInt<4>(0h0)
connect _WIRE_32.bits.param, UInt<3>(0h0)
connect _WIRE_32.bits.opcode, UInt<3>(0h0)
connect _WIRE_32.valid, UInt<1>(0h0)
connect _WIRE_32.ready, UInt<1>(0h0)
wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_33.bits, _WIRE_32.bits
connect _WIRE_33.valid, _WIRE_32.valid
connect _WIRE_33.ready, _WIRE_32.ready
invalidate _WIRE_33.bits.corrupt
invalidate _WIRE_33.bits.data
invalidate _WIRE_33.bits.address
invalidate _WIRE_33.bits.source
invalidate _WIRE_33.bits.size
invalidate _WIRE_33.bits.param
invalidate _WIRE_33.bits.opcode
invalidate _WIRE_33.valid
invalidate _WIRE_33.ready
wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_34.bits.corrupt, UInt<1>(0h0)
connect _WIRE_34.bits.data, UInt<64>(0h0)
connect _WIRE_34.bits.address, UInt<29>(0h0)
connect _WIRE_34.bits.source, UInt<1>(0h0)
connect _WIRE_34.bits.size, UInt<4>(0h0)
connect _WIRE_34.bits.param, UInt<3>(0h0)
connect _WIRE_34.bits.opcode, UInt<3>(0h0)
connect _WIRE_34.valid, UInt<1>(0h0)
connect _WIRE_34.ready, UInt<1>(0h0)
wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_35.bits, _WIRE_34.bits
connect _WIRE_35.valid, _WIRE_34.valid
connect _WIRE_35.ready, _WIRE_34.ready
invalidate _WIRE_35.bits.corrupt
invalidate _WIRE_35.bits.data
invalidate _WIRE_35.bits.address
invalidate _WIRE_35.bits.source
invalidate _WIRE_35.bits.size
invalidate _WIRE_35.bits.param
invalidate _WIRE_35.bits.opcode
invalidate _WIRE_35.valid
invalidate _WIRE_35.ready
wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_36.bits.corrupt, UInt<1>(0h0)
connect _WIRE_36.bits.data, UInt<64>(0h0)
connect _WIRE_36.bits.address, UInt<29>(0h0)
connect _WIRE_36.bits.source, UInt<8>(0h0)
connect _WIRE_36.bits.size, UInt<4>(0h0)
connect _WIRE_36.bits.param, UInt<3>(0h0)
connect _WIRE_36.bits.opcode, UInt<3>(0h0)
connect _WIRE_36.valid, UInt<1>(0h0)
connect _WIRE_36.ready, UInt<1>(0h0)
wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_37.bits, _WIRE_36.bits
connect _WIRE_37.valid, _WIRE_36.valid
connect _WIRE_37.ready, _WIRE_36.ready
connect _WIRE_37.valid, UInt<1>(0h0)
wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_38.bits.corrupt, UInt<1>(0h0)
connect _WIRE_38.bits.data, UInt<64>(0h0)
connect _WIRE_38.bits.address, UInt<29>(0h0)
connect _WIRE_38.bits.source, UInt<1>(0h0)
connect _WIRE_38.bits.size, UInt<4>(0h0)
connect _WIRE_38.bits.param, UInt<3>(0h0)
connect _WIRE_38.bits.opcode, UInt<3>(0h0)
connect _WIRE_38.valid, UInt<1>(0h0)
connect _WIRE_38.ready, UInt<1>(0h0)
wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_39.bits, _WIRE_38.bits
connect _WIRE_39.valid, _WIRE_38.valid
connect _WIRE_39.ready, _WIRE_38.ready
connect _WIRE_39.ready, UInt<1>(0h1)
connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt
connect anonIn_1.d.bits.data, in[1].d.bits.data
connect anonIn_1.d.bits.denied, in[1].d.bits.denied
connect anonIn_1.d.bits.sink, in[1].d.bits.sink
connect anonIn_1.d.bits.source, in[1].d.bits.source
connect anonIn_1.d.bits.size, in[1].d.bits.size
connect anonIn_1.d.bits.param, in[1].d.bits.param
connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode
connect anonIn_1.d.valid, in[1].d.valid
connect in[1].d.ready, anonIn_1.d.ready
connect anonIn_1.d.bits.source, UInt<1>(0h0)
wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_40.bits.sink, UInt<1>(0h0)
connect _WIRE_40.valid, UInt<1>(0h0)
connect _WIRE_40.ready, UInt<1>(0h0)
wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_41.bits, _WIRE_40.bits
connect _WIRE_41.valid, _WIRE_40.valid
connect _WIRE_41.ready, _WIRE_40.ready
invalidate _WIRE_41.bits.sink
invalidate _WIRE_41.valid
invalidate _WIRE_41.ready
wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_42.bits.sink, UInt<1>(0h0)
connect _WIRE_42.valid, UInt<1>(0h0)
connect _WIRE_42.ready, UInt<1>(0h0)
wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_43.bits, _WIRE_42.bits
connect _WIRE_43.valid, _WIRE_42.valid
connect _WIRE_43.ready, _WIRE_42.ready
invalidate _WIRE_43.bits.sink
invalidate _WIRE_43.valid
invalidate _WIRE_43.ready
wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_44.bits.sink, UInt<1>(0h0)
connect _WIRE_44.valid, UInt<1>(0h0)
connect _WIRE_44.ready, UInt<1>(0h0)
wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_45.bits, _WIRE_44.bits
connect _WIRE_45.valid, _WIRE_44.valid
connect _WIRE_45.ready, _WIRE_44.ready
connect _WIRE_45.valid, UInt<1>(0h0)
wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_46.bits.sink, UInt<1>(0h0)
connect _WIRE_46.valid, UInt<1>(0h0)
connect _WIRE_46.ready, UInt<1>(0h0)
wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_47.bits, _WIRE_46.bits
connect _WIRE_47.valid, _WIRE_46.valid
connect _WIRE_47.ready, _WIRE_46.ready
connect _WIRE_47.ready, UInt<1>(0h1)
wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1]
connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt
connect anonOut.a.bits.data, out[0].a.bits.data
connect anonOut.a.bits.mask, out[0].a.bits.mask
connect anonOut.a.bits.address, out[0].a.bits.address
connect anonOut.a.bits.source, out[0].a.bits.source
connect anonOut.a.bits.size, out[0].a.bits.size
connect anonOut.a.bits.param, out[0].a.bits.param
connect anonOut.a.bits.opcode, out[0].a.bits.opcode
connect anonOut.a.valid, out[0].a.valid
connect out[0].a.ready, anonOut.a.ready
wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_48.bits.corrupt, UInt<1>(0h0)
connect _WIRE_48.bits.data, UInt<64>(0h0)
connect _WIRE_48.bits.mask, UInt<8>(0h0)
connect _WIRE_48.bits.address, UInt<29>(0h0)
connect _WIRE_48.bits.source, UInt<8>(0h0)
connect _WIRE_48.bits.size, UInt<4>(0h0)
connect _WIRE_48.bits.param, UInt<2>(0h0)
connect _WIRE_48.bits.opcode, UInt<3>(0h0)
connect _WIRE_48.valid, UInt<1>(0h0)
connect _WIRE_48.ready, UInt<1>(0h0)
wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_49.bits, _WIRE_48.bits
connect _WIRE_49.valid, _WIRE_48.valid
connect _WIRE_49.ready, _WIRE_48.ready
invalidate _WIRE_49.bits.corrupt
invalidate _WIRE_49.bits.data
invalidate _WIRE_49.bits.mask
invalidate _WIRE_49.bits.address
invalidate _WIRE_49.bits.source
invalidate _WIRE_49.bits.size
invalidate _WIRE_49.bits.param
invalidate _WIRE_49.bits.opcode
invalidate _WIRE_49.valid
invalidate _WIRE_49.ready
wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_50.bits.corrupt, UInt<1>(0h0)
connect _WIRE_50.bits.data, UInt<64>(0h0)
connect _WIRE_50.bits.mask, UInt<8>(0h0)
connect _WIRE_50.bits.address, UInt<29>(0h0)
connect _WIRE_50.bits.source, UInt<8>(0h0)
connect _WIRE_50.bits.size, UInt<4>(0h0)
connect _WIRE_50.bits.param, UInt<2>(0h0)
connect _WIRE_50.bits.opcode, UInt<3>(0h0)
connect _WIRE_50.valid, UInt<1>(0h0)
connect _WIRE_50.ready, UInt<1>(0h0)
wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_51.bits, _WIRE_50.bits
connect _WIRE_51.valid, _WIRE_50.valid
connect _WIRE_51.ready, _WIRE_50.ready
invalidate _WIRE_51.bits.corrupt
invalidate _WIRE_51.bits.data
invalidate _WIRE_51.bits.mask
invalidate _WIRE_51.bits.address
invalidate _WIRE_51.bits.source
invalidate _WIRE_51.bits.size
invalidate _WIRE_51.bits.param
invalidate _WIRE_51.bits.opcode
invalidate _WIRE_51.valid
invalidate _WIRE_51.ready
wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_52.bits.corrupt, UInt<1>(0h0)
connect _WIRE_52.bits.data, UInt<64>(0h0)
connect _WIRE_52.bits.mask, UInt<8>(0h0)
connect _WIRE_52.bits.address, UInt<29>(0h0)
connect _WIRE_52.bits.source, UInt<8>(0h0)
connect _WIRE_52.bits.size, UInt<4>(0h0)
connect _WIRE_52.bits.param, UInt<2>(0h0)
connect _WIRE_52.bits.opcode, UInt<3>(0h0)
connect _WIRE_52.valid, UInt<1>(0h0)
connect _WIRE_52.ready, UInt<1>(0h0)
wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_53.bits, _WIRE_52.bits
connect _WIRE_53.valid, _WIRE_52.valid
connect _WIRE_53.ready, _WIRE_52.ready
connect _WIRE_53.valid, UInt<1>(0h0)
wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_54.bits.corrupt, UInt<1>(0h0)
connect _WIRE_54.bits.data, UInt<64>(0h0)
connect _WIRE_54.bits.mask, UInt<8>(0h0)
connect _WIRE_54.bits.address, UInt<29>(0h0)
connect _WIRE_54.bits.source, UInt<8>(0h0)
connect _WIRE_54.bits.size, UInt<4>(0h0)
connect _WIRE_54.bits.param, UInt<2>(0h0)
connect _WIRE_54.bits.opcode, UInt<3>(0h0)
connect _WIRE_54.valid, UInt<1>(0h0)
connect _WIRE_54.ready, UInt<1>(0h0)
wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_55.bits, _WIRE_54.bits
connect _WIRE_55.valid, _WIRE_54.valid
connect _WIRE_55.ready, _WIRE_54.ready
connect _WIRE_55.ready, UInt<1>(0h1)
wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_56.bits.corrupt, UInt<1>(0h0)
connect _WIRE_56.bits.data, UInt<64>(0h0)
connect _WIRE_56.bits.address, UInt<29>(0h0)
connect _WIRE_56.bits.source, UInt<8>(0h0)
connect _WIRE_56.bits.size, UInt<4>(0h0)
connect _WIRE_56.bits.param, UInt<3>(0h0)
connect _WIRE_56.bits.opcode, UInt<3>(0h0)
connect _WIRE_56.valid, UInt<1>(0h0)
connect _WIRE_56.ready, UInt<1>(0h0)
wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_57.bits, _WIRE_56.bits
connect _WIRE_57.valid, _WIRE_56.valid
connect _WIRE_57.ready, _WIRE_56.ready
invalidate _WIRE_57.bits.corrupt
invalidate _WIRE_57.bits.data
invalidate _WIRE_57.bits.address
invalidate _WIRE_57.bits.source
invalidate _WIRE_57.bits.size
invalidate _WIRE_57.bits.param
invalidate _WIRE_57.bits.opcode
invalidate _WIRE_57.valid
invalidate _WIRE_57.ready
wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_58.bits.corrupt, UInt<1>(0h0)
connect _WIRE_58.bits.data, UInt<64>(0h0)
connect _WIRE_58.bits.address, UInt<29>(0h0)
connect _WIRE_58.bits.source, UInt<8>(0h0)
connect _WIRE_58.bits.size, UInt<4>(0h0)
connect _WIRE_58.bits.param, UInt<3>(0h0)
connect _WIRE_58.bits.opcode, UInt<3>(0h0)
connect _WIRE_58.valid, UInt<1>(0h0)
connect _WIRE_58.ready, UInt<1>(0h0)
wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_59.bits, _WIRE_58.bits
connect _WIRE_59.valid, _WIRE_58.valid
connect _WIRE_59.ready, _WIRE_58.ready
invalidate _WIRE_59.bits.corrupt
invalidate _WIRE_59.bits.data
invalidate _WIRE_59.bits.address
invalidate _WIRE_59.bits.source
invalidate _WIRE_59.bits.size
invalidate _WIRE_59.bits.param
invalidate _WIRE_59.bits.opcode
invalidate _WIRE_59.valid
invalidate _WIRE_59.ready
wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_60.bits.corrupt, UInt<1>(0h0)
connect _WIRE_60.bits.data, UInt<64>(0h0)
connect _WIRE_60.bits.address, UInt<29>(0h0)
connect _WIRE_60.bits.source, UInt<8>(0h0)
connect _WIRE_60.bits.size, UInt<4>(0h0)
connect _WIRE_60.bits.param, UInt<3>(0h0)
connect _WIRE_60.bits.opcode, UInt<3>(0h0)
connect _WIRE_60.valid, UInt<1>(0h0)
connect _WIRE_60.ready, UInt<1>(0h0)
wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_61.bits, _WIRE_60.bits
connect _WIRE_61.valid, _WIRE_60.valid
connect _WIRE_61.ready, _WIRE_60.ready
connect _WIRE_61.ready, UInt<1>(0h1)
wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_62.bits.corrupt, UInt<1>(0h0)
connect _WIRE_62.bits.data, UInt<64>(0h0)
connect _WIRE_62.bits.address, UInt<29>(0h0)
connect _WIRE_62.bits.source, UInt<8>(0h0)
connect _WIRE_62.bits.size, UInt<4>(0h0)
connect _WIRE_62.bits.param, UInt<3>(0h0)
connect _WIRE_62.bits.opcode, UInt<3>(0h0)
connect _WIRE_62.valid, UInt<1>(0h0)
connect _WIRE_62.ready, UInt<1>(0h0)
wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_63.bits, _WIRE_62.bits
connect _WIRE_63.valid, _WIRE_62.valid
connect _WIRE_63.ready, _WIRE_62.ready
connect _WIRE_63.valid, UInt<1>(0h0)
connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt
connect out[0].d.bits.data, anonOut.d.bits.data
connect out[0].d.bits.denied, anonOut.d.bits.denied
connect out[0].d.bits.sink, anonOut.d.bits.sink
connect out[0].d.bits.source, anonOut.d.bits.source
connect out[0].d.bits.size, anonOut.d.bits.size
connect out[0].d.bits.param, anonOut.d.bits.param
connect out[0].d.bits.opcode, anonOut.d.bits.opcode
connect out[0].d.valid, anonOut.d.valid
connect anonOut.d.ready, out[0].d.ready
node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0))
connect out[0].d.bits.sink, _out_0_d_bits_sink_T
wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_64.bits.sink, UInt<1>(0h0)
connect _WIRE_64.valid, UInt<1>(0h0)
connect _WIRE_64.ready, UInt<1>(0h0)
wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_65.bits, _WIRE_64.bits
connect _WIRE_65.valid, _WIRE_64.valid
connect _WIRE_65.ready, _WIRE_64.ready
invalidate _WIRE_65.bits.sink
invalidate _WIRE_65.valid
invalidate _WIRE_65.ready
wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_66.bits.sink, UInt<1>(0h0)
connect _WIRE_66.valid, UInt<1>(0h0)
connect _WIRE_66.ready, UInt<1>(0h0)
wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_67.bits, _WIRE_66.bits
connect _WIRE_67.valid, _WIRE_66.valid
connect _WIRE_67.ready, _WIRE_66.ready
invalidate _WIRE_67.bits.sink
invalidate _WIRE_67.valid
invalidate _WIRE_67.ready
wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_68.bits.sink, UInt<1>(0h0)
connect _WIRE_68.valid, UInt<1>(0h0)
connect _WIRE_68.ready, UInt<1>(0h0)
wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_69.bits, _WIRE_68.bits
connect _WIRE_69.valid, _WIRE_68.valid
connect _WIRE_69.ready, _WIRE_68.ready
connect _WIRE_69.ready, UInt<1>(0h1)
wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_70.bits.sink, UInt<1>(0h0)
connect _WIRE_70.valid, UInt<1>(0h0)
connect _WIRE_70.ready, UInt<1>(0h0)
wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_71.bits, _WIRE_70.bits
connect _WIRE_71.valid, _WIRE_70.valid
connect _WIRE_71.ready, _WIRE_70.ready
connect _WIRE_71.valid, UInt<1>(0h0)
wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0)
connect _addressC_WIRE.bits.data, UInt<64>(0h0)
connect _addressC_WIRE.bits.address, UInt<29>(0h0)
connect _addressC_WIRE.bits.source, UInt<8>(0h0)
connect _addressC_WIRE.bits.size, UInt<4>(0h0)
connect _addressC_WIRE.bits.param, UInt<3>(0h0)
connect _addressC_WIRE.bits.opcode, UInt<3>(0h0)
connect _addressC_WIRE.valid, UInt<1>(0h0)
connect _addressC_WIRE.ready, UInt<1>(0h0)
wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_1.bits, _addressC_WIRE.bits
connect _addressC_WIRE_1.valid, _addressC_WIRE.valid
connect _addressC_WIRE_1.ready, _addressC_WIRE.ready
wire _addressC_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _addressC_WIRE_2.bits.data, UInt<64>(0h0)
connect _addressC_WIRE_2.bits.address, UInt<29>(0h0)
connect _addressC_WIRE_2.bits.source, UInt<8>(0h0)
connect _addressC_WIRE_2.bits.size, UInt<4>(0h0)
connect _addressC_WIRE_2.bits.param, UInt<3>(0h0)
connect _addressC_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _addressC_WIRE_2.valid, UInt<1>(0h0)
connect _addressC_WIRE_2.ready, UInt<1>(0h0)
wire _addressC_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_3.bits, _addressC_WIRE_2.bits
connect _addressC_WIRE_3.valid, _addressC_WIRE_2.valid
connect _addressC_WIRE_3.ready, _addressC_WIRE_2.ready
node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_1 = cvt(_requestAIO_T)
node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<1>(0h0)))
node _requestAIO_T_3 = asSInt(_requestAIO_T_2)
node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0)))
node requestAIO_0_0 = or(UInt<1>(0h1), _requestAIO_T_4)
node _requestAIO_T_5 = xor(in[1].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_6 = cvt(_requestAIO_T_5)
node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<1>(0h0)))
node _requestAIO_T_8 = asSInt(_requestAIO_T_7)
node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0)))
node requestAIO_1_0 = or(UInt<1>(0h1), _requestAIO_T_9)
node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0))
node _requestCIO_T_1 = cvt(_requestCIO_T)
node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0)))
node _requestCIO_T_3 = asSInt(_requestCIO_T_2)
node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0)))
node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4)
node _requestCIO_T_5 = xor(_addressC_WIRE_3.bits.address, UInt<1>(0h0))
node _requestCIO_T_6 = cvt(_requestCIO_T_5)
node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0)))
node _requestCIO_T_8 = asSInt(_requestCIO_T_7)
node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0)))
node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_9)
wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE.bits.address, UInt<29>(0h0)
connect _requestBOI_WIRE.bits.source, UInt<8>(0h0)
connect _requestBOI_WIRE.bits.size, UInt<4>(0h0)
connect _requestBOI_WIRE.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE.valid, UInt<1>(0h0)
connect _requestBOI_WIRE.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits
connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid
connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready
node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<7>(0h0))
node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 6, 0)
node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 7)
node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0))
node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits)
node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2)
node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<7>(0h7f))
node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4)
wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE_2.bits.address, UInt<29>(0h0)
connect _requestBOI_WIRE_2.bits.source, UInt<8>(0h0)
connect _requestBOI_WIRE_2.bits.size, UInt<4>(0h0)
connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_2.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_2.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits
connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid
connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready
node requestBOI_0_1 = eq(_requestBOI_WIRE_3.bits.source, UInt<8>(0h80))
node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<7>(0h0))
node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 6, 0)
node _requestDOI_T = shr(out[0].d.bits.source, 7)
node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0))
node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits)
node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2)
node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<7>(0h7f))
node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4)
node requestDOI_0_1 = eq(out[0].d.bits.source, UInt<8>(0h80))
wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE.valid, UInt<1>(0h0)
connect _requestEIO_WIRE.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits
connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid
connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready
wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE_2.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_2.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits
connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid
connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready
node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size)
node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0)
node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1)
node beatsAI_decode = shr(_beatsAI_decode_T_2, 3)
node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2)
node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0))
node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0))
node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size)
node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0)
node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4)
node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 3)
node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2)
node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0))
node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0))
wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0)
connect _beatsBO_WIRE.bits.data, UInt<64>(0h0)
connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0)
connect _beatsBO_WIRE.bits.address, UInt<29>(0h0)
connect _beatsBO_WIRE.bits.source, UInt<8>(0h0)
connect _beatsBO_WIRE.bits.size, UInt<4>(0h0)
connect _beatsBO_WIRE.bits.param, UInt<2>(0h0)
connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0)
connect _beatsBO_WIRE.valid, UInt<1>(0h0)
connect _beatsBO_WIRE.ready, UInt<1>(0h0)
wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits
connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid
connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready
node _beatsBO_decode_T = dshl(UInt<12>(0hfff), _beatsBO_WIRE_1.bits.size)
node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0)
node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1)
node beatsBO_decode = shr(_beatsBO_decode_T_2, 3)
node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2)
node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0))
node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0))
wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.data, UInt<64>(0h0)
connect _beatsCI_WIRE.bits.address, UInt<29>(0h0)
connect _beatsCI_WIRE.bits.source, UInt<8>(0h0)
connect _beatsCI_WIRE.bits.size, UInt<4>(0h0)
connect _beatsCI_WIRE.bits.param, UInt<3>(0h0)
connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0)
connect _beatsCI_WIRE.valid, UInt<1>(0h0)
connect _beatsCI_WIRE.ready, UInt<1>(0h0)
wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits
connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid
connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready
node _beatsCI_decode_T = dshl(UInt<12>(0hfff), _beatsCI_WIRE_1.bits.size)
node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0)
node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1)
node beatsCI_decode = shr(_beatsCI_decode_T_2, 3)
node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0)
node beatsCI_0 = mux(beatsCI_opdata, beatsCI_decode, UInt<1>(0h0))
wire _beatsCI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _beatsCI_WIRE_2.bits.data, UInt<64>(0h0)
connect _beatsCI_WIRE_2.bits.address, UInt<29>(0h0)
connect _beatsCI_WIRE_2.bits.source, UInt<8>(0h0)
connect _beatsCI_WIRE_2.bits.size, UInt<4>(0h0)
connect _beatsCI_WIRE_2.bits.param, UInt<3>(0h0)
connect _beatsCI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _beatsCI_WIRE_2.valid, UInt<1>(0h0)
connect _beatsCI_WIRE_2.ready, UInt<1>(0h0)
wire _beatsCI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_3.bits, _beatsCI_WIRE_2.bits
connect _beatsCI_WIRE_3.valid, _beatsCI_WIRE_2.valid
connect _beatsCI_WIRE_3.ready, _beatsCI_WIRE_2.ready
node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), _beatsCI_WIRE_3.bits.size)
node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0)
node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4)
node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 3)
node beatsCI_opdata_1 = bits(_beatsCI_WIRE_3.bits.opcode, 0, 0)
node beatsCI_1 = mux(UInt<1>(0h0), beatsCI_decode_1, UInt<1>(0h0))
node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size)
node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0)
node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1)
node beatsDO_decode = shr(_beatsDO_decode_T_2, 3)
node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0)
node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0))
wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0)
connect _beatsEI_WIRE.valid, UInt<1>(0h0)
connect _beatsEI_WIRE.ready, UInt<1>(0h0)
wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits
connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid
connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready
wire _beatsEI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_2.bits.sink, UInt<1>(0h0)
connect _beatsEI_WIRE_2.valid, UInt<1>(0h0)
connect _beatsEI_WIRE_2.ready, UInt<1>(0h0)
wire _beatsEI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_3.bits, _beatsEI_WIRE_2.bits
connect _beatsEI_WIRE_3.valid, _beatsEI_WIRE_2.valid
connect _beatsEI_WIRE_3.ready, _beatsEI_WIRE_2.ready
wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsAOI_filtered[0].bits, in[0].a.bits
node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h1))
node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T)
connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1
connect in[0].a.ready, portsAOI_filtered[0].ready
wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsAOI_filtered_1[0].bits, in[1].a.bits
node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h1))
node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2)
connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3
connect in[1].a.ready, portsAOI_filtered_1[0].ready
wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0)
connect _portsBIO_WIRE.bits.data, UInt<64>(0h0)
connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0)
connect _portsBIO_WIRE.bits.address, UInt<29>(0h0)
connect _portsBIO_WIRE.bits.source, UInt<8>(0h0)
connect _portsBIO_WIRE.bits.size, UInt<4>(0h0)
connect _portsBIO_WIRE.bits.param, UInt<2>(0h0)
connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0)
connect _portsBIO_WIRE.valid, UInt<1>(0h0)
connect _portsBIO_WIRE.ready, UInt<1>(0h0)
wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits
connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid
connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready
wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits
node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0))
node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T)
connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1
connect portsBIO_filtered[1].bits, _portsBIO_WIRE_1.bits
node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0))
node _portsBIO_filtered_1_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_1_valid_T)
connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1
node _portsBIO_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0))
node _portsBIO_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0))
node _portsBIO_T_2 = or(_portsBIO_T, _portsBIO_T_1)
wire _portsBIO_WIRE_2 : UInt<1>
connect _portsBIO_WIRE_2, _portsBIO_T_2
connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE_2
wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.data, UInt<64>(0h0)
connect _portsCOI_WIRE.bits.address, UInt<29>(0h0)
connect _portsCOI_WIRE.bits.source, UInt<8>(0h0)
connect _portsCOI_WIRE.bits.size, UInt<4>(0h0)
connect _portsCOI_WIRE.bits.param, UInt<3>(0h0)
connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0)
connect _portsCOI_WIRE.valid, UInt<1>(0h0)
connect _portsCOI_WIRE.ready, UInt<1>(0h0)
wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits
connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid
connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready
wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits
node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h1))
node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T)
connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1
connect _portsCOI_WIRE_1.ready, portsCOI_filtered[0].ready
wire _portsCOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _portsCOI_WIRE_2.bits.data, UInt<64>(0h0)
connect _portsCOI_WIRE_2.bits.address, UInt<29>(0h0)
connect _portsCOI_WIRE_2.bits.source, UInt<8>(0h0)
connect _portsCOI_WIRE_2.bits.size, UInt<4>(0h0)
connect _portsCOI_WIRE_2.bits.param, UInt<3>(0h0)
connect _portsCOI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _portsCOI_WIRE_2.valid, UInt<1>(0h0)
connect _portsCOI_WIRE_2.ready, UInt<1>(0h0)
wire _portsCOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_3.bits, _portsCOI_WIRE_2.bits
connect _portsCOI_WIRE_3.valid, _portsCOI_WIRE_2.valid
connect _portsCOI_WIRE_3.ready, _portsCOI_WIRE_2.ready
wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsCOI_filtered_1[0].bits, _portsCOI_WIRE_3.bits
node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h1))
node _portsCOI_filtered_0_valid_T_3 = and(_portsCOI_WIRE_3.valid, _portsCOI_filtered_0_valid_T_2)
connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3
connect _portsCOI_WIRE_3.ready, portsCOI_filtered_1[0].ready
wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[0].bits.data, out[0].d.bits.data
connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[0].bits.source, out[0].d.bits.source
connect portsDIO_filtered[0].bits.size, out[0].d.bits.size
connect portsDIO_filtered[0].bits.param, out[0].d.bits.param
connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0))
node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T)
connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1
connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[1].bits.data, out[0].d.bits.data
connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[1].bits.source, out[0].d.bits.source
connect portsDIO_filtered[1].bits.size, out[0].d.bits.size
connect portsDIO_filtered[1].bits.param, out[0].d.bits.param
connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0))
node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T)
connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1
node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_2 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1)
wire _portsDIO_out_0_d_ready_WIRE : UInt<1>
connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_2
connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE
wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0)
connect _portsEOI_WIRE.valid, UInt<1>(0h0)
connect _portsEOI_WIRE.ready, UInt<1>(0h0)
wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits
connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid
connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready
wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1]
connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits
node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h1))
node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T)
connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1
connect _portsEOI_WIRE_1.ready, portsEOI_filtered[0].ready
wire _portsEOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_2.bits.sink, UInt<1>(0h0)
connect _portsEOI_WIRE_2.valid, UInt<1>(0h0)
connect _portsEOI_WIRE_2.ready, UInt<1>(0h0)
wire _portsEOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_3.bits, _portsEOI_WIRE_2.bits
connect _portsEOI_WIRE_3.valid, _portsEOI_WIRE_2.valid
connect _portsEOI_WIRE_3.ready, _portsEOI_WIRE_2.ready
wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1]
connect portsEOI_filtered_1[0].bits, _portsEOI_WIRE_3.bits
node _portsEOI_filtered_0_valid_T_2 = or(UInt<1>(0h0), UInt<1>(0h1))
node _portsEOI_filtered_0_valid_T_3 = and(_portsEOI_WIRE_3.valid, _portsEOI_filtered_0_valid_T_2)
connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3
connect _portsEOI_WIRE_3.ready, portsEOI_filtered_1[0].ready
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, out[0].a.ready)
node _readys_T = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid)
node readys_valid = bits(_readys_T, 1, 0)
node _readys_T_1 = eq(readys_valid, _readys_T)
node _readys_T_2 = asUInt(reset)
node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0))
when _readys_T_3 :
node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0))
when _readys_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf
assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert
regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T = not(readys_mask)
node _readys_filter_T_1 = and(readys_valid, _readys_filter_T)
node readys_filter = cat(_readys_filter_T_1, readys_valid)
node _readys_unready_T = shr(readys_filter, 1)
node _readys_unready_T_1 = or(readys_filter, _readys_unready_T)
node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0)
node _readys_unready_T_3 = shr(_readys_unready_T_2, 1)
node _readys_unready_T_4 = shl(readys_mask, 2)
node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4)
node _readys_readys_T = shr(readys_unready, 2)
node _readys_readys_T_1 = bits(readys_unready, 1, 0)
node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1)
node readys_readys = not(_readys_readys_T_2)
node _readys_T_5 = orr(readys_valid)
node _readys_T_6 = and(latch, _readys_T_5)
when _readys_T_6 :
node _readys_mask_T = and(readys_readys, readys_valid)
node _readys_mask_T_1 = shl(_readys_mask_T, 1)
node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0)
node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2)
node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0)
connect readys_mask, _readys_mask_T_4
node _readys_T_7 = bits(readys_readys, 1, 0)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
wire readys : UInt<1>[2]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
node _winner_T = and(readys[0], portsAOI_filtered[0].valid)
node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid)
wire winner : UInt<1>[2]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node _prefixOR_T = or(prefixOR_1, winner[1])
node _T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_1 = eq(winner[0], UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = eq(prefixOR_1, UInt<1>(0h0))
node _T_4 = eq(winner[1], UInt<1>(0h0))
node _T_5 = or(_T_3, _T_4)
node _T_6 = and(_T_2, _T_5)
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf
assert(clock, _T_6, UInt<1>(0h1), "") : assert
node _T_10 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _T_11 = eq(_T_10, UInt<1>(0h0))
node _T_12 = or(winner[0], winner[1])
node _T_13 = or(_T_11, _T_12)
node _T_14 = asUInt(reset)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
node _T_16 = eq(_T_13, UInt<1>(0h0))
when _T_16 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1
assert(clock, _T_13, UInt<1>(0h1), "") : assert_1
node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0))
node initBeats = or(maskedBeats_0, maskedBeats_1)
node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[2]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
regreset state : UInt<1>[2], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _filtered_0_ready_T = and(out[0].a.ready, allowed[0])
connect portsAOI_filtered[0].ready, _filtered_0_ready_T
node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1])
connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1
node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _out_0_a_valid_T_1 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_2 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_1, _out_0_a_valid_T_2)
wire _out_0_a_valid_WIRE : UInt<1>
connect _out_0_a_valid_WIRE, _out_0_a_valid_T_3
node _out_0_a_valid_T_4 = mux(idle, _out_0_a_valid_T, _out_0_a_valid_WIRE)
connect out[0].a.valid, _out_0_a_valid_T_4
wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_2 = or(_out_0_a_bits_T, _out_0_a_bits_T_1)
wire _out_0_a_bits_WIRE_1 : UInt<1>
connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_2
connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1
node _out_0_a_bits_T_3 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_4 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_5 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_4)
wire _out_0_a_bits_WIRE_2 : UInt<64>
connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_5
connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2
node _out_0_a_bits_T_6 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_7 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_7)
wire _out_0_a_bits_WIRE_3 : UInt<8>
connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_8
connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3
wire _out_0_a_bits_WIRE_4 : { }
connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4
wire _out_0_a_bits_WIRE_5 : { }
connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5
node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_11 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10)
wire _out_0_a_bits_WIRE_6 : UInt<29>
connect _out_0_a_bits_WIRE_6, _out_0_a_bits_T_11
connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_6
node _out_0_a_bits_T_12 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_13 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_12, _out_0_a_bits_T_13)
wire _out_0_a_bits_WIRE_7 : UInt<8>
connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_14
connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_7
node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16)
wire _out_0_a_bits_WIRE_8 : UInt<4>
connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_17
connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_8
node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_20 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19)
wire _out_0_a_bits_WIRE_9 : UInt<3>
connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_20
connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_9
node _out_0_a_bits_T_21 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_22 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_22)
wire _out_0_a_bits_WIRE_10 : UInt<3>
connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_23
connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_10
connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt
connect out[0].a.bits.data, _out_0_a_bits_WIRE.data
connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask
connect out[0].a.bits.address, _out_0_a_bits_WIRE.address
connect out[0].a.bits.source, _out_0_a_bits_WIRE.source
connect out[0].a.bits.size, _out_0_a_bits_WIRE.size
connect out[0].a.bits.param, _out_0_a_bits_WIRE.param
connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode
wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_72.bits.corrupt, UInt<1>(0h0)
connect _WIRE_72.bits.data, UInt<64>(0h0)
connect _WIRE_72.bits.address, UInt<29>(0h0)
connect _WIRE_72.bits.source, UInt<8>(0h0)
connect _WIRE_72.bits.size, UInt<4>(0h0)
connect _WIRE_72.bits.param, UInt<3>(0h0)
connect _WIRE_72.bits.opcode, UInt<3>(0h0)
connect _WIRE_72.valid, UInt<1>(0h0)
connect _WIRE_72.ready, UInt<1>(0h0)
wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_73.bits, _WIRE_72.bits
connect _WIRE_73.valid, _WIRE_72.valid
connect _WIRE_73.ready, _WIRE_72.ready
invalidate _WIRE_73.bits.corrupt
invalidate _WIRE_73.bits.data
invalidate _WIRE_73.bits.address
invalidate _WIRE_73.bits.source
invalidate _WIRE_73.bits.size
invalidate _WIRE_73.bits.param
invalidate _WIRE_73.bits.opcode
wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_74.bits.sink, UInt<1>(0h0)
connect _WIRE_74.valid, UInt<1>(0h0)
connect _WIRE_74.ready, UInt<1>(0h0)
wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_75.bits, _WIRE_74.bits
connect _WIRE_75.valid, _WIRE_74.valid
connect _WIRE_75.ready, _WIRE_74.ready
invalidate _WIRE_75.bits.sink
connect portsCOI_filtered[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_1[0].ready, UInt<1>(0h0)
connect portsEOI_filtered[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_1[0].ready, UInt<1>(0h0)
wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_76.bits.corrupt, UInt<1>(0h0)
connect _WIRE_76.bits.data, UInt<64>(0h0)
connect _WIRE_76.bits.mask, UInt<8>(0h0)
connect _WIRE_76.bits.address, UInt<29>(0h0)
connect _WIRE_76.bits.source, UInt<8>(0h0)
connect _WIRE_76.bits.size, UInt<4>(0h0)
connect _WIRE_76.bits.param, UInt<2>(0h0)
connect _WIRE_76.bits.opcode, UInt<3>(0h0)
connect _WIRE_76.valid, UInt<1>(0h0)
connect _WIRE_76.ready, UInt<1>(0h0)
wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_77.bits, _WIRE_76.bits
connect _WIRE_77.valid, _WIRE_76.valid
connect _WIRE_77.ready, _WIRE_76.ready
invalidate _WIRE_77.bits.corrupt
invalidate _WIRE_77.bits.data
invalidate _WIRE_77.bits.mask
invalidate _WIRE_77.bits.address
invalidate _WIRE_77.bits.source
invalidate _WIRE_77.bits.size
invalidate _WIRE_77.bits.param
invalidate _WIRE_77.bits.opcode
connect in[0].d, portsDIO_filtered[0]
connect portsBIO_filtered[0].ready, UInt<1>(0h0)
wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_78.bits.corrupt, UInt<1>(0h0)
connect _WIRE_78.bits.data, UInt<64>(0h0)
connect _WIRE_78.bits.mask, UInt<8>(0h0)
connect _WIRE_78.bits.address, UInt<29>(0h0)
connect _WIRE_78.bits.source, UInt<8>(0h0)
connect _WIRE_78.bits.size, UInt<4>(0h0)
connect _WIRE_78.bits.param, UInt<2>(0h0)
connect _WIRE_78.bits.opcode, UInt<3>(0h0)
connect _WIRE_78.valid, UInt<1>(0h0)
connect _WIRE_78.ready, UInt<1>(0h0)
wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_79.bits, _WIRE_78.bits
connect _WIRE_79.valid, _WIRE_78.valid
connect _WIRE_79.ready, _WIRE_78.ready
invalidate _WIRE_79.bits.corrupt
invalidate _WIRE_79.bits.data
invalidate _WIRE_79.bits.mask
invalidate _WIRE_79.bits.address
invalidate _WIRE_79.bits.source
invalidate _WIRE_79.bits.size
invalidate _WIRE_79.bits.param
invalidate _WIRE_79.bits.opcode
connect in[1].d, portsDIO_filtered[1]
connect portsBIO_filtered[1].ready, UInt<1>(0h0)
extmodule plusarg_reader_90 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_91 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLXbar_cbus_in_i2_o1_a29d64s8k1z4u( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset, // @[Xbar.scala:74:9]
output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire requestDOI_0_1 = auto_anon_out_d_bits_source == 8'h80; // @[Parameters.scala:46:9]
wire portsDIO_filtered_0_valid = auto_anon_out_d_valid & ~(auto_anon_out_d_bits_source[7]); // @[Xbar.scala:355:40]
wire portsDIO_filtered_1_valid = auto_anon_out_d_valid & requestDOI_0_1; // @[Xbar.scala:355:40]
reg [8:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire [1:0] readys_valid = {auto_anon_in_1_a_valid, auto_anon_in_0_a_valid}; // @[Arbiter.scala:68:51]
reg [1:0] readys_mask; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_1 = readys_valid & ~readys_mask; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51]
wire [1:0] readys_readys = ~({readys_mask[1], _readys_filter_T_1[1] | readys_mask[0]} & ({_readys_filter_T_1[0], auto_anon_in_1_a_valid} | _readys_filter_T_1)); // @[package.scala:262:43]
wire winner_0 = readys_readys[0] & auto_anon_in_0_a_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire winner_1 = readys_readys[1] & auto_anon_in_1_a_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire _out_0_a_valid_T = auto_anon_in_0_a_valid | auto_anon_in_1_a_valid; // @[Arbiter.scala:79:31] |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a29d64s7k1z3u :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_10
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a29d64s7k1z3u
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a29d64s7k1z3u
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<29>(0h0)
connect _WIRE.bits.source, UInt<7>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<29>(0h0)
connect _WIRE_2.bits.source, UInt<7>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<29>(0h0)
connect _WIRE_8.bits.source, UInt<7>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_10.bits.sink, UInt<1>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0)
extmodule plusarg_reader_48 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_49 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLBuffer_a29d64s7k1z3u( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [6:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21]
TLMonitor_10 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21]
.io_in_a_valid (auto_in_a_valid),
.io_in_a_bits_opcode (auto_in_a_bits_opcode),
.io_in_a_bits_param (auto_in_a_bits_param),
.io_in_a_bits_size (auto_in_a_bits_size),
.io_in_a_bits_source (auto_in_a_bits_source),
.io_in_a_bits_address (auto_in_a_bits_address),
.io_in_a_bits_mask (auto_in_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_a_bits_corrupt),
.io_in_d_ready (auto_in_d_ready),
.io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21]
.io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21]
.io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21]
.io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21]
.io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21]
.io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21]
.io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21]
.io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a29d64s7k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (_nodeOut_a_q_io_enq_ready),
.io_enq_valid (auto_in_a_valid),
.io_enq_bits_opcode (auto_in_a_bits_opcode),
.io_enq_bits_param (auto_in_a_bits_param),
.io_enq_bits_size (auto_in_a_bits_size),
.io_enq_bits_source (auto_in_a_bits_source),
.io_enq_bits_address (auto_in_a_bits_address),
.io_enq_bits_mask (auto_in_a_bits_mask),
.io_enq_bits_data (auto_in_a_bits_data),
.io_enq_bits_corrupt (auto_in_a_bits_corrupt),
.io_deq_ready (auto_out_a_ready),
.io_deq_valid (auto_out_a_valid),
.io_deq_bits_opcode (auto_out_a_bits_opcode),
.io_deq_bits_param (auto_out_a_bits_param),
.io_deq_bits_size (auto_out_a_bits_size),
.io_deq_bits_source (auto_out_a_bits_source),
.io_deq_bits_address (auto_out_a_bits_address),
.io_deq_bits_mask (auto_out_a_bits_mask),
.io_deq_bits_data (auto_out_a_bits_data),
.io_deq_bits_corrupt (auto_out_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a29d64s7k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (auto_out_d_ready),
.io_enq_valid (auto_out_d_valid),
.io_enq_bits_opcode (auto_out_d_bits_opcode),
.io_enq_bits_param (2'h0), // @[Decoupled.scala:362:21]
.io_enq_bits_size (auto_out_d_bits_size),
.io_enq_bits_source (auto_out_d_bits_source),
.io_enq_bits_sink (1'h0), // @[Decoupled.scala:362:21]
.io_enq_bits_denied (1'h0), // @[Decoupled.scala:362:21]
.io_enq_bits_data (auto_out_d_bits_data),
.io_enq_bits_corrupt (1'h0), // @[Decoupled.scala:362:21]
.io_deq_ready (auto_in_d_ready),
.io_deq_valid (_nodeIn_d_q_io_deq_valid),
.io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode),
.io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param),
.io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size),
.io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source),
.io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink),
.io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied),
.io_deq_bits_data (auto_in_d_bits_data),
.io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21]
assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_42 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>}
node _reg_T = asAsyncReset(reset)
regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0)
when io.en :
connect reg, io.d
connect io.q, reg | module AsyncResetRegVec_w1_i0_42( // @[AsyncResetReg.scala:56:7]
input clock, // @[AsyncResetReg.scala:56:7]
input reset, // @[AsyncResetReg.scala:56:7]
input io_d, // @[AsyncResetReg.scala:59:14]
output io_q // @[AsyncResetReg.scala:59:14]
);
wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7]
wire _reg_T = reset; // @[AsyncResetReg.scala:61:29]
wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14]
wire io_q_0; // @[AsyncResetReg.scala:56:7]
reg reg_0; // @[AsyncResetReg.scala:61:50]
assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50]
always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29]
if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29]
reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50]
else // @[AsyncResetReg.scala:56:7]
reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50]
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_137 :
input clock : Clock
input reset : Reset
output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}}
regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff)
reg value_reg : { symbol : UInt<10>}, clock
connect io.output_prev.key, key_reg
connect io.output_prev.value, value_reg
connect io.output_nxt.key, key_reg
connect io.output_nxt.value, value_reg
connect io.cur_output_keyval.key, key_reg
connect io.cur_output_keyval.value, value_reg
when io.cmd.valid :
node _T = eq(UInt<1>(0h0), io.cmd.bits)
when _T :
connect key_reg, io.input_nxt.key
connect value_reg, io.input_nxt.value
else :
node _T_1 = eq(UInt<1>(0h1), io.cmd.bits)
when _T_1 :
when io.insert_here :
connect key_reg, io.cur_input_keyval.key
connect value_reg, io.cur_input_keyval.value
else :
node _T_2 = geq(key_reg, io.cur_input_keyval.key)
when _T_2 :
connect key_reg, io.input_prev.key
connect value_reg, io.input_prev.value
else :
skip | module PriorityQueueStage_137( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_312 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_312( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLUART :
input clock : Clock
input reset : Reset
output auto : { int_xing_out : { sync : UInt<1>[1]}, flip control_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, io_out : { txd : UInt<1>, flip rxd : UInt<1>}}
inst buffer of TLBuffer_a29d64s11k1z2u
connect buffer.clock, clock
connect buffer.reset, reset
inst intsource of IntSyncCrossingSource_n1x1_4
connect intsource.clock, clock
connect intsource.reset, reset
wire ioNodeOut : { txd : UInt<1>, flip rxd : UInt<1>}
invalidate ioNodeOut.rxd
invalidate ioNodeOut.txd
wire intnodeOut : UInt<1>[1]
invalidate intnodeOut[0]
wire controlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate controlNodeIn.d.bits.corrupt
invalidate controlNodeIn.d.bits.data
invalidate controlNodeIn.d.bits.denied
invalidate controlNodeIn.d.bits.sink
invalidate controlNodeIn.d.bits.source
invalidate controlNodeIn.d.bits.size
invalidate controlNodeIn.d.bits.param
invalidate controlNodeIn.d.bits.opcode
invalidate controlNodeIn.d.valid
invalidate controlNodeIn.d.ready
invalidate controlNodeIn.a.bits.corrupt
invalidate controlNodeIn.a.bits.data
invalidate controlNodeIn.a.bits.mask
invalidate controlNodeIn.a.bits.address
invalidate controlNodeIn.a.bits.source
invalidate controlNodeIn.a.bits.size
invalidate controlNodeIn.a.bits.param
invalidate controlNodeIn.a.bits.opcode
invalidate controlNodeIn.a.valid
invalidate controlNodeIn.a.ready
inst monitor of TLMonitor_40
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, controlNodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, controlNodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, controlNodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, controlNodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, controlNodeIn.d.bits.source
connect monitor.io.in.d.bits.size, controlNodeIn.d.bits.size
connect monitor.io.in.d.bits.param, controlNodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, controlNodeIn.d.bits.opcode
connect monitor.io.in.d.valid, controlNodeIn.d.valid
connect monitor.io.in.d.ready, controlNodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, controlNodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, controlNodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, controlNodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, controlNodeIn.a.bits.address
connect monitor.io.in.a.bits.source, controlNodeIn.a.bits.source
connect monitor.io.in.a.bits.size, controlNodeIn.a.bits.size
connect monitor.io.in.a.bits.param, controlNodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, controlNodeIn.a.bits.opcode
connect monitor.io.in.a.valid, controlNodeIn.a.valid
connect monitor.io.in.a.ready, controlNodeIn.a.ready
wire controlXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate controlXingOut.d.bits.corrupt
invalidate controlXingOut.d.bits.data
invalidate controlXingOut.d.bits.denied
invalidate controlXingOut.d.bits.sink
invalidate controlXingOut.d.bits.source
invalidate controlXingOut.d.bits.size
invalidate controlXingOut.d.bits.param
invalidate controlXingOut.d.bits.opcode
invalidate controlXingOut.d.valid
invalidate controlXingOut.d.ready
invalidate controlXingOut.a.bits.corrupt
invalidate controlXingOut.a.bits.data
invalidate controlXingOut.a.bits.mask
invalidate controlXingOut.a.bits.address
invalidate controlXingOut.a.bits.source
invalidate controlXingOut.a.bits.size
invalidate controlXingOut.a.bits.param
invalidate controlXingOut.a.bits.opcode
invalidate controlXingOut.a.valid
invalidate controlXingOut.a.ready
wire controlXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate controlXingIn.d.bits.corrupt
invalidate controlXingIn.d.bits.data
invalidate controlXingIn.d.bits.denied
invalidate controlXingIn.d.bits.sink
invalidate controlXingIn.d.bits.source
invalidate controlXingIn.d.bits.size
invalidate controlXingIn.d.bits.param
invalidate controlXingIn.d.bits.opcode
invalidate controlXingIn.d.valid
invalidate controlXingIn.d.ready
invalidate controlXingIn.a.bits.corrupt
invalidate controlXingIn.a.bits.data
invalidate controlXingIn.a.bits.mask
invalidate controlXingIn.a.bits.address
invalidate controlXingIn.a.bits.source
invalidate controlXingIn.a.bits.size
invalidate controlXingIn.a.bits.param
invalidate controlXingIn.a.bits.opcode
invalidate controlXingIn.a.valid
invalidate controlXingIn.a.ready
connect controlXingOut, controlXingIn
wire intXingOut : { sync : UInt<1>[1]}
invalidate intXingOut.sync[0]
wire intXingIn : { sync : UInt<1>[1]}
invalidate intXingIn.sync[0]
connect intXingOut, intXingIn
connect intsource.auto.in[0], intnodeOut[0]
connect buffer.auto.out.d, controlNodeIn.d
connect controlNodeIn.a.bits, buffer.auto.out.a.bits
connect controlNodeIn.a.valid, buffer.auto.out.a.valid
connect buffer.auto.out.a.ready, controlNodeIn.a.ready
connect buffer.auto.in, controlXingOut
connect intXingIn, intsource.auto.out
connect auto.io_out, ioNodeOut
connect controlXingIn, auto.control_xing_in
connect auto.int_xing_out, intXingOut
inst txm of UARTTx
connect txm.clock, clock
connect txm.reset, reset
inst txq of Queue8_UInt8
connect txq.clock, clock
connect txq.reset, reset
inst rxm of UARTRx
connect rxm.clock, clock
connect rxm.reset, reset
inst rxq of Queue8_UInt8_1
connect rxq.clock, clock
connect rxq.reset, reset
regreset div : UInt<16>, clock, reset, UInt<16>(0h10f4)
regreset txen : UInt<1>, clock, reset, UInt<1>(0h0)
regreset rxen : UInt<1>, clock, reset, UInt<1>(0h0)
regreset enwire4 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset invpol : UInt<1>, clock, reset, UInt<1>(0h0)
regreset enparity : UInt<1>, clock, reset, UInt<1>(0h0)
regreset parity : UInt<1>, clock, reset, UInt<1>(0h0)
regreset errorparity : UInt<1>, clock, reset, UInt<1>(0h0)
regreset errie : UInt<1>, clock, reset, UInt<1>(0h0)
regreset txwm : UInt<4>, clock, reset, UInt<4>(0h0)
regreset rxwm : UInt<4>, clock, reset, UInt<4>(0h0)
regreset nstop : UInt<1>, clock, reset, UInt<1>(0h0)
regreset data8or9 : UInt<1>, clock, reset, UInt<1>(0h1)
connect txm.io.en, txen
connect txm.io.in, txq.io.deq
connect txm.io.div, div
connect txm.io.nstop, nstop
connect ioNodeOut.txd, txm.io.out
connect rxm.io.en, rxen
connect rxm.io.in, ioNodeOut.rxd
connect rxq.io.enq.valid, rxm.io.out.valid
connect rxq.io.enq.bits, rxm.io.out.bits
connect rxm.io.div, div
node _tx_busy_T = orr(txq.io.count)
node _tx_busy_T_1 = or(txm.io.tx_busy, _tx_busy_T)
node tx_busy = and(_tx_busy_T_1, txen)
wire _ie_WIRE : { rxwm : UInt<1>, txwm : UInt<1>}
connect _ie_WIRE.txwm, UInt<1>(0h0)
connect _ie_WIRE.rxwm, UInt<1>(0h0)
regreset ie : { rxwm : UInt<1>, txwm : UInt<1>}, clock, reset, _ie_WIRE
wire ip : { rxwm : UInt<1>, txwm : UInt<1>}
node _ip_txwm_T = lt(txq.io.count, txwm)
connect ip.txwm, _ip_txwm_T
node _ip_rxwm_T = gt(rxq.io.count, rxwm)
connect ip.rxwm, _ip_rxwm_T
node _intnodeOut_0_T = and(ip.txwm, ie.txwm)
node _intnodeOut_0_T_1 = and(ip.rxwm, ie.rxwm)
node _intnodeOut_0_T_2 = or(_intnodeOut_0_T, _intnodeOut_0_T_1)
connect intnodeOut[0], _intnodeOut_0_T_2
wire quash : UInt<1>
node _T = eq(txq.io.enq.ready, UInt<1>(0h0))
node _T_1 = eq(rxq.io.deq.valid, UInt<1>(0h0))
wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
node _in_bits_read_T = eq(controlNodeIn.a.bits.opcode, UInt<3>(0h4))
connect in.bits.read, _in_bits_read_T
node _in_bits_index_T = shr(controlNodeIn.a.bits.address, 3)
connect in.bits.index, _in_bits_index_T
connect in.bits.data, controlNodeIn.a.bits.data
connect in.bits.mask, controlNodeIn.a.bits.mask
connect in.bits.extra.tlrr_extra.source, controlNodeIn.a.bits.source
connect in.bits.extra.tlrr_extra.size, controlNodeIn.a.bits.size
wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
connect out_front.bits, in.bits
node out_maskMatch = not(UInt<9>(0h3))
node out_findex = and(out_front.bits.index, out_maskMatch)
node out_bindex = and(out_front.bits.index, out_maskMatch)
node _out_T = eq(out_findex, UInt<9>(0h0))
node _out_T_1 = eq(out_bindex, UInt<9>(0h0))
node _out_T_2 = eq(out_findex, UInt<9>(0h0))
node _out_T_3 = eq(out_bindex, UInt<9>(0h0))
node _out_T_4 = eq(out_findex, UInt<9>(0h0))
node _out_T_5 = eq(out_bindex, UInt<9>(0h0))
node _out_T_6 = eq(out_findex, UInt<9>(0h0))
node _out_T_7 = eq(out_bindex, UInt<9>(0h0))
wire out_rivalid : UInt<1>[16]
wire out_wivalid : UInt<1>[16]
wire out_roready : UInt<1>[16]
wire out_woready : UInt<1>[16]
node _out_frontMask_T = bits(out_front.bits.mask, 0, 0)
node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1)
node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2)
node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3)
node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4)
node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5)
node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6)
node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7)
node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8)
node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10)
node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo)
node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12)
node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14)
node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo)
node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo)
node _out_backMask_T = bits(out_front.bits.mask, 0, 0)
node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1)
node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2)
node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3)
node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4)
node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5)
node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6)
node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7)
node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8)
node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10)
node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo)
node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12)
node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14)
node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo)
node out_backMask = cat(out_backMask_hi, out_backMask_lo)
node _out_rimask_T = bits(out_frontMask, 7, 0)
node out_rimask = orr(_out_rimask_T)
node _out_wimask_T = bits(out_frontMask, 7, 0)
node out_wimask = andr(_out_wimask_T)
node _out_romask_T = bits(out_backMask, 7, 0)
node out_romask = orr(_out_romask_T)
node _out_womask_T = bits(out_backMask, 7, 0)
node out_womask = andr(_out_womask_T)
node out_f_rivalid = and(out_rivalid[0], out_rimask)
node out_f_roready = and(out_roready[0], out_romask)
node out_f_wivalid = and(out_wivalid[0], out_wimask)
node out_f_woready = and(out_woready[0], out_womask)
node _out_T_8 = bits(out_front.bits.data, 7, 0)
node _out_txq_io_enq_valid_T = eq(quash, UInt<1>(0h0))
node _out_txq_io_enq_valid_T_1 = and(out_f_woready, _out_txq_io_enq_valid_T)
connect txq.io.enq.valid, _out_txq_io_enq_valid_T_1
connect txq.io.enq.bits, _out_T_8
node _out_T_9 = and(out_f_wivalid, UInt<1>(0h1))
node _out_T_10 = and(UInt<1>(0h1), out_f_woready)
node _out_T_11 = eq(out_rimask, UInt<1>(0h0))
node _out_T_12 = eq(out_wimask, UInt<1>(0h0))
node _out_T_13 = eq(out_romask, UInt<1>(0h0))
node _out_T_14 = eq(out_womask, UInt<1>(0h0))
node _out_T_15 = or(UInt<1>(0h0), UInt<8>(0h0))
node _out_T_16 = bits(_out_T_15, 7, 0)
node _out_rimask_T_1 = bits(out_frontMask, 30, 8)
node out_rimask_1 = orr(_out_rimask_T_1)
node _out_wimask_T_1 = bits(out_frontMask, 30, 8)
node out_wimask_1 = andr(_out_wimask_T_1)
node _out_romask_T_1 = bits(out_backMask, 30, 8)
node out_romask_1 = orr(_out_romask_T_1)
node _out_womask_T_1 = bits(out_backMask, 30, 8)
node out_womask_1 = andr(_out_womask_T_1)
node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1)
node out_f_roready_1 = and(out_roready[1], out_romask_1)
node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1)
node out_f_woready_1 = and(out_woready[1], out_womask_1)
node _out_T_17 = bits(out_front.bits.data, 30, 8)
node _out_T_18 = and(out_f_rivalid_1, UInt<1>(0h1))
node _out_T_19 = and(UInt<1>(0h1), out_f_roready_1)
node _out_T_20 = eq(out_rimask_1, UInt<1>(0h0))
node _out_T_21 = eq(out_wimask_1, UInt<1>(0h0))
node _out_T_22 = eq(out_romask_1, UInt<1>(0h0))
node _out_T_23 = eq(out_womask_1, UInt<1>(0h0))
node _out_prepend_T = or(_out_T_16, UInt<8>(0h0))
node out_prepend = cat(UInt<1>(0h0), _out_prepend_T)
node _out_T_24 = or(out_prepend, UInt<31>(0h0))
node _out_T_25 = bits(_out_T_24, 30, 0)
node _out_rimask_T_2 = bits(out_frontMask, 31, 31)
node out_rimask_2 = orr(_out_rimask_T_2)
node _out_wimask_T_2 = bits(out_frontMask, 31, 31)
node out_wimask_2 = andr(_out_wimask_T_2)
node _out_romask_T_2 = bits(out_backMask, 31, 31)
node out_romask_2 = orr(_out_romask_T_2)
node _out_womask_T_2 = bits(out_backMask, 31, 31)
node out_womask_2 = andr(_out_womask_T_2)
node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2)
node out_f_roready_2 = and(out_roready[2], out_romask_2)
node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2)
node out_f_woready_2 = and(out_woready[2], out_womask_2)
node _out_T_26 = bits(out_front.bits.data, 31, 31)
node _out_quash_T = bits(_out_T_26, 0, 0)
node _out_quash_T_1 = and(out_f_woready_2, _out_quash_T)
connect quash, _out_quash_T_1
node _out_T_27 = and(out_f_rivalid_2, UInt<1>(0h1))
node _out_T_28 = and(UInt<1>(0h1), out_f_roready_2)
node _out_T_29 = eq(out_rimask_2, UInt<1>(0h0))
node _out_T_30 = eq(out_wimask_2, UInt<1>(0h0))
node _out_T_31 = eq(out_romask_2, UInt<1>(0h0))
node _out_T_32 = eq(out_womask_2, UInt<1>(0h0))
node _out_prepend_T_1 = or(_out_T_25, UInt<31>(0h0))
node out_prepend_1 = cat(_T, _out_prepend_T_1)
node _out_T_33 = or(out_prepend_1, UInt<32>(0h0))
node _out_T_34 = bits(_out_T_33, 31, 0)
node _out_rimask_T_3 = bits(out_frontMask, 39, 32)
node out_rimask_3 = orr(_out_rimask_T_3)
node _out_wimask_T_3 = bits(out_frontMask, 39, 32)
node out_wimask_3 = andr(_out_wimask_T_3)
node _out_romask_T_3 = bits(out_backMask, 39, 32)
node out_romask_3 = orr(_out_romask_T_3)
node _out_womask_T_3 = bits(out_backMask, 39, 32)
node out_womask_3 = andr(_out_womask_T_3)
node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3)
node out_f_roready_3 = and(out_roready[3], out_romask_3)
node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3)
node out_f_woready_3 = and(out_woready[3], out_womask_3)
connect rxq.io.deq.ready, out_f_roready_3
node _out_T_35 = bits(out_front.bits.data, 39, 32)
node _out_T_36 = and(out_f_rivalid_3, UInt<1>(0h1))
node _out_T_37 = and(UInt<1>(0h1), out_f_roready_3)
node _out_T_38 = eq(out_rimask_3, UInt<1>(0h0))
node _out_T_39 = eq(out_wimask_3, UInt<1>(0h0))
node _out_T_40 = eq(out_romask_3, UInt<1>(0h0))
node _out_T_41 = eq(out_womask_3, UInt<1>(0h0))
node _out_prepend_T_2 = or(_out_T_34, UInt<32>(0h0))
node out_prepend_2 = cat(rxq.io.deq.bits, _out_prepend_T_2)
node _out_T_42 = or(out_prepend_2, UInt<40>(0h0))
node _out_T_43 = bits(_out_T_42, 39, 0)
node _out_rimask_T_4 = bits(out_frontMask, 62, 40)
node out_rimask_4 = orr(_out_rimask_T_4)
node _out_wimask_T_4 = bits(out_frontMask, 62, 40)
node out_wimask_4 = andr(_out_wimask_T_4)
node _out_romask_T_4 = bits(out_backMask, 62, 40)
node out_romask_4 = orr(_out_romask_T_4)
node _out_womask_T_4 = bits(out_backMask, 62, 40)
node out_womask_4 = andr(_out_womask_T_4)
node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4)
node out_f_roready_4 = and(out_roready[4], out_romask_4)
node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4)
node out_f_woready_4 = and(out_woready[4], out_womask_4)
node _out_T_44 = bits(out_front.bits.data, 62, 40)
node _out_T_45 = and(out_f_rivalid_4, UInt<1>(0h1))
node _out_T_46 = and(UInt<1>(0h1), out_f_roready_4)
node _out_T_47 = eq(out_rimask_4, UInt<1>(0h0))
node _out_T_48 = eq(out_wimask_4, UInt<1>(0h0))
node _out_T_49 = eq(out_romask_4, UInt<1>(0h0))
node _out_T_50 = eq(out_womask_4, UInt<1>(0h0))
node _out_prepend_T_3 = or(_out_T_43, UInt<40>(0h0))
node out_prepend_3 = cat(UInt<1>(0h0), _out_prepend_T_3)
node _out_T_51 = or(out_prepend_3, UInt<63>(0h0))
node _out_T_52 = bits(_out_T_51, 62, 0)
node _out_rimask_T_5 = bits(out_frontMask, 63, 63)
node out_rimask_5 = orr(_out_rimask_T_5)
node _out_wimask_T_5 = bits(out_frontMask, 63, 63)
node out_wimask_5 = andr(_out_wimask_T_5)
node _out_romask_T_5 = bits(out_backMask, 63, 63)
node out_romask_5 = orr(_out_romask_T_5)
node _out_womask_T_5 = bits(out_backMask, 63, 63)
node out_womask_5 = andr(_out_womask_T_5)
node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5)
node out_f_roready_5 = and(out_roready[5], out_romask_5)
node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5)
node out_f_woready_5 = and(out_woready[5], out_womask_5)
node _out_T_53 = bits(out_front.bits.data, 63, 63)
node _out_T_54 = and(out_f_rivalid_5, UInt<1>(0h1))
node _out_T_55 = and(UInt<1>(0h1), out_f_roready_5)
node _out_T_56 = eq(out_rimask_5, UInt<1>(0h0))
node _out_T_57 = eq(out_wimask_5, UInt<1>(0h0))
node _out_T_58 = eq(out_romask_5, UInt<1>(0h0))
node _out_T_59 = eq(out_womask_5, UInt<1>(0h0))
node _out_prepend_T_4 = or(_out_T_52, UInt<63>(0h0))
node out_prepend_4 = cat(_T_1, _out_prepend_T_4)
node _out_T_60 = or(out_prepend_4, UInt<64>(0h0))
node _out_T_61 = bits(_out_T_60, 63, 0)
node _out_rimask_T_6 = bits(out_frontMask, 0, 0)
node out_rimask_6 = orr(_out_rimask_T_6)
node _out_wimask_T_6 = bits(out_frontMask, 0, 0)
node out_wimask_6 = andr(_out_wimask_T_6)
node _out_romask_T_6 = bits(out_backMask, 0, 0)
node out_romask_6 = orr(_out_romask_T_6)
node _out_womask_T_6 = bits(out_backMask, 0, 0)
node out_womask_6 = andr(_out_womask_T_6)
node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6)
node out_f_roready_6 = and(out_roready[6], out_romask_6)
node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6)
node out_f_woready_6 = and(out_woready[6], out_womask_6)
node _out_T_62 = bits(out_front.bits.data, 0, 0)
when out_f_woready_6 :
connect txen, _out_T_62
node _out_T_63 = and(out_f_rivalid_6, UInt<1>(0h1))
node _out_T_64 = and(UInt<1>(0h1), out_f_roready_6)
node _out_T_65 = and(out_f_wivalid_6, UInt<1>(0h1))
node _out_T_66 = and(UInt<1>(0h1), out_f_woready_6)
node _out_T_67 = eq(out_rimask_6, UInt<1>(0h0))
node _out_T_68 = eq(out_wimask_6, UInt<1>(0h0))
node _out_T_69 = eq(out_romask_6, UInt<1>(0h0))
node _out_T_70 = eq(out_womask_6, UInt<1>(0h0))
node _out_T_71 = or(txen, UInt<1>(0h0))
node _out_T_72 = bits(_out_T_71, 0, 0)
node _out_rimask_T_7 = bits(out_frontMask, 1, 1)
node out_rimask_7 = orr(_out_rimask_T_7)
node _out_wimask_T_7 = bits(out_frontMask, 1, 1)
node out_wimask_7 = andr(_out_wimask_T_7)
node _out_romask_T_7 = bits(out_backMask, 1, 1)
node out_romask_7 = orr(_out_romask_T_7)
node _out_womask_T_7 = bits(out_backMask, 1, 1)
node out_womask_7 = andr(_out_womask_T_7)
node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7)
node out_f_roready_7 = and(out_roready[7], out_romask_7)
node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7)
node out_f_woready_7 = and(out_woready[7], out_womask_7)
node _out_T_73 = bits(out_front.bits.data, 1, 1)
when out_f_woready_7 :
connect nstop, _out_T_73
node _out_T_74 = and(out_f_rivalid_7, UInt<1>(0h1))
node _out_T_75 = and(UInt<1>(0h1), out_f_roready_7)
node _out_T_76 = and(out_f_wivalid_7, UInt<1>(0h1))
node _out_T_77 = and(UInt<1>(0h1), out_f_woready_7)
node _out_T_78 = eq(out_rimask_7, UInt<1>(0h0))
node _out_T_79 = eq(out_wimask_7, UInt<1>(0h0))
node _out_T_80 = eq(out_romask_7, UInt<1>(0h0))
node _out_T_81 = eq(out_womask_7, UInt<1>(0h0))
node _out_prepend_T_5 = or(_out_T_72, UInt<1>(0h0))
node out_prepend_5 = cat(nstop, _out_prepend_T_5)
node _out_T_82 = or(out_prepend_5, UInt<2>(0h0))
node _out_T_83 = bits(_out_T_82, 1, 0)
node _out_rimask_T_8 = bits(out_frontMask, 19, 16)
node out_rimask_8 = orr(_out_rimask_T_8)
node _out_wimask_T_8 = bits(out_frontMask, 19, 16)
node out_wimask_8 = andr(_out_wimask_T_8)
node _out_romask_T_8 = bits(out_backMask, 19, 16)
node out_romask_8 = orr(_out_romask_T_8)
node _out_womask_T_8 = bits(out_backMask, 19, 16)
node out_womask_8 = andr(_out_womask_T_8)
node out_f_rivalid_8 = and(out_rivalid[8], out_rimask_8)
node out_f_roready_8 = and(out_roready[8], out_romask_8)
node out_f_wivalid_8 = and(out_wivalid[8], out_wimask_8)
node out_f_woready_8 = and(out_woready[8], out_womask_8)
node _out_T_84 = bits(out_front.bits.data, 19, 16)
when out_f_woready_8 :
connect txwm, _out_T_84
node _out_T_85 = and(out_f_rivalid_8, UInt<1>(0h1))
node _out_T_86 = and(UInt<1>(0h1), out_f_roready_8)
node _out_T_87 = and(out_f_wivalid_8, UInt<1>(0h1))
node _out_T_88 = and(UInt<1>(0h1), out_f_woready_8)
node _out_T_89 = eq(out_rimask_8, UInt<1>(0h0))
node _out_T_90 = eq(out_wimask_8, UInt<1>(0h0))
node _out_T_91 = eq(out_romask_8, UInt<1>(0h0))
node _out_T_92 = eq(out_womask_8, UInt<1>(0h0))
node _out_prepend_T_6 = or(_out_T_83, UInt<16>(0h0))
node out_prepend_6 = cat(txwm, _out_prepend_T_6)
node _out_T_93 = or(out_prepend_6, UInt<20>(0h0))
node _out_T_94 = bits(_out_T_93, 19, 0)
node _out_rimask_T_9 = bits(out_frontMask, 32, 32)
node out_rimask_9 = orr(_out_rimask_T_9)
node _out_wimask_T_9 = bits(out_frontMask, 32, 32)
node out_wimask_9 = andr(_out_wimask_T_9)
node _out_romask_T_9 = bits(out_backMask, 32, 32)
node out_romask_9 = orr(_out_romask_T_9)
node _out_womask_T_9 = bits(out_backMask, 32, 32)
node out_womask_9 = andr(_out_womask_T_9)
node out_f_rivalid_9 = and(out_rivalid[9], out_rimask_9)
node out_f_roready_9 = and(out_roready[9], out_romask_9)
node out_f_wivalid_9 = and(out_wivalid[9], out_wimask_9)
node out_f_woready_9 = and(out_woready[9], out_womask_9)
node _out_T_95 = bits(out_front.bits.data, 32, 32)
when out_f_woready_9 :
connect rxen, _out_T_95
node _out_T_96 = and(out_f_rivalid_9, UInt<1>(0h1))
node _out_T_97 = and(UInt<1>(0h1), out_f_roready_9)
node _out_T_98 = and(out_f_wivalid_9, UInt<1>(0h1))
node _out_T_99 = and(UInt<1>(0h1), out_f_woready_9)
node _out_T_100 = eq(out_rimask_9, UInt<1>(0h0))
node _out_T_101 = eq(out_wimask_9, UInt<1>(0h0))
node _out_T_102 = eq(out_romask_9, UInt<1>(0h0))
node _out_T_103 = eq(out_womask_9, UInt<1>(0h0))
node _out_prepend_T_7 = or(_out_T_94, UInt<32>(0h0))
node out_prepend_7 = cat(rxen, _out_prepend_T_7)
node _out_T_104 = or(out_prepend_7, UInt<33>(0h0))
node _out_T_105 = bits(_out_T_104, 32, 0)
node _out_rimask_T_10 = bits(out_frontMask, 51, 48)
node out_rimask_10 = orr(_out_rimask_T_10)
node _out_wimask_T_10 = bits(out_frontMask, 51, 48)
node out_wimask_10 = andr(_out_wimask_T_10)
node _out_romask_T_10 = bits(out_backMask, 51, 48)
node out_romask_10 = orr(_out_romask_T_10)
node _out_womask_T_10 = bits(out_backMask, 51, 48)
node out_womask_10 = andr(_out_womask_T_10)
node out_f_rivalid_10 = and(out_rivalid[10], out_rimask_10)
node out_f_roready_10 = and(out_roready[10], out_romask_10)
node out_f_wivalid_10 = and(out_wivalid[10], out_wimask_10)
node out_f_woready_10 = and(out_woready[10], out_womask_10)
node _out_T_106 = bits(out_front.bits.data, 51, 48)
when out_f_woready_10 :
connect rxwm, _out_T_106
node _out_T_107 = and(out_f_rivalid_10, UInt<1>(0h1))
node _out_T_108 = and(UInt<1>(0h1), out_f_roready_10)
node _out_T_109 = and(out_f_wivalid_10, UInt<1>(0h1))
node _out_T_110 = and(UInt<1>(0h1), out_f_woready_10)
node _out_T_111 = eq(out_rimask_10, UInt<1>(0h0))
node _out_T_112 = eq(out_wimask_10, UInt<1>(0h0))
node _out_T_113 = eq(out_romask_10, UInt<1>(0h0))
node _out_T_114 = eq(out_womask_10, UInt<1>(0h0))
node _out_prepend_T_8 = or(_out_T_105, UInt<48>(0h0))
node out_prepend_8 = cat(rxwm, _out_prepend_T_8)
node _out_T_115 = or(out_prepend_8, UInt<52>(0h0))
node _out_T_116 = bits(_out_T_115, 51, 0)
node _out_rimask_T_11 = bits(out_frontMask, 0, 0)
node out_rimask_11 = orr(_out_rimask_T_11)
node _out_wimask_T_11 = bits(out_frontMask, 0, 0)
node out_wimask_11 = andr(_out_wimask_T_11)
node _out_romask_T_11 = bits(out_backMask, 0, 0)
node out_romask_11 = orr(_out_romask_T_11)
node _out_womask_T_11 = bits(out_backMask, 0, 0)
node out_womask_11 = andr(_out_womask_T_11)
node out_f_rivalid_11 = and(out_rivalid[11], out_rimask_11)
node out_f_roready_11 = and(out_roready[11], out_romask_11)
node out_f_wivalid_11 = and(out_wivalid[11], out_wimask_11)
node out_f_woready_11 = and(out_woready[11], out_womask_11)
node _out_T_117 = bits(out_front.bits.data, 0, 0)
when out_f_woready_11 :
connect ie.txwm, _out_T_117
node _out_T_118 = and(out_f_rivalid_11, UInt<1>(0h1))
node _out_T_119 = and(UInt<1>(0h1), out_f_roready_11)
node _out_T_120 = and(out_f_wivalid_11, UInt<1>(0h1))
node _out_T_121 = and(UInt<1>(0h1), out_f_woready_11)
node _out_T_122 = eq(out_rimask_11, UInt<1>(0h0))
node _out_T_123 = eq(out_wimask_11, UInt<1>(0h0))
node _out_T_124 = eq(out_romask_11, UInt<1>(0h0))
node _out_T_125 = eq(out_womask_11, UInt<1>(0h0))
node _out_T_126 = or(ie.txwm, UInt<1>(0h0))
node _out_T_127 = bits(_out_T_126, 0, 0)
node _out_rimask_T_12 = bits(out_frontMask, 1, 1)
node out_rimask_12 = orr(_out_rimask_T_12)
node _out_wimask_T_12 = bits(out_frontMask, 1, 1)
node out_wimask_12 = andr(_out_wimask_T_12)
node _out_romask_T_12 = bits(out_backMask, 1, 1)
node out_romask_12 = orr(_out_romask_T_12)
node _out_womask_T_12 = bits(out_backMask, 1, 1)
node out_womask_12 = andr(_out_womask_T_12)
node out_f_rivalid_12 = and(out_rivalid[12], out_rimask_12)
node out_f_roready_12 = and(out_roready[12], out_romask_12)
node out_f_wivalid_12 = and(out_wivalid[12], out_wimask_12)
node out_f_woready_12 = and(out_woready[12], out_womask_12)
node _out_T_128 = bits(out_front.bits.data, 1, 1)
when out_f_woready_12 :
connect ie.rxwm, _out_T_128
node _out_T_129 = and(out_f_rivalid_12, UInt<1>(0h1))
node _out_T_130 = and(UInt<1>(0h1), out_f_roready_12)
node _out_T_131 = and(out_f_wivalid_12, UInt<1>(0h1))
node _out_T_132 = and(UInt<1>(0h1), out_f_woready_12)
node _out_T_133 = eq(out_rimask_12, UInt<1>(0h0))
node _out_T_134 = eq(out_wimask_12, UInt<1>(0h0))
node _out_T_135 = eq(out_romask_12, UInt<1>(0h0))
node _out_T_136 = eq(out_womask_12, UInt<1>(0h0))
node _out_prepend_T_9 = or(_out_T_127, UInt<1>(0h0))
node out_prepend_9 = cat(ie.rxwm, _out_prepend_T_9)
node _out_T_137 = or(out_prepend_9, UInt<2>(0h0))
node _out_T_138 = bits(_out_T_137, 1, 0)
node _out_rimask_T_13 = bits(out_frontMask, 32, 32)
node out_rimask_13 = orr(_out_rimask_T_13)
node _out_wimask_T_13 = bits(out_frontMask, 32, 32)
node out_wimask_13 = andr(_out_wimask_T_13)
node _out_romask_T_13 = bits(out_backMask, 32, 32)
node out_romask_13 = orr(_out_romask_T_13)
node _out_womask_T_13 = bits(out_backMask, 32, 32)
node out_womask_13 = andr(_out_womask_T_13)
node out_f_rivalid_13 = and(out_rivalid[13], out_rimask_13)
node out_f_roready_13 = and(out_roready[13], out_romask_13)
node out_f_wivalid_13 = and(out_wivalid[13], out_wimask_13)
node out_f_woready_13 = and(out_woready[13], out_womask_13)
node _out_T_139 = bits(out_front.bits.data, 32, 32)
node _out_T_140 = and(out_f_rivalid_13, UInt<1>(0h1))
node _out_T_141 = and(UInt<1>(0h1), out_f_roready_13)
node _out_T_142 = eq(out_rimask_13, UInt<1>(0h0))
node _out_T_143 = eq(out_wimask_13, UInt<1>(0h0))
node _out_T_144 = eq(out_romask_13, UInt<1>(0h0))
node _out_T_145 = eq(out_womask_13, UInt<1>(0h0))
node _out_prepend_T_10 = or(_out_T_138, UInt<32>(0h0))
node out_prepend_10 = cat(ip.txwm, _out_prepend_T_10)
node _out_T_146 = or(out_prepend_10, UInt<33>(0h0))
node _out_T_147 = bits(_out_T_146, 32, 0)
node _out_rimask_T_14 = bits(out_frontMask, 33, 33)
node out_rimask_14 = orr(_out_rimask_T_14)
node _out_wimask_T_14 = bits(out_frontMask, 33, 33)
node out_wimask_14 = andr(_out_wimask_T_14)
node _out_romask_T_14 = bits(out_backMask, 33, 33)
node out_romask_14 = orr(_out_romask_T_14)
node _out_womask_T_14 = bits(out_backMask, 33, 33)
node out_womask_14 = andr(_out_womask_T_14)
node out_f_rivalid_14 = and(out_rivalid[14], out_rimask_14)
node out_f_roready_14 = and(out_roready[14], out_romask_14)
node out_f_wivalid_14 = and(out_wivalid[14], out_wimask_14)
node out_f_woready_14 = and(out_woready[14], out_womask_14)
node _out_T_148 = bits(out_front.bits.data, 33, 33)
node _out_T_149 = and(out_f_rivalid_14, UInt<1>(0h1))
node _out_T_150 = and(UInt<1>(0h1), out_f_roready_14)
node _out_T_151 = eq(out_rimask_14, UInt<1>(0h0))
node _out_T_152 = eq(out_wimask_14, UInt<1>(0h0))
node _out_T_153 = eq(out_romask_14, UInt<1>(0h0))
node _out_T_154 = eq(out_womask_14, UInt<1>(0h0))
node _out_prepend_T_11 = or(_out_T_147, UInt<33>(0h0))
node out_prepend_11 = cat(ip.rxwm, _out_prepend_T_11)
node _out_T_155 = or(out_prepend_11, UInt<34>(0h0))
node _out_T_156 = bits(_out_T_155, 33, 0)
node _out_rimask_T_15 = bits(out_frontMask, 15, 0)
node out_rimask_15 = orr(_out_rimask_T_15)
node _out_wimask_T_15 = bits(out_frontMask, 15, 0)
node out_wimask_15 = andr(_out_wimask_T_15)
node _out_romask_T_15 = bits(out_backMask, 15, 0)
node out_romask_15 = orr(_out_romask_T_15)
node _out_womask_T_15 = bits(out_backMask, 15, 0)
node out_womask_15 = andr(_out_womask_T_15)
node out_f_rivalid_15 = and(out_rivalid[15], out_rimask_15)
node out_f_roready_15 = and(out_roready[15], out_romask_15)
node out_f_wivalid_15 = and(out_wivalid[15], out_wimask_15)
node out_f_woready_15 = and(out_woready[15], out_womask_15)
node _out_T_157 = bits(out_front.bits.data, 15, 0)
when out_f_woready_15 :
connect div, _out_T_157
node _out_T_158 = and(out_f_rivalid_15, UInt<1>(0h1))
node _out_T_159 = and(UInt<1>(0h1), out_f_roready_15)
node _out_T_160 = and(out_f_wivalid_15, UInt<1>(0h1))
node _out_T_161 = and(UInt<1>(0h1), out_f_woready_15)
node _out_T_162 = eq(out_rimask_15, UInt<1>(0h0))
node _out_T_163 = eq(out_wimask_15, UInt<1>(0h0))
node _out_T_164 = eq(out_romask_15, UInt<1>(0h0))
node _out_T_165 = eq(out_womask_15, UInt<1>(0h0))
node _out_T_166 = or(div, UInt<16>(0h0))
node _out_T_167 = bits(_out_T_166, 15, 0)
node _out_iindex_T = bits(out_front.bits.index, 0, 0)
node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1)
node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2)
node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3)
node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4)
node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5)
node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6)
node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7)
node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8)
node out_iindex = cat(_out_iindex_T_1, _out_iindex_T)
node _out_oindex_T = bits(out_front.bits.index, 0, 0)
node _out_oindex_T_1 = bits(out_front.bits.index, 1, 1)
node _out_oindex_T_2 = bits(out_front.bits.index, 2, 2)
node _out_oindex_T_3 = bits(out_front.bits.index, 3, 3)
node _out_oindex_T_4 = bits(out_front.bits.index, 4, 4)
node _out_oindex_T_5 = bits(out_front.bits.index, 5, 5)
node _out_oindex_T_6 = bits(out_front.bits.index, 6, 6)
node _out_oindex_T_7 = bits(out_front.bits.index, 7, 7)
node _out_oindex_T_8 = bits(out_front.bits.index, 8, 8)
node out_oindex = cat(_out_oindex_T_1, _out_oindex_T)
node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex)
node out_frontSel_0 = bits(_out_frontSel_T, 0, 0)
node out_frontSel_1 = bits(_out_frontSel_T, 1, 1)
node out_frontSel_2 = bits(_out_frontSel_T, 2, 2)
node out_frontSel_3 = bits(_out_frontSel_T, 3, 3)
node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex)
node out_backSel_0 = bits(_out_backSel_T, 0, 0)
node out_backSel_1 = bits(_out_backSel_T, 1, 1)
node out_backSel_2 = bits(_out_backSel_T, 2, 2)
node out_backSel_3 = bits(_out_backSel_T, 3, 3)
node _out_rifireMux_T = and(in.valid, out_front.ready)
node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read)
wire out_rifireMux_out : UInt<1>
node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0)
node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T)
connect out_rifireMux_out, UInt<1>(0h1)
connect out_rivalid[5], _out_rifireMux_T_3
connect out_rivalid[4], _out_rifireMux_T_3
connect out_rivalid[3], _out_rifireMux_T_3
connect out_rivalid[2], _out_rifireMux_T_3
connect out_rivalid[1], _out_rifireMux_T_3
connect out_rivalid[0], _out_rifireMux_T_3
node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0))
node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4)
wire out_rifireMux_out_1 : UInt<1>
node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1)
node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_2)
connect out_rifireMux_out_1, UInt<1>(0h1)
connect out_rivalid[10], _out_rifireMux_T_7
connect out_rivalid[9], _out_rifireMux_T_7
connect out_rivalid[8], _out_rifireMux_T_7
connect out_rivalid[7], _out_rifireMux_T_7
connect out_rivalid[6], _out_rifireMux_T_7
node _out_rifireMux_T_8 = eq(_out_T_2, UInt<1>(0h0))
node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8)
wire out_rifireMux_out_2 : UInt<1>
node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2)
node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_4)
connect out_rifireMux_out_2, UInt<1>(0h1)
connect out_rivalid[14], _out_rifireMux_T_11
connect out_rivalid[13], _out_rifireMux_T_11
connect out_rivalid[12], _out_rifireMux_T_11
connect out_rivalid[11], _out_rifireMux_T_11
node _out_rifireMux_T_12 = eq(_out_T_4, UInt<1>(0h0))
node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12)
wire out_rifireMux_out_3 : UInt<1>
node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3)
node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, _out_T_6)
connect out_rifireMux_out_3, UInt<1>(0h1)
connect out_rivalid[15], _out_rifireMux_T_15
node _out_rifireMux_T_16 = eq(_out_T_6, UInt<1>(0h0))
node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16)
node _out_rifireMux_T_18 = geq(out_iindex, UInt<3>(0h4))
wire _out_rifireMux_WIRE : UInt<1>[4]
connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5
connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9
connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13
connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17
node out_rifireMux = mux(_out_rifireMux_T_18, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex])
node _out_wifireMux_T = and(in.valid, out_front.ready)
node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0))
node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1)
wire out_wifireMux_out : UInt<1>
node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0)
node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T)
connect out_wifireMux_out, UInt<1>(0h1)
connect out_wivalid[5], _out_wifireMux_T_4
connect out_wivalid[4], _out_wifireMux_T_4
connect out_wivalid[3], _out_wifireMux_T_4
connect out_wivalid[2], _out_wifireMux_T_4
connect out_wivalid[1], _out_wifireMux_T_4
connect out_wivalid[0], _out_wifireMux_T_4
node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0))
node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5)
wire out_wifireMux_out_1 : UInt<1>
node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1)
node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_2)
connect out_wifireMux_out_1, UInt<1>(0h1)
connect out_wivalid[10], _out_wifireMux_T_8
connect out_wivalid[9], _out_wifireMux_T_8
connect out_wivalid[8], _out_wifireMux_T_8
connect out_wivalid[7], _out_wifireMux_T_8
connect out_wivalid[6], _out_wifireMux_T_8
node _out_wifireMux_T_9 = eq(_out_T_2, UInt<1>(0h0))
node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9)
wire out_wifireMux_out_2 : UInt<1>
node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2)
node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_4)
connect out_wifireMux_out_2, UInt<1>(0h1)
connect out_wivalid[14], _out_wifireMux_T_12
connect out_wivalid[13], _out_wifireMux_T_12
connect out_wivalid[12], _out_wifireMux_T_12
connect out_wivalid[11], _out_wifireMux_T_12
node _out_wifireMux_T_13 = eq(_out_T_4, UInt<1>(0h0))
node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13)
wire out_wifireMux_out_3 : UInt<1>
node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3)
node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, _out_T_6)
connect out_wifireMux_out_3, UInt<1>(0h1)
connect out_wivalid[15], _out_wifireMux_T_16
node _out_wifireMux_T_17 = eq(_out_T_6, UInt<1>(0h0))
node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17)
node _out_wifireMux_T_19 = geq(out_iindex, UInt<3>(0h4))
wire _out_wifireMux_WIRE : UInt<1>[4]
connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6
connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10
connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14
connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18
node out_wifireMux = mux(_out_wifireMux_T_19, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex])
node _out_rofireMux_T = and(out_front.valid, out.ready)
node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read)
wire out_rofireMux_out : UInt<1>
node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0)
node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1)
connect out_rofireMux_out, UInt<1>(0h1)
connect out_roready[5], _out_rofireMux_T_3
connect out_roready[4], _out_rofireMux_T_3
connect out_roready[3], _out_rofireMux_T_3
connect out_roready[2], _out_rofireMux_T_3
connect out_roready[1], _out_rofireMux_T_3
connect out_roready[0], _out_rofireMux_T_3
node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0))
node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4)
wire out_rofireMux_out_1 : UInt<1>
node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1)
node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_3)
connect out_rofireMux_out_1, UInt<1>(0h1)
connect out_roready[10], _out_rofireMux_T_7
connect out_roready[9], _out_rofireMux_T_7
connect out_roready[8], _out_rofireMux_T_7
connect out_roready[7], _out_rofireMux_T_7
connect out_roready[6], _out_rofireMux_T_7
node _out_rofireMux_T_8 = eq(_out_T_3, UInt<1>(0h0))
node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8)
wire out_rofireMux_out_2 : UInt<1>
node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2)
node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_5)
connect out_rofireMux_out_2, UInt<1>(0h1)
connect out_roready[14], _out_rofireMux_T_11
connect out_roready[13], _out_rofireMux_T_11
connect out_roready[12], _out_rofireMux_T_11
connect out_roready[11], _out_rofireMux_T_11
node _out_rofireMux_T_12 = eq(_out_T_5, UInt<1>(0h0))
node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12)
wire out_rofireMux_out_3 : UInt<1>
node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3)
node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, _out_T_7)
connect out_rofireMux_out_3, UInt<1>(0h1)
connect out_roready[15], _out_rofireMux_T_15
node _out_rofireMux_T_16 = eq(_out_T_7, UInt<1>(0h0))
node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16)
node _out_rofireMux_T_18 = geq(out_oindex, UInt<3>(0h4))
wire _out_rofireMux_WIRE : UInt<1>[4]
connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5
connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9
connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13
connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17
node out_rofireMux = mux(_out_rofireMux_T_18, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex])
node _out_wofireMux_T = and(out_front.valid, out.ready)
node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0))
node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1)
wire out_wofireMux_out : UInt<1>
node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0)
node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1)
connect out_wofireMux_out, UInt<1>(0h1)
connect out_woready[5], _out_wofireMux_T_4
connect out_woready[4], _out_wofireMux_T_4
connect out_woready[3], _out_wofireMux_T_4
connect out_woready[2], _out_wofireMux_T_4
connect out_woready[1], _out_wofireMux_T_4
connect out_woready[0], _out_wofireMux_T_4
node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0))
node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5)
wire out_wofireMux_out_1 : UInt<1>
node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1)
node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_3)
connect out_wofireMux_out_1, UInt<1>(0h1)
connect out_woready[10], _out_wofireMux_T_8
connect out_woready[9], _out_wofireMux_T_8
connect out_woready[8], _out_wofireMux_T_8
connect out_woready[7], _out_wofireMux_T_8
connect out_woready[6], _out_wofireMux_T_8
node _out_wofireMux_T_9 = eq(_out_T_3, UInt<1>(0h0))
node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9)
wire out_wofireMux_out_2 : UInt<1>
node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2)
node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_5)
connect out_wofireMux_out_2, UInt<1>(0h1)
connect out_woready[14], _out_wofireMux_T_12
connect out_woready[13], _out_wofireMux_T_12
connect out_woready[12], _out_wofireMux_T_12
connect out_woready[11], _out_wofireMux_T_12
node _out_wofireMux_T_13 = eq(_out_T_5, UInt<1>(0h0))
node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13)
wire out_wofireMux_out_3 : UInt<1>
node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3)
node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, _out_T_7)
connect out_wofireMux_out_3, UInt<1>(0h1)
connect out_woready[15], _out_wofireMux_T_16
node _out_wofireMux_T_17 = eq(_out_T_7, UInt<1>(0h0))
node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17)
node _out_wofireMux_T_19 = geq(out_oindex, UInt<3>(0h4))
wire _out_wofireMux_WIRE : UInt<1>[4]
connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6
connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10
connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14
connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18
node out_wofireMux = mux(_out_wofireMux_T_19, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex])
node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux)
node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux)
node _out_in_ready_T = and(out_front.ready, out_iready)
connect in.ready, _out_in_ready_T
node _out_front_valid_T = and(in.valid, out_iready)
connect out_front.valid, _out_front_valid_T
node _out_front_ready_T = and(out.ready, out_oready)
connect out_front.ready, _out_front_ready_T
node _out_out_valid_T = and(out_front.valid, out_oready)
connect out.valid, _out_out_valid_T
connect out.bits.read, out_front.bits.read
node _out_out_bits_data_T = geq(out_oindex, UInt<3>(0h4))
wire _out_out_bits_data_WIRE : UInt<1>[4]
connect _out_out_bits_data_WIRE[0], _out_T_1
connect _out_out_bits_data_WIRE[1], _out_T_3
connect _out_out_bits_data_WIRE[2], _out_T_5
connect _out_out_bits_data_WIRE[3], _out_T_7
node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex])
node _out_out_bits_data_T_2 = geq(out_oindex, UInt<3>(0h4))
wire _out_out_bits_data_WIRE_1 : UInt<64>[4]
connect _out_out_bits_data_WIRE_1[0], _out_T_61
connect _out_out_bits_data_WIRE_1[1], _out_T_116
connect _out_out_bits_data_WIRE_1[2], _out_T_156
connect _out_out_bits_data_WIRE_1[3], _out_T_167
node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex])
node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0))
connect out.bits.data, _out_out_bits_data_T_4
connect out.bits.extra, out_front.bits.extra
connect in.valid, controlNodeIn.a.valid
connect controlNodeIn.a.ready, in.ready
connect controlNodeIn.d.valid, out.valid
connect out.ready, controlNodeIn.d.ready
wire controlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect controlNodeIn_d_bits_d.opcode, UInt<1>(0h0)
connect controlNodeIn_d_bits_d.param, UInt<1>(0h0)
connect controlNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size
connect controlNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source
connect controlNodeIn_d_bits_d.sink, UInt<1>(0h0)
connect controlNodeIn_d_bits_d.denied, UInt<1>(0h0)
invalidate controlNodeIn_d_bits_d.data
connect controlNodeIn_d_bits_d.corrupt, UInt<1>(0h0)
connect controlNodeIn.d.bits.corrupt, controlNodeIn_d_bits_d.corrupt
connect controlNodeIn.d.bits.data, controlNodeIn_d_bits_d.data
connect controlNodeIn.d.bits.denied, controlNodeIn_d_bits_d.denied
connect controlNodeIn.d.bits.sink, controlNodeIn_d_bits_d.sink
connect controlNodeIn.d.bits.source, controlNodeIn_d_bits_d.source
connect controlNodeIn.d.bits.size, controlNodeIn_d_bits_d.size
connect controlNodeIn.d.bits.param, controlNodeIn_d_bits_d.param
connect controlNodeIn.d.bits.opcode, controlNodeIn_d_bits_d.opcode
connect controlNodeIn.d.bits.data, out.bits.data
node _controlNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0))
connect controlNodeIn.d.bits.opcode, _controlNodeIn_d_bits_opcode_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<29>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<29>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1) | module TLUART( // @[UART.scala:127:25]
input clock, // @[UART.scala:127:25]
input reset, // @[UART.scala:127:25]
output auto_int_xing_out_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_control_xing_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_control_xing_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_control_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_control_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_control_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_control_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_control_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_control_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_control_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_control_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_control_xing_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_control_xing_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_control_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_control_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_control_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_control_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_io_out_txd, // @[LazyModuleImp.scala:107:25]
input auto_io_out_rxd // @[LazyModuleImp.scala:107:25]
);
wire out_front_valid; // @[RegisterRouter.scala:87:24]
wire out_front_ready; // @[RegisterRouter.scala:87:24]
wire out_bits_read; // @[RegisterRouter.scala:87:24]
wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18]
wire in_bits_read; // @[RegisterRouter.scala:73:18]
wire buffer_auto_out_d_valid; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_ready; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire [10:0] buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_out_a_valid; // @[Buffer.scala:40:9]
wire buffer_auto_out_a_ready; // @[Buffer.scala:40:9]
wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9]
wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9]
wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9]
wire [10:0] buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_ready; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9]
wire [10:0] buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_a_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_a_ready; // @[Buffer.scala:40:9]
wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [10:0] buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire _rxq_io_deq_valid; // @[UART.scala:133:19]
wire [7:0] _rxq_io_deq_bits; // @[UART.scala:133:19]
wire [3:0] _rxq_io_count; // @[UART.scala:133:19]
wire _rxm_io_out_valid; // @[UART.scala:132:19]
wire [7:0] _rxm_io_out_bits; // @[UART.scala:132:19]
wire _txq_io_enq_ready; // @[UART.scala:130:19]
wire _txq_io_deq_valid; // @[UART.scala:130:19]
wire [7:0] _txq_io_deq_bits; // @[UART.scala:130:19]
wire [3:0] _txq_io_count; // @[UART.scala:130:19]
wire _txm_io_in_ready; // @[UART.scala:129:19]
wire _txm_io_tx_busy; // @[UART.scala:129:19]
wire auto_control_xing_in_a_valid_0 = auto_control_xing_in_a_valid; // @[UART.scala:127:25]
wire [2:0] auto_control_xing_in_a_bits_opcode_0 = auto_control_xing_in_a_bits_opcode; // @[UART.scala:127:25]
wire [2:0] auto_control_xing_in_a_bits_param_0 = auto_control_xing_in_a_bits_param; // @[UART.scala:127:25]
wire [1:0] auto_control_xing_in_a_bits_size_0 = auto_control_xing_in_a_bits_size; // @[UART.scala:127:25]
wire [10:0] auto_control_xing_in_a_bits_source_0 = auto_control_xing_in_a_bits_source; // @[UART.scala:127:25]
wire [28:0] auto_control_xing_in_a_bits_address_0 = auto_control_xing_in_a_bits_address; // @[UART.scala:127:25]
wire [7:0] auto_control_xing_in_a_bits_mask_0 = auto_control_xing_in_a_bits_mask; // @[UART.scala:127:25]
wire [63:0] auto_control_xing_in_a_bits_data_0 = auto_control_xing_in_a_bits_data; // @[UART.scala:127:25]
wire auto_control_xing_in_a_bits_corrupt_0 = auto_control_xing_in_a_bits_corrupt; // @[UART.scala:127:25]
wire auto_control_xing_in_d_ready_0 = auto_control_xing_in_d_ready; // @[UART.scala:127:25]
wire auto_io_out_rxd_0 = auto_io_out_rxd; // @[UART.scala:127:25]
wire [8:0] out_maskMatch = 9'h1FC; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_15 = 8'h0; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_16 = 8'h0; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T = 8'h0; // @[RegisterRouter.scala:87:24]
wire [8:0] out_prepend = 9'h0; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_T_24 = 31'h0; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_T_25 = 31'h0; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_prepend_T_1 = 31'h0; // @[RegisterRouter.scala:87:24]
wire [2:0] controlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17]
wire [63:0] controlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17]
wire auto_control_xing_in_d_bits_sink = 1'h0; // @[UART.scala:127:25]
wire auto_control_xing_in_d_bits_denied = 1'h0; // @[UART.scala:127:25]
wire auto_control_xing_in_d_bits_corrupt = 1'h0; // @[UART.scala:127:25]
wire buffer_auto_in_d_bits_sink = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_bits_denied = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_bits_sink = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_bits_denied = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire buffer_nodeOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire buffer_nodeOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire buffer_nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire buffer_nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire controlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire controlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire controlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire controlXingOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire controlXingOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire controlXingOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire controlXingIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire controlXingIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire controlXingIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire _ie_WIRE_rxwm = 1'h0; // @[UART.scala:186:32]
wire _ie_WIRE_txwm = 1'h0; // @[UART.scala:186:32]
wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17]
wire controlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17]
wire controlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17]
wire controlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17]
wire [1:0] auto_control_xing_in_d_bits_param = 2'h0; // @[UART.scala:127:25]
wire [1:0] buffer_auto_in_d_bits_param = 2'h0; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_d_bits_param = 2'h0; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] buffer_nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] controlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] controlXingOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] controlXingIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] controlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17]
wire intXingOut_sync_0; // @[MixedNode.scala:542:17]
wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24]
wire controlXingIn_a_ready; // @[MixedNode.scala:551:17]
wire controlXingIn_a_valid = auto_control_xing_in_a_valid_0; // @[UART.scala:127:25]
wire [2:0] controlXingIn_a_bits_opcode = auto_control_xing_in_a_bits_opcode_0; // @[UART.scala:127:25]
wire [2:0] controlXingIn_a_bits_param = auto_control_xing_in_a_bits_param_0; // @[UART.scala:127:25]
wire [1:0] controlXingIn_a_bits_size = auto_control_xing_in_a_bits_size_0; // @[UART.scala:127:25]
wire [10:0] controlXingIn_a_bits_source = auto_control_xing_in_a_bits_source_0; // @[UART.scala:127:25]
wire [28:0] controlXingIn_a_bits_address = auto_control_xing_in_a_bits_address_0; // @[UART.scala:127:25]
wire [7:0] controlXingIn_a_bits_mask = auto_control_xing_in_a_bits_mask_0; // @[UART.scala:127:25]
wire [63:0] controlXingIn_a_bits_data = auto_control_xing_in_a_bits_data_0; // @[UART.scala:127:25]
wire controlXingIn_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt_0; // @[UART.scala:127:25]
wire controlXingIn_d_ready = auto_control_xing_in_d_ready_0; // @[UART.scala:127:25]
wire controlXingIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] controlXingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] controlXingIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [10:0] controlXingIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] controlXingIn_d_bits_data; // @[MixedNode.scala:551:17]
wire ioNodeOut_txd; // @[MixedNode.scala:542:17]
wire ioNodeOut_rxd = auto_io_out_rxd_0; // @[UART.scala:127:25]
wire auto_int_xing_out_sync_0_0; // @[UART.scala:127:25]
wire auto_control_xing_in_a_ready_0; // @[UART.scala:127:25]
wire [2:0] auto_control_xing_in_d_bits_opcode_0; // @[UART.scala:127:25]
wire [1:0] auto_control_xing_in_d_bits_size_0; // @[UART.scala:127:25]
wire [10:0] auto_control_xing_in_d_bits_source_0; // @[UART.scala:127:25]
wire [63:0] auto_control_xing_in_d_bits_data_0; // @[UART.scala:127:25]
wire auto_control_xing_in_d_valid_0; // @[UART.scala:127:25]
wire auto_io_out_txd_0; // @[UART.scala:127:25]
wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire controlXingOut_a_ready = buffer_auto_in_a_ready; // @[Buffer.scala:40:9]
wire controlXingOut_a_valid; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_a_valid = buffer_auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] controlXingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] controlXingOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [1:0] controlXingOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] buffer_nodeIn_a_bits_size = buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [10:0] controlXingOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [10:0] buffer_nodeIn_a_bits_source = buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [28:0] controlXingOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [28:0] buffer_nodeIn_a_bits_address = buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] controlXingOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [7:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] controlXingOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [63:0] buffer_nodeIn_a_bits_data = buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire controlXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_a_bits_corrupt = buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire controlXingOut_d_ready; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_d_ready = buffer_auto_in_d_ready; // @[Buffer.scala:40:9]
wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire controlXingOut_d_valid = buffer_auto_in_d_valid; // @[Buffer.scala:40:9]
wire [2:0] controlXingOut_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [10:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [1:0] controlXingOut_d_bits_size = buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9]
wire [10:0] controlXingOut_d_bits_source = buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9]
wire [63:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [63:0] controlXingOut_d_bits_data = buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9]
wire controlNodeIn_a_ready; // @[MixedNode.scala:551:17]
wire buffer_nodeOut_a_ready = buffer_auto_out_a_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire controlNodeIn_a_valid = buffer_auto_out_a_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] controlNodeIn_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] controlNodeIn_a_bits_param = buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9]
wire [10:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [1:0] controlNodeIn_a_bits_size = buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9]
wire [28:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [10:0] controlNodeIn_a_bits_source = buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9]
wire [7:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [28:0] controlNodeIn_a_bits_address = buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9]
wire [63:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [7:0] controlNodeIn_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9]
wire buffer_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire [63:0] controlNodeIn_a_bits_data = buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire controlNodeIn_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9]
wire controlNodeIn_d_ready = buffer_auto_out_d_ready; // @[Buffer.scala:40:9]
wire controlNodeIn_d_valid; // @[MixedNode.scala:551:17]
wire buffer_nodeOut_d_valid = buffer_auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] controlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] controlNodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] buffer_nodeOut_d_bits_size = buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [10:0] controlNodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [10:0] buffer_nodeOut_d_bits_source = buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [63:0] controlNodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [63:0] buffer_nodeOut_d_bits_data = buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9]
assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_out_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_corrupt = buffer_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_auto_out_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9]
assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9]
assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_corrupt = buffer_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_io_out_txd_0 = ioNodeOut_txd; // @[UART.scala:127:25]
wire _intnodeOut_0_T_2; // @[UART.scala:191:41]
wire intnodeOut_0; // @[MixedNode.scala:542:17]
wire in_ready; // @[RegisterRouter.scala:73:18]
assign buffer_auto_out_a_ready = controlNodeIn_a_ready; // @[Buffer.scala:40:9]
wire in_valid = controlNodeIn_a_valid; // @[RegisterRouter.scala:73:18]
wire [1:0] in_bits_extra_tlrr_extra_size = controlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18]
wire [10:0] in_bits_extra_tlrr_extra_source = controlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18]
wire [7:0] in_bits_mask = controlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18]
wire [63:0] in_bits_data = controlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18]
wire out_ready = controlNodeIn_d_ready; // @[RegisterRouter.scala:87:24]
wire out_valid; // @[RegisterRouter.scala:87:24]
assign buffer_auto_out_d_valid = controlNodeIn_d_valid; // @[Buffer.scala:40:9]
assign buffer_auto_out_d_bits_opcode = controlNodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] controlNodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign buffer_auto_out_d_bits_size = controlNodeIn_d_bits_size; // @[Buffer.scala:40:9]
wire [10:0] controlNodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign buffer_auto_out_d_bits_source = controlNodeIn_d_bits_source; // @[Buffer.scala:40:9]
wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24]
assign buffer_auto_out_d_bits_data = controlNodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign controlXingIn_a_ready = controlXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_a_valid = controlXingOut_a_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_opcode = controlXingOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_param = controlXingOut_a_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_size = controlXingOut_a_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_source = controlXingOut_a_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_address = controlXingOut_a_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_mask = controlXingOut_a_bits_mask; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_data = controlXingOut_a_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_corrupt = controlXingOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_ready = controlXingOut_d_ready; // @[Buffer.scala:40:9]
assign controlXingIn_d_valid = controlXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign controlXingIn_d_bits_opcode = controlXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign controlXingIn_d_bits_size = controlXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign controlXingIn_d_bits_source = controlXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign controlXingIn_d_bits_data = controlXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign auto_control_xing_in_a_ready_0 = controlXingIn_a_ready; // @[UART.scala:127:25]
assign controlXingOut_a_valid = controlXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_opcode = controlXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_param = controlXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_size = controlXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_source = controlXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_address = controlXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_mask = controlXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_data = controlXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_corrupt = controlXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_d_ready = controlXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_control_xing_in_d_valid_0 = controlXingIn_d_valid; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_opcode_0 = controlXingIn_d_bits_opcode; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_size_0 = controlXingIn_d_bits_size; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_source_0 = controlXingIn_d_bits_source; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_data_0 = controlXingIn_d_bits_data; // @[UART.scala:127:25]
wire intXingIn_sync_0; // @[MixedNode.scala:551:17]
assign auto_int_xing_out_sync_0_0 = intXingOut_sync_0; // @[UART.scala:127:25]
assign intXingOut_sync_0 = intXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
reg [15:0] div; // @[UART.scala:135:20]
wire [15:0] _out_T_166 = div; // @[RegisterRouter.scala:87:24]
reg txen; // @[UART.scala:141:21]
wire _out_T_71 = txen; // @[RegisterRouter.scala:87:24]
reg rxen; // @[UART.scala:142:21]
reg [3:0] txwm; // @[UART.scala:149:21]
reg [3:0] rxwm; // @[UART.scala:150:21]
reg nstop; // @[UART.scala:151:22]
wire _tx_busy_T = |_txq_io_count; // @[UART.scala:130:19, :175:49]
wire _tx_busy_T_1 = _txm_io_tx_busy | _tx_busy_T; // @[UART.scala:129:19, :175:{33,49}]
wire tx_busy = _tx_busy_T_1 & txen; // @[UART.scala:141:21, :175:{33,54}]
reg ie_rxwm; // @[UART.scala:186:19]
reg ie_txwm; // @[UART.scala:186:19]
wire _out_T_126 = ie_txwm; // @[RegisterRouter.scala:87:24]
wire _ip_rxwm_T; // @[UART.scala:190:28]
wire _ip_txwm_T; // @[UART.scala:189:28]
wire ip_rxwm; // @[UART.scala:187:16]
wire ip_txwm; // @[UART.scala:187:16]
assign _ip_txwm_T = _txq_io_count < txwm; // @[UART.scala:130:19, :149:21, :189:28]
assign ip_txwm = _ip_txwm_T; // @[UART.scala:187:16, :189:28]
assign _ip_rxwm_T = _rxq_io_count > rxwm; // @[UART.scala:133:19, :150:21, :190:28]
assign ip_rxwm = _ip_rxwm_T; // @[UART.scala:187:16, :190:28]
wire _intnodeOut_0_T = ip_txwm & ie_txwm; // @[UART.scala:186:19, :187:16, :191:29]
wire _intnodeOut_0_T_1 = ip_rxwm & ie_rxwm; // @[UART.scala:186:19, :187:16, :191:53]
assign _intnodeOut_0_T_2 = _intnodeOut_0_T | _intnodeOut_0_T_1; // @[UART.scala:191:{29,41,53}]
assign intnodeOut_0 = _intnodeOut_0_T_2; // @[UART.scala:191:41]
wire _out_quash_T_1; // @[RegMapFIFO.scala:26:26]
wire quash; // @[RegMapFIFO.scala:11:21]
wire _out_in_ready_T; // @[RegisterRouter.scala:87:24]
assign controlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18]
wire _in_bits_read_T; // @[RegisterRouter.scala:74:36]
wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24]
wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24]
wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24]
wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24]
wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24]
wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24]
wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24]
assign _in_bits_read_T = controlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36]
wire [25:0] _in_bits_index_T = controlNodeIn_a_bits_address[28:3]; // @[Edges.scala:192:34]
assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19]
wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24]
wire _out_out_valid_T; // @[RegisterRouter.scala:87:24]
assign controlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
wire _controlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25]
assign controlNodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24]
assign controlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign controlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24]
assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24]
assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
wire [8:0] _GEN = out_front_bits_index & 9'h1FC; // @[RegisterRouter.scala:87:24]
wire [8:0] out_findex; // @[RegisterRouter.scala:87:24]
assign out_findex = _GEN; // @[RegisterRouter.scala:87:24]
wire [8:0] out_bindex; // @[RegisterRouter.scala:87:24]
assign out_bindex = _GEN; // @[RegisterRouter.scala:87:24]
wire _GEN_0 = out_findex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T; // @[RegisterRouter.scala:87:24]
assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_2; // @[RegisterRouter.scala:87:24]
assign _out_T_2 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_4; // @[RegisterRouter.scala:87:24]
assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_6; // @[RegisterRouter.scala:87:24]
assign _out_T_6 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _GEN_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1; // @[RegisterRouter.scala:87:24]
assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_T_3; // @[RegisterRouter.scala:87:24]
assign _out_T_3 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_T_5; // @[RegisterRouter.scala:87:24]
assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_T_7; // @[RegisterRouter.scala:87:24]
assign _out_T_7 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_1 = _out_T_3; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2 = _out_T_5; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_3 = _out_T_7; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24]
wire out_rivalid_0; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_rivalid_4; // @[RegisterRouter.scala:87:24]
wire out_rivalid_5; // @[RegisterRouter.scala:87:24]
wire out_rivalid_6; // @[RegisterRouter.scala:87:24]
wire out_rivalid_7; // @[RegisterRouter.scala:87:24]
wire out_rivalid_8; // @[RegisterRouter.scala:87:24]
wire out_rivalid_9; // @[RegisterRouter.scala:87:24]
wire out_rivalid_10; // @[RegisterRouter.scala:87:24]
wire out_rivalid_11; // @[RegisterRouter.scala:87:24]
wire out_rivalid_12; // @[RegisterRouter.scala:87:24]
wire out_rivalid_13; // @[RegisterRouter.scala:87:24]
wire out_rivalid_14; // @[RegisterRouter.scala:87:24]
wire out_rivalid_15; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24]
wire out_wivalid_0; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1; // @[RegisterRouter.scala:87:24]
wire out_wivalid_2; // @[RegisterRouter.scala:87:24]
wire out_wivalid_3; // @[RegisterRouter.scala:87:24]
wire out_wivalid_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_5; // @[RegisterRouter.scala:87:24]
wire out_wivalid_6; // @[RegisterRouter.scala:87:24]
wire out_wivalid_7; // @[RegisterRouter.scala:87:24]
wire out_wivalid_8; // @[RegisterRouter.scala:87:24]
wire out_wivalid_9; // @[RegisterRouter.scala:87:24]
wire out_wivalid_10; // @[RegisterRouter.scala:87:24]
wire out_wivalid_11; // @[RegisterRouter.scala:87:24]
wire out_wivalid_12; // @[RegisterRouter.scala:87:24]
wire out_wivalid_13; // @[RegisterRouter.scala:87:24]
wire out_wivalid_14; // @[RegisterRouter.scala:87:24]
wire out_wivalid_15; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24]
wire out_roready_0; // @[RegisterRouter.scala:87:24]
wire out_roready_1; // @[RegisterRouter.scala:87:24]
wire out_roready_2; // @[RegisterRouter.scala:87:24]
wire out_roready_3; // @[RegisterRouter.scala:87:24]
wire out_roready_4; // @[RegisterRouter.scala:87:24]
wire out_roready_5; // @[RegisterRouter.scala:87:24]
wire out_roready_6; // @[RegisterRouter.scala:87:24]
wire out_roready_7; // @[RegisterRouter.scala:87:24]
wire out_roready_8; // @[RegisterRouter.scala:87:24]
wire out_roready_9; // @[RegisterRouter.scala:87:24]
wire out_roready_10; // @[RegisterRouter.scala:87:24]
wire out_roready_11; // @[RegisterRouter.scala:87:24]
wire out_roready_12; // @[RegisterRouter.scala:87:24]
wire out_roready_13; // @[RegisterRouter.scala:87:24]
wire out_roready_14; // @[RegisterRouter.scala:87:24]
wire out_roready_15; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24]
wire out_woready_0; // @[RegisterRouter.scala:87:24]
wire out_woready_1; // @[RegisterRouter.scala:87:24]
wire out_woready_2; // @[RegisterRouter.scala:87:24]
wire out_woready_3; // @[RegisterRouter.scala:87:24]
wire out_woready_4; // @[RegisterRouter.scala:87:24]
wire out_woready_5; // @[RegisterRouter.scala:87:24]
wire out_woready_6; // @[RegisterRouter.scala:87:24]
wire out_woready_7; // @[RegisterRouter.scala:87:24]
wire out_woready_8; // @[RegisterRouter.scala:87:24]
wire out_woready_9; // @[RegisterRouter.scala:87:24]
wire out_woready_10; // @[RegisterRouter.scala:87:24]
wire out_woready_11; // @[RegisterRouter.scala:87:24]
wire out_woready_12; // @[RegisterRouter.scala:87:24]
wire out_woready_13; // @[RegisterRouter.scala:87:24]
wire out_woready_14; // @[RegisterRouter.scala:87:24]
wire out_woready_15; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask = |_out_rimask_T; // @[RegisterRouter.scala:87:24]
wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire out_romask = |_out_romask_T; // @[RegisterRouter.scala:87:24]
wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24]
wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_9 = out_f_wivalid; // @[RegisterRouter.scala:87:24]
wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24]
wire _out_T_10 = out_f_woready; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire _out_txq_io_enq_valid_T = ~quash; // @[RegMapFIFO.scala:11:21, :18:33]
wire _out_txq_io_enq_valid_T_1 = out_f_woready & _out_txq_io_enq_valid_T; // @[RegisterRouter.scala:87:24]
wire _out_T_11 = ~out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_12 = ~out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_13 = ~out_romask; // @[RegisterRouter.scala:87:24]
wire _out_T_14 = ~out_womask; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_rimask_T_1 = out_frontMask[30:8]; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_wimask_T_1 = out_frontMask[30:8]; // @[RegisterRouter.scala:87:24]
wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24]
wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_romask_T_1 = out_backMask[30:8]; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_womask_T_1 = out_backMask[30:8]; // @[RegisterRouter.scala:87:24]
wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24]
wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_18 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_19 = out_f_roready_1; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_T_17 = out_front_bits_data[30:8]; // @[RegisterRouter.scala:87:24]
wire _out_T_20 = ~out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_21 = ~out_wimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_22 = ~out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_23 = ~out_womask_1; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_2 = out_frontMask[31]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_2 = out_frontMask[31]; // @[RegisterRouter.scala:87:24]
wire out_rimask_2 = _out_rimask_T_2; // @[RegisterRouter.scala:87:24]
wire out_wimask_2 = _out_wimask_T_2; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_2 = out_backMask[31]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_2 = out_backMask[31]; // @[RegisterRouter.scala:87:24]
wire out_romask_2 = _out_romask_T_2; // @[RegisterRouter.scala:87:24]
wire out_womask_2 = _out_womask_T_2; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_27 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_28 = out_f_roready_2; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24]
wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_26 = out_front_bits_data[31]; // @[RegisterRouter.scala:87:24]
wire _out_quash_T = _out_T_26; // @[RegisterRouter.scala:87:24]
assign _out_quash_T_1 = out_f_woready_2 & _out_quash_T; // @[RegisterRouter.scala:87:24]
assign quash = _out_quash_T_1; // @[RegMapFIFO.scala:11:21, :26:26]
wire _out_T_29 = ~out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_30 = ~out_wimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_31 = ~out_romask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_32 = ~out_womask_2; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1 = {~_txq_io_enq_ready, 31'h0}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_33 = out_prepend_1; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_34 = _out_T_33; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_2 = _out_T_34; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_3 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_3 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24]
wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24]
wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_3 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_3 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24]
wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24]
wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_36 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_37 = out_f_roready_3; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24]
wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_35 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire _out_T_38 = ~out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_39 = ~out_wimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_40 = ~out_romask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_41 = ~out_womask_3; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_2 = {_rxq_io_deq_bits, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_42 = out_prepend_2; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_43 = _out_T_42; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_3 = _out_T_43; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_rimask_T_4 = out_frontMask[62:40]; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_wimask_T_4 = out_frontMask[62:40]; // @[RegisterRouter.scala:87:24]
wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24]
wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_romask_T_4 = out_backMask[62:40]; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_womask_T_4 = out_backMask[62:40]; // @[RegisterRouter.scala:87:24]
wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24]
wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_45 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24]
wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_46 = out_f_roready_4; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24]
wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_T_44 = out_front_bits_data[62:40]; // @[RegisterRouter.scala:87:24]
wire _out_T_47 = ~out_rimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_48 = ~out_wimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_49 = ~out_romask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_50 = ~out_womask_4; // @[RegisterRouter.scala:87:24]
wire [40:0] out_prepend_3 = {1'h0, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24]
wire [62:0] _out_T_51 = {22'h0, out_prepend_3}; // @[RegisterRouter.scala:87:24]
wire [62:0] _out_T_52 = _out_T_51; // @[RegisterRouter.scala:87:24]
wire [62:0] _out_prepend_T_4 = _out_T_52; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_5 = out_frontMask[63]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_5 = out_frontMask[63]; // @[RegisterRouter.scala:87:24]
wire out_rimask_5 = _out_rimask_T_5; // @[RegisterRouter.scala:87:24]
wire out_wimask_5 = _out_wimask_T_5; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_5 = out_backMask[63]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_5 = out_backMask[63]; // @[RegisterRouter.scala:87:24]
wire out_romask_5 = _out_romask_T_5; // @[RegisterRouter.scala:87:24]
wire out_womask_5 = _out_womask_T_5; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_54 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24]
wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_55 = out_f_roready_5; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24]
wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_53 = out_front_bits_data[63]; // @[RegisterRouter.scala:87:24]
wire _out_T_56 = ~out_rimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_57 = ~out_wimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_58 = ~out_romask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_59 = ~out_womask_5; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_4 = {~_rxq_io_deq_valid, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_60 = out_prepend_4; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_61 = _out_T_60; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_1_0 = _out_T_61; // @[MuxLiteral.scala:49:48]
wire _out_rimask_T_6 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_6 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_11 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_11 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire out_rimask_6 = _out_rimask_T_6; // @[RegisterRouter.scala:87:24]
wire out_wimask_6 = _out_wimask_T_6; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_6 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_6 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_11 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_11 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire out_romask_6 = _out_romask_T_6; // @[RegisterRouter.scala:87:24]
wire out_womask_6 = _out_womask_T_6; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_63 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24]
wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_64 = out_f_roready_6; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_65 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24]
wire out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_66 = out_f_woready_6; // @[RegisterRouter.scala:87:24]
wire _out_T_62 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24]
wire _out_T_117 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24]
wire _out_T_67 = ~out_rimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_68 = ~out_wimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_69 = ~out_romask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_70 = ~out_womask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_72 = _out_T_71; // @[RegisterRouter.scala:87:24]
wire _out_prepend_T_5 = _out_T_72; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_7 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_7 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_12 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_12 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire out_rimask_7 = _out_rimask_T_7; // @[RegisterRouter.scala:87:24]
wire out_wimask_7 = _out_wimask_T_7; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_7 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_7 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_12 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_12 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire out_romask_7 = _out_romask_T_7; // @[RegisterRouter.scala:87:24]
wire out_womask_7 = _out_womask_T_7; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_74 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24]
wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_75 = out_f_roready_7; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_76 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24]
wire out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_77 = out_f_woready_7; // @[RegisterRouter.scala:87:24]
wire _out_T_73 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24]
wire _out_T_128 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24]
wire _out_T_78 = ~out_rimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_79 = ~out_wimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_80 = ~out_romask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_81 = ~out_womask_7; // @[RegisterRouter.scala:87:24]
wire [1:0] out_prepend_5 = {nstop, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_82 = out_prepend_5; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_83 = _out_T_82; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_rimask_T_8 = out_frontMask[19:16]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_wimask_T_8 = out_frontMask[19:16]; // @[RegisterRouter.scala:87:24]
wire out_rimask_8 = |_out_rimask_T_8; // @[RegisterRouter.scala:87:24]
wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_romask_T_8 = out_backMask[19:16]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_womask_T_8 = out_backMask[19:16]; // @[RegisterRouter.scala:87:24]
wire out_romask_8 = |_out_romask_T_8; // @[RegisterRouter.scala:87:24]
wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_85 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24]
wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_86 = out_f_roready_8; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_87 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24]
wire out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_88 = out_f_woready_8; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_84 = out_front_bits_data[19:16]; // @[RegisterRouter.scala:87:24]
wire _out_T_89 = ~out_rimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_90 = ~out_wimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_91 = ~out_romask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_92 = ~out_womask_8; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_6 = {14'h0, _out_T_83}; // @[RegisterRouter.scala:87:24]
wire [19:0] out_prepend_6 = {txwm, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24]
wire [19:0] _out_T_93 = out_prepend_6; // @[RegisterRouter.scala:87:24]
wire [19:0] _out_T_94 = _out_T_93; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_9 = out_frontMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_9 = out_frontMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_13 = out_frontMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_13 = out_frontMask[32]; // @[RegisterRouter.scala:87:24]
wire out_rimask_9 = _out_rimask_T_9; // @[RegisterRouter.scala:87:24]
wire out_wimask_9 = _out_wimask_T_9; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_9 = out_backMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_9 = out_backMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_13 = out_backMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_13 = out_backMask[32]; // @[RegisterRouter.scala:87:24]
wire out_romask_9 = _out_romask_T_9; // @[RegisterRouter.scala:87:24]
wire out_womask_9 = _out_womask_T_9; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_96 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24]
wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_97 = out_f_roready_9; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_98 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24]
wire out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_99 = out_f_woready_9; // @[RegisterRouter.scala:87:24]
wire _out_T_95 = out_front_bits_data[32]; // @[RegisterRouter.scala:87:24]
wire _out_T_139 = out_front_bits_data[32]; // @[RegisterRouter.scala:87:24]
wire _out_T_100 = ~out_rimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_101 = ~out_wimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_102 = ~out_romask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_103 = ~out_womask_9; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_7 = {12'h0, _out_T_94}; // @[RegisterRouter.scala:87:24]
wire [32:0] out_prepend_7 = {rxen, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24]
wire [32:0] _out_T_104 = out_prepend_7; // @[RegisterRouter.scala:87:24]
wire [32:0] _out_T_105 = _out_T_104; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_rimask_T_10 = out_frontMask[51:48]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_wimask_T_10 = out_frontMask[51:48]; // @[RegisterRouter.scala:87:24]
wire out_rimask_10 = |_out_rimask_T_10; // @[RegisterRouter.scala:87:24]
wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_romask_T_10 = out_backMask[51:48]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_womask_T_10 = out_backMask[51:48]; // @[RegisterRouter.scala:87:24]
wire out_romask_10 = |_out_romask_T_10; // @[RegisterRouter.scala:87:24]
wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_107 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24]
wire out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_108 = out_f_roready_10; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_109 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24]
wire out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_110 = out_f_woready_10; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_106 = out_front_bits_data[51:48]; // @[RegisterRouter.scala:87:24]
wire _out_T_111 = ~out_rimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_112 = ~out_wimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_113 = ~out_romask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_114 = ~out_womask_10; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_8 = {15'h0, _out_T_105}; // @[RegisterRouter.scala:87:24]
wire [51:0] out_prepend_8 = {rxwm, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24]
wire [51:0] _out_T_115 = out_prepend_8; // @[RegisterRouter.scala:87:24]
wire [51:0] _out_T_116 = _out_T_115; // @[RegisterRouter.scala:87:24]
wire out_rimask_11 = _out_rimask_T_11; // @[RegisterRouter.scala:87:24]
wire out_wimask_11 = _out_wimask_T_11; // @[RegisterRouter.scala:87:24]
wire out_romask_11 = _out_romask_T_11; // @[RegisterRouter.scala:87:24]
wire out_womask_11 = _out_womask_T_11; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_118 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24]
wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_119 = out_f_roready_11; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_120 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24]
wire out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_121 = out_f_woready_11; // @[RegisterRouter.scala:87:24]
wire _out_T_122 = ~out_rimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_123 = ~out_wimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_124 = ~out_romask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_125 = ~out_womask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_127 = _out_T_126; // @[RegisterRouter.scala:87:24]
wire _out_prepend_T_9 = _out_T_127; // @[RegisterRouter.scala:87:24]
wire out_rimask_12 = _out_rimask_T_12; // @[RegisterRouter.scala:87:24]
wire out_wimask_12 = _out_wimask_T_12; // @[RegisterRouter.scala:87:24]
wire out_romask_12 = _out_romask_T_12; // @[RegisterRouter.scala:87:24]
wire out_womask_12 = _out_womask_T_12; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_129 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24]
wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_130 = out_f_roready_12; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_131 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24]
wire out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_132 = out_f_woready_12; // @[RegisterRouter.scala:87:24]
wire _out_T_133 = ~out_rimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_134 = ~out_wimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_135 = ~out_romask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_136 = ~out_womask_12; // @[RegisterRouter.scala:87:24]
wire [1:0] out_prepend_9 = {ie_rxwm, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_137 = out_prepend_9; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_138 = _out_T_137; // @[RegisterRouter.scala:87:24]
wire out_rimask_13 = _out_rimask_T_13; // @[RegisterRouter.scala:87:24]
wire out_wimask_13 = _out_wimask_T_13; // @[RegisterRouter.scala:87:24]
wire out_romask_13 = _out_romask_T_13; // @[RegisterRouter.scala:87:24]
wire out_womask_13 = _out_womask_T_13; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_140 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24]
wire out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_141 = out_f_roready_13; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24]
wire out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_142 = ~out_rimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_143 = ~out_wimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_144 = ~out_romask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_145 = ~out_womask_13; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_10 = {30'h0, _out_T_138}; // @[RegisterRouter.scala:87:24]
wire [32:0] out_prepend_10 = {ip_txwm, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24]
wire [32:0] _out_T_146 = out_prepend_10; // @[RegisterRouter.scala:87:24]
wire [32:0] _out_T_147 = _out_T_146; // @[RegisterRouter.scala:87:24]
wire [32:0] _out_prepend_T_11 = _out_T_147; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_14 = out_frontMask[33]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_14 = out_frontMask[33]; // @[RegisterRouter.scala:87:24]
wire out_rimask_14 = _out_rimask_T_14; // @[RegisterRouter.scala:87:24]
wire out_wimask_14 = _out_wimask_T_14; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_14 = out_backMask[33]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_14 = out_backMask[33]; // @[RegisterRouter.scala:87:24]
wire out_romask_14 = _out_romask_T_14; // @[RegisterRouter.scala:87:24]
wire out_womask_14 = _out_womask_T_14; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_149 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24]
wire out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_150 = out_f_roready_14; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24]
wire out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_148 = out_front_bits_data[33]; // @[RegisterRouter.scala:87:24]
wire _out_T_151 = ~out_rimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_152 = ~out_wimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_153 = ~out_romask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_154 = ~out_womask_14; // @[RegisterRouter.scala:87:24]
wire [33:0] out_prepend_11 = {ip_rxwm, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24]
wire [33:0] _out_T_155 = out_prepend_11; // @[RegisterRouter.scala:87:24]
wire [33:0] _out_T_156 = _out_T_155; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_rimask_T_15 = out_frontMask[15:0]; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_wimask_T_15 = out_frontMask[15:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask_15 = |_out_rimask_T_15; // @[RegisterRouter.scala:87:24]
wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_romask_T_15 = out_backMask[15:0]; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_womask_T_15 = out_backMask[15:0]; // @[RegisterRouter.scala:87:24]
wire out_romask_15 = |_out_romask_T_15; // @[RegisterRouter.scala:87:24]
wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_158 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24]
wire out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_159 = out_f_roready_15; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_160 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24]
wire out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_161 = out_f_woready_15; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_157 = out_front_bits_data[15:0]; // @[RegisterRouter.scala:87:24]
wire _out_T_162 = ~out_rimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_163 = ~out_wimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_164 = ~out_romask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_165 = ~out_womask_15; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_167 = _out_T_166; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24]
wire [1:0] out_iindex = {_out_iindex_T_1, _out_iindex_T}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_oindex = {_out_oindex_T_1, _out_oindex_T}; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35]
wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35]
wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35]
wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35]
wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35]
wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35]
wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35]
wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35]
wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35]
wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35]
wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24]
wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_4 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_5 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_2; // @[RegisterRouter.scala:87:24]
assign out_rivalid_6 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_7 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_8 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_9 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_10 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_8 = ~_out_T_2; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_4; // @[RegisterRouter.scala:87:24]
assign out_rivalid_11 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_rivalid_12 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_rivalid_13 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_rivalid_14 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_12 = ~_out_T_4; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_15 = _out_rifireMux_T_14 & _out_T_6; // @[RegisterRouter.scala:87:24]
assign out_rivalid_15 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_16 = ~_out_T_6; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_4 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_5 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_2; // @[RegisterRouter.scala:87:24]
assign out_wivalid_6 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_7 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_8 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_9 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_10 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_9 = ~_out_T_2; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_11 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_wivalid_12 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_wivalid_13 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_wivalid_14 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_13 = ~_out_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_16 = _out_wifireMux_T_15 & _out_T_6; // @[RegisterRouter.scala:87:24]
assign out_wivalid_15 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_17 = ~_out_T_6; // @[RegisterRouter.scala:87:24]
wire _GEN_3 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_4 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_5 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_6 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_7 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_8 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_9 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_10 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_8 = ~_out_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_5; // @[RegisterRouter.scala:87:24]
assign out_roready_11 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_roready_12 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_roready_13 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_roready_14 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_12 = ~_out_T_5; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_15 = _out_rofireMux_T_14 & _out_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_15 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_16 = ~_out_T_7; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_4 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_5 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_3; // @[RegisterRouter.scala:87:24]
assign out_woready_6 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_7 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_8 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_9 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_10 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_9 = ~_out_T_3; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_5; // @[RegisterRouter.scala:87:24]
assign out_woready_11 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_woready_12 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_woready_13 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_woready_14 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_13 = ~_out_T_5; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_16 = _out_wofireMux_T_15 & _out_T_7; // @[RegisterRouter.scala:87:24]
assign out_woready_15 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_17 = ~_out_T_7; // @[RegisterRouter.scala:87:24]
assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24]
assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24]
assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24]
assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24]
wire [3:0] _GEN_4 = {{_out_out_bits_data_WIRE_3}, {_out_out_bits_data_WIRE_2}, {_out_out_bits_data_WIRE_1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}]
wire _out_out_bits_data_T_1 = _GEN_4[out_oindex]; // @[MuxLiteral.scala:49:10]
wire [63:0] _out_out_bits_data_WIRE_1_1 = {12'h0, _out_T_116}; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_1_2 = {30'h0, _out_T_156}; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_1_3 = {48'h0, _out_T_167}; // @[MuxLiteral.scala:49:48]
wire [3:0][63:0] _GEN_5 = {{_out_out_bits_data_WIRE_1_3}, {_out_out_bits_data_WIRE_1_2}, {_out_out_bits_data_WIRE_1_1}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}]
wire [63:0] _out_out_bits_data_T_3 = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10]
assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10]
assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
assign controlNodeIn_d_bits_size = controlNodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign controlNodeIn_d_bits_source = controlNodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign controlNodeIn_d_bits_opcode = {2'h0, _controlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}]
always @(posedge clock) begin // @[UART.scala:127:25]
if (reset) begin // @[UART.scala:127:25]
div <= 16'h10F4; // @[UART.scala:135:20]
txen <= 1'h0; // @[UART.scala:141:21]
rxen <= 1'h0; // @[UART.scala:142:21]
txwm <= 4'h0; // @[UART.scala:149:21]
rxwm <= 4'h0; // @[UART.scala:150:21]
nstop <= 1'h0; // @[UART.scala:151:22]
ie_rxwm <= 1'h0; // @[UART.scala:186:19]
ie_txwm <= 1'h0; // @[UART.scala:186:19]
end
else begin // @[UART.scala:127:25]
if (out_f_woready_15) // @[RegisterRouter.scala:87:24]
div <= _out_T_157; // @[RegisterRouter.scala:87:24]
if (out_f_woready_6) // @[RegisterRouter.scala:87:24]
txen <= _out_T_62; // @[RegisterRouter.scala:87:24]
if (out_f_woready_9) // @[RegisterRouter.scala:87:24]
rxen <= _out_T_95; // @[RegisterRouter.scala:87:24]
if (out_f_woready_8) // @[RegisterRouter.scala:87:24]
txwm <= _out_T_84; // @[RegisterRouter.scala:87:24]
if (out_f_woready_10) // @[RegisterRouter.scala:87:24]
rxwm <= _out_T_106; // @[RegisterRouter.scala:87:24]
if (out_f_woready_7) // @[RegisterRouter.scala:87:24]
nstop <= _out_T_73; // @[RegisterRouter.scala:87:24]
if (out_f_woready_12) // @[RegisterRouter.scala:87:24]
ie_rxwm <= _out_T_128; // @[RegisterRouter.scala:87:24]
if (out_f_woready_11) // @[RegisterRouter.scala:87:24]
ie_txwm <= _out_T_117; // @[RegisterRouter.scala:87:24]
end
always @(posedge)
IntSyncCrossingSource_n1x1_4 intsource ( // @[Crossing.scala:29:31]
.clock (clock),
.reset (reset),
.auto_in_0 (intnodeOut_0), // @[MixedNode.scala:542:17]
.auto_out_sync_0 (intXingIn_sync_0)
); // @[Crossing.scala:29:31]
TLMonitor_40 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (controlNodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (controlNodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (controlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (controlNodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (controlNodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (controlNodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (controlNodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (controlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (controlNodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (controlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (controlNodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (controlNodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (controlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (controlNodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (controlNodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (controlNodeIn_d_bits_data) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
UARTTx txm ( // @[UART.scala:129:19]
.clock (clock),
.reset (reset),
.io_en (txen), // @[UART.scala:141:21]
.io_in_ready (_txm_io_in_ready),
.io_in_valid (_txq_io_deq_valid), // @[UART.scala:130:19]
.io_in_bits (_txq_io_deq_bits), // @[UART.scala:130:19]
.io_out (ioNodeOut_txd),
.io_div (div), // @[UART.scala:135:20]
.io_nstop (nstop), // @[UART.scala:151:22]
.io_tx_busy (_txm_io_tx_busy)
); // @[UART.scala:129:19]
Queue8_UInt8 txq ( // @[UART.scala:130:19]
.clock (clock),
.reset (reset),
.io_enq_ready (_txq_io_enq_ready),
.io_enq_valid (_out_txq_io_enq_valid_T_1), // @[RegMapFIFO.scala:18:30]
.io_enq_bits (_out_T_8), // @[RegisterRouter.scala:87:24]
.io_deq_ready (_txm_io_in_ready), // @[UART.scala:129:19]
.io_deq_valid (_txq_io_deq_valid),
.io_deq_bits (_txq_io_deq_bits),
.io_count (_txq_io_count)
); // @[UART.scala:130:19]
UARTRx rxm ( // @[UART.scala:132:19]
.clock (clock),
.reset (reset),
.io_en (rxen), // @[UART.scala:142:21]
.io_in (ioNodeOut_rxd), // @[MixedNode.scala:542:17]
.io_out_valid (_rxm_io_out_valid),
.io_out_bits (_rxm_io_out_bits),
.io_div (div) // @[UART.scala:135:20]
); // @[UART.scala:132:19]
Queue8_UInt8_1 rxq ( // @[UART.scala:133:19]
.clock (clock),
.reset (reset),
.io_enq_valid (_rxm_io_out_valid), // @[UART.scala:132:19]
.io_enq_bits (_rxm_io_out_bits), // @[UART.scala:132:19]
.io_deq_ready (out_f_roready_3), // @[RegisterRouter.scala:87:24]
.io_deq_valid (_rxq_io_deq_valid),
.io_deq_bits (_rxq_io_deq_bits),
.io_count (_rxq_io_count)
); // @[UART.scala:133:19]
assign auto_int_xing_out_sync_0 = auto_int_xing_out_sync_0_0; // @[UART.scala:127:25]
assign auto_control_xing_in_a_ready = auto_control_xing_in_a_ready_0; // @[UART.scala:127:25]
assign auto_control_xing_in_d_valid = auto_control_xing_in_d_valid_0; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_opcode = auto_control_xing_in_d_bits_opcode_0; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_size = auto_control_xing_in_d_bits_size_0; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_source = auto_control_xing_in_d_bits_source_0; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_data = auto_control_xing_in_d_bits_data_0; // @[UART.scala:127:25]
assign auto_io_out_txd = auto_io_out_txd_0; // @[UART.scala:127:25]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_100 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[30]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
connect _source_ok_WIRE[9], _source_ok_T_29
connect _source_ok_WIRE[10], _source_ok_T_30
connect _source_ok_WIRE[11], _source_ok_T_31
connect _source_ok_WIRE[12], _source_ok_T_32
connect _source_ok_WIRE[13], _source_ok_T_33
connect _source_ok_WIRE[14], _source_ok_T_34
connect _source_ok_WIRE[15], _source_ok_T_35
connect _source_ok_WIRE[16], _source_ok_T_36
connect _source_ok_WIRE[17], _source_ok_T_37
connect _source_ok_WIRE[18], _source_ok_T_38
connect _source_ok_WIRE[19], _source_ok_T_39
connect _source_ok_WIRE[20], _source_ok_T_40
connect _source_ok_WIRE[21], _source_ok_T_41
connect _source_ok_WIRE[22], _source_ok_T_42
connect _source_ok_WIRE[23], _source_ok_T_43
connect _source_ok_WIRE[24], _source_ok_T_44
connect _source_ok_WIRE[25], _source_ok_T_45
connect _source_ok_WIRE[26], _source_ok_T_46
connect _source_ok_WIRE[27], _source_ok_T_47
connect _source_ok_WIRE[28], _source_ok_T_48
connect _source_ok_WIRE[29], _source_ok_T_49
node _source_ok_T_50 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[2])
node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[3])
node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[4])
node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[5])
node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[6])
node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[7])
node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[8])
node _source_ok_T_58 = or(_source_ok_T_57, _source_ok_WIRE[9])
node _source_ok_T_59 = or(_source_ok_T_58, _source_ok_WIRE[10])
node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE[11])
node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE[12])
node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE[13])
node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[14])
node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[15])
node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[16])
node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[17])
node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[18])
node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[19])
node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[20])
node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[21])
node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[22])
node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[23])
node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[24])
node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[25])
node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[26])
node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[27])
node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[28])
node source_ok = or(_source_ok_T_77, _source_ok_WIRE[29])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_99 = cvt(_T_98)
node _T_100 = and(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = asSInt(_T_100)
node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = or(_T_97, _T_102)
node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_105 = eq(_T_104, UInt<1>(0h0))
node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<1>(0h0)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = or(_T_105, _T_110)
node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_113 = eq(_T_112, UInt<1>(0h0))
node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_115 = cvt(_T_114)
node _T_116 = and(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = asSInt(_T_116)
node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = or(_T_113, _T_118)
node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_123 = cvt(_T_122)
node _T_124 = and(_T_123, asSInt(UInt<1>(0h0)))
node _T_125 = asSInt(_T_124)
node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0)))
node _T_127 = or(_T_121, _T_126)
node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_129 = eq(_T_128, UInt<1>(0h0))
node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_131 = cvt(_T_130)
node _T_132 = and(_T_131, asSInt(UInt<1>(0h0)))
node _T_133 = asSInt(_T_132)
node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0)))
node _T_135 = or(_T_129, _T_134)
node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_137 = eq(_T_136, UInt<1>(0h0))
node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_139 = cvt(_T_138)
node _T_140 = and(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = asSInt(_T_140)
node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0)))
node _T_143 = or(_T_137, _T_142)
node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_145 = eq(_T_144, UInt<1>(0h0))
node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_147 = cvt(_T_146)
node _T_148 = and(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = asSInt(_T_148)
node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = or(_T_145, _T_150)
node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<1>(0h0)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = or(_T_153, _T_158)
node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_161 = eq(_T_160, UInt<1>(0h0))
node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_163 = cvt(_T_162)
node _T_164 = and(_T_163, asSInt(UInt<1>(0h0)))
node _T_165 = asSInt(_T_164)
node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0)))
node _T_167 = or(_T_161, _T_166)
node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_171 = cvt(_T_170)
node _T_172 = and(_T_171, asSInt(UInt<1>(0h0)))
node _T_173 = asSInt(_T_172)
node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0)))
node _T_175 = or(_T_169, _T_174)
node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_177 = eq(_T_176, UInt<1>(0h0))
node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_179 = cvt(_T_178)
node _T_180 = and(_T_179, asSInt(UInt<1>(0h0)))
node _T_181 = asSInt(_T_180)
node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0)))
node _T_183 = or(_T_177, _T_182)
node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_185 = eq(_T_184, UInt<1>(0h0))
node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_187 = cvt(_T_186)
node _T_188 = and(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = asSInt(_T_188)
node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0)))
node _T_191 = or(_T_185, _T_190)
node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_193 = eq(_T_192, UInt<1>(0h0))
node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<1>(0h0)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = or(_T_193, _T_198)
node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_201 = eq(_T_200, UInt<1>(0h0))
node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_203 = cvt(_T_202)
node _T_204 = and(_T_203, asSInt(UInt<1>(0h0)))
node _T_205 = asSInt(_T_204)
node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0)))
node _T_207 = or(_T_201, _T_206)
node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_209 = eq(_T_208, UInt<1>(0h0))
node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_211 = cvt(_T_210)
node _T_212 = and(_T_211, asSInt(UInt<1>(0h0)))
node _T_213 = asSInt(_T_212)
node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0)))
node _T_215 = or(_T_209, _T_214)
node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_217 = eq(_T_216, UInt<1>(0h0))
node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_219 = cvt(_T_218)
node _T_220 = and(_T_219, asSInt(UInt<1>(0h0)))
node _T_221 = asSInt(_T_220)
node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0)))
node _T_223 = or(_T_217, _T_222)
node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_227 = cvt(_T_226)
node _T_228 = and(_T_227, asSInt(UInt<1>(0h0)))
node _T_229 = asSInt(_T_228)
node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0)))
node _T_231 = or(_T_225, _T_230)
node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_233 = eq(_T_232, UInt<1>(0h0))
node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_235 = cvt(_T_234)
node _T_236 = and(_T_235, asSInt(UInt<1>(0h0)))
node _T_237 = asSInt(_T_236)
node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0)))
node _T_239 = or(_T_233, _T_238)
node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_243 = cvt(_T_242)
node _T_244 = and(_T_243, asSInt(UInt<1>(0h0)))
node _T_245 = asSInt(_T_244)
node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0)))
node _T_247 = or(_T_241, _T_246)
node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_249 = eq(_T_248, UInt<1>(0h0))
node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_251 = cvt(_T_250)
node _T_252 = and(_T_251, asSInt(UInt<1>(0h0)))
node _T_253 = asSInt(_T_252)
node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0)))
node _T_255 = or(_T_249, _T_254)
node _T_256 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_257 = eq(_T_256, UInt<1>(0h0))
node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_259 = cvt(_T_258)
node _T_260 = and(_T_259, asSInt(UInt<1>(0h0)))
node _T_261 = asSInt(_T_260)
node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0)))
node _T_263 = or(_T_257, _T_262)
node _T_264 = and(_T_11, _T_24)
node _T_265 = and(_T_264, _T_37)
node _T_266 = and(_T_265, _T_50)
node _T_267 = and(_T_266, _T_63)
node _T_268 = and(_T_267, _T_71)
node _T_269 = and(_T_268, _T_79)
node _T_270 = and(_T_269, _T_87)
node _T_271 = and(_T_270, _T_95)
node _T_272 = and(_T_271, _T_103)
node _T_273 = and(_T_272, _T_111)
node _T_274 = and(_T_273, _T_119)
node _T_275 = and(_T_274, _T_127)
node _T_276 = and(_T_275, _T_135)
node _T_277 = and(_T_276, _T_143)
node _T_278 = and(_T_277, _T_151)
node _T_279 = and(_T_278, _T_159)
node _T_280 = and(_T_279, _T_167)
node _T_281 = and(_T_280, _T_175)
node _T_282 = and(_T_281, _T_183)
node _T_283 = and(_T_282, _T_191)
node _T_284 = and(_T_283, _T_199)
node _T_285 = and(_T_284, _T_207)
node _T_286 = and(_T_285, _T_215)
node _T_287 = and(_T_286, _T_223)
node _T_288 = and(_T_287, _T_231)
node _T_289 = and(_T_288, _T_239)
node _T_290 = and(_T_289, _T_247)
node _T_291 = and(_T_290, _T_255)
node _T_292 = and(_T_291, _T_263)
node _T_293 = asUInt(reset)
node _T_294 = eq(_T_293, UInt<1>(0h0))
when _T_294 :
node _T_295 = eq(_T_292, UInt<1>(0h0))
when _T_295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_292, UInt<1>(0h1), "") : assert_1
node _T_296 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_296 :
node _T_297 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_298 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_299 = and(_T_297, _T_298)
node _T_300 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_301 = shr(io.in.a.bits.source, 2)
node _T_302 = eq(_T_301, UInt<1>(0h0))
node _T_303 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_304 = and(_T_302, _T_303)
node _T_305 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_306 = and(_T_304, _T_305)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_307 = shr(io.in.a.bits.source, 2)
node _T_308 = eq(_T_307, UInt<1>(0h1))
node _T_309 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_310 = and(_T_308, _T_309)
node _T_311 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_312 = and(_T_310, _T_311)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_313 = shr(io.in.a.bits.source, 2)
node _T_314 = eq(_T_313, UInt<2>(0h2))
node _T_315 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_316 = and(_T_314, _T_315)
node _T_317 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_318 = and(_T_316, _T_317)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_319 = shr(io.in.a.bits.source, 2)
node _T_320 = eq(_T_319, UInt<2>(0h3))
node _T_321 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_322 = and(_T_320, _T_321)
node _T_323 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_326 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_330 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_331 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_332 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_333 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_334 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_335 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_337 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_338 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_339 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_340 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_341 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_342 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_343 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_345 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_346 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_347 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_349 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_350 = or(_T_300, _T_306)
node _T_351 = or(_T_350, _T_312)
node _T_352 = or(_T_351, _T_318)
node _T_353 = or(_T_352, _T_324)
node _T_354 = or(_T_353, _T_325)
node _T_355 = or(_T_354, _T_326)
node _T_356 = or(_T_355, _T_327)
node _T_357 = or(_T_356, _T_328)
node _T_358 = or(_T_357, _T_329)
node _T_359 = or(_T_358, _T_330)
node _T_360 = or(_T_359, _T_331)
node _T_361 = or(_T_360, _T_332)
node _T_362 = or(_T_361, _T_333)
node _T_363 = or(_T_362, _T_334)
node _T_364 = or(_T_363, _T_335)
node _T_365 = or(_T_364, _T_336)
node _T_366 = or(_T_365, _T_337)
node _T_367 = or(_T_366, _T_338)
node _T_368 = or(_T_367, _T_339)
node _T_369 = or(_T_368, _T_340)
node _T_370 = or(_T_369, _T_341)
node _T_371 = or(_T_370, _T_342)
node _T_372 = or(_T_371, _T_343)
node _T_373 = or(_T_372, _T_344)
node _T_374 = or(_T_373, _T_345)
node _T_375 = or(_T_374, _T_346)
node _T_376 = or(_T_375, _T_347)
node _T_377 = or(_T_376, _T_348)
node _T_378 = or(_T_377, _T_349)
node _T_379 = and(_T_299, _T_378)
node _T_380 = or(UInt<1>(0h0), _T_379)
node _T_381 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_382 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_383 = cvt(_T_382)
node _T_384 = and(_T_383, asSInt(UInt<13>(0h1000)))
node _T_385 = asSInt(_T_384)
node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0)))
node _T_387 = and(_T_381, _T_386)
node _T_388 = or(UInt<1>(0h0), _T_387)
node _T_389 = and(_T_380, _T_388)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_389, UInt<1>(0h1), "") : assert_2
node _T_393 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_394 = shr(io.in.a.bits.source, 2)
node _T_395 = eq(_T_394, UInt<1>(0h0))
node _T_396 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_397 = and(_T_395, _T_396)
node _T_398 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_399 = and(_T_397, _T_398)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_400 = shr(io.in.a.bits.source, 2)
node _T_401 = eq(_T_400, UInt<1>(0h1))
node _T_402 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_403 = and(_T_401, _T_402)
node _T_404 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_405 = and(_T_403, _T_404)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_406 = shr(io.in.a.bits.source, 2)
node _T_407 = eq(_T_406, UInt<2>(0h2))
node _T_408 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_409 = and(_T_407, _T_408)
node _T_410 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_411 = and(_T_409, _T_410)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_412 = shr(io.in.a.bits.source, 2)
node _T_413 = eq(_T_412, UInt<2>(0h3))
node _T_414 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_415 = and(_T_413, _T_414)
node _T_416 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_419 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_423 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_424 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_425 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_426 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_427 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_428 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_429 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_430 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_431 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_432 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_433 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_434 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_435 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_436 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_437 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_438 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_439 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_440 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_441 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_442 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[30]
connect _WIRE[0], _T_393
connect _WIRE[1], _T_399
connect _WIRE[2], _T_405
connect _WIRE[3], _T_411
connect _WIRE[4], _T_417
connect _WIRE[5], _T_418
connect _WIRE[6], _T_419
connect _WIRE[7], _T_420
connect _WIRE[8], _T_421
connect _WIRE[9], _T_422
connect _WIRE[10], _T_423
connect _WIRE[11], _T_424
connect _WIRE[12], _T_425
connect _WIRE[13], _T_426
connect _WIRE[14], _T_427
connect _WIRE[15], _T_428
connect _WIRE[16], _T_429
connect _WIRE[17], _T_430
connect _WIRE[18], _T_431
connect _WIRE[19], _T_432
connect _WIRE[20], _T_433
connect _WIRE[21], _T_434
connect _WIRE[22], _T_435
connect _WIRE[23], _T_436
connect _WIRE[24], _T_437
connect _WIRE[25], _T_438
connect _WIRE[26], _T_439
connect _WIRE[27], _T_440
connect _WIRE[28], _T_441
connect _WIRE[29], _T_442
node _T_443 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_444 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_445 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_446 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_447 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_448 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_449 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_450 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_451 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_452 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_453 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_454 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_455 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_456 = mux(_WIRE[5], _T_443, UInt<1>(0h0))
node _T_457 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_458 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_459 = mux(_WIRE[8], _T_444, UInt<1>(0h0))
node _T_460 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_461 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_462 = mux(_WIRE[11], _T_445, UInt<1>(0h0))
node _T_463 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_464 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_465 = mux(_WIRE[14], _T_446, UInt<1>(0h0))
node _T_466 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_467 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_468 = mux(_WIRE[17], _T_447, UInt<1>(0h0))
node _T_469 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0))
node _T_470 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0))
node _T_471 = mux(_WIRE[20], _T_448, UInt<1>(0h0))
node _T_472 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0))
node _T_473 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0))
node _T_474 = mux(_WIRE[23], _T_449, UInt<1>(0h0))
node _T_475 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0))
node _T_476 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0))
node _T_477 = mux(_WIRE[26], _T_450, UInt<1>(0h0))
node _T_478 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0))
node _T_479 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0))
node _T_480 = mux(_WIRE[29], UInt<1>(0h0), UInt<1>(0h0))
node _T_481 = or(_T_451, _T_452)
node _T_482 = or(_T_481, _T_453)
node _T_483 = or(_T_482, _T_454)
node _T_484 = or(_T_483, _T_455)
node _T_485 = or(_T_484, _T_456)
node _T_486 = or(_T_485, _T_457)
node _T_487 = or(_T_486, _T_458)
node _T_488 = or(_T_487, _T_459)
node _T_489 = or(_T_488, _T_460)
node _T_490 = or(_T_489, _T_461)
node _T_491 = or(_T_490, _T_462)
node _T_492 = or(_T_491, _T_463)
node _T_493 = or(_T_492, _T_464)
node _T_494 = or(_T_493, _T_465)
node _T_495 = or(_T_494, _T_466)
node _T_496 = or(_T_495, _T_467)
node _T_497 = or(_T_496, _T_468)
node _T_498 = or(_T_497, _T_469)
node _T_499 = or(_T_498, _T_470)
node _T_500 = or(_T_499, _T_471)
node _T_501 = or(_T_500, _T_472)
node _T_502 = or(_T_501, _T_473)
node _T_503 = or(_T_502, _T_474)
node _T_504 = or(_T_503, _T_475)
node _T_505 = or(_T_504, _T_476)
node _T_506 = or(_T_505, _T_477)
node _T_507 = or(_T_506, _T_478)
node _T_508 = or(_T_507, _T_479)
node _T_509 = or(_T_508, _T_480)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_509
node _T_510 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_511 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_512 = and(_T_510, _T_511)
node _T_513 = or(UInt<1>(0h0), _T_512)
node _T_514 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_515 = cvt(_T_514)
node _T_516 = and(_T_515, asSInt(UInt<13>(0h1000)))
node _T_517 = asSInt(_T_516)
node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0)))
node _T_519 = and(_T_513, _T_518)
node _T_520 = or(UInt<1>(0h0), _T_519)
node _T_521 = and(_WIRE_1, _T_520)
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_521, UInt<1>(0h1), "") : assert_3
node _T_525 = asUInt(reset)
node _T_526 = eq(_T_525, UInt<1>(0h0))
when _T_526 :
node _T_527 = eq(source_ok, UInt<1>(0h0))
when _T_527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_528 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_529 = asUInt(reset)
node _T_530 = eq(_T_529, UInt<1>(0h0))
when _T_530 :
node _T_531 = eq(_T_528, UInt<1>(0h0))
when _T_531 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_528, UInt<1>(0h1), "") : assert_5
node _T_532 = asUInt(reset)
node _T_533 = eq(_T_532, UInt<1>(0h0))
when _T_533 :
node _T_534 = eq(is_aligned, UInt<1>(0h0))
when _T_534 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_535 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_536 = asUInt(reset)
node _T_537 = eq(_T_536, UInt<1>(0h0))
when _T_537 :
node _T_538 = eq(_T_535, UInt<1>(0h0))
when _T_538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_535, UInt<1>(0h1), "") : assert_7
node _T_539 = not(io.in.a.bits.mask)
node _T_540 = eq(_T_539, UInt<1>(0h0))
node _T_541 = asUInt(reset)
node _T_542 = eq(_T_541, UInt<1>(0h0))
when _T_542 :
node _T_543 = eq(_T_540, UInt<1>(0h0))
when _T_543 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_540, UInt<1>(0h1), "") : assert_8
node _T_544 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_544, UInt<1>(0h1), "") : assert_9
node _T_548 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_548 :
node _T_549 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_550 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_551 = and(_T_549, _T_550)
node _T_552 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_553 = shr(io.in.a.bits.source, 2)
node _T_554 = eq(_T_553, UInt<1>(0h0))
node _T_555 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_556 = and(_T_554, _T_555)
node _T_557 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_558 = and(_T_556, _T_557)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_559 = shr(io.in.a.bits.source, 2)
node _T_560 = eq(_T_559, UInt<1>(0h1))
node _T_561 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_562 = and(_T_560, _T_561)
node _T_563 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_564 = and(_T_562, _T_563)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_565 = shr(io.in.a.bits.source, 2)
node _T_566 = eq(_T_565, UInt<2>(0h2))
node _T_567 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_568 = and(_T_566, _T_567)
node _T_569 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_570 = and(_T_568, _T_569)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_571 = shr(io.in.a.bits.source, 2)
node _T_572 = eq(_T_571, UInt<2>(0h3))
node _T_573 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_574 = and(_T_572, _T_573)
node _T_575 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_576 = and(_T_574, _T_575)
node _T_577 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_578 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_579 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_580 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_581 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_582 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_583 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_584 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_585 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_586 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_587 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_588 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_589 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_590 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_591 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_592 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_593 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_594 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_595 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_596 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_597 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_598 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_599 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_600 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_601 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_602 = or(_T_552, _T_558)
node _T_603 = or(_T_602, _T_564)
node _T_604 = or(_T_603, _T_570)
node _T_605 = or(_T_604, _T_576)
node _T_606 = or(_T_605, _T_577)
node _T_607 = or(_T_606, _T_578)
node _T_608 = or(_T_607, _T_579)
node _T_609 = or(_T_608, _T_580)
node _T_610 = or(_T_609, _T_581)
node _T_611 = or(_T_610, _T_582)
node _T_612 = or(_T_611, _T_583)
node _T_613 = or(_T_612, _T_584)
node _T_614 = or(_T_613, _T_585)
node _T_615 = or(_T_614, _T_586)
node _T_616 = or(_T_615, _T_587)
node _T_617 = or(_T_616, _T_588)
node _T_618 = or(_T_617, _T_589)
node _T_619 = or(_T_618, _T_590)
node _T_620 = or(_T_619, _T_591)
node _T_621 = or(_T_620, _T_592)
node _T_622 = or(_T_621, _T_593)
node _T_623 = or(_T_622, _T_594)
node _T_624 = or(_T_623, _T_595)
node _T_625 = or(_T_624, _T_596)
node _T_626 = or(_T_625, _T_597)
node _T_627 = or(_T_626, _T_598)
node _T_628 = or(_T_627, _T_599)
node _T_629 = or(_T_628, _T_600)
node _T_630 = or(_T_629, _T_601)
node _T_631 = and(_T_551, _T_630)
node _T_632 = or(UInt<1>(0h0), _T_631)
node _T_633 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_634 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_635 = cvt(_T_634)
node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000)))
node _T_637 = asSInt(_T_636)
node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0)))
node _T_639 = and(_T_633, _T_638)
node _T_640 = or(UInt<1>(0h0), _T_639)
node _T_641 = and(_T_632, _T_640)
node _T_642 = asUInt(reset)
node _T_643 = eq(_T_642, UInt<1>(0h0))
when _T_643 :
node _T_644 = eq(_T_641, UInt<1>(0h0))
when _T_644 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_641, UInt<1>(0h1), "") : assert_10
node _T_645 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_646 = shr(io.in.a.bits.source, 2)
node _T_647 = eq(_T_646, UInt<1>(0h0))
node _T_648 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_649 = and(_T_647, _T_648)
node _T_650 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_651 = and(_T_649, _T_650)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_652 = shr(io.in.a.bits.source, 2)
node _T_653 = eq(_T_652, UInt<1>(0h1))
node _T_654 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_655 = and(_T_653, _T_654)
node _T_656 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_657 = and(_T_655, _T_656)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_658 = shr(io.in.a.bits.source, 2)
node _T_659 = eq(_T_658, UInt<2>(0h2))
node _T_660 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_661 = and(_T_659, _T_660)
node _T_662 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_663 = and(_T_661, _T_662)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_664 = shr(io.in.a.bits.source, 2)
node _T_665 = eq(_T_664, UInt<2>(0h3))
node _T_666 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_667 = and(_T_665, _T_666)
node _T_668 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_669 = and(_T_667, _T_668)
node _T_670 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_671 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_672 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_673 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_674 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_675 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_676 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_677 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_678 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_679 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_680 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_681 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_682 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_683 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_684 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_685 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_686 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_687 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_688 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_689 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_692 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_693 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_694 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[30]
connect _WIRE_2[0], _T_645
connect _WIRE_2[1], _T_651
connect _WIRE_2[2], _T_657
connect _WIRE_2[3], _T_663
connect _WIRE_2[4], _T_669
connect _WIRE_2[5], _T_670
connect _WIRE_2[6], _T_671
connect _WIRE_2[7], _T_672
connect _WIRE_2[8], _T_673
connect _WIRE_2[9], _T_674
connect _WIRE_2[10], _T_675
connect _WIRE_2[11], _T_676
connect _WIRE_2[12], _T_677
connect _WIRE_2[13], _T_678
connect _WIRE_2[14], _T_679
connect _WIRE_2[15], _T_680
connect _WIRE_2[16], _T_681
connect _WIRE_2[17], _T_682
connect _WIRE_2[18], _T_683
connect _WIRE_2[19], _T_684
connect _WIRE_2[20], _T_685
connect _WIRE_2[21], _T_686
connect _WIRE_2[22], _T_687
connect _WIRE_2[23], _T_688
connect _WIRE_2[24], _T_689
connect _WIRE_2[25], _T_690
connect _WIRE_2[26], _T_691
connect _WIRE_2[27], _T_692
connect _WIRE_2[28], _T_693
connect _WIRE_2[29], _T_694
node _T_695 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_696 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_697 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_698 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_699 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_700 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_701 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_702 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_703 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_704 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_705 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_706 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_707 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_708 = mux(_WIRE_2[5], _T_695, UInt<1>(0h0))
node _T_709 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_710 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_711 = mux(_WIRE_2[8], _T_696, UInt<1>(0h0))
node _T_712 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_713 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_714 = mux(_WIRE_2[11], _T_697, UInt<1>(0h0))
node _T_715 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_716 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_717 = mux(_WIRE_2[14], _T_698, UInt<1>(0h0))
node _T_718 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_719 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_720 = mux(_WIRE_2[17], _T_699, UInt<1>(0h0))
node _T_721 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0))
node _T_722 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0))
node _T_723 = mux(_WIRE_2[20], _T_700, UInt<1>(0h0))
node _T_724 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0))
node _T_725 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0))
node _T_726 = mux(_WIRE_2[23], _T_701, UInt<1>(0h0))
node _T_727 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0))
node _T_728 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0))
node _T_729 = mux(_WIRE_2[26], _T_702, UInt<1>(0h0))
node _T_730 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0))
node _T_731 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0))
node _T_732 = mux(_WIRE_2[29], UInt<1>(0h0), UInt<1>(0h0))
node _T_733 = or(_T_703, _T_704)
node _T_734 = or(_T_733, _T_705)
node _T_735 = or(_T_734, _T_706)
node _T_736 = or(_T_735, _T_707)
node _T_737 = or(_T_736, _T_708)
node _T_738 = or(_T_737, _T_709)
node _T_739 = or(_T_738, _T_710)
node _T_740 = or(_T_739, _T_711)
node _T_741 = or(_T_740, _T_712)
node _T_742 = or(_T_741, _T_713)
node _T_743 = or(_T_742, _T_714)
node _T_744 = or(_T_743, _T_715)
node _T_745 = or(_T_744, _T_716)
node _T_746 = or(_T_745, _T_717)
node _T_747 = or(_T_746, _T_718)
node _T_748 = or(_T_747, _T_719)
node _T_749 = or(_T_748, _T_720)
node _T_750 = or(_T_749, _T_721)
node _T_751 = or(_T_750, _T_722)
node _T_752 = or(_T_751, _T_723)
node _T_753 = or(_T_752, _T_724)
node _T_754 = or(_T_753, _T_725)
node _T_755 = or(_T_754, _T_726)
node _T_756 = or(_T_755, _T_727)
node _T_757 = or(_T_756, _T_728)
node _T_758 = or(_T_757, _T_729)
node _T_759 = or(_T_758, _T_730)
node _T_760 = or(_T_759, _T_731)
node _T_761 = or(_T_760, _T_732)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_761
node _T_762 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_763 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_764 = and(_T_762, _T_763)
node _T_765 = or(UInt<1>(0h0), _T_764)
node _T_766 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_767 = cvt(_T_766)
node _T_768 = and(_T_767, asSInt(UInt<13>(0h1000)))
node _T_769 = asSInt(_T_768)
node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0)))
node _T_771 = and(_T_765, _T_770)
node _T_772 = or(UInt<1>(0h0), _T_771)
node _T_773 = and(_WIRE_3, _T_772)
node _T_774 = asUInt(reset)
node _T_775 = eq(_T_774, UInt<1>(0h0))
when _T_775 :
node _T_776 = eq(_T_773, UInt<1>(0h0))
when _T_776 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_773, UInt<1>(0h1), "") : assert_11
node _T_777 = asUInt(reset)
node _T_778 = eq(_T_777, UInt<1>(0h0))
when _T_778 :
node _T_779 = eq(source_ok, UInt<1>(0h0))
when _T_779 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_780 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_781 = asUInt(reset)
node _T_782 = eq(_T_781, UInt<1>(0h0))
when _T_782 :
node _T_783 = eq(_T_780, UInt<1>(0h0))
when _T_783 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_780, UInt<1>(0h1), "") : assert_13
node _T_784 = asUInt(reset)
node _T_785 = eq(_T_784, UInt<1>(0h0))
when _T_785 :
node _T_786 = eq(is_aligned, UInt<1>(0h0))
when _T_786 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_787 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_788 = asUInt(reset)
node _T_789 = eq(_T_788, UInt<1>(0h0))
when _T_789 :
node _T_790 = eq(_T_787, UInt<1>(0h0))
when _T_790 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_787, UInt<1>(0h1), "") : assert_15
node _T_791 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_792 = asUInt(reset)
node _T_793 = eq(_T_792, UInt<1>(0h0))
when _T_793 :
node _T_794 = eq(_T_791, UInt<1>(0h0))
when _T_794 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_791, UInt<1>(0h1), "") : assert_16
node _T_795 = not(io.in.a.bits.mask)
node _T_796 = eq(_T_795, UInt<1>(0h0))
node _T_797 = asUInt(reset)
node _T_798 = eq(_T_797, UInt<1>(0h0))
when _T_798 :
node _T_799 = eq(_T_796, UInt<1>(0h0))
when _T_799 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_796, UInt<1>(0h1), "") : assert_17
node _T_800 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_801 = asUInt(reset)
node _T_802 = eq(_T_801, UInt<1>(0h0))
when _T_802 :
node _T_803 = eq(_T_800, UInt<1>(0h0))
when _T_803 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_800, UInt<1>(0h1), "") : assert_18
node _T_804 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_804 :
node _T_805 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_806 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_807 = and(_T_805, _T_806)
node _T_808 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_809 = shr(io.in.a.bits.source, 2)
node _T_810 = eq(_T_809, UInt<1>(0h0))
node _T_811 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_812 = and(_T_810, _T_811)
node _T_813 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_814 = and(_T_812, _T_813)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_815 = shr(io.in.a.bits.source, 2)
node _T_816 = eq(_T_815, UInt<1>(0h1))
node _T_817 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_818 = and(_T_816, _T_817)
node _T_819 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_820 = and(_T_818, _T_819)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_821 = shr(io.in.a.bits.source, 2)
node _T_822 = eq(_T_821, UInt<2>(0h2))
node _T_823 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_824 = and(_T_822, _T_823)
node _T_825 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_826 = and(_T_824, _T_825)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_827 = shr(io.in.a.bits.source, 2)
node _T_828 = eq(_T_827, UInt<2>(0h3))
node _T_829 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_830 = and(_T_828, _T_829)
node _T_831 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_832 = and(_T_830, _T_831)
node _T_833 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_834 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_835 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_836 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_837 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_838 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_839 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_840 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_841 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_842 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_843 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_844 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_845 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_846 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_847 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_848 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_849 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_850 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_851 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_852 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_853 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_854 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_855 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_856 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_857 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_858 = or(_T_808, _T_814)
node _T_859 = or(_T_858, _T_820)
node _T_860 = or(_T_859, _T_826)
node _T_861 = or(_T_860, _T_832)
node _T_862 = or(_T_861, _T_833)
node _T_863 = or(_T_862, _T_834)
node _T_864 = or(_T_863, _T_835)
node _T_865 = or(_T_864, _T_836)
node _T_866 = or(_T_865, _T_837)
node _T_867 = or(_T_866, _T_838)
node _T_868 = or(_T_867, _T_839)
node _T_869 = or(_T_868, _T_840)
node _T_870 = or(_T_869, _T_841)
node _T_871 = or(_T_870, _T_842)
node _T_872 = or(_T_871, _T_843)
node _T_873 = or(_T_872, _T_844)
node _T_874 = or(_T_873, _T_845)
node _T_875 = or(_T_874, _T_846)
node _T_876 = or(_T_875, _T_847)
node _T_877 = or(_T_876, _T_848)
node _T_878 = or(_T_877, _T_849)
node _T_879 = or(_T_878, _T_850)
node _T_880 = or(_T_879, _T_851)
node _T_881 = or(_T_880, _T_852)
node _T_882 = or(_T_881, _T_853)
node _T_883 = or(_T_882, _T_854)
node _T_884 = or(_T_883, _T_855)
node _T_885 = or(_T_884, _T_856)
node _T_886 = or(_T_885, _T_857)
node _T_887 = and(_T_807, _T_886)
node _T_888 = or(UInt<1>(0h0), _T_887)
node _T_889 = asUInt(reset)
node _T_890 = eq(_T_889, UInt<1>(0h0))
when _T_890 :
node _T_891 = eq(_T_888, UInt<1>(0h0))
when _T_891 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_888, UInt<1>(0h1), "") : assert_19
node _T_892 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_893 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_894 = and(_T_892, _T_893)
node _T_895 = or(UInt<1>(0h0), _T_894)
node _T_896 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_897 = cvt(_T_896)
node _T_898 = and(_T_897, asSInt(UInt<13>(0h1000)))
node _T_899 = asSInt(_T_898)
node _T_900 = eq(_T_899, asSInt(UInt<1>(0h0)))
node _T_901 = and(_T_895, _T_900)
node _T_902 = or(UInt<1>(0h0), _T_901)
node _T_903 = asUInt(reset)
node _T_904 = eq(_T_903, UInt<1>(0h0))
when _T_904 :
node _T_905 = eq(_T_902, UInt<1>(0h0))
when _T_905 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_902, UInt<1>(0h1), "") : assert_20
node _T_906 = asUInt(reset)
node _T_907 = eq(_T_906, UInt<1>(0h0))
when _T_907 :
node _T_908 = eq(source_ok, UInt<1>(0h0))
when _T_908 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_909 = asUInt(reset)
node _T_910 = eq(_T_909, UInt<1>(0h0))
when _T_910 :
node _T_911 = eq(is_aligned, UInt<1>(0h0))
when _T_911 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_912 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_913 = asUInt(reset)
node _T_914 = eq(_T_913, UInt<1>(0h0))
when _T_914 :
node _T_915 = eq(_T_912, UInt<1>(0h0))
when _T_915 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_912, UInt<1>(0h1), "") : assert_23
node _T_916 = eq(io.in.a.bits.mask, mask)
node _T_917 = asUInt(reset)
node _T_918 = eq(_T_917, UInt<1>(0h0))
when _T_918 :
node _T_919 = eq(_T_916, UInt<1>(0h0))
when _T_919 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_916, UInt<1>(0h1), "") : assert_24
node _T_920 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_921 = asUInt(reset)
node _T_922 = eq(_T_921, UInt<1>(0h0))
when _T_922 :
node _T_923 = eq(_T_920, UInt<1>(0h0))
when _T_923 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_920, UInt<1>(0h1), "") : assert_25
node _T_924 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_924 :
node _T_925 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_926 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_927 = and(_T_925, _T_926)
node _T_928 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_929 = shr(io.in.a.bits.source, 2)
node _T_930 = eq(_T_929, UInt<1>(0h0))
node _T_931 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_932 = and(_T_930, _T_931)
node _T_933 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_934 = and(_T_932, _T_933)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_935 = shr(io.in.a.bits.source, 2)
node _T_936 = eq(_T_935, UInt<1>(0h1))
node _T_937 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_938 = and(_T_936, _T_937)
node _T_939 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_940 = and(_T_938, _T_939)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_941 = shr(io.in.a.bits.source, 2)
node _T_942 = eq(_T_941, UInt<2>(0h2))
node _T_943 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_944 = and(_T_942, _T_943)
node _T_945 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_946 = and(_T_944, _T_945)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_947 = shr(io.in.a.bits.source, 2)
node _T_948 = eq(_T_947, UInt<2>(0h3))
node _T_949 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_950 = and(_T_948, _T_949)
node _T_951 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_952 = and(_T_950, _T_951)
node _T_953 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_954 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_955 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_956 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_957 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_958 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_959 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_960 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_961 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_962 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_963 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_964 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_965 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_966 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_967 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_968 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_969 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_970 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_971 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_972 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_973 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_974 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_975 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_976 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_977 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_978 = or(_T_928, _T_934)
node _T_979 = or(_T_978, _T_940)
node _T_980 = or(_T_979, _T_946)
node _T_981 = or(_T_980, _T_952)
node _T_982 = or(_T_981, _T_953)
node _T_983 = or(_T_982, _T_954)
node _T_984 = or(_T_983, _T_955)
node _T_985 = or(_T_984, _T_956)
node _T_986 = or(_T_985, _T_957)
node _T_987 = or(_T_986, _T_958)
node _T_988 = or(_T_987, _T_959)
node _T_989 = or(_T_988, _T_960)
node _T_990 = or(_T_989, _T_961)
node _T_991 = or(_T_990, _T_962)
node _T_992 = or(_T_991, _T_963)
node _T_993 = or(_T_992, _T_964)
node _T_994 = or(_T_993, _T_965)
node _T_995 = or(_T_994, _T_966)
node _T_996 = or(_T_995, _T_967)
node _T_997 = or(_T_996, _T_968)
node _T_998 = or(_T_997, _T_969)
node _T_999 = or(_T_998, _T_970)
node _T_1000 = or(_T_999, _T_971)
node _T_1001 = or(_T_1000, _T_972)
node _T_1002 = or(_T_1001, _T_973)
node _T_1003 = or(_T_1002, _T_974)
node _T_1004 = or(_T_1003, _T_975)
node _T_1005 = or(_T_1004, _T_976)
node _T_1006 = or(_T_1005, _T_977)
node _T_1007 = and(_T_927, _T_1006)
node _T_1008 = or(UInt<1>(0h0), _T_1007)
node _T_1009 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1010 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1011 = and(_T_1009, _T_1010)
node _T_1012 = or(UInt<1>(0h0), _T_1011)
node _T_1013 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1014 = cvt(_T_1013)
node _T_1015 = and(_T_1014, asSInt(UInt<13>(0h1000)))
node _T_1016 = asSInt(_T_1015)
node _T_1017 = eq(_T_1016, asSInt(UInt<1>(0h0)))
node _T_1018 = and(_T_1012, _T_1017)
node _T_1019 = or(UInt<1>(0h0), _T_1018)
node _T_1020 = and(_T_1008, _T_1019)
node _T_1021 = asUInt(reset)
node _T_1022 = eq(_T_1021, UInt<1>(0h0))
when _T_1022 :
node _T_1023 = eq(_T_1020, UInt<1>(0h0))
when _T_1023 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_1020, UInt<1>(0h1), "") : assert_26
node _T_1024 = asUInt(reset)
node _T_1025 = eq(_T_1024, UInt<1>(0h0))
when _T_1025 :
node _T_1026 = eq(source_ok, UInt<1>(0h0))
when _T_1026 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_1027 = asUInt(reset)
node _T_1028 = eq(_T_1027, UInt<1>(0h0))
when _T_1028 :
node _T_1029 = eq(is_aligned, UInt<1>(0h0))
when _T_1029 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_1030 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1031 = asUInt(reset)
node _T_1032 = eq(_T_1031, UInt<1>(0h0))
when _T_1032 :
node _T_1033 = eq(_T_1030, UInt<1>(0h0))
when _T_1033 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_1030, UInt<1>(0h1), "") : assert_29
node _T_1034 = eq(io.in.a.bits.mask, mask)
node _T_1035 = asUInt(reset)
node _T_1036 = eq(_T_1035, UInt<1>(0h0))
when _T_1036 :
node _T_1037 = eq(_T_1034, UInt<1>(0h0))
when _T_1037 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_1034, UInt<1>(0h1), "") : assert_30
node _T_1038 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_1038 :
node _T_1039 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1040 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1041 = and(_T_1039, _T_1040)
node _T_1042 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_1043 = shr(io.in.a.bits.source, 2)
node _T_1044 = eq(_T_1043, UInt<1>(0h0))
node _T_1045 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_1046 = and(_T_1044, _T_1045)
node _T_1047 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_1048 = and(_T_1046, _T_1047)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_1049 = shr(io.in.a.bits.source, 2)
node _T_1050 = eq(_T_1049, UInt<1>(0h1))
node _T_1051 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_1052 = and(_T_1050, _T_1051)
node _T_1053 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_1054 = and(_T_1052, _T_1053)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_1055 = shr(io.in.a.bits.source, 2)
node _T_1056 = eq(_T_1055, UInt<2>(0h2))
node _T_1057 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_1058 = and(_T_1056, _T_1057)
node _T_1059 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_1060 = and(_T_1058, _T_1059)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_1061 = shr(io.in.a.bits.source, 2)
node _T_1062 = eq(_T_1061, UInt<2>(0h3))
node _T_1063 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_1064 = and(_T_1062, _T_1063)
node _T_1065 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_1066 = and(_T_1064, _T_1065)
node _T_1067 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1068 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_1069 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1070 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1071 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_1072 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1073 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1074 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1075 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1076 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1077 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_1078 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1079 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1080 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1081 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1082 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1083 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1084 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1085 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1086 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1087 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1088 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1089 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1090 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1091 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1092 = or(_T_1042, _T_1048)
node _T_1093 = or(_T_1092, _T_1054)
node _T_1094 = or(_T_1093, _T_1060)
node _T_1095 = or(_T_1094, _T_1066)
node _T_1096 = or(_T_1095, _T_1067)
node _T_1097 = or(_T_1096, _T_1068)
node _T_1098 = or(_T_1097, _T_1069)
node _T_1099 = or(_T_1098, _T_1070)
node _T_1100 = or(_T_1099, _T_1071)
node _T_1101 = or(_T_1100, _T_1072)
node _T_1102 = or(_T_1101, _T_1073)
node _T_1103 = or(_T_1102, _T_1074)
node _T_1104 = or(_T_1103, _T_1075)
node _T_1105 = or(_T_1104, _T_1076)
node _T_1106 = or(_T_1105, _T_1077)
node _T_1107 = or(_T_1106, _T_1078)
node _T_1108 = or(_T_1107, _T_1079)
node _T_1109 = or(_T_1108, _T_1080)
node _T_1110 = or(_T_1109, _T_1081)
node _T_1111 = or(_T_1110, _T_1082)
node _T_1112 = or(_T_1111, _T_1083)
node _T_1113 = or(_T_1112, _T_1084)
node _T_1114 = or(_T_1113, _T_1085)
node _T_1115 = or(_T_1114, _T_1086)
node _T_1116 = or(_T_1115, _T_1087)
node _T_1117 = or(_T_1116, _T_1088)
node _T_1118 = or(_T_1117, _T_1089)
node _T_1119 = or(_T_1118, _T_1090)
node _T_1120 = or(_T_1119, _T_1091)
node _T_1121 = and(_T_1041, _T_1120)
node _T_1122 = or(UInt<1>(0h0), _T_1121)
node _T_1123 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1124 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1125 = and(_T_1123, _T_1124)
node _T_1126 = or(UInt<1>(0h0), _T_1125)
node _T_1127 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1128 = cvt(_T_1127)
node _T_1129 = and(_T_1128, asSInt(UInt<13>(0h1000)))
node _T_1130 = asSInt(_T_1129)
node _T_1131 = eq(_T_1130, asSInt(UInt<1>(0h0)))
node _T_1132 = and(_T_1126, _T_1131)
node _T_1133 = or(UInt<1>(0h0), _T_1132)
node _T_1134 = and(_T_1122, _T_1133)
node _T_1135 = asUInt(reset)
node _T_1136 = eq(_T_1135, UInt<1>(0h0))
when _T_1136 :
node _T_1137 = eq(_T_1134, UInt<1>(0h0))
when _T_1137 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_1134, UInt<1>(0h1), "") : assert_31
node _T_1138 = asUInt(reset)
node _T_1139 = eq(_T_1138, UInt<1>(0h0))
when _T_1139 :
node _T_1140 = eq(source_ok, UInt<1>(0h0))
when _T_1140 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_1141 = asUInt(reset)
node _T_1142 = eq(_T_1141, UInt<1>(0h0))
when _T_1142 :
node _T_1143 = eq(is_aligned, UInt<1>(0h0))
when _T_1143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_1144 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1145 = asUInt(reset)
node _T_1146 = eq(_T_1145, UInt<1>(0h0))
when _T_1146 :
node _T_1147 = eq(_T_1144, UInt<1>(0h0))
when _T_1147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_1144, UInt<1>(0h1), "") : assert_34
node _T_1148 = not(mask)
node _T_1149 = and(io.in.a.bits.mask, _T_1148)
node _T_1150 = eq(_T_1149, UInt<1>(0h0))
node _T_1151 = asUInt(reset)
node _T_1152 = eq(_T_1151, UInt<1>(0h0))
when _T_1152 :
node _T_1153 = eq(_T_1150, UInt<1>(0h0))
when _T_1153 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_1150, UInt<1>(0h1), "") : assert_35
node _T_1154 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_1154 :
node _T_1155 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1156 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1157 = and(_T_1155, _T_1156)
node _T_1158 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_1159 = shr(io.in.a.bits.source, 2)
node _T_1160 = eq(_T_1159, UInt<1>(0h0))
node _T_1161 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_1162 = and(_T_1160, _T_1161)
node _T_1163 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_1164 = and(_T_1162, _T_1163)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_1165 = shr(io.in.a.bits.source, 2)
node _T_1166 = eq(_T_1165, UInt<1>(0h1))
node _T_1167 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_1168 = and(_T_1166, _T_1167)
node _T_1169 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_1170 = and(_T_1168, _T_1169)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_1171 = shr(io.in.a.bits.source, 2)
node _T_1172 = eq(_T_1171, UInt<2>(0h2))
node _T_1173 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_1174 = and(_T_1172, _T_1173)
node _T_1175 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_1176 = and(_T_1174, _T_1175)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_1177 = shr(io.in.a.bits.source, 2)
node _T_1178 = eq(_T_1177, UInt<2>(0h3))
node _T_1179 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_1180 = and(_T_1178, _T_1179)
node _T_1181 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_1182 = and(_T_1180, _T_1181)
node _T_1183 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1184 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_1185 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1186 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1187 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_1188 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1189 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1190 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1191 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1192 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1193 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_1194 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1195 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1196 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1197 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1198 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1199 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1200 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1201 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1202 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1203 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1204 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1205 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1206 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1207 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1208 = or(_T_1158, _T_1164)
node _T_1209 = or(_T_1208, _T_1170)
node _T_1210 = or(_T_1209, _T_1176)
node _T_1211 = or(_T_1210, _T_1182)
node _T_1212 = or(_T_1211, _T_1183)
node _T_1213 = or(_T_1212, _T_1184)
node _T_1214 = or(_T_1213, _T_1185)
node _T_1215 = or(_T_1214, _T_1186)
node _T_1216 = or(_T_1215, _T_1187)
node _T_1217 = or(_T_1216, _T_1188)
node _T_1218 = or(_T_1217, _T_1189)
node _T_1219 = or(_T_1218, _T_1190)
node _T_1220 = or(_T_1219, _T_1191)
node _T_1221 = or(_T_1220, _T_1192)
node _T_1222 = or(_T_1221, _T_1193)
node _T_1223 = or(_T_1222, _T_1194)
node _T_1224 = or(_T_1223, _T_1195)
node _T_1225 = or(_T_1224, _T_1196)
node _T_1226 = or(_T_1225, _T_1197)
node _T_1227 = or(_T_1226, _T_1198)
node _T_1228 = or(_T_1227, _T_1199)
node _T_1229 = or(_T_1228, _T_1200)
node _T_1230 = or(_T_1229, _T_1201)
node _T_1231 = or(_T_1230, _T_1202)
node _T_1232 = or(_T_1231, _T_1203)
node _T_1233 = or(_T_1232, _T_1204)
node _T_1234 = or(_T_1233, _T_1205)
node _T_1235 = or(_T_1234, _T_1206)
node _T_1236 = or(_T_1235, _T_1207)
node _T_1237 = and(_T_1157, _T_1236)
node _T_1238 = or(UInt<1>(0h0), _T_1237)
node _T_1239 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1240 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1241 = cvt(_T_1240)
node _T_1242 = and(_T_1241, asSInt(UInt<13>(0h1000)))
node _T_1243 = asSInt(_T_1242)
node _T_1244 = eq(_T_1243, asSInt(UInt<1>(0h0)))
node _T_1245 = and(_T_1239, _T_1244)
node _T_1246 = or(UInt<1>(0h0), _T_1245)
node _T_1247 = and(_T_1238, _T_1246)
node _T_1248 = asUInt(reset)
node _T_1249 = eq(_T_1248, UInt<1>(0h0))
when _T_1249 :
node _T_1250 = eq(_T_1247, UInt<1>(0h0))
when _T_1250 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1247, UInt<1>(0h1), "") : assert_36
node _T_1251 = asUInt(reset)
node _T_1252 = eq(_T_1251, UInt<1>(0h0))
when _T_1252 :
node _T_1253 = eq(source_ok, UInt<1>(0h0))
when _T_1253 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1254 = asUInt(reset)
node _T_1255 = eq(_T_1254, UInt<1>(0h0))
when _T_1255 :
node _T_1256 = eq(is_aligned, UInt<1>(0h0))
when _T_1256 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1257 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1258 = asUInt(reset)
node _T_1259 = eq(_T_1258, UInt<1>(0h0))
when _T_1259 :
node _T_1260 = eq(_T_1257, UInt<1>(0h0))
when _T_1260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1257, UInt<1>(0h1), "") : assert_39
node _T_1261 = eq(io.in.a.bits.mask, mask)
node _T_1262 = asUInt(reset)
node _T_1263 = eq(_T_1262, UInt<1>(0h0))
when _T_1263 :
node _T_1264 = eq(_T_1261, UInt<1>(0h0))
when _T_1264 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1261, UInt<1>(0h1), "") : assert_40
node _T_1265 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1265 :
node _T_1266 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1267 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1268 = and(_T_1266, _T_1267)
node _T_1269 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_1270 = shr(io.in.a.bits.source, 2)
node _T_1271 = eq(_T_1270, UInt<1>(0h0))
node _T_1272 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_1273 = and(_T_1271, _T_1272)
node _T_1274 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_1275 = and(_T_1273, _T_1274)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_1276 = shr(io.in.a.bits.source, 2)
node _T_1277 = eq(_T_1276, UInt<1>(0h1))
node _T_1278 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_1279 = and(_T_1277, _T_1278)
node _T_1280 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_1281 = and(_T_1279, _T_1280)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_1282 = shr(io.in.a.bits.source, 2)
node _T_1283 = eq(_T_1282, UInt<2>(0h2))
node _T_1284 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_1285 = and(_T_1283, _T_1284)
node _T_1286 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_1287 = and(_T_1285, _T_1286)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_1288 = shr(io.in.a.bits.source, 2)
node _T_1289 = eq(_T_1288, UInt<2>(0h3))
node _T_1290 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_1291 = and(_T_1289, _T_1290)
node _T_1292 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_1293 = and(_T_1291, _T_1292)
node _T_1294 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1295 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_1296 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1297 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1298 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_1299 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1300 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1301 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1302 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1303 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1304 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_1305 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1306 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1307 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1308 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1309 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1310 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1311 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1312 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1313 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1314 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1315 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1316 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1317 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1318 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1319 = or(_T_1269, _T_1275)
node _T_1320 = or(_T_1319, _T_1281)
node _T_1321 = or(_T_1320, _T_1287)
node _T_1322 = or(_T_1321, _T_1293)
node _T_1323 = or(_T_1322, _T_1294)
node _T_1324 = or(_T_1323, _T_1295)
node _T_1325 = or(_T_1324, _T_1296)
node _T_1326 = or(_T_1325, _T_1297)
node _T_1327 = or(_T_1326, _T_1298)
node _T_1328 = or(_T_1327, _T_1299)
node _T_1329 = or(_T_1328, _T_1300)
node _T_1330 = or(_T_1329, _T_1301)
node _T_1331 = or(_T_1330, _T_1302)
node _T_1332 = or(_T_1331, _T_1303)
node _T_1333 = or(_T_1332, _T_1304)
node _T_1334 = or(_T_1333, _T_1305)
node _T_1335 = or(_T_1334, _T_1306)
node _T_1336 = or(_T_1335, _T_1307)
node _T_1337 = or(_T_1336, _T_1308)
node _T_1338 = or(_T_1337, _T_1309)
node _T_1339 = or(_T_1338, _T_1310)
node _T_1340 = or(_T_1339, _T_1311)
node _T_1341 = or(_T_1340, _T_1312)
node _T_1342 = or(_T_1341, _T_1313)
node _T_1343 = or(_T_1342, _T_1314)
node _T_1344 = or(_T_1343, _T_1315)
node _T_1345 = or(_T_1344, _T_1316)
node _T_1346 = or(_T_1345, _T_1317)
node _T_1347 = or(_T_1346, _T_1318)
node _T_1348 = and(_T_1268, _T_1347)
node _T_1349 = or(UInt<1>(0h0), _T_1348)
node _T_1350 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1351 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1352 = cvt(_T_1351)
node _T_1353 = and(_T_1352, asSInt(UInt<13>(0h1000)))
node _T_1354 = asSInt(_T_1353)
node _T_1355 = eq(_T_1354, asSInt(UInt<1>(0h0)))
node _T_1356 = and(_T_1350, _T_1355)
node _T_1357 = or(UInt<1>(0h0), _T_1356)
node _T_1358 = and(_T_1349, _T_1357)
node _T_1359 = asUInt(reset)
node _T_1360 = eq(_T_1359, UInt<1>(0h0))
when _T_1360 :
node _T_1361 = eq(_T_1358, UInt<1>(0h0))
when _T_1361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1358, UInt<1>(0h1), "") : assert_41
node _T_1362 = asUInt(reset)
node _T_1363 = eq(_T_1362, UInt<1>(0h0))
when _T_1363 :
node _T_1364 = eq(source_ok, UInt<1>(0h0))
when _T_1364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1365 = asUInt(reset)
node _T_1366 = eq(_T_1365, UInt<1>(0h0))
when _T_1366 :
node _T_1367 = eq(is_aligned, UInt<1>(0h0))
when _T_1367 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1368 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1369 = asUInt(reset)
node _T_1370 = eq(_T_1369, UInt<1>(0h0))
when _T_1370 :
node _T_1371 = eq(_T_1368, UInt<1>(0h0))
when _T_1371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1368, UInt<1>(0h1), "") : assert_44
node _T_1372 = eq(io.in.a.bits.mask, mask)
node _T_1373 = asUInt(reset)
node _T_1374 = eq(_T_1373, UInt<1>(0h0))
when _T_1374 :
node _T_1375 = eq(_T_1372, UInt<1>(0h0))
when _T_1375 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1372, UInt<1>(0h1), "") : assert_45
node _T_1376 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1376 :
node _T_1377 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1378 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1379 = and(_T_1377, _T_1378)
node _T_1380 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_1381 = shr(io.in.a.bits.source, 2)
node _T_1382 = eq(_T_1381, UInt<1>(0h0))
node _T_1383 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_1384 = and(_T_1382, _T_1383)
node _T_1385 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_1386 = and(_T_1384, _T_1385)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_1387 = shr(io.in.a.bits.source, 2)
node _T_1388 = eq(_T_1387, UInt<1>(0h1))
node _T_1389 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_1390 = and(_T_1388, _T_1389)
node _T_1391 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_1392 = and(_T_1390, _T_1391)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_1393 = shr(io.in.a.bits.source, 2)
node _T_1394 = eq(_T_1393, UInt<2>(0h2))
node _T_1395 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_1396 = and(_T_1394, _T_1395)
node _T_1397 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_1398 = and(_T_1396, _T_1397)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_1399 = shr(io.in.a.bits.source, 2)
node _T_1400 = eq(_T_1399, UInt<2>(0h3))
node _T_1401 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_1402 = and(_T_1400, _T_1401)
node _T_1403 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_1404 = and(_T_1402, _T_1403)
node _T_1405 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1406 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_1407 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1408 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1409 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_1410 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1411 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1412 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1413 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1414 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1415 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_1416 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1417 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1418 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1419 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1420 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1421 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1422 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1423 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1424 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1425 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1426 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1427 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1428 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1429 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1430 = or(_T_1380, _T_1386)
node _T_1431 = or(_T_1430, _T_1392)
node _T_1432 = or(_T_1431, _T_1398)
node _T_1433 = or(_T_1432, _T_1404)
node _T_1434 = or(_T_1433, _T_1405)
node _T_1435 = or(_T_1434, _T_1406)
node _T_1436 = or(_T_1435, _T_1407)
node _T_1437 = or(_T_1436, _T_1408)
node _T_1438 = or(_T_1437, _T_1409)
node _T_1439 = or(_T_1438, _T_1410)
node _T_1440 = or(_T_1439, _T_1411)
node _T_1441 = or(_T_1440, _T_1412)
node _T_1442 = or(_T_1441, _T_1413)
node _T_1443 = or(_T_1442, _T_1414)
node _T_1444 = or(_T_1443, _T_1415)
node _T_1445 = or(_T_1444, _T_1416)
node _T_1446 = or(_T_1445, _T_1417)
node _T_1447 = or(_T_1446, _T_1418)
node _T_1448 = or(_T_1447, _T_1419)
node _T_1449 = or(_T_1448, _T_1420)
node _T_1450 = or(_T_1449, _T_1421)
node _T_1451 = or(_T_1450, _T_1422)
node _T_1452 = or(_T_1451, _T_1423)
node _T_1453 = or(_T_1452, _T_1424)
node _T_1454 = or(_T_1453, _T_1425)
node _T_1455 = or(_T_1454, _T_1426)
node _T_1456 = or(_T_1455, _T_1427)
node _T_1457 = or(_T_1456, _T_1428)
node _T_1458 = or(_T_1457, _T_1429)
node _T_1459 = and(_T_1379, _T_1458)
node _T_1460 = or(UInt<1>(0h0), _T_1459)
node _T_1461 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1462 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1463 = cvt(_T_1462)
node _T_1464 = and(_T_1463, asSInt(UInt<13>(0h1000)))
node _T_1465 = asSInt(_T_1464)
node _T_1466 = eq(_T_1465, asSInt(UInt<1>(0h0)))
node _T_1467 = and(_T_1461, _T_1466)
node _T_1468 = or(UInt<1>(0h0), _T_1467)
node _T_1469 = and(_T_1460, _T_1468)
node _T_1470 = asUInt(reset)
node _T_1471 = eq(_T_1470, UInt<1>(0h0))
when _T_1471 :
node _T_1472 = eq(_T_1469, UInt<1>(0h0))
when _T_1472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1469, UInt<1>(0h1), "") : assert_46
node _T_1473 = asUInt(reset)
node _T_1474 = eq(_T_1473, UInt<1>(0h0))
when _T_1474 :
node _T_1475 = eq(source_ok, UInt<1>(0h0))
when _T_1475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1476 = asUInt(reset)
node _T_1477 = eq(_T_1476, UInt<1>(0h0))
when _T_1477 :
node _T_1478 = eq(is_aligned, UInt<1>(0h0))
when _T_1478 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1479 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1480 = asUInt(reset)
node _T_1481 = eq(_T_1480, UInt<1>(0h0))
when _T_1481 :
node _T_1482 = eq(_T_1479, UInt<1>(0h0))
when _T_1482 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1479, UInt<1>(0h1), "") : assert_49
node _T_1483 = eq(io.in.a.bits.mask, mask)
node _T_1484 = asUInt(reset)
node _T_1485 = eq(_T_1484, UInt<1>(0h0))
when _T_1485 :
node _T_1486 = eq(_T_1483, UInt<1>(0h0))
when _T_1486 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1483, UInt<1>(0h1), "") : assert_50
node _T_1487 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1488 = asUInt(reset)
node _T_1489 = eq(_T_1488, UInt<1>(0h0))
when _T_1489 :
node _T_1490 = eq(_T_1487, UInt<1>(0h0))
when _T_1490 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1487, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1491 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1492 = asUInt(reset)
node _T_1493 = eq(_T_1492, UInt<1>(0h0))
when _T_1493 :
node _T_1494 = eq(_T_1491, UInt<1>(0h0))
when _T_1494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1491, UInt<1>(0h1), "") : assert_52
node _source_ok_T_78 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_79 = shr(io.in.d.bits.source, 2)
node _source_ok_T_80 = eq(_source_ok_T_79, UInt<1>(0h0))
node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81)
node _source_ok_T_83 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_85 = shr(io.in.d.bits.source, 2)
node _source_ok_T_86 = eq(_source_ok_T_85, UInt<1>(0h1))
node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87)
node _source_ok_T_89 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_91 = shr(io.in.d.bits.source, 2)
node _source_ok_T_92 = eq(_source_ok_T_91, UInt<2>(0h2))
node _source_ok_T_93 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93)
node _source_ok_T_95 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_97 = shr(io.in.d.bits.source, 2)
node _source_ok_T_98 = eq(_source_ok_T_97, UInt<2>(0h3))
node _source_ok_T_99 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99)
node _source_ok_T_101 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101)
node _source_ok_T_103 = eq(io.in.d.bits.source, UInt<6>(0h3c))
node _source_ok_T_104 = eq(io.in.d.bits.source, UInt<6>(0h3d))
node _source_ok_T_105 = eq(io.in.d.bits.source, UInt<6>(0h3e))
node _source_ok_T_106 = eq(io.in.d.bits.source, UInt<6>(0h38))
node _source_ok_T_107 = eq(io.in.d.bits.source, UInt<6>(0h39))
node _source_ok_T_108 = eq(io.in.d.bits.source, UInt<6>(0h3a))
node _source_ok_T_109 = eq(io.in.d.bits.source, UInt<6>(0h34))
node _source_ok_T_110 = eq(io.in.d.bits.source, UInt<6>(0h35))
node _source_ok_T_111 = eq(io.in.d.bits.source, UInt<6>(0h36))
node _source_ok_T_112 = eq(io.in.d.bits.source, UInt<6>(0h30))
node _source_ok_T_113 = eq(io.in.d.bits.source, UInt<6>(0h31))
node _source_ok_T_114 = eq(io.in.d.bits.source, UInt<6>(0h32))
node _source_ok_T_115 = eq(io.in.d.bits.source, UInt<6>(0h2c))
node _source_ok_T_116 = eq(io.in.d.bits.source, UInt<6>(0h2d))
node _source_ok_T_117 = eq(io.in.d.bits.source, UInt<6>(0h2e))
node _source_ok_T_118 = eq(io.in.d.bits.source, UInt<6>(0h28))
node _source_ok_T_119 = eq(io.in.d.bits.source, UInt<6>(0h29))
node _source_ok_T_120 = eq(io.in.d.bits.source, UInt<6>(0h2a))
node _source_ok_T_121 = eq(io.in.d.bits.source, UInt<6>(0h24))
node _source_ok_T_122 = eq(io.in.d.bits.source, UInt<6>(0h25))
node _source_ok_T_123 = eq(io.in.d.bits.source, UInt<6>(0h26))
node _source_ok_T_124 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_125 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_T_126 = eq(io.in.d.bits.source, UInt<6>(0h22))
node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[30]
connect _source_ok_WIRE_1[0], _source_ok_T_78
connect _source_ok_WIRE_1[1], _source_ok_T_84
connect _source_ok_WIRE_1[2], _source_ok_T_90
connect _source_ok_WIRE_1[3], _source_ok_T_96
connect _source_ok_WIRE_1[4], _source_ok_T_102
connect _source_ok_WIRE_1[5], _source_ok_T_103
connect _source_ok_WIRE_1[6], _source_ok_T_104
connect _source_ok_WIRE_1[7], _source_ok_T_105
connect _source_ok_WIRE_1[8], _source_ok_T_106
connect _source_ok_WIRE_1[9], _source_ok_T_107
connect _source_ok_WIRE_1[10], _source_ok_T_108
connect _source_ok_WIRE_1[11], _source_ok_T_109
connect _source_ok_WIRE_1[12], _source_ok_T_110
connect _source_ok_WIRE_1[13], _source_ok_T_111
connect _source_ok_WIRE_1[14], _source_ok_T_112
connect _source_ok_WIRE_1[15], _source_ok_T_113
connect _source_ok_WIRE_1[16], _source_ok_T_114
connect _source_ok_WIRE_1[17], _source_ok_T_115
connect _source_ok_WIRE_1[18], _source_ok_T_116
connect _source_ok_WIRE_1[19], _source_ok_T_117
connect _source_ok_WIRE_1[20], _source_ok_T_118
connect _source_ok_WIRE_1[21], _source_ok_T_119
connect _source_ok_WIRE_1[22], _source_ok_T_120
connect _source_ok_WIRE_1[23], _source_ok_T_121
connect _source_ok_WIRE_1[24], _source_ok_T_122
connect _source_ok_WIRE_1[25], _source_ok_T_123
connect _source_ok_WIRE_1[26], _source_ok_T_124
connect _source_ok_WIRE_1[27], _source_ok_T_125
connect _source_ok_WIRE_1[28], _source_ok_T_126
connect _source_ok_WIRE_1[29], _source_ok_T_127
node _source_ok_T_128 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_129 = or(_source_ok_T_128, _source_ok_WIRE_1[2])
node _source_ok_T_130 = or(_source_ok_T_129, _source_ok_WIRE_1[3])
node _source_ok_T_131 = or(_source_ok_T_130, _source_ok_WIRE_1[4])
node _source_ok_T_132 = or(_source_ok_T_131, _source_ok_WIRE_1[5])
node _source_ok_T_133 = or(_source_ok_T_132, _source_ok_WIRE_1[6])
node _source_ok_T_134 = or(_source_ok_T_133, _source_ok_WIRE_1[7])
node _source_ok_T_135 = or(_source_ok_T_134, _source_ok_WIRE_1[8])
node _source_ok_T_136 = or(_source_ok_T_135, _source_ok_WIRE_1[9])
node _source_ok_T_137 = or(_source_ok_T_136, _source_ok_WIRE_1[10])
node _source_ok_T_138 = or(_source_ok_T_137, _source_ok_WIRE_1[11])
node _source_ok_T_139 = or(_source_ok_T_138, _source_ok_WIRE_1[12])
node _source_ok_T_140 = or(_source_ok_T_139, _source_ok_WIRE_1[13])
node _source_ok_T_141 = or(_source_ok_T_140, _source_ok_WIRE_1[14])
node _source_ok_T_142 = or(_source_ok_T_141, _source_ok_WIRE_1[15])
node _source_ok_T_143 = or(_source_ok_T_142, _source_ok_WIRE_1[16])
node _source_ok_T_144 = or(_source_ok_T_143, _source_ok_WIRE_1[17])
node _source_ok_T_145 = or(_source_ok_T_144, _source_ok_WIRE_1[18])
node _source_ok_T_146 = or(_source_ok_T_145, _source_ok_WIRE_1[19])
node _source_ok_T_147 = or(_source_ok_T_146, _source_ok_WIRE_1[20])
node _source_ok_T_148 = or(_source_ok_T_147, _source_ok_WIRE_1[21])
node _source_ok_T_149 = or(_source_ok_T_148, _source_ok_WIRE_1[22])
node _source_ok_T_150 = or(_source_ok_T_149, _source_ok_WIRE_1[23])
node _source_ok_T_151 = or(_source_ok_T_150, _source_ok_WIRE_1[24])
node _source_ok_T_152 = or(_source_ok_T_151, _source_ok_WIRE_1[25])
node _source_ok_T_153 = or(_source_ok_T_152, _source_ok_WIRE_1[26])
node _source_ok_T_154 = or(_source_ok_T_153, _source_ok_WIRE_1[27])
node _source_ok_T_155 = or(_source_ok_T_154, _source_ok_WIRE_1[28])
node source_ok_1 = or(_source_ok_T_155, _source_ok_WIRE_1[29])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1495 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1495 :
node _T_1496 = asUInt(reset)
node _T_1497 = eq(_T_1496, UInt<1>(0h0))
when _T_1497 :
node _T_1498 = eq(source_ok_1, UInt<1>(0h0))
when _T_1498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1499 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1500 = asUInt(reset)
node _T_1501 = eq(_T_1500, UInt<1>(0h0))
when _T_1501 :
node _T_1502 = eq(_T_1499, UInt<1>(0h0))
when _T_1502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1499, UInt<1>(0h1), "") : assert_54
node _T_1503 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1504 = asUInt(reset)
node _T_1505 = eq(_T_1504, UInt<1>(0h0))
when _T_1505 :
node _T_1506 = eq(_T_1503, UInt<1>(0h0))
when _T_1506 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1503, UInt<1>(0h1), "") : assert_55
node _T_1507 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1508 = asUInt(reset)
node _T_1509 = eq(_T_1508, UInt<1>(0h0))
when _T_1509 :
node _T_1510 = eq(_T_1507, UInt<1>(0h0))
when _T_1510 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1507, UInt<1>(0h1), "") : assert_56
node _T_1511 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1512 = asUInt(reset)
node _T_1513 = eq(_T_1512, UInt<1>(0h0))
when _T_1513 :
node _T_1514 = eq(_T_1511, UInt<1>(0h0))
when _T_1514 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1511, UInt<1>(0h1), "") : assert_57
node _T_1515 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1515 :
node _T_1516 = asUInt(reset)
node _T_1517 = eq(_T_1516, UInt<1>(0h0))
when _T_1517 :
node _T_1518 = eq(source_ok_1, UInt<1>(0h0))
when _T_1518 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1519 = asUInt(reset)
node _T_1520 = eq(_T_1519, UInt<1>(0h0))
when _T_1520 :
node _T_1521 = eq(sink_ok, UInt<1>(0h0))
when _T_1521 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1522 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1523 = asUInt(reset)
node _T_1524 = eq(_T_1523, UInt<1>(0h0))
when _T_1524 :
node _T_1525 = eq(_T_1522, UInt<1>(0h0))
when _T_1525 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1522, UInt<1>(0h1), "") : assert_60
node _T_1526 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1527 = asUInt(reset)
node _T_1528 = eq(_T_1527, UInt<1>(0h0))
when _T_1528 :
node _T_1529 = eq(_T_1526, UInt<1>(0h0))
when _T_1529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1526, UInt<1>(0h1), "") : assert_61
node _T_1530 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1531 = asUInt(reset)
node _T_1532 = eq(_T_1531, UInt<1>(0h0))
when _T_1532 :
node _T_1533 = eq(_T_1530, UInt<1>(0h0))
when _T_1533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1530, UInt<1>(0h1), "") : assert_62
node _T_1534 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1535 = asUInt(reset)
node _T_1536 = eq(_T_1535, UInt<1>(0h0))
when _T_1536 :
node _T_1537 = eq(_T_1534, UInt<1>(0h0))
when _T_1537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1534, UInt<1>(0h1), "") : assert_63
node _T_1538 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1539 = or(UInt<1>(0h0), _T_1538)
node _T_1540 = asUInt(reset)
node _T_1541 = eq(_T_1540, UInt<1>(0h0))
when _T_1541 :
node _T_1542 = eq(_T_1539, UInt<1>(0h0))
when _T_1542 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1539, UInt<1>(0h1), "") : assert_64
node _T_1543 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1543 :
node _T_1544 = asUInt(reset)
node _T_1545 = eq(_T_1544, UInt<1>(0h0))
when _T_1545 :
node _T_1546 = eq(source_ok_1, UInt<1>(0h0))
when _T_1546 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1547 = asUInt(reset)
node _T_1548 = eq(_T_1547, UInt<1>(0h0))
when _T_1548 :
node _T_1549 = eq(sink_ok, UInt<1>(0h0))
when _T_1549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1550 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1551 = asUInt(reset)
node _T_1552 = eq(_T_1551, UInt<1>(0h0))
when _T_1552 :
node _T_1553 = eq(_T_1550, UInt<1>(0h0))
when _T_1553 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1550, UInt<1>(0h1), "") : assert_67
node _T_1554 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1555 = asUInt(reset)
node _T_1556 = eq(_T_1555, UInt<1>(0h0))
when _T_1556 :
node _T_1557 = eq(_T_1554, UInt<1>(0h0))
when _T_1557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1554, UInt<1>(0h1), "") : assert_68
node _T_1558 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1559 = asUInt(reset)
node _T_1560 = eq(_T_1559, UInt<1>(0h0))
when _T_1560 :
node _T_1561 = eq(_T_1558, UInt<1>(0h0))
when _T_1561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1558, UInt<1>(0h1), "") : assert_69
node _T_1562 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1563 = or(_T_1562, io.in.d.bits.corrupt)
node _T_1564 = asUInt(reset)
node _T_1565 = eq(_T_1564, UInt<1>(0h0))
when _T_1565 :
node _T_1566 = eq(_T_1563, UInt<1>(0h0))
when _T_1566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1563, UInt<1>(0h1), "") : assert_70
node _T_1567 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1568 = or(UInt<1>(0h0), _T_1567)
node _T_1569 = asUInt(reset)
node _T_1570 = eq(_T_1569, UInt<1>(0h0))
when _T_1570 :
node _T_1571 = eq(_T_1568, UInt<1>(0h0))
when _T_1571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1568, UInt<1>(0h1), "") : assert_71
node _T_1572 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1572 :
node _T_1573 = asUInt(reset)
node _T_1574 = eq(_T_1573, UInt<1>(0h0))
when _T_1574 :
node _T_1575 = eq(source_ok_1, UInt<1>(0h0))
when _T_1575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1576 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1577 = asUInt(reset)
node _T_1578 = eq(_T_1577, UInt<1>(0h0))
when _T_1578 :
node _T_1579 = eq(_T_1576, UInt<1>(0h0))
when _T_1579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1576, UInt<1>(0h1), "") : assert_73
node _T_1580 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1581 = asUInt(reset)
node _T_1582 = eq(_T_1581, UInt<1>(0h0))
when _T_1582 :
node _T_1583 = eq(_T_1580, UInt<1>(0h0))
when _T_1583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1580, UInt<1>(0h1), "") : assert_74
node _T_1584 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1585 = or(UInt<1>(0h0), _T_1584)
node _T_1586 = asUInt(reset)
node _T_1587 = eq(_T_1586, UInt<1>(0h0))
when _T_1587 :
node _T_1588 = eq(_T_1585, UInt<1>(0h0))
when _T_1588 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1585, UInt<1>(0h1), "") : assert_75
node _T_1589 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1589 :
node _T_1590 = asUInt(reset)
node _T_1591 = eq(_T_1590, UInt<1>(0h0))
when _T_1591 :
node _T_1592 = eq(source_ok_1, UInt<1>(0h0))
when _T_1592 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1593 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1594 = asUInt(reset)
node _T_1595 = eq(_T_1594, UInt<1>(0h0))
when _T_1595 :
node _T_1596 = eq(_T_1593, UInt<1>(0h0))
when _T_1596 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1593, UInt<1>(0h1), "") : assert_77
node _T_1597 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1598 = or(_T_1597, io.in.d.bits.corrupt)
node _T_1599 = asUInt(reset)
node _T_1600 = eq(_T_1599, UInt<1>(0h0))
when _T_1600 :
node _T_1601 = eq(_T_1598, UInt<1>(0h0))
when _T_1601 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1598, UInt<1>(0h1), "") : assert_78
node _T_1602 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1603 = or(UInt<1>(0h0), _T_1602)
node _T_1604 = asUInt(reset)
node _T_1605 = eq(_T_1604, UInt<1>(0h0))
when _T_1605 :
node _T_1606 = eq(_T_1603, UInt<1>(0h0))
when _T_1606 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1603, UInt<1>(0h1), "") : assert_79
node _T_1607 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1607 :
node _T_1608 = asUInt(reset)
node _T_1609 = eq(_T_1608, UInt<1>(0h0))
when _T_1609 :
node _T_1610 = eq(source_ok_1, UInt<1>(0h0))
when _T_1610 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1611 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1612 = asUInt(reset)
node _T_1613 = eq(_T_1612, UInt<1>(0h0))
when _T_1613 :
node _T_1614 = eq(_T_1611, UInt<1>(0h0))
when _T_1614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1611, UInt<1>(0h1), "") : assert_81
node _T_1615 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1616 = asUInt(reset)
node _T_1617 = eq(_T_1616, UInt<1>(0h0))
when _T_1617 :
node _T_1618 = eq(_T_1615, UInt<1>(0h0))
when _T_1618 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1615, UInt<1>(0h1), "") : assert_82
node _T_1619 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1620 = or(UInt<1>(0h0), _T_1619)
node _T_1621 = asUInt(reset)
node _T_1622 = eq(_T_1621, UInt<1>(0h0))
when _T_1622 :
node _T_1623 = eq(_T_1620, UInt<1>(0h0))
when _T_1623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1620, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<21>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1624 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1625 = asUInt(reset)
node _T_1626 = eq(_T_1625, UInt<1>(0h0))
when _T_1626 :
node _T_1627 = eq(_T_1624, UInt<1>(0h0))
when _T_1627 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1624, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<21>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1628 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1629 = asUInt(reset)
node _T_1630 = eq(_T_1629, UInt<1>(0h0))
when _T_1630 :
node _T_1631 = eq(_T_1628, UInt<1>(0h0))
when _T_1631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1628, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1632 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1633 = asUInt(reset)
node _T_1634 = eq(_T_1633, UInt<1>(0h0))
when _T_1634 :
node _T_1635 = eq(_T_1632, UInt<1>(0h0))
when _T_1635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1632, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1636 = eq(a_first, UInt<1>(0h0))
node _T_1637 = and(io.in.a.valid, _T_1636)
when _T_1637 :
node _T_1638 = eq(io.in.a.bits.opcode, opcode)
node _T_1639 = asUInt(reset)
node _T_1640 = eq(_T_1639, UInt<1>(0h0))
when _T_1640 :
node _T_1641 = eq(_T_1638, UInt<1>(0h0))
when _T_1641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1638, UInt<1>(0h1), "") : assert_87
node _T_1642 = eq(io.in.a.bits.param, param)
node _T_1643 = asUInt(reset)
node _T_1644 = eq(_T_1643, UInt<1>(0h0))
when _T_1644 :
node _T_1645 = eq(_T_1642, UInt<1>(0h0))
when _T_1645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1642, UInt<1>(0h1), "") : assert_88
node _T_1646 = eq(io.in.a.bits.size, size)
node _T_1647 = asUInt(reset)
node _T_1648 = eq(_T_1647, UInt<1>(0h0))
when _T_1648 :
node _T_1649 = eq(_T_1646, UInt<1>(0h0))
when _T_1649 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1646, UInt<1>(0h1), "") : assert_89
node _T_1650 = eq(io.in.a.bits.source, source)
node _T_1651 = asUInt(reset)
node _T_1652 = eq(_T_1651, UInt<1>(0h0))
when _T_1652 :
node _T_1653 = eq(_T_1650, UInt<1>(0h0))
when _T_1653 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1650, UInt<1>(0h1), "") : assert_90
node _T_1654 = eq(io.in.a.bits.address, address)
node _T_1655 = asUInt(reset)
node _T_1656 = eq(_T_1655, UInt<1>(0h0))
when _T_1656 :
node _T_1657 = eq(_T_1654, UInt<1>(0h0))
when _T_1657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1654, UInt<1>(0h1), "") : assert_91
node _T_1658 = and(io.in.a.ready, io.in.a.valid)
node _T_1659 = and(_T_1658, a_first)
when _T_1659 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1660 = eq(d_first, UInt<1>(0h0))
node _T_1661 = and(io.in.d.valid, _T_1660)
when _T_1661 :
node _T_1662 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1663 = asUInt(reset)
node _T_1664 = eq(_T_1663, UInt<1>(0h0))
when _T_1664 :
node _T_1665 = eq(_T_1662, UInt<1>(0h0))
when _T_1665 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1662, UInt<1>(0h1), "") : assert_92
node _T_1666 = eq(io.in.d.bits.param, param_1)
node _T_1667 = asUInt(reset)
node _T_1668 = eq(_T_1667, UInt<1>(0h0))
when _T_1668 :
node _T_1669 = eq(_T_1666, UInt<1>(0h0))
when _T_1669 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1666, UInt<1>(0h1), "") : assert_93
node _T_1670 = eq(io.in.d.bits.size, size_1)
node _T_1671 = asUInt(reset)
node _T_1672 = eq(_T_1671, UInt<1>(0h0))
when _T_1672 :
node _T_1673 = eq(_T_1670, UInt<1>(0h0))
when _T_1673 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1670, UInt<1>(0h1), "") : assert_94
node _T_1674 = eq(io.in.d.bits.source, source_1)
node _T_1675 = asUInt(reset)
node _T_1676 = eq(_T_1675, UInt<1>(0h0))
when _T_1676 :
node _T_1677 = eq(_T_1674, UInt<1>(0h0))
when _T_1677 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1674, UInt<1>(0h1), "") : assert_95
node _T_1678 = eq(io.in.d.bits.sink, sink)
node _T_1679 = asUInt(reset)
node _T_1680 = eq(_T_1679, UInt<1>(0h0))
when _T_1680 :
node _T_1681 = eq(_T_1678, UInt<1>(0h0))
when _T_1681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1678, UInt<1>(0h1), "") : assert_96
node _T_1682 = eq(io.in.d.bits.denied, denied)
node _T_1683 = asUInt(reset)
node _T_1684 = eq(_T_1683, UInt<1>(0h0))
when _T_1684 :
node _T_1685 = eq(_T_1682, UInt<1>(0h0))
when _T_1685 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1682, UInt<1>(0h1), "") : assert_97
node _T_1686 = and(io.in.d.ready, io.in.d.valid)
node _T_1687 = and(_T_1686, d_first)
when _T_1687 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<260>
connect a_sizes_set, UInt<260>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1688 = and(io.in.a.valid, a_first_1)
node _T_1689 = and(_T_1688, UInt<1>(0h1))
when _T_1689 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1690 = and(io.in.a.ready, io.in.a.valid)
node _T_1691 = and(_T_1690, a_first_1)
node _T_1692 = and(_T_1691, UInt<1>(0h1))
when _T_1692 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1693 = dshr(inflight, io.in.a.bits.source)
node _T_1694 = bits(_T_1693, 0, 0)
node _T_1695 = eq(_T_1694, UInt<1>(0h0))
node _T_1696 = asUInt(reset)
node _T_1697 = eq(_T_1696, UInt<1>(0h0))
when _T_1697 :
node _T_1698 = eq(_T_1695, UInt<1>(0h0))
when _T_1698 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1695, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<260>
connect d_sizes_clr, UInt<260>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1699 = and(io.in.d.valid, d_first_1)
node _T_1700 = and(_T_1699, UInt<1>(0h1))
node _T_1701 = eq(d_release_ack, UInt<1>(0h0))
node _T_1702 = and(_T_1700, _T_1701)
when _T_1702 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1703 = and(io.in.d.ready, io.in.d.valid)
node _T_1704 = and(_T_1703, d_first_1)
node _T_1705 = and(_T_1704, UInt<1>(0h1))
node _T_1706 = eq(d_release_ack, UInt<1>(0h0))
node _T_1707 = and(_T_1705, _T_1706)
when _T_1707 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1708 = and(io.in.d.valid, d_first_1)
node _T_1709 = and(_T_1708, UInt<1>(0h1))
node _T_1710 = eq(d_release_ack, UInt<1>(0h0))
node _T_1711 = and(_T_1709, _T_1710)
when _T_1711 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1712 = dshr(inflight, io.in.d.bits.source)
node _T_1713 = bits(_T_1712, 0, 0)
node _T_1714 = or(_T_1713, same_cycle_resp)
node _T_1715 = asUInt(reset)
node _T_1716 = eq(_T_1715, UInt<1>(0h0))
when _T_1716 :
node _T_1717 = eq(_T_1714, UInt<1>(0h0))
when _T_1717 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1714, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1718 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1719 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1720 = or(_T_1718, _T_1719)
node _T_1721 = asUInt(reset)
node _T_1722 = eq(_T_1721, UInt<1>(0h0))
when _T_1722 :
node _T_1723 = eq(_T_1720, UInt<1>(0h0))
when _T_1723 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1720, UInt<1>(0h1), "") : assert_100
node _T_1724 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1725 = asUInt(reset)
node _T_1726 = eq(_T_1725, UInt<1>(0h0))
when _T_1726 :
node _T_1727 = eq(_T_1724, UInt<1>(0h0))
when _T_1727 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1724, UInt<1>(0h1), "") : assert_101
else :
node _T_1728 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1729 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1730 = or(_T_1728, _T_1729)
node _T_1731 = asUInt(reset)
node _T_1732 = eq(_T_1731, UInt<1>(0h0))
when _T_1732 :
node _T_1733 = eq(_T_1730, UInt<1>(0h0))
when _T_1733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1730, UInt<1>(0h1), "") : assert_102
node _T_1734 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1735 = asUInt(reset)
node _T_1736 = eq(_T_1735, UInt<1>(0h0))
when _T_1736 :
node _T_1737 = eq(_T_1734, UInt<1>(0h0))
when _T_1737 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1734, UInt<1>(0h1), "") : assert_103
node _T_1738 = and(io.in.d.valid, d_first_1)
node _T_1739 = and(_T_1738, a_first_1)
node _T_1740 = and(_T_1739, io.in.a.valid)
node _T_1741 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1742 = and(_T_1740, _T_1741)
node _T_1743 = eq(d_release_ack, UInt<1>(0h0))
node _T_1744 = and(_T_1742, _T_1743)
when _T_1744 :
node _T_1745 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1746 = or(_T_1745, io.in.a.ready)
node _T_1747 = asUInt(reset)
node _T_1748 = eq(_T_1747, UInt<1>(0h0))
when _T_1748 :
node _T_1749 = eq(_T_1746, UInt<1>(0h0))
when _T_1749 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1746, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_236
node _T_1750 = orr(inflight)
node _T_1751 = eq(_T_1750, UInt<1>(0h0))
node _T_1752 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1753 = or(_T_1751, _T_1752)
node _T_1754 = lt(watchdog, plusarg_reader.out)
node _T_1755 = or(_T_1753, _T_1754)
node _T_1756 = asUInt(reset)
node _T_1757 = eq(_T_1756, UInt<1>(0h0))
when _T_1757 :
node _T_1758 = eq(_T_1755, UInt<1>(0h0))
when _T_1758 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1755, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1759 = and(io.in.a.ready, io.in.a.valid)
node _T_1760 = and(io.in.d.ready, io.in.d.valid)
node _T_1761 = or(_T_1759, _T_1760)
when _T_1761 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<21>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<260>
connect c_sizes_set, UInt<260>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<21>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1762 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<21>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1763 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1764 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1765 = and(_T_1763, _T_1764)
node _T_1766 = and(_T_1762, _T_1765)
when _T_1766 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<21>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1767 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1768 = and(_T_1767, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<21>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1769 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1770 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1771 = and(_T_1769, _T_1770)
node _T_1772 = and(_T_1768, _T_1771)
when _T_1772 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<21>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1773 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1774 = bits(_T_1773, 0, 0)
node _T_1775 = eq(_T_1774, UInt<1>(0h0))
node _T_1776 = asUInt(reset)
node _T_1777 = eq(_T_1776, UInt<1>(0h0))
when _T_1777 :
node _T_1778 = eq(_T_1775, UInt<1>(0h0))
when _T_1778 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1775, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<260>
connect d_sizes_clr_1, UInt<260>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1779 = and(io.in.d.valid, d_first_2)
node _T_1780 = and(_T_1779, UInt<1>(0h1))
node _T_1781 = and(_T_1780, d_release_ack_1)
when _T_1781 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1782 = and(io.in.d.ready, io.in.d.valid)
node _T_1783 = and(_T_1782, d_first_2)
node _T_1784 = and(_T_1783, UInt<1>(0h1))
node _T_1785 = and(_T_1784, d_release_ack_1)
when _T_1785 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1786 = and(io.in.d.valid, d_first_2)
node _T_1787 = and(_T_1786, UInt<1>(0h1))
node _T_1788 = and(_T_1787, d_release_ack_1)
when _T_1788 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1789 = dshr(inflight_1, io.in.d.bits.source)
node _T_1790 = bits(_T_1789, 0, 0)
node _T_1791 = or(_T_1790, same_cycle_resp_1)
node _T_1792 = asUInt(reset)
node _T_1793 = eq(_T_1792, UInt<1>(0h0))
when _T_1793 :
node _T_1794 = eq(_T_1791, UInt<1>(0h0))
when _T_1794 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1791, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<21>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1795 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1796 = asUInt(reset)
node _T_1797 = eq(_T_1796, UInt<1>(0h0))
when _T_1797 :
node _T_1798 = eq(_T_1795, UInt<1>(0h0))
when _T_1798 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1795, UInt<1>(0h1), "") : assert_108
else :
node _T_1799 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1800 = asUInt(reset)
node _T_1801 = eq(_T_1800, UInt<1>(0h0))
when _T_1801 :
node _T_1802 = eq(_T_1799, UInt<1>(0h0))
when _T_1802 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1799, UInt<1>(0h1), "") : assert_109
node _T_1803 = and(io.in.d.valid, d_first_2)
node _T_1804 = and(_T_1803, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<21>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1805 = and(_T_1804, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<21>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1806 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1807 = and(_T_1805, _T_1806)
node _T_1808 = and(_T_1807, d_release_ack_1)
node _T_1809 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1810 = and(_T_1808, _T_1809)
when _T_1810 :
node _T_1811 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<21>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1812 = or(_T_1811, _WIRE_27.ready)
node _T_1813 = asUInt(reset)
node _T_1814 = eq(_T_1813, UInt<1>(0h0))
when _T_1814 :
node _T_1815 = eq(_T_1812, UInt<1>(0h0))
when _T_1815 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1812, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_237
node _T_1816 = orr(inflight_1)
node _T_1817 = eq(_T_1816, UInt<1>(0h0))
node _T_1818 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1819 = or(_T_1817, _T_1818)
node _T_1820 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1821 = or(_T_1819, _T_1820)
node _T_1822 = asUInt(reset)
node _T_1823 = eq(_T_1822, UInt<1>(0h0))
when _T_1823 :
node _T_1824 = eq(_T_1821, UInt<1>(0h0))
when _T_1824 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1821, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<21>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1825 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1826 = and(io.in.d.ready, io.in.d.valid)
node _T_1827 = or(_T_1825, _T_1826)
when _T_1827 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_100( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_14 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}}}, flip router_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, in_vc : UInt<2>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}}, flip vcalloc_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}, flip out_credit_available : { `1` : UInt<1>[1], `0` : UInt<1>[4]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<2>, sa_stall : UInt<2>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<4>, flip vc_free : UInt<4>}}
inst input_buffer of InputBuffer_14
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
connect input_buffer.io.deq[2].ready, UInt<1>(0h0)
connect input_buffer.io.deq[3].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter4_RouteComputerReq_1
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, fifo_deps : UInt<4>}[4], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id)
when _T_9 :
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h1)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
connect route_arbiter.io.in[0].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[0].bits.flow.egress_node_id
invalidate route_arbiter.io.in[0].bits.flow.egress_node
invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[0].bits.flow.ingress_node
invalidate route_arbiter.io.in[0].bits.flow.vnet_id
invalidate route_arbiter.io.in[0].bits.src_virt_id
node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1))
connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T
connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id
connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node
connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id
connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node
connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id
connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1)
node _T_10 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid)
when _T_10 :
connect states[1].g, UInt<3>(0h2)
node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1))
connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T
connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id
connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node
connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id
connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node
connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id
connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2)
node _T_11 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid)
when _T_11 :
connect states[2].g, UInt<3>(0h2)
node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1))
connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T
connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id
connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node
connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id
connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node
connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id
connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3)
node _T_12 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid)
when _T_12 :
connect states[3].g, UInt<3>(0h2)
node _T_13 = and(io.router_req.ready, io.router_req.valid)
when _T_13 :
node _T_14 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_15 = asUInt(reset)
node _T_16 = eq(_T_15, UInt<1>(0h0))
when _T_16 :
node _T_17 = eq(_T_14, UInt<1>(0h0))
when _T_17 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_14, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_18 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_18 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
node _T_19 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_19 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
node _T_20 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id)
when _T_20 :
connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
node _T_21 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id)
when _T_21 :
connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1`
regreset mask : UInt<4>, clock, reset, UInt<4>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, in_vc : UInt<2>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}[4]
wire vcalloc_vals : UInt<1>[4]
node vcalloc_filter_lo = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_hi = cat(vcalloc_vals[3], vcalloc_vals[2])
node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo)
node vcalloc_filter_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_hi_1 = cat(vcalloc_vals[3], vcalloc_vals[2])
node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1)
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4)
node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5)
node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6)
node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7)
node _vcalloc_filter_T_13 = mux(_vcalloc_filter_T_12, UInt<8>(0h80), UInt<8>(0h0))
node _vcalloc_filter_T_14 = mux(_vcalloc_filter_T_11, UInt<8>(0h40), _vcalloc_filter_T_13)
node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_10, UInt<8>(0h20), _vcalloc_filter_T_14)
node _vcalloc_filter_T_16 = mux(_vcalloc_filter_T_9, UInt<8>(0h10), _vcalloc_filter_T_15)
node _vcalloc_filter_T_17 = mux(_vcalloc_filter_T_8, UInt<8>(0h8), _vcalloc_filter_T_16)
node _vcalloc_filter_T_18 = mux(_vcalloc_filter_T_7, UInt<8>(0h4), _vcalloc_filter_T_17)
node _vcalloc_filter_T_19 = mux(_vcalloc_filter_T_6, UInt<8>(0h2), _vcalloc_filter_T_18)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<8>(0h1), _vcalloc_filter_T_19)
node _vcalloc_sel_T = bits(vcalloc_filter, 3, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 4)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_22 = and(io.router_req.ready, io.router_req.valid)
when _T_22 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_23 = or(vcalloc_vals[0], vcalloc_vals[1])
node _T_24 = or(_T_23, vcalloc_vals[2])
node _T_25 = or(_T_24, vcalloc_vals[3])
when _T_25 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = not(UInt<3>(0h0))
node _mask_T_6 = not(UInt<4>(0h0))
node _mask_T_7 = bits(vcalloc_sel, 0, 0)
node _mask_T_8 = bits(vcalloc_sel, 1, 1)
node _mask_T_9 = bits(vcalloc_sel, 2, 2)
node _mask_T_10 = bits(vcalloc_sel, 3, 3)
node _mask_T_11 = mux(_mask_T_7, _mask_T_3, UInt<1>(0h0))
node _mask_T_12 = mux(_mask_T_8, _mask_T_4, UInt<1>(0h0))
node _mask_T_13 = mux(_mask_T_9, _mask_T_5, UInt<1>(0h0))
node _mask_T_14 = mux(_mask_T_10, _mask_T_6, UInt<1>(0h0))
node _mask_T_15 = or(_mask_T_11, _mask_T_12)
node _mask_T_16 = or(_mask_T_15, _mask_T_13)
node _mask_T_17 = or(_mask_T_16, _mask_T_14)
wire _mask_WIRE : UInt<4>
connect _mask_WIRE, _mask_T_17
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2])
node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_2
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2)
node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, in_vc : UInt<2>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `1` : UInt<1>[1], `0` : UInt<1>[4]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[4]
node _io_vcalloc_req_bits_T_4 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_6 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_7 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_8 = or(_io_vcalloc_req_bits_T_4, _io_vcalloc_req_bits_T_5)
node _io_vcalloc_req_bits_T_9 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_6)
node _io_vcalloc_req_bits_T_10 = or(_io_vcalloc_req_bits_T_9, _io_vcalloc_req_bits_T_7)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_10
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_12)
node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_15, _io_vcalloc_req_bits_T_13)
node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_14)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_17
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_21 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_19)
node _io_vcalloc_req_bits_T_23 = or(_io_vcalloc_req_bits_T_22, _io_vcalloc_req_bits_T_20)
node _io_vcalloc_req_bits_T_24 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_21)
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_24
connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5
node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_29 = or(_io_vcalloc_req_bits_T_25, _io_vcalloc_req_bits_T_26)
node _io_vcalloc_req_bits_T_30 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_27)
node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_30, _io_vcalloc_req_bits_T_28)
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_31
connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>[1]
node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_33)
node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_34)
node _io_vcalloc_req_bits_T_38 = or(_io_vcalloc_req_bits_T_37, _io_vcalloc_req_bits_T_35)
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_38
connect _io_vcalloc_req_bits_WIRE_7[0], _io_vcalloc_req_bits_WIRE_8
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_7
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_43 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_40)
node _io_vcalloc_req_bits_T_44 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_41)
node _io_vcalloc_req_bits_T_45 = or(_io_vcalloc_req_bits_T_44, _io_vcalloc_req_bits_T_42)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_45
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_9
wire _io_vcalloc_req_bits_WIRE_10 : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}
node _io_vcalloc_req_bits_T_46 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_47 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_50 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_47)
node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_48)
node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_49)
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_52
connect _io_vcalloc_req_bits_WIRE_10.egress_node_id, _io_vcalloc_req_bits_WIRE_11
node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54)
node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_57, _io_vcalloc_req_bits_T_55)
node _io_vcalloc_req_bits_T_59 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_56)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_59
connect _io_vcalloc_req_bits_WIRE_10.egress_node, _io_vcalloc_req_bits_WIRE_12
node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_61 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_62 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_60, _io_vcalloc_req_bits_T_61)
node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_62)
node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_63)
wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_66
connect _io_vcalloc_req_bits_WIRE_10.ingress_node_id, _io_vcalloc_req_bits_WIRE_13
node _io_vcalloc_req_bits_T_67 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_71 = or(_io_vcalloc_req_bits_T_67, _io_vcalloc_req_bits_T_68)
node _io_vcalloc_req_bits_T_72 = or(_io_vcalloc_req_bits_T_71, _io_vcalloc_req_bits_T_69)
node _io_vcalloc_req_bits_T_73 = or(_io_vcalloc_req_bits_T_72, _io_vcalloc_req_bits_T_70)
wire _io_vcalloc_req_bits_WIRE_14 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_73
connect _io_vcalloc_req_bits_WIRE_10.ingress_node, _io_vcalloc_req_bits_WIRE_14
node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_76 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_77 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_74, _io_vcalloc_req_bits_T_75)
node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_76)
node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_77)
wire _io_vcalloc_req_bits_WIRE_15 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_80
connect _io_vcalloc_req_bits_WIRE_10.vnet_id, _io_vcalloc_req_bits_WIRE_15
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_10
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
connect vcalloc_vals[0], UInt<1>(0h0)
invalidate vcalloc_reqs[0].vc_sel.`0`[0]
invalidate vcalloc_reqs[0].vc_sel.`0`[1]
invalidate vcalloc_reqs[0].vc_sel.`0`[2]
invalidate vcalloc_reqs[0].vc_sel.`0`[3]
invalidate vcalloc_reqs[0].vc_sel.`1`[0]
invalidate vcalloc_reqs[0].in_vc
invalidate vcalloc_reqs[0].flow.egress_node_id
invalidate vcalloc_reqs[0].flow.egress_node
invalidate vcalloc_reqs[0].flow.ingress_node_id
invalidate vcalloc_reqs[0].flow.ingress_node
invalidate vcalloc_reqs[0].flow.vnet_id
node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2))
node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1)
connect vcalloc_vals[1], _vcalloc_vals_1_T_2
connect vcalloc_reqs[1].in_vc, UInt<1>(0h1)
connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0`
connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1`
connect vcalloc_reqs[1].flow, states[1].flow
node _T_26 = bits(vcalloc_sel, 1, 1)
node _T_27 = and(vcalloc_vals[1], _T_26)
node _T_28 = and(_T_27, io.vcalloc_req.ready)
when _T_28 :
connect states[1].g, UInt<3>(0h3)
node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2))
node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1)
connect vcalloc_vals[2], _vcalloc_vals_2_T_2
connect vcalloc_reqs[2].in_vc, UInt<2>(0h2)
connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0`
connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1`
connect vcalloc_reqs[2].flow, states[2].flow
node _T_29 = bits(vcalloc_sel, 2, 2)
node _T_30 = and(vcalloc_vals[2], _T_29)
node _T_31 = and(_T_30, io.vcalloc_req.ready)
when _T_31 :
connect states[2].g, UInt<3>(0h3)
node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2))
node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1)
connect vcalloc_vals[3], _vcalloc_vals_3_T_2
connect vcalloc_reqs[3].in_vc, UInt<2>(0h3)
connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0`
connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1`
connect vcalloc_reqs[3].flow, states[3].flow
node _T_32 = bits(vcalloc_sel, 3, 3)
node _T_33 = and(vcalloc_vals[3], _T_32)
node _T_34 = and(_T_33, io.vcalloc_req.ready)
when _T_34 :
connect states[3].g, UInt<3>(0h3)
node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = add(vcalloc_vals[2], vcalloc_vals[3])
node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0)
node _io_debug_va_stall_T_4 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_3)
node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 2, 0)
node _io_debug_va_stall_T_6 = sub(_io_debug_va_stall_T_5, io.vcalloc_req.ready)
node _io_debug_va_stall_T_7 = tail(_io_debug_va_stall_T_6, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_7
node _T_35 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_35 :
node _T_36 = bits(vcalloc_sel, 0, 0)
when _T_36 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].g, UInt<3>(0h3)
node _T_37 = eq(states[0].g, UInt<3>(0h2))
node _T_38 = asUInt(reset)
node _T_39 = eq(_T_38, UInt<1>(0h0))
when _T_39 :
node _T_40 = eq(_T_37, UInt<1>(0h0))
when _T_40 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3
assert(clock, _T_37, UInt<1>(0h1), "") : assert_3
node _T_41 = bits(vcalloc_sel, 1, 1)
when _T_41 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].g, UInt<3>(0h3)
node _T_42 = eq(states[1].g, UInt<3>(0h2))
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4
assert(clock, _T_42, UInt<1>(0h1), "") : assert_4
node _T_46 = bits(vcalloc_sel, 2, 2)
when _T_46 :
connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[2].g, UInt<3>(0h3)
node _T_47 = eq(states[2].g, UInt<3>(0h2))
node _T_48 = asUInt(reset)
node _T_49 = eq(_T_48, UInt<1>(0h0))
when _T_49 :
node _T_50 = eq(_T_47, UInt<1>(0h0))
when _T_50 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5
assert(clock, _T_47, UInt<1>(0h1), "") : assert_5
node _T_51 = bits(vcalloc_sel, 3, 3)
when _T_51 :
connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[3].g, UInt<3>(0h3)
node _T_52 = eq(states[3].g, UInt<3>(0h2))
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6
assert(clock, _T_52, UInt<1>(0h1), "") : assert_6
inst salloc_arb of SwitchArbiter_48
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
connect salloc_arb.io.in[0].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[0].bits.tail
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0]
node credit_available_lo = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0])
node credit_available_hi = cat(states[1].vc_sel.`0`[3], states[1].vc_sel.`0`[2])
node _credit_available_T = cat(credit_available_hi, credit_available_lo)
node _credit_available_T_1 = cat(states[1].vc_sel.`1`[0], _credit_available_T)
node credit_available_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_hi_1 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node _credit_available_T_2 = cat(credit_available_hi_1, credit_available_lo_1)
node _credit_available_T_3 = cat(io.out_credit_available.`1`[0], _credit_available_T_2)
node _credit_available_T_4 = and(_credit_available_T_1, _credit_available_T_3)
node credit_available = neq(_credit_available_T_4, UInt<1>(0h0))
node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3))
node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available)
node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid)
connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2
connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0]
connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail
node _T_56 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid)
node _T_57 = and(_T_56, input_buffer.io.deq[1].bits.tail)
when _T_57 :
connect states[1].g, UInt<3>(0h0)
connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready
node credit_available_lo_2 = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0])
node credit_available_hi_2 = cat(states[2].vc_sel.`0`[3], states[2].vc_sel.`0`[2])
node _credit_available_T_5 = cat(credit_available_hi_2, credit_available_lo_2)
node _credit_available_T_6 = cat(states[2].vc_sel.`1`[0], _credit_available_T_5)
node credit_available_lo_3 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_hi_3 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node _credit_available_T_7 = cat(credit_available_hi_3, credit_available_lo_3)
node _credit_available_T_8 = cat(io.out_credit_available.`1`[0], _credit_available_T_7)
node _credit_available_T_9 = and(_credit_available_T_6, _credit_available_T_8)
node credit_available_1 = neq(_credit_available_T_9, UInt<1>(0h0))
node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3))
node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_1)
node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid)
connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2
connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0]
connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail
node _T_58 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid)
node _T_59 = and(_T_58, input_buffer.io.deq[2].bits.tail)
when _T_59 :
connect states[2].g, UInt<3>(0h0)
connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready
node credit_available_lo_4 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0])
node credit_available_hi_4 = cat(states[3].vc_sel.`0`[3], states[3].vc_sel.`0`[2])
node _credit_available_T_10 = cat(credit_available_hi_4, credit_available_lo_4)
node _credit_available_T_11 = cat(states[3].vc_sel.`1`[0], _credit_available_T_10)
node credit_available_lo_5 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_hi_5 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node _credit_available_T_12 = cat(credit_available_hi_5, credit_available_lo_5)
node _credit_available_T_13 = cat(io.out_credit_available.`1`[0], _credit_available_T_12)
node _credit_available_T_14 = and(_credit_available_T_11, _credit_available_T_13)
node credit_available_2 = neq(_credit_available_T_14, UInt<1>(0h0))
node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3))
node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_2)
node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid)
connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2
connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0]
connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail
node _T_60 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid)
node _T_61 = and(_T_60, input_buffer.io.deq[3].bits.tail)
when _T_61 :
connect states[3].g, UInt<3>(0h0)
connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4)
node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6)
node _io_debug_sa_stall_T_8 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3)
node _io_debug_sa_stall_T_9 = bits(_io_debug_sa_stall_T_8, 1, 0)
node _io_debug_sa_stall_T_10 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_7)
node _io_debug_sa_stall_T_11 = bits(_io_debug_sa_stall_T_10, 1, 0)
node _io_debug_sa_stall_T_12 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11)
node _io_debug_sa_stall_T_13 = bits(_io_debug_sa_stall_T_12, 2, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_13
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
reg salloc_outs : { valid : UInt<1>, vid : UInt<2>, out_vid : UInt<2>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], clock
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _io_in_vc_free_T_5 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_7 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_8 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_9 = or(_io_in_vc_free_T_5, _io_in_vc_free_T_6)
node _io_in_vc_free_T_10 = or(_io_in_vc_free_T_9, _io_in_vc_free_T_7)
node _io_in_vc_free_T_11 = or(_io_in_vc_free_T_10, _io_in_vc_free_T_8)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_11
node _io_in_vc_free_T_12 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_12, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_13
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 3, 2)
node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 1, 0)
node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi)
node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo)
node _salloc_outs_0_vid_T_2 = bits(_salloc_outs_0_vid_T_1, 1, 1)
node _salloc_outs_0_vid_T_3 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_2)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T_3
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
wire vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[4]}
wire _vc_sel_WIRE : UInt<1>[4]
node _vc_sel_T_4 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_5 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_6 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_7 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_8 = or(_vc_sel_T_4, _vc_sel_T_5)
node _vc_sel_T_9 = or(_vc_sel_T_8, _vc_sel_T_6)
node _vc_sel_T_10 = or(_vc_sel_T_9, _vc_sel_T_7)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_10
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_11 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_12 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_13 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_14 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_15 = or(_vc_sel_T_11, _vc_sel_T_12)
node _vc_sel_T_16 = or(_vc_sel_T_15, _vc_sel_T_13)
node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_14)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_17
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
node _vc_sel_T_18 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_19 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_20 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_21 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_22 = or(_vc_sel_T_18, _vc_sel_T_19)
node _vc_sel_T_23 = or(_vc_sel_T_22, _vc_sel_T_20)
node _vc_sel_T_24 = or(_vc_sel_T_23, _vc_sel_T_21)
wire _vc_sel_WIRE_3 : UInt<1>
connect _vc_sel_WIRE_3, _vc_sel_T_24
connect _vc_sel_WIRE[2], _vc_sel_WIRE_3
node _vc_sel_T_25 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_26 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_27 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_28 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_29 = or(_vc_sel_T_25, _vc_sel_T_26)
node _vc_sel_T_30 = or(_vc_sel_T_29, _vc_sel_T_27)
node _vc_sel_T_31 = or(_vc_sel_T_30, _vc_sel_T_28)
wire _vc_sel_WIRE_4 : UInt<1>
connect _vc_sel_WIRE_4, _vc_sel_T_31
connect _vc_sel_WIRE[3], _vc_sel_WIRE_4
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_5 : UInt<1>[1]
node _vc_sel_T_32 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_33 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_34 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_35 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_36 = or(_vc_sel_T_32, _vc_sel_T_33)
node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_34)
node _vc_sel_T_38 = or(_vc_sel_T_37, _vc_sel_T_35)
wire _vc_sel_WIRE_6 : UInt<1>
connect _vc_sel_WIRE_6, _vc_sel_T_38
connect _vc_sel_WIRE_5[0], _vc_sel_WIRE_6
connect vc_sel.`1`, _vc_sel_WIRE_5
node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1])
node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2])
node channel_oh_0 = or(_channel_oh_T_1, vc_sel.`0`[3])
node virt_channel_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0])
node virt_channel_hi = cat(vc_sel.`0`[3], vc_sel.`0`[2])
node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo)
node virt_channel_hi_1 = bits(_virt_channel_T, 3, 2)
node virt_channel_lo_1 = bits(_virt_channel_T, 1, 0)
node _virt_channel_T_1 = orr(virt_channel_hi_1)
node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1)
node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1)
node _virt_channel_T_4 = cat(_virt_channel_T_1, _virt_channel_T_3)
node _virt_channel_T_5 = mux(channel_oh_0, _virt_channel_T_4, UInt<1>(0h0))
node _virt_channel_T_6 = mux(vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0))
node _virt_channel_T_7 = or(_virt_channel_T_5, _virt_channel_T_6)
wire virt_channel : UInt<2>
connect virt_channel, _virt_channel_T_7
node _T_62 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_62 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_payload_T_4 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_6 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_7 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_8 = or(_salloc_outs_0_flit_payload_T_4, _salloc_outs_0_flit_payload_T_5)
node _salloc_outs_0_flit_payload_T_9 = or(_salloc_outs_0_flit_payload_T_8, _salloc_outs_0_flit_payload_T_6)
node _salloc_outs_0_flit_payload_T_10 = or(_salloc_outs_0_flit_payload_T_9, _salloc_outs_0_flit_payload_T_7)
wire _salloc_outs_0_flit_payload_WIRE : UInt<37>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_10
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_head_T_4 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_6 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_7 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_8 = or(_salloc_outs_0_flit_head_T_4, _salloc_outs_0_flit_head_T_5)
node _salloc_outs_0_flit_head_T_9 = or(_salloc_outs_0_flit_head_T_8, _salloc_outs_0_flit_head_T_6)
node _salloc_outs_0_flit_head_T_10 = or(_salloc_outs_0_flit_head_T_9, _salloc_outs_0_flit_head_T_7)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_10
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_tail_T_4 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_6 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_7 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_8 = or(_salloc_outs_0_flit_tail_T_4, _salloc_outs_0_flit_tail_T_5)
node _salloc_outs_0_flit_tail_T_9 = or(_salloc_outs_0_flit_tail_T_8, _salloc_outs_0_flit_tail_T_6)
node _salloc_outs_0_flit_tail_T_10 = or(_salloc_outs_0_flit_tail_T_9, _salloc_outs_0_flit_tail_T_7)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_10
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}
node _salloc_outs_0_flit_flow_T_4 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_6 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_7 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_8 = or(_salloc_outs_0_flit_flow_T_4, _salloc_outs_0_flit_flow_T_5)
node _salloc_outs_0_flit_flow_T_9 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_6)
node _salloc_outs_0_flit_flow_T_10 = or(_salloc_outs_0_flit_flow_T_9, _salloc_outs_0_flit_flow_T_7)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<1>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_10
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_12)
node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_15, _salloc_outs_0_flit_flow_T_13)
node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_14)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_17
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_20 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_21 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_19)
node _salloc_outs_0_flit_flow_T_23 = or(_salloc_outs_0_flit_flow_T_22, _salloc_outs_0_flit_flow_T_20)
node _salloc_outs_0_flit_flow_T_24 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_21)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<1>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_24
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_29 = or(_salloc_outs_0_flit_flow_T_25, _salloc_outs_0_flit_flow_T_26)
node _salloc_outs_0_flit_flow_T_30 = or(_salloc_outs_0_flit_flow_T_29, _salloc_outs_0_flit_flow_T_27)
node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_30, _salloc_outs_0_flit_flow_T_28)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_31
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_34 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_35 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_33)
node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_34)
node _salloc_outs_0_flit_flow_T_38 = or(_salloc_outs_0_flit_flow_T_37, _salloc_outs_0_flit_flow_T_35)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<1>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_38
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
invalidate states[0].fifo_deps
invalidate states[0].flow.egress_node_id
invalidate states[0].flow.egress_node
invalidate states[0].flow.ingress_node_id
invalidate states[0].flow.ingress_node
invalidate states[0].flow.vnet_id
invalidate states[0].vc_sel.`0`[0]
invalidate states[0].vc_sel.`0`[1]
invalidate states[0].vc_sel.`0`[2]
invalidate states[0].vc_sel.`0`[3]
invalidate states[0].vc_sel.`1`[0]
invalidate states[0].g
connect states[1].vc_sel.`0`[2], UInt<1>(0h0)
connect states[1].vc_sel.`0`[3], UInt<1>(0h0)
connect states[2].vc_sel.`0`[0], UInt<1>(0h0)
connect states[2].vc_sel.`0`[1], UInt<1>(0h0)
connect states[2].vc_sel.`0`[3], UInt<1>(0h0)
connect states[3].vc_sel.`0`[0], UInt<1>(0h0)
connect states[3].vc_sel.`0`[1], UInt<1>(0h0)
node _T_63 = asUInt(reset)
when _T_63 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0)
connect states[2].g, UInt<3>(0h0)
connect states[3].g, UInt<3>(0h0) | module InputUnit_14( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [1:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_3, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [36:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [1:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [1:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [36:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [3:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [3:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_3; // @[InputUnit.scala:266:32]
wire vcalloc_vals_2; // @[InputUnit.scala:266:32]
wire vcalloc_vals_1; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [3:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [1:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [36:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [36:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [36:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [36:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_1_g; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_0; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_1_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19]
reg states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19]
reg states_1_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_2_g; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_2_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19]
reg states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19]
reg states_2_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_3_g; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_3_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19]
reg states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19]
reg states_3_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:158:7, :192:19, :229:22]
wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:158:7, :192:19, :229:22]
wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:158:7, :192:19, :229:22]
reg [3:0] mask; // @[InputUnit.scala:250:21]
wire [3:0] _vcalloc_filter_T_3 = {vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, 1'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32]
wire [7:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 8'h1 : _vcalloc_filter_T_3[1] ? 8'h2 : _vcalloc_filter_T_3[2] ? 8'h4 : _vcalloc_filter_T_3[3] ? 8'h8 : vcalloc_vals_1 ? 8'h20 : vcalloc_vals_2 ? 8'h40 : {vcalloc_vals_3, 7'h0}; // @[OneHot.scala:85:71]
wire [3:0] vcalloc_sel = vcalloc_filter[3:0] | vcalloc_filter[7:4]; // @[Mux.scala:50:70]
wire io_vcalloc_req_valid_0 = vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3; // @[package.scala:81:59]
assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:158:7, :192:19, :266:32]
assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:158:7, :192:19, :266:32]
assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:158:7, :192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36]
wire _GEN_2 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36]
wire _GEN_3 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] |
Generate the Verilog code corresponding to this FIRRTL code module Tile_223 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_479
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_223( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_479 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_20 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[9]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2])
node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3])
node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4])
node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5])
node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6])
node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7])
node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = and(_T_11, _T_24)
node _T_97 = and(_T_96, _T_37)
node _T_98 = and(_T_97, _T_50)
node _T_99 = and(_T_98, _T_63)
node _T_100 = and(_T_99, _T_71)
node _T_101 = and(_T_100, _T_79)
node _T_102 = and(_T_101, _T_87)
node _T_103 = and(_T_102, _T_95)
node _T_104 = asUInt(reset)
node _T_105 = eq(_T_104, UInt<1>(0h0))
when _T_105 :
node _T_106 = eq(_T_103, UInt<1>(0h0))
when _T_106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_103, UInt<1>(0h1), "") : assert_1
node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_107 :
node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_112 = shr(io.in.a.bits.source, 2)
node _T_113 = eq(_T_112, UInt<1>(0h0))
node _T_114 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_115 = and(_T_113, _T_114)
node _T_116 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_117 = and(_T_115, _T_116)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_118 = shr(io.in.a.bits.source, 2)
node _T_119 = eq(_T_118, UInt<1>(0h1))
node _T_120 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_121 = and(_T_119, _T_120)
node _T_122 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_123 = and(_T_121, _T_122)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_124 = shr(io.in.a.bits.source, 2)
node _T_125 = eq(_T_124, UInt<2>(0h2))
node _T_126 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_127 = and(_T_125, _T_126)
node _T_128 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_129 = and(_T_127, _T_128)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_130 = shr(io.in.a.bits.source, 2)
node _T_131 = eq(_T_130, UInt<2>(0h3))
node _T_132 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_133 = and(_T_131, _T_132)
node _T_134 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_135 = and(_T_133, _T_134)
node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_140 = or(_T_111, _T_117)
node _T_141 = or(_T_140, _T_123)
node _T_142 = or(_T_141, _T_129)
node _T_143 = or(_T_142, _T_135)
node _T_144 = or(_T_143, _T_136)
node _T_145 = or(_T_144, _T_137)
node _T_146 = or(_T_145, _T_138)
node _T_147 = or(_T_146, _T_139)
node _T_148 = and(_T_110, _T_147)
node _T_149 = or(UInt<1>(0h0), _T_148)
node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_151 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_152 = cvt(_T_151)
node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000)))
node _T_154 = asSInt(_T_153)
node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0)))
node _T_156 = and(_T_150, _T_155)
node _T_157 = or(UInt<1>(0h0), _T_156)
node _T_158 = and(_T_149, _T_157)
node _T_159 = asUInt(reset)
node _T_160 = eq(_T_159, UInt<1>(0h0))
when _T_160 :
node _T_161 = eq(_T_158, UInt<1>(0h0))
when _T_161 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_158, UInt<1>(0h1), "") : assert_2
node _T_162 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_163 = shr(io.in.a.bits.source, 2)
node _T_164 = eq(_T_163, UInt<1>(0h0))
node _T_165 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_166 = and(_T_164, _T_165)
node _T_167 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_168 = and(_T_166, _T_167)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_169 = shr(io.in.a.bits.source, 2)
node _T_170 = eq(_T_169, UInt<1>(0h1))
node _T_171 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_172 = and(_T_170, _T_171)
node _T_173 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_174 = and(_T_172, _T_173)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_175 = shr(io.in.a.bits.source, 2)
node _T_176 = eq(_T_175, UInt<2>(0h2))
node _T_177 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_178 = and(_T_176, _T_177)
node _T_179 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_180 = and(_T_178, _T_179)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_181 = shr(io.in.a.bits.source, 2)
node _T_182 = eq(_T_181, UInt<2>(0h3))
node _T_183 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_184 = and(_T_182, _T_183)
node _T_185 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_188 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_189 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_190 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[9]
connect _WIRE[0], _T_162
connect _WIRE[1], _T_168
connect _WIRE[2], _T_174
connect _WIRE[3], _T_180
connect _WIRE[4], _T_186
connect _WIRE[5], _T_187
connect _WIRE[6], _T_188
connect _WIRE[7], _T_189
connect _WIRE[8], _T_190
node _T_191 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_192 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_193 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_194 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_195 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_196 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_197 = mux(_WIRE[5], _T_191, UInt<1>(0h0))
node _T_198 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_199 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_200 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_201 = or(_T_192, _T_193)
node _T_202 = or(_T_201, _T_194)
node _T_203 = or(_T_202, _T_195)
node _T_204 = or(_T_203, _T_196)
node _T_205 = or(_T_204, _T_197)
node _T_206 = or(_T_205, _T_198)
node _T_207 = or(_T_206, _T_199)
node _T_208 = or(_T_207, _T_200)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_208
node _T_209 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_210 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_211 = and(_T_209, _T_210)
node _T_212 = or(UInt<1>(0h0), _T_211)
node _T_213 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_214 = cvt(_T_213)
node _T_215 = and(_T_214, asSInt(UInt<13>(0h1000)))
node _T_216 = asSInt(_T_215)
node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0)))
node _T_218 = and(_T_212, _T_217)
node _T_219 = or(UInt<1>(0h0), _T_218)
node _T_220 = and(_WIRE_1, _T_219)
node _T_221 = asUInt(reset)
node _T_222 = eq(_T_221, UInt<1>(0h0))
when _T_222 :
node _T_223 = eq(_T_220, UInt<1>(0h0))
when _T_223 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_220, UInt<1>(0h1), "") : assert_3
node _T_224 = asUInt(reset)
node _T_225 = eq(_T_224, UInt<1>(0h0))
when _T_225 :
node _T_226 = eq(source_ok, UInt<1>(0h0))
when _T_226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_227 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_228 = asUInt(reset)
node _T_229 = eq(_T_228, UInt<1>(0h0))
when _T_229 :
node _T_230 = eq(_T_227, UInt<1>(0h0))
when _T_230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_227, UInt<1>(0h1), "") : assert_5
node _T_231 = asUInt(reset)
node _T_232 = eq(_T_231, UInt<1>(0h0))
when _T_232 :
node _T_233 = eq(is_aligned, UInt<1>(0h0))
when _T_233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_234 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_235 = asUInt(reset)
node _T_236 = eq(_T_235, UInt<1>(0h0))
when _T_236 :
node _T_237 = eq(_T_234, UInt<1>(0h0))
when _T_237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_234, UInt<1>(0h1), "") : assert_7
node _T_238 = not(io.in.a.bits.mask)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_239, UInt<1>(0h1), "") : assert_8
node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_244 = asUInt(reset)
node _T_245 = eq(_T_244, UInt<1>(0h0))
when _T_245 :
node _T_246 = eq(_T_243, UInt<1>(0h0))
when _T_246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_243, UInt<1>(0h1), "") : assert_9
node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_247 :
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_250 = and(_T_248, _T_249)
node _T_251 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_252 = shr(io.in.a.bits.source, 2)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_255 = and(_T_253, _T_254)
node _T_256 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_257 = and(_T_255, _T_256)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_258 = shr(io.in.a.bits.source, 2)
node _T_259 = eq(_T_258, UInt<1>(0h1))
node _T_260 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_261 = and(_T_259, _T_260)
node _T_262 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_263 = and(_T_261, _T_262)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_264 = shr(io.in.a.bits.source, 2)
node _T_265 = eq(_T_264, UInt<2>(0h2))
node _T_266 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_267 = and(_T_265, _T_266)
node _T_268 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_269 = and(_T_267, _T_268)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_270 = shr(io.in.a.bits.source, 2)
node _T_271 = eq(_T_270, UInt<2>(0h3))
node _T_272 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_273 = and(_T_271, _T_272)
node _T_274 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_275 = and(_T_273, _T_274)
node _T_276 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_277 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_278 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_279 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_280 = or(_T_251, _T_257)
node _T_281 = or(_T_280, _T_263)
node _T_282 = or(_T_281, _T_269)
node _T_283 = or(_T_282, _T_275)
node _T_284 = or(_T_283, _T_276)
node _T_285 = or(_T_284, _T_277)
node _T_286 = or(_T_285, _T_278)
node _T_287 = or(_T_286, _T_279)
node _T_288 = and(_T_250, _T_287)
node _T_289 = or(UInt<1>(0h0), _T_288)
node _T_290 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_291 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_292 = cvt(_T_291)
node _T_293 = and(_T_292, asSInt(UInt<13>(0h1000)))
node _T_294 = asSInt(_T_293)
node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0)))
node _T_296 = and(_T_290, _T_295)
node _T_297 = or(UInt<1>(0h0), _T_296)
node _T_298 = and(_T_289, _T_297)
node _T_299 = asUInt(reset)
node _T_300 = eq(_T_299, UInt<1>(0h0))
when _T_300 :
node _T_301 = eq(_T_298, UInt<1>(0h0))
when _T_301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_298, UInt<1>(0h1), "") : assert_10
node _T_302 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_303 = shr(io.in.a.bits.source, 2)
node _T_304 = eq(_T_303, UInt<1>(0h0))
node _T_305 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_306 = and(_T_304, _T_305)
node _T_307 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_308 = and(_T_306, _T_307)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_309 = shr(io.in.a.bits.source, 2)
node _T_310 = eq(_T_309, UInt<1>(0h1))
node _T_311 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_312 = and(_T_310, _T_311)
node _T_313 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_314 = and(_T_312, _T_313)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_315 = shr(io.in.a.bits.source, 2)
node _T_316 = eq(_T_315, UInt<2>(0h2))
node _T_317 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_318 = and(_T_316, _T_317)
node _T_319 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_321 = shr(io.in.a.bits.source, 2)
node _T_322 = eq(_T_321, UInt<2>(0h3))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_326 = and(_T_324, _T_325)
node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_330 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[9]
connect _WIRE_2[0], _T_302
connect _WIRE_2[1], _T_308
connect _WIRE_2[2], _T_314
connect _WIRE_2[3], _T_320
connect _WIRE_2[4], _T_326
connect _WIRE_2[5], _T_327
connect _WIRE_2[6], _T_328
connect _WIRE_2[7], _T_329
connect _WIRE_2[8], _T_330
node _T_331 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_332 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_333 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_334 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_335 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_336 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_337 = mux(_WIRE_2[5], _T_331, UInt<1>(0h0))
node _T_338 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_339 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_340 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_341 = or(_T_332, _T_333)
node _T_342 = or(_T_341, _T_334)
node _T_343 = or(_T_342, _T_335)
node _T_344 = or(_T_343, _T_336)
node _T_345 = or(_T_344, _T_337)
node _T_346 = or(_T_345, _T_338)
node _T_347 = or(_T_346, _T_339)
node _T_348 = or(_T_347, _T_340)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_348
node _T_349 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_350 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_351 = and(_T_349, _T_350)
node _T_352 = or(UInt<1>(0h0), _T_351)
node _T_353 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_354 = cvt(_T_353)
node _T_355 = and(_T_354, asSInt(UInt<13>(0h1000)))
node _T_356 = asSInt(_T_355)
node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0)))
node _T_358 = and(_T_352, _T_357)
node _T_359 = or(UInt<1>(0h0), _T_358)
node _T_360 = and(_WIRE_3, _T_359)
node _T_361 = asUInt(reset)
node _T_362 = eq(_T_361, UInt<1>(0h0))
when _T_362 :
node _T_363 = eq(_T_360, UInt<1>(0h0))
when _T_363 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_360, UInt<1>(0h1), "") : assert_11
node _T_364 = asUInt(reset)
node _T_365 = eq(_T_364, UInt<1>(0h0))
when _T_365 :
node _T_366 = eq(source_ok, UInt<1>(0h0))
when _T_366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_367 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_368 = asUInt(reset)
node _T_369 = eq(_T_368, UInt<1>(0h0))
when _T_369 :
node _T_370 = eq(_T_367, UInt<1>(0h0))
when _T_370 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_367, UInt<1>(0h1), "") : assert_13
node _T_371 = asUInt(reset)
node _T_372 = eq(_T_371, UInt<1>(0h0))
when _T_372 :
node _T_373 = eq(is_aligned, UInt<1>(0h0))
when _T_373 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_374 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_375 = asUInt(reset)
node _T_376 = eq(_T_375, UInt<1>(0h0))
when _T_376 :
node _T_377 = eq(_T_374, UInt<1>(0h0))
when _T_377 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_374, UInt<1>(0h1), "") : assert_15
node _T_378 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_T_378, UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_378, UInt<1>(0h1), "") : assert_16
node _T_382 = not(io.in.a.bits.mask)
node _T_383 = eq(_T_382, UInt<1>(0h0))
node _T_384 = asUInt(reset)
node _T_385 = eq(_T_384, UInt<1>(0h0))
when _T_385 :
node _T_386 = eq(_T_383, UInt<1>(0h0))
when _T_386 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_383, UInt<1>(0h1), "") : assert_17
node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_387, UInt<1>(0h1), "") : assert_18
node _T_391 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_391 :
node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_394 = and(_T_392, _T_393)
node _T_395 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_396 = shr(io.in.a.bits.source, 2)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_399 = and(_T_397, _T_398)
node _T_400 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_401 = and(_T_399, _T_400)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_402 = shr(io.in.a.bits.source, 2)
node _T_403 = eq(_T_402, UInt<1>(0h1))
node _T_404 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_405 = and(_T_403, _T_404)
node _T_406 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_407 = and(_T_405, _T_406)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_408 = shr(io.in.a.bits.source, 2)
node _T_409 = eq(_T_408, UInt<2>(0h2))
node _T_410 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_411 = and(_T_409, _T_410)
node _T_412 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_413 = and(_T_411, _T_412)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_414 = shr(io.in.a.bits.source, 2)
node _T_415 = eq(_T_414, UInt<2>(0h3))
node _T_416 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_417 = and(_T_415, _T_416)
node _T_418 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_419 = and(_T_417, _T_418)
node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_423 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_424 = or(_T_395, _T_401)
node _T_425 = or(_T_424, _T_407)
node _T_426 = or(_T_425, _T_413)
node _T_427 = or(_T_426, _T_419)
node _T_428 = or(_T_427, _T_420)
node _T_429 = or(_T_428, _T_421)
node _T_430 = or(_T_429, _T_422)
node _T_431 = or(_T_430, _T_423)
node _T_432 = and(_T_394, _T_431)
node _T_433 = or(UInt<1>(0h0), _T_432)
node _T_434 = asUInt(reset)
node _T_435 = eq(_T_434, UInt<1>(0h0))
when _T_435 :
node _T_436 = eq(_T_433, UInt<1>(0h0))
when _T_436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_433, UInt<1>(0h1), "") : assert_19
node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_438 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_439 = and(_T_437, _T_438)
node _T_440 = or(UInt<1>(0h0), _T_439)
node _T_441 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_442 = cvt(_T_441)
node _T_443 = and(_T_442, asSInt(UInt<13>(0h1000)))
node _T_444 = asSInt(_T_443)
node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0)))
node _T_446 = and(_T_440, _T_445)
node _T_447 = or(UInt<1>(0h0), _T_446)
node _T_448 = asUInt(reset)
node _T_449 = eq(_T_448, UInt<1>(0h0))
when _T_449 :
node _T_450 = eq(_T_447, UInt<1>(0h0))
when _T_450 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_447, UInt<1>(0h1), "") : assert_20
node _T_451 = asUInt(reset)
node _T_452 = eq(_T_451, UInt<1>(0h0))
when _T_452 :
node _T_453 = eq(source_ok, UInt<1>(0h0))
when _T_453 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_454 = asUInt(reset)
node _T_455 = eq(_T_454, UInt<1>(0h0))
when _T_455 :
node _T_456 = eq(is_aligned, UInt<1>(0h0))
when _T_456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_457 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_T_457, UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_457, UInt<1>(0h1), "") : assert_23
node _T_461 = eq(io.in.a.bits.mask, mask)
node _T_462 = asUInt(reset)
node _T_463 = eq(_T_462, UInt<1>(0h0))
when _T_463 :
node _T_464 = eq(_T_461, UInt<1>(0h0))
when _T_464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_461, UInt<1>(0h1), "") : assert_24
node _T_465 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_466 = asUInt(reset)
node _T_467 = eq(_T_466, UInt<1>(0h0))
when _T_467 :
node _T_468 = eq(_T_465, UInt<1>(0h0))
when _T_468 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_465, UInt<1>(0h1), "") : assert_25
node _T_469 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_469 :
node _T_470 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_471 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_472 = and(_T_470, _T_471)
node _T_473 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_474 = shr(io.in.a.bits.source, 2)
node _T_475 = eq(_T_474, UInt<1>(0h0))
node _T_476 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_477 = and(_T_475, _T_476)
node _T_478 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_479 = and(_T_477, _T_478)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_480 = shr(io.in.a.bits.source, 2)
node _T_481 = eq(_T_480, UInt<1>(0h1))
node _T_482 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_483 = and(_T_481, _T_482)
node _T_484 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_485 = and(_T_483, _T_484)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_486 = shr(io.in.a.bits.source, 2)
node _T_487 = eq(_T_486, UInt<2>(0h2))
node _T_488 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_489 = and(_T_487, _T_488)
node _T_490 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_491 = and(_T_489, _T_490)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_492 = shr(io.in.a.bits.source, 2)
node _T_493 = eq(_T_492, UInt<2>(0h3))
node _T_494 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_495 = and(_T_493, _T_494)
node _T_496 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_497 = and(_T_495, _T_496)
node _T_498 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_499 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_500 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_501 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_502 = or(_T_473, _T_479)
node _T_503 = or(_T_502, _T_485)
node _T_504 = or(_T_503, _T_491)
node _T_505 = or(_T_504, _T_497)
node _T_506 = or(_T_505, _T_498)
node _T_507 = or(_T_506, _T_499)
node _T_508 = or(_T_507, _T_500)
node _T_509 = or(_T_508, _T_501)
node _T_510 = and(_T_472, _T_509)
node _T_511 = or(UInt<1>(0h0), _T_510)
node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_513 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_514 = and(_T_512, _T_513)
node _T_515 = or(UInt<1>(0h0), _T_514)
node _T_516 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_517 = cvt(_T_516)
node _T_518 = and(_T_517, asSInt(UInt<13>(0h1000)))
node _T_519 = asSInt(_T_518)
node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0)))
node _T_521 = and(_T_515, _T_520)
node _T_522 = or(UInt<1>(0h0), _T_521)
node _T_523 = and(_T_511, _T_522)
node _T_524 = asUInt(reset)
node _T_525 = eq(_T_524, UInt<1>(0h0))
when _T_525 :
node _T_526 = eq(_T_523, UInt<1>(0h0))
when _T_526 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_523, UInt<1>(0h1), "") : assert_26
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(source_ok, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_530 = asUInt(reset)
node _T_531 = eq(_T_530, UInt<1>(0h0))
when _T_531 :
node _T_532 = eq(is_aligned, UInt<1>(0h0))
when _T_532 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_533 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_534 = asUInt(reset)
node _T_535 = eq(_T_534, UInt<1>(0h0))
when _T_535 :
node _T_536 = eq(_T_533, UInt<1>(0h0))
when _T_536 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_533, UInt<1>(0h1), "") : assert_29
node _T_537 = eq(io.in.a.bits.mask, mask)
node _T_538 = asUInt(reset)
node _T_539 = eq(_T_538, UInt<1>(0h0))
when _T_539 :
node _T_540 = eq(_T_537, UInt<1>(0h0))
when _T_540 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_537, UInt<1>(0h1), "") : assert_30
node _T_541 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_541 :
node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_543 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_544 = and(_T_542, _T_543)
node _T_545 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_546 = shr(io.in.a.bits.source, 2)
node _T_547 = eq(_T_546, UInt<1>(0h0))
node _T_548 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_549 = and(_T_547, _T_548)
node _T_550 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_551 = and(_T_549, _T_550)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_552 = shr(io.in.a.bits.source, 2)
node _T_553 = eq(_T_552, UInt<1>(0h1))
node _T_554 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_555 = and(_T_553, _T_554)
node _T_556 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_557 = and(_T_555, _T_556)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_558 = shr(io.in.a.bits.source, 2)
node _T_559 = eq(_T_558, UInt<2>(0h2))
node _T_560 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_561 = and(_T_559, _T_560)
node _T_562 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_563 = and(_T_561, _T_562)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_564 = shr(io.in.a.bits.source, 2)
node _T_565 = eq(_T_564, UInt<2>(0h3))
node _T_566 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_567 = and(_T_565, _T_566)
node _T_568 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_569 = and(_T_567, _T_568)
node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_573 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_574 = or(_T_545, _T_551)
node _T_575 = or(_T_574, _T_557)
node _T_576 = or(_T_575, _T_563)
node _T_577 = or(_T_576, _T_569)
node _T_578 = or(_T_577, _T_570)
node _T_579 = or(_T_578, _T_571)
node _T_580 = or(_T_579, _T_572)
node _T_581 = or(_T_580, _T_573)
node _T_582 = and(_T_544, _T_581)
node _T_583 = or(UInt<1>(0h0), _T_582)
node _T_584 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_585 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_586 = and(_T_584, _T_585)
node _T_587 = or(UInt<1>(0h0), _T_586)
node _T_588 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_589 = cvt(_T_588)
node _T_590 = and(_T_589, asSInt(UInt<13>(0h1000)))
node _T_591 = asSInt(_T_590)
node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0)))
node _T_593 = and(_T_587, _T_592)
node _T_594 = or(UInt<1>(0h0), _T_593)
node _T_595 = and(_T_583, _T_594)
node _T_596 = asUInt(reset)
node _T_597 = eq(_T_596, UInt<1>(0h0))
when _T_597 :
node _T_598 = eq(_T_595, UInt<1>(0h0))
when _T_598 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_595, UInt<1>(0h1), "") : assert_31
node _T_599 = asUInt(reset)
node _T_600 = eq(_T_599, UInt<1>(0h0))
when _T_600 :
node _T_601 = eq(source_ok, UInt<1>(0h0))
when _T_601 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(is_aligned, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_605 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_606 = asUInt(reset)
node _T_607 = eq(_T_606, UInt<1>(0h0))
when _T_607 :
node _T_608 = eq(_T_605, UInt<1>(0h0))
when _T_608 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_605, UInt<1>(0h1), "") : assert_34
node _T_609 = not(mask)
node _T_610 = and(io.in.a.bits.mask, _T_609)
node _T_611 = eq(_T_610, UInt<1>(0h0))
node _T_612 = asUInt(reset)
node _T_613 = eq(_T_612, UInt<1>(0h0))
when _T_613 :
node _T_614 = eq(_T_611, UInt<1>(0h0))
when _T_614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_611, UInt<1>(0h1), "") : assert_35
node _T_615 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_615 :
node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_618 = and(_T_616, _T_617)
node _T_619 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_620 = shr(io.in.a.bits.source, 2)
node _T_621 = eq(_T_620, UInt<1>(0h0))
node _T_622 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_623 = and(_T_621, _T_622)
node _T_624 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_625 = and(_T_623, _T_624)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_626 = shr(io.in.a.bits.source, 2)
node _T_627 = eq(_T_626, UInt<1>(0h1))
node _T_628 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_629 = and(_T_627, _T_628)
node _T_630 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_631 = and(_T_629, _T_630)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_632 = shr(io.in.a.bits.source, 2)
node _T_633 = eq(_T_632, UInt<2>(0h2))
node _T_634 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_635 = and(_T_633, _T_634)
node _T_636 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_637 = and(_T_635, _T_636)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_638 = shr(io.in.a.bits.source, 2)
node _T_639 = eq(_T_638, UInt<2>(0h3))
node _T_640 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_641 = and(_T_639, _T_640)
node _T_642 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_643 = and(_T_641, _T_642)
node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_648 = or(_T_619, _T_625)
node _T_649 = or(_T_648, _T_631)
node _T_650 = or(_T_649, _T_637)
node _T_651 = or(_T_650, _T_643)
node _T_652 = or(_T_651, _T_644)
node _T_653 = or(_T_652, _T_645)
node _T_654 = or(_T_653, _T_646)
node _T_655 = or(_T_654, _T_647)
node _T_656 = and(_T_618, _T_655)
node _T_657 = or(UInt<1>(0h0), _T_656)
node _T_658 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_659 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_660 = and(_T_658, _T_659)
node _T_661 = or(UInt<1>(0h0), _T_660)
node _T_662 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_663 = cvt(_T_662)
node _T_664 = and(_T_663, asSInt(UInt<13>(0h1000)))
node _T_665 = asSInt(_T_664)
node _T_666 = eq(_T_665, asSInt(UInt<1>(0h0)))
node _T_667 = and(_T_661, _T_666)
node _T_668 = or(UInt<1>(0h0), _T_667)
node _T_669 = and(_T_657, _T_668)
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(_T_669, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_669, UInt<1>(0h1), "") : assert_36
node _T_673 = asUInt(reset)
node _T_674 = eq(_T_673, UInt<1>(0h0))
when _T_674 :
node _T_675 = eq(source_ok, UInt<1>(0h0))
when _T_675 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_676 = asUInt(reset)
node _T_677 = eq(_T_676, UInt<1>(0h0))
when _T_677 :
node _T_678 = eq(is_aligned, UInt<1>(0h0))
when _T_678 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_679 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_680 = asUInt(reset)
node _T_681 = eq(_T_680, UInt<1>(0h0))
when _T_681 :
node _T_682 = eq(_T_679, UInt<1>(0h0))
when _T_682 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_679, UInt<1>(0h1), "") : assert_39
node _T_683 = eq(io.in.a.bits.mask, mask)
node _T_684 = asUInt(reset)
node _T_685 = eq(_T_684, UInt<1>(0h0))
when _T_685 :
node _T_686 = eq(_T_683, UInt<1>(0h0))
when _T_686 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_683, UInt<1>(0h1), "") : assert_40
node _T_687 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_687 :
node _T_688 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_689 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_690 = and(_T_688, _T_689)
node _T_691 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_692 = shr(io.in.a.bits.source, 2)
node _T_693 = eq(_T_692, UInt<1>(0h0))
node _T_694 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_695 = and(_T_693, _T_694)
node _T_696 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_697 = and(_T_695, _T_696)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_698 = shr(io.in.a.bits.source, 2)
node _T_699 = eq(_T_698, UInt<1>(0h1))
node _T_700 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_701 = and(_T_699, _T_700)
node _T_702 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_703 = and(_T_701, _T_702)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_704 = shr(io.in.a.bits.source, 2)
node _T_705 = eq(_T_704, UInt<2>(0h2))
node _T_706 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_707 = and(_T_705, _T_706)
node _T_708 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_709 = and(_T_707, _T_708)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_710 = shr(io.in.a.bits.source, 2)
node _T_711 = eq(_T_710, UInt<2>(0h3))
node _T_712 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_713 = and(_T_711, _T_712)
node _T_714 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_715 = and(_T_713, _T_714)
node _T_716 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_717 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_718 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_719 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_720 = or(_T_691, _T_697)
node _T_721 = or(_T_720, _T_703)
node _T_722 = or(_T_721, _T_709)
node _T_723 = or(_T_722, _T_715)
node _T_724 = or(_T_723, _T_716)
node _T_725 = or(_T_724, _T_717)
node _T_726 = or(_T_725, _T_718)
node _T_727 = or(_T_726, _T_719)
node _T_728 = and(_T_690, _T_727)
node _T_729 = or(UInt<1>(0h0), _T_728)
node _T_730 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_731 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_732 = and(_T_730, _T_731)
node _T_733 = or(UInt<1>(0h0), _T_732)
node _T_734 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_735 = cvt(_T_734)
node _T_736 = and(_T_735, asSInt(UInt<13>(0h1000)))
node _T_737 = asSInt(_T_736)
node _T_738 = eq(_T_737, asSInt(UInt<1>(0h0)))
node _T_739 = and(_T_733, _T_738)
node _T_740 = or(UInt<1>(0h0), _T_739)
node _T_741 = and(_T_729, _T_740)
node _T_742 = asUInt(reset)
node _T_743 = eq(_T_742, UInt<1>(0h0))
when _T_743 :
node _T_744 = eq(_T_741, UInt<1>(0h0))
when _T_744 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_741, UInt<1>(0h1), "") : assert_41
node _T_745 = asUInt(reset)
node _T_746 = eq(_T_745, UInt<1>(0h0))
when _T_746 :
node _T_747 = eq(source_ok, UInt<1>(0h0))
when _T_747 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_748 = asUInt(reset)
node _T_749 = eq(_T_748, UInt<1>(0h0))
when _T_749 :
node _T_750 = eq(is_aligned, UInt<1>(0h0))
when _T_750 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_751 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_752 = asUInt(reset)
node _T_753 = eq(_T_752, UInt<1>(0h0))
when _T_753 :
node _T_754 = eq(_T_751, UInt<1>(0h0))
when _T_754 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_751, UInt<1>(0h1), "") : assert_44
node _T_755 = eq(io.in.a.bits.mask, mask)
node _T_756 = asUInt(reset)
node _T_757 = eq(_T_756, UInt<1>(0h0))
when _T_757 :
node _T_758 = eq(_T_755, UInt<1>(0h0))
when _T_758 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_755, UInt<1>(0h1), "") : assert_45
node _T_759 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_759 :
node _T_760 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_761 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_762 = and(_T_760, _T_761)
node _T_763 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_764 = shr(io.in.a.bits.source, 2)
node _T_765 = eq(_T_764, UInt<1>(0h0))
node _T_766 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_767 = and(_T_765, _T_766)
node _T_768 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_769 = and(_T_767, _T_768)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_770 = shr(io.in.a.bits.source, 2)
node _T_771 = eq(_T_770, UInt<1>(0h1))
node _T_772 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_773 = and(_T_771, _T_772)
node _T_774 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_775 = and(_T_773, _T_774)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_776 = shr(io.in.a.bits.source, 2)
node _T_777 = eq(_T_776, UInt<2>(0h2))
node _T_778 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_779 = and(_T_777, _T_778)
node _T_780 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_781 = and(_T_779, _T_780)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_782 = shr(io.in.a.bits.source, 2)
node _T_783 = eq(_T_782, UInt<2>(0h3))
node _T_784 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_785 = and(_T_783, _T_784)
node _T_786 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_787 = and(_T_785, _T_786)
node _T_788 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_789 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_790 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_791 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_792 = or(_T_763, _T_769)
node _T_793 = or(_T_792, _T_775)
node _T_794 = or(_T_793, _T_781)
node _T_795 = or(_T_794, _T_787)
node _T_796 = or(_T_795, _T_788)
node _T_797 = or(_T_796, _T_789)
node _T_798 = or(_T_797, _T_790)
node _T_799 = or(_T_798, _T_791)
node _T_800 = and(_T_762, _T_799)
node _T_801 = or(UInt<1>(0h0), _T_800)
node _T_802 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_803 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_804 = and(_T_802, _T_803)
node _T_805 = or(UInt<1>(0h0), _T_804)
node _T_806 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_807 = cvt(_T_806)
node _T_808 = and(_T_807, asSInt(UInt<13>(0h1000)))
node _T_809 = asSInt(_T_808)
node _T_810 = eq(_T_809, asSInt(UInt<1>(0h0)))
node _T_811 = and(_T_805, _T_810)
node _T_812 = or(UInt<1>(0h0), _T_811)
node _T_813 = and(_T_801, _T_812)
node _T_814 = asUInt(reset)
node _T_815 = eq(_T_814, UInt<1>(0h0))
when _T_815 :
node _T_816 = eq(_T_813, UInt<1>(0h0))
when _T_816 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_813, UInt<1>(0h1), "") : assert_46
node _T_817 = asUInt(reset)
node _T_818 = eq(_T_817, UInt<1>(0h0))
when _T_818 :
node _T_819 = eq(source_ok, UInt<1>(0h0))
when _T_819 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_820 = asUInt(reset)
node _T_821 = eq(_T_820, UInt<1>(0h0))
when _T_821 :
node _T_822 = eq(is_aligned, UInt<1>(0h0))
when _T_822 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_823 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_824 = asUInt(reset)
node _T_825 = eq(_T_824, UInt<1>(0h0))
when _T_825 :
node _T_826 = eq(_T_823, UInt<1>(0h0))
when _T_826 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_823, UInt<1>(0h1), "") : assert_49
node _T_827 = eq(io.in.a.bits.mask, mask)
node _T_828 = asUInt(reset)
node _T_829 = eq(_T_828, UInt<1>(0h0))
when _T_829 :
node _T_830 = eq(_T_827, UInt<1>(0h0))
when _T_830 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_827, UInt<1>(0h1), "") : assert_50
node _T_831 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_832 = asUInt(reset)
node _T_833 = eq(_T_832, UInt<1>(0h0))
when _T_833 :
node _T_834 = eq(_T_831, UInt<1>(0h0))
when _T_834 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_831, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_835 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_836 = asUInt(reset)
node _T_837 = eq(_T_836, UInt<1>(0h0))
when _T_837 :
node _T_838 = eq(_T_835, UInt<1>(0h0))
when _T_838 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_835, UInt<1>(0h1), "") : assert_52
node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_37 = shr(io.in.d.bits.source, 2)
node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0))
node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39)
node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_43 = shr(io.in.d.bits.source, 2)
node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1))
node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45)
node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_49 = shr(io.in.d.bits.source, 2)
node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2))
node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51)
node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_55 = shr(io.in.d.bits.source, 2)
node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3))
node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57)
node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h22))
node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[9]
connect _source_ok_WIRE_1[0], _source_ok_T_36
connect _source_ok_WIRE_1[1], _source_ok_T_42
connect _source_ok_WIRE_1[2], _source_ok_T_48
connect _source_ok_WIRE_1[3], _source_ok_T_54
connect _source_ok_WIRE_1[4], _source_ok_T_60
connect _source_ok_WIRE_1[5], _source_ok_T_61
connect _source_ok_WIRE_1[6], _source_ok_T_62
connect _source_ok_WIRE_1[7], _source_ok_T_63
connect _source_ok_WIRE_1[8], _source_ok_T_64
node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2])
node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3])
node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4])
node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5])
node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6])
node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7])
node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_839 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_839 :
node _T_840 = asUInt(reset)
node _T_841 = eq(_T_840, UInt<1>(0h0))
when _T_841 :
node _T_842 = eq(source_ok_1, UInt<1>(0h0))
when _T_842 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_843 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_844 = asUInt(reset)
node _T_845 = eq(_T_844, UInt<1>(0h0))
when _T_845 :
node _T_846 = eq(_T_843, UInt<1>(0h0))
when _T_846 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_843, UInt<1>(0h1), "") : assert_54
node _T_847 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_848 = asUInt(reset)
node _T_849 = eq(_T_848, UInt<1>(0h0))
when _T_849 :
node _T_850 = eq(_T_847, UInt<1>(0h0))
when _T_850 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_847, UInt<1>(0h1), "") : assert_55
node _T_851 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_852 = asUInt(reset)
node _T_853 = eq(_T_852, UInt<1>(0h0))
when _T_853 :
node _T_854 = eq(_T_851, UInt<1>(0h0))
when _T_854 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_851, UInt<1>(0h1), "") : assert_56
node _T_855 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_856 = asUInt(reset)
node _T_857 = eq(_T_856, UInt<1>(0h0))
when _T_857 :
node _T_858 = eq(_T_855, UInt<1>(0h0))
when _T_858 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_855, UInt<1>(0h1), "") : assert_57
node _T_859 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_859 :
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(source_ok_1, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_863 = asUInt(reset)
node _T_864 = eq(_T_863, UInt<1>(0h0))
when _T_864 :
node _T_865 = eq(sink_ok, UInt<1>(0h0))
when _T_865 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_866 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_867 = asUInt(reset)
node _T_868 = eq(_T_867, UInt<1>(0h0))
when _T_868 :
node _T_869 = eq(_T_866, UInt<1>(0h0))
when _T_869 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_866, UInt<1>(0h1), "") : assert_60
node _T_870 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_871 = asUInt(reset)
node _T_872 = eq(_T_871, UInt<1>(0h0))
when _T_872 :
node _T_873 = eq(_T_870, UInt<1>(0h0))
when _T_873 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_870, UInt<1>(0h1), "") : assert_61
node _T_874 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_875 = asUInt(reset)
node _T_876 = eq(_T_875, UInt<1>(0h0))
when _T_876 :
node _T_877 = eq(_T_874, UInt<1>(0h0))
when _T_877 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_874, UInt<1>(0h1), "") : assert_62
node _T_878 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_879 = asUInt(reset)
node _T_880 = eq(_T_879, UInt<1>(0h0))
when _T_880 :
node _T_881 = eq(_T_878, UInt<1>(0h0))
when _T_881 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_878, UInt<1>(0h1), "") : assert_63
node _T_882 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_883 = or(UInt<1>(0h1), _T_882)
node _T_884 = asUInt(reset)
node _T_885 = eq(_T_884, UInt<1>(0h0))
when _T_885 :
node _T_886 = eq(_T_883, UInt<1>(0h0))
when _T_886 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_883, UInt<1>(0h1), "") : assert_64
node _T_887 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_887 :
node _T_888 = asUInt(reset)
node _T_889 = eq(_T_888, UInt<1>(0h0))
when _T_889 :
node _T_890 = eq(source_ok_1, UInt<1>(0h0))
when _T_890 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_891 = asUInt(reset)
node _T_892 = eq(_T_891, UInt<1>(0h0))
when _T_892 :
node _T_893 = eq(sink_ok, UInt<1>(0h0))
when _T_893 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_894 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_895 = asUInt(reset)
node _T_896 = eq(_T_895, UInt<1>(0h0))
when _T_896 :
node _T_897 = eq(_T_894, UInt<1>(0h0))
when _T_897 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_894, UInt<1>(0h1), "") : assert_67
node _T_898 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_899 = asUInt(reset)
node _T_900 = eq(_T_899, UInt<1>(0h0))
when _T_900 :
node _T_901 = eq(_T_898, UInt<1>(0h0))
when _T_901 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_898, UInt<1>(0h1), "") : assert_68
node _T_902 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_903 = asUInt(reset)
node _T_904 = eq(_T_903, UInt<1>(0h0))
when _T_904 :
node _T_905 = eq(_T_902, UInt<1>(0h0))
when _T_905 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_902, UInt<1>(0h1), "") : assert_69
node _T_906 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_907 = or(_T_906, io.in.d.bits.corrupt)
node _T_908 = asUInt(reset)
node _T_909 = eq(_T_908, UInt<1>(0h0))
when _T_909 :
node _T_910 = eq(_T_907, UInt<1>(0h0))
when _T_910 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_907, UInt<1>(0h1), "") : assert_70
node _T_911 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_912 = or(UInt<1>(0h1), _T_911)
node _T_913 = asUInt(reset)
node _T_914 = eq(_T_913, UInt<1>(0h0))
when _T_914 :
node _T_915 = eq(_T_912, UInt<1>(0h0))
when _T_915 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_912, UInt<1>(0h1), "") : assert_71
node _T_916 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_916 :
node _T_917 = asUInt(reset)
node _T_918 = eq(_T_917, UInt<1>(0h0))
when _T_918 :
node _T_919 = eq(source_ok_1, UInt<1>(0h0))
when _T_919 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_920 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_921 = asUInt(reset)
node _T_922 = eq(_T_921, UInt<1>(0h0))
when _T_922 :
node _T_923 = eq(_T_920, UInt<1>(0h0))
when _T_923 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_920, UInt<1>(0h1), "") : assert_73
node _T_924 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_925 = asUInt(reset)
node _T_926 = eq(_T_925, UInt<1>(0h0))
when _T_926 :
node _T_927 = eq(_T_924, UInt<1>(0h0))
when _T_927 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_924, UInt<1>(0h1), "") : assert_74
node _T_928 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_929 = or(UInt<1>(0h1), _T_928)
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_T_929, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_929, UInt<1>(0h1), "") : assert_75
node _T_933 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_933 :
node _T_934 = asUInt(reset)
node _T_935 = eq(_T_934, UInt<1>(0h0))
when _T_935 :
node _T_936 = eq(source_ok_1, UInt<1>(0h0))
when _T_936 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_937 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_938 = asUInt(reset)
node _T_939 = eq(_T_938, UInt<1>(0h0))
when _T_939 :
node _T_940 = eq(_T_937, UInt<1>(0h0))
when _T_940 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_937, UInt<1>(0h1), "") : assert_77
node _T_941 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_942 = or(_T_941, io.in.d.bits.corrupt)
node _T_943 = asUInt(reset)
node _T_944 = eq(_T_943, UInt<1>(0h0))
when _T_944 :
node _T_945 = eq(_T_942, UInt<1>(0h0))
when _T_945 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_942, UInt<1>(0h1), "") : assert_78
node _T_946 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_947 = or(UInt<1>(0h1), _T_946)
node _T_948 = asUInt(reset)
node _T_949 = eq(_T_948, UInt<1>(0h0))
when _T_949 :
node _T_950 = eq(_T_947, UInt<1>(0h0))
when _T_950 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_947, UInt<1>(0h1), "") : assert_79
node _T_951 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_951 :
node _T_952 = asUInt(reset)
node _T_953 = eq(_T_952, UInt<1>(0h0))
when _T_953 :
node _T_954 = eq(source_ok_1, UInt<1>(0h0))
when _T_954 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_955 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_956 = asUInt(reset)
node _T_957 = eq(_T_956, UInt<1>(0h0))
when _T_957 :
node _T_958 = eq(_T_955, UInt<1>(0h0))
when _T_958 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_955, UInt<1>(0h1), "") : assert_81
node _T_959 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_960 = asUInt(reset)
node _T_961 = eq(_T_960, UInt<1>(0h0))
when _T_961 :
node _T_962 = eq(_T_959, UInt<1>(0h0))
when _T_962 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_959, UInt<1>(0h1), "") : assert_82
node _T_963 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_964 = or(UInt<1>(0h1), _T_963)
node _T_965 = asUInt(reset)
node _T_966 = eq(_T_965, UInt<1>(0h0))
when _T_966 :
node _T_967 = eq(_T_964, UInt<1>(0h0))
when _T_967 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_964, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<14>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_968 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_969 = asUInt(reset)
node _T_970 = eq(_T_969, UInt<1>(0h0))
when _T_970 :
node _T_971 = eq(_T_968, UInt<1>(0h0))
when _T_971 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_968, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<14>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_972 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_973 = asUInt(reset)
node _T_974 = eq(_T_973, UInt<1>(0h0))
when _T_974 :
node _T_975 = eq(_T_972, UInt<1>(0h0))
when _T_975 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_972, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_976 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_977 = asUInt(reset)
node _T_978 = eq(_T_977, UInt<1>(0h0))
when _T_978 :
node _T_979 = eq(_T_976, UInt<1>(0h0))
when _T_979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_976, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_980 = eq(a_first, UInt<1>(0h0))
node _T_981 = and(io.in.a.valid, _T_980)
when _T_981 :
node _T_982 = eq(io.in.a.bits.opcode, opcode)
node _T_983 = asUInt(reset)
node _T_984 = eq(_T_983, UInt<1>(0h0))
when _T_984 :
node _T_985 = eq(_T_982, UInt<1>(0h0))
when _T_985 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_982, UInt<1>(0h1), "") : assert_87
node _T_986 = eq(io.in.a.bits.param, param)
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(_T_986, UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_986, UInt<1>(0h1), "") : assert_88
node _T_990 = eq(io.in.a.bits.size, size)
node _T_991 = asUInt(reset)
node _T_992 = eq(_T_991, UInt<1>(0h0))
when _T_992 :
node _T_993 = eq(_T_990, UInt<1>(0h0))
when _T_993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_990, UInt<1>(0h1), "") : assert_89
node _T_994 = eq(io.in.a.bits.source, source)
node _T_995 = asUInt(reset)
node _T_996 = eq(_T_995, UInt<1>(0h0))
when _T_996 :
node _T_997 = eq(_T_994, UInt<1>(0h0))
when _T_997 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_994, UInt<1>(0h1), "") : assert_90
node _T_998 = eq(io.in.a.bits.address, address)
node _T_999 = asUInt(reset)
node _T_1000 = eq(_T_999, UInt<1>(0h0))
when _T_1000 :
node _T_1001 = eq(_T_998, UInt<1>(0h0))
when _T_1001 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_998, UInt<1>(0h1), "") : assert_91
node _T_1002 = and(io.in.a.ready, io.in.a.valid)
node _T_1003 = and(_T_1002, a_first)
when _T_1003 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1004 = eq(d_first, UInt<1>(0h0))
node _T_1005 = and(io.in.d.valid, _T_1004)
when _T_1005 :
node _T_1006 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1007 = asUInt(reset)
node _T_1008 = eq(_T_1007, UInt<1>(0h0))
when _T_1008 :
node _T_1009 = eq(_T_1006, UInt<1>(0h0))
when _T_1009 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1006, UInt<1>(0h1), "") : assert_92
node _T_1010 = eq(io.in.d.bits.param, param_1)
node _T_1011 = asUInt(reset)
node _T_1012 = eq(_T_1011, UInt<1>(0h0))
when _T_1012 :
node _T_1013 = eq(_T_1010, UInt<1>(0h0))
when _T_1013 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1010, UInt<1>(0h1), "") : assert_93
node _T_1014 = eq(io.in.d.bits.size, size_1)
node _T_1015 = asUInt(reset)
node _T_1016 = eq(_T_1015, UInt<1>(0h0))
when _T_1016 :
node _T_1017 = eq(_T_1014, UInt<1>(0h0))
when _T_1017 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1014, UInt<1>(0h1), "") : assert_94
node _T_1018 = eq(io.in.d.bits.source, source_1)
node _T_1019 = asUInt(reset)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
node _T_1021 = eq(_T_1018, UInt<1>(0h0))
when _T_1021 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1018, UInt<1>(0h1), "") : assert_95
node _T_1022 = eq(io.in.d.bits.sink, sink)
node _T_1023 = asUInt(reset)
node _T_1024 = eq(_T_1023, UInt<1>(0h0))
when _T_1024 :
node _T_1025 = eq(_T_1022, UInt<1>(0h0))
when _T_1025 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1022, UInt<1>(0h1), "") : assert_96
node _T_1026 = eq(io.in.d.bits.denied, denied)
node _T_1027 = asUInt(reset)
node _T_1028 = eq(_T_1027, UInt<1>(0h0))
when _T_1028 :
node _T_1029 = eq(_T_1026, UInt<1>(0h0))
when _T_1029 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1026, UInt<1>(0h1), "") : assert_97
node _T_1030 = and(io.in.d.ready, io.in.d.valid)
node _T_1031 = and(_T_1030, d_first)
when _T_1031 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<520>
connect a_sizes_set, UInt<520>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1032 = and(io.in.a.valid, a_first_1)
node _T_1033 = and(_T_1032, UInt<1>(0h1))
when _T_1033 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1034 = and(io.in.a.ready, io.in.a.valid)
node _T_1035 = and(_T_1034, a_first_1)
node _T_1036 = and(_T_1035, UInt<1>(0h1))
when _T_1036 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1037 = dshr(inflight, io.in.a.bits.source)
node _T_1038 = bits(_T_1037, 0, 0)
node _T_1039 = eq(_T_1038, UInt<1>(0h0))
node _T_1040 = asUInt(reset)
node _T_1041 = eq(_T_1040, UInt<1>(0h0))
when _T_1041 :
node _T_1042 = eq(_T_1039, UInt<1>(0h0))
when _T_1042 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1039, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<520>
connect d_sizes_clr, UInt<520>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1043 = and(io.in.d.valid, d_first_1)
node _T_1044 = and(_T_1043, UInt<1>(0h1))
node _T_1045 = eq(d_release_ack, UInt<1>(0h0))
node _T_1046 = and(_T_1044, _T_1045)
when _T_1046 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1047 = and(io.in.d.ready, io.in.d.valid)
node _T_1048 = and(_T_1047, d_first_1)
node _T_1049 = and(_T_1048, UInt<1>(0h1))
node _T_1050 = eq(d_release_ack, UInt<1>(0h0))
node _T_1051 = and(_T_1049, _T_1050)
when _T_1051 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1052 = and(io.in.d.valid, d_first_1)
node _T_1053 = and(_T_1052, UInt<1>(0h1))
node _T_1054 = eq(d_release_ack, UInt<1>(0h0))
node _T_1055 = and(_T_1053, _T_1054)
when _T_1055 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1056 = dshr(inflight, io.in.d.bits.source)
node _T_1057 = bits(_T_1056, 0, 0)
node _T_1058 = or(_T_1057, same_cycle_resp)
node _T_1059 = asUInt(reset)
node _T_1060 = eq(_T_1059, UInt<1>(0h0))
when _T_1060 :
node _T_1061 = eq(_T_1058, UInt<1>(0h0))
when _T_1061 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1058, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1062 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1063 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1064 = or(_T_1062, _T_1063)
node _T_1065 = asUInt(reset)
node _T_1066 = eq(_T_1065, UInt<1>(0h0))
when _T_1066 :
node _T_1067 = eq(_T_1064, UInt<1>(0h0))
when _T_1067 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1064, UInt<1>(0h1), "") : assert_100
node _T_1068 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1069 = asUInt(reset)
node _T_1070 = eq(_T_1069, UInt<1>(0h0))
when _T_1070 :
node _T_1071 = eq(_T_1068, UInt<1>(0h0))
when _T_1071 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1068, UInt<1>(0h1), "") : assert_101
else :
node _T_1072 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1073 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1074 = or(_T_1072, _T_1073)
node _T_1075 = asUInt(reset)
node _T_1076 = eq(_T_1075, UInt<1>(0h0))
when _T_1076 :
node _T_1077 = eq(_T_1074, UInt<1>(0h0))
when _T_1077 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1074, UInt<1>(0h1), "") : assert_102
node _T_1078 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1079 = asUInt(reset)
node _T_1080 = eq(_T_1079, UInt<1>(0h0))
when _T_1080 :
node _T_1081 = eq(_T_1078, UInt<1>(0h0))
when _T_1081 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1078, UInt<1>(0h1), "") : assert_103
node _T_1082 = and(io.in.d.valid, d_first_1)
node _T_1083 = and(_T_1082, a_first_1)
node _T_1084 = and(_T_1083, io.in.a.valid)
node _T_1085 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1086 = and(_T_1084, _T_1085)
node _T_1087 = eq(d_release_ack, UInt<1>(0h0))
node _T_1088 = and(_T_1086, _T_1087)
when _T_1088 :
node _T_1089 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1090 = or(_T_1089, io.in.a.ready)
node _T_1091 = asUInt(reset)
node _T_1092 = eq(_T_1091, UInt<1>(0h0))
when _T_1092 :
node _T_1093 = eq(_T_1090, UInt<1>(0h0))
when _T_1093 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1090, UInt<1>(0h1), "") : assert_104
node _T_1094 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1095 = orr(a_set_wo_ready)
node _T_1096 = eq(_T_1095, UInt<1>(0h0))
node _T_1097 = or(_T_1094, _T_1096)
node _T_1098 = asUInt(reset)
node _T_1099 = eq(_T_1098, UInt<1>(0h0))
when _T_1099 :
node _T_1100 = eq(_T_1097, UInt<1>(0h0))
when _T_1100 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1097, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_40
node _T_1101 = orr(inflight)
node _T_1102 = eq(_T_1101, UInt<1>(0h0))
node _T_1103 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1104 = or(_T_1102, _T_1103)
node _T_1105 = lt(watchdog, plusarg_reader.out)
node _T_1106 = or(_T_1104, _T_1105)
node _T_1107 = asUInt(reset)
node _T_1108 = eq(_T_1107, UInt<1>(0h0))
when _T_1108 :
node _T_1109 = eq(_T_1106, UInt<1>(0h0))
when _T_1109 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1106, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1110 = and(io.in.a.ready, io.in.a.valid)
node _T_1111 = and(io.in.d.ready, io.in.d.valid)
node _T_1112 = or(_T_1110, _T_1111)
when _T_1112 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<14>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<14>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<520>
connect c_sizes_set, UInt<520>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<14>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1113 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<14>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1114 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1115 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1116 = and(_T_1114, _T_1115)
node _T_1117 = and(_T_1113, _T_1116)
when _T_1117 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<14>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<14>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1118 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1119 = and(_T_1118, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<14>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1120 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1121 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1122 = and(_T_1120, _T_1121)
node _T_1123 = and(_T_1119, _T_1122)
when _T_1123 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<14>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<14>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<14>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<14>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<14>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<14>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1124 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1125 = bits(_T_1124, 0, 0)
node _T_1126 = eq(_T_1125, UInt<1>(0h0))
node _T_1127 = asUInt(reset)
node _T_1128 = eq(_T_1127, UInt<1>(0h0))
when _T_1128 :
node _T_1129 = eq(_T_1126, UInt<1>(0h0))
when _T_1129 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1126, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<14>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<14>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<520>
connect d_sizes_clr_1, UInt<520>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1130 = and(io.in.d.valid, d_first_2)
node _T_1131 = and(_T_1130, UInt<1>(0h1))
node _T_1132 = and(_T_1131, d_release_ack_1)
when _T_1132 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1133 = and(io.in.d.ready, io.in.d.valid)
node _T_1134 = and(_T_1133, d_first_2)
node _T_1135 = and(_T_1134, UInt<1>(0h1))
node _T_1136 = and(_T_1135, d_release_ack_1)
when _T_1136 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1137 = and(io.in.d.valid, d_first_2)
node _T_1138 = and(_T_1137, UInt<1>(0h1))
node _T_1139 = and(_T_1138, d_release_ack_1)
when _T_1139 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<14>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<14>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<14>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1140 = dshr(inflight_1, io.in.d.bits.source)
node _T_1141 = bits(_T_1140, 0, 0)
node _T_1142 = or(_T_1141, same_cycle_resp_1)
node _T_1143 = asUInt(reset)
node _T_1144 = eq(_T_1143, UInt<1>(0h0))
when _T_1144 :
node _T_1145 = eq(_T_1142, UInt<1>(0h0))
when _T_1145 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1142, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<14>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1146 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1147 = asUInt(reset)
node _T_1148 = eq(_T_1147, UInt<1>(0h0))
when _T_1148 :
node _T_1149 = eq(_T_1146, UInt<1>(0h0))
when _T_1149 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1146, UInt<1>(0h1), "") : assert_109
else :
node _T_1150 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1151 = asUInt(reset)
node _T_1152 = eq(_T_1151, UInt<1>(0h0))
when _T_1152 :
node _T_1153 = eq(_T_1150, UInt<1>(0h0))
when _T_1153 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1150, UInt<1>(0h1), "") : assert_110
node _T_1154 = and(io.in.d.valid, d_first_2)
node _T_1155 = and(_T_1154, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<14>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1156 = and(_T_1155, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<14>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1157 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1158 = and(_T_1156, _T_1157)
node _T_1159 = and(_T_1158, d_release_ack_1)
node _T_1160 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1161 = and(_T_1159, _T_1160)
when _T_1161 :
node _T_1162 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<14>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<4>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1163 = or(_T_1162, _WIRE_27.ready)
node _T_1164 = asUInt(reset)
node _T_1165 = eq(_T_1164, UInt<1>(0h0))
when _T_1165 :
node _T_1166 = eq(_T_1163, UInt<1>(0h0))
when _T_1166 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1163, UInt<1>(0h1), "") : assert_111
node _T_1167 = orr(c_set_wo_ready)
when _T_1167 :
node _T_1168 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1169 = asUInt(reset)
node _T_1170 = eq(_T_1169, UInt<1>(0h0))
when _T_1170 :
node _T_1171 = eq(_T_1168, UInt<1>(0h0))
when _T_1171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1168, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_41
node _T_1172 = orr(inflight_1)
node _T_1173 = eq(_T_1172, UInt<1>(0h0))
node _T_1174 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1175 = or(_T_1173, _T_1174)
node _T_1176 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1177 = or(_T_1175, _T_1176)
node _T_1178 = asUInt(reset)
node _T_1179 = eq(_T_1178, UInt<1>(0h0))
when _T_1179 :
node _T_1180 = eq(_T_1177, UInt<1>(0h0))
when _T_1180 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1177, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<14>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<4>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1181 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1182 = and(io.in.d.ready, io.in.d.valid)
node _T_1183 = or(_T_1181, _T_1182)
when _T_1183 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_20( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [13:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_first_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_first_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_first_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_first_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_set_wo_ready_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_set_wo_ready_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_opcodes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_sizes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_sizes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_opcodes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_opcodes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_sizes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_sizes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_probe_ack_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_probe_ack_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_probe_ack_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_probe_ack_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_4_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_5_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31]
wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire _source_ok_T_29 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_35 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [13:0] _is_aligned_T = {2'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 14'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_36 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_37 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_38 = _source_ok_T_37 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_44 = _source_ok_T_43 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31]
wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31]
wire _source_ok_T_62 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31]
wire _source_ok_T_63 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31]
wire _source_ok_T_64 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31]
wire _source_ok_T_65 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_68 = _source_ok_T_67 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_69 = _source_ok_T_68 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_71 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1110 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1110; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1110; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [13:0] address; // @[Monitor.scala:391:22]
wire _T_1183 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1183; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1183; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1183; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [519:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [519:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1036 = _T_1110 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1036 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1036 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1036 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1036 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1036 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1082 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1082 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1051 = _T_1183 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1051 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1051 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1051 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [519:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1154 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1154 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1136 = _T_1183 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1136 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1136 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1136 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_265 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_282
connect io_out_source_valid_1.clock, clock
connect io_out_source_valid_1.reset, reset
connect io_out_source_valid_1.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid_1.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_265( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_282 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IssueUnitCollapsing_4 :
input clock : Clock
input reset : Reset
output io : { flip dis_uops : { flip ready : UInt<1>, valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}[1], iss_valids : UInt<1>[1], iss_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1], flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<6>, poisoned : UInt<1>}}[3], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<4>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<6>}[1], flip fu_types : UInt<10>[1], flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip flush_pipeline : UInt<1>, flip ld_miss : UInt<1>, event_empty : UInt<1>, flip tsc_reg : UInt<64>}
wire _WIRE : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect _WIRE, io.dis_uops[0].bits
connect _WIRE.iw_p1_poisoned, UInt<1>(0h0)
connect _WIRE.iw_p2_poisoned, UInt<1>(0h0)
connect _WIRE.iw_state, UInt<2>(0h1)
node _T = eq(io.dis_uops[0].bits.uopc, UInt<7>(0h2))
node _T_1 = eq(io.dis_uops[0].bits.lrs2_rtype, UInt<2>(0h0))
node _T_2 = and(_T, _T_1)
node _T_3 = eq(io.dis_uops[0].bits.uopc, UInt<7>(0h43))
node _T_4 = or(_T_2, _T_3)
when _T_4 :
connect _WIRE.iw_state, UInt<2>(0h2)
else :
node _T_5 = eq(io.dis_uops[0].bits.uopc, UInt<7>(0h2))
node _T_6 = neq(io.dis_uops[0].bits.lrs2_rtype, UInt<2>(0h0))
node _T_7 = and(_T_5, _T_6)
when _T_7 :
connect _WIRE.lrs2_rtype, UInt<2>(0h2)
connect _WIRE.prs2_busy, UInt<1>(0h0)
connect _WIRE.prs3_busy, UInt<1>(0h0)
node _T_8 = and(io.dis_uops[0].bits.ppred_busy, io.dis_uops[0].valid)
node _T_9 = eq(_T_8, UInt<1>(0h0))
node _T_10 = asUInt(reset)
node _T_11 = eq(_T_10, UInt<1>(0h0))
when _T_11 :
node _T_12 = eq(_T_9, UInt<1>(0h0))
when _T_12 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-unit.scala:145 assert(!(io.dis_uops(w).bits.ppred_busy && io.dis_uops(w).valid))\n") : printf
assert(clock, _T_9, UInt<1>(0h1), "") : assert
connect _WIRE.ppred_busy, UInt<1>(0h0)
inst slots_0 of IssueSlot_32
connect slots_0.clock, clock
connect slots_0.reset, reset
inst slots_1 of IssueSlot_33
connect slots_1.clock, clock
connect slots_1.reset, reset
inst slots_2 of IssueSlot_34
connect slots_2.clock, clock
connect slots_2.reset, reset
inst slots_3 of IssueSlot_35
connect slots_3.clock, clock
connect slots_3.reset, reset
inst slots_4 of IssueSlot_36
connect slots_4.clock, clock
connect slots_4.reset, reset
inst slots_5 of IssueSlot_37
connect slots_5.clock, clock
connect slots_5.reset, reset
inst slots_6 of IssueSlot_38
connect slots_6.clock, clock
connect slots_6.reset, reset
inst slots_7 of IssueSlot_39
connect slots_7.clock, clock
connect slots_7.reset, reset
wire issue_slots : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<6>, poisoned : UInt<1>}}[3], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<4>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<6>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}}[8]
connect issue_slots[0].debug.state, slots_0.io.debug.state
connect issue_slots[0].debug.ppred, slots_0.io.debug.ppred
connect issue_slots[0].debug.p3, slots_0.io.debug.p3
connect issue_slots[0].debug.p2, slots_0.io.debug.p2
connect issue_slots[0].debug.p1, slots_0.io.debug.p1
connect issue_slots[0].uop.debug_tsrc, slots_0.io.uop.debug_tsrc
connect issue_slots[0].uop.debug_fsrc, slots_0.io.uop.debug_fsrc
connect issue_slots[0].uop.bp_xcpt_if, slots_0.io.uop.bp_xcpt_if
connect issue_slots[0].uop.bp_debug_if, slots_0.io.uop.bp_debug_if
connect issue_slots[0].uop.xcpt_ma_if, slots_0.io.uop.xcpt_ma_if
connect issue_slots[0].uop.xcpt_ae_if, slots_0.io.uop.xcpt_ae_if
connect issue_slots[0].uop.xcpt_pf_if, slots_0.io.uop.xcpt_pf_if
connect issue_slots[0].uop.fp_single, slots_0.io.uop.fp_single
connect issue_slots[0].uop.fp_val, slots_0.io.uop.fp_val
connect issue_slots[0].uop.frs3_en, slots_0.io.uop.frs3_en
connect issue_slots[0].uop.lrs2_rtype, slots_0.io.uop.lrs2_rtype
connect issue_slots[0].uop.lrs1_rtype, slots_0.io.uop.lrs1_rtype
connect issue_slots[0].uop.dst_rtype, slots_0.io.uop.dst_rtype
connect issue_slots[0].uop.ldst_val, slots_0.io.uop.ldst_val
connect issue_slots[0].uop.lrs3, slots_0.io.uop.lrs3
connect issue_slots[0].uop.lrs2, slots_0.io.uop.lrs2
connect issue_slots[0].uop.lrs1, slots_0.io.uop.lrs1
connect issue_slots[0].uop.ldst, slots_0.io.uop.ldst
connect issue_slots[0].uop.ldst_is_rs1, slots_0.io.uop.ldst_is_rs1
connect issue_slots[0].uop.flush_on_commit, slots_0.io.uop.flush_on_commit
connect issue_slots[0].uop.is_unique, slots_0.io.uop.is_unique
connect issue_slots[0].uop.is_sys_pc2epc, slots_0.io.uop.is_sys_pc2epc
connect issue_slots[0].uop.uses_stq, slots_0.io.uop.uses_stq
connect issue_slots[0].uop.uses_ldq, slots_0.io.uop.uses_ldq
connect issue_slots[0].uop.is_amo, slots_0.io.uop.is_amo
connect issue_slots[0].uop.is_fencei, slots_0.io.uop.is_fencei
connect issue_slots[0].uop.is_fence, slots_0.io.uop.is_fence
connect issue_slots[0].uop.mem_signed, slots_0.io.uop.mem_signed
connect issue_slots[0].uop.mem_size, slots_0.io.uop.mem_size
connect issue_slots[0].uop.mem_cmd, slots_0.io.uop.mem_cmd
connect issue_slots[0].uop.bypassable, slots_0.io.uop.bypassable
connect issue_slots[0].uop.exc_cause, slots_0.io.uop.exc_cause
connect issue_slots[0].uop.exception, slots_0.io.uop.exception
connect issue_slots[0].uop.stale_pdst, slots_0.io.uop.stale_pdst
connect issue_slots[0].uop.ppred_busy, slots_0.io.uop.ppred_busy
connect issue_slots[0].uop.prs3_busy, slots_0.io.uop.prs3_busy
connect issue_slots[0].uop.prs2_busy, slots_0.io.uop.prs2_busy
connect issue_slots[0].uop.prs1_busy, slots_0.io.uop.prs1_busy
connect issue_slots[0].uop.ppred, slots_0.io.uop.ppred
connect issue_slots[0].uop.prs3, slots_0.io.uop.prs3
connect issue_slots[0].uop.prs2, slots_0.io.uop.prs2
connect issue_slots[0].uop.prs1, slots_0.io.uop.prs1
connect issue_slots[0].uop.pdst, slots_0.io.uop.pdst
connect issue_slots[0].uop.rxq_idx, slots_0.io.uop.rxq_idx
connect issue_slots[0].uop.stq_idx, slots_0.io.uop.stq_idx
connect issue_slots[0].uop.ldq_idx, slots_0.io.uop.ldq_idx
connect issue_slots[0].uop.rob_idx, slots_0.io.uop.rob_idx
connect issue_slots[0].uop.csr_addr, slots_0.io.uop.csr_addr
connect issue_slots[0].uop.imm_packed, slots_0.io.uop.imm_packed
connect issue_slots[0].uop.taken, slots_0.io.uop.taken
connect issue_slots[0].uop.pc_lob, slots_0.io.uop.pc_lob
connect issue_slots[0].uop.edge_inst, slots_0.io.uop.edge_inst
connect issue_slots[0].uop.ftq_idx, slots_0.io.uop.ftq_idx
connect issue_slots[0].uop.br_tag, slots_0.io.uop.br_tag
connect issue_slots[0].uop.br_mask, slots_0.io.uop.br_mask
connect issue_slots[0].uop.is_sfb, slots_0.io.uop.is_sfb
connect issue_slots[0].uop.is_jal, slots_0.io.uop.is_jal
connect issue_slots[0].uop.is_jalr, slots_0.io.uop.is_jalr
connect issue_slots[0].uop.is_br, slots_0.io.uop.is_br
connect issue_slots[0].uop.iw_p2_poisoned, slots_0.io.uop.iw_p2_poisoned
connect issue_slots[0].uop.iw_p1_poisoned, slots_0.io.uop.iw_p1_poisoned
connect issue_slots[0].uop.iw_state, slots_0.io.uop.iw_state
connect issue_slots[0].uop.ctrl.is_std, slots_0.io.uop.ctrl.is_std
connect issue_slots[0].uop.ctrl.is_sta, slots_0.io.uop.ctrl.is_sta
connect issue_slots[0].uop.ctrl.is_load, slots_0.io.uop.ctrl.is_load
connect issue_slots[0].uop.ctrl.csr_cmd, slots_0.io.uop.ctrl.csr_cmd
connect issue_slots[0].uop.ctrl.fcn_dw, slots_0.io.uop.ctrl.fcn_dw
connect issue_slots[0].uop.ctrl.op_fcn, slots_0.io.uop.ctrl.op_fcn
connect issue_slots[0].uop.ctrl.imm_sel, slots_0.io.uop.ctrl.imm_sel
connect issue_slots[0].uop.ctrl.op2_sel, slots_0.io.uop.ctrl.op2_sel
connect issue_slots[0].uop.ctrl.op1_sel, slots_0.io.uop.ctrl.op1_sel
connect issue_slots[0].uop.ctrl.br_type, slots_0.io.uop.ctrl.br_type
connect issue_slots[0].uop.fu_code, slots_0.io.uop.fu_code
connect issue_slots[0].uop.iq_type, slots_0.io.uop.iq_type
connect issue_slots[0].uop.debug_pc, slots_0.io.uop.debug_pc
connect issue_slots[0].uop.is_rvc, slots_0.io.uop.is_rvc
connect issue_slots[0].uop.debug_inst, slots_0.io.uop.debug_inst
connect issue_slots[0].uop.inst, slots_0.io.uop.inst
connect issue_slots[0].uop.uopc, slots_0.io.uop.uopc
connect issue_slots[0].out_uop.debug_tsrc, slots_0.io.out_uop.debug_tsrc
connect issue_slots[0].out_uop.debug_fsrc, slots_0.io.out_uop.debug_fsrc
connect issue_slots[0].out_uop.bp_xcpt_if, slots_0.io.out_uop.bp_xcpt_if
connect issue_slots[0].out_uop.bp_debug_if, slots_0.io.out_uop.bp_debug_if
connect issue_slots[0].out_uop.xcpt_ma_if, slots_0.io.out_uop.xcpt_ma_if
connect issue_slots[0].out_uop.xcpt_ae_if, slots_0.io.out_uop.xcpt_ae_if
connect issue_slots[0].out_uop.xcpt_pf_if, slots_0.io.out_uop.xcpt_pf_if
connect issue_slots[0].out_uop.fp_single, slots_0.io.out_uop.fp_single
connect issue_slots[0].out_uop.fp_val, slots_0.io.out_uop.fp_val
connect issue_slots[0].out_uop.frs3_en, slots_0.io.out_uop.frs3_en
connect issue_slots[0].out_uop.lrs2_rtype, slots_0.io.out_uop.lrs2_rtype
connect issue_slots[0].out_uop.lrs1_rtype, slots_0.io.out_uop.lrs1_rtype
connect issue_slots[0].out_uop.dst_rtype, slots_0.io.out_uop.dst_rtype
connect issue_slots[0].out_uop.ldst_val, slots_0.io.out_uop.ldst_val
connect issue_slots[0].out_uop.lrs3, slots_0.io.out_uop.lrs3
connect issue_slots[0].out_uop.lrs2, slots_0.io.out_uop.lrs2
connect issue_slots[0].out_uop.lrs1, slots_0.io.out_uop.lrs1
connect issue_slots[0].out_uop.ldst, slots_0.io.out_uop.ldst
connect issue_slots[0].out_uop.ldst_is_rs1, slots_0.io.out_uop.ldst_is_rs1
connect issue_slots[0].out_uop.flush_on_commit, slots_0.io.out_uop.flush_on_commit
connect issue_slots[0].out_uop.is_unique, slots_0.io.out_uop.is_unique
connect issue_slots[0].out_uop.is_sys_pc2epc, slots_0.io.out_uop.is_sys_pc2epc
connect issue_slots[0].out_uop.uses_stq, slots_0.io.out_uop.uses_stq
connect issue_slots[0].out_uop.uses_ldq, slots_0.io.out_uop.uses_ldq
connect issue_slots[0].out_uop.is_amo, slots_0.io.out_uop.is_amo
connect issue_slots[0].out_uop.is_fencei, slots_0.io.out_uop.is_fencei
connect issue_slots[0].out_uop.is_fence, slots_0.io.out_uop.is_fence
connect issue_slots[0].out_uop.mem_signed, slots_0.io.out_uop.mem_signed
connect issue_slots[0].out_uop.mem_size, slots_0.io.out_uop.mem_size
connect issue_slots[0].out_uop.mem_cmd, slots_0.io.out_uop.mem_cmd
connect issue_slots[0].out_uop.bypassable, slots_0.io.out_uop.bypassable
connect issue_slots[0].out_uop.exc_cause, slots_0.io.out_uop.exc_cause
connect issue_slots[0].out_uop.exception, slots_0.io.out_uop.exception
connect issue_slots[0].out_uop.stale_pdst, slots_0.io.out_uop.stale_pdst
connect issue_slots[0].out_uop.ppred_busy, slots_0.io.out_uop.ppred_busy
connect issue_slots[0].out_uop.prs3_busy, slots_0.io.out_uop.prs3_busy
connect issue_slots[0].out_uop.prs2_busy, slots_0.io.out_uop.prs2_busy
connect issue_slots[0].out_uop.prs1_busy, slots_0.io.out_uop.prs1_busy
connect issue_slots[0].out_uop.ppred, slots_0.io.out_uop.ppred
connect issue_slots[0].out_uop.prs3, slots_0.io.out_uop.prs3
connect issue_slots[0].out_uop.prs2, slots_0.io.out_uop.prs2
connect issue_slots[0].out_uop.prs1, slots_0.io.out_uop.prs1
connect issue_slots[0].out_uop.pdst, slots_0.io.out_uop.pdst
connect issue_slots[0].out_uop.rxq_idx, slots_0.io.out_uop.rxq_idx
connect issue_slots[0].out_uop.stq_idx, slots_0.io.out_uop.stq_idx
connect issue_slots[0].out_uop.ldq_idx, slots_0.io.out_uop.ldq_idx
connect issue_slots[0].out_uop.rob_idx, slots_0.io.out_uop.rob_idx
connect issue_slots[0].out_uop.csr_addr, slots_0.io.out_uop.csr_addr
connect issue_slots[0].out_uop.imm_packed, slots_0.io.out_uop.imm_packed
connect issue_slots[0].out_uop.taken, slots_0.io.out_uop.taken
connect issue_slots[0].out_uop.pc_lob, slots_0.io.out_uop.pc_lob
connect issue_slots[0].out_uop.edge_inst, slots_0.io.out_uop.edge_inst
connect issue_slots[0].out_uop.ftq_idx, slots_0.io.out_uop.ftq_idx
connect issue_slots[0].out_uop.br_tag, slots_0.io.out_uop.br_tag
connect issue_slots[0].out_uop.br_mask, slots_0.io.out_uop.br_mask
connect issue_slots[0].out_uop.is_sfb, slots_0.io.out_uop.is_sfb
connect issue_slots[0].out_uop.is_jal, slots_0.io.out_uop.is_jal
connect issue_slots[0].out_uop.is_jalr, slots_0.io.out_uop.is_jalr
connect issue_slots[0].out_uop.is_br, slots_0.io.out_uop.is_br
connect issue_slots[0].out_uop.iw_p2_poisoned, slots_0.io.out_uop.iw_p2_poisoned
connect issue_slots[0].out_uop.iw_p1_poisoned, slots_0.io.out_uop.iw_p1_poisoned
connect issue_slots[0].out_uop.iw_state, slots_0.io.out_uop.iw_state
connect issue_slots[0].out_uop.ctrl.is_std, slots_0.io.out_uop.ctrl.is_std
connect issue_slots[0].out_uop.ctrl.is_sta, slots_0.io.out_uop.ctrl.is_sta
connect issue_slots[0].out_uop.ctrl.is_load, slots_0.io.out_uop.ctrl.is_load
connect issue_slots[0].out_uop.ctrl.csr_cmd, slots_0.io.out_uop.ctrl.csr_cmd
connect issue_slots[0].out_uop.ctrl.fcn_dw, slots_0.io.out_uop.ctrl.fcn_dw
connect issue_slots[0].out_uop.ctrl.op_fcn, slots_0.io.out_uop.ctrl.op_fcn
connect issue_slots[0].out_uop.ctrl.imm_sel, slots_0.io.out_uop.ctrl.imm_sel
connect issue_slots[0].out_uop.ctrl.op2_sel, slots_0.io.out_uop.ctrl.op2_sel
connect issue_slots[0].out_uop.ctrl.op1_sel, slots_0.io.out_uop.ctrl.op1_sel
connect issue_slots[0].out_uop.ctrl.br_type, slots_0.io.out_uop.ctrl.br_type
connect issue_slots[0].out_uop.fu_code, slots_0.io.out_uop.fu_code
connect issue_slots[0].out_uop.iq_type, slots_0.io.out_uop.iq_type
connect issue_slots[0].out_uop.debug_pc, slots_0.io.out_uop.debug_pc
connect issue_slots[0].out_uop.is_rvc, slots_0.io.out_uop.is_rvc
connect issue_slots[0].out_uop.debug_inst, slots_0.io.out_uop.debug_inst
connect issue_slots[0].out_uop.inst, slots_0.io.out_uop.inst
connect issue_slots[0].out_uop.uopc, slots_0.io.out_uop.uopc
connect slots_0.io.in_uop.bits.debug_tsrc, issue_slots[0].in_uop.bits.debug_tsrc
connect slots_0.io.in_uop.bits.debug_fsrc, issue_slots[0].in_uop.bits.debug_fsrc
connect slots_0.io.in_uop.bits.bp_xcpt_if, issue_slots[0].in_uop.bits.bp_xcpt_if
connect slots_0.io.in_uop.bits.bp_debug_if, issue_slots[0].in_uop.bits.bp_debug_if
connect slots_0.io.in_uop.bits.xcpt_ma_if, issue_slots[0].in_uop.bits.xcpt_ma_if
connect slots_0.io.in_uop.bits.xcpt_ae_if, issue_slots[0].in_uop.bits.xcpt_ae_if
connect slots_0.io.in_uop.bits.xcpt_pf_if, issue_slots[0].in_uop.bits.xcpt_pf_if
connect slots_0.io.in_uop.bits.fp_single, issue_slots[0].in_uop.bits.fp_single
connect slots_0.io.in_uop.bits.fp_val, issue_slots[0].in_uop.bits.fp_val
connect slots_0.io.in_uop.bits.frs3_en, issue_slots[0].in_uop.bits.frs3_en
connect slots_0.io.in_uop.bits.lrs2_rtype, issue_slots[0].in_uop.bits.lrs2_rtype
connect slots_0.io.in_uop.bits.lrs1_rtype, issue_slots[0].in_uop.bits.lrs1_rtype
connect slots_0.io.in_uop.bits.dst_rtype, issue_slots[0].in_uop.bits.dst_rtype
connect slots_0.io.in_uop.bits.ldst_val, issue_slots[0].in_uop.bits.ldst_val
connect slots_0.io.in_uop.bits.lrs3, issue_slots[0].in_uop.bits.lrs3
connect slots_0.io.in_uop.bits.lrs2, issue_slots[0].in_uop.bits.lrs2
connect slots_0.io.in_uop.bits.lrs1, issue_slots[0].in_uop.bits.lrs1
connect slots_0.io.in_uop.bits.ldst, issue_slots[0].in_uop.bits.ldst
connect slots_0.io.in_uop.bits.ldst_is_rs1, issue_slots[0].in_uop.bits.ldst_is_rs1
connect slots_0.io.in_uop.bits.flush_on_commit, issue_slots[0].in_uop.bits.flush_on_commit
connect slots_0.io.in_uop.bits.is_unique, issue_slots[0].in_uop.bits.is_unique
connect slots_0.io.in_uop.bits.is_sys_pc2epc, issue_slots[0].in_uop.bits.is_sys_pc2epc
connect slots_0.io.in_uop.bits.uses_stq, issue_slots[0].in_uop.bits.uses_stq
connect slots_0.io.in_uop.bits.uses_ldq, issue_slots[0].in_uop.bits.uses_ldq
connect slots_0.io.in_uop.bits.is_amo, issue_slots[0].in_uop.bits.is_amo
connect slots_0.io.in_uop.bits.is_fencei, issue_slots[0].in_uop.bits.is_fencei
connect slots_0.io.in_uop.bits.is_fence, issue_slots[0].in_uop.bits.is_fence
connect slots_0.io.in_uop.bits.mem_signed, issue_slots[0].in_uop.bits.mem_signed
connect slots_0.io.in_uop.bits.mem_size, issue_slots[0].in_uop.bits.mem_size
connect slots_0.io.in_uop.bits.mem_cmd, issue_slots[0].in_uop.bits.mem_cmd
connect slots_0.io.in_uop.bits.bypassable, issue_slots[0].in_uop.bits.bypassable
connect slots_0.io.in_uop.bits.exc_cause, issue_slots[0].in_uop.bits.exc_cause
connect slots_0.io.in_uop.bits.exception, issue_slots[0].in_uop.bits.exception
connect slots_0.io.in_uop.bits.stale_pdst, issue_slots[0].in_uop.bits.stale_pdst
connect slots_0.io.in_uop.bits.ppred_busy, issue_slots[0].in_uop.bits.ppred_busy
connect slots_0.io.in_uop.bits.prs3_busy, issue_slots[0].in_uop.bits.prs3_busy
connect slots_0.io.in_uop.bits.prs2_busy, issue_slots[0].in_uop.bits.prs2_busy
connect slots_0.io.in_uop.bits.prs1_busy, issue_slots[0].in_uop.bits.prs1_busy
connect slots_0.io.in_uop.bits.ppred, issue_slots[0].in_uop.bits.ppred
connect slots_0.io.in_uop.bits.prs3, issue_slots[0].in_uop.bits.prs3
connect slots_0.io.in_uop.bits.prs2, issue_slots[0].in_uop.bits.prs2
connect slots_0.io.in_uop.bits.prs1, issue_slots[0].in_uop.bits.prs1
connect slots_0.io.in_uop.bits.pdst, issue_slots[0].in_uop.bits.pdst
connect slots_0.io.in_uop.bits.rxq_idx, issue_slots[0].in_uop.bits.rxq_idx
connect slots_0.io.in_uop.bits.stq_idx, issue_slots[0].in_uop.bits.stq_idx
connect slots_0.io.in_uop.bits.ldq_idx, issue_slots[0].in_uop.bits.ldq_idx
connect slots_0.io.in_uop.bits.rob_idx, issue_slots[0].in_uop.bits.rob_idx
connect slots_0.io.in_uop.bits.csr_addr, issue_slots[0].in_uop.bits.csr_addr
connect slots_0.io.in_uop.bits.imm_packed, issue_slots[0].in_uop.bits.imm_packed
connect slots_0.io.in_uop.bits.taken, issue_slots[0].in_uop.bits.taken
connect slots_0.io.in_uop.bits.pc_lob, issue_slots[0].in_uop.bits.pc_lob
connect slots_0.io.in_uop.bits.edge_inst, issue_slots[0].in_uop.bits.edge_inst
connect slots_0.io.in_uop.bits.ftq_idx, issue_slots[0].in_uop.bits.ftq_idx
connect slots_0.io.in_uop.bits.br_tag, issue_slots[0].in_uop.bits.br_tag
connect slots_0.io.in_uop.bits.br_mask, issue_slots[0].in_uop.bits.br_mask
connect slots_0.io.in_uop.bits.is_sfb, issue_slots[0].in_uop.bits.is_sfb
connect slots_0.io.in_uop.bits.is_jal, issue_slots[0].in_uop.bits.is_jal
connect slots_0.io.in_uop.bits.is_jalr, issue_slots[0].in_uop.bits.is_jalr
connect slots_0.io.in_uop.bits.is_br, issue_slots[0].in_uop.bits.is_br
connect slots_0.io.in_uop.bits.iw_p2_poisoned, issue_slots[0].in_uop.bits.iw_p2_poisoned
connect slots_0.io.in_uop.bits.iw_p1_poisoned, issue_slots[0].in_uop.bits.iw_p1_poisoned
connect slots_0.io.in_uop.bits.iw_state, issue_slots[0].in_uop.bits.iw_state
connect slots_0.io.in_uop.bits.ctrl.is_std, issue_slots[0].in_uop.bits.ctrl.is_std
connect slots_0.io.in_uop.bits.ctrl.is_sta, issue_slots[0].in_uop.bits.ctrl.is_sta
connect slots_0.io.in_uop.bits.ctrl.is_load, issue_slots[0].in_uop.bits.ctrl.is_load
connect slots_0.io.in_uop.bits.ctrl.csr_cmd, issue_slots[0].in_uop.bits.ctrl.csr_cmd
connect slots_0.io.in_uop.bits.ctrl.fcn_dw, issue_slots[0].in_uop.bits.ctrl.fcn_dw
connect slots_0.io.in_uop.bits.ctrl.op_fcn, issue_slots[0].in_uop.bits.ctrl.op_fcn
connect slots_0.io.in_uop.bits.ctrl.imm_sel, issue_slots[0].in_uop.bits.ctrl.imm_sel
connect slots_0.io.in_uop.bits.ctrl.op2_sel, issue_slots[0].in_uop.bits.ctrl.op2_sel
connect slots_0.io.in_uop.bits.ctrl.op1_sel, issue_slots[0].in_uop.bits.ctrl.op1_sel
connect slots_0.io.in_uop.bits.ctrl.br_type, issue_slots[0].in_uop.bits.ctrl.br_type
connect slots_0.io.in_uop.bits.fu_code, issue_slots[0].in_uop.bits.fu_code
connect slots_0.io.in_uop.bits.iq_type, issue_slots[0].in_uop.bits.iq_type
connect slots_0.io.in_uop.bits.debug_pc, issue_slots[0].in_uop.bits.debug_pc
connect slots_0.io.in_uop.bits.is_rvc, issue_slots[0].in_uop.bits.is_rvc
connect slots_0.io.in_uop.bits.debug_inst, issue_slots[0].in_uop.bits.debug_inst
connect slots_0.io.in_uop.bits.inst, issue_slots[0].in_uop.bits.inst
connect slots_0.io.in_uop.bits.uopc, issue_slots[0].in_uop.bits.uopc
connect slots_0.io.in_uop.valid, issue_slots[0].in_uop.valid
connect slots_0.io.spec_ld_wakeup[0].bits, issue_slots[0].spec_ld_wakeup[0].bits
connect slots_0.io.spec_ld_wakeup[0].valid, issue_slots[0].spec_ld_wakeup[0].valid
connect slots_0.io.pred_wakeup_port.bits, issue_slots[0].pred_wakeup_port.bits
connect slots_0.io.pred_wakeup_port.valid, issue_slots[0].pred_wakeup_port.valid
connect slots_0.io.wakeup_ports[0].bits.poisoned, issue_slots[0].wakeup_ports[0].bits.poisoned
connect slots_0.io.wakeup_ports[0].bits.pdst, issue_slots[0].wakeup_ports[0].bits.pdst
connect slots_0.io.wakeup_ports[0].valid, issue_slots[0].wakeup_ports[0].valid
connect slots_0.io.wakeup_ports[1].bits.poisoned, issue_slots[0].wakeup_ports[1].bits.poisoned
connect slots_0.io.wakeup_ports[1].bits.pdst, issue_slots[0].wakeup_ports[1].bits.pdst
connect slots_0.io.wakeup_ports[1].valid, issue_slots[0].wakeup_ports[1].valid
connect slots_0.io.wakeup_ports[2].bits.poisoned, issue_slots[0].wakeup_ports[2].bits.poisoned
connect slots_0.io.wakeup_ports[2].bits.pdst, issue_slots[0].wakeup_ports[2].bits.pdst
connect slots_0.io.wakeup_ports[2].valid, issue_slots[0].wakeup_ports[2].valid
connect slots_0.io.ldspec_miss, issue_slots[0].ldspec_miss
connect slots_0.io.clear, issue_slots[0].clear
connect slots_0.io.kill, issue_slots[0].kill
connect slots_0.io.brupdate.b2.target_offset, issue_slots[0].brupdate.b2.target_offset
connect slots_0.io.brupdate.b2.jalr_target, issue_slots[0].brupdate.b2.jalr_target
connect slots_0.io.brupdate.b2.pc_sel, issue_slots[0].brupdate.b2.pc_sel
connect slots_0.io.brupdate.b2.cfi_type, issue_slots[0].brupdate.b2.cfi_type
connect slots_0.io.brupdate.b2.taken, issue_slots[0].brupdate.b2.taken
connect slots_0.io.brupdate.b2.mispredict, issue_slots[0].brupdate.b2.mispredict
connect slots_0.io.brupdate.b2.valid, issue_slots[0].brupdate.b2.valid
connect slots_0.io.brupdate.b2.uop.debug_tsrc, issue_slots[0].brupdate.b2.uop.debug_tsrc
connect slots_0.io.brupdate.b2.uop.debug_fsrc, issue_slots[0].brupdate.b2.uop.debug_fsrc
connect slots_0.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[0].brupdate.b2.uop.bp_xcpt_if
connect slots_0.io.brupdate.b2.uop.bp_debug_if, issue_slots[0].brupdate.b2.uop.bp_debug_if
connect slots_0.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[0].brupdate.b2.uop.xcpt_ma_if
connect slots_0.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[0].brupdate.b2.uop.xcpt_ae_if
connect slots_0.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[0].brupdate.b2.uop.xcpt_pf_if
connect slots_0.io.brupdate.b2.uop.fp_single, issue_slots[0].brupdate.b2.uop.fp_single
connect slots_0.io.brupdate.b2.uop.fp_val, issue_slots[0].brupdate.b2.uop.fp_val
connect slots_0.io.brupdate.b2.uop.frs3_en, issue_slots[0].brupdate.b2.uop.frs3_en
connect slots_0.io.brupdate.b2.uop.lrs2_rtype, issue_slots[0].brupdate.b2.uop.lrs2_rtype
connect slots_0.io.brupdate.b2.uop.lrs1_rtype, issue_slots[0].brupdate.b2.uop.lrs1_rtype
connect slots_0.io.brupdate.b2.uop.dst_rtype, issue_slots[0].brupdate.b2.uop.dst_rtype
connect slots_0.io.brupdate.b2.uop.ldst_val, issue_slots[0].brupdate.b2.uop.ldst_val
connect slots_0.io.brupdate.b2.uop.lrs3, issue_slots[0].brupdate.b2.uop.lrs3
connect slots_0.io.brupdate.b2.uop.lrs2, issue_slots[0].brupdate.b2.uop.lrs2
connect slots_0.io.brupdate.b2.uop.lrs1, issue_slots[0].brupdate.b2.uop.lrs1
connect slots_0.io.brupdate.b2.uop.ldst, issue_slots[0].brupdate.b2.uop.ldst
connect slots_0.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[0].brupdate.b2.uop.ldst_is_rs1
connect slots_0.io.brupdate.b2.uop.flush_on_commit, issue_slots[0].brupdate.b2.uop.flush_on_commit
connect slots_0.io.brupdate.b2.uop.is_unique, issue_slots[0].brupdate.b2.uop.is_unique
connect slots_0.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[0].brupdate.b2.uop.is_sys_pc2epc
connect slots_0.io.brupdate.b2.uop.uses_stq, issue_slots[0].brupdate.b2.uop.uses_stq
connect slots_0.io.brupdate.b2.uop.uses_ldq, issue_slots[0].brupdate.b2.uop.uses_ldq
connect slots_0.io.brupdate.b2.uop.is_amo, issue_slots[0].brupdate.b2.uop.is_amo
connect slots_0.io.brupdate.b2.uop.is_fencei, issue_slots[0].brupdate.b2.uop.is_fencei
connect slots_0.io.brupdate.b2.uop.is_fence, issue_slots[0].brupdate.b2.uop.is_fence
connect slots_0.io.brupdate.b2.uop.mem_signed, issue_slots[0].brupdate.b2.uop.mem_signed
connect slots_0.io.brupdate.b2.uop.mem_size, issue_slots[0].brupdate.b2.uop.mem_size
connect slots_0.io.brupdate.b2.uop.mem_cmd, issue_slots[0].brupdate.b2.uop.mem_cmd
connect slots_0.io.brupdate.b2.uop.bypassable, issue_slots[0].brupdate.b2.uop.bypassable
connect slots_0.io.brupdate.b2.uop.exc_cause, issue_slots[0].brupdate.b2.uop.exc_cause
connect slots_0.io.brupdate.b2.uop.exception, issue_slots[0].brupdate.b2.uop.exception
connect slots_0.io.brupdate.b2.uop.stale_pdst, issue_slots[0].brupdate.b2.uop.stale_pdst
connect slots_0.io.brupdate.b2.uop.ppred_busy, issue_slots[0].brupdate.b2.uop.ppred_busy
connect slots_0.io.brupdate.b2.uop.prs3_busy, issue_slots[0].brupdate.b2.uop.prs3_busy
connect slots_0.io.brupdate.b2.uop.prs2_busy, issue_slots[0].brupdate.b2.uop.prs2_busy
connect slots_0.io.brupdate.b2.uop.prs1_busy, issue_slots[0].brupdate.b2.uop.prs1_busy
connect slots_0.io.brupdate.b2.uop.ppred, issue_slots[0].brupdate.b2.uop.ppred
connect slots_0.io.brupdate.b2.uop.prs3, issue_slots[0].brupdate.b2.uop.prs3
connect slots_0.io.brupdate.b2.uop.prs2, issue_slots[0].brupdate.b2.uop.prs2
connect slots_0.io.brupdate.b2.uop.prs1, issue_slots[0].brupdate.b2.uop.prs1
connect slots_0.io.brupdate.b2.uop.pdst, issue_slots[0].brupdate.b2.uop.pdst
connect slots_0.io.brupdate.b2.uop.rxq_idx, issue_slots[0].brupdate.b2.uop.rxq_idx
connect slots_0.io.brupdate.b2.uop.stq_idx, issue_slots[0].brupdate.b2.uop.stq_idx
connect slots_0.io.brupdate.b2.uop.ldq_idx, issue_slots[0].brupdate.b2.uop.ldq_idx
connect slots_0.io.brupdate.b2.uop.rob_idx, issue_slots[0].brupdate.b2.uop.rob_idx
connect slots_0.io.brupdate.b2.uop.csr_addr, issue_slots[0].brupdate.b2.uop.csr_addr
connect slots_0.io.brupdate.b2.uop.imm_packed, issue_slots[0].brupdate.b2.uop.imm_packed
connect slots_0.io.brupdate.b2.uop.taken, issue_slots[0].brupdate.b2.uop.taken
connect slots_0.io.brupdate.b2.uop.pc_lob, issue_slots[0].brupdate.b2.uop.pc_lob
connect slots_0.io.brupdate.b2.uop.edge_inst, issue_slots[0].brupdate.b2.uop.edge_inst
connect slots_0.io.brupdate.b2.uop.ftq_idx, issue_slots[0].brupdate.b2.uop.ftq_idx
connect slots_0.io.brupdate.b2.uop.br_tag, issue_slots[0].brupdate.b2.uop.br_tag
connect slots_0.io.brupdate.b2.uop.br_mask, issue_slots[0].brupdate.b2.uop.br_mask
connect slots_0.io.brupdate.b2.uop.is_sfb, issue_slots[0].brupdate.b2.uop.is_sfb
connect slots_0.io.brupdate.b2.uop.is_jal, issue_slots[0].brupdate.b2.uop.is_jal
connect slots_0.io.brupdate.b2.uop.is_jalr, issue_slots[0].brupdate.b2.uop.is_jalr
connect slots_0.io.brupdate.b2.uop.is_br, issue_slots[0].brupdate.b2.uop.is_br
connect slots_0.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[0].brupdate.b2.uop.iw_p2_poisoned
connect slots_0.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[0].brupdate.b2.uop.iw_p1_poisoned
connect slots_0.io.brupdate.b2.uop.iw_state, issue_slots[0].brupdate.b2.uop.iw_state
connect slots_0.io.brupdate.b2.uop.ctrl.is_std, issue_slots[0].brupdate.b2.uop.ctrl.is_std
connect slots_0.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[0].brupdate.b2.uop.ctrl.is_sta
connect slots_0.io.brupdate.b2.uop.ctrl.is_load, issue_slots[0].brupdate.b2.uop.ctrl.is_load
connect slots_0.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[0].brupdate.b2.uop.ctrl.csr_cmd
connect slots_0.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[0].brupdate.b2.uop.ctrl.fcn_dw
connect slots_0.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[0].brupdate.b2.uop.ctrl.op_fcn
connect slots_0.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[0].brupdate.b2.uop.ctrl.imm_sel
connect slots_0.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[0].brupdate.b2.uop.ctrl.op2_sel
connect slots_0.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[0].brupdate.b2.uop.ctrl.op1_sel
connect slots_0.io.brupdate.b2.uop.ctrl.br_type, issue_slots[0].brupdate.b2.uop.ctrl.br_type
connect slots_0.io.brupdate.b2.uop.fu_code, issue_slots[0].brupdate.b2.uop.fu_code
connect slots_0.io.brupdate.b2.uop.iq_type, issue_slots[0].brupdate.b2.uop.iq_type
connect slots_0.io.brupdate.b2.uop.debug_pc, issue_slots[0].brupdate.b2.uop.debug_pc
connect slots_0.io.brupdate.b2.uop.is_rvc, issue_slots[0].brupdate.b2.uop.is_rvc
connect slots_0.io.brupdate.b2.uop.debug_inst, issue_slots[0].brupdate.b2.uop.debug_inst
connect slots_0.io.brupdate.b2.uop.inst, issue_slots[0].brupdate.b2.uop.inst
connect slots_0.io.brupdate.b2.uop.uopc, issue_slots[0].brupdate.b2.uop.uopc
connect slots_0.io.brupdate.b1.mispredict_mask, issue_slots[0].brupdate.b1.mispredict_mask
connect slots_0.io.brupdate.b1.resolve_mask, issue_slots[0].brupdate.b1.resolve_mask
connect slots_0.io.grant, issue_slots[0].grant
connect issue_slots[0].request_hp, slots_0.io.request_hp
connect issue_slots[0].request, slots_0.io.request
connect issue_slots[0].will_be_valid, slots_0.io.will_be_valid
connect issue_slots[0].valid, slots_0.io.valid
connect issue_slots[1].debug.state, slots_1.io.debug.state
connect issue_slots[1].debug.ppred, slots_1.io.debug.ppred
connect issue_slots[1].debug.p3, slots_1.io.debug.p3
connect issue_slots[1].debug.p2, slots_1.io.debug.p2
connect issue_slots[1].debug.p1, slots_1.io.debug.p1
connect issue_slots[1].uop.debug_tsrc, slots_1.io.uop.debug_tsrc
connect issue_slots[1].uop.debug_fsrc, slots_1.io.uop.debug_fsrc
connect issue_slots[1].uop.bp_xcpt_if, slots_1.io.uop.bp_xcpt_if
connect issue_slots[1].uop.bp_debug_if, slots_1.io.uop.bp_debug_if
connect issue_slots[1].uop.xcpt_ma_if, slots_1.io.uop.xcpt_ma_if
connect issue_slots[1].uop.xcpt_ae_if, slots_1.io.uop.xcpt_ae_if
connect issue_slots[1].uop.xcpt_pf_if, slots_1.io.uop.xcpt_pf_if
connect issue_slots[1].uop.fp_single, slots_1.io.uop.fp_single
connect issue_slots[1].uop.fp_val, slots_1.io.uop.fp_val
connect issue_slots[1].uop.frs3_en, slots_1.io.uop.frs3_en
connect issue_slots[1].uop.lrs2_rtype, slots_1.io.uop.lrs2_rtype
connect issue_slots[1].uop.lrs1_rtype, slots_1.io.uop.lrs1_rtype
connect issue_slots[1].uop.dst_rtype, slots_1.io.uop.dst_rtype
connect issue_slots[1].uop.ldst_val, slots_1.io.uop.ldst_val
connect issue_slots[1].uop.lrs3, slots_1.io.uop.lrs3
connect issue_slots[1].uop.lrs2, slots_1.io.uop.lrs2
connect issue_slots[1].uop.lrs1, slots_1.io.uop.lrs1
connect issue_slots[1].uop.ldst, slots_1.io.uop.ldst
connect issue_slots[1].uop.ldst_is_rs1, slots_1.io.uop.ldst_is_rs1
connect issue_slots[1].uop.flush_on_commit, slots_1.io.uop.flush_on_commit
connect issue_slots[1].uop.is_unique, slots_1.io.uop.is_unique
connect issue_slots[1].uop.is_sys_pc2epc, slots_1.io.uop.is_sys_pc2epc
connect issue_slots[1].uop.uses_stq, slots_1.io.uop.uses_stq
connect issue_slots[1].uop.uses_ldq, slots_1.io.uop.uses_ldq
connect issue_slots[1].uop.is_amo, slots_1.io.uop.is_amo
connect issue_slots[1].uop.is_fencei, slots_1.io.uop.is_fencei
connect issue_slots[1].uop.is_fence, slots_1.io.uop.is_fence
connect issue_slots[1].uop.mem_signed, slots_1.io.uop.mem_signed
connect issue_slots[1].uop.mem_size, slots_1.io.uop.mem_size
connect issue_slots[1].uop.mem_cmd, slots_1.io.uop.mem_cmd
connect issue_slots[1].uop.bypassable, slots_1.io.uop.bypassable
connect issue_slots[1].uop.exc_cause, slots_1.io.uop.exc_cause
connect issue_slots[1].uop.exception, slots_1.io.uop.exception
connect issue_slots[1].uop.stale_pdst, slots_1.io.uop.stale_pdst
connect issue_slots[1].uop.ppred_busy, slots_1.io.uop.ppred_busy
connect issue_slots[1].uop.prs3_busy, slots_1.io.uop.prs3_busy
connect issue_slots[1].uop.prs2_busy, slots_1.io.uop.prs2_busy
connect issue_slots[1].uop.prs1_busy, slots_1.io.uop.prs1_busy
connect issue_slots[1].uop.ppred, slots_1.io.uop.ppred
connect issue_slots[1].uop.prs3, slots_1.io.uop.prs3
connect issue_slots[1].uop.prs2, slots_1.io.uop.prs2
connect issue_slots[1].uop.prs1, slots_1.io.uop.prs1
connect issue_slots[1].uop.pdst, slots_1.io.uop.pdst
connect issue_slots[1].uop.rxq_idx, slots_1.io.uop.rxq_idx
connect issue_slots[1].uop.stq_idx, slots_1.io.uop.stq_idx
connect issue_slots[1].uop.ldq_idx, slots_1.io.uop.ldq_idx
connect issue_slots[1].uop.rob_idx, slots_1.io.uop.rob_idx
connect issue_slots[1].uop.csr_addr, slots_1.io.uop.csr_addr
connect issue_slots[1].uop.imm_packed, slots_1.io.uop.imm_packed
connect issue_slots[1].uop.taken, slots_1.io.uop.taken
connect issue_slots[1].uop.pc_lob, slots_1.io.uop.pc_lob
connect issue_slots[1].uop.edge_inst, slots_1.io.uop.edge_inst
connect issue_slots[1].uop.ftq_idx, slots_1.io.uop.ftq_idx
connect issue_slots[1].uop.br_tag, slots_1.io.uop.br_tag
connect issue_slots[1].uop.br_mask, slots_1.io.uop.br_mask
connect issue_slots[1].uop.is_sfb, slots_1.io.uop.is_sfb
connect issue_slots[1].uop.is_jal, slots_1.io.uop.is_jal
connect issue_slots[1].uop.is_jalr, slots_1.io.uop.is_jalr
connect issue_slots[1].uop.is_br, slots_1.io.uop.is_br
connect issue_slots[1].uop.iw_p2_poisoned, slots_1.io.uop.iw_p2_poisoned
connect issue_slots[1].uop.iw_p1_poisoned, slots_1.io.uop.iw_p1_poisoned
connect issue_slots[1].uop.iw_state, slots_1.io.uop.iw_state
connect issue_slots[1].uop.ctrl.is_std, slots_1.io.uop.ctrl.is_std
connect issue_slots[1].uop.ctrl.is_sta, slots_1.io.uop.ctrl.is_sta
connect issue_slots[1].uop.ctrl.is_load, slots_1.io.uop.ctrl.is_load
connect issue_slots[1].uop.ctrl.csr_cmd, slots_1.io.uop.ctrl.csr_cmd
connect issue_slots[1].uop.ctrl.fcn_dw, slots_1.io.uop.ctrl.fcn_dw
connect issue_slots[1].uop.ctrl.op_fcn, slots_1.io.uop.ctrl.op_fcn
connect issue_slots[1].uop.ctrl.imm_sel, slots_1.io.uop.ctrl.imm_sel
connect issue_slots[1].uop.ctrl.op2_sel, slots_1.io.uop.ctrl.op2_sel
connect issue_slots[1].uop.ctrl.op1_sel, slots_1.io.uop.ctrl.op1_sel
connect issue_slots[1].uop.ctrl.br_type, slots_1.io.uop.ctrl.br_type
connect issue_slots[1].uop.fu_code, slots_1.io.uop.fu_code
connect issue_slots[1].uop.iq_type, slots_1.io.uop.iq_type
connect issue_slots[1].uop.debug_pc, slots_1.io.uop.debug_pc
connect issue_slots[1].uop.is_rvc, slots_1.io.uop.is_rvc
connect issue_slots[1].uop.debug_inst, slots_1.io.uop.debug_inst
connect issue_slots[1].uop.inst, slots_1.io.uop.inst
connect issue_slots[1].uop.uopc, slots_1.io.uop.uopc
connect issue_slots[1].out_uop.debug_tsrc, slots_1.io.out_uop.debug_tsrc
connect issue_slots[1].out_uop.debug_fsrc, slots_1.io.out_uop.debug_fsrc
connect issue_slots[1].out_uop.bp_xcpt_if, slots_1.io.out_uop.bp_xcpt_if
connect issue_slots[1].out_uop.bp_debug_if, slots_1.io.out_uop.bp_debug_if
connect issue_slots[1].out_uop.xcpt_ma_if, slots_1.io.out_uop.xcpt_ma_if
connect issue_slots[1].out_uop.xcpt_ae_if, slots_1.io.out_uop.xcpt_ae_if
connect issue_slots[1].out_uop.xcpt_pf_if, slots_1.io.out_uop.xcpt_pf_if
connect issue_slots[1].out_uop.fp_single, slots_1.io.out_uop.fp_single
connect issue_slots[1].out_uop.fp_val, slots_1.io.out_uop.fp_val
connect issue_slots[1].out_uop.frs3_en, slots_1.io.out_uop.frs3_en
connect issue_slots[1].out_uop.lrs2_rtype, slots_1.io.out_uop.lrs2_rtype
connect issue_slots[1].out_uop.lrs1_rtype, slots_1.io.out_uop.lrs1_rtype
connect issue_slots[1].out_uop.dst_rtype, slots_1.io.out_uop.dst_rtype
connect issue_slots[1].out_uop.ldst_val, slots_1.io.out_uop.ldst_val
connect issue_slots[1].out_uop.lrs3, slots_1.io.out_uop.lrs3
connect issue_slots[1].out_uop.lrs2, slots_1.io.out_uop.lrs2
connect issue_slots[1].out_uop.lrs1, slots_1.io.out_uop.lrs1
connect issue_slots[1].out_uop.ldst, slots_1.io.out_uop.ldst
connect issue_slots[1].out_uop.ldst_is_rs1, slots_1.io.out_uop.ldst_is_rs1
connect issue_slots[1].out_uop.flush_on_commit, slots_1.io.out_uop.flush_on_commit
connect issue_slots[1].out_uop.is_unique, slots_1.io.out_uop.is_unique
connect issue_slots[1].out_uop.is_sys_pc2epc, slots_1.io.out_uop.is_sys_pc2epc
connect issue_slots[1].out_uop.uses_stq, slots_1.io.out_uop.uses_stq
connect issue_slots[1].out_uop.uses_ldq, slots_1.io.out_uop.uses_ldq
connect issue_slots[1].out_uop.is_amo, slots_1.io.out_uop.is_amo
connect issue_slots[1].out_uop.is_fencei, slots_1.io.out_uop.is_fencei
connect issue_slots[1].out_uop.is_fence, slots_1.io.out_uop.is_fence
connect issue_slots[1].out_uop.mem_signed, slots_1.io.out_uop.mem_signed
connect issue_slots[1].out_uop.mem_size, slots_1.io.out_uop.mem_size
connect issue_slots[1].out_uop.mem_cmd, slots_1.io.out_uop.mem_cmd
connect issue_slots[1].out_uop.bypassable, slots_1.io.out_uop.bypassable
connect issue_slots[1].out_uop.exc_cause, slots_1.io.out_uop.exc_cause
connect issue_slots[1].out_uop.exception, slots_1.io.out_uop.exception
connect issue_slots[1].out_uop.stale_pdst, slots_1.io.out_uop.stale_pdst
connect issue_slots[1].out_uop.ppred_busy, slots_1.io.out_uop.ppred_busy
connect issue_slots[1].out_uop.prs3_busy, slots_1.io.out_uop.prs3_busy
connect issue_slots[1].out_uop.prs2_busy, slots_1.io.out_uop.prs2_busy
connect issue_slots[1].out_uop.prs1_busy, slots_1.io.out_uop.prs1_busy
connect issue_slots[1].out_uop.ppred, slots_1.io.out_uop.ppred
connect issue_slots[1].out_uop.prs3, slots_1.io.out_uop.prs3
connect issue_slots[1].out_uop.prs2, slots_1.io.out_uop.prs2
connect issue_slots[1].out_uop.prs1, slots_1.io.out_uop.prs1
connect issue_slots[1].out_uop.pdst, slots_1.io.out_uop.pdst
connect issue_slots[1].out_uop.rxq_idx, slots_1.io.out_uop.rxq_idx
connect issue_slots[1].out_uop.stq_idx, slots_1.io.out_uop.stq_idx
connect issue_slots[1].out_uop.ldq_idx, slots_1.io.out_uop.ldq_idx
connect issue_slots[1].out_uop.rob_idx, slots_1.io.out_uop.rob_idx
connect issue_slots[1].out_uop.csr_addr, slots_1.io.out_uop.csr_addr
connect issue_slots[1].out_uop.imm_packed, slots_1.io.out_uop.imm_packed
connect issue_slots[1].out_uop.taken, slots_1.io.out_uop.taken
connect issue_slots[1].out_uop.pc_lob, slots_1.io.out_uop.pc_lob
connect issue_slots[1].out_uop.edge_inst, slots_1.io.out_uop.edge_inst
connect issue_slots[1].out_uop.ftq_idx, slots_1.io.out_uop.ftq_idx
connect issue_slots[1].out_uop.br_tag, slots_1.io.out_uop.br_tag
connect issue_slots[1].out_uop.br_mask, slots_1.io.out_uop.br_mask
connect issue_slots[1].out_uop.is_sfb, slots_1.io.out_uop.is_sfb
connect issue_slots[1].out_uop.is_jal, slots_1.io.out_uop.is_jal
connect issue_slots[1].out_uop.is_jalr, slots_1.io.out_uop.is_jalr
connect issue_slots[1].out_uop.is_br, slots_1.io.out_uop.is_br
connect issue_slots[1].out_uop.iw_p2_poisoned, slots_1.io.out_uop.iw_p2_poisoned
connect issue_slots[1].out_uop.iw_p1_poisoned, slots_1.io.out_uop.iw_p1_poisoned
connect issue_slots[1].out_uop.iw_state, slots_1.io.out_uop.iw_state
connect issue_slots[1].out_uop.ctrl.is_std, slots_1.io.out_uop.ctrl.is_std
connect issue_slots[1].out_uop.ctrl.is_sta, slots_1.io.out_uop.ctrl.is_sta
connect issue_slots[1].out_uop.ctrl.is_load, slots_1.io.out_uop.ctrl.is_load
connect issue_slots[1].out_uop.ctrl.csr_cmd, slots_1.io.out_uop.ctrl.csr_cmd
connect issue_slots[1].out_uop.ctrl.fcn_dw, slots_1.io.out_uop.ctrl.fcn_dw
connect issue_slots[1].out_uop.ctrl.op_fcn, slots_1.io.out_uop.ctrl.op_fcn
connect issue_slots[1].out_uop.ctrl.imm_sel, slots_1.io.out_uop.ctrl.imm_sel
connect issue_slots[1].out_uop.ctrl.op2_sel, slots_1.io.out_uop.ctrl.op2_sel
connect issue_slots[1].out_uop.ctrl.op1_sel, slots_1.io.out_uop.ctrl.op1_sel
connect issue_slots[1].out_uop.ctrl.br_type, slots_1.io.out_uop.ctrl.br_type
connect issue_slots[1].out_uop.fu_code, slots_1.io.out_uop.fu_code
connect issue_slots[1].out_uop.iq_type, slots_1.io.out_uop.iq_type
connect issue_slots[1].out_uop.debug_pc, slots_1.io.out_uop.debug_pc
connect issue_slots[1].out_uop.is_rvc, slots_1.io.out_uop.is_rvc
connect issue_slots[1].out_uop.debug_inst, slots_1.io.out_uop.debug_inst
connect issue_slots[1].out_uop.inst, slots_1.io.out_uop.inst
connect issue_slots[1].out_uop.uopc, slots_1.io.out_uop.uopc
connect slots_1.io.in_uop.bits.debug_tsrc, issue_slots[1].in_uop.bits.debug_tsrc
connect slots_1.io.in_uop.bits.debug_fsrc, issue_slots[1].in_uop.bits.debug_fsrc
connect slots_1.io.in_uop.bits.bp_xcpt_if, issue_slots[1].in_uop.bits.bp_xcpt_if
connect slots_1.io.in_uop.bits.bp_debug_if, issue_slots[1].in_uop.bits.bp_debug_if
connect slots_1.io.in_uop.bits.xcpt_ma_if, issue_slots[1].in_uop.bits.xcpt_ma_if
connect slots_1.io.in_uop.bits.xcpt_ae_if, issue_slots[1].in_uop.bits.xcpt_ae_if
connect slots_1.io.in_uop.bits.xcpt_pf_if, issue_slots[1].in_uop.bits.xcpt_pf_if
connect slots_1.io.in_uop.bits.fp_single, issue_slots[1].in_uop.bits.fp_single
connect slots_1.io.in_uop.bits.fp_val, issue_slots[1].in_uop.bits.fp_val
connect slots_1.io.in_uop.bits.frs3_en, issue_slots[1].in_uop.bits.frs3_en
connect slots_1.io.in_uop.bits.lrs2_rtype, issue_slots[1].in_uop.bits.lrs2_rtype
connect slots_1.io.in_uop.bits.lrs1_rtype, issue_slots[1].in_uop.bits.lrs1_rtype
connect slots_1.io.in_uop.bits.dst_rtype, issue_slots[1].in_uop.bits.dst_rtype
connect slots_1.io.in_uop.bits.ldst_val, issue_slots[1].in_uop.bits.ldst_val
connect slots_1.io.in_uop.bits.lrs3, issue_slots[1].in_uop.bits.lrs3
connect slots_1.io.in_uop.bits.lrs2, issue_slots[1].in_uop.bits.lrs2
connect slots_1.io.in_uop.bits.lrs1, issue_slots[1].in_uop.bits.lrs1
connect slots_1.io.in_uop.bits.ldst, issue_slots[1].in_uop.bits.ldst
connect slots_1.io.in_uop.bits.ldst_is_rs1, issue_slots[1].in_uop.bits.ldst_is_rs1
connect slots_1.io.in_uop.bits.flush_on_commit, issue_slots[1].in_uop.bits.flush_on_commit
connect slots_1.io.in_uop.bits.is_unique, issue_slots[1].in_uop.bits.is_unique
connect slots_1.io.in_uop.bits.is_sys_pc2epc, issue_slots[1].in_uop.bits.is_sys_pc2epc
connect slots_1.io.in_uop.bits.uses_stq, issue_slots[1].in_uop.bits.uses_stq
connect slots_1.io.in_uop.bits.uses_ldq, issue_slots[1].in_uop.bits.uses_ldq
connect slots_1.io.in_uop.bits.is_amo, issue_slots[1].in_uop.bits.is_amo
connect slots_1.io.in_uop.bits.is_fencei, issue_slots[1].in_uop.bits.is_fencei
connect slots_1.io.in_uop.bits.is_fence, issue_slots[1].in_uop.bits.is_fence
connect slots_1.io.in_uop.bits.mem_signed, issue_slots[1].in_uop.bits.mem_signed
connect slots_1.io.in_uop.bits.mem_size, issue_slots[1].in_uop.bits.mem_size
connect slots_1.io.in_uop.bits.mem_cmd, issue_slots[1].in_uop.bits.mem_cmd
connect slots_1.io.in_uop.bits.bypassable, issue_slots[1].in_uop.bits.bypassable
connect slots_1.io.in_uop.bits.exc_cause, issue_slots[1].in_uop.bits.exc_cause
connect slots_1.io.in_uop.bits.exception, issue_slots[1].in_uop.bits.exception
connect slots_1.io.in_uop.bits.stale_pdst, issue_slots[1].in_uop.bits.stale_pdst
connect slots_1.io.in_uop.bits.ppred_busy, issue_slots[1].in_uop.bits.ppred_busy
connect slots_1.io.in_uop.bits.prs3_busy, issue_slots[1].in_uop.bits.prs3_busy
connect slots_1.io.in_uop.bits.prs2_busy, issue_slots[1].in_uop.bits.prs2_busy
connect slots_1.io.in_uop.bits.prs1_busy, issue_slots[1].in_uop.bits.prs1_busy
connect slots_1.io.in_uop.bits.ppred, issue_slots[1].in_uop.bits.ppred
connect slots_1.io.in_uop.bits.prs3, issue_slots[1].in_uop.bits.prs3
connect slots_1.io.in_uop.bits.prs2, issue_slots[1].in_uop.bits.prs2
connect slots_1.io.in_uop.bits.prs1, issue_slots[1].in_uop.bits.prs1
connect slots_1.io.in_uop.bits.pdst, issue_slots[1].in_uop.bits.pdst
connect slots_1.io.in_uop.bits.rxq_idx, issue_slots[1].in_uop.bits.rxq_idx
connect slots_1.io.in_uop.bits.stq_idx, issue_slots[1].in_uop.bits.stq_idx
connect slots_1.io.in_uop.bits.ldq_idx, issue_slots[1].in_uop.bits.ldq_idx
connect slots_1.io.in_uop.bits.rob_idx, issue_slots[1].in_uop.bits.rob_idx
connect slots_1.io.in_uop.bits.csr_addr, issue_slots[1].in_uop.bits.csr_addr
connect slots_1.io.in_uop.bits.imm_packed, issue_slots[1].in_uop.bits.imm_packed
connect slots_1.io.in_uop.bits.taken, issue_slots[1].in_uop.bits.taken
connect slots_1.io.in_uop.bits.pc_lob, issue_slots[1].in_uop.bits.pc_lob
connect slots_1.io.in_uop.bits.edge_inst, issue_slots[1].in_uop.bits.edge_inst
connect slots_1.io.in_uop.bits.ftq_idx, issue_slots[1].in_uop.bits.ftq_idx
connect slots_1.io.in_uop.bits.br_tag, issue_slots[1].in_uop.bits.br_tag
connect slots_1.io.in_uop.bits.br_mask, issue_slots[1].in_uop.bits.br_mask
connect slots_1.io.in_uop.bits.is_sfb, issue_slots[1].in_uop.bits.is_sfb
connect slots_1.io.in_uop.bits.is_jal, issue_slots[1].in_uop.bits.is_jal
connect slots_1.io.in_uop.bits.is_jalr, issue_slots[1].in_uop.bits.is_jalr
connect slots_1.io.in_uop.bits.is_br, issue_slots[1].in_uop.bits.is_br
connect slots_1.io.in_uop.bits.iw_p2_poisoned, issue_slots[1].in_uop.bits.iw_p2_poisoned
connect slots_1.io.in_uop.bits.iw_p1_poisoned, issue_slots[1].in_uop.bits.iw_p1_poisoned
connect slots_1.io.in_uop.bits.iw_state, issue_slots[1].in_uop.bits.iw_state
connect slots_1.io.in_uop.bits.ctrl.is_std, issue_slots[1].in_uop.bits.ctrl.is_std
connect slots_1.io.in_uop.bits.ctrl.is_sta, issue_slots[1].in_uop.bits.ctrl.is_sta
connect slots_1.io.in_uop.bits.ctrl.is_load, issue_slots[1].in_uop.bits.ctrl.is_load
connect slots_1.io.in_uop.bits.ctrl.csr_cmd, issue_slots[1].in_uop.bits.ctrl.csr_cmd
connect slots_1.io.in_uop.bits.ctrl.fcn_dw, issue_slots[1].in_uop.bits.ctrl.fcn_dw
connect slots_1.io.in_uop.bits.ctrl.op_fcn, issue_slots[1].in_uop.bits.ctrl.op_fcn
connect slots_1.io.in_uop.bits.ctrl.imm_sel, issue_slots[1].in_uop.bits.ctrl.imm_sel
connect slots_1.io.in_uop.bits.ctrl.op2_sel, issue_slots[1].in_uop.bits.ctrl.op2_sel
connect slots_1.io.in_uop.bits.ctrl.op1_sel, issue_slots[1].in_uop.bits.ctrl.op1_sel
connect slots_1.io.in_uop.bits.ctrl.br_type, issue_slots[1].in_uop.bits.ctrl.br_type
connect slots_1.io.in_uop.bits.fu_code, issue_slots[1].in_uop.bits.fu_code
connect slots_1.io.in_uop.bits.iq_type, issue_slots[1].in_uop.bits.iq_type
connect slots_1.io.in_uop.bits.debug_pc, issue_slots[1].in_uop.bits.debug_pc
connect slots_1.io.in_uop.bits.is_rvc, issue_slots[1].in_uop.bits.is_rvc
connect slots_1.io.in_uop.bits.debug_inst, issue_slots[1].in_uop.bits.debug_inst
connect slots_1.io.in_uop.bits.inst, issue_slots[1].in_uop.bits.inst
connect slots_1.io.in_uop.bits.uopc, issue_slots[1].in_uop.bits.uopc
connect slots_1.io.in_uop.valid, issue_slots[1].in_uop.valid
connect slots_1.io.spec_ld_wakeup[0].bits, issue_slots[1].spec_ld_wakeup[0].bits
connect slots_1.io.spec_ld_wakeup[0].valid, issue_slots[1].spec_ld_wakeup[0].valid
connect slots_1.io.pred_wakeup_port.bits, issue_slots[1].pred_wakeup_port.bits
connect slots_1.io.pred_wakeup_port.valid, issue_slots[1].pred_wakeup_port.valid
connect slots_1.io.wakeup_ports[0].bits.poisoned, issue_slots[1].wakeup_ports[0].bits.poisoned
connect slots_1.io.wakeup_ports[0].bits.pdst, issue_slots[1].wakeup_ports[0].bits.pdst
connect slots_1.io.wakeup_ports[0].valid, issue_slots[1].wakeup_ports[0].valid
connect slots_1.io.wakeup_ports[1].bits.poisoned, issue_slots[1].wakeup_ports[1].bits.poisoned
connect slots_1.io.wakeup_ports[1].bits.pdst, issue_slots[1].wakeup_ports[1].bits.pdst
connect slots_1.io.wakeup_ports[1].valid, issue_slots[1].wakeup_ports[1].valid
connect slots_1.io.wakeup_ports[2].bits.poisoned, issue_slots[1].wakeup_ports[2].bits.poisoned
connect slots_1.io.wakeup_ports[2].bits.pdst, issue_slots[1].wakeup_ports[2].bits.pdst
connect slots_1.io.wakeup_ports[2].valid, issue_slots[1].wakeup_ports[2].valid
connect slots_1.io.ldspec_miss, issue_slots[1].ldspec_miss
connect slots_1.io.clear, issue_slots[1].clear
connect slots_1.io.kill, issue_slots[1].kill
connect slots_1.io.brupdate.b2.target_offset, issue_slots[1].brupdate.b2.target_offset
connect slots_1.io.brupdate.b2.jalr_target, issue_slots[1].brupdate.b2.jalr_target
connect slots_1.io.brupdate.b2.pc_sel, issue_slots[1].brupdate.b2.pc_sel
connect slots_1.io.brupdate.b2.cfi_type, issue_slots[1].brupdate.b2.cfi_type
connect slots_1.io.brupdate.b2.taken, issue_slots[1].brupdate.b2.taken
connect slots_1.io.brupdate.b2.mispredict, issue_slots[1].brupdate.b2.mispredict
connect slots_1.io.brupdate.b2.valid, issue_slots[1].brupdate.b2.valid
connect slots_1.io.brupdate.b2.uop.debug_tsrc, issue_slots[1].brupdate.b2.uop.debug_tsrc
connect slots_1.io.brupdate.b2.uop.debug_fsrc, issue_slots[1].brupdate.b2.uop.debug_fsrc
connect slots_1.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[1].brupdate.b2.uop.bp_xcpt_if
connect slots_1.io.brupdate.b2.uop.bp_debug_if, issue_slots[1].brupdate.b2.uop.bp_debug_if
connect slots_1.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[1].brupdate.b2.uop.xcpt_ma_if
connect slots_1.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[1].brupdate.b2.uop.xcpt_ae_if
connect slots_1.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[1].brupdate.b2.uop.xcpt_pf_if
connect slots_1.io.brupdate.b2.uop.fp_single, issue_slots[1].brupdate.b2.uop.fp_single
connect slots_1.io.brupdate.b2.uop.fp_val, issue_slots[1].brupdate.b2.uop.fp_val
connect slots_1.io.brupdate.b2.uop.frs3_en, issue_slots[1].brupdate.b2.uop.frs3_en
connect slots_1.io.brupdate.b2.uop.lrs2_rtype, issue_slots[1].brupdate.b2.uop.lrs2_rtype
connect slots_1.io.brupdate.b2.uop.lrs1_rtype, issue_slots[1].brupdate.b2.uop.lrs1_rtype
connect slots_1.io.brupdate.b2.uop.dst_rtype, issue_slots[1].brupdate.b2.uop.dst_rtype
connect slots_1.io.brupdate.b2.uop.ldst_val, issue_slots[1].brupdate.b2.uop.ldst_val
connect slots_1.io.brupdate.b2.uop.lrs3, issue_slots[1].brupdate.b2.uop.lrs3
connect slots_1.io.brupdate.b2.uop.lrs2, issue_slots[1].brupdate.b2.uop.lrs2
connect slots_1.io.brupdate.b2.uop.lrs1, issue_slots[1].brupdate.b2.uop.lrs1
connect slots_1.io.brupdate.b2.uop.ldst, issue_slots[1].brupdate.b2.uop.ldst
connect slots_1.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[1].brupdate.b2.uop.ldst_is_rs1
connect slots_1.io.brupdate.b2.uop.flush_on_commit, issue_slots[1].brupdate.b2.uop.flush_on_commit
connect slots_1.io.brupdate.b2.uop.is_unique, issue_slots[1].brupdate.b2.uop.is_unique
connect slots_1.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[1].brupdate.b2.uop.is_sys_pc2epc
connect slots_1.io.brupdate.b2.uop.uses_stq, issue_slots[1].brupdate.b2.uop.uses_stq
connect slots_1.io.brupdate.b2.uop.uses_ldq, issue_slots[1].brupdate.b2.uop.uses_ldq
connect slots_1.io.brupdate.b2.uop.is_amo, issue_slots[1].brupdate.b2.uop.is_amo
connect slots_1.io.brupdate.b2.uop.is_fencei, issue_slots[1].brupdate.b2.uop.is_fencei
connect slots_1.io.brupdate.b2.uop.is_fence, issue_slots[1].brupdate.b2.uop.is_fence
connect slots_1.io.brupdate.b2.uop.mem_signed, issue_slots[1].brupdate.b2.uop.mem_signed
connect slots_1.io.brupdate.b2.uop.mem_size, issue_slots[1].brupdate.b2.uop.mem_size
connect slots_1.io.brupdate.b2.uop.mem_cmd, issue_slots[1].brupdate.b2.uop.mem_cmd
connect slots_1.io.brupdate.b2.uop.bypassable, issue_slots[1].brupdate.b2.uop.bypassable
connect slots_1.io.brupdate.b2.uop.exc_cause, issue_slots[1].brupdate.b2.uop.exc_cause
connect slots_1.io.brupdate.b2.uop.exception, issue_slots[1].brupdate.b2.uop.exception
connect slots_1.io.brupdate.b2.uop.stale_pdst, issue_slots[1].brupdate.b2.uop.stale_pdst
connect slots_1.io.brupdate.b2.uop.ppred_busy, issue_slots[1].brupdate.b2.uop.ppred_busy
connect slots_1.io.brupdate.b2.uop.prs3_busy, issue_slots[1].brupdate.b2.uop.prs3_busy
connect slots_1.io.brupdate.b2.uop.prs2_busy, issue_slots[1].brupdate.b2.uop.prs2_busy
connect slots_1.io.brupdate.b2.uop.prs1_busy, issue_slots[1].brupdate.b2.uop.prs1_busy
connect slots_1.io.brupdate.b2.uop.ppred, issue_slots[1].brupdate.b2.uop.ppred
connect slots_1.io.brupdate.b2.uop.prs3, issue_slots[1].brupdate.b2.uop.prs3
connect slots_1.io.brupdate.b2.uop.prs2, issue_slots[1].brupdate.b2.uop.prs2
connect slots_1.io.brupdate.b2.uop.prs1, issue_slots[1].brupdate.b2.uop.prs1
connect slots_1.io.brupdate.b2.uop.pdst, issue_slots[1].brupdate.b2.uop.pdst
connect slots_1.io.brupdate.b2.uop.rxq_idx, issue_slots[1].brupdate.b2.uop.rxq_idx
connect slots_1.io.brupdate.b2.uop.stq_idx, issue_slots[1].brupdate.b2.uop.stq_idx
connect slots_1.io.brupdate.b2.uop.ldq_idx, issue_slots[1].brupdate.b2.uop.ldq_idx
connect slots_1.io.brupdate.b2.uop.rob_idx, issue_slots[1].brupdate.b2.uop.rob_idx
connect slots_1.io.brupdate.b2.uop.csr_addr, issue_slots[1].brupdate.b2.uop.csr_addr
connect slots_1.io.brupdate.b2.uop.imm_packed, issue_slots[1].brupdate.b2.uop.imm_packed
connect slots_1.io.brupdate.b2.uop.taken, issue_slots[1].brupdate.b2.uop.taken
connect slots_1.io.brupdate.b2.uop.pc_lob, issue_slots[1].brupdate.b2.uop.pc_lob
connect slots_1.io.brupdate.b2.uop.edge_inst, issue_slots[1].brupdate.b2.uop.edge_inst
connect slots_1.io.brupdate.b2.uop.ftq_idx, issue_slots[1].brupdate.b2.uop.ftq_idx
connect slots_1.io.brupdate.b2.uop.br_tag, issue_slots[1].brupdate.b2.uop.br_tag
connect slots_1.io.brupdate.b2.uop.br_mask, issue_slots[1].brupdate.b2.uop.br_mask
connect slots_1.io.brupdate.b2.uop.is_sfb, issue_slots[1].brupdate.b2.uop.is_sfb
connect slots_1.io.brupdate.b2.uop.is_jal, issue_slots[1].brupdate.b2.uop.is_jal
connect slots_1.io.brupdate.b2.uop.is_jalr, issue_slots[1].brupdate.b2.uop.is_jalr
connect slots_1.io.brupdate.b2.uop.is_br, issue_slots[1].brupdate.b2.uop.is_br
connect slots_1.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[1].brupdate.b2.uop.iw_p2_poisoned
connect slots_1.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[1].brupdate.b2.uop.iw_p1_poisoned
connect slots_1.io.brupdate.b2.uop.iw_state, issue_slots[1].brupdate.b2.uop.iw_state
connect slots_1.io.brupdate.b2.uop.ctrl.is_std, issue_slots[1].brupdate.b2.uop.ctrl.is_std
connect slots_1.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[1].brupdate.b2.uop.ctrl.is_sta
connect slots_1.io.brupdate.b2.uop.ctrl.is_load, issue_slots[1].brupdate.b2.uop.ctrl.is_load
connect slots_1.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[1].brupdate.b2.uop.ctrl.csr_cmd
connect slots_1.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[1].brupdate.b2.uop.ctrl.fcn_dw
connect slots_1.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[1].brupdate.b2.uop.ctrl.op_fcn
connect slots_1.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[1].brupdate.b2.uop.ctrl.imm_sel
connect slots_1.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[1].brupdate.b2.uop.ctrl.op2_sel
connect slots_1.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[1].brupdate.b2.uop.ctrl.op1_sel
connect slots_1.io.brupdate.b2.uop.ctrl.br_type, issue_slots[1].brupdate.b2.uop.ctrl.br_type
connect slots_1.io.brupdate.b2.uop.fu_code, issue_slots[1].brupdate.b2.uop.fu_code
connect slots_1.io.brupdate.b2.uop.iq_type, issue_slots[1].brupdate.b2.uop.iq_type
connect slots_1.io.brupdate.b2.uop.debug_pc, issue_slots[1].brupdate.b2.uop.debug_pc
connect slots_1.io.brupdate.b2.uop.is_rvc, issue_slots[1].brupdate.b2.uop.is_rvc
connect slots_1.io.brupdate.b2.uop.debug_inst, issue_slots[1].brupdate.b2.uop.debug_inst
connect slots_1.io.brupdate.b2.uop.inst, issue_slots[1].brupdate.b2.uop.inst
connect slots_1.io.brupdate.b2.uop.uopc, issue_slots[1].brupdate.b2.uop.uopc
connect slots_1.io.brupdate.b1.mispredict_mask, issue_slots[1].brupdate.b1.mispredict_mask
connect slots_1.io.brupdate.b1.resolve_mask, issue_slots[1].brupdate.b1.resolve_mask
connect slots_1.io.grant, issue_slots[1].grant
connect issue_slots[1].request_hp, slots_1.io.request_hp
connect issue_slots[1].request, slots_1.io.request
connect issue_slots[1].will_be_valid, slots_1.io.will_be_valid
connect issue_slots[1].valid, slots_1.io.valid
connect issue_slots[2].debug.state, slots_2.io.debug.state
connect issue_slots[2].debug.ppred, slots_2.io.debug.ppred
connect issue_slots[2].debug.p3, slots_2.io.debug.p3
connect issue_slots[2].debug.p2, slots_2.io.debug.p2
connect issue_slots[2].debug.p1, slots_2.io.debug.p1
connect issue_slots[2].uop.debug_tsrc, slots_2.io.uop.debug_tsrc
connect issue_slots[2].uop.debug_fsrc, slots_2.io.uop.debug_fsrc
connect issue_slots[2].uop.bp_xcpt_if, slots_2.io.uop.bp_xcpt_if
connect issue_slots[2].uop.bp_debug_if, slots_2.io.uop.bp_debug_if
connect issue_slots[2].uop.xcpt_ma_if, slots_2.io.uop.xcpt_ma_if
connect issue_slots[2].uop.xcpt_ae_if, slots_2.io.uop.xcpt_ae_if
connect issue_slots[2].uop.xcpt_pf_if, slots_2.io.uop.xcpt_pf_if
connect issue_slots[2].uop.fp_single, slots_2.io.uop.fp_single
connect issue_slots[2].uop.fp_val, slots_2.io.uop.fp_val
connect issue_slots[2].uop.frs3_en, slots_2.io.uop.frs3_en
connect issue_slots[2].uop.lrs2_rtype, slots_2.io.uop.lrs2_rtype
connect issue_slots[2].uop.lrs1_rtype, slots_2.io.uop.lrs1_rtype
connect issue_slots[2].uop.dst_rtype, slots_2.io.uop.dst_rtype
connect issue_slots[2].uop.ldst_val, slots_2.io.uop.ldst_val
connect issue_slots[2].uop.lrs3, slots_2.io.uop.lrs3
connect issue_slots[2].uop.lrs2, slots_2.io.uop.lrs2
connect issue_slots[2].uop.lrs1, slots_2.io.uop.lrs1
connect issue_slots[2].uop.ldst, slots_2.io.uop.ldst
connect issue_slots[2].uop.ldst_is_rs1, slots_2.io.uop.ldst_is_rs1
connect issue_slots[2].uop.flush_on_commit, slots_2.io.uop.flush_on_commit
connect issue_slots[2].uop.is_unique, slots_2.io.uop.is_unique
connect issue_slots[2].uop.is_sys_pc2epc, slots_2.io.uop.is_sys_pc2epc
connect issue_slots[2].uop.uses_stq, slots_2.io.uop.uses_stq
connect issue_slots[2].uop.uses_ldq, slots_2.io.uop.uses_ldq
connect issue_slots[2].uop.is_amo, slots_2.io.uop.is_amo
connect issue_slots[2].uop.is_fencei, slots_2.io.uop.is_fencei
connect issue_slots[2].uop.is_fence, slots_2.io.uop.is_fence
connect issue_slots[2].uop.mem_signed, slots_2.io.uop.mem_signed
connect issue_slots[2].uop.mem_size, slots_2.io.uop.mem_size
connect issue_slots[2].uop.mem_cmd, slots_2.io.uop.mem_cmd
connect issue_slots[2].uop.bypassable, slots_2.io.uop.bypassable
connect issue_slots[2].uop.exc_cause, slots_2.io.uop.exc_cause
connect issue_slots[2].uop.exception, slots_2.io.uop.exception
connect issue_slots[2].uop.stale_pdst, slots_2.io.uop.stale_pdst
connect issue_slots[2].uop.ppred_busy, slots_2.io.uop.ppred_busy
connect issue_slots[2].uop.prs3_busy, slots_2.io.uop.prs3_busy
connect issue_slots[2].uop.prs2_busy, slots_2.io.uop.prs2_busy
connect issue_slots[2].uop.prs1_busy, slots_2.io.uop.prs1_busy
connect issue_slots[2].uop.ppred, slots_2.io.uop.ppred
connect issue_slots[2].uop.prs3, slots_2.io.uop.prs3
connect issue_slots[2].uop.prs2, slots_2.io.uop.prs2
connect issue_slots[2].uop.prs1, slots_2.io.uop.prs1
connect issue_slots[2].uop.pdst, slots_2.io.uop.pdst
connect issue_slots[2].uop.rxq_idx, slots_2.io.uop.rxq_idx
connect issue_slots[2].uop.stq_idx, slots_2.io.uop.stq_idx
connect issue_slots[2].uop.ldq_idx, slots_2.io.uop.ldq_idx
connect issue_slots[2].uop.rob_idx, slots_2.io.uop.rob_idx
connect issue_slots[2].uop.csr_addr, slots_2.io.uop.csr_addr
connect issue_slots[2].uop.imm_packed, slots_2.io.uop.imm_packed
connect issue_slots[2].uop.taken, slots_2.io.uop.taken
connect issue_slots[2].uop.pc_lob, slots_2.io.uop.pc_lob
connect issue_slots[2].uop.edge_inst, slots_2.io.uop.edge_inst
connect issue_slots[2].uop.ftq_idx, slots_2.io.uop.ftq_idx
connect issue_slots[2].uop.br_tag, slots_2.io.uop.br_tag
connect issue_slots[2].uop.br_mask, slots_2.io.uop.br_mask
connect issue_slots[2].uop.is_sfb, slots_2.io.uop.is_sfb
connect issue_slots[2].uop.is_jal, slots_2.io.uop.is_jal
connect issue_slots[2].uop.is_jalr, slots_2.io.uop.is_jalr
connect issue_slots[2].uop.is_br, slots_2.io.uop.is_br
connect issue_slots[2].uop.iw_p2_poisoned, slots_2.io.uop.iw_p2_poisoned
connect issue_slots[2].uop.iw_p1_poisoned, slots_2.io.uop.iw_p1_poisoned
connect issue_slots[2].uop.iw_state, slots_2.io.uop.iw_state
connect issue_slots[2].uop.ctrl.is_std, slots_2.io.uop.ctrl.is_std
connect issue_slots[2].uop.ctrl.is_sta, slots_2.io.uop.ctrl.is_sta
connect issue_slots[2].uop.ctrl.is_load, slots_2.io.uop.ctrl.is_load
connect issue_slots[2].uop.ctrl.csr_cmd, slots_2.io.uop.ctrl.csr_cmd
connect issue_slots[2].uop.ctrl.fcn_dw, slots_2.io.uop.ctrl.fcn_dw
connect issue_slots[2].uop.ctrl.op_fcn, slots_2.io.uop.ctrl.op_fcn
connect issue_slots[2].uop.ctrl.imm_sel, slots_2.io.uop.ctrl.imm_sel
connect issue_slots[2].uop.ctrl.op2_sel, slots_2.io.uop.ctrl.op2_sel
connect issue_slots[2].uop.ctrl.op1_sel, slots_2.io.uop.ctrl.op1_sel
connect issue_slots[2].uop.ctrl.br_type, slots_2.io.uop.ctrl.br_type
connect issue_slots[2].uop.fu_code, slots_2.io.uop.fu_code
connect issue_slots[2].uop.iq_type, slots_2.io.uop.iq_type
connect issue_slots[2].uop.debug_pc, slots_2.io.uop.debug_pc
connect issue_slots[2].uop.is_rvc, slots_2.io.uop.is_rvc
connect issue_slots[2].uop.debug_inst, slots_2.io.uop.debug_inst
connect issue_slots[2].uop.inst, slots_2.io.uop.inst
connect issue_slots[2].uop.uopc, slots_2.io.uop.uopc
connect issue_slots[2].out_uop.debug_tsrc, slots_2.io.out_uop.debug_tsrc
connect issue_slots[2].out_uop.debug_fsrc, slots_2.io.out_uop.debug_fsrc
connect issue_slots[2].out_uop.bp_xcpt_if, slots_2.io.out_uop.bp_xcpt_if
connect issue_slots[2].out_uop.bp_debug_if, slots_2.io.out_uop.bp_debug_if
connect issue_slots[2].out_uop.xcpt_ma_if, slots_2.io.out_uop.xcpt_ma_if
connect issue_slots[2].out_uop.xcpt_ae_if, slots_2.io.out_uop.xcpt_ae_if
connect issue_slots[2].out_uop.xcpt_pf_if, slots_2.io.out_uop.xcpt_pf_if
connect issue_slots[2].out_uop.fp_single, slots_2.io.out_uop.fp_single
connect issue_slots[2].out_uop.fp_val, slots_2.io.out_uop.fp_val
connect issue_slots[2].out_uop.frs3_en, slots_2.io.out_uop.frs3_en
connect issue_slots[2].out_uop.lrs2_rtype, slots_2.io.out_uop.lrs2_rtype
connect issue_slots[2].out_uop.lrs1_rtype, slots_2.io.out_uop.lrs1_rtype
connect issue_slots[2].out_uop.dst_rtype, slots_2.io.out_uop.dst_rtype
connect issue_slots[2].out_uop.ldst_val, slots_2.io.out_uop.ldst_val
connect issue_slots[2].out_uop.lrs3, slots_2.io.out_uop.lrs3
connect issue_slots[2].out_uop.lrs2, slots_2.io.out_uop.lrs2
connect issue_slots[2].out_uop.lrs1, slots_2.io.out_uop.lrs1
connect issue_slots[2].out_uop.ldst, slots_2.io.out_uop.ldst
connect issue_slots[2].out_uop.ldst_is_rs1, slots_2.io.out_uop.ldst_is_rs1
connect issue_slots[2].out_uop.flush_on_commit, slots_2.io.out_uop.flush_on_commit
connect issue_slots[2].out_uop.is_unique, slots_2.io.out_uop.is_unique
connect issue_slots[2].out_uop.is_sys_pc2epc, slots_2.io.out_uop.is_sys_pc2epc
connect issue_slots[2].out_uop.uses_stq, slots_2.io.out_uop.uses_stq
connect issue_slots[2].out_uop.uses_ldq, slots_2.io.out_uop.uses_ldq
connect issue_slots[2].out_uop.is_amo, slots_2.io.out_uop.is_amo
connect issue_slots[2].out_uop.is_fencei, slots_2.io.out_uop.is_fencei
connect issue_slots[2].out_uop.is_fence, slots_2.io.out_uop.is_fence
connect issue_slots[2].out_uop.mem_signed, slots_2.io.out_uop.mem_signed
connect issue_slots[2].out_uop.mem_size, slots_2.io.out_uop.mem_size
connect issue_slots[2].out_uop.mem_cmd, slots_2.io.out_uop.mem_cmd
connect issue_slots[2].out_uop.bypassable, slots_2.io.out_uop.bypassable
connect issue_slots[2].out_uop.exc_cause, slots_2.io.out_uop.exc_cause
connect issue_slots[2].out_uop.exception, slots_2.io.out_uop.exception
connect issue_slots[2].out_uop.stale_pdst, slots_2.io.out_uop.stale_pdst
connect issue_slots[2].out_uop.ppred_busy, slots_2.io.out_uop.ppred_busy
connect issue_slots[2].out_uop.prs3_busy, slots_2.io.out_uop.prs3_busy
connect issue_slots[2].out_uop.prs2_busy, slots_2.io.out_uop.prs2_busy
connect issue_slots[2].out_uop.prs1_busy, slots_2.io.out_uop.prs1_busy
connect issue_slots[2].out_uop.ppred, slots_2.io.out_uop.ppred
connect issue_slots[2].out_uop.prs3, slots_2.io.out_uop.prs3
connect issue_slots[2].out_uop.prs2, slots_2.io.out_uop.prs2
connect issue_slots[2].out_uop.prs1, slots_2.io.out_uop.prs1
connect issue_slots[2].out_uop.pdst, slots_2.io.out_uop.pdst
connect issue_slots[2].out_uop.rxq_idx, slots_2.io.out_uop.rxq_idx
connect issue_slots[2].out_uop.stq_idx, slots_2.io.out_uop.stq_idx
connect issue_slots[2].out_uop.ldq_idx, slots_2.io.out_uop.ldq_idx
connect issue_slots[2].out_uop.rob_idx, slots_2.io.out_uop.rob_idx
connect issue_slots[2].out_uop.csr_addr, slots_2.io.out_uop.csr_addr
connect issue_slots[2].out_uop.imm_packed, slots_2.io.out_uop.imm_packed
connect issue_slots[2].out_uop.taken, slots_2.io.out_uop.taken
connect issue_slots[2].out_uop.pc_lob, slots_2.io.out_uop.pc_lob
connect issue_slots[2].out_uop.edge_inst, slots_2.io.out_uop.edge_inst
connect issue_slots[2].out_uop.ftq_idx, slots_2.io.out_uop.ftq_idx
connect issue_slots[2].out_uop.br_tag, slots_2.io.out_uop.br_tag
connect issue_slots[2].out_uop.br_mask, slots_2.io.out_uop.br_mask
connect issue_slots[2].out_uop.is_sfb, slots_2.io.out_uop.is_sfb
connect issue_slots[2].out_uop.is_jal, slots_2.io.out_uop.is_jal
connect issue_slots[2].out_uop.is_jalr, slots_2.io.out_uop.is_jalr
connect issue_slots[2].out_uop.is_br, slots_2.io.out_uop.is_br
connect issue_slots[2].out_uop.iw_p2_poisoned, slots_2.io.out_uop.iw_p2_poisoned
connect issue_slots[2].out_uop.iw_p1_poisoned, slots_2.io.out_uop.iw_p1_poisoned
connect issue_slots[2].out_uop.iw_state, slots_2.io.out_uop.iw_state
connect issue_slots[2].out_uop.ctrl.is_std, slots_2.io.out_uop.ctrl.is_std
connect issue_slots[2].out_uop.ctrl.is_sta, slots_2.io.out_uop.ctrl.is_sta
connect issue_slots[2].out_uop.ctrl.is_load, slots_2.io.out_uop.ctrl.is_load
connect issue_slots[2].out_uop.ctrl.csr_cmd, slots_2.io.out_uop.ctrl.csr_cmd
connect issue_slots[2].out_uop.ctrl.fcn_dw, slots_2.io.out_uop.ctrl.fcn_dw
connect issue_slots[2].out_uop.ctrl.op_fcn, slots_2.io.out_uop.ctrl.op_fcn
connect issue_slots[2].out_uop.ctrl.imm_sel, slots_2.io.out_uop.ctrl.imm_sel
connect issue_slots[2].out_uop.ctrl.op2_sel, slots_2.io.out_uop.ctrl.op2_sel
connect issue_slots[2].out_uop.ctrl.op1_sel, slots_2.io.out_uop.ctrl.op1_sel
connect issue_slots[2].out_uop.ctrl.br_type, slots_2.io.out_uop.ctrl.br_type
connect issue_slots[2].out_uop.fu_code, slots_2.io.out_uop.fu_code
connect issue_slots[2].out_uop.iq_type, slots_2.io.out_uop.iq_type
connect issue_slots[2].out_uop.debug_pc, slots_2.io.out_uop.debug_pc
connect issue_slots[2].out_uop.is_rvc, slots_2.io.out_uop.is_rvc
connect issue_slots[2].out_uop.debug_inst, slots_2.io.out_uop.debug_inst
connect issue_slots[2].out_uop.inst, slots_2.io.out_uop.inst
connect issue_slots[2].out_uop.uopc, slots_2.io.out_uop.uopc
connect slots_2.io.in_uop.bits.debug_tsrc, issue_slots[2].in_uop.bits.debug_tsrc
connect slots_2.io.in_uop.bits.debug_fsrc, issue_slots[2].in_uop.bits.debug_fsrc
connect slots_2.io.in_uop.bits.bp_xcpt_if, issue_slots[2].in_uop.bits.bp_xcpt_if
connect slots_2.io.in_uop.bits.bp_debug_if, issue_slots[2].in_uop.bits.bp_debug_if
connect slots_2.io.in_uop.bits.xcpt_ma_if, issue_slots[2].in_uop.bits.xcpt_ma_if
connect slots_2.io.in_uop.bits.xcpt_ae_if, issue_slots[2].in_uop.bits.xcpt_ae_if
connect slots_2.io.in_uop.bits.xcpt_pf_if, issue_slots[2].in_uop.bits.xcpt_pf_if
connect slots_2.io.in_uop.bits.fp_single, issue_slots[2].in_uop.bits.fp_single
connect slots_2.io.in_uop.bits.fp_val, issue_slots[2].in_uop.bits.fp_val
connect slots_2.io.in_uop.bits.frs3_en, issue_slots[2].in_uop.bits.frs3_en
connect slots_2.io.in_uop.bits.lrs2_rtype, issue_slots[2].in_uop.bits.lrs2_rtype
connect slots_2.io.in_uop.bits.lrs1_rtype, issue_slots[2].in_uop.bits.lrs1_rtype
connect slots_2.io.in_uop.bits.dst_rtype, issue_slots[2].in_uop.bits.dst_rtype
connect slots_2.io.in_uop.bits.ldst_val, issue_slots[2].in_uop.bits.ldst_val
connect slots_2.io.in_uop.bits.lrs3, issue_slots[2].in_uop.bits.lrs3
connect slots_2.io.in_uop.bits.lrs2, issue_slots[2].in_uop.bits.lrs2
connect slots_2.io.in_uop.bits.lrs1, issue_slots[2].in_uop.bits.lrs1
connect slots_2.io.in_uop.bits.ldst, issue_slots[2].in_uop.bits.ldst
connect slots_2.io.in_uop.bits.ldst_is_rs1, issue_slots[2].in_uop.bits.ldst_is_rs1
connect slots_2.io.in_uop.bits.flush_on_commit, issue_slots[2].in_uop.bits.flush_on_commit
connect slots_2.io.in_uop.bits.is_unique, issue_slots[2].in_uop.bits.is_unique
connect slots_2.io.in_uop.bits.is_sys_pc2epc, issue_slots[2].in_uop.bits.is_sys_pc2epc
connect slots_2.io.in_uop.bits.uses_stq, issue_slots[2].in_uop.bits.uses_stq
connect slots_2.io.in_uop.bits.uses_ldq, issue_slots[2].in_uop.bits.uses_ldq
connect slots_2.io.in_uop.bits.is_amo, issue_slots[2].in_uop.bits.is_amo
connect slots_2.io.in_uop.bits.is_fencei, issue_slots[2].in_uop.bits.is_fencei
connect slots_2.io.in_uop.bits.is_fence, issue_slots[2].in_uop.bits.is_fence
connect slots_2.io.in_uop.bits.mem_signed, issue_slots[2].in_uop.bits.mem_signed
connect slots_2.io.in_uop.bits.mem_size, issue_slots[2].in_uop.bits.mem_size
connect slots_2.io.in_uop.bits.mem_cmd, issue_slots[2].in_uop.bits.mem_cmd
connect slots_2.io.in_uop.bits.bypassable, issue_slots[2].in_uop.bits.bypassable
connect slots_2.io.in_uop.bits.exc_cause, issue_slots[2].in_uop.bits.exc_cause
connect slots_2.io.in_uop.bits.exception, issue_slots[2].in_uop.bits.exception
connect slots_2.io.in_uop.bits.stale_pdst, issue_slots[2].in_uop.bits.stale_pdst
connect slots_2.io.in_uop.bits.ppred_busy, issue_slots[2].in_uop.bits.ppred_busy
connect slots_2.io.in_uop.bits.prs3_busy, issue_slots[2].in_uop.bits.prs3_busy
connect slots_2.io.in_uop.bits.prs2_busy, issue_slots[2].in_uop.bits.prs2_busy
connect slots_2.io.in_uop.bits.prs1_busy, issue_slots[2].in_uop.bits.prs1_busy
connect slots_2.io.in_uop.bits.ppred, issue_slots[2].in_uop.bits.ppred
connect slots_2.io.in_uop.bits.prs3, issue_slots[2].in_uop.bits.prs3
connect slots_2.io.in_uop.bits.prs2, issue_slots[2].in_uop.bits.prs2
connect slots_2.io.in_uop.bits.prs1, issue_slots[2].in_uop.bits.prs1
connect slots_2.io.in_uop.bits.pdst, issue_slots[2].in_uop.bits.pdst
connect slots_2.io.in_uop.bits.rxq_idx, issue_slots[2].in_uop.bits.rxq_idx
connect slots_2.io.in_uop.bits.stq_idx, issue_slots[2].in_uop.bits.stq_idx
connect slots_2.io.in_uop.bits.ldq_idx, issue_slots[2].in_uop.bits.ldq_idx
connect slots_2.io.in_uop.bits.rob_idx, issue_slots[2].in_uop.bits.rob_idx
connect slots_2.io.in_uop.bits.csr_addr, issue_slots[2].in_uop.bits.csr_addr
connect slots_2.io.in_uop.bits.imm_packed, issue_slots[2].in_uop.bits.imm_packed
connect slots_2.io.in_uop.bits.taken, issue_slots[2].in_uop.bits.taken
connect slots_2.io.in_uop.bits.pc_lob, issue_slots[2].in_uop.bits.pc_lob
connect slots_2.io.in_uop.bits.edge_inst, issue_slots[2].in_uop.bits.edge_inst
connect slots_2.io.in_uop.bits.ftq_idx, issue_slots[2].in_uop.bits.ftq_idx
connect slots_2.io.in_uop.bits.br_tag, issue_slots[2].in_uop.bits.br_tag
connect slots_2.io.in_uop.bits.br_mask, issue_slots[2].in_uop.bits.br_mask
connect slots_2.io.in_uop.bits.is_sfb, issue_slots[2].in_uop.bits.is_sfb
connect slots_2.io.in_uop.bits.is_jal, issue_slots[2].in_uop.bits.is_jal
connect slots_2.io.in_uop.bits.is_jalr, issue_slots[2].in_uop.bits.is_jalr
connect slots_2.io.in_uop.bits.is_br, issue_slots[2].in_uop.bits.is_br
connect slots_2.io.in_uop.bits.iw_p2_poisoned, issue_slots[2].in_uop.bits.iw_p2_poisoned
connect slots_2.io.in_uop.bits.iw_p1_poisoned, issue_slots[2].in_uop.bits.iw_p1_poisoned
connect slots_2.io.in_uop.bits.iw_state, issue_slots[2].in_uop.bits.iw_state
connect slots_2.io.in_uop.bits.ctrl.is_std, issue_slots[2].in_uop.bits.ctrl.is_std
connect slots_2.io.in_uop.bits.ctrl.is_sta, issue_slots[2].in_uop.bits.ctrl.is_sta
connect slots_2.io.in_uop.bits.ctrl.is_load, issue_slots[2].in_uop.bits.ctrl.is_load
connect slots_2.io.in_uop.bits.ctrl.csr_cmd, issue_slots[2].in_uop.bits.ctrl.csr_cmd
connect slots_2.io.in_uop.bits.ctrl.fcn_dw, issue_slots[2].in_uop.bits.ctrl.fcn_dw
connect slots_2.io.in_uop.bits.ctrl.op_fcn, issue_slots[2].in_uop.bits.ctrl.op_fcn
connect slots_2.io.in_uop.bits.ctrl.imm_sel, issue_slots[2].in_uop.bits.ctrl.imm_sel
connect slots_2.io.in_uop.bits.ctrl.op2_sel, issue_slots[2].in_uop.bits.ctrl.op2_sel
connect slots_2.io.in_uop.bits.ctrl.op1_sel, issue_slots[2].in_uop.bits.ctrl.op1_sel
connect slots_2.io.in_uop.bits.ctrl.br_type, issue_slots[2].in_uop.bits.ctrl.br_type
connect slots_2.io.in_uop.bits.fu_code, issue_slots[2].in_uop.bits.fu_code
connect slots_2.io.in_uop.bits.iq_type, issue_slots[2].in_uop.bits.iq_type
connect slots_2.io.in_uop.bits.debug_pc, issue_slots[2].in_uop.bits.debug_pc
connect slots_2.io.in_uop.bits.is_rvc, issue_slots[2].in_uop.bits.is_rvc
connect slots_2.io.in_uop.bits.debug_inst, issue_slots[2].in_uop.bits.debug_inst
connect slots_2.io.in_uop.bits.inst, issue_slots[2].in_uop.bits.inst
connect slots_2.io.in_uop.bits.uopc, issue_slots[2].in_uop.bits.uopc
connect slots_2.io.in_uop.valid, issue_slots[2].in_uop.valid
connect slots_2.io.spec_ld_wakeup[0].bits, issue_slots[2].spec_ld_wakeup[0].bits
connect slots_2.io.spec_ld_wakeup[0].valid, issue_slots[2].spec_ld_wakeup[0].valid
connect slots_2.io.pred_wakeup_port.bits, issue_slots[2].pred_wakeup_port.bits
connect slots_2.io.pred_wakeup_port.valid, issue_slots[2].pred_wakeup_port.valid
connect slots_2.io.wakeup_ports[0].bits.poisoned, issue_slots[2].wakeup_ports[0].bits.poisoned
connect slots_2.io.wakeup_ports[0].bits.pdst, issue_slots[2].wakeup_ports[0].bits.pdst
connect slots_2.io.wakeup_ports[0].valid, issue_slots[2].wakeup_ports[0].valid
connect slots_2.io.wakeup_ports[1].bits.poisoned, issue_slots[2].wakeup_ports[1].bits.poisoned
connect slots_2.io.wakeup_ports[1].bits.pdst, issue_slots[2].wakeup_ports[1].bits.pdst
connect slots_2.io.wakeup_ports[1].valid, issue_slots[2].wakeup_ports[1].valid
connect slots_2.io.wakeup_ports[2].bits.poisoned, issue_slots[2].wakeup_ports[2].bits.poisoned
connect slots_2.io.wakeup_ports[2].bits.pdst, issue_slots[2].wakeup_ports[2].bits.pdst
connect slots_2.io.wakeup_ports[2].valid, issue_slots[2].wakeup_ports[2].valid
connect slots_2.io.ldspec_miss, issue_slots[2].ldspec_miss
connect slots_2.io.clear, issue_slots[2].clear
connect slots_2.io.kill, issue_slots[2].kill
connect slots_2.io.brupdate.b2.target_offset, issue_slots[2].brupdate.b2.target_offset
connect slots_2.io.brupdate.b2.jalr_target, issue_slots[2].brupdate.b2.jalr_target
connect slots_2.io.brupdate.b2.pc_sel, issue_slots[2].brupdate.b2.pc_sel
connect slots_2.io.brupdate.b2.cfi_type, issue_slots[2].brupdate.b2.cfi_type
connect slots_2.io.brupdate.b2.taken, issue_slots[2].brupdate.b2.taken
connect slots_2.io.brupdate.b2.mispredict, issue_slots[2].brupdate.b2.mispredict
connect slots_2.io.brupdate.b2.valid, issue_slots[2].brupdate.b2.valid
connect slots_2.io.brupdate.b2.uop.debug_tsrc, issue_slots[2].brupdate.b2.uop.debug_tsrc
connect slots_2.io.brupdate.b2.uop.debug_fsrc, issue_slots[2].brupdate.b2.uop.debug_fsrc
connect slots_2.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[2].brupdate.b2.uop.bp_xcpt_if
connect slots_2.io.brupdate.b2.uop.bp_debug_if, issue_slots[2].brupdate.b2.uop.bp_debug_if
connect slots_2.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[2].brupdate.b2.uop.xcpt_ma_if
connect slots_2.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[2].brupdate.b2.uop.xcpt_ae_if
connect slots_2.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[2].brupdate.b2.uop.xcpt_pf_if
connect slots_2.io.brupdate.b2.uop.fp_single, issue_slots[2].brupdate.b2.uop.fp_single
connect slots_2.io.brupdate.b2.uop.fp_val, issue_slots[2].brupdate.b2.uop.fp_val
connect slots_2.io.brupdate.b2.uop.frs3_en, issue_slots[2].brupdate.b2.uop.frs3_en
connect slots_2.io.brupdate.b2.uop.lrs2_rtype, issue_slots[2].brupdate.b2.uop.lrs2_rtype
connect slots_2.io.brupdate.b2.uop.lrs1_rtype, issue_slots[2].brupdate.b2.uop.lrs1_rtype
connect slots_2.io.brupdate.b2.uop.dst_rtype, issue_slots[2].brupdate.b2.uop.dst_rtype
connect slots_2.io.brupdate.b2.uop.ldst_val, issue_slots[2].brupdate.b2.uop.ldst_val
connect slots_2.io.brupdate.b2.uop.lrs3, issue_slots[2].brupdate.b2.uop.lrs3
connect slots_2.io.brupdate.b2.uop.lrs2, issue_slots[2].brupdate.b2.uop.lrs2
connect slots_2.io.brupdate.b2.uop.lrs1, issue_slots[2].brupdate.b2.uop.lrs1
connect slots_2.io.brupdate.b2.uop.ldst, issue_slots[2].brupdate.b2.uop.ldst
connect slots_2.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[2].brupdate.b2.uop.ldst_is_rs1
connect slots_2.io.brupdate.b2.uop.flush_on_commit, issue_slots[2].brupdate.b2.uop.flush_on_commit
connect slots_2.io.brupdate.b2.uop.is_unique, issue_slots[2].brupdate.b2.uop.is_unique
connect slots_2.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[2].brupdate.b2.uop.is_sys_pc2epc
connect slots_2.io.brupdate.b2.uop.uses_stq, issue_slots[2].brupdate.b2.uop.uses_stq
connect slots_2.io.brupdate.b2.uop.uses_ldq, issue_slots[2].brupdate.b2.uop.uses_ldq
connect slots_2.io.brupdate.b2.uop.is_amo, issue_slots[2].brupdate.b2.uop.is_amo
connect slots_2.io.brupdate.b2.uop.is_fencei, issue_slots[2].brupdate.b2.uop.is_fencei
connect slots_2.io.brupdate.b2.uop.is_fence, issue_slots[2].brupdate.b2.uop.is_fence
connect slots_2.io.brupdate.b2.uop.mem_signed, issue_slots[2].brupdate.b2.uop.mem_signed
connect slots_2.io.brupdate.b2.uop.mem_size, issue_slots[2].brupdate.b2.uop.mem_size
connect slots_2.io.brupdate.b2.uop.mem_cmd, issue_slots[2].brupdate.b2.uop.mem_cmd
connect slots_2.io.brupdate.b2.uop.bypassable, issue_slots[2].brupdate.b2.uop.bypassable
connect slots_2.io.brupdate.b2.uop.exc_cause, issue_slots[2].brupdate.b2.uop.exc_cause
connect slots_2.io.brupdate.b2.uop.exception, issue_slots[2].brupdate.b2.uop.exception
connect slots_2.io.brupdate.b2.uop.stale_pdst, issue_slots[2].brupdate.b2.uop.stale_pdst
connect slots_2.io.brupdate.b2.uop.ppred_busy, issue_slots[2].brupdate.b2.uop.ppred_busy
connect slots_2.io.brupdate.b2.uop.prs3_busy, issue_slots[2].brupdate.b2.uop.prs3_busy
connect slots_2.io.brupdate.b2.uop.prs2_busy, issue_slots[2].brupdate.b2.uop.prs2_busy
connect slots_2.io.brupdate.b2.uop.prs1_busy, issue_slots[2].brupdate.b2.uop.prs1_busy
connect slots_2.io.brupdate.b2.uop.ppred, issue_slots[2].brupdate.b2.uop.ppred
connect slots_2.io.brupdate.b2.uop.prs3, issue_slots[2].brupdate.b2.uop.prs3
connect slots_2.io.brupdate.b2.uop.prs2, issue_slots[2].brupdate.b2.uop.prs2
connect slots_2.io.brupdate.b2.uop.prs1, issue_slots[2].brupdate.b2.uop.prs1
connect slots_2.io.brupdate.b2.uop.pdst, issue_slots[2].brupdate.b2.uop.pdst
connect slots_2.io.brupdate.b2.uop.rxq_idx, issue_slots[2].brupdate.b2.uop.rxq_idx
connect slots_2.io.brupdate.b2.uop.stq_idx, issue_slots[2].brupdate.b2.uop.stq_idx
connect slots_2.io.brupdate.b2.uop.ldq_idx, issue_slots[2].brupdate.b2.uop.ldq_idx
connect slots_2.io.brupdate.b2.uop.rob_idx, issue_slots[2].brupdate.b2.uop.rob_idx
connect slots_2.io.brupdate.b2.uop.csr_addr, issue_slots[2].brupdate.b2.uop.csr_addr
connect slots_2.io.brupdate.b2.uop.imm_packed, issue_slots[2].brupdate.b2.uop.imm_packed
connect slots_2.io.brupdate.b2.uop.taken, issue_slots[2].brupdate.b2.uop.taken
connect slots_2.io.brupdate.b2.uop.pc_lob, issue_slots[2].brupdate.b2.uop.pc_lob
connect slots_2.io.brupdate.b2.uop.edge_inst, issue_slots[2].brupdate.b2.uop.edge_inst
connect slots_2.io.brupdate.b2.uop.ftq_idx, issue_slots[2].brupdate.b2.uop.ftq_idx
connect slots_2.io.brupdate.b2.uop.br_tag, issue_slots[2].brupdate.b2.uop.br_tag
connect slots_2.io.brupdate.b2.uop.br_mask, issue_slots[2].brupdate.b2.uop.br_mask
connect slots_2.io.brupdate.b2.uop.is_sfb, issue_slots[2].brupdate.b2.uop.is_sfb
connect slots_2.io.brupdate.b2.uop.is_jal, issue_slots[2].brupdate.b2.uop.is_jal
connect slots_2.io.brupdate.b2.uop.is_jalr, issue_slots[2].brupdate.b2.uop.is_jalr
connect slots_2.io.brupdate.b2.uop.is_br, issue_slots[2].brupdate.b2.uop.is_br
connect slots_2.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[2].brupdate.b2.uop.iw_p2_poisoned
connect slots_2.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[2].brupdate.b2.uop.iw_p1_poisoned
connect slots_2.io.brupdate.b2.uop.iw_state, issue_slots[2].brupdate.b2.uop.iw_state
connect slots_2.io.brupdate.b2.uop.ctrl.is_std, issue_slots[2].brupdate.b2.uop.ctrl.is_std
connect slots_2.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[2].brupdate.b2.uop.ctrl.is_sta
connect slots_2.io.brupdate.b2.uop.ctrl.is_load, issue_slots[2].brupdate.b2.uop.ctrl.is_load
connect slots_2.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[2].brupdate.b2.uop.ctrl.csr_cmd
connect slots_2.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[2].brupdate.b2.uop.ctrl.fcn_dw
connect slots_2.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[2].brupdate.b2.uop.ctrl.op_fcn
connect slots_2.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[2].brupdate.b2.uop.ctrl.imm_sel
connect slots_2.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[2].brupdate.b2.uop.ctrl.op2_sel
connect slots_2.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[2].brupdate.b2.uop.ctrl.op1_sel
connect slots_2.io.brupdate.b2.uop.ctrl.br_type, issue_slots[2].brupdate.b2.uop.ctrl.br_type
connect slots_2.io.brupdate.b2.uop.fu_code, issue_slots[2].brupdate.b2.uop.fu_code
connect slots_2.io.brupdate.b2.uop.iq_type, issue_slots[2].brupdate.b2.uop.iq_type
connect slots_2.io.brupdate.b2.uop.debug_pc, issue_slots[2].brupdate.b2.uop.debug_pc
connect slots_2.io.brupdate.b2.uop.is_rvc, issue_slots[2].brupdate.b2.uop.is_rvc
connect slots_2.io.brupdate.b2.uop.debug_inst, issue_slots[2].brupdate.b2.uop.debug_inst
connect slots_2.io.brupdate.b2.uop.inst, issue_slots[2].brupdate.b2.uop.inst
connect slots_2.io.brupdate.b2.uop.uopc, issue_slots[2].brupdate.b2.uop.uopc
connect slots_2.io.brupdate.b1.mispredict_mask, issue_slots[2].brupdate.b1.mispredict_mask
connect slots_2.io.brupdate.b1.resolve_mask, issue_slots[2].brupdate.b1.resolve_mask
connect slots_2.io.grant, issue_slots[2].grant
connect issue_slots[2].request_hp, slots_2.io.request_hp
connect issue_slots[2].request, slots_2.io.request
connect issue_slots[2].will_be_valid, slots_2.io.will_be_valid
connect issue_slots[2].valid, slots_2.io.valid
connect issue_slots[3].debug.state, slots_3.io.debug.state
connect issue_slots[3].debug.ppred, slots_3.io.debug.ppred
connect issue_slots[3].debug.p3, slots_3.io.debug.p3
connect issue_slots[3].debug.p2, slots_3.io.debug.p2
connect issue_slots[3].debug.p1, slots_3.io.debug.p1
connect issue_slots[3].uop.debug_tsrc, slots_3.io.uop.debug_tsrc
connect issue_slots[3].uop.debug_fsrc, slots_3.io.uop.debug_fsrc
connect issue_slots[3].uop.bp_xcpt_if, slots_3.io.uop.bp_xcpt_if
connect issue_slots[3].uop.bp_debug_if, slots_3.io.uop.bp_debug_if
connect issue_slots[3].uop.xcpt_ma_if, slots_3.io.uop.xcpt_ma_if
connect issue_slots[3].uop.xcpt_ae_if, slots_3.io.uop.xcpt_ae_if
connect issue_slots[3].uop.xcpt_pf_if, slots_3.io.uop.xcpt_pf_if
connect issue_slots[3].uop.fp_single, slots_3.io.uop.fp_single
connect issue_slots[3].uop.fp_val, slots_3.io.uop.fp_val
connect issue_slots[3].uop.frs3_en, slots_3.io.uop.frs3_en
connect issue_slots[3].uop.lrs2_rtype, slots_3.io.uop.lrs2_rtype
connect issue_slots[3].uop.lrs1_rtype, slots_3.io.uop.lrs1_rtype
connect issue_slots[3].uop.dst_rtype, slots_3.io.uop.dst_rtype
connect issue_slots[3].uop.ldst_val, slots_3.io.uop.ldst_val
connect issue_slots[3].uop.lrs3, slots_3.io.uop.lrs3
connect issue_slots[3].uop.lrs2, slots_3.io.uop.lrs2
connect issue_slots[3].uop.lrs1, slots_3.io.uop.lrs1
connect issue_slots[3].uop.ldst, slots_3.io.uop.ldst
connect issue_slots[3].uop.ldst_is_rs1, slots_3.io.uop.ldst_is_rs1
connect issue_slots[3].uop.flush_on_commit, slots_3.io.uop.flush_on_commit
connect issue_slots[3].uop.is_unique, slots_3.io.uop.is_unique
connect issue_slots[3].uop.is_sys_pc2epc, slots_3.io.uop.is_sys_pc2epc
connect issue_slots[3].uop.uses_stq, slots_3.io.uop.uses_stq
connect issue_slots[3].uop.uses_ldq, slots_3.io.uop.uses_ldq
connect issue_slots[3].uop.is_amo, slots_3.io.uop.is_amo
connect issue_slots[3].uop.is_fencei, slots_3.io.uop.is_fencei
connect issue_slots[3].uop.is_fence, slots_3.io.uop.is_fence
connect issue_slots[3].uop.mem_signed, slots_3.io.uop.mem_signed
connect issue_slots[3].uop.mem_size, slots_3.io.uop.mem_size
connect issue_slots[3].uop.mem_cmd, slots_3.io.uop.mem_cmd
connect issue_slots[3].uop.bypassable, slots_3.io.uop.bypassable
connect issue_slots[3].uop.exc_cause, slots_3.io.uop.exc_cause
connect issue_slots[3].uop.exception, slots_3.io.uop.exception
connect issue_slots[3].uop.stale_pdst, slots_3.io.uop.stale_pdst
connect issue_slots[3].uop.ppred_busy, slots_3.io.uop.ppred_busy
connect issue_slots[3].uop.prs3_busy, slots_3.io.uop.prs3_busy
connect issue_slots[3].uop.prs2_busy, slots_3.io.uop.prs2_busy
connect issue_slots[3].uop.prs1_busy, slots_3.io.uop.prs1_busy
connect issue_slots[3].uop.ppred, slots_3.io.uop.ppred
connect issue_slots[3].uop.prs3, slots_3.io.uop.prs3
connect issue_slots[3].uop.prs2, slots_3.io.uop.prs2
connect issue_slots[3].uop.prs1, slots_3.io.uop.prs1
connect issue_slots[3].uop.pdst, slots_3.io.uop.pdst
connect issue_slots[3].uop.rxq_idx, slots_3.io.uop.rxq_idx
connect issue_slots[3].uop.stq_idx, slots_3.io.uop.stq_idx
connect issue_slots[3].uop.ldq_idx, slots_3.io.uop.ldq_idx
connect issue_slots[3].uop.rob_idx, slots_3.io.uop.rob_idx
connect issue_slots[3].uop.csr_addr, slots_3.io.uop.csr_addr
connect issue_slots[3].uop.imm_packed, slots_3.io.uop.imm_packed
connect issue_slots[3].uop.taken, slots_3.io.uop.taken
connect issue_slots[3].uop.pc_lob, slots_3.io.uop.pc_lob
connect issue_slots[3].uop.edge_inst, slots_3.io.uop.edge_inst
connect issue_slots[3].uop.ftq_idx, slots_3.io.uop.ftq_idx
connect issue_slots[3].uop.br_tag, slots_3.io.uop.br_tag
connect issue_slots[3].uop.br_mask, slots_3.io.uop.br_mask
connect issue_slots[3].uop.is_sfb, slots_3.io.uop.is_sfb
connect issue_slots[3].uop.is_jal, slots_3.io.uop.is_jal
connect issue_slots[3].uop.is_jalr, slots_3.io.uop.is_jalr
connect issue_slots[3].uop.is_br, slots_3.io.uop.is_br
connect issue_slots[3].uop.iw_p2_poisoned, slots_3.io.uop.iw_p2_poisoned
connect issue_slots[3].uop.iw_p1_poisoned, slots_3.io.uop.iw_p1_poisoned
connect issue_slots[3].uop.iw_state, slots_3.io.uop.iw_state
connect issue_slots[3].uop.ctrl.is_std, slots_3.io.uop.ctrl.is_std
connect issue_slots[3].uop.ctrl.is_sta, slots_3.io.uop.ctrl.is_sta
connect issue_slots[3].uop.ctrl.is_load, slots_3.io.uop.ctrl.is_load
connect issue_slots[3].uop.ctrl.csr_cmd, slots_3.io.uop.ctrl.csr_cmd
connect issue_slots[3].uop.ctrl.fcn_dw, slots_3.io.uop.ctrl.fcn_dw
connect issue_slots[3].uop.ctrl.op_fcn, slots_3.io.uop.ctrl.op_fcn
connect issue_slots[3].uop.ctrl.imm_sel, slots_3.io.uop.ctrl.imm_sel
connect issue_slots[3].uop.ctrl.op2_sel, slots_3.io.uop.ctrl.op2_sel
connect issue_slots[3].uop.ctrl.op1_sel, slots_3.io.uop.ctrl.op1_sel
connect issue_slots[3].uop.ctrl.br_type, slots_3.io.uop.ctrl.br_type
connect issue_slots[3].uop.fu_code, slots_3.io.uop.fu_code
connect issue_slots[3].uop.iq_type, slots_3.io.uop.iq_type
connect issue_slots[3].uop.debug_pc, slots_3.io.uop.debug_pc
connect issue_slots[3].uop.is_rvc, slots_3.io.uop.is_rvc
connect issue_slots[3].uop.debug_inst, slots_3.io.uop.debug_inst
connect issue_slots[3].uop.inst, slots_3.io.uop.inst
connect issue_slots[3].uop.uopc, slots_3.io.uop.uopc
connect issue_slots[3].out_uop.debug_tsrc, slots_3.io.out_uop.debug_tsrc
connect issue_slots[3].out_uop.debug_fsrc, slots_3.io.out_uop.debug_fsrc
connect issue_slots[3].out_uop.bp_xcpt_if, slots_3.io.out_uop.bp_xcpt_if
connect issue_slots[3].out_uop.bp_debug_if, slots_3.io.out_uop.bp_debug_if
connect issue_slots[3].out_uop.xcpt_ma_if, slots_3.io.out_uop.xcpt_ma_if
connect issue_slots[3].out_uop.xcpt_ae_if, slots_3.io.out_uop.xcpt_ae_if
connect issue_slots[3].out_uop.xcpt_pf_if, slots_3.io.out_uop.xcpt_pf_if
connect issue_slots[3].out_uop.fp_single, slots_3.io.out_uop.fp_single
connect issue_slots[3].out_uop.fp_val, slots_3.io.out_uop.fp_val
connect issue_slots[3].out_uop.frs3_en, slots_3.io.out_uop.frs3_en
connect issue_slots[3].out_uop.lrs2_rtype, slots_3.io.out_uop.lrs2_rtype
connect issue_slots[3].out_uop.lrs1_rtype, slots_3.io.out_uop.lrs1_rtype
connect issue_slots[3].out_uop.dst_rtype, slots_3.io.out_uop.dst_rtype
connect issue_slots[3].out_uop.ldst_val, slots_3.io.out_uop.ldst_val
connect issue_slots[3].out_uop.lrs3, slots_3.io.out_uop.lrs3
connect issue_slots[3].out_uop.lrs2, slots_3.io.out_uop.lrs2
connect issue_slots[3].out_uop.lrs1, slots_3.io.out_uop.lrs1
connect issue_slots[3].out_uop.ldst, slots_3.io.out_uop.ldst
connect issue_slots[3].out_uop.ldst_is_rs1, slots_3.io.out_uop.ldst_is_rs1
connect issue_slots[3].out_uop.flush_on_commit, slots_3.io.out_uop.flush_on_commit
connect issue_slots[3].out_uop.is_unique, slots_3.io.out_uop.is_unique
connect issue_slots[3].out_uop.is_sys_pc2epc, slots_3.io.out_uop.is_sys_pc2epc
connect issue_slots[3].out_uop.uses_stq, slots_3.io.out_uop.uses_stq
connect issue_slots[3].out_uop.uses_ldq, slots_3.io.out_uop.uses_ldq
connect issue_slots[3].out_uop.is_amo, slots_3.io.out_uop.is_amo
connect issue_slots[3].out_uop.is_fencei, slots_3.io.out_uop.is_fencei
connect issue_slots[3].out_uop.is_fence, slots_3.io.out_uop.is_fence
connect issue_slots[3].out_uop.mem_signed, slots_3.io.out_uop.mem_signed
connect issue_slots[3].out_uop.mem_size, slots_3.io.out_uop.mem_size
connect issue_slots[3].out_uop.mem_cmd, slots_3.io.out_uop.mem_cmd
connect issue_slots[3].out_uop.bypassable, slots_3.io.out_uop.bypassable
connect issue_slots[3].out_uop.exc_cause, slots_3.io.out_uop.exc_cause
connect issue_slots[3].out_uop.exception, slots_3.io.out_uop.exception
connect issue_slots[3].out_uop.stale_pdst, slots_3.io.out_uop.stale_pdst
connect issue_slots[3].out_uop.ppred_busy, slots_3.io.out_uop.ppred_busy
connect issue_slots[3].out_uop.prs3_busy, slots_3.io.out_uop.prs3_busy
connect issue_slots[3].out_uop.prs2_busy, slots_3.io.out_uop.prs2_busy
connect issue_slots[3].out_uop.prs1_busy, slots_3.io.out_uop.prs1_busy
connect issue_slots[3].out_uop.ppred, slots_3.io.out_uop.ppred
connect issue_slots[3].out_uop.prs3, slots_3.io.out_uop.prs3
connect issue_slots[3].out_uop.prs2, slots_3.io.out_uop.prs2
connect issue_slots[3].out_uop.prs1, slots_3.io.out_uop.prs1
connect issue_slots[3].out_uop.pdst, slots_3.io.out_uop.pdst
connect issue_slots[3].out_uop.rxq_idx, slots_3.io.out_uop.rxq_idx
connect issue_slots[3].out_uop.stq_idx, slots_3.io.out_uop.stq_idx
connect issue_slots[3].out_uop.ldq_idx, slots_3.io.out_uop.ldq_idx
connect issue_slots[3].out_uop.rob_idx, slots_3.io.out_uop.rob_idx
connect issue_slots[3].out_uop.csr_addr, slots_3.io.out_uop.csr_addr
connect issue_slots[3].out_uop.imm_packed, slots_3.io.out_uop.imm_packed
connect issue_slots[3].out_uop.taken, slots_3.io.out_uop.taken
connect issue_slots[3].out_uop.pc_lob, slots_3.io.out_uop.pc_lob
connect issue_slots[3].out_uop.edge_inst, slots_3.io.out_uop.edge_inst
connect issue_slots[3].out_uop.ftq_idx, slots_3.io.out_uop.ftq_idx
connect issue_slots[3].out_uop.br_tag, slots_3.io.out_uop.br_tag
connect issue_slots[3].out_uop.br_mask, slots_3.io.out_uop.br_mask
connect issue_slots[3].out_uop.is_sfb, slots_3.io.out_uop.is_sfb
connect issue_slots[3].out_uop.is_jal, slots_3.io.out_uop.is_jal
connect issue_slots[3].out_uop.is_jalr, slots_3.io.out_uop.is_jalr
connect issue_slots[3].out_uop.is_br, slots_3.io.out_uop.is_br
connect issue_slots[3].out_uop.iw_p2_poisoned, slots_3.io.out_uop.iw_p2_poisoned
connect issue_slots[3].out_uop.iw_p1_poisoned, slots_3.io.out_uop.iw_p1_poisoned
connect issue_slots[3].out_uop.iw_state, slots_3.io.out_uop.iw_state
connect issue_slots[3].out_uop.ctrl.is_std, slots_3.io.out_uop.ctrl.is_std
connect issue_slots[3].out_uop.ctrl.is_sta, slots_3.io.out_uop.ctrl.is_sta
connect issue_slots[3].out_uop.ctrl.is_load, slots_3.io.out_uop.ctrl.is_load
connect issue_slots[3].out_uop.ctrl.csr_cmd, slots_3.io.out_uop.ctrl.csr_cmd
connect issue_slots[3].out_uop.ctrl.fcn_dw, slots_3.io.out_uop.ctrl.fcn_dw
connect issue_slots[3].out_uop.ctrl.op_fcn, slots_3.io.out_uop.ctrl.op_fcn
connect issue_slots[3].out_uop.ctrl.imm_sel, slots_3.io.out_uop.ctrl.imm_sel
connect issue_slots[3].out_uop.ctrl.op2_sel, slots_3.io.out_uop.ctrl.op2_sel
connect issue_slots[3].out_uop.ctrl.op1_sel, slots_3.io.out_uop.ctrl.op1_sel
connect issue_slots[3].out_uop.ctrl.br_type, slots_3.io.out_uop.ctrl.br_type
connect issue_slots[3].out_uop.fu_code, slots_3.io.out_uop.fu_code
connect issue_slots[3].out_uop.iq_type, slots_3.io.out_uop.iq_type
connect issue_slots[3].out_uop.debug_pc, slots_3.io.out_uop.debug_pc
connect issue_slots[3].out_uop.is_rvc, slots_3.io.out_uop.is_rvc
connect issue_slots[3].out_uop.debug_inst, slots_3.io.out_uop.debug_inst
connect issue_slots[3].out_uop.inst, slots_3.io.out_uop.inst
connect issue_slots[3].out_uop.uopc, slots_3.io.out_uop.uopc
connect slots_3.io.in_uop.bits.debug_tsrc, issue_slots[3].in_uop.bits.debug_tsrc
connect slots_3.io.in_uop.bits.debug_fsrc, issue_slots[3].in_uop.bits.debug_fsrc
connect slots_3.io.in_uop.bits.bp_xcpt_if, issue_slots[3].in_uop.bits.bp_xcpt_if
connect slots_3.io.in_uop.bits.bp_debug_if, issue_slots[3].in_uop.bits.bp_debug_if
connect slots_3.io.in_uop.bits.xcpt_ma_if, issue_slots[3].in_uop.bits.xcpt_ma_if
connect slots_3.io.in_uop.bits.xcpt_ae_if, issue_slots[3].in_uop.bits.xcpt_ae_if
connect slots_3.io.in_uop.bits.xcpt_pf_if, issue_slots[3].in_uop.bits.xcpt_pf_if
connect slots_3.io.in_uop.bits.fp_single, issue_slots[3].in_uop.bits.fp_single
connect slots_3.io.in_uop.bits.fp_val, issue_slots[3].in_uop.bits.fp_val
connect slots_3.io.in_uop.bits.frs3_en, issue_slots[3].in_uop.bits.frs3_en
connect slots_3.io.in_uop.bits.lrs2_rtype, issue_slots[3].in_uop.bits.lrs2_rtype
connect slots_3.io.in_uop.bits.lrs1_rtype, issue_slots[3].in_uop.bits.lrs1_rtype
connect slots_3.io.in_uop.bits.dst_rtype, issue_slots[3].in_uop.bits.dst_rtype
connect slots_3.io.in_uop.bits.ldst_val, issue_slots[3].in_uop.bits.ldst_val
connect slots_3.io.in_uop.bits.lrs3, issue_slots[3].in_uop.bits.lrs3
connect slots_3.io.in_uop.bits.lrs2, issue_slots[3].in_uop.bits.lrs2
connect slots_3.io.in_uop.bits.lrs1, issue_slots[3].in_uop.bits.lrs1
connect slots_3.io.in_uop.bits.ldst, issue_slots[3].in_uop.bits.ldst
connect slots_3.io.in_uop.bits.ldst_is_rs1, issue_slots[3].in_uop.bits.ldst_is_rs1
connect slots_3.io.in_uop.bits.flush_on_commit, issue_slots[3].in_uop.bits.flush_on_commit
connect slots_3.io.in_uop.bits.is_unique, issue_slots[3].in_uop.bits.is_unique
connect slots_3.io.in_uop.bits.is_sys_pc2epc, issue_slots[3].in_uop.bits.is_sys_pc2epc
connect slots_3.io.in_uop.bits.uses_stq, issue_slots[3].in_uop.bits.uses_stq
connect slots_3.io.in_uop.bits.uses_ldq, issue_slots[3].in_uop.bits.uses_ldq
connect slots_3.io.in_uop.bits.is_amo, issue_slots[3].in_uop.bits.is_amo
connect slots_3.io.in_uop.bits.is_fencei, issue_slots[3].in_uop.bits.is_fencei
connect slots_3.io.in_uop.bits.is_fence, issue_slots[3].in_uop.bits.is_fence
connect slots_3.io.in_uop.bits.mem_signed, issue_slots[3].in_uop.bits.mem_signed
connect slots_3.io.in_uop.bits.mem_size, issue_slots[3].in_uop.bits.mem_size
connect slots_3.io.in_uop.bits.mem_cmd, issue_slots[3].in_uop.bits.mem_cmd
connect slots_3.io.in_uop.bits.bypassable, issue_slots[3].in_uop.bits.bypassable
connect slots_3.io.in_uop.bits.exc_cause, issue_slots[3].in_uop.bits.exc_cause
connect slots_3.io.in_uop.bits.exception, issue_slots[3].in_uop.bits.exception
connect slots_3.io.in_uop.bits.stale_pdst, issue_slots[3].in_uop.bits.stale_pdst
connect slots_3.io.in_uop.bits.ppred_busy, issue_slots[3].in_uop.bits.ppred_busy
connect slots_3.io.in_uop.bits.prs3_busy, issue_slots[3].in_uop.bits.prs3_busy
connect slots_3.io.in_uop.bits.prs2_busy, issue_slots[3].in_uop.bits.prs2_busy
connect slots_3.io.in_uop.bits.prs1_busy, issue_slots[3].in_uop.bits.prs1_busy
connect slots_3.io.in_uop.bits.ppred, issue_slots[3].in_uop.bits.ppred
connect slots_3.io.in_uop.bits.prs3, issue_slots[3].in_uop.bits.prs3
connect slots_3.io.in_uop.bits.prs2, issue_slots[3].in_uop.bits.prs2
connect slots_3.io.in_uop.bits.prs1, issue_slots[3].in_uop.bits.prs1
connect slots_3.io.in_uop.bits.pdst, issue_slots[3].in_uop.bits.pdst
connect slots_3.io.in_uop.bits.rxq_idx, issue_slots[3].in_uop.bits.rxq_idx
connect slots_3.io.in_uop.bits.stq_idx, issue_slots[3].in_uop.bits.stq_idx
connect slots_3.io.in_uop.bits.ldq_idx, issue_slots[3].in_uop.bits.ldq_idx
connect slots_3.io.in_uop.bits.rob_idx, issue_slots[3].in_uop.bits.rob_idx
connect slots_3.io.in_uop.bits.csr_addr, issue_slots[3].in_uop.bits.csr_addr
connect slots_3.io.in_uop.bits.imm_packed, issue_slots[3].in_uop.bits.imm_packed
connect slots_3.io.in_uop.bits.taken, issue_slots[3].in_uop.bits.taken
connect slots_3.io.in_uop.bits.pc_lob, issue_slots[3].in_uop.bits.pc_lob
connect slots_3.io.in_uop.bits.edge_inst, issue_slots[3].in_uop.bits.edge_inst
connect slots_3.io.in_uop.bits.ftq_idx, issue_slots[3].in_uop.bits.ftq_idx
connect slots_3.io.in_uop.bits.br_tag, issue_slots[3].in_uop.bits.br_tag
connect slots_3.io.in_uop.bits.br_mask, issue_slots[3].in_uop.bits.br_mask
connect slots_3.io.in_uop.bits.is_sfb, issue_slots[3].in_uop.bits.is_sfb
connect slots_3.io.in_uop.bits.is_jal, issue_slots[3].in_uop.bits.is_jal
connect slots_3.io.in_uop.bits.is_jalr, issue_slots[3].in_uop.bits.is_jalr
connect slots_3.io.in_uop.bits.is_br, issue_slots[3].in_uop.bits.is_br
connect slots_3.io.in_uop.bits.iw_p2_poisoned, issue_slots[3].in_uop.bits.iw_p2_poisoned
connect slots_3.io.in_uop.bits.iw_p1_poisoned, issue_slots[3].in_uop.bits.iw_p1_poisoned
connect slots_3.io.in_uop.bits.iw_state, issue_slots[3].in_uop.bits.iw_state
connect slots_3.io.in_uop.bits.ctrl.is_std, issue_slots[3].in_uop.bits.ctrl.is_std
connect slots_3.io.in_uop.bits.ctrl.is_sta, issue_slots[3].in_uop.bits.ctrl.is_sta
connect slots_3.io.in_uop.bits.ctrl.is_load, issue_slots[3].in_uop.bits.ctrl.is_load
connect slots_3.io.in_uop.bits.ctrl.csr_cmd, issue_slots[3].in_uop.bits.ctrl.csr_cmd
connect slots_3.io.in_uop.bits.ctrl.fcn_dw, issue_slots[3].in_uop.bits.ctrl.fcn_dw
connect slots_3.io.in_uop.bits.ctrl.op_fcn, issue_slots[3].in_uop.bits.ctrl.op_fcn
connect slots_3.io.in_uop.bits.ctrl.imm_sel, issue_slots[3].in_uop.bits.ctrl.imm_sel
connect slots_3.io.in_uop.bits.ctrl.op2_sel, issue_slots[3].in_uop.bits.ctrl.op2_sel
connect slots_3.io.in_uop.bits.ctrl.op1_sel, issue_slots[3].in_uop.bits.ctrl.op1_sel
connect slots_3.io.in_uop.bits.ctrl.br_type, issue_slots[3].in_uop.bits.ctrl.br_type
connect slots_3.io.in_uop.bits.fu_code, issue_slots[3].in_uop.bits.fu_code
connect slots_3.io.in_uop.bits.iq_type, issue_slots[3].in_uop.bits.iq_type
connect slots_3.io.in_uop.bits.debug_pc, issue_slots[3].in_uop.bits.debug_pc
connect slots_3.io.in_uop.bits.is_rvc, issue_slots[3].in_uop.bits.is_rvc
connect slots_3.io.in_uop.bits.debug_inst, issue_slots[3].in_uop.bits.debug_inst
connect slots_3.io.in_uop.bits.inst, issue_slots[3].in_uop.bits.inst
connect slots_3.io.in_uop.bits.uopc, issue_slots[3].in_uop.bits.uopc
connect slots_3.io.in_uop.valid, issue_slots[3].in_uop.valid
connect slots_3.io.spec_ld_wakeup[0].bits, issue_slots[3].spec_ld_wakeup[0].bits
connect slots_3.io.spec_ld_wakeup[0].valid, issue_slots[3].spec_ld_wakeup[0].valid
connect slots_3.io.pred_wakeup_port.bits, issue_slots[3].pred_wakeup_port.bits
connect slots_3.io.pred_wakeup_port.valid, issue_slots[3].pred_wakeup_port.valid
connect slots_3.io.wakeup_ports[0].bits.poisoned, issue_slots[3].wakeup_ports[0].bits.poisoned
connect slots_3.io.wakeup_ports[0].bits.pdst, issue_slots[3].wakeup_ports[0].bits.pdst
connect slots_3.io.wakeup_ports[0].valid, issue_slots[3].wakeup_ports[0].valid
connect slots_3.io.wakeup_ports[1].bits.poisoned, issue_slots[3].wakeup_ports[1].bits.poisoned
connect slots_3.io.wakeup_ports[1].bits.pdst, issue_slots[3].wakeup_ports[1].bits.pdst
connect slots_3.io.wakeup_ports[1].valid, issue_slots[3].wakeup_ports[1].valid
connect slots_3.io.wakeup_ports[2].bits.poisoned, issue_slots[3].wakeup_ports[2].bits.poisoned
connect slots_3.io.wakeup_ports[2].bits.pdst, issue_slots[3].wakeup_ports[2].bits.pdst
connect slots_3.io.wakeup_ports[2].valid, issue_slots[3].wakeup_ports[2].valid
connect slots_3.io.ldspec_miss, issue_slots[3].ldspec_miss
connect slots_3.io.clear, issue_slots[3].clear
connect slots_3.io.kill, issue_slots[3].kill
connect slots_3.io.brupdate.b2.target_offset, issue_slots[3].brupdate.b2.target_offset
connect slots_3.io.brupdate.b2.jalr_target, issue_slots[3].brupdate.b2.jalr_target
connect slots_3.io.brupdate.b2.pc_sel, issue_slots[3].brupdate.b2.pc_sel
connect slots_3.io.brupdate.b2.cfi_type, issue_slots[3].brupdate.b2.cfi_type
connect slots_3.io.brupdate.b2.taken, issue_slots[3].brupdate.b2.taken
connect slots_3.io.brupdate.b2.mispredict, issue_slots[3].brupdate.b2.mispredict
connect slots_3.io.brupdate.b2.valid, issue_slots[3].brupdate.b2.valid
connect slots_3.io.brupdate.b2.uop.debug_tsrc, issue_slots[3].brupdate.b2.uop.debug_tsrc
connect slots_3.io.brupdate.b2.uop.debug_fsrc, issue_slots[3].brupdate.b2.uop.debug_fsrc
connect slots_3.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[3].brupdate.b2.uop.bp_xcpt_if
connect slots_3.io.brupdate.b2.uop.bp_debug_if, issue_slots[3].brupdate.b2.uop.bp_debug_if
connect slots_3.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[3].brupdate.b2.uop.xcpt_ma_if
connect slots_3.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[3].brupdate.b2.uop.xcpt_ae_if
connect slots_3.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[3].brupdate.b2.uop.xcpt_pf_if
connect slots_3.io.brupdate.b2.uop.fp_single, issue_slots[3].brupdate.b2.uop.fp_single
connect slots_3.io.brupdate.b2.uop.fp_val, issue_slots[3].brupdate.b2.uop.fp_val
connect slots_3.io.brupdate.b2.uop.frs3_en, issue_slots[3].brupdate.b2.uop.frs3_en
connect slots_3.io.brupdate.b2.uop.lrs2_rtype, issue_slots[3].brupdate.b2.uop.lrs2_rtype
connect slots_3.io.brupdate.b2.uop.lrs1_rtype, issue_slots[3].brupdate.b2.uop.lrs1_rtype
connect slots_3.io.brupdate.b2.uop.dst_rtype, issue_slots[3].brupdate.b2.uop.dst_rtype
connect slots_3.io.brupdate.b2.uop.ldst_val, issue_slots[3].brupdate.b2.uop.ldst_val
connect slots_3.io.brupdate.b2.uop.lrs3, issue_slots[3].brupdate.b2.uop.lrs3
connect slots_3.io.brupdate.b2.uop.lrs2, issue_slots[3].brupdate.b2.uop.lrs2
connect slots_3.io.brupdate.b2.uop.lrs1, issue_slots[3].brupdate.b2.uop.lrs1
connect slots_3.io.brupdate.b2.uop.ldst, issue_slots[3].brupdate.b2.uop.ldst
connect slots_3.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[3].brupdate.b2.uop.ldst_is_rs1
connect slots_3.io.brupdate.b2.uop.flush_on_commit, issue_slots[3].brupdate.b2.uop.flush_on_commit
connect slots_3.io.brupdate.b2.uop.is_unique, issue_slots[3].brupdate.b2.uop.is_unique
connect slots_3.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[3].brupdate.b2.uop.is_sys_pc2epc
connect slots_3.io.brupdate.b2.uop.uses_stq, issue_slots[3].brupdate.b2.uop.uses_stq
connect slots_3.io.brupdate.b2.uop.uses_ldq, issue_slots[3].brupdate.b2.uop.uses_ldq
connect slots_3.io.brupdate.b2.uop.is_amo, issue_slots[3].brupdate.b2.uop.is_amo
connect slots_3.io.brupdate.b2.uop.is_fencei, issue_slots[3].brupdate.b2.uop.is_fencei
connect slots_3.io.brupdate.b2.uop.is_fence, issue_slots[3].brupdate.b2.uop.is_fence
connect slots_3.io.brupdate.b2.uop.mem_signed, issue_slots[3].brupdate.b2.uop.mem_signed
connect slots_3.io.brupdate.b2.uop.mem_size, issue_slots[3].brupdate.b2.uop.mem_size
connect slots_3.io.brupdate.b2.uop.mem_cmd, issue_slots[3].brupdate.b2.uop.mem_cmd
connect slots_3.io.brupdate.b2.uop.bypassable, issue_slots[3].brupdate.b2.uop.bypassable
connect slots_3.io.brupdate.b2.uop.exc_cause, issue_slots[3].brupdate.b2.uop.exc_cause
connect slots_3.io.brupdate.b2.uop.exception, issue_slots[3].brupdate.b2.uop.exception
connect slots_3.io.brupdate.b2.uop.stale_pdst, issue_slots[3].brupdate.b2.uop.stale_pdst
connect slots_3.io.brupdate.b2.uop.ppred_busy, issue_slots[3].brupdate.b2.uop.ppred_busy
connect slots_3.io.brupdate.b2.uop.prs3_busy, issue_slots[3].brupdate.b2.uop.prs3_busy
connect slots_3.io.brupdate.b2.uop.prs2_busy, issue_slots[3].brupdate.b2.uop.prs2_busy
connect slots_3.io.brupdate.b2.uop.prs1_busy, issue_slots[3].brupdate.b2.uop.prs1_busy
connect slots_3.io.brupdate.b2.uop.ppred, issue_slots[3].brupdate.b2.uop.ppred
connect slots_3.io.brupdate.b2.uop.prs3, issue_slots[3].brupdate.b2.uop.prs3
connect slots_3.io.brupdate.b2.uop.prs2, issue_slots[3].brupdate.b2.uop.prs2
connect slots_3.io.brupdate.b2.uop.prs1, issue_slots[3].brupdate.b2.uop.prs1
connect slots_3.io.brupdate.b2.uop.pdst, issue_slots[3].brupdate.b2.uop.pdst
connect slots_3.io.brupdate.b2.uop.rxq_idx, issue_slots[3].brupdate.b2.uop.rxq_idx
connect slots_3.io.brupdate.b2.uop.stq_idx, issue_slots[3].brupdate.b2.uop.stq_idx
connect slots_3.io.brupdate.b2.uop.ldq_idx, issue_slots[3].brupdate.b2.uop.ldq_idx
connect slots_3.io.brupdate.b2.uop.rob_idx, issue_slots[3].brupdate.b2.uop.rob_idx
connect slots_3.io.brupdate.b2.uop.csr_addr, issue_slots[3].brupdate.b2.uop.csr_addr
connect slots_3.io.brupdate.b2.uop.imm_packed, issue_slots[3].brupdate.b2.uop.imm_packed
connect slots_3.io.brupdate.b2.uop.taken, issue_slots[3].brupdate.b2.uop.taken
connect slots_3.io.brupdate.b2.uop.pc_lob, issue_slots[3].brupdate.b2.uop.pc_lob
connect slots_3.io.brupdate.b2.uop.edge_inst, issue_slots[3].brupdate.b2.uop.edge_inst
connect slots_3.io.brupdate.b2.uop.ftq_idx, issue_slots[3].brupdate.b2.uop.ftq_idx
connect slots_3.io.brupdate.b2.uop.br_tag, issue_slots[3].brupdate.b2.uop.br_tag
connect slots_3.io.brupdate.b2.uop.br_mask, issue_slots[3].brupdate.b2.uop.br_mask
connect slots_3.io.brupdate.b2.uop.is_sfb, issue_slots[3].brupdate.b2.uop.is_sfb
connect slots_3.io.brupdate.b2.uop.is_jal, issue_slots[3].brupdate.b2.uop.is_jal
connect slots_3.io.brupdate.b2.uop.is_jalr, issue_slots[3].brupdate.b2.uop.is_jalr
connect slots_3.io.brupdate.b2.uop.is_br, issue_slots[3].brupdate.b2.uop.is_br
connect slots_3.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[3].brupdate.b2.uop.iw_p2_poisoned
connect slots_3.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[3].brupdate.b2.uop.iw_p1_poisoned
connect slots_3.io.brupdate.b2.uop.iw_state, issue_slots[3].brupdate.b2.uop.iw_state
connect slots_3.io.brupdate.b2.uop.ctrl.is_std, issue_slots[3].brupdate.b2.uop.ctrl.is_std
connect slots_3.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[3].brupdate.b2.uop.ctrl.is_sta
connect slots_3.io.brupdate.b2.uop.ctrl.is_load, issue_slots[3].brupdate.b2.uop.ctrl.is_load
connect slots_3.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[3].brupdate.b2.uop.ctrl.csr_cmd
connect slots_3.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[3].brupdate.b2.uop.ctrl.fcn_dw
connect slots_3.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[3].brupdate.b2.uop.ctrl.op_fcn
connect slots_3.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[3].brupdate.b2.uop.ctrl.imm_sel
connect slots_3.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[3].brupdate.b2.uop.ctrl.op2_sel
connect slots_3.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[3].brupdate.b2.uop.ctrl.op1_sel
connect slots_3.io.brupdate.b2.uop.ctrl.br_type, issue_slots[3].brupdate.b2.uop.ctrl.br_type
connect slots_3.io.brupdate.b2.uop.fu_code, issue_slots[3].brupdate.b2.uop.fu_code
connect slots_3.io.brupdate.b2.uop.iq_type, issue_slots[3].brupdate.b2.uop.iq_type
connect slots_3.io.brupdate.b2.uop.debug_pc, issue_slots[3].brupdate.b2.uop.debug_pc
connect slots_3.io.brupdate.b2.uop.is_rvc, issue_slots[3].brupdate.b2.uop.is_rvc
connect slots_3.io.brupdate.b2.uop.debug_inst, issue_slots[3].brupdate.b2.uop.debug_inst
connect slots_3.io.brupdate.b2.uop.inst, issue_slots[3].brupdate.b2.uop.inst
connect slots_3.io.brupdate.b2.uop.uopc, issue_slots[3].brupdate.b2.uop.uopc
connect slots_3.io.brupdate.b1.mispredict_mask, issue_slots[3].brupdate.b1.mispredict_mask
connect slots_3.io.brupdate.b1.resolve_mask, issue_slots[3].brupdate.b1.resolve_mask
connect slots_3.io.grant, issue_slots[3].grant
connect issue_slots[3].request_hp, slots_3.io.request_hp
connect issue_slots[3].request, slots_3.io.request
connect issue_slots[3].will_be_valid, slots_3.io.will_be_valid
connect issue_slots[3].valid, slots_3.io.valid
connect issue_slots[4].debug.state, slots_4.io.debug.state
connect issue_slots[4].debug.ppred, slots_4.io.debug.ppred
connect issue_slots[4].debug.p3, slots_4.io.debug.p3
connect issue_slots[4].debug.p2, slots_4.io.debug.p2
connect issue_slots[4].debug.p1, slots_4.io.debug.p1
connect issue_slots[4].uop.debug_tsrc, slots_4.io.uop.debug_tsrc
connect issue_slots[4].uop.debug_fsrc, slots_4.io.uop.debug_fsrc
connect issue_slots[4].uop.bp_xcpt_if, slots_4.io.uop.bp_xcpt_if
connect issue_slots[4].uop.bp_debug_if, slots_4.io.uop.bp_debug_if
connect issue_slots[4].uop.xcpt_ma_if, slots_4.io.uop.xcpt_ma_if
connect issue_slots[4].uop.xcpt_ae_if, slots_4.io.uop.xcpt_ae_if
connect issue_slots[4].uop.xcpt_pf_if, slots_4.io.uop.xcpt_pf_if
connect issue_slots[4].uop.fp_single, slots_4.io.uop.fp_single
connect issue_slots[4].uop.fp_val, slots_4.io.uop.fp_val
connect issue_slots[4].uop.frs3_en, slots_4.io.uop.frs3_en
connect issue_slots[4].uop.lrs2_rtype, slots_4.io.uop.lrs2_rtype
connect issue_slots[4].uop.lrs1_rtype, slots_4.io.uop.lrs1_rtype
connect issue_slots[4].uop.dst_rtype, slots_4.io.uop.dst_rtype
connect issue_slots[4].uop.ldst_val, slots_4.io.uop.ldst_val
connect issue_slots[4].uop.lrs3, slots_4.io.uop.lrs3
connect issue_slots[4].uop.lrs2, slots_4.io.uop.lrs2
connect issue_slots[4].uop.lrs1, slots_4.io.uop.lrs1
connect issue_slots[4].uop.ldst, slots_4.io.uop.ldst
connect issue_slots[4].uop.ldst_is_rs1, slots_4.io.uop.ldst_is_rs1
connect issue_slots[4].uop.flush_on_commit, slots_4.io.uop.flush_on_commit
connect issue_slots[4].uop.is_unique, slots_4.io.uop.is_unique
connect issue_slots[4].uop.is_sys_pc2epc, slots_4.io.uop.is_sys_pc2epc
connect issue_slots[4].uop.uses_stq, slots_4.io.uop.uses_stq
connect issue_slots[4].uop.uses_ldq, slots_4.io.uop.uses_ldq
connect issue_slots[4].uop.is_amo, slots_4.io.uop.is_amo
connect issue_slots[4].uop.is_fencei, slots_4.io.uop.is_fencei
connect issue_slots[4].uop.is_fence, slots_4.io.uop.is_fence
connect issue_slots[4].uop.mem_signed, slots_4.io.uop.mem_signed
connect issue_slots[4].uop.mem_size, slots_4.io.uop.mem_size
connect issue_slots[4].uop.mem_cmd, slots_4.io.uop.mem_cmd
connect issue_slots[4].uop.bypassable, slots_4.io.uop.bypassable
connect issue_slots[4].uop.exc_cause, slots_4.io.uop.exc_cause
connect issue_slots[4].uop.exception, slots_4.io.uop.exception
connect issue_slots[4].uop.stale_pdst, slots_4.io.uop.stale_pdst
connect issue_slots[4].uop.ppred_busy, slots_4.io.uop.ppred_busy
connect issue_slots[4].uop.prs3_busy, slots_4.io.uop.prs3_busy
connect issue_slots[4].uop.prs2_busy, slots_4.io.uop.prs2_busy
connect issue_slots[4].uop.prs1_busy, slots_4.io.uop.prs1_busy
connect issue_slots[4].uop.ppred, slots_4.io.uop.ppred
connect issue_slots[4].uop.prs3, slots_4.io.uop.prs3
connect issue_slots[4].uop.prs2, slots_4.io.uop.prs2
connect issue_slots[4].uop.prs1, slots_4.io.uop.prs1
connect issue_slots[4].uop.pdst, slots_4.io.uop.pdst
connect issue_slots[4].uop.rxq_idx, slots_4.io.uop.rxq_idx
connect issue_slots[4].uop.stq_idx, slots_4.io.uop.stq_idx
connect issue_slots[4].uop.ldq_idx, slots_4.io.uop.ldq_idx
connect issue_slots[4].uop.rob_idx, slots_4.io.uop.rob_idx
connect issue_slots[4].uop.csr_addr, slots_4.io.uop.csr_addr
connect issue_slots[4].uop.imm_packed, slots_4.io.uop.imm_packed
connect issue_slots[4].uop.taken, slots_4.io.uop.taken
connect issue_slots[4].uop.pc_lob, slots_4.io.uop.pc_lob
connect issue_slots[4].uop.edge_inst, slots_4.io.uop.edge_inst
connect issue_slots[4].uop.ftq_idx, slots_4.io.uop.ftq_idx
connect issue_slots[4].uop.br_tag, slots_4.io.uop.br_tag
connect issue_slots[4].uop.br_mask, slots_4.io.uop.br_mask
connect issue_slots[4].uop.is_sfb, slots_4.io.uop.is_sfb
connect issue_slots[4].uop.is_jal, slots_4.io.uop.is_jal
connect issue_slots[4].uop.is_jalr, slots_4.io.uop.is_jalr
connect issue_slots[4].uop.is_br, slots_4.io.uop.is_br
connect issue_slots[4].uop.iw_p2_poisoned, slots_4.io.uop.iw_p2_poisoned
connect issue_slots[4].uop.iw_p1_poisoned, slots_4.io.uop.iw_p1_poisoned
connect issue_slots[4].uop.iw_state, slots_4.io.uop.iw_state
connect issue_slots[4].uop.ctrl.is_std, slots_4.io.uop.ctrl.is_std
connect issue_slots[4].uop.ctrl.is_sta, slots_4.io.uop.ctrl.is_sta
connect issue_slots[4].uop.ctrl.is_load, slots_4.io.uop.ctrl.is_load
connect issue_slots[4].uop.ctrl.csr_cmd, slots_4.io.uop.ctrl.csr_cmd
connect issue_slots[4].uop.ctrl.fcn_dw, slots_4.io.uop.ctrl.fcn_dw
connect issue_slots[4].uop.ctrl.op_fcn, slots_4.io.uop.ctrl.op_fcn
connect issue_slots[4].uop.ctrl.imm_sel, slots_4.io.uop.ctrl.imm_sel
connect issue_slots[4].uop.ctrl.op2_sel, slots_4.io.uop.ctrl.op2_sel
connect issue_slots[4].uop.ctrl.op1_sel, slots_4.io.uop.ctrl.op1_sel
connect issue_slots[4].uop.ctrl.br_type, slots_4.io.uop.ctrl.br_type
connect issue_slots[4].uop.fu_code, slots_4.io.uop.fu_code
connect issue_slots[4].uop.iq_type, slots_4.io.uop.iq_type
connect issue_slots[4].uop.debug_pc, slots_4.io.uop.debug_pc
connect issue_slots[4].uop.is_rvc, slots_4.io.uop.is_rvc
connect issue_slots[4].uop.debug_inst, slots_4.io.uop.debug_inst
connect issue_slots[4].uop.inst, slots_4.io.uop.inst
connect issue_slots[4].uop.uopc, slots_4.io.uop.uopc
connect issue_slots[4].out_uop.debug_tsrc, slots_4.io.out_uop.debug_tsrc
connect issue_slots[4].out_uop.debug_fsrc, slots_4.io.out_uop.debug_fsrc
connect issue_slots[4].out_uop.bp_xcpt_if, slots_4.io.out_uop.bp_xcpt_if
connect issue_slots[4].out_uop.bp_debug_if, slots_4.io.out_uop.bp_debug_if
connect issue_slots[4].out_uop.xcpt_ma_if, slots_4.io.out_uop.xcpt_ma_if
connect issue_slots[4].out_uop.xcpt_ae_if, slots_4.io.out_uop.xcpt_ae_if
connect issue_slots[4].out_uop.xcpt_pf_if, slots_4.io.out_uop.xcpt_pf_if
connect issue_slots[4].out_uop.fp_single, slots_4.io.out_uop.fp_single
connect issue_slots[4].out_uop.fp_val, slots_4.io.out_uop.fp_val
connect issue_slots[4].out_uop.frs3_en, slots_4.io.out_uop.frs3_en
connect issue_slots[4].out_uop.lrs2_rtype, slots_4.io.out_uop.lrs2_rtype
connect issue_slots[4].out_uop.lrs1_rtype, slots_4.io.out_uop.lrs1_rtype
connect issue_slots[4].out_uop.dst_rtype, slots_4.io.out_uop.dst_rtype
connect issue_slots[4].out_uop.ldst_val, slots_4.io.out_uop.ldst_val
connect issue_slots[4].out_uop.lrs3, slots_4.io.out_uop.lrs3
connect issue_slots[4].out_uop.lrs2, slots_4.io.out_uop.lrs2
connect issue_slots[4].out_uop.lrs1, slots_4.io.out_uop.lrs1
connect issue_slots[4].out_uop.ldst, slots_4.io.out_uop.ldst
connect issue_slots[4].out_uop.ldst_is_rs1, slots_4.io.out_uop.ldst_is_rs1
connect issue_slots[4].out_uop.flush_on_commit, slots_4.io.out_uop.flush_on_commit
connect issue_slots[4].out_uop.is_unique, slots_4.io.out_uop.is_unique
connect issue_slots[4].out_uop.is_sys_pc2epc, slots_4.io.out_uop.is_sys_pc2epc
connect issue_slots[4].out_uop.uses_stq, slots_4.io.out_uop.uses_stq
connect issue_slots[4].out_uop.uses_ldq, slots_4.io.out_uop.uses_ldq
connect issue_slots[4].out_uop.is_amo, slots_4.io.out_uop.is_amo
connect issue_slots[4].out_uop.is_fencei, slots_4.io.out_uop.is_fencei
connect issue_slots[4].out_uop.is_fence, slots_4.io.out_uop.is_fence
connect issue_slots[4].out_uop.mem_signed, slots_4.io.out_uop.mem_signed
connect issue_slots[4].out_uop.mem_size, slots_4.io.out_uop.mem_size
connect issue_slots[4].out_uop.mem_cmd, slots_4.io.out_uop.mem_cmd
connect issue_slots[4].out_uop.bypassable, slots_4.io.out_uop.bypassable
connect issue_slots[4].out_uop.exc_cause, slots_4.io.out_uop.exc_cause
connect issue_slots[4].out_uop.exception, slots_4.io.out_uop.exception
connect issue_slots[4].out_uop.stale_pdst, slots_4.io.out_uop.stale_pdst
connect issue_slots[4].out_uop.ppred_busy, slots_4.io.out_uop.ppred_busy
connect issue_slots[4].out_uop.prs3_busy, slots_4.io.out_uop.prs3_busy
connect issue_slots[4].out_uop.prs2_busy, slots_4.io.out_uop.prs2_busy
connect issue_slots[4].out_uop.prs1_busy, slots_4.io.out_uop.prs1_busy
connect issue_slots[4].out_uop.ppred, slots_4.io.out_uop.ppred
connect issue_slots[4].out_uop.prs3, slots_4.io.out_uop.prs3
connect issue_slots[4].out_uop.prs2, slots_4.io.out_uop.prs2
connect issue_slots[4].out_uop.prs1, slots_4.io.out_uop.prs1
connect issue_slots[4].out_uop.pdst, slots_4.io.out_uop.pdst
connect issue_slots[4].out_uop.rxq_idx, slots_4.io.out_uop.rxq_idx
connect issue_slots[4].out_uop.stq_idx, slots_4.io.out_uop.stq_idx
connect issue_slots[4].out_uop.ldq_idx, slots_4.io.out_uop.ldq_idx
connect issue_slots[4].out_uop.rob_idx, slots_4.io.out_uop.rob_idx
connect issue_slots[4].out_uop.csr_addr, slots_4.io.out_uop.csr_addr
connect issue_slots[4].out_uop.imm_packed, slots_4.io.out_uop.imm_packed
connect issue_slots[4].out_uop.taken, slots_4.io.out_uop.taken
connect issue_slots[4].out_uop.pc_lob, slots_4.io.out_uop.pc_lob
connect issue_slots[4].out_uop.edge_inst, slots_4.io.out_uop.edge_inst
connect issue_slots[4].out_uop.ftq_idx, slots_4.io.out_uop.ftq_idx
connect issue_slots[4].out_uop.br_tag, slots_4.io.out_uop.br_tag
connect issue_slots[4].out_uop.br_mask, slots_4.io.out_uop.br_mask
connect issue_slots[4].out_uop.is_sfb, slots_4.io.out_uop.is_sfb
connect issue_slots[4].out_uop.is_jal, slots_4.io.out_uop.is_jal
connect issue_slots[4].out_uop.is_jalr, slots_4.io.out_uop.is_jalr
connect issue_slots[4].out_uop.is_br, slots_4.io.out_uop.is_br
connect issue_slots[4].out_uop.iw_p2_poisoned, slots_4.io.out_uop.iw_p2_poisoned
connect issue_slots[4].out_uop.iw_p1_poisoned, slots_4.io.out_uop.iw_p1_poisoned
connect issue_slots[4].out_uop.iw_state, slots_4.io.out_uop.iw_state
connect issue_slots[4].out_uop.ctrl.is_std, slots_4.io.out_uop.ctrl.is_std
connect issue_slots[4].out_uop.ctrl.is_sta, slots_4.io.out_uop.ctrl.is_sta
connect issue_slots[4].out_uop.ctrl.is_load, slots_4.io.out_uop.ctrl.is_load
connect issue_slots[4].out_uop.ctrl.csr_cmd, slots_4.io.out_uop.ctrl.csr_cmd
connect issue_slots[4].out_uop.ctrl.fcn_dw, slots_4.io.out_uop.ctrl.fcn_dw
connect issue_slots[4].out_uop.ctrl.op_fcn, slots_4.io.out_uop.ctrl.op_fcn
connect issue_slots[4].out_uop.ctrl.imm_sel, slots_4.io.out_uop.ctrl.imm_sel
connect issue_slots[4].out_uop.ctrl.op2_sel, slots_4.io.out_uop.ctrl.op2_sel
connect issue_slots[4].out_uop.ctrl.op1_sel, slots_4.io.out_uop.ctrl.op1_sel
connect issue_slots[4].out_uop.ctrl.br_type, slots_4.io.out_uop.ctrl.br_type
connect issue_slots[4].out_uop.fu_code, slots_4.io.out_uop.fu_code
connect issue_slots[4].out_uop.iq_type, slots_4.io.out_uop.iq_type
connect issue_slots[4].out_uop.debug_pc, slots_4.io.out_uop.debug_pc
connect issue_slots[4].out_uop.is_rvc, slots_4.io.out_uop.is_rvc
connect issue_slots[4].out_uop.debug_inst, slots_4.io.out_uop.debug_inst
connect issue_slots[4].out_uop.inst, slots_4.io.out_uop.inst
connect issue_slots[4].out_uop.uopc, slots_4.io.out_uop.uopc
connect slots_4.io.in_uop.bits.debug_tsrc, issue_slots[4].in_uop.bits.debug_tsrc
connect slots_4.io.in_uop.bits.debug_fsrc, issue_slots[4].in_uop.bits.debug_fsrc
connect slots_4.io.in_uop.bits.bp_xcpt_if, issue_slots[4].in_uop.bits.bp_xcpt_if
connect slots_4.io.in_uop.bits.bp_debug_if, issue_slots[4].in_uop.bits.bp_debug_if
connect slots_4.io.in_uop.bits.xcpt_ma_if, issue_slots[4].in_uop.bits.xcpt_ma_if
connect slots_4.io.in_uop.bits.xcpt_ae_if, issue_slots[4].in_uop.bits.xcpt_ae_if
connect slots_4.io.in_uop.bits.xcpt_pf_if, issue_slots[4].in_uop.bits.xcpt_pf_if
connect slots_4.io.in_uop.bits.fp_single, issue_slots[4].in_uop.bits.fp_single
connect slots_4.io.in_uop.bits.fp_val, issue_slots[4].in_uop.bits.fp_val
connect slots_4.io.in_uop.bits.frs3_en, issue_slots[4].in_uop.bits.frs3_en
connect slots_4.io.in_uop.bits.lrs2_rtype, issue_slots[4].in_uop.bits.lrs2_rtype
connect slots_4.io.in_uop.bits.lrs1_rtype, issue_slots[4].in_uop.bits.lrs1_rtype
connect slots_4.io.in_uop.bits.dst_rtype, issue_slots[4].in_uop.bits.dst_rtype
connect slots_4.io.in_uop.bits.ldst_val, issue_slots[4].in_uop.bits.ldst_val
connect slots_4.io.in_uop.bits.lrs3, issue_slots[4].in_uop.bits.lrs3
connect slots_4.io.in_uop.bits.lrs2, issue_slots[4].in_uop.bits.lrs2
connect slots_4.io.in_uop.bits.lrs1, issue_slots[4].in_uop.bits.lrs1
connect slots_4.io.in_uop.bits.ldst, issue_slots[4].in_uop.bits.ldst
connect slots_4.io.in_uop.bits.ldst_is_rs1, issue_slots[4].in_uop.bits.ldst_is_rs1
connect slots_4.io.in_uop.bits.flush_on_commit, issue_slots[4].in_uop.bits.flush_on_commit
connect slots_4.io.in_uop.bits.is_unique, issue_slots[4].in_uop.bits.is_unique
connect slots_4.io.in_uop.bits.is_sys_pc2epc, issue_slots[4].in_uop.bits.is_sys_pc2epc
connect slots_4.io.in_uop.bits.uses_stq, issue_slots[4].in_uop.bits.uses_stq
connect slots_4.io.in_uop.bits.uses_ldq, issue_slots[4].in_uop.bits.uses_ldq
connect slots_4.io.in_uop.bits.is_amo, issue_slots[4].in_uop.bits.is_amo
connect slots_4.io.in_uop.bits.is_fencei, issue_slots[4].in_uop.bits.is_fencei
connect slots_4.io.in_uop.bits.is_fence, issue_slots[4].in_uop.bits.is_fence
connect slots_4.io.in_uop.bits.mem_signed, issue_slots[4].in_uop.bits.mem_signed
connect slots_4.io.in_uop.bits.mem_size, issue_slots[4].in_uop.bits.mem_size
connect slots_4.io.in_uop.bits.mem_cmd, issue_slots[4].in_uop.bits.mem_cmd
connect slots_4.io.in_uop.bits.bypassable, issue_slots[4].in_uop.bits.bypassable
connect slots_4.io.in_uop.bits.exc_cause, issue_slots[4].in_uop.bits.exc_cause
connect slots_4.io.in_uop.bits.exception, issue_slots[4].in_uop.bits.exception
connect slots_4.io.in_uop.bits.stale_pdst, issue_slots[4].in_uop.bits.stale_pdst
connect slots_4.io.in_uop.bits.ppred_busy, issue_slots[4].in_uop.bits.ppred_busy
connect slots_4.io.in_uop.bits.prs3_busy, issue_slots[4].in_uop.bits.prs3_busy
connect slots_4.io.in_uop.bits.prs2_busy, issue_slots[4].in_uop.bits.prs2_busy
connect slots_4.io.in_uop.bits.prs1_busy, issue_slots[4].in_uop.bits.prs1_busy
connect slots_4.io.in_uop.bits.ppred, issue_slots[4].in_uop.bits.ppred
connect slots_4.io.in_uop.bits.prs3, issue_slots[4].in_uop.bits.prs3
connect slots_4.io.in_uop.bits.prs2, issue_slots[4].in_uop.bits.prs2
connect slots_4.io.in_uop.bits.prs1, issue_slots[4].in_uop.bits.prs1
connect slots_4.io.in_uop.bits.pdst, issue_slots[4].in_uop.bits.pdst
connect slots_4.io.in_uop.bits.rxq_idx, issue_slots[4].in_uop.bits.rxq_idx
connect slots_4.io.in_uop.bits.stq_idx, issue_slots[4].in_uop.bits.stq_idx
connect slots_4.io.in_uop.bits.ldq_idx, issue_slots[4].in_uop.bits.ldq_idx
connect slots_4.io.in_uop.bits.rob_idx, issue_slots[4].in_uop.bits.rob_idx
connect slots_4.io.in_uop.bits.csr_addr, issue_slots[4].in_uop.bits.csr_addr
connect slots_4.io.in_uop.bits.imm_packed, issue_slots[4].in_uop.bits.imm_packed
connect slots_4.io.in_uop.bits.taken, issue_slots[4].in_uop.bits.taken
connect slots_4.io.in_uop.bits.pc_lob, issue_slots[4].in_uop.bits.pc_lob
connect slots_4.io.in_uop.bits.edge_inst, issue_slots[4].in_uop.bits.edge_inst
connect slots_4.io.in_uop.bits.ftq_idx, issue_slots[4].in_uop.bits.ftq_idx
connect slots_4.io.in_uop.bits.br_tag, issue_slots[4].in_uop.bits.br_tag
connect slots_4.io.in_uop.bits.br_mask, issue_slots[4].in_uop.bits.br_mask
connect slots_4.io.in_uop.bits.is_sfb, issue_slots[4].in_uop.bits.is_sfb
connect slots_4.io.in_uop.bits.is_jal, issue_slots[4].in_uop.bits.is_jal
connect slots_4.io.in_uop.bits.is_jalr, issue_slots[4].in_uop.bits.is_jalr
connect slots_4.io.in_uop.bits.is_br, issue_slots[4].in_uop.bits.is_br
connect slots_4.io.in_uop.bits.iw_p2_poisoned, issue_slots[4].in_uop.bits.iw_p2_poisoned
connect slots_4.io.in_uop.bits.iw_p1_poisoned, issue_slots[4].in_uop.bits.iw_p1_poisoned
connect slots_4.io.in_uop.bits.iw_state, issue_slots[4].in_uop.bits.iw_state
connect slots_4.io.in_uop.bits.ctrl.is_std, issue_slots[4].in_uop.bits.ctrl.is_std
connect slots_4.io.in_uop.bits.ctrl.is_sta, issue_slots[4].in_uop.bits.ctrl.is_sta
connect slots_4.io.in_uop.bits.ctrl.is_load, issue_slots[4].in_uop.bits.ctrl.is_load
connect slots_4.io.in_uop.bits.ctrl.csr_cmd, issue_slots[4].in_uop.bits.ctrl.csr_cmd
connect slots_4.io.in_uop.bits.ctrl.fcn_dw, issue_slots[4].in_uop.bits.ctrl.fcn_dw
connect slots_4.io.in_uop.bits.ctrl.op_fcn, issue_slots[4].in_uop.bits.ctrl.op_fcn
connect slots_4.io.in_uop.bits.ctrl.imm_sel, issue_slots[4].in_uop.bits.ctrl.imm_sel
connect slots_4.io.in_uop.bits.ctrl.op2_sel, issue_slots[4].in_uop.bits.ctrl.op2_sel
connect slots_4.io.in_uop.bits.ctrl.op1_sel, issue_slots[4].in_uop.bits.ctrl.op1_sel
connect slots_4.io.in_uop.bits.ctrl.br_type, issue_slots[4].in_uop.bits.ctrl.br_type
connect slots_4.io.in_uop.bits.fu_code, issue_slots[4].in_uop.bits.fu_code
connect slots_4.io.in_uop.bits.iq_type, issue_slots[4].in_uop.bits.iq_type
connect slots_4.io.in_uop.bits.debug_pc, issue_slots[4].in_uop.bits.debug_pc
connect slots_4.io.in_uop.bits.is_rvc, issue_slots[4].in_uop.bits.is_rvc
connect slots_4.io.in_uop.bits.debug_inst, issue_slots[4].in_uop.bits.debug_inst
connect slots_4.io.in_uop.bits.inst, issue_slots[4].in_uop.bits.inst
connect slots_4.io.in_uop.bits.uopc, issue_slots[4].in_uop.bits.uopc
connect slots_4.io.in_uop.valid, issue_slots[4].in_uop.valid
connect slots_4.io.spec_ld_wakeup[0].bits, issue_slots[4].spec_ld_wakeup[0].bits
connect slots_4.io.spec_ld_wakeup[0].valid, issue_slots[4].spec_ld_wakeup[0].valid
connect slots_4.io.pred_wakeup_port.bits, issue_slots[4].pred_wakeup_port.bits
connect slots_4.io.pred_wakeup_port.valid, issue_slots[4].pred_wakeup_port.valid
connect slots_4.io.wakeup_ports[0].bits.poisoned, issue_slots[4].wakeup_ports[0].bits.poisoned
connect slots_4.io.wakeup_ports[0].bits.pdst, issue_slots[4].wakeup_ports[0].bits.pdst
connect slots_4.io.wakeup_ports[0].valid, issue_slots[4].wakeup_ports[0].valid
connect slots_4.io.wakeup_ports[1].bits.poisoned, issue_slots[4].wakeup_ports[1].bits.poisoned
connect slots_4.io.wakeup_ports[1].bits.pdst, issue_slots[4].wakeup_ports[1].bits.pdst
connect slots_4.io.wakeup_ports[1].valid, issue_slots[4].wakeup_ports[1].valid
connect slots_4.io.wakeup_ports[2].bits.poisoned, issue_slots[4].wakeup_ports[2].bits.poisoned
connect slots_4.io.wakeup_ports[2].bits.pdst, issue_slots[4].wakeup_ports[2].bits.pdst
connect slots_4.io.wakeup_ports[2].valid, issue_slots[4].wakeup_ports[2].valid
connect slots_4.io.ldspec_miss, issue_slots[4].ldspec_miss
connect slots_4.io.clear, issue_slots[4].clear
connect slots_4.io.kill, issue_slots[4].kill
connect slots_4.io.brupdate.b2.target_offset, issue_slots[4].brupdate.b2.target_offset
connect slots_4.io.brupdate.b2.jalr_target, issue_slots[4].brupdate.b2.jalr_target
connect slots_4.io.brupdate.b2.pc_sel, issue_slots[4].brupdate.b2.pc_sel
connect slots_4.io.brupdate.b2.cfi_type, issue_slots[4].brupdate.b2.cfi_type
connect slots_4.io.brupdate.b2.taken, issue_slots[4].brupdate.b2.taken
connect slots_4.io.brupdate.b2.mispredict, issue_slots[4].brupdate.b2.mispredict
connect slots_4.io.brupdate.b2.valid, issue_slots[4].brupdate.b2.valid
connect slots_4.io.brupdate.b2.uop.debug_tsrc, issue_slots[4].brupdate.b2.uop.debug_tsrc
connect slots_4.io.brupdate.b2.uop.debug_fsrc, issue_slots[4].brupdate.b2.uop.debug_fsrc
connect slots_4.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[4].brupdate.b2.uop.bp_xcpt_if
connect slots_4.io.brupdate.b2.uop.bp_debug_if, issue_slots[4].brupdate.b2.uop.bp_debug_if
connect slots_4.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[4].brupdate.b2.uop.xcpt_ma_if
connect slots_4.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[4].brupdate.b2.uop.xcpt_ae_if
connect slots_4.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[4].brupdate.b2.uop.xcpt_pf_if
connect slots_4.io.brupdate.b2.uop.fp_single, issue_slots[4].brupdate.b2.uop.fp_single
connect slots_4.io.brupdate.b2.uop.fp_val, issue_slots[4].brupdate.b2.uop.fp_val
connect slots_4.io.brupdate.b2.uop.frs3_en, issue_slots[4].brupdate.b2.uop.frs3_en
connect slots_4.io.brupdate.b2.uop.lrs2_rtype, issue_slots[4].brupdate.b2.uop.lrs2_rtype
connect slots_4.io.brupdate.b2.uop.lrs1_rtype, issue_slots[4].brupdate.b2.uop.lrs1_rtype
connect slots_4.io.brupdate.b2.uop.dst_rtype, issue_slots[4].brupdate.b2.uop.dst_rtype
connect slots_4.io.brupdate.b2.uop.ldst_val, issue_slots[4].brupdate.b2.uop.ldst_val
connect slots_4.io.brupdate.b2.uop.lrs3, issue_slots[4].brupdate.b2.uop.lrs3
connect slots_4.io.brupdate.b2.uop.lrs2, issue_slots[4].brupdate.b2.uop.lrs2
connect slots_4.io.brupdate.b2.uop.lrs1, issue_slots[4].brupdate.b2.uop.lrs1
connect slots_4.io.brupdate.b2.uop.ldst, issue_slots[4].brupdate.b2.uop.ldst
connect slots_4.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[4].brupdate.b2.uop.ldst_is_rs1
connect slots_4.io.brupdate.b2.uop.flush_on_commit, issue_slots[4].brupdate.b2.uop.flush_on_commit
connect slots_4.io.brupdate.b2.uop.is_unique, issue_slots[4].brupdate.b2.uop.is_unique
connect slots_4.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[4].brupdate.b2.uop.is_sys_pc2epc
connect slots_4.io.brupdate.b2.uop.uses_stq, issue_slots[4].brupdate.b2.uop.uses_stq
connect slots_4.io.brupdate.b2.uop.uses_ldq, issue_slots[4].brupdate.b2.uop.uses_ldq
connect slots_4.io.brupdate.b2.uop.is_amo, issue_slots[4].brupdate.b2.uop.is_amo
connect slots_4.io.brupdate.b2.uop.is_fencei, issue_slots[4].brupdate.b2.uop.is_fencei
connect slots_4.io.brupdate.b2.uop.is_fence, issue_slots[4].brupdate.b2.uop.is_fence
connect slots_4.io.brupdate.b2.uop.mem_signed, issue_slots[4].brupdate.b2.uop.mem_signed
connect slots_4.io.brupdate.b2.uop.mem_size, issue_slots[4].brupdate.b2.uop.mem_size
connect slots_4.io.brupdate.b2.uop.mem_cmd, issue_slots[4].brupdate.b2.uop.mem_cmd
connect slots_4.io.brupdate.b2.uop.bypassable, issue_slots[4].brupdate.b2.uop.bypassable
connect slots_4.io.brupdate.b2.uop.exc_cause, issue_slots[4].brupdate.b2.uop.exc_cause
connect slots_4.io.brupdate.b2.uop.exception, issue_slots[4].brupdate.b2.uop.exception
connect slots_4.io.brupdate.b2.uop.stale_pdst, issue_slots[4].brupdate.b2.uop.stale_pdst
connect slots_4.io.brupdate.b2.uop.ppred_busy, issue_slots[4].brupdate.b2.uop.ppred_busy
connect slots_4.io.brupdate.b2.uop.prs3_busy, issue_slots[4].brupdate.b2.uop.prs3_busy
connect slots_4.io.brupdate.b2.uop.prs2_busy, issue_slots[4].brupdate.b2.uop.prs2_busy
connect slots_4.io.brupdate.b2.uop.prs1_busy, issue_slots[4].brupdate.b2.uop.prs1_busy
connect slots_4.io.brupdate.b2.uop.ppred, issue_slots[4].brupdate.b2.uop.ppred
connect slots_4.io.brupdate.b2.uop.prs3, issue_slots[4].brupdate.b2.uop.prs3
connect slots_4.io.brupdate.b2.uop.prs2, issue_slots[4].brupdate.b2.uop.prs2
connect slots_4.io.brupdate.b2.uop.prs1, issue_slots[4].brupdate.b2.uop.prs1
connect slots_4.io.brupdate.b2.uop.pdst, issue_slots[4].brupdate.b2.uop.pdst
connect slots_4.io.brupdate.b2.uop.rxq_idx, issue_slots[4].brupdate.b2.uop.rxq_idx
connect slots_4.io.brupdate.b2.uop.stq_idx, issue_slots[4].brupdate.b2.uop.stq_idx
connect slots_4.io.brupdate.b2.uop.ldq_idx, issue_slots[4].brupdate.b2.uop.ldq_idx
connect slots_4.io.brupdate.b2.uop.rob_idx, issue_slots[4].brupdate.b2.uop.rob_idx
connect slots_4.io.brupdate.b2.uop.csr_addr, issue_slots[4].brupdate.b2.uop.csr_addr
connect slots_4.io.brupdate.b2.uop.imm_packed, issue_slots[4].brupdate.b2.uop.imm_packed
connect slots_4.io.brupdate.b2.uop.taken, issue_slots[4].brupdate.b2.uop.taken
connect slots_4.io.brupdate.b2.uop.pc_lob, issue_slots[4].brupdate.b2.uop.pc_lob
connect slots_4.io.brupdate.b2.uop.edge_inst, issue_slots[4].brupdate.b2.uop.edge_inst
connect slots_4.io.brupdate.b2.uop.ftq_idx, issue_slots[4].brupdate.b2.uop.ftq_idx
connect slots_4.io.brupdate.b2.uop.br_tag, issue_slots[4].brupdate.b2.uop.br_tag
connect slots_4.io.brupdate.b2.uop.br_mask, issue_slots[4].brupdate.b2.uop.br_mask
connect slots_4.io.brupdate.b2.uop.is_sfb, issue_slots[4].brupdate.b2.uop.is_sfb
connect slots_4.io.brupdate.b2.uop.is_jal, issue_slots[4].brupdate.b2.uop.is_jal
connect slots_4.io.brupdate.b2.uop.is_jalr, issue_slots[4].brupdate.b2.uop.is_jalr
connect slots_4.io.brupdate.b2.uop.is_br, issue_slots[4].brupdate.b2.uop.is_br
connect slots_4.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[4].brupdate.b2.uop.iw_p2_poisoned
connect slots_4.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[4].brupdate.b2.uop.iw_p1_poisoned
connect slots_4.io.brupdate.b2.uop.iw_state, issue_slots[4].brupdate.b2.uop.iw_state
connect slots_4.io.brupdate.b2.uop.ctrl.is_std, issue_slots[4].brupdate.b2.uop.ctrl.is_std
connect slots_4.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[4].brupdate.b2.uop.ctrl.is_sta
connect slots_4.io.brupdate.b2.uop.ctrl.is_load, issue_slots[4].brupdate.b2.uop.ctrl.is_load
connect slots_4.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[4].brupdate.b2.uop.ctrl.csr_cmd
connect slots_4.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[4].brupdate.b2.uop.ctrl.fcn_dw
connect slots_4.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[4].brupdate.b2.uop.ctrl.op_fcn
connect slots_4.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[4].brupdate.b2.uop.ctrl.imm_sel
connect slots_4.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[4].brupdate.b2.uop.ctrl.op2_sel
connect slots_4.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[4].brupdate.b2.uop.ctrl.op1_sel
connect slots_4.io.brupdate.b2.uop.ctrl.br_type, issue_slots[4].brupdate.b2.uop.ctrl.br_type
connect slots_4.io.brupdate.b2.uop.fu_code, issue_slots[4].brupdate.b2.uop.fu_code
connect slots_4.io.brupdate.b2.uop.iq_type, issue_slots[4].brupdate.b2.uop.iq_type
connect slots_4.io.brupdate.b2.uop.debug_pc, issue_slots[4].brupdate.b2.uop.debug_pc
connect slots_4.io.brupdate.b2.uop.is_rvc, issue_slots[4].brupdate.b2.uop.is_rvc
connect slots_4.io.brupdate.b2.uop.debug_inst, issue_slots[4].brupdate.b2.uop.debug_inst
connect slots_4.io.brupdate.b2.uop.inst, issue_slots[4].brupdate.b2.uop.inst
connect slots_4.io.brupdate.b2.uop.uopc, issue_slots[4].brupdate.b2.uop.uopc
connect slots_4.io.brupdate.b1.mispredict_mask, issue_slots[4].brupdate.b1.mispredict_mask
connect slots_4.io.brupdate.b1.resolve_mask, issue_slots[4].brupdate.b1.resolve_mask
connect slots_4.io.grant, issue_slots[4].grant
connect issue_slots[4].request_hp, slots_4.io.request_hp
connect issue_slots[4].request, slots_4.io.request
connect issue_slots[4].will_be_valid, slots_4.io.will_be_valid
connect issue_slots[4].valid, slots_4.io.valid
connect issue_slots[5].debug.state, slots_5.io.debug.state
connect issue_slots[5].debug.ppred, slots_5.io.debug.ppred
connect issue_slots[5].debug.p3, slots_5.io.debug.p3
connect issue_slots[5].debug.p2, slots_5.io.debug.p2
connect issue_slots[5].debug.p1, slots_5.io.debug.p1
connect issue_slots[5].uop.debug_tsrc, slots_5.io.uop.debug_tsrc
connect issue_slots[5].uop.debug_fsrc, slots_5.io.uop.debug_fsrc
connect issue_slots[5].uop.bp_xcpt_if, slots_5.io.uop.bp_xcpt_if
connect issue_slots[5].uop.bp_debug_if, slots_5.io.uop.bp_debug_if
connect issue_slots[5].uop.xcpt_ma_if, slots_5.io.uop.xcpt_ma_if
connect issue_slots[5].uop.xcpt_ae_if, slots_5.io.uop.xcpt_ae_if
connect issue_slots[5].uop.xcpt_pf_if, slots_5.io.uop.xcpt_pf_if
connect issue_slots[5].uop.fp_single, slots_5.io.uop.fp_single
connect issue_slots[5].uop.fp_val, slots_5.io.uop.fp_val
connect issue_slots[5].uop.frs3_en, slots_5.io.uop.frs3_en
connect issue_slots[5].uop.lrs2_rtype, slots_5.io.uop.lrs2_rtype
connect issue_slots[5].uop.lrs1_rtype, slots_5.io.uop.lrs1_rtype
connect issue_slots[5].uop.dst_rtype, slots_5.io.uop.dst_rtype
connect issue_slots[5].uop.ldst_val, slots_5.io.uop.ldst_val
connect issue_slots[5].uop.lrs3, slots_5.io.uop.lrs3
connect issue_slots[5].uop.lrs2, slots_5.io.uop.lrs2
connect issue_slots[5].uop.lrs1, slots_5.io.uop.lrs1
connect issue_slots[5].uop.ldst, slots_5.io.uop.ldst
connect issue_slots[5].uop.ldst_is_rs1, slots_5.io.uop.ldst_is_rs1
connect issue_slots[5].uop.flush_on_commit, slots_5.io.uop.flush_on_commit
connect issue_slots[5].uop.is_unique, slots_5.io.uop.is_unique
connect issue_slots[5].uop.is_sys_pc2epc, slots_5.io.uop.is_sys_pc2epc
connect issue_slots[5].uop.uses_stq, slots_5.io.uop.uses_stq
connect issue_slots[5].uop.uses_ldq, slots_5.io.uop.uses_ldq
connect issue_slots[5].uop.is_amo, slots_5.io.uop.is_amo
connect issue_slots[5].uop.is_fencei, slots_5.io.uop.is_fencei
connect issue_slots[5].uop.is_fence, slots_5.io.uop.is_fence
connect issue_slots[5].uop.mem_signed, slots_5.io.uop.mem_signed
connect issue_slots[5].uop.mem_size, slots_5.io.uop.mem_size
connect issue_slots[5].uop.mem_cmd, slots_5.io.uop.mem_cmd
connect issue_slots[5].uop.bypassable, slots_5.io.uop.bypassable
connect issue_slots[5].uop.exc_cause, slots_5.io.uop.exc_cause
connect issue_slots[5].uop.exception, slots_5.io.uop.exception
connect issue_slots[5].uop.stale_pdst, slots_5.io.uop.stale_pdst
connect issue_slots[5].uop.ppred_busy, slots_5.io.uop.ppred_busy
connect issue_slots[5].uop.prs3_busy, slots_5.io.uop.prs3_busy
connect issue_slots[5].uop.prs2_busy, slots_5.io.uop.prs2_busy
connect issue_slots[5].uop.prs1_busy, slots_5.io.uop.prs1_busy
connect issue_slots[5].uop.ppred, slots_5.io.uop.ppred
connect issue_slots[5].uop.prs3, slots_5.io.uop.prs3
connect issue_slots[5].uop.prs2, slots_5.io.uop.prs2
connect issue_slots[5].uop.prs1, slots_5.io.uop.prs1
connect issue_slots[5].uop.pdst, slots_5.io.uop.pdst
connect issue_slots[5].uop.rxq_idx, slots_5.io.uop.rxq_idx
connect issue_slots[5].uop.stq_idx, slots_5.io.uop.stq_idx
connect issue_slots[5].uop.ldq_idx, slots_5.io.uop.ldq_idx
connect issue_slots[5].uop.rob_idx, slots_5.io.uop.rob_idx
connect issue_slots[5].uop.csr_addr, slots_5.io.uop.csr_addr
connect issue_slots[5].uop.imm_packed, slots_5.io.uop.imm_packed
connect issue_slots[5].uop.taken, slots_5.io.uop.taken
connect issue_slots[5].uop.pc_lob, slots_5.io.uop.pc_lob
connect issue_slots[5].uop.edge_inst, slots_5.io.uop.edge_inst
connect issue_slots[5].uop.ftq_idx, slots_5.io.uop.ftq_idx
connect issue_slots[5].uop.br_tag, slots_5.io.uop.br_tag
connect issue_slots[5].uop.br_mask, slots_5.io.uop.br_mask
connect issue_slots[5].uop.is_sfb, slots_5.io.uop.is_sfb
connect issue_slots[5].uop.is_jal, slots_5.io.uop.is_jal
connect issue_slots[5].uop.is_jalr, slots_5.io.uop.is_jalr
connect issue_slots[5].uop.is_br, slots_5.io.uop.is_br
connect issue_slots[5].uop.iw_p2_poisoned, slots_5.io.uop.iw_p2_poisoned
connect issue_slots[5].uop.iw_p1_poisoned, slots_5.io.uop.iw_p1_poisoned
connect issue_slots[5].uop.iw_state, slots_5.io.uop.iw_state
connect issue_slots[5].uop.ctrl.is_std, slots_5.io.uop.ctrl.is_std
connect issue_slots[5].uop.ctrl.is_sta, slots_5.io.uop.ctrl.is_sta
connect issue_slots[5].uop.ctrl.is_load, slots_5.io.uop.ctrl.is_load
connect issue_slots[5].uop.ctrl.csr_cmd, slots_5.io.uop.ctrl.csr_cmd
connect issue_slots[5].uop.ctrl.fcn_dw, slots_5.io.uop.ctrl.fcn_dw
connect issue_slots[5].uop.ctrl.op_fcn, slots_5.io.uop.ctrl.op_fcn
connect issue_slots[5].uop.ctrl.imm_sel, slots_5.io.uop.ctrl.imm_sel
connect issue_slots[5].uop.ctrl.op2_sel, slots_5.io.uop.ctrl.op2_sel
connect issue_slots[5].uop.ctrl.op1_sel, slots_5.io.uop.ctrl.op1_sel
connect issue_slots[5].uop.ctrl.br_type, slots_5.io.uop.ctrl.br_type
connect issue_slots[5].uop.fu_code, slots_5.io.uop.fu_code
connect issue_slots[5].uop.iq_type, slots_5.io.uop.iq_type
connect issue_slots[5].uop.debug_pc, slots_5.io.uop.debug_pc
connect issue_slots[5].uop.is_rvc, slots_5.io.uop.is_rvc
connect issue_slots[5].uop.debug_inst, slots_5.io.uop.debug_inst
connect issue_slots[5].uop.inst, slots_5.io.uop.inst
connect issue_slots[5].uop.uopc, slots_5.io.uop.uopc
connect issue_slots[5].out_uop.debug_tsrc, slots_5.io.out_uop.debug_tsrc
connect issue_slots[5].out_uop.debug_fsrc, slots_5.io.out_uop.debug_fsrc
connect issue_slots[5].out_uop.bp_xcpt_if, slots_5.io.out_uop.bp_xcpt_if
connect issue_slots[5].out_uop.bp_debug_if, slots_5.io.out_uop.bp_debug_if
connect issue_slots[5].out_uop.xcpt_ma_if, slots_5.io.out_uop.xcpt_ma_if
connect issue_slots[5].out_uop.xcpt_ae_if, slots_5.io.out_uop.xcpt_ae_if
connect issue_slots[5].out_uop.xcpt_pf_if, slots_5.io.out_uop.xcpt_pf_if
connect issue_slots[5].out_uop.fp_single, slots_5.io.out_uop.fp_single
connect issue_slots[5].out_uop.fp_val, slots_5.io.out_uop.fp_val
connect issue_slots[5].out_uop.frs3_en, slots_5.io.out_uop.frs3_en
connect issue_slots[5].out_uop.lrs2_rtype, slots_5.io.out_uop.lrs2_rtype
connect issue_slots[5].out_uop.lrs1_rtype, slots_5.io.out_uop.lrs1_rtype
connect issue_slots[5].out_uop.dst_rtype, slots_5.io.out_uop.dst_rtype
connect issue_slots[5].out_uop.ldst_val, slots_5.io.out_uop.ldst_val
connect issue_slots[5].out_uop.lrs3, slots_5.io.out_uop.lrs3
connect issue_slots[5].out_uop.lrs2, slots_5.io.out_uop.lrs2
connect issue_slots[5].out_uop.lrs1, slots_5.io.out_uop.lrs1
connect issue_slots[5].out_uop.ldst, slots_5.io.out_uop.ldst
connect issue_slots[5].out_uop.ldst_is_rs1, slots_5.io.out_uop.ldst_is_rs1
connect issue_slots[5].out_uop.flush_on_commit, slots_5.io.out_uop.flush_on_commit
connect issue_slots[5].out_uop.is_unique, slots_5.io.out_uop.is_unique
connect issue_slots[5].out_uop.is_sys_pc2epc, slots_5.io.out_uop.is_sys_pc2epc
connect issue_slots[5].out_uop.uses_stq, slots_5.io.out_uop.uses_stq
connect issue_slots[5].out_uop.uses_ldq, slots_5.io.out_uop.uses_ldq
connect issue_slots[5].out_uop.is_amo, slots_5.io.out_uop.is_amo
connect issue_slots[5].out_uop.is_fencei, slots_5.io.out_uop.is_fencei
connect issue_slots[5].out_uop.is_fence, slots_5.io.out_uop.is_fence
connect issue_slots[5].out_uop.mem_signed, slots_5.io.out_uop.mem_signed
connect issue_slots[5].out_uop.mem_size, slots_5.io.out_uop.mem_size
connect issue_slots[5].out_uop.mem_cmd, slots_5.io.out_uop.mem_cmd
connect issue_slots[5].out_uop.bypassable, slots_5.io.out_uop.bypassable
connect issue_slots[5].out_uop.exc_cause, slots_5.io.out_uop.exc_cause
connect issue_slots[5].out_uop.exception, slots_5.io.out_uop.exception
connect issue_slots[5].out_uop.stale_pdst, slots_5.io.out_uop.stale_pdst
connect issue_slots[5].out_uop.ppred_busy, slots_5.io.out_uop.ppred_busy
connect issue_slots[5].out_uop.prs3_busy, slots_5.io.out_uop.prs3_busy
connect issue_slots[5].out_uop.prs2_busy, slots_5.io.out_uop.prs2_busy
connect issue_slots[5].out_uop.prs1_busy, slots_5.io.out_uop.prs1_busy
connect issue_slots[5].out_uop.ppred, slots_5.io.out_uop.ppred
connect issue_slots[5].out_uop.prs3, slots_5.io.out_uop.prs3
connect issue_slots[5].out_uop.prs2, slots_5.io.out_uop.prs2
connect issue_slots[5].out_uop.prs1, slots_5.io.out_uop.prs1
connect issue_slots[5].out_uop.pdst, slots_5.io.out_uop.pdst
connect issue_slots[5].out_uop.rxq_idx, slots_5.io.out_uop.rxq_idx
connect issue_slots[5].out_uop.stq_idx, slots_5.io.out_uop.stq_idx
connect issue_slots[5].out_uop.ldq_idx, slots_5.io.out_uop.ldq_idx
connect issue_slots[5].out_uop.rob_idx, slots_5.io.out_uop.rob_idx
connect issue_slots[5].out_uop.csr_addr, slots_5.io.out_uop.csr_addr
connect issue_slots[5].out_uop.imm_packed, slots_5.io.out_uop.imm_packed
connect issue_slots[5].out_uop.taken, slots_5.io.out_uop.taken
connect issue_slots[5].out_uop.pc_lob, slots_5.io.out_uop.pc_lob
connect issue_slots[5].out_uop.edge_inst, slots_5.io.out_uop.edge_inst
connect issue_slots[5].out_uop.ftq_idx, slots_5.io.out_uop.ftq_idx
connect issue_slots[5].out_uop.br_tag, slots_5.io.out_uop.br_tag
connect issue_slots[5].out_uop.br_mask, slots_5.io.out_uop.br_mask
connect issue_slots[5].out_uop.is_sfb, slots_5.io.out_uop.is_sfb
connect issue_slots[5].out_uop.is_jal, slots_5.io.out_uop.is_jal
connect issue_slots[5].out_uop.is_jalr, slots_5.io.out_uop.is_jalr
connect issue_slots[5].out_uop.is_br, slots_5.io.out_uop.is_br
connect issue_slots[5].out_uop.iw_p2_poisoned, slots_5.io.out_uop.iw_p2_poisoned
connect issue_slots[5].out_uop.iw_p1_poisoned, slots_5.io.out_uop.iw_p1_poisoned
connect issue_slots[5].out_uop.iw_state, slots_5.io.out_uop.iw_state
connect issue_slots[5].out_uop.ctrl.is_std, slots_5.io.out_uop.ctrl.is_std
connect issue_slots[5].out_uop.ctrl.is_sta, slots_5.io.out_uop.ctrl.is_sta
connect issue_slots[5].out_uop.ctrl.is_load, slots_5.io.out_uop.ctrl.is_load
connect issue_slots[5].out_uop.ctrl.csr_cmd, slots_5.io.out_uop.ctrl.csr_cmd
connect issue_slots[5].out_uop.ctrl.fcn_dw, slots_5.io.out_uop.ctrl.fcn_dw
connect issue_slots[5].out_uop.ctrl.op_fcn, slots_5.io.out_uop.ctrl.op_fcn
connect issue_slots[5].out_uop.ctrl.imm_sel, slots_5.io.out_uop.ctrl.imm_sel
connect issue_slots[5].out_uop.ctrl.op2_sel, slots_5.io.out_uop.ctrl.op2_sel
connect issue_slots[5].out_uop.ctrl.op1_sel, slots_5.io.out_uop.ctrl.op1_sel
connect issue_slots[5].out_uop.ctrl.br_type, slots_5.io.out_uop.ctrl.br_type
connect issue_slots[5].out_uop.fu_code, slots_5.io.out_uop.fu_code
connect issue_slots[5].out_uop.iq_type, slots_5.io.out_uop.iq_type
connect issue_slots[5].out_uop.debug_pc, slots_5.io.out_uop.debug_pc
connect issue_slots[5].out_uop.is_rvc, slots_5.io.out_uop.is_rvc
connect issue_slots[5].out_uop.debug_inst, slots_5.io.out_uop.debug_inst
connect issue_slots[5].out_uop.inst, slots_5.io.out_uop.inst
connect issue_slots[5].out_uop.uopc, slots_5.io.out_uop.uopc
connect slots_5.io.in_uop.bits.debug_tsrc, issue_slots[5].in_uop.bits.debug_tsrc
connect slots_5.io.in_uop.bits.debug_fsrc, issue_slots[5].in_uop.bits.debug_fsrc
connect slots_5.io.in_uop.bits.bp_xcpt_if, issue_slots[5].in_uop.bits.bp_xcpt_if
connect slots_5.io.in_uop.bits.bp_debug_if, issue_slots[5].in_uop.bits.bp_debug_if
connect slots_5.io.in_uop.bits.xcpt_ma_if, issue_slots[5].in_uop.bits.xcpt_ma_if
connect slots_5.io.in_uop.bits.xcpt_ae_if, issue_slots[5].in_uop.bits.xcpt_ae_if
connect slots_5.io.in_uop.bits.xcpt_pf_if, issue_slots[5].in_uop.bits.xcpt_pf_if
connect slots_5.io.in_uop.bits.fp_single, issue_slots[5].in_uop.bits.fp_single
connect slots_5.io.in_uop.bits.fp_val, issue_slots[5].in_uop.bits.fp_val
connect slots_5.io.in_uop.bits.frs3_en, issue_slots[5].in_uop.bits.frs3_en
connect slots_5.io.in_uop.bits.lrs2_rtype, issue_slots[5].in_uop.bits.lrs2_rtype
connect slots_5.io.in_uop.bits.lrs1_rtype, issue_slots[5].in_uop.bits.lrs1_rtype
connect slots_5.io.in_uop.bits.dst_rtype, issue_slots[5].in_uop.bits.dst_rtype
connect slots_5.io.in_uop.bits.ldst_val, issue_slots[5].in_uop.bits.ldst_val
connect slots_5.io.in_uop.bits.lrs3, issue_slots[5].in_uop.bits.lrs3
connect slots_5.io.in_uop.bits.lrs2, issue_slots[5].in_uop.bits.lrs2
connect slots_5.io.in_uop.bits.lrs1, issue_slots[5].in_uop.bits.lrs1
connect slots_5.io.in_uop.bits.ldst, issue_slots[5].in_uop.bits.ldst
connect slots_5.io.in_uop.bits.ldst_is_rs1, issue_slots[5].in_uop.bits.ldst_is_rs1
connect slots_5.io.in_uop.bits.flush_on_commit, issue_slots[5].in_uop.bits.flush_on_commit
connect slots_5.io.in_uop.bits.is_unique, issue_slots[5].in_uop.bits.is_unique
connect slots_5.io.in_uop.bits.is_sys_pc2epc, issue_slots[5].in_uop.bits.is_sys_pc2epc
connect slots_5.io.in_uop.bits.uses_stq, issue_slots[5].in_uop.bits.uses_stq
connect slots_5.io.in_uop.bits.uses_ldq, issue_slots[5].in_uop.bits.uses_ldq
connect slots_5.io.in_uop.bits.is_amo, issue_slots[5].in_uop.bits.is_amo
connect slots_5.io.in_uop.bits.is_fencei, issue_slots[5].in_uop.bits.is_fencei
connect slots_5.io.in_uop.bits.is_fence, issue_slots[5].in_uop.bits.is_fence
connect slots_5.io.in_uop.bits.mem_signed, issue_slots[5].in_uop.bits.mem_signed
connect slots_5.io.in_uop.bits.mem_size, issue_slots[5].in_uop.bits.mem_size
connect slots_5.io.in_uop.bits.mem_cmd, issue_slots[5].in_uop.bits.mem_cmd
connect slots_5.io.in_uop.bits.bypassable, issue_slots[5].in_uop.bits.bypassable
connect slots_5.io.in_uop.bits.exc_cause, issue_slots[5].in_uop.bits.exc_cause
connect slots_5.io.in_uop.bits.exception, issue_slots[5].in_uop.bits.exception
connect slots_5.io.in_uop.bits.stale_pdst, issue_slots[5].in_uop.bits.stale_pdst
connect slots_5.io.in_uop.bits.ppred_busy, issue_slots[5].in_uop.bits.ppred_busy
connect slots_5.io.in_uop.bits.prs3_busy, issue_slots[5].in_uop.bits.prs3_busy
connect slots_5.io.in_uop.bits.prs2_busy, issue_slots[5].in_uop.bits.prs2_busy
connect slots_5.io.in_uop.bits.prs1_busy, issue_slots[5].in_uop.bits.prs1_busy
connect slots_5.io.in_uop.bits.ppred, issue_slots[5].in_uop.bits.ppred
connect slots_5.io.in_uop.bits.prs3, issue_slots[5].in_uop.bits.prs3
connect slots_5.io.in_uop.bits.prs2, issue_slots[5].in_uop.bits.prs2
connect slots_5.io.in_uop.bits.prs1, issue_slots[5].in_uop.bits.prs1
connect slots_5.io.in_uop.bits.pdst, issue_slots[5].in_uop.bits.pdst
connect slots_5.io.in_uop.bits.rxq_idx, issue_slots[5].in_uop.bits.rxq_idx
connect slots_5.io.in_uop.bits.stq_idx, issue_slots[5].in_uop.bits.stq_idx
connect slots_5.io.in_uop.bits.ldq_idx, issue_slots[5].in_uop.bits.ldq_idx
connect slots_5.io.in_uop.bits.rob_idx, issue_slots[5].in_uop.bits.rob_idx
connect slots_5.io.in_uop.bits.csr_addr, issue_slots[5].in_uop.bits.csr_addr
connect slots_5.io.in_uop.bits.imm_packed, issue_slots[5].in_uop.bits.imm_packed
connect slots_5.io.in_uop.bits.taken, issue_slots[5].in_uop.bits.taken
connect slots_5.io.in_uop.bits.pc_lob, issue_slots[5].in_uop.bits.pc_lob
connect slots_5.io.in_uop.bits.edge_inst, issue_slots[5].in_uop.bits.edge_inst
connect slots_5.io.in_uop.bits.ftq_idx, issue_slots[5].in_uop.bits.ftq_idx
connect slots_5.io.in_uop.bits.br_tag, issue_slots[5].in_uop.bits.br_tag
connect slots_5.io.in_uop.bits.br_mask, issue_slots[5].in_uop.bits.br_mask
connect slots_5.io.in_uop.bits.is_sfb, issue_slots[5].in_uop.bits.is_sfb
connect slots_5.io.in_uop.bits.is_jal, issue_slots[5].in_uop.bits.is_jal
connect slots_5.io.in_uop.bits.is_jalr, issue_slots[5].in_uop.bits.is_jalr
connect slots_5.io.in_uop.bits.is_br, issue_slots[5].in_uop.bits.is_br
connect slots_5.io.in_uop.bits.iw_p2_poisoned, issue_slots[5].in_uop.bits.iw_p2_poisoned
connect slots_5.io.in_uop.bits.iw_p1_poisoned, issue_slots[5].in_uop.bits.iw_p1_poisoned
connect slots_5.io.in_uop.bits.iw_state, issue_slots[5].in_uop.bits.iw_state
connect slots_5.io.in_uop.bits.ctrl.is_std, issue_slots[5].in_uop.bits.ctrl.is_std
connect slots_5.io.in_uop.bits.ctrl.is_sta, issue_slots[5].in_uop.bits.ctrl.is_sta
connect slots_5.io.in_uop.bits.ctrl.is_load, issue_slots[5].in_uop.bits.ctrl.is_load
connect slots_5.io.in_uop.bits.ctrl.csr_cmd, issue_slots[5].in_uop.bits.ctrl.csr_cmd
connect slots_5.io.in_uop.bits.ctrl.fcn_dw, issue_slots[5].in_uop.bits.ctrl.fcn_dw
connect slots_5.io.in_uop.bits.ctrl.op_fcn, issue_slots[5].in_uop.bits.ctrl.op_fcn
connect slots_5.io.in_uop.bits.ctrl.imm_sel, issue_slots[5].in_uop.bits.ctrl.imm_sel
connect slots_5.io.in_uop.bits.ctrl.op2_sel, issue_slots[5].in_uop.bits.ctrl.op2_sel
connect slots_5.io.in_uop.bits.ctrl.op1_sel, issue_slots[5].in_uop.bits.ctrl.op1_sel
connect slots_5.io.in_uop.bits.ctrl.br_type, issue_slots[5].in_uop.bits.ctrl.br_type
connect slots_5.io.in_uop.bits.fu_code, issue_slots[5].in_uop.bits.fu_code
connect slots_5.io.in_uop.bits.iq_type, issue_slots[5].in_uop.bits.iq_type
connect slots_5.io.in_uop.bits.debug_pc, issue_slots[5].in_uop.bits.debug_pc
connect slots_5.io.in_uop.bits.is_rvc, issue_slots[5].in_uop.bits.is_rvc
connect slots_5.io.in_uop.bits.debug_inst, issue_slots[5].in_uop.bits.debug_inst
connect slots_5.io.in_uop.bits.inst, issue_slots[5].in_uop.bits.inst
connect slots_5.io.in_uop.bits.uopc, issue_slots[5].in_uop.bits.uopc
connect slots_5.io.in_uop.valid, issue_slots[5].in_uop.valid
connect slots_5.io.spec_ld_wakeup[0].bits, issue_slots[5].spec_ld_wakeup[0].bits
connect slots_5.io.spec_ld_wakeup[0].valid, issue_slots[5].spec_ld_wakeup[0].valid
connect slots_5.io.pred_wakeup_port.bits, issue_slots[5].pred_wakeup_port.bits
connect slots_5.io.pred_wakeup_port.valid, issue_slots[5].pred_wakeup_port.valid
connect slots_5.io.wakeup_ports[0].bits.poisoned, issue_slots[5].wakeup_ports[0].bits.poisoned
connect slots_5.io.wakeup_ports[0].bits.pdst, issue_slots[5].wakeup_ports[0].bits.pdst
connect slots_5.io.wakeup_ports[0].valid, issue_slots[5].wakeup_ports[0].valid
connect slots_5.io.wakeup_ports[1].bits.poisoned, issue_slots[5].wakeup_ports[1].bits.poisoned
connect slots_5.io.wakeup_ports[1].bits.pdst, issue_slots[5].wakeup_ports[1].bits.pdst
connect slots_5.io.wakeup_ports[1].valid, issue_slots[5].wakeup_ports[1].valid
connect slots_5.io.wakeup_ports[2].bits.poisoned, issue_slots[5].wakeup_ports[2].bits.poisoned
connect slots_5.io.wakeup_ports[2].bits.pdst, issue_slots[5].wakeup_ports[2].bits.pdst
connect slots_5.io.wakeup_ports[2].valid, issue_slots[5].wakeup_ports[2].valid
connect slots_5.io.ldspec_miss, issue_slots[5].ldspec_miss
connect slots_5.io.clear, issue_slots[5].clear
connect slots_5.io.kill, issue_slots[5].kill
connect slots_5.io.brupdate.b2.target_offset, issue_slots[5].brupdate.b2.target_offset
connect slots_5.io.brupdate.b2.jalr_target, issue_slots[5].brupdate.b2.jalr_target
connect slots_5.io.brupdate.b2.pc_sel, issue_slots[5].brupdate.b2.pc_sel
connect slots_5.io.brupdate.b2.cfi_type, issue_slots[5].brupdate.b2.cfi_type
connect slots_5.io.brupdate.b2.taken, issue_slots[5].brupdate.b2.taken
connect slots_5.io.brupdate.b2.mispredict, issue_slots[5].brupdate.b2.mispredict
connect slots_5.io.brupdate.b2.valid, issue_slots[5].brupdate.b2.valid
connect slots_5.io.brupdate.b2.uop.debug_tsrc, issue_slots[5].brupdate.b2.uop.debug_tsrc
connect slots_5.io.brupdate.b2.uop.debug_fsrc, issue_slots[5].brupdate.b2.uop.debug_fsrc
connect slots_5.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[5].brupdate.b2.uop.bp_xcpt_if
connect slots_5.io.brupdate.b2.uop.bp_debug_if, issue_slots[5].brupdate.b2.uop.bp_debug_if
connect slots_5.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[5].brupdate.b2.uop.xcpt_ma_if
connect slots_5.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[5].brupdate.b2.uop.xcpt_ae_if
connect slots_5.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[5].brupdate.b2.uop.xcpt_pf_if
connect slots_5.io.brupdate.b2.uop.fp_single, issue_slots[5].brupdate.b2.uop.fp_single
connect slots_5.io.brupdate.b2.uop.fp_val, issue_slots[5].brupdate.b2.uop.fp_val
connect slots_5.io.brupdate.b2.uop.frs3_en, issue_slots[5].brupdate.b2.uop.frs3_en
connect slots_5.io.brupdate.b2.uop.lrs2_rtype, issue_slots[5].brupdate.b2.uop.lrs2_rtype
connect slots_5.io.brupdate.b2.uop.lrs1_rtype, issue_slots[5].brupdate.b2.uop.lrs1_rtype
connect slots_5.io.brupdate.b2.uop.dst_rtype, issue_slots[5].brupdate.b2.uop.dst_rtype
connect slots_5.io.brupdate.b2.uop.ldst_val, issue_slots[5].brupdate.b2.uop.ldst_val
connect slots_5.io.brupdate.b2.uop.lrs3, issue_slots[5].brupdate.b2.uop.lrs3
connect slots_5.io.brupdate.b2.uop.lrs2, issue_slots[5].brupdate.b2.uop.lrs2
connect slots_5.io.brupdate.b2.uop.lrs1, issue_slots[5].brupdate.b2.uop.lrs1
connect slots_5.io.brupdate.b2.uop.ldst, issue_slots[5].brupdate.b2.uop.ldst
connect slots_5.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[5].brupdate.b2.uop.ldst_is_rs1
connect slots_5.io.brupdate.b2.uop.flush_on_commit, issue_slots[5].brupdate.b2.uop.flush_on_commit
connect slots_5.io.brupdate.b2.uop.is_unique, issue_slots[5].brupdate.b2.uop.is_unique
connect slots_5.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[5].brupdate.b2.uop.is_sys_pc2epc
connect slots_5.io.brupdate.b2.uop.uses_stq, issue_slots[5].brupdate.b2.uop.uses_stq
connect slots_5.io.brupdate.b2.uop.uses_ldq, issue_slots[5].brupdate.b2.uop.uses_ldq
connect slots_5.io.brupdate.b2.uop.is_amo, issue_slots[5].brupdate.b2.uop.is_amo
connect slots_5.io.brupdate.b2.uop.is_fencei, issue_slots[5].brupdate.b2.uop.is_fencei
connect slots_5.io.brupdate.b2.uop.is_fence, issue_slots[5].brupdate.b2.uop.is_fence
connect slots_5.io.brupdate.b2.uop.mem_signed, issue_slots[5].brupdate.b2.uop.mem_signed
connect slots_5.io.brupdate.b2.uop.mem_size, issue_slots[5].brupdate.b2.uop.mem_size
connect slots_5.io.brupdate.b2.uop.mem_cmd, issue_slots[5].brupdate.b2.uop.mem_cmd
connect slots_5.io.brupdate.b2.uop.bypassable, issue_slots[5].brupdate.b2.uop.bypassable
connect slots_5.io.brupdate.b2.uop.exc_cause, issue_slots[5].brupdate.b2.uop.exc_cause
connect slots_5.io.brupdate.b2.uop.exception, issue_slots[5].brupdate.b2.uop.exception
connect slots_5.io.brupdate.b2.uop.stale_pdst, issue_slots[5].brupdate.b2.uop.stale_pdst
connect slots_5.io.brupdate.b2.uop.ppred_busy, issue_slots[5].brupdate.b2.uop.ppred_busy
connect slots_5.io.brupdate.b2.uop.prs3_busy, issue_slots[5].brupdate.b2.uop.prs3_busy
connect slots_5.io.brupdate.b2.uop.prs2_busy, issue_slots[5].brupdate.b2.uop.prs2_busy
connect slots_5.io.brupdate.b2.uop.prs1_busy, issue_slots[5].brupdate.b2.uop.prs1_busy
connect slots_5.io.brupdate.b2.uop.ppred, issue_slots[5].brupdate.b2.uop.ppred
connect slots_5.io.brupdate.b2.uop.prs3, issue_slots[5].brupdate.b2.uop.prs3
connect slots_5.io.brupdate.b2.uop.prs2, issue_slots[5].brupdate.b2.uop.prs2
connect slots_5.io.brupdate.b2.uop.prs1, issue_slots[5].brupdate.b2.uop.prs1
connect slots_5.io.brupdate.b2.uop.pdst, issue_slots[5].brupdate.b2.uop.pdst
connect slots_5.io.brupdate.b2.uop.rxq_idx, issue_slots[5].brupdate.b2.uop.rxq_idx
connect slots_5.io.brupdate.b2.uop.stq_idx, issue_slots[5].brupdate.b2.uop.stq_idx
connect slots_5.io.brupdate.b2.uop.ldq_idx, issue_slots[5].brupdate.b2.uop.ldq_idx
connect slots_5.io.brupdate.b2.uop.rob_idx, issue_slots[5].brupdate.b2.uop.rob_idx
connect slots_5.io.brupdate.b2.uop.csr_addr, issue_slots[5].brupdate.b2.uop.csr_addr
connect slots_5.io.brupdate.b2.uop.imm_packed, issue_slots[5].brupdate.b2.uop.imm_packed
connect slots_5.io.brupdate.b2.uop.taken, issue_slots[5].brupdate.b2.uop.taken
connect slots_5.io.brupdate.b2.uop.pc_lob, issue_slots[5].brupdate.b2.uop.pc_lob
connect slots_5.io.brupdate.b2.uop.edge_inst, issue_slots[5].brupdate.b2.uop.edge_inst
connect slots_5.io.brupdate.b2.uop.ftq_idx, issue_slots[5].brupdate.b2.uop.ftq_idx
connect slots_5.io.brupdate.b2.uop.br_tag, issue_slots[5].brupdate.b2.uop.br_tag
connect slots_5.io.brupdate.b2.uop.br_mask, issue_slots[5].brupdate.b2.uop.br_mask
connect slots_5.io.brupdate.b2.uop.is_sfb, issue_slots[5].brupdate.b2.uop.is_sfb
connect slots_5.io.brupdate.b2.uop.is_jal, issue_slots[5].brupdate.b2.uop.is_jal
connect slots_5.io.brupdate.b2.uop.is_jalr, issue_slots[5].brupdate.b2.uop.is_jalr
connect slots_5.io.brupdate.b2.uop.is_br, issue_slots[5].brupdate.b2.uop.is_br
connect slots_5.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[5].brupdate.b2.uop.iw_p2_poisoned
connect slots_5.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[5].brupdate.b2.uop.iw_p1_poisoned
connect slots_5.io.brupdate.b2.uop.iw_state, issue_slots[5].brupdate.b2.uop.iw_state
connect slots_5.io.brupdate.b2.uop.ctrl.is_std, issue_slots[5].brupdate.b2.uop.ctrl.is_std
connect slots_5.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[5].brupdate.b2.uop.ctrl.is_sta
connect slots_5.io.brupdate.b2.uop.ctrl.is_load, issue_slots[5].brupdate.b2.uop.ctrl.is_load
connect slots_5.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[5].brupdate.b2.uop.ctrl.csr_cmd
connect slots_5.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[5].brupdate.b2.uop.ctrl.fcn_dw
connect slots_5.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[5].brupdate.b2.uop.ctrl.op_fcn
connect slots_5.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[5].brupdate.b2.uop.ctrl.imm_sel
connect slots_5.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[5].brupdate.b2.uop.ctrl.op2_sel
connect slots_5.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[5].brupdate.b2.uop.ctrl.op1_sel
connect slots_5.io.brupdate.b2.uop.ctrl.br_type, issue_slots[5].brupdate.b2.uop.ctrl.br_type
connect slots_5.io.brupdate.b2.uop.fu_code, issue_slots[5].brupdate.b2.uop.fu_code
connect slots_5.io.brupdate.b2.uop.iq_type, issue_slots[5].brupdate.b2.uop.iq_type
connect slots_5.io.brupdate.b2.uop.debug_pc, issue_slots[5].brupdate.b2.uop.debug_pc
connect slots_5.io.brupdate.b2.uop.is_rvc, issue_slots[5].brupdate.b2.uop.is_rvc
connect slots_5.io.brupdate.b2.uop.debug_inst, issue_slots[5].brupdate.b2.uop.debug_inst
connect slots_5.io.brupdate.b2.uop.inst, issue_slots[5].brupdate.b2.uop.inst
connect slots_5.io.brupdate.b2.uop.uopc, issue_slots[5].brupdate.b2.uop.uopc
connect slots_5.io.brupdate.b1.mispredict_mask, issue_slots[5].brupdate.b1.mispredict_mask
connect slots_5.io.brupdate.b1.resolve_mask, issue_slots[5].brupdate.b1.resolve_mask
connect slots_5.io.grant, issue_slots[5].grant
connect issue_slots[5].request_hp, slots_5.io.request_hp
connect issue_slots[5].request, slots_5.io.request
connect issue_slots[5].will_be_valid, slots_5.io.will_be_valid
connect issue_slots[5].valid, slots_5.io.valid
connect issue_slots[6].debug.state, slots_6.io.debug.state
connect issue_slots[6].debug.ppred, slots_6.io.debug.ppred
connect issue_slots[6].debug.p3, slots_6.io.debug.p3
connect issue_slots[6].debug.p2, slots_6.io.debug.p2
connect issue_slots[6].debug.p1, slots_6.io.debug.p1
connect issue_slots[6].uop.debug_tsrc, slots_6.io.uop.debug_tsrc
connect issue_slots[6].uop.debug_fsrc, slots_6.io.uop.debug_fsrc
connect issue_slots[6].uop.bp_xcpt_if, slots_6.io.uop.bp_xcpt_if
connect issue_slots[6].uop.bp_debug_if, slots_6.io.uop.bp_debug_if
connect issue_slots[6].uop.xcpt_ma_if, slots_6.io.uop.xcpt_ma_if
connect issue_slots[6].uop.xcpt_ae_if, slots_6.io.uop.xcpt_ae_if
connect issue_slots[6].uop.xcpt_pf_if, slots_6.io.uop.xcpt_pf_if
connect issue_slots[6].uop.fp_single, slots_6.io.uop.fp_single
connect issue_slots[6].uop.fp_val, slots_6.io.uop.fp_val
connect issue_slots[6].uop.frs3_en, slots_6.io.uop.frs3_en
connect issue_slots[6].uop.lrs2_rtype, slots_6.io.uop.lrs2_rtype
connect issue_slots[6].uop.lrs1_rtype, slots_6.io.uop.lrs1_rtype
connect issue_slots[6].uop.dst_rtype, slots_6.io.uop.dst_rtype
connect issue_slots[6].uop.ldst_val, slots_6.io.uop.ldst_val
connect issue_slots[6].uop.lrs3, slots_6.io.uop.lrs3
connect issue_slots[6].uop.lrs2, slots_6.io.uop.lrs2
connect issue_slots[6].uop.lrs1, slots_6.io.uop.lrs1
connect issue_slots[6].uop.ldst, slots_6.io.uop.ldst
connect issue_slots[6].uop.ldst_is_rs1, slots_6.io.uop.ldst_is_rs1
connect issue_slots[6].uop.flush_on_commit, slots_6.io.uop.flush_on_commit
connect issue_slots[6].uop.is_unique, slots_6.io.uop.is_unique
connect issue_slots[6].uop.is_sys_pc2epc, slots_6.io.uop.is_sys_pc2epc
connect issue_slots[6].uop.uses_stq, slots_6.io.uop.uses_stq
connect issue_slots[6].uop.uses_ldq, slots_6.io.uop.uses_ldq
connect issue_slots[6].uop.is_amo, slots_6.io.uop.is_amo
connect issue_slots[6].uop.is_fencei, slots_6.io.uop.is_fencei
connect issue_slots[6].uop.is_fence, slots_6.io.uop.is_fence
connect issue_slots[6].uop.mem_signed, slots_6.io.uop.mem_signed
connect issue_slots[6].uop.mem_size, slots_6.io.uop.mem_size
connect issue_slots[6].uop.mem_cmd, slots_6.io.uop.mem_cmd
connect issue_slots[6].uop.bypassable, slots_6.io.uop.bypassable
connect issue_slots[6].uop.exc_cause, slots_6.io.uop.exc_cause
connect issue_slots[6].uop.exception, slots_6.io.uop.exception
connect issue_slots[6].uop.stale_pdst, slots_6.io.uop.stale_pdst
connect issue_slots[6].uop.ppred_busy, slots_6.io.uop.ppred_busy
connect issue_slots[6].uop.prs3_busy, slots_6.io.uop.prs3_busy
connect issue_slots[6].uop.prs2_busy, slots_6.io.uop.prs2_busy
connect issue_slots[6].uop.prs1_busy, slots_6.io.uop.prs1_busy
connect issue_slots[6].uop.ppred, slots_6.io.uop.ppred
connect issue_slots[6].uop.prs3, slots_6.io.uop.prs3
connect issue_slots[6].uop.prs2, slots_6.io.uop.prs2
connect issue_slots[6].uop.prs1, slots_6.io.uop.prs1
connect issue_slots[6].uop.pdst, slots_6.io.uop.pdst
connect issue_slots[6].uop.rxq_idx, slots_6.io.uop.rxq_idx
connect issue_slots[6].uop.stq_idx, slots_6.io.uop.stq_idx
connect issue_slots[6].uop.ldq_idx, slots_6.io.uop.ldq_idx
connect issue_slots[6].uop.rob_idx, slots_6.io.uop.rob_idx
connect issue_slots[6].uop.csr_addr, slots_6.io.uop.csr_addr
connect issue_slots[6].uop.imm_packed, slots_6.io.uop.imm_packed
connect issue_slots[6].uop.taken, slots_6.io.uop.taken
connect issue_slots[6].uop.pc_lob, slots_6.io.uop.pc_lob
connect issue_slots[6].uop.edge_inst, slots_6.io.uop.edge_inst
connect issue_slots[6].uop.ftq_idx, slots_6.io.uop.ftq_idx
connect issue_slots[6].uop.br_tag, slots_6.io.uop.br_tag
connect issue_slots[6].uop.br_mask, slots_6.io.uop.br_mask
connect issue_slots[6].uop.is_sfb, slots_6.io.uop.is_sfb
connect issue_slots[6].uop.is_jal, slots_6.io.uop.is_jal
connect issue_slots[6].uop.is_jalr, slots_6.io.uop.is_jalr
connect issue_slots[6].uop.is_br, slots_6.io.uop.is_br
connect issue_slots[6].uop.iw_p2_poisoned, slots_6.io.uop.iw_p2_poisoned
connect issue_slots[6].uop.iw_p1_poisoned, slots_6.io.uop.iw_p1_poisoned
connect issue_slots[6].uop.iw_state, slots_6.io.uop.iw_state
connect issue_slots[6].uop.ctrl.is_std, slots_6.io.uop.ctrl.is_std
connect issue_slots[6].uop.ctrl.is_sta, slots_6.io.uop.ctrl.is_sta
connect issue_slots[6].uop.ctrl.is_load, slots_6.io.uop.ctrl.is_load
connect issue_slots[6].uop.ctrl.csr_cmd, slots_6.io.uop.ctrl.csr_cmd
connect issue_slots[6].uop.ctrl.fcn_dw, slots_6.io.uop.ctrl.fcn_dw
connect issue_slots[6].uop.ctrl.op_fcn, slots_6.io.uop.ctrl.op_fcn
connect issue_slots[6].uop.ctrl.imm_sel, slots_6.io.uop.ctrl.imm_sel
connect issue_slots[6].uop.ctrl.op2_sel, slots_6.io.uop.ctrl.op2_sel
connect issue_slots[6].uop.ctrl.op1_sel, slots_6.io.uop.ctrl.op1_sel
connect issue_slots[6].uop.ctrl.br_type, slots_6.io.uop.ctrl.br_type
connect issue_slots[6].uop.fu_code, slots_6.io.uop.fu_code
connect issue_slots[6].uop.iq_type, slots_6.io.uop.iq_type
connect issue_slots[6].uop.debug_pc, slots_6.io.uop.debug_pc
connect issue_slots[6].uop.is_rvc, slots_6.io.uop.is_rvc
connect issue_slots[6].uop.debug_inst, slots_6.io.uop.debug_inst
connect issue_slots[6].uop.inst, slots_6.io.uop.inst
connect issue_slots[6].uop.uopc, slots_6.io.uop.uopc
connect issue_slots[6].out_uop.debug_tsrc, slots_6.io.out_uop.debug_tsrc
connect issue_slots[6].out_uop.debug_fsrc, slots_6.io.out_uop.debug_fsrc
connect issue_slots[6].out_uop.bp_xcpt_if, slots_6.io.out_uop.bp_xcpt_if
connect issue_slots[6].out_uop.bp_debug_if, slots_6.io.out_uop.bp_debug_if
connect issue_slots[6].out_uop.xcpt_ma_if, slots_6.io.out_uop.xcpt_ma_if
connect issue_slots[6].out_uop.xcpt_ae_if, slots_6.io.out_uop.xcpt_ae_if
connect issue_slots[6].out_uop.xcpt_pf_if, slots_6.io.out_uop.xcpt_pf_if
connect issue_slots[6].out_uop.fp_single, slots_6.io.out_uop.fp_single
connect issue_slots[6].out_uop.fp_val, slots_6.io.out_uop.fp_val
connect issue_slots[6].out_uop.frs3_en, slots_6.io.out_uop.frs3_en
connect issue_slots[6].out_uop.lrs2_rtype, slots_6.io.out_uop.lrs2_rtype
connect issue_slots[6].out_uop.lrs1_rtype, slots_6.io.out_uop.lrs1_rtype
connect issue_slots[6].out_uop.dst_rtype, slots_6.io.out_uop.dst_rtype
connect issue_slots[6].out_uop.ldst_val, slots_6.io.out_uop.ldst_val
connect issue_slots[6].out_uop.lrs3, slots_6.io.out_uop.lrs3
connect issue_slots[6].out_uop.lrs2, slots_6.io.out_uop.lrs2
connect issue_slots[6].out_uop.lrs1, slots_6.io.out_uop.lrs1
connect issue_slots[6].out_uop.ldst, slots_6.io.out_uop.ldst
connect issue_slots[6].out_uop.ldst_is_rs1, slots_6.io.out_uop.ldst_is_rs1
connect issue_slots[6].out_uop.flush_on_commit, slots_6.io.out_uop.flush_on_commit
connect issue_slots[6].out_uop.is_unique, slots_6.io.out_uop.is_unique
connect issue_slots[6].out_uop.is_sys_pc2epc, slots_6.io.out_uop.is_sys_pc2epc
connect issue_slots[6].out_uop.uses_stq, slots_6.io.out_uop.uses_stq
connect issue_slots[6].out_uop.uses_ldq, slots_6.io.out_uop.uses_ldq
connect issue_slots[6].out_uop.is_amo, slots_6.io.out_uop.is_amo
connect issue_slots[6].out_uop.is_fencei, slots_6.io.out_uop.is_fencei
connect issue_slots[6].out_uop.is_fence, slots_6.io.out_uop.is_fence
connect issue_slots[6].out_uop.mem_signed, slots_6.io.out_uop.mem_signed
connect issue_slots[6].out_uop.mem_size, slots_6.io.out_uop.mem_size
connect issue_slots[6].out_uop.mem_cmd, slots_6.io.out_uop.mem_cmd
connect issue_slots[6].out_uop.bypassable, slots_6.io.out_uop.bypassable
connect issue_slots[6].out_uop.exc_cause, slots_6.io.out_uop.exc_cause
connect issue_slots[6].out_uop.exception, slots_6.io.out_uop.exception
connect issue_slots[6].out_uop.stale_pdst, slots_6.io.out_uop.stale_pdst
connect issue_slots[6].out_uop.ppred_busy, slots_6.io.out_uop.ppred_busy
connect issue_slots[6].out_uop.prs3_busy, slots_6.io.out_uop.prs3_busy
connect issue_slots[6].out_uop.prs2_busy, slots_6.io.out_uop.prs2_busy
connect issue_slots[6].out_uop.prs1_busy, slots_6.io.out_uop.prs1_busy
connect issue_slots[6].out_uop.ppred, slots_6.io.out_uop.ppred
connect issue_slots[6].out_uop.prs3, slots_6.io.out_uop.prs3
connect issue_slots[6].out_uop.prs2, slots_6.io.out_uop.prs2
connect issue_slots[6].out_uop.prs1, slots_6.io.out_uop.prs1
connect issue_slots[6].out_uop.pdst, slots_6.io.out_uop.pdst
connect issue_slots[6].out_uop.rxq_idx, slots_6.io.out_uop.rxq_idx
connect issue_slots[6].out_uop.stq_idx, slots_6.io.out_uop.stq_idx
connect issue_slots[6].out_uop.ldq_idx, slots_6.io.out_uop.ldq_idx
connect issue_slots[6].out_uop.rob_idx, slots_6.io.out_uop.rob_idx
connect issue_slots[6].out_uop.csr_addr, slots_6.io.out_uop.csr_addr
connect issue_slots[6].out_uop.imm_packed, slots_6.io.out_uop.imm_packed
connect issue_slots[6].out_uop.taken, slots_6.io.out_uop.taken
connect issue_slots[6].out_uop.pc_lob, slots_6.io.out_uop.pc_lob
connect issue_slots[6].out_uop.edge_inst, slots_6.io.out_uop.edge_inst
connect issue_slots[6].out_uop.ftq_idx, slots_6.io.out_uop.ftq_idx
connect issue_slots[6].out_uop.br_tag, slots_6.io.out_uop.br_tag
connect issue_slots[6].out_uop.br_mask, slots_6.io.out_uop.br_mask
connect issue_slots[6].out_uop.is_sfb, slots_6.io.out_uop.is_sfb
connect issue_slots[6].out_uop.is_jal, slots_6.io.out_uop.is_jal
connect issue_slots[6].out_uop.is_jalr, slots_6.io.out_uop.is_jalr
connect issue_slots[6].out_uop.is_br, slots_6.io.out_uop.is_br
connect issue_slots[6].out_uop.iw_p2_poisoned, slots_6.io.out_uop.iw_p2_poisoned
connect issue_slots[6].out_uop.iw_p1_poisoned, slots_6.io.out_uop.iw_p1_poisoned
connect issue_slots[6].out_uop.iw_state, slots_6.io.out_uop.iw_state
connect issue_slots[6].out_uop.ctrl.is_std, slots_6.io.out_uop.ctrl.is_std
connect issue_slots[6].out_uop.ctrl.is_sta, slots_6.io.out_uop.ctrl.is_sta
connect issue_slots[6].out_uop.ctrl.is_load, slots_6.io.out_uop.ctrl.is_load
connect issue_slots[6].out_uop.ctrl.csr_cmd, slots_6.io.out_uop.ctrl.csr_cmd
connect issue_slots[6].out_uop.ctrl.fcn_dw, slots_6.io.out_uop.ctrl.fcn_dw
connect issue_slots[6].out_uop.ctrl.op_fcn, slots_6.io.out_uop.ctrl.op_fcn
connect issue_slots[6].out_uop.ctrl.imm_sel, slots_6.io.out_uop.ctrl.imm_sel
connect issue_slots[6].out_uop.ctrl.op2_sel, slots_6.io.out_uop.ctrl.op2_sel
connect issue_slots[6].out_uop.ctrl.op1_sel, slots_6.io.out_uop.ctrl.op1_sel
connect issue_slots[6].out_uop.ctrl.br_type, slots_6.io.out_uop.ctrl.br_type
connect issue_slots[6].out_uop.fu_code, slots_6.io.out_uop.fu_code
connect issue_slots[6].out_uop.iq_type, slots_6.io.out_uop.iq_type
connect issue_slots[6].out_uop.debug_pc, slots_6.io.out_uop.debug_pc
connect issue_slots[6].out_uop.is_rvc, slots_6.io.out_uop.is_rvc
connect issue_slots[6].out_uop.debug_inst, slots_6.io.out_uop.debug_inst
connect issue_slots[6].out_uop.inst, slots_6.io.out_uop.inst
connect issue_slots[6].out_uop.uopc, slots_6.io.out_uop.uopc
connect slots_6.io.in_uop.bits.debug_tsrc, issue_slots[6].in_uop.bits.debug_tsrc
connect slots_6.io.in_uop.bits.debug_fsrc, issue_slots[6].in_uop.bits.debug_fsrc
connect slots_6.io.in_uop.bits.bp_xcpt_if, issue_slots[6].in_uop.bits.bp_xcpt_if
connect slots_6.io.in_uop.bits.bp_debug_if, issue_slots[6].in_uop.bits.bp_debug_if
connect slots_6.io.in_uop.bits.xcpt_ma_if, issue_slots[6].in_uop.bits.xcpt_ma_if
connect slots_6.io.in_uop.bits.xcpt_ae_if, issue_slots[6].in_uop.bits.xcpt_ae_if
connect slots_6.io.in_uop.bits.xcpt_pf_if, issue_slots[6].in_uop.bits.xcpt_pf_if
connect slots_6.io.in_uop.bits.fp_single, issue_slots[6].in_uop.bits.fp_single
connect slots_6.io.in_uop.bits.fp_val, issue_slots[6].in_uop.bits.fp_val
connect slots_6.io.in_uop.bits.frs3_en, issue_slots[6].in_uop.bits.frs3_en
connect slots_6.io.in_uop.bits.lrs2_rtype, issue_slots[6].in_uop.bits.lrs2_rtype
connect slots_6.io.in_uop.bits.lrs1_rtype, issue_slots[6].in_uop.bits.lrs1_rtype
connect slots_6.io.in_uop.bits.dst_rtype, issue_slots[6].in_uop.bits.dst_rtype
connect slots_6.io.in_uop.bits.ldst_val, issue_slots[6].in_uop.bits.ldst_val
connect slots_6.io.in_uop.bits.lrs3, issue_slots[6].in_uop.bits.lrs3
connect slots_6.io.in_uop.bits.lrs2, issue_slots[6].in_uop.bits.lrs2
connect slots_6.io.in_uop.bits.lrs1, issue_slots[6].in_uop.bits.lrs1
connect slots_6.io.in_uop.bits.ldst, issue_slots[6].in_uop.bits.ldst
connect slots_6.io.in_uop.bits.ldst_is_rs1, issue_slots[6].in_uop.bits.ldst_is_rs1
connect slots_6.io.in_uop.bits.flush_on_commit, issue_slots[6].in_uop.bits.flush_on_commit
connect slots_6.io.in_uop.bits.is_unique, issue_slots[6].in_uop.bits.is_unique
connect slots_6.io.in_uop.bits.is_sys_pc2epc, issue_slots[6].in_uop.bits.is_sys_pc2epc
connect slots_6.io.in_uop.bits.uses_stq, issue_slots[6].in_uop.bits.uses_stq
connect slots_6.io.in_uop.bits.uses_ldq, issue_slots[6].in_uop.bits.uses_ldq
connect slots_6.io.in_uop.bits.is_amo, issue_slots[6].in_uop.bits.is_amo
connect slots_6.io.in_uop.bits.is_fencei, issue_slots[6].in_uop.bits.is_fencei
connect slots_6.io.in_uop.bits.is_fence, issue_slots[6].in_uop.bits.is_fence
connect slots_6.io.in_uop.bits.mem_signed, issue_slots[6].in_uop.bits.mem_signed
connect slots_6.io.in_uop.bits.mem_size, issue_slots[6].in_uop.bits.mem_size
connect slots_6.io.in_uop.bits.mem_cmd, issue_slots[6].in_uop.bits.mem_cmd
connect slots_6.io.in_uop.bits.bypassable, issue_slots[6].in_uop.bits.bypassable
connect slots_6.io.in_uop.bits.exc_cause, issue_slots[6].in_uop.bits.exc_cause
connect slots_6.io.in_uop.bits.exception, issue_slots[6].in_uop.bits.exception
connect slots_6.io.in_uop.bits.stale_pdst, issue_slots[6].in_uop.bits.stale_pdst
connect slots_6.io.in_uop.bits.ppred_busy, issue_slots[6].in_uop.bits.ppred_busy
connect slots_6.io.in_uop.bits.prs3_busy, issue_slots[6].in_uop.bits.prs3_busy
connect slots_6.io.in_uop.bits.prs2_busy, issue_slots[6].in_uop.bits.prs2_busy
connect slots_6.io.in_uop.bits.prs1_busy, issue_slots[6].in_uop.bits.prs1_busy
connect slots_6.io.in_uop.bits.ppred, issue_slots[6].in_uop.bits.ppred
connect slots_6.io.in_uop.bits.prs3, issue_slots[6].in_uop.bits.prs3
connect slots_6.io.in_uop.bits.prs2, issue_slots[6].in_uop.bits.prs2
connect slots_6.io.in_uop.bits.prs1, issue_slots[6].in_uop.bits.prs1
connect slots_6.io.in_uop.bits.pdst, issue_slots[6].in_uop.bits.pdst
connect slots_6.io.in_uop.bits.rxq_idx, issue_slots[6].in_uop.bits.rxq_idx
connect slots_6.io.in_uop.bits.stq_idx, issue_slots[6].in_uop.bits.stq_idx
connect slots_6.io.in_uop.bits.ldq_idx, issue_slots[6].in_uop.bits.ldq_idx
connect slots_6.io.in_uop.bits.rob_idx, issue_slots[6].in_uop.bits.rob_idx
connect slots_6.io.in_uop.bits.csr_addr, issue_slots[6].in_uop.bits.csr_addr
connect slots_6.io.in_uop.bits.imm_packed, issue_slots[6].in_uop.bits.imm_packed
connect slots_6.io.in_uop.bits.taken, issue_slots[6].in_uop.bits.taken
connect slots_6.io.in_uop.bits.pc_lob, issue_slots[6].in_uop.bits.pc_lob
connect slots_6.io.in_uop.bits.edge_inst, issue_slots[6].in_uop.bits.edge_inst
connect slots_6.io.in_uop.bits.ftq_idx, issue_slots[6].in_uop.bits.ftq_idx
connect slots_6.io.in_uop.bits.br_tag, issue_slots[6].in_uop.bits.br_tag
connect slots_6.io.in_uop.bits.br_mask, issue_slots[6].in_uop.bits.br_mask
connect slots_6.io.in_uop.bits.is_sfb, issue_slots[6].in_uop.bits.is_sfb
connect slots_6.io.in_uop.bits.is_jal, issue_slots[6].in_uop.bits.is_jal
connect slots_6.io.in_uop.bits.is_jalr, issue_slots[6].in_uop.bits.is_jalr
connect slots_6.io.in_uop.bits.is_br, issue_slots[6].in_uop.bits.is_br
connect slots_6.io.in_uop.bits.iw_p2_poisoned, issue_slots[6].in_uop.bits.iw_p2_poisoned
connect slots_6.io.in_uop.bits.iw_p1_poisoned, issue_slots[6].in_uop.bits.iw_p1_poisoned
connect slots_6.io.in_uop.bits.iw_state, issue_slots[6].in_uop.bits.iw_state
connect slots_6.io.in_uop.bits.ctrl.is_std, issue_slots[6].in_uop.bits.ctrl.is_std
connect slots_6.io.in_uop.bits.ctrl.is_sta, issue_slots[6].in_uop.bits.ctrl.is_sta
connect slots_6.io.in_uop.bits.ctrl.is_load, issue_slots[6].in_uop.bits.ctrl.is_load
connect slots_6.io.in_uop.bits.ctrl.csr_cmd, issue_slots[6].in_uop.bits.ctrl.csr_cmd
connect slots_6.io.in_uop.bits.ctrl.fcn_dw, issue_slots[6].in_uop.bits.ctrl.fcn_dw
connect slots_6.io.in_uop.bits.ctrl.op_fcn, issue_slots[6].in_uop.bits.ctrl.op_fcn
connect slots_6.io.in_uop.bits.ctrl.imm_sel, issue_slots[6].in_uop.bits.ctrl.imm_sel
connect slots_6.io.in_uop.bits.ctrl.op2_sel, issue_slots[6].in_uop.bits.ctrl.op2_sel
connect slots_6.io.in_uop.bits.ctrl.op1_sel, issue_slots[6].in_uop.bits.ctrl.op1_sel
connect slots_6.io.in_uop.bits.ctrl.br_type, issue_slots[6].in_uop.bits.ctrl.br_type
connect slots_6.io.in_uop.bits.fu_code, issue_slots[6].in_uop.bits.fu_code
connect slots_6.io.in_uop.bits.iq_type, issue_slots[6].in_uop.bits.iq_type
connect slots_6.io.in_uop.bits.debug_pc, issue_slots[6].in_uop.bits.debug_pc
connect slots_6.io.in_uop.bits.is_rvc, issue_slots[6].in_uop.bits.is_rvc
connect slots_6.io.in_uop.bits.debug_inst, issue_slots[6].in_uop.bits.debug_inst
connect slots_6.io.in_uop.bits.inst, issue_slots[6].in_uop.bits.inst
connect slots_6.io.in_uop.bits.uopc, issue_slots[6].in_uop.bits.uopc
connect slots_6.io.in_uop.valid, issue_slots[6].in_uop.valid
connect slots_6.io.spec_ld_wakeup[0].bits, issue_slots[6].spec_ld_wakeup[0].bits
connect slots_6.io.spec_ld_wakeup[0].valid, issue_slots[6].spec_ld_wakeup[0].valid
connect slots_6.io.pred_wakeup_port.bits, issue_slots[6].pred_wakeup_port.bits
connect slots_6.io.pred_wakeup_port.valid, issue_slots[6].pred_wakeup_port.valid
connect slots_6.io.wakeup_ports[0].bits.poisoned, issue_slots[6].wakeup_ports[0].bits.poisoned
connect slots_6.io.wakeup_ports[0].bits.pdst, issue_slots[6].wakeup_ports[0].bits.pdst
connect slots_6.io.wakeup_ports[0].valid, issue_slots[6].wakeup_ports[0].valid
connect slots_6.io.wakeup_ports[1].bits.poisoned, issue_slots[6].wakeup_ports[1].bits.poisoned
connect slots_6.io.wakeup_ports[1].bits.pdst, issue_slots[6].wakeup_ports[1].bits.pdst
connect slots_6.io.wakeup_ports[1].valid, issue_slots[6].wakeup_ports[1].valid
connect slots_6.io.wakeup_ports[2].bits.poisoned, issue_slots[6].wakeup_ports[2].bits.poisoned
connect slots_6.io.wakeup_ports[2].bits.pdst, issue_slots[6].wakeup_ports[2].bits.pdst
connect slots_6.io.wakeup_ports[2].valid, issue_slots[6].wakeup_ports[2].valid
connect slots_6.io.ldspec_miss, issue_slots[6].ldspec_miss
connect slots_6.io.clear, issue_slots[6].clear
connect slots_6.io.kill, issue_slots[6].kill
connect slots_6.io.brupdate.b2.target_offset, issue_slots[6].brupdate.b2.target_offset
connect slots_6.io.brupdate.b2.jalr_target, issue_slots[6].brupdate.b2.jalr_target
connect slots_6.io.brupdate.b2.pc_sel, issue_slots[6].brupdate.b2.pc_sel
connect slots_6.io.brupdate.b2.cfi_type, issue_slots[6].brupdate.b2.cfi_type
connect slots_6.io.brupdate.b2.taken, issue_slots[6].brupdate.b2.taken
connect slots_6.io.brupdate.b2.mispredict, issue_slots[6].brupdate.b2.mispredict
connect slots_6.io.brupdate.b2.valid, issue_slots[6].brupdate.b2.valid
connect slots_6.io.brupdate.b2.uop.debug_tsrc, issue_slots[6].brupdate.b2.uop.debug_tsrc
connect slots_6.io.brupdate.b2.uop.debug_fsrc, issue_slots[6].brupdate.b2.uop.debug_fsrc
connect slots_6.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[6].brupdate.b2.uop.bp_xcpt_if
connect slots_6.io.brupdate.b2.uop.bp_debug_if, issue_slots[6].brupdate.b2.uop.bp_debug_if
connect slots_6.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[6].brupdate.b2.uop.xcpt_ma_if
connect slots_6.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[6].brupdate.b2.uop.xcpt_ae_if
connect slots_6.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[6].brupdate.b2.uop.xcpt_pf_if
connect slots_6.io.brupdate.b2.uop.fp_single, issue_slots[6].brupdate.b2.uop.fp_single
connect slots_6.io.brupdate.b2.uop.fp_val, issue_slots[6].brupdate.b2.uop.fp_val
connect slots_6.io.brupdate.b2.uop.frs3_en, issue_slots[6].brupdate.b2.uop.frs3_en
connect slots_6.io.brupdate.b2.uop.lrs2_rtype, issue_slots[6].brupdate.b2.uop.lrs2_rtype
connect slots_6.io.brupdate.b2.uop.lrs1_rtype, issue_slots[6].brupdate.b2.uop.lrs1_rtype
connect slots_6.io.brupdate.b2.uop.dst_rtype, issue_slots[6].brupdate.b2.uop.dst_rtype
connect slots_6.io.brupdate.b2.uop.ldst_val, issue_slots[6].brupdate.b2.uop.ldst_val
connect slots_6.io.brupdate.b2.uop.lrs3, issue_slots[6].brupdate.b2.uop.lrs3
connect slots_6.io.brupdate.b2.uop.lrs2, issue_slots[6].brupdate.b2.uop.lrs2
connect slots_6.io.brupdate.b2.uop.lrs1, issue_slots[6].brupdate.b2.uop.lrs1
connect slots_6.io.brupdate.b2.uop.ldst, issue_slots[6].brupdate.b2.uop.ldst
connect slots_6.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[6].brupdate.b2.uop.ldst_is_rs1
connect slots_6.io.brupdate.b2.uop.flush_on_commit, issue_slots[6].brupdate.b2.uop.flush_on_commit
connect slots_6.io.brupdate.b2.uop.is_unique, issue_slots[6].brupdate.b2.uop.is_unique
connect slots_6.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[6].brupdate.b2.uop.is_sys_pc2epc
connect slots_6.io.brupdate.b2.uop.uses_stq, issue_slots[6].brupdate.b2.uop.uses_stq
connect slots_6.io.brupdate.b2.uop.uses_ldq, issue_slots[6].brupdate.b2.uop.uses_ldq
connect slots_6.io.brupdate.b2.uop.is_amo, issue_slots[6].brupdate.b2.uop.is_amo
connect slots_6.io.brupdate.b2.uop.is_fencei, issue_slots[6].brupdate.b2.uop.is_fencei
connect slots_6.io.brupdate.b2.uop.is_fence, issue_slots[6].brupdate.b2.uop.is_fence
connect slots_6.io.brupdate.b2.uop.mem_signed, issue_slots[6].brupdate.b2.uop.mem_signed
connect slots_6.io.brupdate.b2.uop.mem_size, issue_slots[6].brupdate.b2.uop.mem_size
connect slots_6.io.brupdate.b2.uop.mem_cmd, issue_slots[6].brupdate.b2.uop.mem_cmd
connect slots_6.io.brupdate.b2.uop.bypassable, issue_slots[6].brupdate.b2.uop.bypassable
connect slots_6.io.brupdate.b2.uop.exc_cause, issue_slots[6].brupdate.b2.uop.exc_cause
connect slots_6.io.brupdate.b2.uop.exception, issue_slots[6].brupdate.b2.uop.exception
connect slots_6.io.brupdate.b2.uop.stale_pdst, issue_slots[6].brupdate.b2.uop.stale_pdst
connect slots_6.io.brupdate.b2.uop.ppred_busy, issue_slots[6].brupdate.b2.uop.ppred_busy
connect slots_6.io.brupdate.b2.uop.prs3_busy, issue_slots[6].brupdate.b2.uop.prs3_busy
connect slots_6.io.brupdate.b2.uop.prs2_busy, issue_slots[6].brupdate.b2.uop.prs2_busy
connect slots_6.io.brupdate.b2.uop.prs1_busy, issue_slots[6].brupdate.b2.uop.prs1_busy
connect slots_6.io.brupdate.b2.uop.ppred, issue_slots[6].brupdate.b2.uop.ppred
connect slots_6.io.brupdate.b2.uop.prs3, issue_slots[6].brupdate.b2.uop.prs3
connect slots_6.io.brupdate.b2.uop.prs2, issue_slots[6].brupdate.b2.uop.prs2
connect slots_6.io.brupdate.b2.uop.prs1, issue_slots[6].brupdate.b2.uop.prs1
connect slots_6.io.brupdate.b2.uop.pdst, issue_slots[6].brupdate.b2.uop.pdst
connect slots_6.io.brupdate.b2.uop.rxq_idx, issue_slots[6].brupdate.b2.uop.rxq_idx
connect slots_6.io.brupdate.b2.uop.stq_idx, issue_slots[6].brupdate.b2.uop.stq_idx
connect slots_6.io.brupdate.b2.uop.ldq_idx, issue_slots[6].brupdate.b2.uop.ldq_idx
connect slots_6.io.brupdate.b2.uop.rob_idx, issue_slots[6].brupdate.b2.uop.rob_idx
connect slots_6.io.brupdate.b2.uop.csr_addr, issue_slots[6].brupdate.b2.uop.csr_addr
connect slots_6.io.brupdate.b2.uop.imm_packed, issue_slots[6].brupdate.b2.uop.imm_packed
connect slots_6.io.brupdate.b2.uop.taken, issue_slots[6].brupdate.b2.uop.taken
connect slots_6.io.brupdate.b2.uop.pc_lob, issue_slots[6].brupdate.b2.uop.pc_lob
connect slots_6.io.brupdate.b2.uop.edge_inst, issue_slots[6].brupdate.b2.uop.edge_inst
connect slots_6.io.brupdate.b2.uop.ftq_idx, issue_slots[6].brupdate.b2.uop.ftq_idx
connect slots_6.io.brupdate.b2.uop.br_tag, issue_slots[6].brupdate.b2.uop.br_tag
connect slots_6.io.brupdate.b2.uop.br_mask, issue_slots[6].brupdate.b2.uop.br_mask
connect slots_6.io.brupdate.b2.uop.is_sfb, issue_slots[6].brupdate.b2.uop.is_sfb
connect slots_6.io.brupdate.b2.uop.is_jal, issue_slots[6].brupdate.b2.uop.is_jal
connect slots_6.io.brupdate.b2.uop.is_jalr, issue_slots[6].brupdate.b2.uop.is_jalr
connect slots_6.io.brupdate.b2.uop.is_br, issue_slots[6].brupdate.b2.uop.is_br
connect slots_6.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[6].brupdate.b2.uop.iw_p2_poisoned
connect slots_6.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[6].brupdate.b2.uop.iw_p1_poisoned
connect slots_6.io.brupdate.b2.uop.iw_state, issue_slots[6].brupdate.b2.uop.iw_state
connect slots_6.io.brupdate.b2.uop.ctrl.is_std, issue_slots[6].brupdate.b2.uop.ctrl.is_std
connect slots_6.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[6].brupdate.b2.uop.ctrl.is_sta
connect slots_6.io.brupdate.b2.uop.ctrl.is_load, issue_slots[6].brupdate.b2.uop.ctrl.is_load
connect slots_6.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[6].brupdate.b2.uop.ctrl.csr_cmd
connect slots_6.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[6].brupdate.b2.uop.ctrl.fcn_dw
connect slots_6.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[6].brupdate.b2.uop.ctrl.op_fcn
connect slots_6.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[6].brupdate.b2.uop.ctrl.imm_sel
connect slots_6.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[6].brupdate.b2.uop.ctrl.op2_sel
connect slots_6.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[6].brupdate.b2.uop.ctrl.op1_sel
connect slots_6.io.brupdate.b2.uop.ctrl.br_type, issue_slots[6].brupdate.b2.uop.ctrl.br_type
connect slots_6.io.brupdate.b2.uop.fu_code, issue_slots[6].brupdate.b2.uop.fu_code
connect slots_6.io.brupdate.b2.uop.iq_type, issue_slots[6].brupdate.b2.uop.iq_type
connect slots_6.io.brupdate.b2.uop.debug_pc, issue_slots[6].brupdate.b2.uop.debug_pc
connect slots_6.io.brupdate.b2.uop.is_rvc, issue_slots[6].brupdate.b2.uop.is_rvc
connect slots_6.io.brupdate.b2.uop.debug_inst, issue_slots[6].brupdate.b2.uop.debug_inst
connect slots_6.io.brupdate.b2.uop.inst, issue_slots[6].brupdate.b2.uop.inst
connect slots_6.io.brupdate.b2.uop.uopc, issue_slots[6].brupdate.b2.uop.uopc
connect slots_6.io.brupdate.b1.mispredict_mask, issue_slots[6].brupdate.b1.mispredict_mask
connect slots_6.io.brupdate.b1.resolve_mask, issue_slots[6].brupdate.b1.resolve_mask
connect slots_6.io.grant, issue_slots[6].grant
connect issue_slots[6].request_hp, slots_6.io.request_hp
connect issue_slots[6].request, slots_6.io.request
connect issue_slots[6].will_be_valid, slots_6.io.will_be_valid
connect issue_slots[6].valid, slots_6.io.valid
connect issue_slots[7].debug.state, slots_7.io.debug.state
connect issue_slots[7].debug.ppred, slots_7.io.debug.ppred
connect issue_slots[7].debug.p3, slots_7.io.debug.p3
connect issue_slots[7].debug.p2, slots_7.io.debug.p2
connect issue_slots[7].debug.p1, slots_7.io.debug.p1
connect issue_slots[7].uop.debug_tsrc, slots_7.io.uop.debug_tsrc
connect issue_slots[7].uop.debug_fsrc, slots_7.io.uop.debug_fsrc
connect issue_slots[7].uop.bp_xcpt_if, slots_7.io.uop.bp_xcpt_if
connect issue_slots[7].uop.bp_debug_if, slots_7.io.uop.bp_debug_if
connect issue_slots[7].uop.xcpt_ma_if, slots_7.io.uop.xcpt_ma_if
connect issue_slots[7].uop.xcpt_ae_if, slots_7.io.uop.xcpt_ae_if
connect issue_slots[7].uop.xcpt_pf_if, slots_7.io.uop.xcpt_pf_if
connect issue_slots[7].uop.fp_single, slots_7.io.uop.fp_single
connect issue_slots[7].uop.fp_val, slots_7.io.uop.fp_val
connect issue_slots[7].uop.frs3_en, slots_7.io.uop.frs3_en
connect issue_slots[7].uop.lrs2_rtype, slots_7.io.uop.lrs2_rtype
connect issue_slots[7].uop.lrs1_rtype, slots_7.io.uop.lrs1_rtype
connect issue_slots[7].uop.dst_rtype, slots_7.io.uop.dst_rtype
connect issue_slots[7].uop.ldst_val, slots_7.io.uop.ldst_val
connect issue_slots[7].uop.lrs3, slots_7.io.uop.lrs3
connect issue_slots[7].uop.lrs2, slots_7.io.uop.lrs2
connect issue_slots[7].uop.lrs1, slots_7.io.uop.lrs1
connect issue_slots[7].uop.ldst, slots_7.io.uop.ldst
connect issue_slots[7].uop.ldst_is_rs1, slots_7.io.uop.ldst_is_rs1
connect issue_slots[7].uop.flush_on_commit, slots_7.io.uop.flush_on_commit
connect issue_slots[7].uop.is_unique, slots_7.io.uop.is_unique
connect issue_slots[7].uop.is_sys_pc2epc, slots_7.io.uop.is_sys_pc2epc
connect issue_slots[7].uop.uses_stq, slots_7.io.uop.uses_stq
connect issue_slots[7].uop.uses_ldq, slots_7.io.uop.uses_ldq
connect issue_slots[7].uop.is_amo, slots_7.io.uop.is_amo
connect issue_slots[7].uop.is_fencei, slots_7.io.uop.is_fencei
connect issue_slots[7].uop.is_fence, slots_7.io.uop.is_fence
connect issue_slots[7].uop.mem_signed, slots_7.io.uop.mem_signed
connect issue_slots[7].uop.mem_size, slots_7.io.uop.mem_size
connect issue_slots[7].uop.mem_cmd, slots_7.io.uop.mem_cmd
connect issue_slots[7].uop.bypassable, slots_7.io.uop.bypassable
connect issue_slots[7].uop.exc_cause, slots_7.io.uop.exc_cause
connect issue_slots[7].uop.exception, slots_7.io.uop.exception
connect issue_slots[7].uop.stale_pdst, slots_7.io.uop.stale_pdst
connect issue_slots[7].uop.ppred_busy, slots_7.io.uop.ppred_busy
connect issue_slots[7].uop.prs3_busy, slots_7.io.uop.prs3_busy
connect issue_slots[7].uop.prs2_busy, slots_7.io.uop.prs2_busy
connect issue_slots[7].uop.prs1_busy, slots_7.io.uop.prs1_busy
connect issue_slots[7].uop.ppred, slots_7.io.uop.ppred
connect issue_slots[7].uop.prs3, slots_7.io.uop.prs3
connect issue_slots[7].uop.prs2, slots_7.io.uop.prs2
connect issue_slots[7].uop.prs1, slots_7.io.uop.prs1
connect issue_slots[7].uop.pdst, slots_7.io.uop.pdst
connect issue_slots[7].uop.rxq_idx, slots_7.io.uop.rxq_idx
connect issue_slots[7].uop.stq_idx, slots_7.io.uop.stq_idx
connect issue_slots[7].uop.ldq_idx, slots_7.io.uop.ldq_idx
connect issue_slots[7].uop.rob_idx, slots_7.io.uop.rob_idx
connect issue_slots[7].uop.csr_addr, slots_7.io.uop.csr_addr
connect issue_slots[7].uop.imm_packed, slots_7.io.uop.imm_packed
connect issue_slots[7].uop.taken, slots_7.io.uop.taken
connect issue_slots[7].uop.pc_lob, slots_7.io.uop.pc_lob
connect issue_slots[7].uop.edge_inst, slots_7.io.uop.edge_inst
connect issue_slots[7].uop.ftq_idx, slots_7.io.uop.ftq_idx
connect issue_slots[7].uop.br_tag, slots_7.io.uop.br_tag
connect issue_slots[7].uop.br_mask, slots_7.io.uop.br_mask
connect issue_slots[7].uop.is_sfb, slots_7.io.uop.is_sfb
connect issue_slots[7].uop.is_jal, slots_7.io.uop.is_jal
connect issue_slots[7].uop.is_jalr, slots_7.io.uop.is_jalr
connect issue_slots[7].uop.is_br, slots_7.io.uop.is_br
connect issue_slots[7].uop.iw_p2_poisoned, slots_7.io.uop.iw_p2_poisoned
connect issue_slots[7].uop.iw_p1_poisoned, slots_7.io.uop.iw_p1_poisoned
connect issue_slots[7].uop.iw_state, slots_7.io.uop.iw_state
connect issue_slots[7].uop.ctrl.is_std, slots_7.io.uop.ctrl.is_std
connect issue_slots[7].uop.ctrl.is_sta, slots_7.io.uop.ctrl.is_sta
connect issue_slots[7].uop.ctrl.is_load, slots_7.io.uop.ctrl.is_load
connect issue_slots[7].uop.ctrl.csr_cmd, slots_7.io.uop.ctrl.csr_cmd
connect issue_slots[7].uop.ctrl.fcn_dw, slots_7.io.uop.ctrl.fcn_dw
connect issue_slots[7].uop.ctrl.op_fcn, slots_7.io.uop.ctrl.op_fcn
connect issue_slots[7].uop.ctrl.imm_sel, slots_7.io.uop.ctrl.imm_sel
connect issue_slots[7].uop.ctrl.op2_sel, slots_7.io.uop.ctrl.op2_sel
connect issue_slots[7].uop.ctrl.op1_sel, slots_7.io.uop.ctrl.op1_sel
connect issue_slots[7].uop.ctrl.br_type, slots_7.io.uop.ctrl.br_type
connect issue_slots[7].uop.fu_code, slots_7.io.uop.fu_code
connect issue_slots[7].uop.iq_type, slots_7.io.uop.iq_type
connect issue_slots[7].uop.debug_pc, slots_7.io.uop.debug_pc
connect issue_slots[7].uop.is_rvc, slots_7.io.uop.is_rvc
connect issue_slots[7].uop.debug_inst, slots_7.io.uop.debug_inst
connect issue_slots[7].uop.inst, slots_7.io.uop.inst
connect issue_slots[7].uop.uopc, slots_7.io.uop.uopc
connect issue_slots[7].out_uop.debug_tsrc, slots_7.io.out_uop.debug_tsrc
connect issue_slots[7].out_uop.debug_fsrc, slots_7.io.out_uop.debug_fsrc
connect issue_slots[7].out_uop.bp_xcpt_if, slots_7.io.out_uop.bp_xcpt_if
connect issue_slots[7].out_uop.bp_debug_if, slots_7.io.out_uop.bp_debug_if
connect issue_slots[7].out_uop.xcpt_ma_if, slots_7.io.out_uop.xcpt_ma_if
connect issue_slots[7].out_uop.xcpt_ae_if, slots_7.io.out_uop.xcpt_ae_if
connect issue_slots[7].out_uop.xcpt_pf_if, slots_7.io.out_uop.xcpt_pf_if
connect issue_slots[7].out_uop.fp_single, slots_7.io.out_uop.fp_single
connect issue_slots[7].out_uop.fp_val, slots_7.io.out_uop.fp_val
connect issue_slots[7].out_uop.frs3_en, slots_7.io.out_uop.frs3_en
connect issue_slots[7].out_uop.lrs2_rtype, slots_7.io.out_uop.lrs2_rtype
connect issue_slots[7].out_uop.lrs1_rtype, slots_7.io.out_uop.lrs1_rtype
connect issue_slots[7].out_uop.dst_rtype, slots_7.io.out_uop.dst_rtype
connect issue_slots[7].out_uop.ldst_val, slots_7.io.out_uop.ldst_val
connect issue_slots[7].out_uop.lrs3, slots_7.io.out_uop.lrs3
connect issue_slots[7].out_uop.lrs2, slots_7.io.out_uop.lrs2
connect issue_slots[7].out_uop.lrs1, slots_7.io.out_uop.lrs1
connect issue_slots[7].out_uop.ldst, slots_7.io.out_uop.ldst
connect issue_slots[7].out_uop.ldst_is_rs1, slots_7.io.out_uop.ldst_is_rs1
connect issue_slots[7].out_uop.flush_on_commit, slots_7.io.out_uop.flush_on_commit
connect issue_slots[7].out_uop.is_unique, slots_7.io.out_uop.is_unique
connect issue_slots[7].out_uop.is_sys_pc2epc, slots_7.io.out_uop.is_sys_pc2epc
connect issue_slots[7].out_uop.uses_stq, slots_7.io.out_uop.uses_stq
connect issue_slots[7].out_uop.uses_ldq, slots_7.io.out_uop.uses_ldq
connect issue_slots[7].out_uop.is_amo, slots_7.io.out_uop.is_amo
connect issue_slots[7].out_uop.is_fencei, slots_7.io.out_uop.is_fencei
connect issue_slots[7].out_uop.is_fence, slots_7.io.out_uop.is_fence
connect issue_slots[7].out_uop.mem_signed, slots_7.io.out_uop.mem_signed
connect issue_slots[7].out_uop.mem_size, slots_7.io.out_uop.mem_size
connect issue_slots[7].out_uop.mem_cmd, slots_7.io.out_uop.mem_cmd
connect issue_slots[7].out_uop.bypassable, slots_7.io.out_uop.bypassable
connect issue_slots[7].out_uop.exc_cause, slots_7.io.out_uop.exc_cause
connect issue_slots[7].out_uop.exception, slots_7.io.out_uop.exception
connect issue_slots[7].out_uop.stale_pdst, slots_7.io.out_uop.stale_pdst
connect issue_slots[7].out_uop.ppred_busy, slots_7.io.out_uop.ppred_busy
connect issue_slots[7].out_uop.prs3_busy, slots_7.io.out_uop.prs3_busy
connect issue_slots[7].out_uop.prs2_busy, slots_7.io.out_uop.prs2_busy
connect issue_slots[7].out_uop.prs1_busy, slots_7.io.out_uop.prs1_busy
connect issue_slots[7].out_uop.ppred, slots_7.io.out_uop.ppred
connect issue_slots[7].out_uop.prs3, slots_7.io.out_uop.prs3
connect issue_slots[7].out_uop.prs2, slots_7.io.out_uop.prs2
connect issue_slots[7].out_uop.prs1, slots_7.io.out_uop.prs1
connect issue_slots[7].out_uop.pdst, slots_7.io.out_uop.pdst
connect issue_slots[7].out_uop.rxq_idx, slots_7.io.out_uop.rxq_idx
connect issue_slots[7].out_uop.stq_idx, slots_7.io.out_uop.stq_idx
connect issue_slots[7].out_uop.ldq_idx, slots_7.io.out_uop.ldq_idx
connect issue_slots[7].out_uop.rob_idx, slots_7.io.out_uop.rob_idx
connect issue_slots[7].out_uop.csr_addr, slots_7.io.out_uop.csr_addr
connect issue_slots[7].out_uop.imm_packed, slots_7.io.out_uop.imm_packed
connect issue_slots[7].out_uop.taken, slots_7.io.out_uop.taken
connect issue_slots[7].out_uop.pc_lob, slots_7.io.out_uop.pc_lob
connect issue_slots[7].out_uop.edge_inst, slots_7.io.out_uop.edge_inst
connect issue_slots[7].out_uop.ftq_idx, slots_7.io.out_uop.ftq_idx
connect issue_slots[7].out_uop.br_tag, slots_7.io.out_uop.br_tag
connect issue_slots[7].out_uop.br_mask, slots_7.io.out_uop.br_mask
connect issue_slots[7].out_uop.is_sfb, slots_7.io.out_uop.is_sfb
connect issue_slots[7].out_uop.is_jal, slots_7.io.out_uop.is_jal
connect issue_slots[7].out_uop.is_jalr, slots_7.io.out_uop.is_jalr
connect issue_slots[7].out_uop.is_br, slots_7.io.out_uop.is_br
connect issue_slots[7].out_uop.iw_p2_poisoned, slots_7.io.out_uop.iw_p2_poisoned
connect issue_slots[7].out_uop.iw_p1_poisoned, slots_7.io.out_uop.iw_p1_poisoned
connect issue_slots[7].out_uop.iw_state, slots_7.io.out_uop.iw_state
connect issue_slots[7].out_uop.ctrl.is_std, slots_7.io.out_uop.ctrl.is_std
connect issue_slots[7].out_uop.ctrl.is_sta, slots_7.io.out_uop.ctrl.is_sta
connect issue_slots[7].out_uop.ctrl.is_load, slots_7.io.out_uop.ctrl.is_load
connect issue_slots[7].out_uop.ctrl.csr_cmd, slots_7.io.out_uop.ctrl.csr_cmd
connect issue_slots[7].out_uop.ctrl.fcn_dw, slots_7.io.out_uop.ctrl.fcn_dw
connect issue_slots[7].out_uop.ctrl.op_fcn, slots_7.io.out_uop.ctrl.op_fcn
connect issue_slots[7].out_uop.ctrl.imm_sel, slots_7.io.out_uop.ctrl.imm_sel
connect issue_slots[7].out_uop.ctrl.op2_sel, slots_7.io.out_uop.ctrl.op2_sel
connect issue_slots[7].out_uop.ctrl.op1_sel, slots_7.io.out_uop.ctrl.op1_sel
connect issue_slots[7].out_uop.ctrl.br_type, slots_7.io.out_uop.ctrl.br_type
connect issue_slots[7].out_uop.fu_code, slots_7.io.out_uop.fu_code
connect issue_slots[7].out_uop.iq_type, slots_7.io.out_uop.iq_type
connect issue_slots[7].out_uop.debug_pc, slots_7.io.out_uop.debug_pc
connect issue_slots[7].out_uop.is_rvc, slots_7.io.out_uop.is_rvc
connect issue_slots[7].out_uop.debug_inst, slots_7.io.out_uop.debug_inst
connect issue_slots[7].out_uop.inst, slots_7.io.out_uop.inst
connect issue_slots[7].out_uop.uopc, slots_7.io.out_uop.uopc
connect slots_7.io.in_uop.bits.debug_tsrc, issue_slots[7].in_uop.bits.debug_tsrc
connect slots_7.io.in_uop.bits.debug_fsrc, issue_slots[7].in_uop.bits.debug_fsrc
connect slots_7.io.in_uop.bits.bp_xcpt_if, issue_slots[7].in_uop.bits.bp_xcpt_if
connect slots_7.io.in_uop.bits.bp_debug_if, issue_slots[7].in_uop.bits.bp_debug_if
connect slots_7.io.in_uop.bits.xcpt_ma_if, issue_slots[7].in_uop.bits.xcpt_ma_if
connect slots_7.io.in_uop.bits.xcpt_ae_if, issue_slots[7].in_uop.bits.xcpt_ae_if
connect slots_7.io.in_uop.bits.xcpt_pf_if, issue_slots[7].in_uop.bits.xcpt_pf_if
connect slots_7.io.in_uop.bits.fp_single, issue_slots[7].in_uop.bits.fp_single
connect slots_7.io.in_uop.bits.fp_val, issue_slots[7].in_uop.bits.fp_val
connect slots_7.io.in_uop.bits.frs3_en, issue_slots[7].in_uop.bits.frs3_en
connect slots_7.io.in_uop.bits.lrs2_rtype, issue_slots[7].in_uop.bits.lrs2_rtype
connect slots_7.io.in_uop.bits.lrs1_rtype, issue_slots[7].in_uop.bits.lrs1_rtype
connect slots_7.io.in_uop.bits.dst_rtype, issue_slots[7].in_uop.bits.dst_rtype
connect slots_7.io.in_uop.bits.ldst_val, issue_slots[7].in_uop.bits.ldst_val
connect slots_7.io.in_uop.bits.lrs3, issue_slots[7].in_uop.bits.lrs3
connect slots_7.io.in_uop.bits.lrs2, issue_slots[7].in_uop.bits.lrs2
connect slots_7.io.in_uop.bits.lrs1, issue_slots[7].in_uop.bits.lrs1
connect slots_7.io.in_uop.bits.ldst, issue_slots[7].in_uop.bits.ldst
connect slots_7.io.in_uop.bits.ldst_is_rs1, issue_slots[7].in_uop.bits.ldst_is_rs1
connect slots_7.io.in_uop.bits.flush_on_commit, issue_slots[7].in_uop.bits.flush_on_commit
connect slots_7.io.in_uop.bits.is_unique, issue_slots[7].in_uop.bits.is_unique
connect slots_7.io.in_uop.bits.is_sys_pc2epc, issue_slots[7].in_uop.bits.is_sys_pc2epc
connect slots_7.io.in_uop.bits.uses_stq, issue_slots[7].in_uop.bits.uses_stq
connect slots_7.io.in_uop.bits.uses_ldq, issue_slots[7].in_uop.bits.uses_ldq
connect slots_7.io.in_uop.bits.is_amo, issue_slots[7].in_uop.bits.is_amo
connect slots_7.io.in_uop.bits.is_fencei, issue_slots[7].in_uop.bits.is_fencei
connect slots_7.io.in_uop.bits.is_fence, issue_slots[7].in_uop.bits.is_fence
connect slots_7.io.in_uop.bits.mem_signed, issue_slots[7].in_uop.bits.mem_signed
connect slots_7.io.in_uop.bits.mem_size, issue_slots[7].in_uop.bits.mem_size
connect slots_7.io.in_uop.bits.mem_cmd, issue_slots[7].in_uop.bits.mem_cmd
connect slots_7.io.in_uop.bits.bypassable, issue_slots[7].in_uop.bits.bypassable
connect slots_7.io.in_uop.bits.exc_cause, issue_slots[7].in_uop.bits.exc_cause
connect slots_7.io.in_uop.bits.exception, issue_slots[7].in_uop.bits.exception
connect slots_7.io.in_uop.bits.stale_pdst, issue_slots[7].in_uop.bits.stale_pdst
connect slots_7.io.in_uop.bits.ppred_busy, issue_slots[7].in_uop.bits.ppred_busy
connect slots_7.io.in_uop.bits.prs3_busy, issue_slots[7].in_uop.bits.prs3_busy
connect slots_7.io.in_uop.bits.prs2_busy, issue_slots[7].in_uop.bits.prs2_busy
connect slots_7.io.in_uop.bits.prs1_busy, issue_slots[7].in_uop.bits.prs1_busy
connect slots_7.io.in_uop.bits.ppred, issue_slots[7].in_uop.bits.ppred
connect slots_7.io.in_uop.bits.prs3, issue_slots[7].in_uop.bits.prs3
connect slots_7.io.in_uop.bits.prs2, issue_slots[7].in_uop.bits.prs2
connect slots_7.io.in_uop.bits.prs1, issue_slots[7].in_uop.bits.prs1
connect slots_7.io.in_uop.bits.pdst, issue_slots[7].in_uop.bits.pdst
connect slots_7.io.in_uop.bits.rxq_idx, issue_slots[7].in_uop.bits.rxq_idx
connect slots_7.io.in_uop.bits.stq_idx, issue_slots[7].in_uop.bits.stq_idx
connect slots_7.io.in_uop.bits.ldq_idx, issue_slots[7].in_uop.bits.ldq_idx
connect slots_7.io.in_uop.bits.rob_idx, issue_slots[7].in_uop.bits.rob_idx
connect slots_7.io.in_uop.bits.csr_addr, issue_slots[7].in_uop.bits.csr_addr
connect slots_7.io.in_uop.bits.imm_packed, issue_slots[7].in_uop.bits.imm_packed
connect slots_7.io.in_uop.bits.taken, issue_slots[7].in_uop.bits.taken
connect slots_7.io.in_uop.bits.pc_lob, issue_slots[7].in_uop.bits.pc_lob
connect slots_7.io.in_uop.bits.edge_inst, issue_slots[7].in_uop.bits.edge_inst
connect slots_7.io.in_uop.bits.ftq_idx, issue_slots[7].in_uop.bits.ftq_idx
connect slots_7.io.in_uop.bits.br_tag, issue_slots[7].in_uop.bits.br_tag
connect slots_7.io.in_uop.bits.br_mask, issue_slots[7].in_uop.bits.br_mask
connect slots_7.io.in_uop.bits.is_sfb, issue_slots[7].in_uop.bits.is_sfb
connect slots_7.io.in_uop.bits.is_jal, issue_slots[7].in_uop.bits.is_jal
connect slots_7.io.in_uop.bits.is_jalr, issue_slots[7].in_uop.bits.is_jalr
connect slots_7.io.in_uop.bits.is_br, issue_slots[7].in_uop.bits.is_br
connect slots_7.io.in_uop.bits.iw_p2_poisoned, issue_slots[7].in_uop.bits.iw_p2_poisoned
connect slots_7.io.in_uop.bits.iw_p1_poisoned, issue_slots[7].in_uop.bits.iw_p1_poisoned
connect slots_7.io.in_uop.bits.iw_state, issue_slots[7].in_uop.bits.iw_state
connect slots_7.io.in_uop.bits.ctrl.is_std, issue_slots[7].in_uop.bits.ctrl.is_std
connect slots_7.io.in_uop.bits.ctrl.is_sta, issue_slots[7].in_uop.bits.ctrl.is_sta
connect slots_7.io.in_uop.bits.ctrl.is_load, issue_slots[7].in_uop.bits.ctrl.is_load
connect slots_7.io.in_uop.bits.ctrl.csr_cmd, issue_slots[7].in_uop.bits.ctrl.csr_cmd
connect slots_7.io.in_uop.bits.ctrl.fcn_dw, issue_slots[7].in_uop.bits.ctrl.fcn_dw
connect slots_7.io.in_uop.bits.ctrl.op_fcn, issue_slots[7].in_uop.bits.ctrl.op_fcn
connect slots_7.io.in_uop.bits.ctrl.imm_sel, issue_slots[7].in_uop.bits.ctrl.imm_sel
connect slots_7.io.in_uop.bits.ctrl.op2_sel, issue_slots[7].in_uop.bits.ctrl.op2_sel
connect slots_7.io.in_uop.bits.ctrl.op1_sel, issue_slots[7].in_uop.bits.ctrl.op1_sel
connect slots_7.io.in_uop.bits.ctrl.br_type, issue_slots[7].in_uop.bits.ctrl.br_type
connect slots_7.io.in_uop.bits.fu_code, issue_slots[7].in_uop.bits.fu_code
connect slots_7.io.in_uop.bits.iq_type, issue_slots[7].in_uop.bits.iq_type
connect slots_7.io.in_uop.bits.debug_pc, issue_slots[7].in_uop.bits.debug_pc
connect slots_7.io.in_uop.bits.is_rvc, issue_slots[7].in_uop.bits.is_rvc
connect slots_7.io.in_uop.bits.debug_inst, issue_slots[7].in_uop.bits.debug_inst
connect slots_7.io.in_uop.bits.inst, issue_slots[7].in_uop.bits.inst
connect slots_7.io.in_uop.bits.uopc, issue_slots[7].in_uop.bits.uopc
connect slots_7.io.in_uop.valid, issue_slots[7].in_uop.valid
connect slots_7.io.spec_ld_wakeup[0].bits, issue_slots[7].spec_ld_wakeup[0].bits
connect slots_7.io.spec_ld_wakeup[0].valid, issue_slots[7].spec_ld_wakeup[0].valid
connect slots_7.io.pred_wakeup_port.bits, issue_slots[7].pred_wakeup_port.bits
connect slots_7.io.pred_wakeup_port.valid, issue_slots[7].pred_wakeup_port.valid
connect slots_7.io.wakeup_ports[0].bits.poisoned, issue_slots[7].wakeup_ports[0].bits.poisoned
connect slots_7.io.wakeup_ports[0].bits.pdst, issue_slots[7].wakeup_ports[0].bits.pdst
connect slots_7.io.wakeup_ports[0].valid, issue_slots[7].wakeup_ports[0].valid
connect slots_7.io.wakeup_ports[1].bits.poisoned, issue_slots[7].wakeup_ports[1].bits.poisoned
connect slots_7.io.wakeup_ports[1].bits.pdst, issue_slots[7].wakeup_ports[1].bits.pdst
connect slots_7.io.wakeup_ports[1].valid, issue_slots[7].wakeup_ports[1].valid
connect slots_7.io.wakeup_ports[2].bits.poisoned, issue_slots[7].wakeup_ports[2].bits.poisoned
connect slots_7.io.wakeup_ports[2].bits.pdst, issue_slots[7].wakeup_ports[2].bits.pdst
connect slots_7.io.wakeup_ports[2].valid, issue_slots[7].wakeup_ports[2].valid
connect slots_7.io.ldspec_miss, issue_slots[7].ldspec_miss
connect slots_7.io.clear, issue_slots[7].clear
connect slots_7.io.kill, issue_slots[7].kill
connect slots_7.io.brupdate.b2.target_offset, issue_slots[7].brupdate.b2.target_offset
connect slots_7.io.brupdate.b2.jalr_target, issue_slots[7].brupdate.b2.jalr_target
connect slots_7.io.brupdate.b2.pc_sel, issue_slots[7].brupdate.b2.pc_sel
connect slots_7.io.brupdate.b2.cfi_type, issue_slots[7].brupdate.b2.cfi_type
connect slots_7.io.brupdate.b2.taken, issue_slots[7].brupdate.b2.taken
connect slots_7.io.brupdate.b2.mispredict, issue_slots[7].brupdate.b2.mispredict
connect slots_7.io.brupdate.b2.valid, issue_slots[7].brupdate.b2.valid
connect slots_7.io.brupdate.b2.uop.debug_tsrc, issue_slots[7].brupdate.b2.uop.debug_tsrc
connect slots_7.io.brupdate.b2.uop.debug_fsrc, issue_slots[7].brupdate.b2.uop.debug_fsrc
connect slots_7.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[7].brupdate.b2.uop.bp_xcpt_if
connect slots_7.io.brupdate.b2.uop.bp_debug_if, issue_slots[7].brupdate.b2.uop.bp_debug_if
connect slots_7.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[7].brupdate.b2.uop.xcpt_ma_if
connect slots_7.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[7].brupdate.b2.uop.xcpt_ae_if
connect slots_7.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[7].brupdate.b2.uop.xcpt_pf_if
connect slots_7.io.brupdate.b2.uop.fp_single, issue_slots[7].brupdate.b2.uop.fp_single
connect slots_7.io.brupdate.b2.uop.fp_val, issue_slots[7].brupdate.b2.uop.fp_val
connect slots_7.io.brupdate.b2.uop.frs3_en, issue_slots[7].brupdate.b2.uop.frs3_en
connect slots_7.io.brupdate.b2.uop.lrs2_rtype, issue_slots[7].brupdate.b2.uop.lrs2_rtype
connect slots_7.io.brupdate.b2.uop.lrs1_rtype, issue_slots[7].brupdate.b2.uop.lrs1_rtype
connect slots_7.io.brupdate.b2.uop.dst_rtype, issue_slots[7].brupdate.b2.uop.dst_rtype
connect slots_7.io.brupdate.b2.uop.ldst_val, issue_slots[7].brupdate.b2.uop.ldst_val
connect slots_7.io.brupdate.b2.uop.lrs3, issue_slots[7].brupdate.b2.uop.lrs3
connect slots_7.io.brupdate.b2.uop.lrs2, issue_slots[7].brupdate.b2.uop.lrs2
connect slots_7.io.brupdate.b2.uop.lrs1, issue_slots[7].brupdate.b2.uop.lrs1
connect slots_7.io.brupdate.b2.uop.ldst, issue_slots[7].brupdate.b2.uop.ldst
connect slots_7.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[7].brupdate.b2.uop.ldst_is_rs1
connect slots_7.io.brupdate.b2.uop.flush_on_commit, issue_slots[7].brupdate.b2.uop.flush_on_commit
connect slots_7.io.brupdate.b2.uop.is_unique, issue_slots[7].brupdate.b2.uop.is_unique
connect slots_7.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[7].brupdate.b2.uop.is_sys_pc2epc
connect slots_7.io.brupdate.b2.uop.uses_stq, issue_slots[7].brupdate.b2.uop.uses_stq
connect slots_7.io.brupdate.b2.uop.uses_ldq, issue_slots[7].brupdate.b2.uop.uses_ldq
connect slots_7.io.brupdate.b2.uop.is_amo, issue_slots[7].brupdate.b2.uop.is_amo
connect slots_7.io.brupdate.b2.uop.is_fencei, issue_slots[7].brupdate.b2.uop.is_fencei
connect slots_7.io.brupdate.b2.uop.is_fence, issue_slots[7].brupdate.b2.uop.is_fence
connect slots_7.io.brupdate.b2.uop.mem_signed, issue_slots[7].brupdate.b2.uop.mem_signed
connect slots_7.io.brupdate.b2.uop.mem_size, issue_slots[7].brupdate.b2.uop.mem_size
connect slots_7.io.brupdate.b2.uop.mem_cmd, issue_slots[7].brupdate.b2.uop.mem_cmd
connect slots_7.io.brupdate.b2.uop.bypassable, issue_slots[7].brupdate.b2.uop.bypassable
connect slots_7.io.brupdate.b2.uop.exc_cause, issue_slots[7].brupdate.b2.uop.exc_cause
connect slots_7.io.brupdate.b2.uop.exception, issue_slots[7].brupdate.b2.uop.exception
connect slots_7.io.brupdate.b2.uop.stale_pdst, issue_slots[7].brupdate.b2.uop.stale_pdst
connect slots_7.io.brupdate.b2.uop.ppred_busy, issue_slots[7].brupdate.b2.uop.ppred_busy
connect slots_7.io.brupdate.b2.uop.prs3_busy, issue_slots[7].brupdate.b2.uop.prs3_busy
connect slots_7.io.brupdate.b2.uop.prs2_busy, issue_slots[7].brupdate.b2.uop.prs2_busy
connect slots_7.io.brupdate.b2.uop.prs1_busy, issue_slots[7].brupdate.b2.uop.prs1_busy
connect slots_7.io.brupdate.b2.uop.ppred, issue_slots[7].brupdate.b2.uop.ppred
connect slots_7.io.brupdate.b2.uop.prs3, issue_slots[7].brupdate.b2.uop.prs3
connect slots_7.io.brupdate.b2.uop.prs2, issue_slots[7].brupdate.b2.uop.prs2
connect slots_7.io.brupdate.b2.uop.prs1, issue_slots[7].brupdate.b2.uop.prs1
connect slots_7.io.brupdate.b2.uop.pdst, issue_slots[7].brupdate.b2.uop.pdst
connect slots_7.io.brupdate.b2.uop.rxq_idx, issue_slots[7].brupdate.b2.uop.rxq_idx
connect slots_7.io.brupdate.b2.uop.stq_idx, issue_slots[7].brupdate.b2.uop.stq_idx
connect slots_7.io.brupdate.b2.uop.ldq_idx, issue_slots[7].brupdate.b2.uop.ldq_idx
connect slots_7.io.brupdate.b2.uop.rob_idx, issue_slots[7].brupdate.b2.uop.rob_idx
connect slots_7.io.brupdate.b2.uop.csr_addr, issue_slots[7].brupdate.b2.uop.csr_addr
connect slots_7.io.brupdate.b2.uop.imm_packed, issue_slots[7].brupdate.b2.uop.imm_packed
connect slots_7.io.brupdate.b2.uop.taken, issue_slots[7].brupdate.b2.uop.taken
connect slots_7.io.brupdate.b2.uop.pc_lob, issue_slots[7].brupdate.b2.uop.pc_lob
connect slots_7.io.brupdate.b2.uop.edge_inst, issue_slots[7].brupdate.b2.uop.edge_inst
connect slots_7.io.brupdate.b2.uop.ftq_idx, issue_slots[7].brupdate.b2.uop.ftq_idx
connect slots_7.io.brupdate.b2.uop.br_tag, issue_slots[7].brupdate.b2.uop.br_tag
connect slots_7.io.brupdate.b2.uop.br_mask, issue_slots[7].brupdate.b2.uop.br_mask
connect slots_7.io.brupdate.b2.uop.is_sfb, issue_slots[7].brupdate.b2.uop.is_sfb
connect slots_7.io.brupdate.b2.uop.is_jal, issue_slots[7].brupdate.b2.uop.is_jal
connect slots_7.io.brupdate.b2.uop.is_jalr, issue_slots[7].brupdate.b2.uop.is_jalr
connect slots_7.io.brupdate.b2.uop.is_br, issue_slots[7].brupdate.b2.uop.is_br
connect slots_7.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[7].brupdate.b2.uop.iw_p2_poisoned
connect slots_7.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[7].brupdate.b2.uop.iw_p1_poisoned
connect slots_7.io.brupdate.b2.uop.iw_state, issue_slots[7].brupdate.b2.uop.iw_state
connect slots_7.io.brupdate.b2.uop.ctrl.is_std, issue_slots[7].brupdate.b2.uop.ctrl.is_std
connect slots_7.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[7].brupdate.b2.uop.ctrl.is_sta
connect slots_7.io.brupdate.b2.uop.ctrl.is_load, issue_slots[7].brupdate.b2.uop.ctrl.is_load
connect slots_7.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[7].brupdate.b2.uop.ctrl.csr_cmd
connect slots_7.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[7].brupdate.b2.uop.ctrl.fcn_dw
connect slots_7.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[7].brupdate.b2.uop.ctrl.op_fcn
connect slots_7.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[7].brupdate.b2.uop.ctrl.imm_sel
connect slots_7.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[7].brupdate.b2.uop.ctrl.op2_sel
connect slots_7.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[7].brupdate.b2.uop.ctrl.op1_sel
connect slots_7.io.brupdate.b2.uop.ctrl.br_type, issue_slots[7].brupdate.b2.uop.ctrl.br_type
connect slots_7.io.brupdate.b2.uop.fu_code, issue_slots[7].brupdate.b2.uop.fu_code
connect slots_7.io.brupdate.b2.uop.iq_type, issue_slots[7].brupdate.b2.uop.iq_type
connect slots_7.io.brupdate.b2.uop.debug_pc, issue_slots[7].brupdate.b2.uop.debug_pc
connect slots_7.io.brupdate.b2.uop.is_rvc, issue_slots[7].brupdate.b2.uop.is_rvc
connect slots_7.io.brupdate.b2.uop.debug_inst, issue_slots[7].brupdate.b2.uop.debug_inst
connect slots_7.io.brupdate.b2.uop.inst, issue_slots[7].brupdate.b2.uop.inst
connect slots_7.io.brupdate.b2.uop.uopc, issue_slots[7].brupdate.b2.uop.uopc
connect slots_7.io.brupdate.b1.mispredict_mask, issue_slots[7].brupdate.b1.mispredict_mask
connect slots_7.io.brupdate.b1.resolve_mask, issue_slots[7].brupdate.b1.resolve_mask
connect slots_7.io.grant, issue_slots[7].grant
connect issue_slots[7].request_hp, slots_7.io.request_hp
connect issue_slots[7].request, slots_7.io.request
connect issue_slots[7].will_be_valid, slots_7.io.will_be_valid
connect issue_slots[7].valid, slots_7.io.valid
connect issue_slots[0].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[0].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[0].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[0].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[0].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[0].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[0].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned
connect issue_slots[0].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst
connect issue_slots[0].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[0].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[0].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[0].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[0].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[0].ldspec_miss, io.ld_miss
connect issue_slots[0].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[0].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[0].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[0].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[0].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[0].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[0].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[0].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[0].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[0].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[0].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[0].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[0].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[0].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[0].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[0].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[0].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[0].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[0].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[0].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[0].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[0].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[0].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[0].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[0].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[0].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[0].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[0].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[0].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[0].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[0].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[0].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[0].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[0].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[0].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[0].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[0].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[0].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[0].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[0].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[0].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[0].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[0].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[0].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[0].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[0].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[0].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[0].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[0].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[0].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[0].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[0].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[0].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[0].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[0].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[0].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[0].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[0].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[0].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[0].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[0].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[0].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[0].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[0].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[0].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[0].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[0].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[0].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[0].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[0].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[0].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[0].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[0].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[0].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[0].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[0].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[0].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[0].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[0].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[0].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[0].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[0].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[0].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[0].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[0].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[0].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[0].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[0].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[0].kill, io.flush_pipeline
connect issue_slots[1].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[1].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[1].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[1].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[1].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[1].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[1].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned
connect issue_slots[1].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst
connect issue_slots[1].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[1].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[1].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[1].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[1].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[1].ldspec_miss, io.ld_miss
connect issue_slots[1].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[1].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[1].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[1].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[1].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[1].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[1].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[1].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[1].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[1].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[1].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[1].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[1].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[1].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[1].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[1].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[1].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[1].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[1].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[1].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[1].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[1].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[1].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[1].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[1].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[1].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[1].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[1].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[1].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[1].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[1].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[1].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[1].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[1].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[1].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[1].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[1].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[1].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[1].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[1].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[1].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[1].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[1].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[1].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[1].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[1].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[1].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[1].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[1].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[1].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[1].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[1].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[1].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[1].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[1].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[1].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[1].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[1].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[1].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[1].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[1].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[1].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[1].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[1].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[1].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[1].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[1].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[1].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[1].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[1].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[1].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[1].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[1].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[1].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[1].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[1].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[1].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[1].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[1].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[1].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[1].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[1].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[1].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[1].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[1].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[1].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[1].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[1].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[1].kill, io.flush_pipeline
connect issue_slots[2].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[2].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[2].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[2].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[2].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[2].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[2].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned
connect issue_slots[2].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst
connect issue_slots[2].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[2].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[2].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[2].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[2].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[2].ldspec_miss, io.ld_miss
connect issue_slots[2].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[2].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[2].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[2].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[2].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[2].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[2].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[2].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[2].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[2].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[2].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[2].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[2].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[2].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[2].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[2].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[2].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[2].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[2].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[2].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[2].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[2].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[2].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[2].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[2].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[2].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[2].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[2].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[2].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[2].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[2].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[2].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[2].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[2].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[2].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[2].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[2].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[2].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[2].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[2].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[2].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[2].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[2].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[2].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[2].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[2].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[2].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[2].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[2].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[2].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[2].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[2].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[2].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[2].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[2].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[2].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[2].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[2].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[2].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[2].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[2].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[2].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[2].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[2].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[2].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[2].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[2].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[2].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[2].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[2].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[2].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[2].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[2].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[2].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[2].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[2].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[2].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[2].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[2].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[2].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[2].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[2].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[2].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[2].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[2].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[2].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[2].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[2].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[2].kill, io.flush_pipeline
connect issue_slots[3].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[3].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[3].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[3].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[3].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[3].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[3].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned
connect issue_slots[3].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst
connect issue_slots[3].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[3].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[3].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[3].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[3].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[3].ldspec_miss, io.ld_miss
connect issue_slots[3].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[3].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[3].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[3].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[3].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[3].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[3].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[3].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[3].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[3].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[3].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[3].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[3].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[3].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[3].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[3].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[3].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[3].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[3].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[3].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[3].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[3].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[3].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[3].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[3].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[3].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[3].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[3].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[3].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[3].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[3].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[3].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[3].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[3].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[3].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[3].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[3].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[3].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[3].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[3].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[3].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[3].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[3].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[3].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[3].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[3].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[3].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[3].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[3].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[3].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[3].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[3].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[3].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[3].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[3].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[3].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[3].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[3].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[3].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[3].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[3].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[3].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[3].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[3].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[3].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[3].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[3].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[3].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[3].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[3].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[3].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[3].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[3].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[3].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[3].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[3].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[3].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[3].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[3].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[3].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[3].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[3].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[3].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[3].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[3].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[3].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[3].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[3].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[3].kill, io.flush_pipeline
connect issue_slots[4].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[4].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[4].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[4].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[4].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[4].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[4].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned
connect issue_slots[4].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst
connect issue_slots[4].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[4].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[4].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[4].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[4].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[4].ldspec_miss, io.ld_miss
connect issue_slots[4].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[4].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[4].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[4].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[4].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[4].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[4].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[4].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[4].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[4].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[4].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[4].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[4].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[4].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[4].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[4].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[4].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[4].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[4].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[4].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[4].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[4].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[4].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[4].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[4].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[4].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[4].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[4].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[4].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[4].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[4].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[4].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[4].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[4].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[4].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[4].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[4].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[4].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[4].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[4].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[4].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[4].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[4].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[4].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[4].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[4].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[4].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[4].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[4].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[4].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[4].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[4].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[4].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[4].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[4].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[4].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[4].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[4].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[4].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[4].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[4].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[4].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[4].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[4].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[4].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[4].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[4].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[4].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[4].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[4].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[4].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[4].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[4].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[4].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[4].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[4].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[4].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[4].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[4].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[4].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[4].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[4].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[4].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[4].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[4].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[4].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[4].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[4].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[4].kill, io.flush_pipeline
connect issue_slots[5].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[5].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[5].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[5].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[5].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[5].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[5].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned
connect issue_slots[5].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst
connect issue_slots[5].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[5].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[5].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[5].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[5].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[5].ldspec_miss, io.ld_miss
connect issue_slots[5].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[5].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[5].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[5].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[5].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[5].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[5].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[5].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[5].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[5].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[5].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[5].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[5].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[5].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[5].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[5].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[5].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[5].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[5].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[5].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[5].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[5].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[5].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[5].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[5].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[5].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[5].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[5].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[5].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[5].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[5].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[5].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[5].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[5].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[5].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[5].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[5].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[5].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[5].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[5].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[5].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[5].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[5].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[5].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[5].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[5].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[5].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[5].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[5].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[5].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[5].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[5].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[5].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[5].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[5].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[5].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[5].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[5].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[5].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[5].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[5].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[5].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[5].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[5].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[5].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[5].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[5].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[5].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[5].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[5].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[5].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[5].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[5].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[5].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[5].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[5].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[5].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[5].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[5].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[5].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[5].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[5].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[5].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[5].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[5].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[5].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[5].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[5].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[5].kill, io.flush_pipeline
connect issue_slots[6].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[6].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[6].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[6].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[6].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[6].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[6].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned
connect issue_slots[6].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst
connect issue_slots[6].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[6].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[6].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[6].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[6].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[6].ldspec_miss, io.ld_miss
connect issue_slots[6].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[6].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[6].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[6].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[6].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[6].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[6].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[6].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[6].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[6].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[6].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[6].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[6].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[6].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[6].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[6].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[6].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[6].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[6].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[6].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[6].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[6].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[6].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[6].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[6].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[6].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[6].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[6].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[6].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[6].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[6].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[6].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[6].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[6].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[6].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[6].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[6].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[6].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[6].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[6].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[6].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[6].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[6].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[6].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[6].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[6].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[6].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[6].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[6].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[6].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[6].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[6].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[6].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[6].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[6].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[6].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[6].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[6].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[6].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[6].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[6].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[6].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[6].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[6].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[6].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[6].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[6].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[6].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[6].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[6].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[6].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[6].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[6].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[6].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[6].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[6].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[6].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[6].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[6].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[6].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[6].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[6].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[6].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[6].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[6].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[6].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[6].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[6].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[6].kill, io.flush_pipeline
connect issue_slots[7].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned
connect issue_slots[7].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst
connect issue_slots[7].wakeup_ports[0].valid, io.wakeup_ports[0].valid
connect issue_slots[7].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned
connect issue_slots[7].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst
connect issue_slots[7].wakeup_ports[1].valid, io.wakeup_ports[1].valid
connect issue_slots[7].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned
connect issue_slots[7].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst
connect issue_slots[7].wakeup_ports[2].valid, io.wakeup_ports[2].valid
connect issue_slots[7].pred_wakeup_port.bits, io.pred_wakeup_port.bits
connect issue_slots[7].pred_wakeup_port.valid, io.pred_wakeup_port.valid
connect issue_slots[7].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits
connect issue_slots[7].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid
connect issue_slots[7].ldspec_miss, io.ld_miss
connect issue_slots[7].brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect issue_slots[7].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect issue_slots[7].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect issue_slots[7].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect issue_slots[7].brupdate.b2.taken, io.brupdate.b2.taken
connect issue_slots[7].brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect issue_slots[7].brupdate.b2.valid, io.brupdate.b2.valid
connect issue_slots[7].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect issue_slots[7].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect issue_slots[7].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect issue_slots[7].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect issue_slots[7].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect issue_slots[7].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect issue_slots[7].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect issue_slots[7].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect issue_slots[7].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect issue_slots[7].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect issue_slots[7].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect issue_slots[7].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect issue_slots[7].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect issue_slots[7].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect issue_slots[7].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect issue_slots[7].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect issue_slots[7].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect issue_slots[7].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect issue_slots[7].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect issue_slots[7].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect issue_slots[7].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect issue_slots[7].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect issue_slots[7].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect issue_slots[7].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect issue_slots[7].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect issue_slots[7].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect issue_slots[7].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect issue_slots[7].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect issue_slots[7].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect issue_slots[7].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect issue_slots[7].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect issue_slots[7].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect issue_slots[7].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect issue_slots[7].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect issue_slots[7].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect issue_slots[7].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect issue_slots[7].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect issue_slots[7].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect issue_slots[7].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect issue_slots[7].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect issue_slots[7].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect issue_slots[7].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect issue_slots[7].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect issue_slots[7].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect issue_slots[7].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect issue_slots[7].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect issue_slots[7].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect issue_slots[7].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect issue_slots[7].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect issue_slots[7].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect issue_slots[7].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect issue_slots[7].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect issue_slots[7].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect issue_slots[7].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect issue_slots[7].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect issue_slots[7].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect issue_slots[7].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect issue_slots[7].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect issue_slots[7].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect issue_slots[7].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect issue_slots[7].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect issue_slots[7].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect issue_slots[7].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect issue_slots[7].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect issue_slots[7].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect issue_slots[7].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect issue_slots[7].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect issue_slots[7].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect issue_slots[7].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect issue_slots[7].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect issue_slots[7].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect issue_slots[7].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect issue_slots[7].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect issue_slots[7].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect issue_slots[7].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect issue_slots[7].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect issue_slots[7].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect issue_slots[7].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect issue_slots[7].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect issue_slots[7].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect issue_slots[7].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect issue_slots[7].kill, io.flush_pipeline
node _io_event_empty_T = or(issue_slots[0].valid, issue_slots[1].valid)
node _io_event_empty_T_1 = or(_io_event_empty_T, issue_slots[2].valid)
node _io_event_empty_T_2 = or(_io_event_empty_T_1, issue_slots[3].valid)
node _io_event_empty_T_3 = or(_io_event_empty_T_2, issue_slots[4].valid)
node _io_event_empty_T_4 = or(_io_event_empty_T_3, issue_slots[5].valid)
node _io_event_empty_T_5 = or(_io_event_empty_T_4, issue_slots[6].valid)
node _io_event_empty_T_6 = or(_io_event_empty_T_5, issue_slots[7].valid)
node _io_event_empty_T_7 = eq(_io_event_empty_T_6, UInt<1>(0h0))
connect io.event_empty, _io_event_empty_T_7
node _count_T = add(slots_0.io.valid, slots_1.io.valid)
node _count_T_1 = bits(_count_T, 1, 0)
node _count_T_2 = add(slots_2.io.valid, slots_3.io.valid)
node _count_T_3 = bits(_count_T_2, 1, 0)
node _count_T_4 = add(_count_T_1, _count_T_3)
node _count_T_5 = bits(_count_T_4, 2, 0)
node _count_T_6 = add(slots_4.io.valid, slots_5.io.valid)
node _count_T_7 = bits(_count_T_6, 1, 0)
node _count_T_8 = add(slots_6.io.valid, slots_7.io.valid)
node _count_T_9 = bits(_count_T_8, 1, 0)
node _count_T_10 = add(_count_T_7, _count_T_9)
node _count_T_11 = bits(_count_T_10, 2, 0)
node _count_T_12 = add(_count_T_5, _count_T_11)
node count = bits(_count_T_12, 3, 0)
node _T_13 = add(issue_slots[0].grant, issue_slots[1].grant)
node _T_14 = bits(_T_13, 1, 0)
node _T_15 = add(issue_slots[2].grant, issue_slots[3].grant)
node _T_16 = bits(_T_15, 1, 0)
node _T_17 = add(_T_14, _T_16)
node _T_18 = bits(_T_17, 2, 0)
node _T_19 = add(issue_slots[4].grant, issue_slots[5].grant)
node _T_20 = bits(_T_19, 1, 0)
node _T_21 = add(issue_slots[6].grant, issue_slots[7].grant)
node _T_22 = bits(_T_21, 1, 0)
node _T_23 = add(_T_20, _T_22)
node _T_24 = bits(_T_23, 2, 0)
node _T_25 = add(_T_18, _T_24)
node _T_26 = bits(_T_25, 3, 0)
node _T_27 = leq(_T_26, UInt<1>(0h1))
node _T_28 = asUInt(reset)
node _T_29 = eq(_T_28, UInt<1>(0h0))
when _T_29 :
node _T_30 = eq(_T_27, UInt<1>(0h0))
when _T_30 :
printf(clock, UInt<1>(0h1), "Assertion failed: [issue] window giving out too many grants.\n at issue-unit.scala:172 assert (PopCount(issue_slots.map(s => s.grant)) <= issueWidth.U, \"[issue] window giving out too many grants.\")\n") : printf_1
assert(clock, _T_27, UInt<1>(0h1), "") : assert_1
node vacants_0 = eq(issue_slots[0].valid, UInt<1>(0h0))
node vacants_1 = eq(issue_slots[1].valid, UInt<1>(0h0))
node vacants_2 = eq(issue_slots[2].valid, UInt<1>(0h0))
node vacants_3 = eq(issue_slots[3].valid, UInt<1>(0h0))
node vacants_4 = eq(issue_slots[4].valid, UInt<1>(0h0))
node vacants_5 = eq(issue_slots[5].valid, UInt<1>(0h0))
node vacants_6 = eq(issue_slots[6].valid, UInt<1>(0h0))
node vacants_7 = eq(issue_slots[7].valid, UInt<1>(0h0))
node vacants_8 = eq(io.dis_uops[0].valid, UInt<1>(0h0))
wire _WIRE_1 : UInt<1>
wire _WIRE_2 : UInt<1>
wire _WIRE_3 : UInt<1>
wire _WIRE_4 : UInt<1>
wire _WIRE_5 : UInt<1>
wire _WIRE_6 : UInt<1>
wire _WIRE_7 : UInt<1>
wire _WIRE_8 : UInt<1>
wire _WIRE_9 : UInt<1>
connect _WIRE_1, UInt<1>(0h0)
wire next : UInt<1>
connect next, _WIRE_1
node _T_31 = eq(_WIRE_1, UInt<1>(0h0))
node _T_32 = and(_T_31, vacants_0)
when _T_32 :
connect next, UInt<1>(0h1)
else :
node _T_33 = bits(_WIRE_1, 0, 0)
node _T_34 = eq(_T_33, UInt<1>(0h0))
node _T_35 = and(_T_34, vacants_0)
when _T_35 :
node _next_T = dshl(_WIRE_1, UInt<1>(0h1))
connect next, _next_T
connect _WIRE_2, next
wire next_1 : UInt<1>
connect next_1, _WIRE_2
node _T_36 = eq(_WIRE_2, UInt<1>(0h0))
node _T_37 = and(_T_36, vacants_1)
when _T_37 :
connect next_1, UInt<1>(0h1)
else :
node _T_38 = bits(_WIRE_2, 0, 0)
node _T_39 = eq(_T_38, UInt<1>(0h0))
node _T_40 = and(_T_39, vacants_1)
when _T_40 :
node _next_T_1 = dshl(_WIRE_2, UInt<1>(0h1))
connect next_1, _next_T_1
connect _WIRE_3, next_1
wire next_2 : UInt<1>
connect next_2, _WIRE_3
node _T_41 = eq(_WIRE_3, UInt<1>(0h0))
node _T_42 = and(_T_41, vacants_2)
when _T_42 :
connect next_2, UInt<1>(0h1)
else :
node _T_43 = bits(_WIRE_3, 0, 0)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = and(_T_44, vacants_2)
when _T_45 :
node _next_T_2 = dshl(_WIRE_3, UInt<1>(0h1))
connect next_2, _next_T_2
connect _WIRE_4, next_2
wire next_3 : UInt<1>
connect next_3, _WIRE_4
node _T_46 = eq(_WIRE_4, UInt<1>(0h0))
node _T_47 = and(_T_46, vacants_3)
when _T_47 :
connect next_3, UInt<1>(0h1)
else :
node _T_48 = bits(_WIRE_4, 0, 0)
node _T_49 = eq(_T_48, UInt<1>(0h0))
node _T_50 = and(_T_49, vacants_3)
when _T_50 :
node _next_T_3 = dshl(_WIRE_4, UInt<1>(0h1))
connect next_3, _next_T_3
connect _WIRE_5, next_3
wire next_4 : UInt<1>
connect next_4, _WIRE_5
node _T_51 = eq(_WIRE_5, UInt<1>(0h0))
node _T_52 = and(_T_51, vacants_4)
when _T_52 :
connect next_4, UInt<1>(0h1)
else :
node _T_53 = bits(_WIRE_5, 0, 0)
node _T_54 = eq(_T_53, UInt<1>(0h0))
node _T_55 = and(_T_54, vacants_4)
when _T_55 :
node _next_T_4 = dshl(_WIRE_5, UInt<1>(0h1))
connect next_4, _next_T_4
connect _WIRE_6, next_4
wire next_5 : UInt<1>
connect next_5, _WIRE_6
node _T_56 = eq(_WIRE_6, UInt<1>(0h0))
node _T_57 = and(_T_56, vacants_5)
when _T_57 :
connect next_5, UInt<1>(0h1)
else :
node _T_58 = bits(_WIRE_6, 0, 0)
node _T_59 = eq(_T_58, UInt<1>(0h0))
node _T_60 = and(_T_59, vacants_5)
when _T_60 :
node _next_T_5 = dshl(_WIRE_6, UInt<1>(0h1))
connect next_5, _next_T_5
connect _WIRE_7, next_5
wire next_6 : UInt<1>
connect next_6, _WIRE_7
node _T_61 = eq(_WIRE_7, UInt<1>(0h0))
node _T_62 = and(_T_61, vacants_6)
when _T_62 :
connect next_6, UInt<1>(0h1)
else :
node _T_63 = bits(_WIRE_7, 0, 0)
node _T_64 = eq(_T_63, UInt<1>(0h0))
node _T_65 = and(_T_64, vacants_6)
when _T_65 :
node _next_T_6 = dshl(_WIRE_7, UInt<1>(0h1))
connect next_6, _next_T_6
connect _WIRE_8, next_6
wire next_7 : UInt<1>
connect next_7, _WIRE_8
node _T_66 = eq(_WIRE_8, UInt<1>(0h0))
node _T_67 = and(_T_66, vacants_7)
when _T_67 :
connect next_7, UInt<1>(0h1)
else :
node _T_68 = bits(_WIRE_8, 0, 0)
node _T_69 = eq(_T_68, UInt<1>(0h0))
node _T_70 = and(_T_69, vacants_7)
when _T_70 :
node _next_T_7 = dshl(_WIRE_8, UInt<1>(0h1))
connect next_7, _next_T_7
connect _WIRE_9, next_7
node _will_be_valid_T = eq(_WIRE.exception, UInt<1>(0h0))
node _will_be_valid_T_1 = and(io.dis_uops[0].valid, _will_be_valid_T)
node _will_be_valid_T_2 = eq(_WIRE.is_fence, UInt<1>(0h0))
node _will_be_valid_T_3 = and(_will_be_valid_T_1, _will_be_valid_T_2)
node _will_be_valid_T_4 = eq(_WIRE.is_fencei, UInt<1>(0h0))
node will_be_valid_8 = and(_will_be_valid_T_3, _will_be_valid_T_4)
connect issue_slots[0].in_uop.valid, UInt<1>(0h0)
connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[1].out_uop.debug_tsrc
connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[1].out_uop.debug_fsrc
connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[1].out_uop.bp_xcpt_if
connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[1].out_uop.bp_debug_if
connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[1].out_uop.xcpt_ma_if
connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[1].out_uop.xcpt_ae_if
connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[1].out_uop.xcpt_pf_if
connect issue_slots[0].in_uop.bits.fp_single, issue_slots[1].out_uop.fp_single
connect issue_slots[0].in_uop.bits.fp_val, issue_slots[1].out_uop.fp_val
connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[1].out_uop.frs3_en
connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[1].out_uop.lrs2_rtype
connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[1].out_uop.lrs1_rtype
connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[1].out_uop.dst_rtype
connect issue_slots[0].in_uop.bits.ldst_val, issue_slots[1].out_uop.ldst_val
connect issue_slots[0].in_uop.bits.lrs3, issue_slots[1].out_uop.lrs3
connect issue_slots[0].in_uop.bits.lrs2, issue_slots[1].out_uop.lrs2
connect issue_slots[0].in_uop.bits.lrs1, issue_slots[1].out_uop.lrs1
connect issue_slots[0].in_uop.bits.ldst, issue_slots[1].out_uop.ldst
connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[1].out_uop.ldst_is_rs1
connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[1].out_uop.flush_on_commit
connect issue_slots[0].in_uop.bits.is_unique, issue_slots[1].out_uop.is_unique
connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[1].out_uop.is_sys_pc2epc
connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[1].out_uop.uses_stq
connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[1].out_uop.uses_ldq
connect issue_slots[0].in_uop.bits.is_amo, issue_slots[1].out_uop.is_amo
connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[1].out_uop.is_fencei
connect issue_slots[0].in_uop.bits.is_fence, issue_slots[1].out_uop.is_fence
connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[1].out_uop.mem_signed
connect issue_slots[0].in_uop.bits.mem_size, issue_slots[1].out_uop.mem_size
connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[1].out_uop.mem_cmd
connect issue_slots[0].in_uop.bits.bypassable, issue_slots[1].out_uop.bypassable
connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[1].out_uop.exc_cause
connect issue_slots[0].in_uop.bits.exception, issue_slots[1].out_uop.exception
connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[1].out_uop.stale_pdst
connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[1].out_uop.ppred_busy
connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[1].out_uop.prs3_busy
connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[1].out_uop.prs2_busy
connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[1].out_uop.prs1_busy
connect issue_slots[0].in_uop.bits.ppred, issue_slots[1].out_uop.ppred
connect issue_slots[0].in_uop.bits.prs3, issue_slots[1].out_uop.prs3
connect issue_slots[0].in_uop.bits.prs2, issue_slots[1].out_uop.prs2
connect issue_slots[0].in_uop.bits.prs1, issue_slots[1].out_uop.prs1
connect issue_slots[0].in_uop.bits.pdst, issue_slots[1].out_uop.pdst
connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[1].out_uop.rxq_idx
connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[1].out_uop.stq_idx
connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[1].out_uop.ldq_idx
connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[1].out_uop.rob_idx
connect issue_slots[0].in_uop.bits.csr_addr, issue_slots[1].out_uop.csr_addr
connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[1].out_uop.imm_packed
connect issue_slots[0].in_uop.bits.taken, issue_slots[1].out_uop.taken
connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[1].out_uop.pc_lob
connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[1].out_uop.edge_inst
connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[1].out_uop.ftq_idx
connect issue_slots[0].in_uop.bits.br_tag, issue_slots[1].out_uop.br_tag
connect issue_slots[0].in_uop.bits.br_mask, issue_slots[1].out_uop.br_mask
connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[1].out_uop.is_sfb
connect issue_slots[0].in_uop.bits.is_jal, issue_slots[1].out_uop.is_jal
connect issue_slots[0].in_uop.bits.is_jalr, issue_slots[1].out_uop.is_jalr
connect issue_slots[0].in_uop.bits.is_br, issue_slots[1].out_uop.is_br
connect issue_slots[0].in_uop.bits.iw_p2_poisoned, issue_slots[1].out_uop.iw_p2_poisoned
connect issue_slots[0].in_uop.bits.iw_p1_poisoned, issue_slots[1].out_uop.iw_p1_poisoned
connect issue_slots[0].in_uop.bits.iw_state, issue_slots[1].out_uop.iw_state
connect issue_slots[0].in_uop.bits.ctrl.is_std, issue_slots[1].out_uop.ctrl.is_std
connect issue_slots[0].in_uop.bits.ctrl.is_sta, issue_slots[1].out_uop.ctrl.is_sta
connect issue_slots[0].in_uop.bits.ctrl.is_load, issue_slots[1].out_uop.ctrl.is_load
connect issue_slots[0].in_uop.bits.ctrl.csr_cmd, issue_slots[1].out_uop.ctrl.csr_cmd
connect issue_slots[0].in_uop.bits.ctrl.fcn_dw, issue_slots[1].out_uop.ctrl.fcn_dw
connect issue_slots[0].in_uop.bits.ctrl.op_fcn, issue_slots[1].out_uop.ctrl.op_fcn
connect issue_slots[0].in_uop.bits.ctrl.imm_sel, issue_slots[1].out_uop.ctrl.imm_sel
connect issue_slots[0].in_uop.bits.ctrl.op2_sel, issue_slots[1].out_uop.ctrl.op2_sel
connect issue_slots[0].in_uop.bits.ctrl.op1_sel, issue_slots[1].out_uop.ctrl.op1_sel
connect issue_slots[0].in_uop.bits.ctrl.br_type, issue_slots[1].out_uop.ctrl.br_type
connect issue_slots[0].in_uop.bits.fu_code, issue_slots[1].out_uop.fu_code
connect issue_slots[0].in_uop.bits.iq_type, issue_slots[1].out_uop.iq_type
connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[1].out_uop.debug_pc
connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[1].out_uop.is_rvc
connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[1].out_uop.debug_inst
connect issue_slots[0].in_uop.bits.inst, issue_slots[1].out_uop.inst
connect issue_slots[0].in_uop.bits.uopc, issue_slots[1].out_uop.uopc
node _T_71 = eq(_WIRE_2, UInt<1>(0h1))
when _T_71 :
connect issue_slots[0].in_uop.valid, issue_slots[1].will_be_valid
connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[1].out_uop.debug_tsrc
connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[1].out_uop.debug_fsrc
connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[1].out_uop.bp_xcpt_if
connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[1].out_uop.bp_debug_if
connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[1].out_uop.xcpt_ma_if
connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[1].out_uop.xcpt_ae_if
connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[1].out_uop.xcpt_pf_if
connect issue_slots[0].in_uop.bits.fp_single, issue_slots[1].out_uop.fp_single
connect issue_slots[0].in_uop.bits.fp_val, issue_slots[1].out_uop.fp_val
connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[1].out_uop.frs3_en
connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[1].out_uop.lrs2_rtype
connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[1].out_uop.lrs1_rtype
connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[1].out_uop.dst_rtype
connect issue_slots[0].in_uop.bits.ldst_val, issue_slots[1].out_uop.ldst_val
connect issue_slots[0].in_uop.bits.lrs3, issue_slots[1].out_uop.lrs3
connect issue_slots[0].in_uop.bits.lrs2, issue_slots[1].out_uop.lrs2
connect issue_slots[0].in_uop.bits.lrs1, issue_slots[1].out_uop.lrs1
connect issue_slots[0].in_uop.bits.ldst, issue_slots[1].out_uop.ldst
connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[1].out_uop.ldst_is_rs1
connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[1].out_uop.flush_on_commit
connect issue_slots[0].in_uop.bits.is_unique, issue_slots[1].out_uop.is_unique
connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[1].out_uop.is_sys_pc2epc
connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[1].out_uop.uses_stq
connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[1].out_uop.uses_ldq
connect issue_slots[0].in_uop.bits.is_amo, issue_slots[1].out_uop.is_amo
connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[1].out_uop.is_fencei
connect issue_slots[0].in_uop.bits.is_fence, issue_slots[1].out_uop.is_fence
connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[1].out_uop.mem_signed
connect issue_slots[0].in_uop.bits.mem_size, issue_slots[1].out_uop.mem_size
connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[1].out_uop.mem_cmd
connect issue_slots[0].in_uop.bits.bypassable, issue_slots[1].out_uop.bypassable
connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[1].out_uop.exc_cause
connect issue_slots[0].in_uop.bits.exception, issue_slots[1].out_uop.exception
connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[1].out_uop.stale_pdst
connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[1].out_uop.ppred_busy
connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[1].out_uop.prs3_busy
connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[1].out_uop.prs2_busy
connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[1].out_uop.prs1_busy
connect issue_slots[0].in_uop.bits.ppred, issue_slots[1].out_uop.ppred
connect issue_slots[0].in_uop.bits.prs3, issue_slots[1].out_uop.prs3
connect issue_slots[0].in_uop.bits.prs2, issue_slots[1].out_uop.prs2
connect issue_slots[0].in_uop.bits.prs1, issue_slots[1].out_uop.prs1
connect issue_slots[0].in_uop.bits.pdst, issue_slots[1].out_uop.pdst
connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[1].out_uop.rxq_idx
connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[1].out_uop.stq_idx
connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[1].out_uop.ldq_idx
connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[1].out_uop.rob_idx
connect issue_slots[0].in_uop.bits.csr_addr, issue_slots[1].out_uop.csr_addr
connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[1].out_uop.imm_packed
connect issue_slots[0].in_uop.bits.taken, issue_slots[1].out_uop.taken
connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[1].out_uop.pc_lob
connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[1].out_uop.edge_inst
connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[1].out_uop.ftq_idx
connect issue_slots[0].in_uop.bits.br_tag, issue_slots[1].out_uop.br_tag
connect issue_slots[0].in_uop.bits.br_mask, issue_slots[1].out_uop.br_mask
connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[1].out_uop.is_sfb
connect issue_slots[0].in_uop.bits.is_jal, issue_slots[1].out_uop.is_jal
connect issue_slots[0].in_uop.bits.is_jalr, issue_slots[1].out_uop.is_jalr
connect issue_slots[0].in_uop.bits.is_br, issue_slots[1].out_uop.is_br
connect issue_slots[0].in_uop.bits.iw_p2_poisoned, issue_slots[1].out_uop.iw_p2_poisoned
connect issue_slots[0].in_uop.bits.iw_p1_poisoned, issue_slots[1].out_uop.iw_p1_poisoned
connect issue_slots[0].in_uop.bits.iw_state, issue_slots[1].out_uop.iw_state
connect issue_slots[0].in_uop.bits.ctrl.is_std, issue_slots[1].out_uop.ctrl.is_std
connect issue_slots[0].in_uop.bits.ctrl.is_sta, issue_slots[1].out_uop.ctrl.is_sta
connect issue_slots[0].in_uop.bits.ctrl.is_load, issue_slots[1].out_uop.ctrl.is_load
connect issue_slots[0].in_uop.bits.ctrl.csr_cmd, issue_slots[1].out_uop.ctrl.csr_cmd
connect issue_slots[0].in_uop.bits.ctrl.fcn_dw, issue_slots[1].out_uop.ctrl.fcn_dw
connect issue_slots[0].in_uop.bits.ctrl.op_fcn, issue_slots[1].out_uop.ctrl.op_fcn
connect issue_slots[0].in_uop.bits.ctrl.imm_sel, issue_slots[1].out_uop.ctrl.imm_sel
connect issue_slots[0].in_uop.bits.ctrl.op2_sel, issue_slots[1].out_uop.ctrl.op2_sel
connect issue_slots[0].in_uop.bits.ctrl.op1_sel, issue_slots[1].out_uop.ctrl.op1_sel
connect issue_slots[0].in_uop.bits.ctrl.br_type, issue_slots[1].out_uop.ctrl.br_type
connect issue_slots[0].in_uop.bits.fu_code, issue_slots[1].out_uop.fu_code
connect issue_slots[0].in_uop.bits.iq_type, issue_slots[1].out_uop.iq_type
connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[1].out_uop.debug_pc
connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[1].out_uop.is_rvc
connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[1].out_uop.debug_inst
connect issue_slots[0].in_uop.bits.inst, issue_slots[1].out_uop.inst
connect issue_slots[0].in_uop.bits.uopc, issue_slots[1].out_uop.uopc
node _issue_slots_0_clear_T = neq(_WIRE_1, UInt<1>(0h0))
connect issue_slots[0].clear, _issue_slots_0_clear_T
connect issue_slots[1].in_uop.valid, UInt<1>(0h0)
connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[2].out_uop.debug_tsrc
connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[2].out_uop.debug_fsrc
connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[2].out_uop.bp_xcpt_if
connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[2].out_uop.bp_debug_if
connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[2].out_uop.xcpt_ma_if
connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[2].out_uop.xcpt_ae_if
connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[2].out_uop.xcpt_pf_if
connect issue_slots[1].in_uop.bits.fp_single, issue_slots[2].out_uop.fp_single
connect issue_slots[1].in_uop.bits.fp_val, issue_slots[2].out_uop.fp_val
connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[2].out_uop.frs3_en
connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[2].out_uop.lrs2_rtype
connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[2].out_uop.lrs1_rtype
connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[2].out_uop.dst_rtype
connect issue_slots[1].in_uop.bits.ldst_val, issue_slots[2].out_uop.ldst_val
connect issue_slots[1].in_uop.bits.lrs3, issue_slots[2].out_uop.lrs3
connect issue_slots[1].in_uop.bits.lrs2, issue_slots[2].out_uop.lrs2
connect issue_slots[1].in_uop.bits.lrs1, issue_slots[2].out_uop.lrs1
connect issue_slots[1].in_uop.bits.ldst, issue_slots[2].out_uop.ldst
connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[2].out_uop.ldst_is_rs1
connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[2].out_uop.flush_on_commit
connect issue_slots[1].in_uop.bits.is_unique, issue_slots[2].out_uop.is_unique
connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[2].out_uop.is_sys_pc2epc
connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[2].out_uop.uses_stq
connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[2].out_uop.uses_ldq
connect issue_slots[1].in_uop.bits.is_amo, issue_slots[2].out_uop.is_amo
connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[2].out_uop.is_fencei
connect issue_slots[1].in_uop.bits.is_fence, issue_slots[2].out_uop.is_fence
connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[2].out_uop.mem_signed
connect issue_slots[1].in_uop.bits.mem_size, issue_slots[2].out_uop.mem_size
connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[2].out_uop.mem_cmd
connect issue_slots[1].in_uop.bits.bypassable, issue_slots[2].out_uop.bypassable
connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[2].out_uop.exc_cause
connect issue_slots[1].in_uop.bits.exception, issue_slots[2].out_uop.exception
connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[2].out_uop.stale_pdst
connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[2].out_uop.ppred_busy
connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[2].out_uop.prs3_busy
connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[2].out_uop.prs2_busy
connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[2].out_uop.prs1_busy
connect issue_slots[1].in_uop.bits.ppred, issue_slots[2].out_uop.ppred
connect issue_slots[1].in_uop.bits.prs3, issue_slots[2].out_uop.prs3
connect issue_slots[1].in_uop.bits.prs2, issue_slots[2].out_uop.prs2
connect issue_slots[1].in_uop.bits.prs1, issue_slots[2].out_uop.prs1
connect issue_slots[1].in_uop.bits.pdst, issue_slots[2].out_uop.pdst
connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[2].out_uop.rxq_idx
connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[2].out_uop.stq_idx
connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[2].out_uop.ldq_idx
connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[2].out_uop.rob_idx
connect issue_slots[1].in_uop.bits.csr_addr, issue_slots[2].out_uop.csr_addr
connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[2].out_uop.imm_packed
connect issue_slots[1].in_uop.bits.taken, issue_slots[2].out_uop.taken
connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[2].out_uop.pc_lob
connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[2].out_uop.edge_inst
connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[2].out_uop.ftq_idx
connect issue_slots[1].in_uop.bits.br_tag, issue_slots[2].out_uop.br_tag
connect issue_slots[1].in_uop.bits.br_mask, issue_slots[2].out_uop.br_mask
connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[2].out_uop.is_sfb
connect issue_slots[1].in_uop.bits.is_jal, issue_slots[2].out_uop.is_jal
connect issue_slots[1].in_uop.bits.is_jalr, issue_slots[2].out_uop.is_jalr
connect issue_slots[1].in_uop.bits.is_br, issue_slots[2].out_uop.is_br
connect issue_slots[1].in_uop.bits.iw_p2_poisoned, issue_slots[2].out_uop.iw_p2_poisoned
connect issue_slots[1].in_uop.bits.iw_p1_poisoned, issue_slots[2].out_uop.iw_p1_poisoned
connect issue_slots[1].in_uop.bits.iw_state, issue_slots[2].out_uop.iw_state
connect issue_slots[1].in_uop.bits.ctrl.is_std, issue_slots[2].out_uop.ctrl.is_std
connect issue_slots[1].in_uop.bits.ctrl.is_sta, issue_slots[2].out_uop.ctrl.is_sta
connect issue_slots[1].in_uop.bits.ctrl.is_load, issue_slots[2].out_uop.ctrl.is_load
connect issue_slots[1].in_uop.bits.ctrl.csr_cmd, issue_slots[2].out_uop.ctrl.csr_cmd
connect issue_slots[1].in_uop.bits.ctrl.fcn_dw, issue_slots[2].out_uop.ctrl.fcn_dw
connect issue_slots[1].in_uop.bits.ctrl.op_fcn, issue_slots[2].out_uop.ctrl.op_fcn
connect issue_slots[1].in_uop.bits.ctrl.imm_sel, issue_slots[2].out_uop.ctrl.imm_sel
connect issue_slots[1].in_uop.bits.ctrl.op2_sel, issue_slots[2].out_uop.ctrl.op2_sel
connect issue_slots[1].in_uop.bits.ctrl.op1_sel, issue_slots[2].out_uop.ctrl.op1_sel
connect issue_slots[1].in_uop.bits.ctrl.br_type, issue_slots[2].out_uop.ctrl.br_type
connect issue_slots[1].in_uop.bits.fu_code, issue_slots[2].out_uop.fu_code
connect issue_slots[1].in_uop.bits.iq_type, issue_slots[2].out_uop.iq_type
connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[2].out_uop.debug_pc
connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[2].out_uop.is_rvc
connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[2].out_uop.debug_inst
connect issue_slots[1].in_uop.bits.inst, issue_slots[2].out_uop.inst
connect issue_slots[1].in_uop.bits.uopc, issue_slots[2].out_uop.uopc
node _T_72 = eq(_WIRE_3, UInt<1>(0h1))
when _T_72 :
connect issue_slots[1].in_uop.valid, issue_slots[2].will_be_valid
connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[2].out_uop.debug_tsrc
connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[2].out_uop.debug_fsrc
connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[2].out_uop.bp_xcpt_if
connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[2].out_uop.bp_debug_if
connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[2].out_uop.xcpt_ma_if
connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[2].out_uop.xcpt_ae_if
connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[2].out_uop.xcpt_pf_if
connect issue_slots[1].in_uop.bits.fp_single, issue_slots[2].out_uop.fp_single
connect issue_slots[1].in_uop.bits.fp_val, issue_slots[2].out_uop.fp_val
connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[2].out_uop.frs3_en
connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[2].out_uop.lrs2_rtype
connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[2].out_uop.lrs1_rtype
connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[2].out_uop.dst_rtype
connect issue_slots[1].in_uop.bits.ldst_val, issue_slots[2].out_uop.ldst_val
connect issue_slots[1].in_uop.bits.lrs3, issue_slots[2].out_uop.lrs3
connect issue_slots[1].in_uop.bits.lrs2, issue_slots[2].out_uop.lrs2
connect issue_slots[1].in_uop.bits.lrs1, issue_slots[2].out_uop.lrs1
connect issue_slots[1].in_uop.bits.ldst, issue_slots[2].out_uop.ldst
connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[2].out_uop.ldst_is_rs1
connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[2].out_uop.flush_on_commit
connect issue_slots[1].in_uop.bits.is_unique, issue_slots[2].out_uop.is_unique
connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[2].out_uop.is_sys_pc2epc
connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[2].out_uop.uses_stq
connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[2].out_uop.uses_ldq
connect issue_slots[1].in_uop.bits.is_amo, issue_slots[2].out_uop.is_amo
connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[2].out_uop.is_fencei
connect issue_slots[1].in_uop.bits.is_fence, issue_slots[2].out_uop.is_fence
connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[2].out_uop.mem_signed
connect issue_slots[1].in_uop.bits.mem_size, issue_slots[2].out_uop.mem_size
connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[2].out_uop.mem_cmd
connect issue_slots[1].in_uop.bits.bypassable, issue_slots[2].out_uop.bypassable
connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[2].out_uop.exc_cause
connect issue_slots[1].in_uop.bits.exception, issue_slots[2].out_uop.exception
connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[2].out_uop.stale_pdst
connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[2].out_uop.ppred_busy
connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[2].out_uop.prs3_busy
connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[2].out_uop.prs2_busy
connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[2].out_uop.prs1_busy
connect issue_slots[1].in_uop.bits.ppred, issue_slots[2].out_uop.ppred
connect issue_slots[1].in_uop.bits.prs3, issue_slots[2].out_uop.prs3
connect issue_slots[1].in_uop.bits.prs2, issue_slots[2].out_uop.prs2
connect issue_slots[1].in_uop.bits.prs1, issue_slots[2].out_uop.prs1
connect issue_slots[1].in_uop.bits.pdst, issue_slots[2].out_uop.pdst
connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[2].out_uop.rxq_idx
connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[2].out_uop.stq_idx
connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[2].out_uop.ldq_idx
connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[2].out_uop.rob_idx
connect issue_slots[1].in_uop.bits.csr_addr, issue_slots[2].out_uop.csr_addr
connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[2].out_uop.imm_packed
connect issue_slots[1].in_uop.bits.taken, issue_slots[2].out_uop.taken
connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[2].out_uop.pc_lob
connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[2].out_uop.edge_inst
connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[2].out_uop.ftq_idx
connect issue_slots[1].in_uop.bits.br_tag, issue_slots[2].out_uop.br_tag
connect issue_slots[1].in_uop.bits.br_mask, issue_slots[2].out_uop.br_mask
connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[2].out_uop.is_sfb
connect issue_slots[1].in_uop.bits.is_jal, issue_slots[2].out_uop.is_jal
connect issue_slots[1].in_uop.bits.is_jalr, issue_slots[2].out_uop.is_jalr
connect issue_slots[1].in_uop.bits.is_br, issue_slots[2].out_uop.is_br
connect issue_slots[1].in_uop.bits.iw_p2_poisoned, issue_slots[2].out_uop.iw_p2_poisoned
connect issue_slots[1].in_uop.bits.iw_p1_poisoned, issue_slots[2].out_uop.iw_p1_poisoned
connect issue_slots[1].in_uop.bits.iw_state, issue_slots[2].out_uop.iw_state
connect issue_slots[1].in_uop.bits.ctrl.is_std, issue_slots[2].out_uop.ctrl.is_std
connect issue_slots[1].in_uop.bits.ctrl.is_sta, issue_slots[2].out_uop.ctrl.is_sta
connect issue_slots[1].in_uop.bits.ctrl.is_load, issue_slots[2].out_uop.ctrl.is_load
connect issue_slots[1].in_uop.bits.ctrl.csr_cmd, issue_slots[2].out_uop.ctrl.csr_cmd
connect issue_slots[1].in_uop.bits.ctrl.fcn_dw, issue_slots[2].out_uop.ctrl.fcn_dw
connect issue_slots[1].in_uop.bits.ctrl.op_fcn, issue_slots[2].out_uop.ctrl.op_fcn
connect issue_slots[1].in_uop.bits.ctrl.imm_sel, issue_slots[2].out_uop.ctrl.imm_sel
connect issue_slots[1].in_uop.bits.ctrl.op2_sel, issue_slots[2].out_uop.ctrl.op2_sel
connect issue_slots[1].in_uop.bits.ctrl.op1_sel, issue_slots[2].out_uop.ctrl.op1_sel
connect issue_slots[1].in_uop.bits.ctrl.br_type, issue_slots[2].out_uop.ctrl.br_type
connect issue_slots[1].in_uop.bits.fu_code, issue_slots[2].out_uop.fu_code
connect issue_slots[1].in_uop.bits.iq_type, issue_slots[2].out_uop.iq_type
connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[2].out_uop.debug_pc
connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[2].out_uop.is_rvc
connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[2].out_uop.debug_inst
connect issue_slots[1].in_uop.bits.inst, issue_slots[2].out_uop.inst
connect issue_slots[1].in_uop.bits.uopc, issue_slots[2].out_uop.uopc
node _issue_slots_1_clear_T = neq(_WIRE_2, UInt<1>(0h0))
connect issue_slots[1].clear, _issue_slots_1_clear_T
connect issue_slots[2].in_uop.valid, UInt<1>(0h0)
connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc
connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc
connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if
connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if
connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if
connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if
connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if
connect issue_slots[2].in_uop.bits.fp_single, issue_slots[3].out_uop.fp_single
connect issue_slots[2].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val
connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en
connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype
connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype
connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype
connect issue_slots[2].in_uop.bits.ldst_val, issue_slots[3].out_uop.ldst_val
connect issue_slots[2].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3
connect issue_slots[2].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2
connect issue_slots[2].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1
connect issue_slots[2].in_uop.bits.ldst, issue_slots[3].out_uop.ldst
connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1
connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit
connect issue_slots[2].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique
connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc
connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq
connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq
connect issue_slots[2].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo
connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei
connect issue_slots[2].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence
connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed
connect issue_slots[2].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size
connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd
connect issue_slots[2].in_uop.bits.bypassable, issue_slots[3].out_uop.bypassable
connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause
connect issue_slots[2].in_uop.bits.exception, issue_slots[3].out_uop.exception
connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst
connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy
connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy
connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy
connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy
connect issue_slots[2].in_uop.bits.ppred, issue_slots[3].out_uop.ppred
connect issue_slots[2].in_uop.bits.prs3, issue_slots[3].out_uop.prs3
connect issue_slots[2].in_uop.bits.prs2, issue_slots[3].out_uop.prs2
connect issue_slots[2].in_uop.bits.prs1, issue_slots[3].out_uop.prs1
connect issue_slots[2].in_uop.bits.pdst, issue_slots[3].out_uop.pdst
connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx
connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx
connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx
connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx
connect issue_slots[2].in_uop.bits.csr_addr, issue_slots[3].out_uop.csr_addr
connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed
connect issue_slots[2].in_uop.bits.taken, issue_slots[3].out_uop.taken
connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob
connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst
connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx
connect issue_slots[2].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag
connect issue_slots[2].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask
connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb
connect issue_slots[2].in_uop.bits.is_jal, issue_slots[3].out_uop.is_jal
connect issue_slots[2].in_uop.bits.is_jalr, issue_slots[3].out_uop.is_jalr
connect issue_slots[2].in_uop.bits.is_br, issue_slots[3].out_uop.is_br
connect issue_slots[2].in_uop.bits.iw_p2_poisoned, issue_slots[3].out_uop.iw_p2_poisoned
connect issue_slots[2].in_uop.bits.iw_p1_poisoned, issue_slots[3].out_uop.iw_p1_poisoned
connect issue_slots[2].in_uop.bits.iw_state, issue_slots[3].out_uop.iw_state
connect issue_slots[2].in_uop.bits.ctrl.is_std, issue_slots[3].out_uop.ctrl.is_std
connect issue_slots[2].in_uop.bits.ctrl.is_sta, issue_slots[3].out_uop.ctrl.is_sta
connect issue_slots[2].in_uop.bits.ctrl.is_load, issue_slots[3].out_uop.ctrl.is_load
connect issue_slots[2].in_uop.bits.ctrl.csr_cmd, issue_slots[3].out_uop.ctrl.csr_cmd
connect issue_slots[2].in_uop.bits.ctrl.fcn_dw, issue_slots[3].out_uop.ctrl.fcn_dw
connect issue_slots[2].in_uop.bits.ctrl.op_fcn, issue_slots[3].out_uop.ctrl.op_fcn
connect issue_slots[2].in_uop.bits.ctrl.imm_sel, issue_slots[3].out_uop.ctrl.imm_sel
connect issue_slots[2].in_uop.bits.ctrl.op2_sel, issue_slots[3].out_uop.ctrl.op2_sel
connect issue_slots[2].in_uop.bits.ctrl.op1_sel, issue_slots[3].out_uop.ctrl.op1_sel
connect issue_slots[2].in_uop.bits.ctrl.br_type, issue_slots[3].out_uop.ctrl.br_type
connect issue_slots[2].in_uop.bits.fu_code, issue_slots[3].out_uop.fu_code
connect issue_slots[2].in_uop.bits.iq_type, issue_slots[3].out_uop.iq_type
connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc
connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc
connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst
connect issue_slots[2].in_uop.bits.inst, issue_slots[3].out_uop.inst
connect issue_slots[2].in_uop.bits.uopc, issue_slots[3].out_uop.uopc
node _T_73 = eq(_WIRE_4, UInt<1>(0h1))
when _T_73 :
connect issue_slots[2].in_uop.valid, issue_slots[3].will_be_valid
connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc
connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc
connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if
connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if
connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if
connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if
connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if
connect issue_slots[2].in_uop.bits.fp_single, issue_slots[3].out_uop.fp_single
connect issue_slots[2].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val
connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en
connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype
connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype
connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype
connect issue_slots[2].in_uop.bits.ldst_val, issue_slots[3].out_uop.ldst_val
connect issue_slots[2].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3
connect issue_slots[2].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2
connect issue_slots[2].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1
connect issue_slots[2].in_uop.bits.ldst, issue_slots[3].out_uop.ldst
connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1
connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit
connect issue_slots[2].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique
connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc
connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq
connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq
connect issue_slots[2].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo
connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei
connect issue_slots[2].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence
connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed
connect issue_slots[2].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size
connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd
connect issue_slots[2].in_uop.bits.bypassable, issue_slots[3].out_uop.bypassable
connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause
connect issue_slots[2].in_uop.bits.exception, issue_slots[3].out_uop.exception
connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst
connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy
connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy
connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy
connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy
connect issue_slots[2].in_uop.bits.ppred, issue_slots[3].out_uop.ppred
connect issue_slots[2].in_uop.bits.prs3, issue_slots[3].out_uop.prs3
connect issue_slots[2].in_uop.bits.prs2, issue_slots[3].out_uop.prs2
connect issue_slots[2].in_uop.bits.prs1, issue_slots[3].out_uop.prs1
connect issue_slots[2].in_uop.bits.pdst, issue_slots[3].out_uop.pdst
connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx
connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx
connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx
connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx
connect issue_slots[2].in_uop.bits.csr_addr, issue_slots[3].out_uop.csr_addr
connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed
connect issue_slots[2].in_uop.bits.taken, issue_slots[3].out_uop.taken
connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob
connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst
connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx
connect issue_slots[2].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag
connect issue_slots[2].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask
connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb
connect issue_slots[2].in_uop.bits.is_jal, issue_slots[3].out_uop.is_jal
connect issue_slots[2].in_uop.bits.is_jalr, issue_slots[3].out_uop.is_jalr
connect issue_slots[2].in_uop.bits.is_br, issue_slots[3].out_uop.is_br
connect issue_slots[2].in_uop.bits.iw_p2_poisoned, issue_slots[3].out_uop.iw_p2_poisoned
connect issue_slots[2].in_uop.bits.iw_p1_poisoned, issue_slots[3].out_uop.iw_p1_poisoned
connect issue_slots[2].in_uop.bits.iw_state, issue_slots[3].out_uop.iw_state
connect issue_slots[2].in_uop.bits.ctrl.is_std, issue_slots[3].out_uop.ctrl.is_std
connect issue_slots[2].in_uop.bits.ctrl.is_sta, issue_slots[3].out_uop.ctrl.is_sta
connect issue_slots[2].in_uop.bits.ctrl.is_load, issue_slots[3].out_uop.ctrl.is_load
connect issue_slots[2].in_uop.bits.ctrl.csr_cmd, issue_slots[3].out_uop.ctrl.csr_cmd
connect issue_slots[2].in_uop.bits.ctrl.fcn_dw, issue_slots[3].out_uop.ctrl.fcn_dw
connect issue_slots[2].in_uop.bits.ctrl.op_fcn, issue_slots[3].out_uop.ctrl.op_fcn
connect issue_slots[2].in_uop.bits.ctrl.imm_sel, issue_slots[3].out_uop.ctrl.imm_sel
connect issue_slots[2].in_uop.bits.ctrl.op2_sel, issue_slots[3].out_uop.ctrl.op2_sel
connect issue_slots[2].in_uop.bits.ctrl.op1_sel, issue_slots[3].out_uop.ctrl.op1_sel
connect issue_slots[2].in_uop.bits.ctrl.br_type, issue_slots[3].out_uop.ctrl.br_type
connect issue_slots[2].in_uop.bits.fu_code, issue_slots[3].out_uop.fu_code
connect issue_slots[2].in_uop.bits.iq_type, issue_slots[3].out_uop.iq_type
connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc
connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc
connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst
connect issue_slots[2].in_uop.bits.inst, issue_slots[3].out_uop.inst
connect issue_slots[2].in_uop.bits.uopc, issue_slots[3].out_uop.uopc
node _issue_slots_2_clear_T = neq(_WIRE_3, UInt<1>(0h0))
connect issue_slots[2].clear, _issue_slots_2_clear_T
connect issue_slots[3].in_uop.valid, UInt<1>(0h0)
connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc
connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc
connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if
connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if
connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if
connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if
connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if
connect issue_slots[3].in_uop.bits.fp_single, issue_slots[4].out_uop.fp_single
connect issue_slots[3].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val
connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en
connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype
connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype
connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype
connect issue_slots[3].in_uop.bits.ldst_val, issue_slots[4].out_uop.ldst_val
connect issue_slots[3].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3
connect issue_slots[3].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2
connect issue_slots[3].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1
connect issue_slots[3].in_uop.bits.ldst, issue_slots[4].out_uop.ldst
connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1
connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit
connect issue_slots[3].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique
connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc
connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq
connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq
connect issue_slots[3].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo
connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei
connect issue_slots[3].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence
connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed
connect issue_slots[3].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size
connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd
connect issue_slots[3].in_uop.bits.bypassable, issue_slots[4].out_uop.bypassable
connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause
connect issue_slots[3].in_uop.bits.exception, issue_slots[4].out_uop.exception
connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst
connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy
connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy
connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy
connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy
connect issue_slots[3].in_uop.bits.ppred, issue_slots[4].out_uop.ppred
connect issue_slots[3].in_uop.bits.prs3, issue_slots[4].out_uop.prs3
connect issue_slots[3].in_uop.bits.prs2, issue_slots[4].out_uop.prs2
connect issue_slots[3].in_uop.bits.prs1, issue_slots[4].out_uop.prs1
connect issue_slots[3].in_uop.bits.pdst, issue_slots[4].out_uop.pdst
connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx
connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx
connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx
connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx
connect issue_slots[3].in_uop.bits.csr_addr, issue_slots[4].out_uop.csr_addr
connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed
connect issue_slots[3].in_uop.bits.taken, issue_slots[4].out_uop.taken
connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob
connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst
connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx
connect issue_slots[3].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag
connect issue_slots[3].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask
connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb
connect issue_slots[3].in_uop.bits.is_jal, issue_slots[4].out_uop.is_jal
connect issue_slots[3].in_uop.bits.is_jalr, issue_slots[4].out_uop.is_jalr
connect issue_slots[3].in_uop.bits.is_br, issue_slots[4].out_uop.is_br
connect issue_slots[3].in_uop.bits.iw_p2_poisoned, issue_slots[4].out_uop.iw_p2_poisoned
connect issue_slots[3].in_uop.bits.iw_p1_poisoned, issue_slots[4].out_uop.iw_p1_poisoned
connect issue_slots[3].in_uop.bits.iw_state, issue_slots[4].out_uop.iw_state
connect issue_slots[3].in_uop.bits.ctrl.is_std, issue_slots[4].out_uop.ctrl.is_std
connect issue_slots[3].in_uop.bits.ctrl.is_sta, issue_slots[4].out_uop.ctrl.is_sta
connect issue_slots[3].in_uop.bits.ctrl.is_load, issue_slots[4].out_uop.ctrl.is_load
connect issue_slots[3].in_uop.bits.ctrl.csr_cmd, issue_slots[4].out_uop.ctrl.csr_cmd
connect issue_slots[3].in_uop.bits.ctrl.fcn_dw, issue_slots[4].out_uop.ctrl.fcn_dw
connect issue_slots[3].in_uop.bits.ctrl.op_fcn, issue_slots[4].out_uop.ctrl.op_fcn
connect issue_slots[3].in_uop.bits.ctrl.imm_sel, issue_slots[4].out_uop.ctrl.imm_sel
connect issue_slots[3].in_uop.bits.ctrl.op2_sel, issue_slots[4].out_uop.ctrl.op2_sel
connect issue_slots[3].in_uop.bits.ctrl.op1_sel, issue_slots[4].out_uop.ctrl.op1_sel
connect issue_slots[3].in_uop.bits.ctrl.br_type, issue_slots[4].out_uop.ctrl.br_type
connect issue_slots[3].in_uop.bits.fu_code, issue_slots[4].out_uop.fu_code
connect issue_slots[3].in_uop.bits.iq_type, issue_slots[4].out_uop.iq_type
connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc
connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc
connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst
connect issue_slots[3].in_uop.bits.inst, issue_slots[4].out_uop.inst
connect issue_slots[3].in_uop.bits.uopc, issue_slots[4].out_uop.uopc
node _T_74 = eq(_WIRE_5, UInt<1>(0h1))
when _T_74 :
connect issue_slots[3].in_uop.valid, issue_slots[4].will_be_valid
connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc
connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc
connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if
connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if
connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if
connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if
connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if
connect issue_slots[3].in_uop.bits.fp_single, issue_slots[4].out_uop.fp_single
connect issue_slots[3].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val
connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en
connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype
connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype
connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype
connect issue_slots[3].in_uop.bits.ldst_val, issue_slots[4].out_uop.ldst_val
connect issue_slots[3].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3
connect issue_slots[3].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2
connect issue_slots[3].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1
connect issue_slots[3].in_uop.bits.ldst, issue_slots[4].out_uop.ldst
connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1
connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit
connect issue_slots[3].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique
connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc
connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq
connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq
connect issue_slots[3].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo
connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei
connect issue_slots[3].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence
connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed
connect issue_slots[3].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size
connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd
connect issue_slots[3].in_uop.bits.bypassable, issue_slots[4].out_uop.bypassable
connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause
connect issue_slots[3].in_uop.bits.exception, issue_slots[4].out_uop.exception
connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst
connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy
connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy
connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy
connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy
connect issue_slots[3].in_uop.bits.ppred, issue_slots[4].out_uop.ppred
connect issue_slots[3].in_uop.bits.prs3, issue_slots[4].out_uop.prs3
connect issue_slots[3].in_uop.bits.prs2, issue_slots[4].out_uop.prs2
connect issue_slots[3].in_uop.bits.prs1, issue_slots[4].out_uop.prs1
connect issue_slots[3].in_uop.bits.pdst, issue_slots[4].out_uop.pdst
connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx
connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx
connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx
connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx
connect issue_slots[3].in_uop.bits.csr_addr, issue_slots[4].out_uop.csr_addr
connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed
connect issue_slots[3].in_uop.bits.taken, issue_slots[4].out_uop.taken
connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob
connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst
connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx
connect issue_slots[3].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag
connect issue_slots[3].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask
connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb
connect issue_slots[3].in_uop.bits.is_jal, issue_slots[4].out_uop.is_jal
connect issue_slots[3].in_uop.bits.is_jalr, issue_slots[4].out_uop.is_jalr
connect issue_slots[3].in_uop.bits.is_br, issue_slots[4].out_uop.is_br
connect issue_slots[3].in_uop.bits.iw_p2_poisoned, issue_slots[4].out_uop.iw_p2_poisoned
connect issue_slots[3].in_uop.bits.iw_p1_poisoned, issue_slots[4].out_uop.iw_p1_poisoned
connect issue_slots[3].in_uop.bits.iw_state, issue_slots[4].out_uop.iw_state
connect issue_slots[3].in_uop.bits.ctrl.is_std, issue_slots[4].out_uop.ctrl.is_std
connect issue_slots[3].in_uop.bits.ctrl.is_sta, issue_slots[4].out_uop.ctrl.is_sta
connect issue_slots[3].in_uop.bits.ctrl.is_load, issue_slots[4].out_uop.ctrl.is_load
connect issue_slots[3].in_uop.bits.ctrl.csr_cmd, issue_slots[4].out_uop.ctrl.csr_cmd
connect issue_slots[3].in_uop.bits.ctrl.fcn_dw, issue_slots[4].out_uop.ctrl.fcn_dw
connect issue_slots[3].in_uop.bits.ctrl.op_fcn, issue_slots[4].out_uop.ctrl.op_fcn
connect issue_slots[3].in_uop.bits.ctrl.imm_sel, issue_slots[4].out_uop.ctrl.imm_sel
connect issue_slots[3].in_uop.bits.ctrl.op2_sel, issue_slots[4].out_uop.ctrl.op2_sel
connect issue_slots[3].in_uop.bits.ctrl.op1_sel, issue_slots[4].out_uop.ctrl.op1_sel
connect issue_slots[3].in_uop.bits.ctrl.br_type, issue_slots[4].out_uop.ctrl.br_type
connect issue_slots[3].in_uop.bits.fu_code, issue_slots[4].out_uop.fu_code
connect issue_slots[3].in_uop.bits.iq_type, issue_slots[4].out_uop.iq_type
connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc
connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc
connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst
connect issue_slots[3].in_uop.bits.inst, issue_slots[4].out_uop.inst
connect issue_slots[3].in_uop.bits.uopc, issue_slots[4].out_uop.uopc
node _issue_slots_3_clear_T = neq(_WIRE_4, UInt<1>(0h0))
connect issue_slots[3].clear, _issue_slots_3_clear_T
connect issue_slots[4].in_uop.valid, UInt<1>(0h0)
connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc
connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc
connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if
connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if
connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if
connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if
connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if
connect issue_slots[4].in_uop.bits.fp_single, issue_slots[5].out_uop.fp_single
connect issue_slots[4].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val
connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en
connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype
connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype
connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype
connect issue_slots[4].in_uop.bits.ldst_val, issue_slots[5].out_uop.ldst_val
connect issue_slots[4].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3
connect issue_slots[4].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2
connect issue_slots[4].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1
connect issue_slots[4].in_uop.bits.ldst, issue_slots[5].out_uop.ldst
connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1
connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit
connect issue_slots[4].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique
connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc
connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq
connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq
connect issue_slots[4].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo
connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei
connect issue_slots[4].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence
connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed
connect issue_slots[4].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size
connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd
connect issue_slots[4].in_uop.bits.bypassable, issue_slots[5].out_uop.bypassable
connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause
connect issue_slots[4].in_uop.bits.exception, issue_slots[5].out_uop.exception
connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst
connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy
connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy
connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy
connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy
connect issue_slots[4].in_uop.bits.ppred, issue_slots[5].out_uop.ppred
connect issue_slots[4].in_uop.bits.prs3, issue_slots[5].out_uop.prs3
connect issue_slots[4].in_uop.bits.prs2, issue_slots[5].out_uop.prs2
connect issue_slots[4].in_uop.bits.prs1, issue_slots[5].out_uop.prs1
connect issue_slots[4].in_uop.bits.pdst, issue_slots[5].out_uop.pdst
connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx
connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx
connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx
connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx
connect issue_slots[4].in_uop.bits.csr_addr, issue_slots[5].out_uop.csr_addr
connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed
connect issue_slots[4].in_uop.bits.taken, issue_slots[5].out_uop.taken
connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob
connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst
connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx
connect issue_slots[4].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag
connect issue_slots[4].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask
connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb
connect issue_slots[4].in_uop.bits.is_jal, issue_slots[5].out_uop.is_jal
connect issue_slots[4].in_uop.bits.is_jalr, issue_slots[5].out_uop.is_jalr
connect issue_slots[4].in_uop.bits.is_br, issue_slots[5].out_uop.is_br
connect issue_slots[4].in_uop.bits.iw_p2_poisoned, issue_slots[5].out_uop.iw_p2_poisoned
connect issue_slots[4].in_uop.bits.iw_p1_poisoned, issue_slots[5].out_uop.iw_p1_poisoned
connect issue_slots[4].in_uop.bits.iw_state, issue_slots[5].out_uop.iw_state
connect issue_slots[4].in_uop.bits.ctrl.is_std, issue_slots[5].out_uop.ctrl.is_std
connect issue_slots[4].in_uop.bits.ctrl.is_sta, issue_slots[5].out_uop.ctrl.is_sta
connect issue_slots[4].in_uop.bits.ctrl.is_load, issue_slots[5].out_uop.ctrl.is_load
connect issue_slots[4].in_uop.bits.ctrl.csr_cmd, issue_slots[5].out_uop.ctrl.csr_cmd
connect issue_slots[4].in_uop.bits.ctrl.fcn_dw, issue_slots[5].out_uop.ctrl.fcn_dw
connect issue_slots[4].in_uop.bits.ctrl.op_fcn, issue_slots[5].out_uop.ctrl.op_fcn
connect issue_slots[4].in_uop.bits.ctrl.imm_sel, issue_slots[5].out_uop.ctrl.imm_sel
connect issue_slots[4].in_uop.bits.ctrl.op2_sel, issue_slots[5].out_uop.ctrl.op2_sel
connect issue_slots[4].in_uop.bits.ctrl.op1_sel, issue_slots[5].out_uop.ctrl.op1_sel
connect issue_slots[4].in_uop.bits.ctrl.br_type, issue_slots[5].out_uop.ctrl.br_type
connect issue_slots[4].in_uop.bits.fu_code, issue_slots[5].out_uop.fu_code
connect issue_slots[4].in_uop.bits.iq_type, issue_slots[5].out_uop.iq_type
connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc
connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc
connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst
connect issue_slots[4].in_uop.bits.inst, issue_slots[5].out_uop.inst
connect issue_slots[4].in_uop.bits.uopc, issue_slots[5].out_uop.uopc
node _T_75 = eq(_WIRE_6, UInt<1>(0h1))
when _T_75 :
connect issue_slots[4].in_uop.valid, issue_slots[5].will_be_valid
connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc
connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc
connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if
connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if
connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if
connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if
connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if
connect issue_slots[4].in_uop.bits.fp_single, issue_slots[5].out_uop.fp_single
connect issue_slots[4].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val
connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en
connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype
connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype
connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype
connect issue_slots[4].in_uop.bits.ldst_val, issue_slots[5].out_uop.ldst_val
connect issue_slots[4].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3
connect issue_slots[4].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2
connect issue_slots[4].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1
connect issue_slots[4].in_uop.bits.ldst, issue_slots[5].out_uop.ldst
connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1
connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit
connect issue_slots[4].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique
connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc
connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq
connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq
connect issue_slots[4].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo
connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei
connect issue_slots[4].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence
connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed
connect issue_slots[4].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size
connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd
connect issue_slots[4].in_uop.bits.bypassable, issue_slots[5].out_uop.bypassable
connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause
connect issue_slots[4].in_uop.bits.exception, issue_slots[5].out_uop.exception
connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst
connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy
connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy
connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy
connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy
connect issue_slots[4].in_uop.bits.ppred, issue_slots[5].out_uop.ppred
connect issue_slots[4].in_uop.bits.prs3, issue_slots[5].out_uop.prs3
connect issue_slots[4].in_uop.bits.prs2, issue_slots[5].out_uop.prs2
connect issue_slots[4].in_uop.bits.prs1, issue_slots[5].out_uop.prs1
connect issue_slots[4].in_uop.bits.pdst, issue_slots[5].out_uop.pdst
connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx
connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx
connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx
connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx
connect issue_slots[4].in_uop.bits.csr_addr, issue_slots[5].out_uop.csr_addr
connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed
connect issue_slots[4].in_uop.bits.taken, issue_slots[5].out_uop.taken
connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob
connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst
connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx
connect issue_slots[4].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag
connect issue_slots[4].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask
connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb
connect issue_slots[4].in_uop.bits.is_jal, issue_slots[5].out_uop.is_jal
connect issue_slots[4].in_uop.bits.is_jalr, issue_slots[5].out_uop.is_jalr
connect issue_slots[4].in_uop.bits.is_br, issue_slots[5].out_uop.is_br
connect issue_slots[4].in_uop.bits.iw_p2_poisoned, issue_slots[5].out_uop.iw_p2_poisoned
connect issue_slots[4].in_uop.bits.iw_p1_poisoned, issue_slots[5].out_uop.iw_p1_poisoned
connect issue_slots[4].in_uop.bits.iw_state, issue_slots[5].out_uop.iw_state
connect issue_slots[4].in_uop.bits.ctrl.is_std, issue_slots[5].out_uop.ctrl.is_std
connect issue_slots[4].in_uop.bits.ctrl.is_sta, issue_slots[5].out_uop.ctrl.is_sta
connect issue_slots[4].in_uop.bits.ctrl.is_load, issue_slots[5].out_uop.ctrl.is_load
connect issue_slots[4].in_uop.bits.ctrl.csr_cmd, issue_slots[5].out_uop.ctrl.csr_cmd
connect issue_slots[4].in_uop.bits.ctrl.fcn_dw, issue_slots[5].out_uop.ctrl.fcn_dw
connect issue_slots[4].in_uop.bits.ctrl.op_fcn, issue_slots[5].out_uop.ctrl.op_fcn
connect issue_slots[4].in_uop.bits.ctrl.imm_sel, issue_slots[5].out_uop.ctrl.imm_sel
connect issue_slots[4].in_uop.bits.ctrl.op2_sel, issue_slots[5].out_uop.ctrl.op2_sel
connect issue_slots[4].in_uop.bits.ctrl.op1_sel, issue_slots[5].out_uop.ctrl.op1_sel
connect issue_slots[4].in_uop.bits.ctrl.br_type, issue_slots[5].out_uop.ctrl.br_type
connect issue_slots[4].in_uop.bits.fu_code, issue_slots[5].out_uop.fu_code
connect issue_slots[4].in_uop.bits.iq_type, issue_slots[5].out_uop.iq_type
connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc
connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc
connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst
connect issue_slots[4].in_uop.bits.inst, issue_slots[5].out_uop.inst
connect issue_slots[4].in_uop.bits.uopc, issue_slots[5].out_uop.uopc
node _issue_slots_4_clear_T = neq(_WIRE_5, UInt<1>(0h0))
connect issue_slots[4].clear, _issue_slots_4_clear_T
connect issue_slots[5].in_uop.valid, UInt<1>(0h0)
connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc
connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc
connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if
connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if
connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if
connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if
connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if
connect issue_slots[5].in_uop.bits.fp_single, issue_slots[6].out_uop.fp_single
connect issue_slots[5].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val
connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en
connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype
connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype
connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype
connect issue_slots[5].in_uop.bits.ldst_val, issue_slots[6].out_uop.ldst_val
connect issue_slots[5].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3
connect issue_slots[5].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2
connect issue_slots[5].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1
connect issue_slots[5].in_uop.bits.ldst, issue_slots[6].out_uop.ldst
connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1
connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit
connect issue_slots[5].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique
connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc
connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq
connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq
connect issue_slots[5].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo
connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei
connect issue_slots[5].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence
connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed
connect issue_slots[5].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size
connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd
connect issue_slots[5].in_uop.bits.bypassable, issue_slots[6].out_uop.bypassable
connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause
connect issue_slots[5].in_uop.bits.exception, issue_slots[6].out_uop.exception
connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst
connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy
connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy
connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy
connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy
connect issue_slots[5].in_uop.bits.ppred, issue_slots[6].out_uop.ppred
connect issue_slots[5].in_uop.bits.prs3, issue_slots[6].out_uop.prs3
connect issue_slots[5].in_uop.bits.prs2, issue_slots[6].out_uop.prs2
connect issue_slots[5].in_uop.bits.prs1, issue_slots[6].out_uop.prs1
connect issue_slots[5].in_uop.bits.pdst, issue_slots[6].out_uop.pdst
connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx
connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx
connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx
connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx
connect issue_slots[5].in_uop.bits.csr_addr, issue_slots[6].out_uop.csr_addr
connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed
connect issue_slots[5].in_uop.bits.taken, issue_slots[6].out_uop.taken
connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob
connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst
connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx
connect issue_slots[5].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag
connect issue_slots[5].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask
connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb
connect issue_slots[5].in_uop.bits.is_jal, issue_slots[6].out_uop.is_jal
connect issue_slots[5].in_uop.bits.is_jalr, issue_slots[6].out_uop.is_jalr
connect issue_slots[5].in_uop.bits.is_br, issue_slots[6].out_uop.is_br
connect issue_slots[5].in_uop.bits.iw_p2_poisoned, issue_slots[6].out_uop.iw_p2_poisoned
connect issue_slots[5].in_uop.bits.iw_p1_poisoned, issue_slots[6].out_uop.iw_p1_poisoned
connect issue_slots[5].in_uop.bits.iw_state, issue_slots[6].out_uop.iw_state
connect issue_slots[5].in_uop.bits.ctrl.is_std, issue_slots[6].out_uop.ctrl.is_std
connect issue_slots[5].in_uop.bits.ctrl.is_sta, issue_slots[6].out_uop.ctrl.is_sta
connect issue_slots[5].in_uop.bits.ctrl.is_load, issue_slots[6].out_uop.ctrl.is_load
connect issue_slots[5].in_uop.bits.ctrl.csr_cmd, issue_slots[6].out_uop.ctrl.csr_cmd
connect issue_slots[5].in_uop.bits.ctrl.fcn_dw, issue_slots[6].out_uop.ctrl.fcn_dw
connect issue_slots[5].in_uop.bits.ctrl.op_fcn, issue_slots[6].out_uop.ctrl.op_fcn
connect issue_slots[5].in_uop.bits.ctrl.imm_sel, issue_slots[6].out_uop.ctrl.imm_sel
connect issue_slots[5].in_uop.bits.ctrl.op2_sel, issue_slots[6].out_uop.ctrl.op2_sel
connect issue_slots[5].in_uop.bits.ctrl.op1_sel, issue_slots[6].out_uop.ctrl.op1_sel
connect issue_slots[5].in_uop.bits.ctrl.br_type, issue_slots[6].out_uop.ctrl.br_type
connect issue_slots[5].in_uop.bits.fu_code, issue_slots[6].out_uop.fu_code
connect issue_slots[5].in_uop.bits.iq_type, issue_slots[6].out_uop.iq_type
connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc
connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc
connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst
connect issue_slots[5].in_uop.bits.inst, issue_slots[6].out_uop.inst
connect issue_slots[5].in_uop.bits.uopc, issue_slots[6].out_uop.uopc
node _T_76 = eq(_WIRE_7, UInt<1>(0h1))
when _T_76 :
connect issue_slots[5].in_uop.valid, issue_slots[6].will_be_valid
connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc
connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc
connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if
connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if
connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if
connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if
connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if
connect issue_slots[5].in_uop.bits.fp_single, issue_slots[6].out_uop.fp_single
connect issue_slots[5].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val
connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en
connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype
connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype
connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype
connect issue_slots[5].in_uop.bits.ldst_val, issue_slots[6].out_uop.ldst_val
connect issue_slots[5].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3
connect issue_slots[5].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2
connect issue_slots[5].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1
connect issue_slots[5].in_uop.bits.ldst, issue_slots[6].out_uop.ldst
connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1
connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit
connect issue_slots[5].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique
connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc
connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq
connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq
connect issue_slots[5].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo
connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei
connect issue_slots[5].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence
connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed
connect issue_slots[5].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size
connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd
connect issue_slots[5].in_uop.bits.bypassable, issue_slots[6].out_uop.bypassable
connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause
connect issue_slots[5].in_uop.bits.exception, issue_slots[6].out_uop.exception
connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst
connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy
connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy
connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy
connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy
connect issue_slots[5].in_uop.bits.ppred, issue_slots[6].out_uop.ppred
connect issue_slots[5].in_uop.bits.prs3, issue_slots[6].out_uop.prs3
connect issue_slots[5].in_uop.bits.prs2, issue_slots[6].out_uop.prs2
connect issue_slots[5].in_uop.bits.prs1, issue_slots[6].out_uop.prs1
connect issue_slots[5].in_uop.bits.pdst, issue_slots[6].out_uop.pdst
connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx
connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx
connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx
connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx
connect issue_slots[5].in_uop.bits.csr_addr, issue_slots[6].out_uop.csr_addr
connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed
connect issue_slots[5].in_uop.bits.taken, issue_slots[6].out_uop.taken
connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob
connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst
connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx
connect issue_slots[5].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag
connect issue_slots[5].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask
connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb
connect issue_slots[5].in_uop.bits.is_jal, issue_slots[6].out_uop.is_jal
connect issue_slots[5].in_uop.bits.is_jalr, issue_slots[6].out_uop.is_jalr
connect issue_slots[5].in_uop.bits.is_br, issue_slots[6].out_uop.is_br
connect issue_slots[5].in_uop.bits.iw_p2_poisoned, issue_slots[6].out_uop.iw_p2_poisoned
connect issue_slots[5].in_uop.bits.iw_p1_poisoned, issue_slots[6].out_uop.iw_p1_poisoned
connect issue_slots[5].in_uop.bits.iw_state, issue_slots[6].out_uop.iw_state
connect issue_slots[5].in_uop.bits.ctrl.is_std, issue_slots[6].out_uop.ctrl.is_std
connect issue_slots[5].in_uop.bits.ctrl.is_sta, issue_slots[6].out_uop.ctrl.is_sta
connect issue_slots[5].in_uop.bits.ctrl.is_load, issue_slots[6].out_uop.ctrl.is_load
connect issue_slots[5].in_uop.bits.ctrl.csr_cmd, issue_slots[6].out_uop.ctrl.csr_cmd
connect issue_slots[5].in_uop.bits.ctrl.fcn_dw, issue_slots[6].out_uop.ctrl.fcn_dw
connect issue_slots[5].in_uop.bits.ctrl.op_fcn, issue_slots[6].out_uop.ctrl.op_fcn
connect issue_slots[5].in_uop.bits.ctrl.imm_sel, issue_slots[6].out_uop.ctrl.imm_sel
connect issue_slots[5].in_uop.bits.ctrl.op2_sel, issue_slots[6].out_uop.ctrl.op2_sel
connect issue_slots[5].in_uop.bits.ctrl.op1_sel, issue_slots[6].out_uop.ctrl.op1_sel
connect issue_slots[5].in_uop.bits.ctrl.br_type, issue_slots[6].out_uop.ctrl.br_type
connect issue_slots[5].in_uop.bits.fu_code, issue_slots[6].out_uop.fu_code
connect issue_slots[5].in_uop.bits.iq_type, issue_slots[6].out_uop.iq_type
connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc
connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc
connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst
connect issue_slots[5].in_uop.bits.inst, issue_slots[6].out_uop.inst
connect issue_slots[5].in_uop.bits.uopc, issue_slots[6].out_uop.uopc
node _issue_slots_5_clear_T = neq(_WIRE_6, UInt<1>(0h0))
connect issue_slots[5].clear, _issue_slots_5_clear_T
connect issue_slots[6].in_uop.valid, UInt<1>(0h0)
connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc
connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc
connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if
connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if
connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if
connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if
connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if
connect issue_slots[6].in_uop.bits.fp_single, issue_slots[7].out_uop.fp_single
connect issue_slots[6].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val
connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en
connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype
connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype
connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype
connect issue_slots[6].in_uop.bits.ldst_val, issue_slots[7].out_uop.ldst_val
connect issue_slots[6].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3
connect issue_slots[6].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2
connect issue_slots[6].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1
connect issue_slots[6].in_uop.bits.ldst, issue_slots[7].out_uop.ldst
connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1
connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit
connect issue_slots[6].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique
connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc
connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq
connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq
connect issue_slots[6].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo
connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei
connect issue_slots[6].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence
connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed
connect issue_slots[6].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size
connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd
connect issue_slots[6].in_uop.bits.bypassable, issue_slots[7].out_uop.bypassable
connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause
connect issue_slots[6].in_uop.bits.exception, issue_slots[7].out_uop.exception
connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst
connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy
connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy
connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy
connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy
connect issue_slots[6].in_uop.bits.ppred, issue_slots[7].out_uop.ppred
connect issue_slots[6].in_uop.bits.prs3, issue_slots[7].out_uop.prs3
connect issue_slots[6].in_uop.bits.prs2, issue_slots[7].out_uop.prs2
connect issue_slots[6].in_uop.bits.prs1, issue_slots[7].out_uop.prs1
connect issue_slots[6].in_uop.bits.pdst, issue_slots[7].out_uop.pdst
connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx
connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx
connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx
connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx
connect issue_slots[6].in_uop.bits.csr_addr, issue_slots[7].out_uop.csr_addr
connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed
connect issue_slots[6].in_uop.bits.taken, issue_slots[7].out_uop.taken
connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob
connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst
connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx
connect issue_slots[6].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag
connect issue_slots[6].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask
connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb
connect issue_slots[6].in_uop.bits.is_jal, issue_slots[7].out_uop.is_jal
connect issue_slots[6].in_uop.bits.is_jalr, issue_slots[7].out_uop.is_jalr
connect issue_slots[6].in_uop.bits.is_br, issue_slots[7].out_uop.is_br
connect issue_slots[6].in_uop.bits.iw_p2_poisoned, issue_slots[7].out_uop.iw_p2_poisoned
connect issue_slots[6].in_uop.bits.iw_p1_poisoned, issue_slots[7].out_uop.iw_p1_poisoned
connect issue_slots[6].in_uop.bits.iw_state, issue_slots[7].out_uop.iw_state
connect issue_slots[6].in_uop.bits.ctrl.is_std, issue_slots[7].out_uop.ctrl.is_std
connect issue_slots[6].in_uop.bits.ctrl.is_sta, issue_slots[7].out_uop.ctrl.is_sta
connect issue_slots[6].in_uop.bits.ctrl.is_load, issue_slots[7].out_uop.ctrl.is_load
connect issue_slots[6].in_uop.bits.ctrl.csr_cmd, issue_slots[7].out_uop.ctrl.csr_cmd
connect issue_slots[6].in_uop.bits.ctrl.fcn_dw, issue_slots[7].out_uop.ctrl.fcn_dw
connect issue_slots[6].in_uop.bits.ctrl.op_fcn, issue_slots[7].out_uop.ctrl.op_fcn
connect issue_slots[6].in_uop.bits.ctrl.imm_sel, issue_slots[7].out_uop.ctrl.imm_sel
connect issue_slots[6].in_uop.bits.ctrl.op2_sel, issue_slots[7].out_uop.ctrl.op2_sel
connect issue_slots[6].in_uop.bits.ctrl.op1_sel, issue_slots[7].out_uop.ctrl.op1_sel
connect issue_slots[6].in_uop.bits.ctrl.br_type, issue_slots[7].out_uop.ctrl.br_type
connect issue_slots[6].in_uop.bits.fu_code, issue_slots[7].out_uop.fu_code
connect issue_slots[6].in_uop.bits.iq_type, issue_slots[7].out_uop.iq_type
connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc
connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc
connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst
connect issue_slots[6].in_uop.bits.inst, issue_slots[7].out_uop.inst
connect issue_slots[6].in_uop.bits.uopc, issue_slots[7].out_uop.uopc
node _T_77 = eq(_WIRE_8, UInt<1>(0h1))
when _T_77 :
connect issue_slots[6].in_uop.valid, issue_slots[7].will_be_valid
connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc
connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc
connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if
connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if
connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if
connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if
connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if
connect issue_slots[6].in_uop.bits.fp_single, issue_slots[7].out_uop.fp_single
connect issue_slots[6].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val
connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en
connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype
connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype
connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype
connect issue_slots[6].in_uop.bits.ldst_val, issue_slots[7].out_uop.ldst_val
connect issue_slots[6].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3
connect issue_slots[6].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2
connect issue_slots[6].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1
connect issue_slots[6].in_uop.bits.ldst, issue_slots[7].out_uop.ldst
connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1
connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit
connect issue_slots[6].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique
connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc
connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq
connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq
connect issue_slots[6].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo
connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei
connect issue_slots[6].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence
connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed
connect issue_slots[6].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size
connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd
connect issue_slots[6].in_uop.bits.bypassable, issue_slots[7].out_uop.bypassable
connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause
connect issue_slots[6].in_uop.bits.exception, issue_slots[7].out_uop.exception
connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst
connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy
connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy
connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy
connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy
connect issue_slots[6].in_uop.bits.ppred, issue_slots[7].out_uop.ppred
connect issue_slots[6].in_uop.bits.prs3, issue_slots[7].out_uop.prs3
connect issue_slots[6].in_uop.bits.prs2, issue_slots[7].out_uop.prs2
connect issue_slots[6].in_uop.bits.prs1, issue_slots[7].out_uop.prs1
connect issue_slots[6].in_uop.bits.pdst, issue_slots[7].out_uop.pdst
connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx
connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx
connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx
connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx
connect issue_slots[6].in_uop.bits.csr_addr, issue_slots[7].out_uop.csr_addr
connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed
connect issue_slots[6].in_uop.bits.taken, issue_slots[7].out_uop.taken
connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob
connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst
connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx
connect issue_slots[6].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag
connect issue_slots[6].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask
connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb
connect issue_slots[6].in_uop.bits.is_jal, issue_slots[7].out_uop.is_jal
connect issue_slots[6].in_uop.bits.is_jalr, issue_slots[7].out_uop.is_jalr
connect issue_slots[6].in_uop.bits.is_br, issue_slots[7].out_uop.is_br
connect issue_slots[6].in_uop.bits.iw_p2_poisoned, issue_slots[7].out_uop.iw_p2_poisoned
connect issue_slots[6].in_uop.bits.iw_p1_poisoned, issue_slots[7].out_uop.iw_p1_poisoned
connect issue_slots[6].in_uop.bits.iw_state, issue_slots[7].out_uop.iw_state
connect issue_slots[6].in_uop.bits.ctrl.is_std, issue_slots[7].out_uop.ctrl.is_std
connect issue_slots[6].in_uop.bits.ctrl.is_sta, issue_slots[7].out_uop.ctrl.is_sta
connect issue_slots[6].in_uop.bits.ctrl.is_load, issue_slots[7].out_uop.ctrl.is_load
connect issue_slots[6].in_uop.bits.ctrl.csr_cmd, issue_slots[7].out_uop.ctrl.csr_cmd
connect issue_slots[6].in_uop.bits.ctrl.fcn_dw, issue_slots[7].out_uop.ctrl.fcn_dw
connect issue_slots[6].in_uop.bits.ctrl.op_fcn, issue_slots[7].out_uop.ctrl.op_fcn
connect issue_slots[6].in_uop.bits.ctrl.imm_sel, issue_slots[7].out_uop.ctrl.imm_sel
connect issue_slots[6].in_uop.bits.ctrl.op2_sel, issue_slots[7].out_uop.ctrl.op2_sel
connect issue_slots[6].in_uop.bits.ctrl.op1_sel, issue_slots[7].out_uop.ctrl.op1_sel
connect issue_slots[6].in_uop.bits.ctrl.br_type, issue_slots[7].out_uop.ctrl.br_type
connect issue_slots[6].in_uop.bits.fu_code, issue_slots[7].out_uop.fu_code
connect issue_slots[6].in_uop.bits.iq_type, issue_slots[7].out_uop.iq_type
connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc
connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc
connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst
connect issue_slots[6].in_uop.bits.inst, issue_slots[7].out_uop.inst
connect issue_slots[6].in_uop.bits.uopc, issue_slots[7].out_uop.uopc
node _issue_slots_6_clear_T = neq(_WIRE_7, UInt<1>(0h0))
connect issue_slots[6].clear, _issue_slots_6_clear_T
connect issue_slots[7].in_uop.valid, UInt<1>(0h0)
connect issue_slots[7].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc
connect issue_slots[7].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc
connect issue_slots[7].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if
connect issue_slots[7].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if
connect issue_slots[7].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if
connect issue_slots[7].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if
connect issue_slots[7].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if
connect issue_slots[7].in_uop.bits.fp_single, _WIRE.fp_single
connect issue_slots[7].in_uop.bits.fp_val, _WIRE.fp_val
connect issue_slots[7].in_uop.bits.frs3_en, _WIRE.frs3_en
connect issue_slots[7].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype
connect issue_slots[7].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype
connect issue_slots[7].in_uop.bits.dst_rtype, _WIRE.dst_rtype
connect issue_slots[7].in_uop.bits.ldst_val, _WIRE.ldst_val
connect issue_slots[7].in_uop.bits.lrs3, _WIRE.lrs3
connect issue_slots[7].in_uop.bits.lrs2, _WIRE.lrs2
connect issue_slots[7].in_uop.bits.lrs1, _WIRE.lrs1
connect issue_slots[7].in_uop.bits.ldst, _WIRE.ldst
connect issue_slots[7].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1
connect issue_slots[7].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit
connect issue_slots[7].in_uop.bits.is_unique, _WIRE.is_unique
connect issue_slots[7].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc
connect issue_slots[7].in_uop.bits.uses_stq, _WIRE.uses_stq
connect issue_slots[7].in_uop.bits.uses_ldq, _WIRE.uses_ldq
connect issue_slots[7].in_uop.bits.is_amo, _WIRE.is_amo
connect issue_slots[7].in_uop.bits.is_fencei, _WIRE.is_fencei
connect issue_slots[7].in_uop.bits.is_fence, _WIRE.is_fence
connect issue_slots[7].in_uop.bits.mem_signed, _WIRE.mem_signed
connect issue_slots[7].in_uop.bits.mem_size, _WIRE.mem_size
connect issue_slots[7].in_uop.bits.mem_cmd, _WIRE.mem_cmd
connect issue_slots[7].in_uop.bits.bypassable, _WIRE.bypassable
connect issue_slots[7].in_uop.bits.exc_cause, _WIRE.exc_cause
connect issue_slots[7].in_uop.bits.exception, _WIRE.exception
connect issue_slots[7].in_uop.bits.stale_pdst, _WIRE.stale_pdst
connect issue_slots[7].in_uop.bits.ppred_busy, _WIRE.ppred_busy
connect issue_slots[7].in_uop.bits.prs3_busy, _WIRE.prs3_busy
connect issue_slots[7].in_uop.bits.prs2_busy, _WIRE.prs2_busy
connect issue_slots[7].in_uop.bits.prs1_busy, _WIRE.prs1_busy
connect issue_slots[7].in_uop.bits.ppred, _WIRE.ppred
connect issue_slots[7].in_uop.bits.prs3, _WIRE.prs3
connect issue_slots[7].in_uop.bits.prs2, _WIRE.prs2
connect issue_slots[7].in_uop.bits.prs1, _WIRE.prs1
connect issue_slots[7].in_uop.bits.pdst, _WIRE.pdst
connect issue_slots[7].in_uop.bits.rxq_idx, _WIRE.rxq_idx
connect issue_slots[7].in_uop.bits.stq_idx, _WIRE.stq_idx
connect issue_slots[7].in_uop.bits.ldq_idx, _WIRE.ldq_idx
connect issue_slots[7].in_uop.bits.rob_idx, _WIRE.rob_idx
connect issue_slots[7].in_uop.bits.csr_addr, _WIRE.csr_addr
connect issue_slots[7].in_uop.bits.imm_packed, _WIRE.imm_packed
connect issue_slots[7].in_uop.bits.taken, _WIRE.taken
connect issue_slots[7].in_uop.bits.pc_lob, _WIRE.pc_lob
connect issue_slots[7].in_uop.bits.edge_inst, _WIRE.edge_inst
connect issue_slots[7].in_uop.bits.ftq_idx, _WIRE.ftq_idx
connect issue_slots[7].in_uop.bits.br_tag, _WIRE.br_tag
connect issue_slots[7].in_uop.bits.br_mask, _WIRE.br_mask
connect issue_slots[7].in_uop.bits.is_sfb, _WIRE.is_sfb
connect issue_slots[7].in_uop.bits.is_jal, _WIRE.is_jal
connect issue_slots[7].in_uop.bits.is_jalr, _WIRE.is_jalr
connect issue_slots[7].in_uop.bits.is_br, _WIRE.is_br
connect issue_slots[7].in_uop.bits.iw_p2_poisoned, _WIRE.iw_p2_poisoned
connect issue_slots[7].in_uop.bits.iw_p1_poisoned, _WIRE.iw_p1_poisoned
connect issue_slots[7].in_uop.bits.iw_state, _WIRE.iw_state
connect issue_slots[7].in_uop.bits.ctrl.is_std, _WIRE.ctrl.is_std
connect issue_slots[7].in_uop.bits.ctrl.is_sta, _WIRE.ctrl.is_sta
connect issue_slots[7].in_uop.bits.ctrl.is_load, _WIRE.ctrl.is_load
connect issue_slots[7].in_uop.bits.ctrl.csr_cmd, _WIRE.ctrl.csr_cmd
connect issue_slots[7].in_uop.bits.ctrl.fcn_dw, _WIRE.ctrl.fcn_dw
connect issue_slots[7].in_uop.bits.ctrl.op_fcn, _WIRE.ctrl.op_fcn
connect issue_slots[7].in_uop.bits.ctrl.imm_sel, _WIRE.ctrl.imm_sel
connect issue_slots[7].in_uop.bits.ctrl.op2_sel, _WIRE.ctrl.op2_sel
connect issue_slots[7].in_uop.bits.ctrl.op1_sel, _WIRE.ctrl.op1_sel
connect issue_slots[7].in_uop.bits.ctrl.br_type, _WIRE.ctrl.br_type
connect issue_slots[7].in_uop.bits.fu_code, _WIRE.fu_code
connect issue_slots[7].in_uop.bits.iq_type, _WIRE.iq_type
connect issue_slots[7].in_uop.bits.debug_pc, _WIRE.debug_pc
connect issue_slots[7].in_uop.bits.is_rvc, _WIRE.is_rvc
connect issue_slots[7].in_uop.bits.debug_inst, _WIRE.debug_inst
connect issue_slots[7].in_uop.bits.inst, _WIRE.inst
connect issue_slots[7].in_uop.bits.uopc, _WIRE.uopc
node _T_78 = eq(_WIRE_9, UInt<1>(0h1))
when _T_78 :
connect issue_slots[7].in_uop.valid, will_be_valid_8
connect issue_slots[7].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc
connect issue_slots[7].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc
connect issue_slots[7].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if
connect issue_slots[7].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if
connect issue_slots[7].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if
connect issue_slots[7].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if
connect issue_slots[7].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if
connect issue_slots[7].in_uop.bits.fp_single, _WIRE.fp_single
connect issue_slots[7].in_uop.bits.fp_val, _WIRE.fp_val
connect issue_slots[7].in_uop.bits.frs3_en, _WIRE.frs3_en
connect issue_slots[7].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype
connect issue_slots[7].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype
connect issue_slots[7].in_uop.bits.dst_rtype, _WIRE.dst_rtype
connect issue_slots[7].in_uop.bits.ldst_val, _WIRE.ldst_val
connect issue_slots[7].in_uop.bits.lrs3, _WIRE.lrs3
connect issue_slots[7].in_uop.bits.lrs2, _WIRE.lrs2
connect issue_slots[7].in_uop.bits.lrs1, _WIRE.lrs1
connect issue_slots[7].in_uop.bits.ldst, _WIRE.ldst
connect issue_slots[7].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1
connect issue_slots[7].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit
connect issue_slots[7].in_uop.bits.is_unique, _WIRE.is_unique
connect issue_slots[7].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc
connect issue_slots[7].in_uop.bits.uses_stq, _WIRE.uses_stq
connect issue_slots[7].in_uop.bits.uses_ldq, _WIRE.uses_ldq
connect issue_slots[7].in_uop.bits.is_amo, _WIRE.is_amo
connect issue_slots[7].in_uop.bits.is_fencei, _WIRE.is_fencei
connect issue_slots[7].in_uop.bits.is_fence, _WIRE.is_fence
connect issue_slots[7].in_uop.bits.mem_signed, _WIRE.mem_signed
connect issue_slots[7].in_uop.bits.mem_size, _WIRE.mem_size
connect issue_slots[7].in_uop.bits.mem_cmd, _WIRE.mem_cmd
connect issue_slots[7].in_uop.bits.bypassable, _WIRE.bypassable
connect issue_slots[7].in_uop.bits.exc_cause, _WIRE.exc_cause
connect issue_slots[7].in_uop.bits.exception, _WIRE.exception
connect issue_slots[7].in_uop.bits.stale_pdst, _WIRE.stale_pdst
connect issue_slots[7].in_uop.bits.ppred_busy, _WIRE.ppred_busy
connect issue_slots[7].in_uop.bits.prs3_busy, _WIRE.prs3_busy
connect issue_slots[7].in_uop.bits.prs2_busy, _WIRE.prs2_busy
connect issue_slots[7].in_uop.bits.prs1_busy, _WIRE.prs1_busy
connect issue_slots[7].in_uop.bits.ppred, _WIRE.ppred
connect issue_slots[7].in_uop.bits.prs3, _WIRE.prs3
connect issue_slots[7].in_uop.bits.prs2, _WIRE.prs2
connect issue_slots[7].in_uop.bits.prs1, _WIRE.prs1
connect issue_slots[7].in_uop.bits.pdst, _WIRE.pdst
connect issue_slots[7].in_uop.bits.rxq_idx, _WIRE.rxq_idx
connect issue_slots[7].in_uop.bits.stq_idx, _WIRE.stq_idx
connect issue_slots[7].in_uop.bits.ldq_idx, _WIRE.ldq_idx
connect issue_slots[7].in_uop.bits.rob_idx, _WIRE.rob_idx
connect issue_slots[7].in_uop.bits.csr_addr, _WIRE.csr_addr
connect issue_slots[7].in_uop.bits.imm_packed, _WIRE.imm_packed
connect issue_slots[7].in_uop.bits.taken, _WIRE.taken
connect issue_slots[7].in_uop.bits.pc_lob, _WIRE.pc_lob
connect issue_slots[7].in_uop.bits.edge_inst, _WIRE.edge_inst
connect issue_slots[7].in_uop.bits.ftq_idx, _WIRE.ftq_idx
connect issue_slots[7].in_uop.bits.br_tag, _WIRE.br_tag
connect issue_slots[7].in_uop.bits.br_mask, _WIRE.br_mask
connect issue_slots[7].in_uop.bits.is_sfb, _WIRE.is_sfb
connect issue_slots[7].in_uop.bits.is_jal, _WIRE.is_jal
connect issue_slots[7].in_uop.bits.is_jalr, _WIRE.is_jalr
connect issue_slots[7].in_uop.bits.is_br, _WIRE.is_br
connect issue_slots[7].in_uop.bits.iw_p2_poisoned, _WIRE.iw_p2_poisoned
connect issue_slots[7].in_uop.bits.iw_p1_poisoned, _WIRE.iw_p1_poisoned
connect issue_slots[7].in_uop.bits.iw_state, _WIRE.iw_state
connect issue_slots[7].in_uop.bits.ctrl.is_std, _WIRE.ctrl.is_std
connect issue_slots[7].in_uop.bits.ctrl.is_sta, _WIRE.ctrl.is_sta
connect issue_slots[7].in_uop.bits.ctrl.is_load, _WIRE.ctrl.is_load
connect issue_slots[7].in_uop.bits.ctrl.csr_cmd, _WIRE.ctrl.csr_cmd
connect issue_slots[7].in_uop.bits.ctrl.fcn_dw, _WIRE.ctrl.fcn_dw
connect issue_slots[7].in_uop.bits.ctrl.op_fcn, _WIRE.ctrl.op_fcn
connect issue_slots[7].in_uop.bits.ctrl.imm_sel, _WIRE.ctrl.imm_sel
connect issue_slots[7].in_uop.bits.ctrl.op2_sel, _WIRE.ctrl.op2_sel
connect issue_slots[7].in_uop.bits.ctrl.op1_sel, _WIRE.ctrl.op1_sel
connect issue_slots[7].in_uop.bits.ctrl.br_type, _WIRE.ctrl.br_type
connect issue_slots[7].in_uop.bits.fu_code, _WIRE.fu_code
connect issue_slots[7].in_uop.bits.iq_type, _WIRE.iq_type
connect issue_slots[7].in_uop.bits.debug_pc, _WIRE.debug_pc
connect issue_slots[7].in_uop.bits.is_rvc, _WIRE.is_rvc
connect issue_slots[7].in_uop.bits.debug_inst, _WIRE.debug_inst
connect issue_slots[7].in_uop.bits.inst, _WIRE.inst
connect issue_slots[7].in_uop.bits.uopc, _WIRE.uopc
node _issue_slots_7_clear_T = neq(_WIRE_8, UInt<1>(0h0))
connect issue_slots[7].clear, _issue_slots_7_clear_T
node _will_be_available_T = eq(issue_slots[0].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_1 = or(_will_be_available_T, issue_slots[0].clear)
node _will_be_available_T_2 = eq(issue_slots[0].in_uop.valid, UInt<1>(0h0))
node will_be_available_0 = and(_will_be_available_T_1, _will_be_available_T_2)
node _will_be_available_T_3 = eq(issue_slots[1].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_4 = or(_will_be_available_T_3, issue_slots[1].clear)
node _will_be_available_T_5 = eq(issue_slots[1].in_uop.valid, UInt<1>(0h0))
node will_be_available_1 = and(_will_be_available_T_4, _will_be_available_T_5)
node _will_be_available_T_6 = eq(issue_slots[2].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_7 = or(_will_be_available_T_6, issue_slots[2].clear)
node _will_be_available_T_8 = eq(issue_slots[2].in_uop.valid, UInt<1>(0h0))
node will_be_available_2 = and(_will_be_available_T_7, _will_be_available_T_8)
node _will_be_available_T_9 = eq(issue_slots[3].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_10 = or(_will_be_available_T_9, issue_slots[3].clear)
node _will_be_available_T_11 = eq(issue_slots[3].in_uop.valid, UInt<1>(0h0))
node will_be_available_3 = and(_will_be_available_T_10, _will_be_available_T_11)
node _will_be_available_T_12 = eq(issue_slots[4].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_13 = or(_will_be_available_T_12, issue_slots[4].clear)
node _will_be_available_T_14 = eq(issue_slots[4].in_uop.valid, UInt<1>(0h0))
node will_be_available_4 = and(_will_be_available_T_13, _will_be_available_T_14)
node _will_be_available_T_15 = eq(issue_slots[5].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_16 = or(_will_be_available_T_15, issue_slots[5].clear)
node _will_be_available_T_17 = eq(issue_slots[5].in_uop.valid, UInt<1>(0h0))
node will_be_available_5 = and(_will_be_available_T_16, _will_be_available_T_17)
node _will_be_available_T_18 = eq(issue_slots[6].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_19 = or(_will_be_available_T_18, issue_slots[6].clear)
node _will_be_available_T_20 = eq(issue_slots[6].in_uop.valid, UInt<1>(0h0))
node will_be_available_6 = and(_will_be_available_T_19, _will_be_available_T_20)
node _will_be_available_T_21 = eq(issue_slots[7].will_be_valid, UInt<1>(0h0))
node _will_be_available_T_22 = or(_will_be_available_T_21, issue_slots[7].clear)
node _will_be_available_T_23 = eq(issue_slots[7].in_uop.valid, UInt<1>(0h0))
node will_be_available_7 = and(_will_be_available_T_22, _will_be_available_T_23)
node _num_available_T = add(will_be_available_0, will_be_available_1)
node _num_available_T_1 = bits(_num_available_T, 1, 0)
node _num_available_T_2 = add(will_be_available_2, will_be_available_3)
node _num_available_T_3 = bits(_num_available_T_2, 1, 0)
node _num_available_T_4 = add(_num_available_T_1, _num_available_T_3)
node _num_available_T_5 = bits(_num_available_T_4, 2, 0)
node _num_available_T_6 = add(will_be_available_4, will_be_available_5)
node _num_available_T_7 = bits(_num_available_T_6, 1, 0)
node _num_available_T_8 = add(will_be_available_6, will_be_available_7)
node _num_available_T_9 = bits(_num_available_T_8, 1, 0)
node _num_available_T_10 = add(_num_available_T_7, _num_available_T_9)
node _num_available_T_11 = bits(_num_available_T_10, 2, 0)
node _num_available_T_12 = add(_num_available_T_5, _num_available_T_11)
node num_available = bits(_num_available_T_12, 3, 0)
node _io_dis_uops_0_ready_T = gt(num_available, UInt<1>(0h0))
reg io_dis_uops_0_ready_REG : UInt<1>, clock
connect io_dis_uops_0_ready_REG, _io_dis_uops_0_ready_T
connect io.dis_uops[0].ready, io_dis_uops_0_ready_REG
connect io.iss_valids[0], UInt<1>(0h0)
wire io_iss_uops_0_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate io_iss_uops_0_uop.debug_tsrc
invalidate io_iss_uops_0_uop.debug_fsrc
invalidate io_iss_uops_0_uop.bp_xcpt_if
invalidate io_iss_uops_0_uop.bp_debug_if
invalidate io_iss_uops_0_uop.xcpt_ma_if
invalidate io_iss_uops_0_uop.xcpt_ae_if
invalidate io_iss_uops_0_uop.xcpt_pf_if
invalidate io_iss_uops_0_uop.fp_single
invalidate io_iss_uops_0_uop.fp_val
invalidate io_iss_uops_0_uop.frs3_en
invalidate io_iss_uops_0_uop.lrs2_rtype
invalidate io_iss_uops_0_uop.lrs1_rtype
invalidate io_iss_uops_0_uop.dst_rtype
invalidate io_iss_uops_0_uop.ldst_val
invalidate io_iss_uops_0_uop.lrs3
invalidate io_iss_uops_0_uop.lrs2
invalidate io_iss_uops_0_uop.lrs1
invalidate io_iss_uops_0_uop.ldst
invalidate io_iss_uops_0_uop.ldst_is_rs1
invalidate io_iss_uops_0_uop.flush_on_commit
invalidate io_iss_uops_0_uop.is_unique
invalidate io_iss_uops_0_uop.is_sys_pc2epc
invalidate io_iss_uops_0_uop.uses_stq
invalidate io_iss_uops_0_uop.uses_ldq
invalidate io_iss_uops_0_uop.is_amo
invalidate io_iss_uops_0_uop.is_fencei
invalidate io_iss_uops_0_uop.is_fence
invalidate io_iss_uops_0_uop.mem_signed
invalidate io_iss_uops_0_uop.mem_size
invalidate io_iss_uops_0_uop.mem_cmd
invalidate io_iss_uops_0_uop.bypassable
invalidate io_iss_uops_0_uop.exc_cause
invalidate io_iss_uops_0_uop.exception
invalidate io_iss_uops_0_uop.stale_pdst
invalidate io_iss_uops_0_uop.ppred_busy
invalidate io_iss_uops_0_uop.prs3_busy
invalidate io_iss_uops_0_uop.prs2_busy
invalidate io_iss_uops_0_uop.prs1_busy
invalidate io_iss_uops_0_uop.ppred
invalidate io_iss_uops_0_uop.prs3
invalidate io_iss_uops_0_uop.prs2
invalidate io_iss_uops_0_uop.prs1
invalidate io_iss_uops_0_uop.pdst
invalidate io_iss_uops_0_uop.rxq_idx
invalidate io_iss_uops_0_uop.stq_idx
invalidate io_iss_uops_0_uop.ldq_idx
invalidate io_iss_uops_0_uop.rob_idx
invalidate io_iss_uops_0_uop.csr_addr
invalidate io_iss_uops_0_uop.imm_packed
invalidate io_iss_uops_0_uop.taken
invalidate io_iss_uops_0_uop.pc_lob
invalidate io_iss_uops_0_uop.edge_inst
invalidate io_iss_uops_0_uop.ftq_idx
invalidate io_iss_uops_0_uop.br_tag
invalidate io_iss_uops_0_uop.br_mask
invalidate io_iss_uops_0_uop.is_sfb
invalidate io_iss_uops_0_uop.is_jal
invalidate io_iss_uops_0_uop.is_jalr
invalidate io_iss_uops_0_uop.is_br
invalidate io_iss_uops_0_uop.iw_p2_poisoned
invalidate io_iss_uops_0_uop.iw_p1_poisoned
invalidate io_iss_uops_0_uop.iw_state
invalidate io_iss_uops_0_uop.ctrl.is_std
invalidate io_iss_uops_0_uop.ctrl.is_sta
invalidate io_iss_uops_0_uop.ctrl.is_load
invalidate io_iss_uops_0_uop.ctrl.csr_cmd
invalidate io_iss_uops_0_uop.ctrl.fcn_dw
invalidate io_iss_uops_0_uop.ctrl.op_fcn
invalidate io_iss_uops_0_uop.ctrl.imm_sel
invalidate io_iss_uops_0_uop.ctrl.op2_sel
invalidate io_iss_uops_0_uop.ctrl.op1_sel
invalidate io_iss_uops_0_uop.ctrl.br_type
invalidate io_iss_uops_0_uop.fu_code
invalidate io_iss_uops_0_uop.iq_type
invalidate io_iss_uops_0_uop.debug_pc
invalidate io_iss_uops_0_uop.is_rvc
invalidate io_iss_uops_0_uop.debug_inst
invalidate io_iss_uops_0_uop.inst
invalidate io_iss_uops_0_uop.uopc
connect io_iss_uops_0_uop.uopc, UInt<7>(0h0)
connect io_iss_uops_0_uop.bypassable, UInt<1>(0h0)
connect io_iss_uops_0_uop.fp_val, UInt<1>(0h0)
connect io_iss_uops_0_uop.uses_stq, UInt<1>(0h0)
connect io_iss_uops_0_uop.uses_ldq, UInt<1>(0h0)
connect io_iss_uops_0_uop.pdst, UInt<1>(0h0)
connect io_iss_uops_0_uop.dst_rtype, UInt<2>(0h2)
wire io_iss_uops_0_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate io_iss_uops_0_cs.is_std
invalidate io_iss_uops_0_cs.is_sta
invalidate io_iss_uops_0_cs.is_load
invalidate io_iss_uops_0_cs.csr_cmd
invalidate io_iss_uops_0_cs.fcn_dw
invalidate io_iss_uops_0_cs.op_fcn
invalidate io_iss_uops_0_cs.imm_sel
invalidate io_iss_uops_0_cs.op2_sel
invalidate io_iss_uops_0_cs.op1_sel
invalidate io_iss_uops_0_cs.br_type
connect io_iss_uops_0_cs.br_type, UInt<4>(0h0)
connect io_iss_uops_0_cs.csr_cmd, UInt<3>(0h0)
connect io_iss_uops_0_cs.is_load, UInt<1>(0h0)
connect io_iss_uops_0_cs.is_sta, UInt<1>(0h0)
connect io_iss_uops_0_cs.is_std, UInt<1>(0h0)
connect io_iss_uops_0_uop.ctrl, io_iss_uops_0_cs
connect io.iss_uops[0], io_iss_uops_0_uop
connect io.iss_uops[0].prs1, UInt<1>(0h0)
connect io.iss_uops[0].prs2, UInt<1>(0h0)
connect io.iss_uops[0].prs3, UInt<1>(0h0)
connect io.iss_uops[0].lrs1_rtype, UInt<2>(0h2)
connect io.iss_uops[0].lrs2_rtype, UInt<2>(0h2)
connect issue_slots[0].grant, UInt<1>(0h0)
node _can_allocate_T = and(issue_slots[0].uop.fu_code, io.fu_types[0])
node can_allocate = neq(_can_allocate_T, UInt<1>(0h0))
node _T_79 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_80 = and(issue_slots[0].request, _T_79)
node _T_81 = and(_T_80, can_allocate)
node _T_82 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_83 = and(_T_81, _T_82)
when _T_83 :
connect issue_slots[0].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[0].uop
node _T_84 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_85 = and(issue_slots[0].request, _T_84)
node _T_86 = and(_T_85, can_allocate)
node _T_87 = or(_T_86, UInt<1>(0h0))
node _T_88 = and(issue_slots[0].request, can_allocate)
node _T_89 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_90 = and(_T_88, _T_89)
node _T_91 = or(_T_90, UInt<1>(0h0))
connect issue_slots[1].grant, UInt<1>(0h0)
node _can_allocate_T_1 = and(issue_slots[1].uop.fu_code, io.fu_types[0])
node can_allocate_1 = neq(_can_allocate_T_1, UInt<1>(0h0))
node _T_92 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_93 = and(issue_slots[1].request, _T_92)
node _T_94 = and(_T_93, can_allocate_1)
node _T_95 = eq(_T_87, UInt<1>(0h0))
node _T_96 = and(_T_94, _T_95)
when _T_96 :
connect issue_slots[1].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[1].uop
node _T_97 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_98 = and(issue_slots[1].request, _T_97)
node _T_99 = and(_T_98, can_allocate_1)
node _T_100 = or(_T_99, _T_87)
node _T_101 = and(issue_slots[1].request, can_allocate_1)
node _T_102 = eq(_T_87, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = or(_T_103, UInt<1>(0h0))
connect issue_slots[2].grant, UInt<1>(0h0)
node _can_allocate_T_2 = and(issue_slots[2].uop.fu_code, io.fu_types[0])
node can_allocate_2 = neq(_can_allocate_T_2, UInt<1>(0h0))
node _T_105 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_106 = and(issue_slots[2].request, _T_105)
node _T_107 = and(_T_106, can_allocate_2)
node _T_108 = eq(_T_100, UInt<1>(0h0))
node _T_109 = and(_T_107, _T_108)
when _T_109 :
connect issue_slots[2].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[2].uop
node _T_110 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_111 = and(issue_slots[2].request, _T_110)
node _T_112 = and(_T_111, can_allocate_2)
node _T_113 = or(_T_112, _T_100)
node _T_114 = and(issue_slots[2].request, can_allocate_2)
node _T_115 = eq(_T_100, UInt<1>(0h0))
node _T_116 = and(_T_114, _T_115)
node _T_117 = or(_T_116, UInt<1>(0h0))
connect issue_slots[3].grant, UInt<1>(0h0)
node _can_allocate_T_3 = and(issue_slots[3].uop.fu_code, io.fu_types[0])
node can_allocate_3 = neq(_can_allocate_T_3, UInt<1>(0h0))
node _T_118 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_119 = and(issue_slots[3].request, _T_118)
node _T_120 = and(_T_119, can_allocate_3)
node _T_121 = eq(_T_113, UInt<1>(0h0))
node _T_122 = and(_T_120, _T_121)
when _T_122 :
connect issue_slots[3].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[3].uop
node _T_123 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_124 = and(issue_slots[3].request, _T_123)
node _T_125 = and(_T_124, can_allocate_3)
node _T_126 = or(_T_125, _T_113)
node _T_127 = and(issue_slots[3].request, can_allocate_3)
node _T_128 = eq(_T_113, UInt<1>(0h0))
node _T_129 = and(_T_127, _T_128)
node _T_130 = or(_T_129, UInt<1>(0h0))
connect issue_slots[4].grant, UInt<1>(0h0)
node _can_allocate_T_4 = and(issue_slots[4].uop.fu_code, io.fu_types[0])
node can_allocate_4 = neq(_can_allocate_T_4, UInt<1>(0h0))
node _T_131 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_132 = and(issue_slots[4].request, _T_131)
node _T_133 = and(_T_132, can_allocate_4)
node _T_134 = eq(_T_126, UInt<1>(0h0))
node _T_135 = and(_T_133, _T_134)
when _T_135 :
connect issue_slots[4].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[4].uop
node _T_136 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_137 = and(issue_slots[4].request, _T_136)
node _T_138 = and(_T_137, can_allocate_4)
node _T_139 = or(_T_138, _T_126)
node _T_140 = and(issue_slots[4].request, can_allocate_4)
node _T_141 = eq(_T_126, UInt<1>(0h0))
node _T_142 = and(_T_140, _T_141)
node _T_143 = or(_T_142, UInt<1>(0h0))
connect issue_slots[5].grant, UInt<1>(0h0)
node _can_allocate_T_5 = and(issue_slots[5].uop.fu_code, io.fu_types[0])
node can_allocate_5 = neq(_can_allocate_T_5, UInt<1>(0h0))
node _T_144 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_145 = and(issue_slots[5].request, _T_144)
node _T_146 = and(_T_145, can_allocate_5)
node _T_147 = eq(_T_139, UInt<1>(0h0))
node _T_148 = and(_T_146, _T_147)
when _T_148 :
connect issue_slots[5].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[5].uop
node _T_149 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_150 = and(issue_slots[5].request, _T_149)
node _T_151 = and(_T_150, can_allocate_5)
node _T_152 = or(_T_151, _T_139)
node _T_153 = and(issue_slots[5].request, can_allocate_5)
node _T_154 = eq(_T_139, UInt<1>(0h0))
node _T_155 = and(_T_153, _T_154)
node _T_156 = or(_T_155, UInt<1>(0h0))
connect issue_slots[6].grant, UInt<1>(0h0)
node _can_allocate_T_6 = and(issue_slots[6].uop.fu_code, io.fu_types[0])
node can_allocate_6 = neq(_can_allocate_T_6, UInt<1>(0h0))
node _T_157 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_158 = and(issue_slots[6].request, _T_157)
node _T_159 = and(_T_158, can_allocate_6)
node _T_160 = eq(_T_152, UInt<1>(0h0))
node _T_161 = and(_T_159, _T_160)
when _T_161 :
connect issue_slots[6].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[6].uop
node _T_162 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_163 = and(issue_slots[6].request, _T_162)
node _T_164 = and(_T_163, can_allocate_6)
node _T_165 = or(_T_164, _T_152)
node _T_166 = and(issue_slots[6].request, can_allocate_6)
node _T_167 = eq(_T_152, UInt<1>(0h0))
node _T_168 = and(_T_166, _T_167)
node _T_169 = or(_T_168, UInt<1>(0h0))
connect issue_slots[7].grant, UInt<1>(0h0)
node _can_allocate_T_7 = and(issue_slots[7].uop.fu_code, io.fu_types[0])
node can_allocate_7 = neq(_can_allocate_T_7, UInt<1>(0h0))
node _T_170 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_171 = and(issue_slots[7].request, _T_170)
node _T_172 = and(_T_171, can_allocate_7)
node _T_173 = eq(_T_165, UInt<1>(0h0))
node _T_174 = and(_T_172, _T_173)
when _T_174 :
connect issue_slots[7].grant, UInt<1>(0h1)
connect io.iss_valids[0], UInt<1>(0h1)
connect io.iss_uops[0], issue_slots[7].uop
node _T_175 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_176 = and(issue_slots[7].request, _T_175)
node _T_177 = and(_T_176, can_allocate_7)
node _T_178 = or(_T_177, _T_165)
node _T_179 = and(issue_slots[7].request, can_allocate_7)
node _T_180 = eq(_T_165, UInt<1>(0h0))
node _T_181 = and(_T_179, _T_180)
node _T_182 = or(_T_181, UInt<1>(0h0)) | module IssueUnitCollapsing_4( // @[issue-unit-age-ordered.scala:29:7]
input clock, // @[issue-unit-age-ordered.scala:29:7]
input reset, // @[issue-unit-age-ordered.scala:29:7]
output io_dis_uops_0_ready, // @[issue-unit.scala:112:14]
input io_dis_uops_0_valid, // @[issue-unit.scala:112:14]
input [6:0] io_dis_uops_0_bits_uopc, // @[issue-unit.scala:112:14]
input [31:0] io_dis_uops_0_bits_inst, // @[issue-unit.scala:112:14]
input [31:0] io_dis_uops_0_bits_debug_inst, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_rvc, // @[issue-unit.scala:112:14]
input [39:0] io_dis_uops_0_bits_debug_pc, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_0_bits_iq_type, // @[issue-unit.scala:112:14]
input [9:0] io_dis_uops_0_bits_fu_code, // @[issue-unit.scala:112:14]
input [3:0] io_dis_uops_0_bits_ctrl_br_type, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_ctrl_op1_sel, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_0_bits_ctrl_op2_sel, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_0_bits_ctrl_imm_sel, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_0_bits_ctrl_op_fcn, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_ctrl_fcn_dw, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_0_bits_ctrl_csr_cmd, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_ctrl_is_load, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_ctrl_is_sta, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_ctrl_is_std, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_iw_state, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_iw_p1_poisoned, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_iw_p2_poisoned, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_br, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_jalr, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_jal, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_sfb, // @[issue-unit.scala:112:14]
input [7:0] io_dis_uops_0_bits_br_mask, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_0_bits_br_tag, // @[issue-unit.scala:112:14]
input [3:0] io_dis_uops_0_bits_ftq_idx, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_edge_inst, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_0_bits_pc_lob, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_taken, // @[issue-unit.scala:112:14]
input [19:0] io_dis_uops_0_bits_imm_packed, // @[issue-unit.scala:112:14]
input [11:0] io_dis_uops_0_bits_csr_addr, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_0_bits_rob_idx, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_0_bits_ldq_idx, // @[issue-unit.scala:112:14]
input [2:0] io_dis_uops_0_bits_stq_idx, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_rxq_idx, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_0_bits_pdst, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_0_bits_prs1, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_0_bits_prs2, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_0_bits_prs3, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_prs1_busy, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_prs2_busy, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_prs3_busy, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_0_bits_stale_pdst, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_exception, // @[issue-unit.scala:112:14]
input [63:0] io_dis_uops_0_bits_exc_cause, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_bypassable, // @[issue-unit.scala:112:14]
input [4:0] io_dis_uops_0_bits_mem_cmd, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_mem_size, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_mem_signed, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_fence, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_fencei, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_amo, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_uses_ldq, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_uses_stq, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_sys_pc2epc, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_is_unique, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_flush_on_commit, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_ldst_is_rs1, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_0_bits_ldst, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_0_bits_lrs1, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_0_bits_lrs2, // @[issue-unit.scala:112:14]
input [5:0] io_dis_uops_0_bits_lrs3, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_ldst_val, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_dst_rtype, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_lrs1_rtype, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_lrs2_rtype, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_frs3_en, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_fp_val, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_fp_single, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_xcpt_pf_if, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_xcpt_ae_if, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_xcpt_ma_if, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_bp_debug_if, // @[issue-unit.scala:112:14]
input io_dis_uops_0_bits_bp_xcpt_if, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_debug_fsrc, // @[issue-unit.scala:112:14]
input [1:0] io_dis_uops_0_bits_debug_tsrc, // @[issue-unit.scala:112:14]
output io_iss_valids_0, // @[issue-unit.scala:112:14]
output [6:0] io_iss_uops_0_uopc, // @[issue-unit.scala:112:14]
output [31:0] io_iss_uops_0_inst, // @[issue-unit.scala:112:14]
output [31:0] io_iss_uops_0_debug_inst, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_rvc, // @[issue-unit.scala:112:14]
output [39:0] io_iss_uops_0_debug_pc, // @[issue-unit.scala:112:14]
output [2:0] io_iss_uops_0_iq_type, // @[issue-unit.scala:112:14]
output [9:0] io_iss_uops_0_fu_code, // @[issue-unit.scala:112:14]
output [3:0] io_iss_uops_0_ctrl_br_type, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_ctrl_op1_sel, // @[issue-unit.scala:112:14]
output [2:0] io_iss_uops_0_ctrl_op2_sel, // @[issue-unit.scala:112:14]
output [2:0] io_iss_uops_0_ctrl_imm_sel, // @[issue-unit.scala:112:14]
output [4:0] io_iss_uops_0_ctrl_op_fcn, // @[issue-unit.scala:112:14]
output io_iss_uops_0_ctrl_fcn_dw, // @[issue-unit.scala:112:14]
output [2:0] io_iss_uops_0_ctrl_csr_cmd, // @[issue-unit.scala:112:14]
output io_iss_uops_0_ctrl_is_load, // @[issue-unit.scala:112:14]
output io_iss_uops_0_ctrl_is_sta, // @[issue-unit.scala:112:14]
output io_iss_uops_0_ctrl_is_std, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_iw_state, // @[issue-unit.scala:112:14]
output io_iss_uops_0_iw_p1_poisoned, // @[issue-unit.scala:112:14]
output io_iss_uops_0_iw_p2_poisoned, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_br, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_jalr, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_jal, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_sfb, // @[issue-unit.scala:112:14]
output [7:0] io_iss_uops_0_br_mask, // @[issue-unit.scala:112:14]
output [2:0] io_iss_uops_0_br_tag, // @[issue-unit.scala:112:14]
output [3:0] io_iss_uops_0_ftq_idx, // @[issue-unit.scala:112:14]
output io_iss_uops_0_edge_inst, // @[issue-unit.scala:112:14]
output [5:0] io_iss_uops_0_pc_lob, // @[issue-unit.scala:112:14]
output io_iss_uops_0_taken, // @[issue-unit.scala:112:14]
output [19:0] io_iss_uops_0_imm_packed, // @[issue-unit.scala:112:14]
output [11:0] io_iss_uops_0_csr_addr, // @[issue-unit.scala:112:14]
output [4:0] io_iss_uops_0_rob_idx, // @[issue-unit.scala:112:14]
output [2:0] io_iss_uops_0_ldq_idx, // @[issue-unit.scala:112:14]
output [2:0] io_iss_uops_0_stq_idx, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_rxq_idx, // @[issue-unit.scala:112:14]
output [5:0] io_iss_uops_0_pdst, // @[issue-unit.scala:112:14]
output [5:0] io_iss_uops_0_prs1, // @[issue-unit.scala:112:14]
output [5:0] io_iss_uops_0_prs2, // @[issue-unit.scala:112:14]
output [5:0] io_iss_uops_0_prs3, // @[issue-unit.scala:112:14]
output [3:0] io_iss_uops_0_ppred, // @[issue-unit.scala:112:14]
output io_iss_uops_0_prs1_busy, // @[issue-unit.scala:112:14]
output io_iss_uops_0_prs2_busy, // @[issue-unit.scala:112:14]
output io_iss_uops_0_prs3_busy, // @[issue-unit.scala:112:14]
output io_iss_uops_0_ppred_busy, // @[issue-unit.scala:112:14]
output [5:0] io_iss_uops_0_stale_pdst, // @[issue-unit.scala:112:14]
output io_iss_uops_0_exception, // @[issue-unit.scala:112:14]
output [63:0] io_iss_uops_0_exc_cause, // @[issue-unit.scala:112:14]
output io_iss_uops_0_bypassable, // @[issue-unit.scala:112:14]
output [4:0] io_iss_uops_0_mem_cmd, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_mem_size, // @[issue-unit.scala:112:14]
output io_iss_uops_0_mem_signed, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_fence, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_fencei, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_amo, // @[issue-unit.scala:112:14]
output io_iss_uops_0_uses_ldq, // @[issue-unit.scala:112:14]
output io_iss_uops_0_uses_stq, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_sys_pc2epc, // @[issue-unit.scala:112:14]
output io_iss_uops_0_is_unique, // @[issue-unit.scala:112:14]
output io_iss_uops_0_flush_on_commit, // @[issue-unit.scala:112:14]
output io_iss_uops_0_ldst_is_rs1, // @[issue-unit.scala:112:14]
output [5:0] io_iss_uops_0_ldst, // @[issue-unit.scala:112:14]
output [5:0] io_iss_uops_0_lrs1, // @[issue-unit.scala:112:14]
output [5:0] io_iss_uops_0_lrs2, // @[issue-unit.scala:112:14]
output [5:0] io_iss_uops_0_lrs3, // @[issue-unit.scala:112:14]
output io_iss_uops_0_ldst_val, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_dst_rtype, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_lrs1_rtype, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_lrs2_rtype, // @[issue-unit.scala:112:14]
output io_iss_uops_0_frs3_en, // @[issue-unit.scala:112:14]
output io_iss_uops_0_fp_val, // @[issue-unit.scala:112:14]
output io_iss_uops_0_fp_single, // @[issue-unit.scala:112:14]
output io_iss_uops_0_xcpt_pf_if, // @[issue-unit.scala:112:14]
output io_iss_uops_0_xcpt_ae_if, // @[issue-unit.scala:112:14]
output io_iss_uops_0_xcpt_ma_if, // @[issue-unit.scala:112:14]
output io_iss_uops_0_bp_debug_if, // @[issue-unit.scala:112:14]
output io_iss_uops_0_bp_xcpt_if, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_debug_fsrc, // @[issue-unit.scala:112:14]
output [1:0] io_iss_uops_0_debug_tsrc, // @[issue-unit.scala:112:14]
input io_wakeup_ports_0_valid, // @[issue-unit.scala:112:14]
input [5:0] io_wakeup_ports_0_bits_pdst, // @[issue-unit.scala:112:14]
input io_wakeup_ports_0_bits_poisoned, // @[issue-unit.scala:112:14]
input io_wakeup_ports_1_valid, // @[issue-unit.scala:112:14]
input [5:0] io_wakeup_ports_1_bits_pdst, // @[issue-unit.scala:112:14]
input io_wakeup_ports_1_bits_poisoned, // @[issue-unit.scala:112:14]
input io_wakeup_ports_2_valid, // @[issue-unit.scala:112:14]
input [5:0] io_wakeup_ports_2_bits_pdst, // @[issue-unit.scala:112:14]
input io_wakeup_ports_2_bits_poisoned, // @[issue-unit.scala:112:14]
input io_spec_ld_wakeup_0_valid, // @[issue-unit.scala:112:14]
input [5:0] io_spec_ld_wakeup_0_bits, // @[issue-unit.scala:112:14]
input [9:0] io_fu_types_0, // @[issue-unit.scala:112:14]
input [7:0] io_brupdate_b1_resolve_mask, // @[issue-unit.scala:112:14]
input [7:0] io_brupdate_b1_mispredict_mask, // @[issue-unit.scala:112:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-unit.scala:112:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-unit.scala:112:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-unit.scala:112:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-unit.scala:112:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-unit.scala:112:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-unit.scala:112:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-unit.scala:112:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-unit.scala:112:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-unit.scala:112:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-unit.scala:112:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_br, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_jal, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-unit.scala:112:14]
input [7:0] io_brupdate_b2_uop_br_mask, // @[issue-unit.scala:112:14]
input [2:0] io_brupdate_b2_uop_br_tag, // @[issue-unit.scala:112:14]
input [3:0] io_brupdate_b2_uop_ftq_idx, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-unit.scala:112:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_taken, // @[issue-unit.scala:112:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-unit.scala:112:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-unit.scala:112:14]
input [4:0] io_brupdate_b2_uop_rob_idx, // @[issue-unit.scala:112:14]
input [2:0] io_brupdate_b2_uop_ldq_idx, // @[issue-unit.scala:112:14]
input [2:0] io_brupdate_b2_uop_stq_idx, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-unit.scala:112:14]
input [5:0] io_brupdate_b2_uop_pdst, // @[issue-unit.scala:112:14]
input [5:0] io_brupdate_b2_uop_prs1, // @[issue-unit.scala:112:14]
input [5:0] io_brupdate_b2_uop_prs2, // @[issue-unit.scala:112:14]
input [5:0] io_brupdate_b2_uop_prs3, // @[issue-unit.scala:112:14]
input [3:0] io_brupdate_b2_uop_ppred, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-unit.scala:112:14]
input [5:0] io_brupdate_b2_uop_stale_pdst, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_exception, // @[issue-unit.scala:112:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_bypassable, // @[issue-unit.scala:112:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_fence, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_amo, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_is_unique, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-unit.scala:112:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-unit.scala:112:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-unit.scala:112:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-unit.scala:112:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_fp_val, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_fp_single, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-unit.scala:112:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-unit.scala:112:14]
input io_brupdate_b2_valid, // @[issue-unit.scala:112:14]
input io_brupdate_b2_mispredict, // @[issue-unit.scala:112:14]
input io_brupdate_b2_taken, // @[issue-unit.scala:112:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-unit.scala:112:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-unit.scala:112:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-unit.scala:112:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-unit.scala:112:14]
input io_flush_pipeline, // @[issue-unit.scala:112:14]
input io_ld_miss, // @[issue-unit.scala:112:14]
input [63:0] io_tsc_reg // @[issue-unit.scala:112:14]
);
wire _slots_7_io_valid; // @[issue-unit.scala:153:73]
wire _slots_6_io_valid; // @[issue-unit.scala:153:73]
wire _slots_5_io_valid; // @[issue-unit.scala:153:73]
wire _slots_4_io_valid; // @[issue-unit.scala:153:73]
wire _slots_3_io_valid; // @[issue-unit.scala:153:73]
wire _slots_2_io_valid; // @[issue-unit.scala:153:73]
wire _slots_1_io_valid; // @[issue-unit.scala:153:73]
wire _slots_0_io_valid; // @[issue-unit.scala:153:73]
wire io_dis_uops_0_valid_0 = io_dis_uops_0_valid; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_dis_uops_0_bits_uopc_0 = io_dis_uops_0_bits_uopc; // @[issue-unit-age-ordered.scala:29:7]
wire [31:0] io_dis_uops_0_bits_inst_0 = io_dis_uops_0_bits_inst; // @[issue-unit-age-ordered.scala:29:7]
wire [31:0] io_dis_uops_0_bits_debug_inst_0 = io_dis_uops_0_bits_debug_inst; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_rvc_0 = io_dis_uops_0_bits_is_rvc; // @[issue-unit-age-ordered.scala:29:7]
wire [39:0] io_dis_uops_0_bits_debug_pc_0 = io_dis_uops_0_bits_debug_pc; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_0_bits_iq_type_0 = io_dis_uops_0_bits_iq_type; // @[issue-unit-age-ordered.scala:29:7]
wire [9:0] io_dis_uops_0_bits_fu_code_0 = io_dis_uops_0_bits_fu_code; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_dis_uops_0_bits_ctrl_br_type_0 = io_dis_uops_0_bits_ctrl_br_type; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_ctrl_op1_sel_0 = io_dis_uops_0_bits_ctrl_op1_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_0_bits_ctrl_op2_sel_0 = io_dis_uops_0_bits_ctrl_op2_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_0_bits_ctrl_imm_sel_0 = io_dis_uops_0_bits_ctrl_imm_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_0_bits_ctrl_op_fcn_0 = io_dis_uops_0_bits_ctrl_op_fcn; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_ctrl_fcn_dw_0 = io_dis_uops_0_bits_ctrl_fcn_dw; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_0_bits_ctrl_csr_cmd_0 = io_dis_uops_0_bits_ctrl_csr_cmd; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_ctrl_is_load_0 = io_dis_uops_0_bits_ctrl_is_load; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_ctrl_is_sta_0 = io_dis_uops_0_bits_ctrl_is_sta; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_ctrl_is_std_0 = io_dis_uops_0_bits_ctrl_is_std; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_iw_state_0 = io_dis_uops_0_bits_iw_state; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_iw_p1_poisoned_0 = io_dis_uops_0_bits_iw_p1_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_iw_p2_poisoned_0 = io_dis_uops_0_bits_iw_p2_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_br_0 = io_dis_uops_0_bits_is_br; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_jalr_0 = io_dis_uops_0_bits_is_jalr; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_jal_0 = io_dis_uops_0_bits_is_jal; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_sfb_0 = io_dis_uops_0_bits_is_sfb; // @[issue-unit-age-ordered.scala:29:7]
wire [7:0] io_dis_uops_0_bits_br_mask_0 = io_dis_uops_0_bits_br_mask; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_0_bits_br_tag_0 = io_dis_uops_0_bits_br_tag; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_dis_uops_0_bits_ftq_idx_0 = io_dis_uops_0_bits_ftq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_edge_inst_0 = io_dis_uops_0_bits_edge_inst; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_0_bits_pc_lob_0 = io_dis_uops_0_bits_pc_lob; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_taken_0 = io_dis_uops_0_bits_taken; // @[issue-unit-age-ordered.scala:29:7]
wire [19:0] io_dis_uops_0_bits_imm_packed_0 = io_dis_uops_0_bits_imm_packed; // @[issue-unit-age-ordered.scala:29:7]
wire [11:0] io_dis_uops_0_bits_csr_addr_0 = io_dis_uops_0_bits_csr_addr; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_0_bits_rob_idx_0 = io_dis_uops_0_bits_rob_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_0_bits_ldq_idx_0 = io_dis_uops_0_bits_ldq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_dis_uops_0_bits_stq_idx_0 = io_dis_uops_0_bits_stq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_rxq_idx_0 = io_dis_uops_0_bits_rxq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_0_bits_pdst_0 = io_dis_uops_0_bits_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_0_bits_prs1_0 = io_dis_uops_0_bits_prs1; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_0_bits_prs2_0 = io_dis_uops_0_bits_prs2; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_0_bits_prs3_0 = io_dis_uops_0_bits_prs3; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_prs1_busy_0 = io_dis_uops_0_bits_prs1_busy; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_prs2_busy_0 = io_dis_uops_0_bits_prs2_busy; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_prs3_busy_0 = io_dis_uops_0_bits_prs3_busy; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_0_bits_stale_pdst_0 = io_dis_uops_0_bits_stale_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_exception_0 = io_dis_uops_0_bits_exception; // @[issue-unit-age-ordered.scala:29:7]
wire [63:0] io_dis_uops_0_bits_exc_cause_0 = io_dis_uops_0_bits_exc_cause; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_bypassable_0 = io_dis_uops_0_bits_bypassable; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_dis_uops_0_bits_mem_cmd_0 = io_dis_uops_0_bits_mem_cmd; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_mem_size_0 = io_dis_uops_0_bits_mem_size; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_mem_signed_0 = io_dis_uops_0_bits_mem_signed; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_fence_0 = io_dis_uops_0_bits_is_fence; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_fencei_0 = io_dis_uops_0_bits_is_fencei; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_amo_0 = io_dis_uops_0_bits_is_amo; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_uses_ldq_0 = io_dis_uops_0_bits_uses_ldq; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_uses_stq_0 = io_dis_uops_0_bits_uses_stq; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_sys_pc2epc_0 = io_dis_uops_0_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_is_unique_0 = io_dis_uops_0_bits_is_unique; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_flush_on_commit_0 = io_dis_uops_0_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_ldst_is_rs1_0 = io_dis_uops_0_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_0_bits_ldst_0 = io_dis_uops_0_bits_ldst; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_0_bits_lrs1_0 = io_dis_uops_0_bits_lrs1; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_0_bits_lrs2_0 = io_dis_uops_0_bits_lrs2; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_dis_uops_0_bits_lrs3_0 = io_dis_uops_0_bits_lrs3; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_ldst_val_0 = io_dis_uops_0_bits_ldst_val; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_dst_rtype_0 = io_dis_uops_0_bits_dst_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_lrs1_rtype_0 = io_dis_uops_0_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_lrs2_rtype_0 = io_dis_uops_0_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_frs3_en_0 = io_dis_uops_0_bits_frs3_en; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_fp_val_0 = io_dis_uops_0_bits_fp_val; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_fp_single_0 = io_dis_uops_0_bits_fp_single; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_xcpt_pf_if_0 = io_dis_uops_0_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_xcpt_ae_if_0 = io_dis_uops_0_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_xcpt_ma_if_0 = io_dis_uops_0_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_bp_debug_if_0 = io_dis_uops_0_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_bp_xcpt_if_0 = io_dis_uops_0_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_debug_fsrc_0 = io_dis_uops_0_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_dis_uops_0_bits_debug_tsrc_0 = io_dis_uops_0_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:29:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-unit-age-ordered.scala:29:7]
wire [9:0] io_fu_types_0_0 = io_fu_types_0; // @[issue-unit-age-ordered.scala:29:7]
wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-unit-age-ordered.scala:29:7]
wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-unit-age-ordered.scala:29:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-unit-age-ordered.scala:29:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-unit-age-ordered.scala:29:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-unit-age-ordered.scala:29:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-unit-age-ordered.scala:29:7]
wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-unit-age-ordered.scala:29:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-unit-age-ordered.scala:29:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-unit-age-ordered.scala:29:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-unit-age-ordered.scala:29:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-unit-age-ordered.scala:29:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-unit-age-ordered.scala:29:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-unit-age-ordered.scala:29:7]
wire io_flush_pipeline_0 = io_flush_pipeline; // @[issue-unit-age-ordered.scala:29:7]
wire io_ld_miss_0 = io_ld_miss; // @[issue-unit-age-ordered.scala:29:7]
wire [63:0] io_tsc_reg_0 = io_tsc_reg; // @[issue-unit-age-ordered.scala:29:7]
wire io_dis_uops_0_bits_ppred_busy = 1'h0; // @[issue-unit-age-ordered.scala:29:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:29:7]
wire issue_slots_0_clear = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_0_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_1_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_2_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_3_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_4_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_5_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_6_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_7_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_prs3_busy = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_ppred_busy = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_prs3_busy = 1'h0; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_ppred_busy = 1'h0; // @[issue-unit.scala:154:28]
wire _issue_slots_0_clear_T = 1'h0; // @[issue-unit-age-ordered.scala:76:49]
wire io_iss_uops_0_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_taken = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_exception = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire io_iss_uops_0_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire io_iss_uops_0_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire io_iss_uops_0_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire io_iss_uops_0_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire [3:0] io_dis_uops_0_bits_ppred = 4'h0; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_pred_wakeup_port_bits = 4'h0; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] issue_slots_0_pred_wakeup_port_bits = 4'h0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_pred_wakeup_port_bits = 4'h0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_pred_wakeup_port_bits = 4'h0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_pred_wakeup_port_bits = 4'h0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_pred_wakeup_port_bits = 4'h0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_pred_wakeup_port_bits = 4'h0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_pred_wakeup_port_bits = 4'h0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_in_uop_bits_ppred = 4'h0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_pred_wakeup_port_bits = 4'h0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_in_uop_bits_ppred = 4'h0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_out_uop_ppred = 4'h0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_uop_ppred = 4'h0; // @[issue-unit.scala:154:28]
wire [3:0] io_iss_uops_0_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] io_iss_uops_0_uop_ftq_idx = 4'h0; // @[consts.scala:269:19]
wire [3:0] io_iss_uops_0_uop_ppred = 4'h0; // @[consts.scala:269:19]
wire [3:0] io_iss_uops_0_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [2:0] io_iss_uops_0_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] io_iss_uops_0_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] io_iss_uops_0_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] io_iss_uops_0_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] io_iss_uops_0_uop_br_tag = 3'h0; // @[consts.scala:269:19]
wire [2:0] io_iss_uops_0_uop_ldq_idx = 3'h0; // @[consts.scala:269:19]
wire [2:0] io_iss_uops_0_uop_stq_idx = 3'h0; // @[consts.scala:269:19]
wire [2:0] io_iss_uops_0_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] io_iss_uops_0_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] io_iss_uops_0_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [4:0] io_iss_uops_0_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] io_iss_uops_0_uop_rob_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] io_iss_uops_0_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] io_iss_uops_0_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [1:0] _next_T = 2'h0; // @[issue-unit-age-ordered.scala:48:26]
wire [1:0] io_iss_uops_0_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] io_iss_uops_0_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] io_iss_uops_0_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] io_iss_uops_0_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] io_iss_uops_0_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] io_iss_uops_0_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] io_iss_uops_0_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] io_iss_uops_0_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] io_iss_uops_0_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] io_iss_uops_0_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] io_iss_uops_0_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] io_iss_uops_0_uop_pdst = 6'h0; // @[consts.scala:269:19]
wire [5:0] io_iss_uops_0_uop_prs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] io_iss_uops_0_uop_prs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] io_iss_uops_0_uop_prs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] io_iss_uops_0_uop_stale_pdst = 6'h0; // @[consts.scala:269:19]
wire [5:0] io_iss_uops_0_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] io_iss_uops_0_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] io_iss_uops_0_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] io_iss_uops_0_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] io_iss_uops_0_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [11:0] io_iss_uops_0_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] io_iss_uops_0_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [7:0] io_iss_uops_0_uop_br_mask = 8'h0; // @[consts.scala:269:19]
wire [9:0] io_iss_uops_0_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] io_iss_uops_0_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] io_iss_uops_0_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] io_iss_uops_0_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [6:0] io_iss_uops_0_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] issue_slots_7_in_uop_bits_uopc = io_dis_uops_0_bits_uopc_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_7_in_uop_bits_inst = io_dis_uops_0_bits_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_7_in_uop_bits_debug_inst = io_dis_uops_0_bits_debug_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_rvc = io_dis_uops_0_bits_is_rvc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_7_in_uop_bits_debug_pc = io_dis_uops_0_bits_debug_pc_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_in_uop_bits_iq_type = io_dis_uops_0_bits_iq_type_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_7_in_uop_bits_fu_code = io_dis_uops_0_bits_fu_code_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_in_uop_bits_ctrl_br_type = io_dis_uops_0_bits_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_in_uop_bits_ctrl_op1_sel = io_dis_uops_0_bits_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_in_uop_bits_ctrl_op2_sel = io_dis_uops_0_bits_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_in_uop_bits_ctrl_imm_sel = io_dis_uops_0_bits_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_in_uop_bits_ctrl_op_fcn = io_dis_uops_0_bits_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_ctrl_fcn_dw = io_dis_uops_0_bits_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_in_uop_bits_ctrl_csr_cmd = io_dis_uops_0_bits_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_ctrl_is_load = io_dis_uops_0_bits_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_ctrl_is_sta = io_dis_uops_0_bits_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_ctrl_is_std = io_dis_uops_0_bits_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_br = io_dis_uops_0_bits_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_jalr = io_dis_uops_0_bits_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_jal = io_dis_uops_0_bits_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_sfb = io_dis_uops_0_bits_is_sfb_0; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_7_in_uop_bits_br_mask = io_dis_uops_0_bits_br_mask_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_in_uop_bits_br_tag = io_dis_uops_0_bits_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_in_uop_bits_ftq_idx = io_dis_uops_0_bits_ftq_idx_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_edge_inst = io_dis_uops_0_bits_edge_inst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_in_uop_bits_pc_lob = io_dis_uops_0_bits_pc_lob_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_taken = io_dis_uops_0_bits_taken_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_7_in_uop_bits_imm_packed = io_dis_uops_0_bits_imm_packed_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_7_in_uop_bits_csr_addr = io_dis_uops_0_bits_csr_addr_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_in_uop_bits_rob_idx = io_dis_uops_0_bits_rob_idx_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_in_uop_bits_ldq_idx = io_dis_uops_0_bits_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_in_uop_bits_stq_idx = io_dis_uops_0_bits_stq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_in_uop_bits_rxq_idx = io_dis_uops_0_bits_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_in_uop_bits_pdst = io_dis_uops_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_in_uop_bits_prs1 = io_dis_uops_0_bits_prs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_in_uop_bits_prs2 = io_dis_uops_0_bits_prs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_in_uop_bits_prs3 = io_dis_uops_0_bits_prs3_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_prs1_busy = io_dis_uops_0_bits_prs1_busy_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_in_uop_bits_stale_pdst = io_dis_uops_0_bits_stale_pdst_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_exception = io_dis_uops_0_bits_exception_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_7_in_uop_bits_exc_cause = io_dis_uops_0_bits_exc_cause_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_bypassable = io_dis_uops_0_bits_bypassable_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_in_uop_bits_mem_cmd = io_dis_uops_0_bits_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_in_uop_bits_mem_size = io_dis_uops_0_bits_mem_size_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_mem_signed = io_dis_uops_0_bits_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_fence = io_dis_uops_0_bits_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_fencei = io_dis_uops_0_bits_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_amo = io_dis_uops_0_bits_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_uses_ldq = io_dis_uops_0_bits_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_uses_stq = io_dis_uops_0_bits_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_sys_pc2epc = io_dis_uops_0_bits_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_is_unique = io_dis_uops_0_bits_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_flush_on_commit = io_dis_uops_0_bits_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_ldst_is_rs1 = io_dis_uops_0_bits_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_in_uop_bits_ldst = io_dis_uops_0_bits_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_in_uop_bits_lrs1 = io_dis_uops_0_bits_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_in_uop_bits_lrs2 = io_dis_uops_0_bits_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_in_uop_bits_lrs3 = io_dis_uops_0_bits_lrs3_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_ldst_val = io_dis_uops_0_bits_ldst_val_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_in_uop_bits_dst_rtype = io_dis_uops_0_bits_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_in_uop_bits_lrs1_rtype = io_dis_uops_0_bits_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_frs3_en = io_dis_uops_0_bits_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_fp_val = io_dis_uops_0_bits_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_fp_single = io_dis_uops_0_bits_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_xcpt_pf_if = io_dis_uops_0_bits_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_xcpt_ae_if = io_dis_uops_0_bits_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_xcpt_ma_if = io_dis_uops_0_bits_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_bp_debug_if = io_dis_uops_0_bits_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_bits_bp_xcpt_if = io_dis_uops_0_bits_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_in_uop_bits_debug_fsrc = io_dis_uops_0_bits_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_in_uop_bits_debug_tsrc = io_dis_uops_0_bits_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_0_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_1_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_2_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_3_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_4_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_5_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_6_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_7_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_0_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_1_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_2_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_3_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_4_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_5_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_6_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_7_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_0_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_1_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_2_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_3_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_4_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_5_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_6_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_7_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_0_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_1_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_2_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_3_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_4_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_5_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_6_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_7_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_0_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_1_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_2_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_3_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_4_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_5_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_6_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_7_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_0_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_1_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_2_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_3_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_4_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_5_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_6_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_7_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_0_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_0_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_1_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_2_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_3_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_4_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_5_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_6_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_7_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_0_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_0_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_1_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_2_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_3_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_4_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_5_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_6_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_7_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_0_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_1_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_2_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_3_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_4_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_5_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_6_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_7_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_0_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_0_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_1_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_2_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_3_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_4_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_5_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_6_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_7_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_0_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_1_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_2_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_3_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_4_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_5_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_6_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_7_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_0_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_1_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_2_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_3_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_4_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_5_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_6_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire [20:0] issue_slots_7_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28]
wire issue_slots_0_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28]
wire issue_slots_1_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28]
wire issue_slots_2_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28]
wire issue_slots_3_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28]
wire issue_slots_4_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28]
wire issue_slots_5_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28]
wire issue_slots_6_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28]
wire issue_slots_7_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28]
wire _io_event_empty_T_7; // @[issue-unit.scala:165:21]
wire io_dis_uops_0_ready_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_valids_0_0; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_iss_uops_0_ctrl_br_type_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_ctrl_op1_sel_0; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_iss_uops_0_ctrl_op2_sel_0; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_iss_uops_0_ctrl_imm_sel_0; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_iss_uops_0_ctrl_op_fcn_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_ctrl_fcn_dw_0; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_iss_uops_0_ctrl_csr_cmd_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_ctrl_is_load_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_ctrl_is_sta_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_ctrl_is_std_0; // @[issue-unit-age-ordered.scala:29:7]
wire [6:0] io_iss_uops_0_uopc_0; // @[issue-unit-age-ordered.scala:29:7]
wire [31:0] io_iss_uops_0_inst_0; // @[issue-unit-age-ordered.scala:29:7]
wire [31:0] io_iss_uops_0_debug_inst_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_rvc_0; // @[issue-unit-age-ordered.scala:29:7]
wire [39:0] io_iss_uops_0_debug_pc_0; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_iss_uops_0_iq_type_0; // @[issue-unit-age-ordered.scala:29:7]
wire [9:0] io_iss_uops_0_fu_code_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_iw_state_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_iw_p1_poisoned_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_iw_p2_poisoned_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_br_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_jalr_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_jal_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_sfb_0; // @[issue-unit-age-ordered.scala:29:7]
wire [7:0] io_iss_uops_0_br_mask_0; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_iss_uops_0_br_tag_0; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_iss_uops_0_ftq_idx_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_edge_inst_0; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_iss_uops_0_pc_lob_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_taken_0; // @[issue-unit-age-ordered.scala:29:7]
wire [19:0] io_iss_uops_0_imm_packed_0; // @[issue-unit-age-ordered.scala:29:7]
wire [11:0] io_iss_uops_0_csr_addr_0; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_iss_uops_0_rob_idx_0; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_iss_uops_0_ldq_idx_0; // @[issue-unit-age-ordered.scala:29:7]
wire [2:0] io_iss_uops_0_stq_idx_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_rxq_idx_0; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_iss_uops_0_pdst_0; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_iss_uops_0_prs1_0; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_iss_uops_0_prs2_0; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_iss_uops_0_prs3_0; // @[issue-unit-age-ordered.scala:29:7]
wire [3:0] io_iss_uops_0_ppred_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_prs1_busy_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_prs2_busy_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_prs3_busy_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_ppred_busy_0; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_iss_uops_0_stale_pdst_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_exception_0; // @[issue-unit-age-ordered.scala:29:7]
wire [63:0] io_iss_uops_0_exc_cause_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_bypassable_0; // @[issue-unit-age-ordered.scala:29:7]
wire [4:0] io_iss_uops_0_mem_cmd_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_mem_size_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_mem_signed_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_fence_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_fencei_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_amo_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_uses_ldq_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_uses_stq_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_is_unique_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_flush_on_commit_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_iss_uops_0_ldst_0; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_iss_uops_0_lrs1_0; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_iss_uops_0_lrs2_0; // @[issue-unit-age-ordered.scala:29:7]
wire [5:0] io_iss_uops_0_lrs3_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_ldst_val_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_dst_rtype_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_frs3_en_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_fp_val_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_fp_single_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_bp_debug_if_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_iss_uops_0_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_debug_fsrc_0; // @[issue-unit-age-ordered.scala:29:7]
wire [1:0] io_iss_uops_0_debug_tsrc_0; // @[issue-unit-age-ordered.scala:29:7]
wire io_event_empty; // @[issue-unit-age-ordered.scala:29:7]
wire _T_5 = io_dis_uops_0_bits_uopc_0 == 7'h2; // @[issue-unit.scala:127:39]
wire _T_4 = _T_5 & io_dis_uops_0_bits_lrs2_rtype_0 == 2'h0 | io_dis_uops_0_bits_uopc_0 == 7'h43; // @[issue-unit.scala:127:{39,50,84,96}, :128:39]
wire [1:0] issue_slots_7_in_uop_bits_iw_state = _T_4 ? 2'h2 : 2'h1; // @[issue-unit.scala:123:26, :127:96, :128:54, :129:30, :154:28]
wire _GEN = _T_4 | ~(_T_5 & (|io_dis_uops_0_bits_lrs2_rtype_0)); // @[issue-unit.scala:120:17, :127:{39,96}, :128:54, :131:{56,90,102}]
wire [1:0] issue_slots_7_in_uop_bits_lrs2_rtype = _GEN ? io_dis_uops_0_bits_lrs2_rtype_0 : 2'h2; // @[issue-unit.scala:120:17, :128:54, :131:102, :154:28]
wire issue_slots_7_in_uop_bits_prs2_busy = _GEN & io_dis_uops_0_bits_prs2_busy_0; // @[issue-unit.scala:120:17, :128:54, :131:102, :154:28]
wire [6:0] issue_slots_1_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_1_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_1_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_1_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_1_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_1_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_1_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_1_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_1_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire _issue_slots_1_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire [6:0] issue_slots_2_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_2_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_2_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_2_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_2_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_2_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_2_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_2_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_2_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_in_uop_bits_uopc = issue_slots_1_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_0_in_uop_bits_inst = issue_slots_1_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_0_in_uop_bits_debug_inst = issue_slots_1_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_rvc = issue_slots_1_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_0_in_uop_bits_debug_pc = issue_slots_1_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_in_uop_bits_iq_type = issue_slots_1_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_0_in_uop_bits_fu_code = issue_slots_1_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_0_in_uop_bits_ctrl_br_type = issue_slots_1_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_ctrl_op1_sel = issue_slots_1_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_in_uop_bits_ctrl_op2_sel = issue_slots_1_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_in_uop_bits_ctrl_imm_sel = issue_slots_1_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_in_uop_bits_ctrl_op_fcn = issue_slots_1_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_ctrl_fcn_dw = issue_slots_1_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_in_uop_bits_ctrl_csr_cmd = issue_slots_1_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_ctrl_is_load = issue_slots_1_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_ctrl_is_sta = issue_slots_1_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_ctrl_is_std = issue_slots_1_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_iw_state = issue_slots_1_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_iw_p1_poisoned = issue_slots_1_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_iw_p2_poisoned = issue_slots_1_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_br = issue_slots_1_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_jalr = issue_slots_1_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_jal = issue_slots_1_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_sfb = issue_slots_1_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_0_in_uop_bits_br_mask = issue_slots_1_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_in_uop_bits_br_tag = issue_slots_1_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_0_in_uop_bits_ftq_idx = issue_slots_1_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_edge_inst = issue_slots_1_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_in_uop_bits_pc_lob = issue_slots_1_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_taken = issue_slots_1_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_0_in_uop_bits_imm_packed = issue_slots_1_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_0_in_uop_bits_csr_addr = issue_slots_1_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_in_uop_bits_rob_idx = issue_slots_1_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_in_uop_bits_ldq_idx = issue_slots_1_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_in_uop_bits_stq_idx = issue_slots_1_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_rxq_idx = issue_slots_1_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_in_uop_bits_pdst = issue_slots_1_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_in_uop_bits_prs1 = issue_slots_1_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_in_uop_bits_prs2 = issue_slots_1_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_in_uop_bits_prs3 = issue_slots_1_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_0_in_uop_bits_ppred = issue_slots_1_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_prs1_busy = issue_slots_1_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_prs2_busy = issue_slots_1_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_prs3_busy = issue_slots_1_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_ppred_busy = issue_slots_1_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_in_uop_bits_stale_pdst = issue_slots_1_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_exception = issue_slots_1_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_0_in_uop_bits_exc_cause = issue_slots_1_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_bypassable = issue_slots_1_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_in_uop_bits_mem_cmd = issue_slots_1_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_mem_size = issue_slots_1_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_mem_signed = issue_slots_1_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_fence = issue_slots_1_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_fencei = issue_slots_1_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_amo = issue_slots_1_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_uses_ldq = issue_slots_1_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_uses_stq = issue_slots_1_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_sys_pc2epc = issue_slots_1_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_is_unique = issue_slots_1_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_flush_on_commit = issue_slots_1_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_ldst_is_rs1 = issue_slots_1_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_in_uop_bits_ldst = issue_slots_1_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_in_uop_bits_lrs1 = issue_slots_1_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_in_uop_bits_lrs2 = issue_slots_1_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_in_uop_bits_lrs3 = issue_slots_1_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_ldst_val = issue_slots_1_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_dst_rtype = issue_slots_1_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_lrs1_rtype = issue_slots_1_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_lrs2_rtype = issue_slots_1_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_frs3_en = issue_slots_1_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_fp_val = issue_slots_1_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_fp_single = issue_slots_1_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_xcpt_pf_if = issue_slots_1_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_xcpt_ae_if = issue_slots_1_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_xcpt_ma_if = issue_slots_1_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_bp_debug_if = issue_slots_1_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_bits_bp_xcpt_if = issue_slots_1_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_debug_fsrc = issue_slots_1_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_in_uop_bits_debug_tsrc = issue_slots_1_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire _issue_slots_2_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire [6:0] issue_slots_3_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_3_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_3_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_3_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_3_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_3_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_3_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_3_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_3_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_in_uop_bits_uopc = issue_slots_2_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_1_in_uop_bits_inst = issue_slots_2_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_1_in_uop_bits_debug_inst = issue_slots_2_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_rvc = issue_slots_2_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_1_in_uop_bits_debug_pc = issue_slots_2_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_in_uop_bits_iq_type = issue_slots_2_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_1_in_uop_bits_fu_code = issue_slots_2_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_in_uop_bits_ctrl_br_type = issue_slots_2_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_ctrl_op1_sel = issue_slots_2_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_in_uop_bits_ctrl_op2_sel = issue_slots_2_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_in_uop_bits_ctrl_imm_sel = issue_slots_2_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_in_uop_bits_ctrl_op_fcn = issue_slots_2_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_ctrl_fcn_dw = issue_slots_2_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_in_uop_bits_ctrl_csr_cmd = issue_slots_2_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_ctrl_is_load = issue_slots_2_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_ctrl_is_sta = issue_slots_2_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_ctrl_is_std = issue_slots_2_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_iw_state = issue_slots_2_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_iw_p1_poisoned = issue_slots_2_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_iw_p2_poisoned = issue_slots_2_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_br = issue_slots_2_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_jalr = issue_slots_2_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_jal = issue_slots_2_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_sfb = issue_slots_2_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_1_in_uop_bits_br_mask = issue_slots_2_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_in_uop_bits_br_tag = issue_slots_2_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_in_uop_bits_ftq_idx = issue_slots_2_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_edge_inst = issue_slots_2_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_in_uop_bits_pc_lob = issue_slots_2_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_taken = issue_slots_2_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_1_in_uop_bits_imm_packed = issue_slots_2_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_1_in_uop_bits_csr_addr = issue_slots_2_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_in_uop_bits_rob_idx = issue_slots_2_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_in_uop_bits_ldq_idx = issue_slots_2_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_in_uop_bits_stq_idx = issue_slots_2_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_rxq_idx = issue_slots_2_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_in_uop_bits_pdst = issue_slots_2_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_in_uop_bits_prs1 = issue_slots_2_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_in_uop_bits_prs2 = issue_slots_2_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_in_uop_bits_prs3 = issue_slots_2_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_in_uop_bits_ppred = issue_slots_2_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_prs1_busy = issue_slots_2_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_prs2_busy = issue_slots_2_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_prs3_busy = issue_slots_2_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_ppred_busy = issue_slots_2_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_in_uop_bits_stale_pdst = issue_slots_2_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_exception = issue_slots_2_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_1_in_uop_bits_exc_cause = issue_slots_2_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_bypassable = issue_slots_2_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_in_uop_bits_mem_cmd = issue_slots_2_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_mem_size = issue_slots_2_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_mem_signed = issue_slots_2_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_fence = issue_slots_2_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_fencei = issue_slots_2_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_amo = issue_slots_2_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_uses_ldq = issue_slots_2_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_uses_stq = issue_slots_2_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_sys_pc2epc = issue_slots_2_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_is_unique = issue_slots_2_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_flush_on_commit = issue_slots_2_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_ldst_is_rs1 = issue_slots_2_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_in_uop_bits_ldst = issue_slots_2_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_in_uop_bits_lrs1 = issue_slots_2_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_in_uop_bits_lrs2 = issue_slots_2_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_in_uop_bits_lrs3 = issue_slots_2_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_ldst_val = issue_slots_2_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_dst_rtype = issue_slots_2_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_lrs1_rtype = issue_slots_2_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_lrs2_rtype = issue_slots_2_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_frs3_en = issue_slots_2_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_fp_val = issue_slots_2_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_fp_single = issue_slots_2_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_xcpt_pf_if = issue_slots_2_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_xcpt_ae_if = issue_slots_2_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_xcpt_ma_if = issue_slots_2_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_bp_debug_if = issue_slots_2_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_bits_bp_xcpt_if = issue_slots_2_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_debug_fsrc = issue_slots_2_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_in_uop_bits_debug_tsrc = issue_slots_2_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire _issue_slots_3_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire [6:0] issue_slots_4_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_4_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_4_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_4_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_4_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_4_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_4_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_4_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_4_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_in_uop_bits_uopc = issue_slots_3_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_2_in_uop_bits_inst = issue_slots_3_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_2_in_uop_bits_debug_inst = issue_slots_3_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_rvc = issue_slots_3_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_2_in_uop_bits_debug_pc = issue_slots_3_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_in_uop_bits_iq_type = issue_slots_3_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_2_in_uop_bits_fu_code = issue_slots_3_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_in_uop_bits_ctrl_br_type = issue_slots_3_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_ctrl_op1_sel = issue_slots_3_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_in_uop_bits_ctrl_op2_sel = issue_slots_3_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_in_uop_bits_ctrl_imm_sel = issue_slots_3_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_in_uop_bits_ctrl_op_fcn = issue_slots_3_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_ctrl_fcn_dw = issue_slots_3_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_in_uop_bits_ctrl_csr_cmd = issue_slots_3_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_ctrl_is_load = issue_slots_3_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_ctrl_is_sta = issue_slots_3_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_ctrl_is_std = issue_slots_3_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_iw_state = issue_slots_3_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_iw_p1_poisoned = issue_slots_3_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_iw_p2_poisoned = issue_slots_3_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_br = issue_slots_3_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_jalr = issue_slots_3_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_jal = issue_slots_3_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_sfb = issue_slots_3_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_2_in_uop_bits_br_mask = issue_slots_3_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_in_uop_bits_br_tag = issue_slots_3_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_in_uop_bits_ftq_idx = issue_slots_3_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_edge_inst = issue_slots_3_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_in_uop_bits_pc_lob = issue_slots_3_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_taken = issue_slots_3_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_2_in_uop_bits_imm_packed = issue_slots_3_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_2_in_uop_bits_csr_addr = issue_slots_3_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_in_uop_bits_rob_idx = issue_slots_3_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_in_uop_bits_ldq_idx = issue_slots_3_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_in_uop_bits_stq_idx = issue_slots_3_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_rxq_idx = issue_slots_3_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_in_uop_bits_pdst = issue_slots_3_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_in_uop_bits_prs1 = issue_slots_3_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_in_uop_bits_prs2 = issue_slots_3_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_in_uop_bits_prs3 = issue_slots_3_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_in_uop_bits_ppred = issue_slots_3_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_prs1_busy = issue_slots_3_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_prs2_busy = issue_slots_3_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_prs3_busy = issue_slots_3_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_ppred_busy = issue_slots_3_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_in_uop_bits_stale_pdst = issue_slots_3_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_exception = issue_slots_3_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_2_in_uop_bits_exc_cause = issue_slots_3_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_bypassable = issue_slots_3_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_in_uop_bits_mem_cmd = issue_slots_3_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_mem_size = issue_slots_3_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_mem_signed = issue_slots_3_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_fence = issue_slots_3_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_fencei = issue_slots_3_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_amo = issue_slots_3_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_uses_ldq = issue_slots_3_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_uses_stq = issue_slots_3_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_sys_pc2epc = issue_slots_3_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_is_unique = issue_slots_3_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_flush_on_commit = issue_slots_3_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_ldst_is_rs1 = issue_slots_3_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_in_uop_bits_ldst = issue_slots_3_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_in_uop_bits_lrs1 = issue_slots_3_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_in_uop_bits_lrs2 = issue_slots_3_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_in_uop_bits_lrs3 = issue_slots_3_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_ldst_val = issue_slots_3_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_dst_rtype = issue_slots_3_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_lrs1_rtype = issue_slots_3_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_lrs2_rtype = issue_slots_3_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_frs3_en = issue_slots_3_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_fp_val = issue_slots_3_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_fp_single = issue_slots_3_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_xcpt_pf_if = issue_slots_3_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_xcpt_ae_if = issue_slots_3_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_xcpt_ma_if = issue_slots_3_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_bp_debug_if = issue_slots_3_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_bits_bp_xcpt_if = issue_slots_3_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_debug_fsrc = issue_slots_3_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_in_uop_bits_debug_tsrc = issue_slots_3_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire _issue_slots_4_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire [6:0] issue_slots_5_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_5_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_5_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_5_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_5_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_5_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_5_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_5_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_5_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_in_uop_bits_uopc = issue_slots_4_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_3_in_uop_bits_inst = issue_slots_4_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_3_in_uop_bits_debug_inst = issue_slots_4_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_rvc = issue_slots_4_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_3_in_uop_bits_debug_pc = issue_slots_4_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_in_uop_bits_iq_type = issue_slots_4_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_3_in_uop_bits_fu_code = issue_slots_4_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_in_uop_bits_ctrl_br_type = issue_slots_4_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_ctrl_op1_sel = issue_slots_4_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_in_uop_bits_ctrl_op2_sel = issue_slots_4_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_in_uop_bits_ctrl_imm_sel = issue_slots_4_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_in_uop_bits_ctrl_op_fcn = issue_slots_4_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_ctrl_fcn_dw = issue_slots_4_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_in_uop_bits_ctrl_csr_cmd = issue_slots_4_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_ctrl_is_load = issue_slots_4_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_ctrl_is_sta = issue_slots_4_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_ctrl_is_std = issue_slots_4_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_iw_state = issue_slots_4_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_iw_p1_poisoned = issue_slots_4_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_iw_p2_poisoned = issue_slots_4_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_br = issue_slots_4_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_jalr = issue_slots_4_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_jal = issue_slots_4_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_sfb = issue_slots_4_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_3_in_uop_bits_br_mask = issue_slots_4_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_in_uop_bits_br_tag = issue_slots_4_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_in_uop_bits_ftq_idx = issue_slots_4_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_edge_inst = issue_slots_4_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_in_uop_bits_pc_lob = issue_slots_4_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_taken = issue_slots_4_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_3_in_uop_bits_imm_packed = issue_slots_4_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_3_in_uop_bits_csr_addr = issue_slots_4_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_in_uop_bits_rob_idx = issue_slots_4_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_in_uop_bits_ldq_idx = issue_slots_4_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_in_uop_bits_stq_idx = issue_slots_4_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_rxq_idx = issue_slots_4_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_in_uop_bits_pdst = issue_slots_4_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_in_uop_bits_prs1 = issue_slots_4_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_in_uop_bits_prs2 = issue_slots_4_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_in_uop_bits_prs3 = issue_slots_4_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_in_uop_bits_ppred = issue_slots_4_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_prs1_busy = issue_slots_4_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_prs2_busy = issue_slots_4_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_prs3_busy = issue_slots_4_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_ppred_busy = issue_slots_4_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_in_uop_bits_stale_pdst = issue_slots_4_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_exception = issue_slots_4_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_3_in_uop_bits_exc_cause = issue_slots_4_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_bypassable = issue_slots_4_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_in_uop_bits_mem_cmd = issue_slots_4_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_mem_size = issue_slots_4_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_mem_signed = issue_slots_4_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_fence = issue_slots_4_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_fencei = issue_slots_4_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_amo = issue_slots_4_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_uses_ldq = issue_slots_4_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_uses_stq = issue_slots_4_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_sys_pc2epc = issue_slots_4_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_is_unique = issue_slots_4_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_flush_on_commit = issue_slots_4_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_ldst_is_rs1 = issue_slots_4_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_in_uop_bits_ldst = issue_slots_4_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_in_uop_bits_lrs1 = issue_slots_4_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_in_uop_bits_lrs2 = issue_slots_4_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_in_uop_bits_lrs3 = issue_slots_4_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_ldst_val = issue_slots_4_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_dst_rtype = issue_slots_4_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_lrs1_rtype = issue_slots_4_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_lrs2_rtype = issue_slots_4_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_frs3_en = issue_slots_4_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_fp_val = issue_slots_4_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_fp_single = issue_slots_4_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_xcpt_pf_if = issue_slots_4_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_xcpt_ae_if = issue_slots_4_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_xcpt_ma_if = issue_slots_4_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_bp_debug_if = issue_slots_4_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_bits_bp_xcpt_if = issue_slots_4_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_debug_fsrc = issue_slots_4_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_in_uop_bits_debug_tsrc = issue_slots_4_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire _issue_slots_5_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire [6:0] issue_slots_6_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_6_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_6_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_6_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_6_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_6_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_6_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_6_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_6_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_in_uop_bits_uopc = issue_slots_5_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_4_in_uop_bits_inst = issue_slots_5_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_4_in_uop_bits_debug_inst = issue_slots_5_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_rvc = issue_slots_5_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_4_in_uop_bits_debug_pc = issue_slots_5_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_in_uop_bits_iq_type = issue_slots_5_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_4_in_uop_bits_fu_code = issue_slots_5_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_in_uop_bits_ctrl_br_type = issue_slots_5_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_ctrl_op1_sel = issue_slots_5_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_in_uop_bits_ctrl_op2_sel = issue_slots_5_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_in_uop_bits_ctrl_imm_sel = issue_slots_5_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_in_uop_bits_ctrl_op_fcn = issue_slots_5_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_ctrl_fcn_dw = issue_slots_5_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_in_uop_bits_ctrl_csr_cmd = issue_slots_5_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_ctrl_is_load = issue_slots_5_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_ctrl_is_sta = issue_slots_5_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_ctrl_is_std = issue_slots_5_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_iw_state = issue_slots_5_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_iw_p1_poisoned = issue_slots_5_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_iw_p2_poisoned = issue_slots_5_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_br = issue_slots_5_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_jalr = issue_slots_5_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_jal = issue_slots_5_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_sfb = issue_slots_5_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_4_in_uop_bits_br_mask = issue_slots_5_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_in_uop_bits_br_tag = issue_slots_5_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_in_uop_bits_ftq_idx = issue_slots_5_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_edge_inst = issue_slots_5_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_in_uop_bits_pc_lob = issue_slots_5_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_taken = issue_slots_5_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_4_in_uop_bits_imm_packed = issue_slots_5_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_4_in_uop_bits_csr_addr = issue_slots_5_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_in_uop_bits_rob_idx = issue_slots_5_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_in_uop_bits_ldq_idx = issue_slots_5_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_in_uop_bits_stq_idx = issue_slots_5_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_rxq_idx = issue_slots_5_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_in_uop_bits_pdst = issue_slots_5_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_in_uop_bits_prs1 = issue_slots_5_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_in_uop_bits_prs2 = issue_slots_5_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_in_uop_bits_prs3 = issue_slots_5_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_in_uop_bits_ppred = issue_slots_5_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_prs1_busy = issue_slots_5_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_prs2_busy = issue_slots_5_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_prs3_busy = issue_slots_5_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_ppred_busy = issue_slots_5_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_in_uop_bits_stale_pdst = issue_slots_5_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_exception = issue_slots_5_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_4_in_uop_bits_exc_cause = issue_slots_5_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_bypassable = issue_slots_5_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_in_uop_bits_mem_cmd = issue_slots_5_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_mem_size = issue_slots_5_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_mem_signed = issue_slots_5_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_fence = issue_slots_5_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_fencei = issue_slots_5_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_amo = issue_slots_5_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_uses_ldq = issue_slots_5_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_uses_stq = issue_slots_5_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_sys_pc2epc = issue_slots_5_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_is_unique = issue_slots_5_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_flush_on_commit = issue_slots_5_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_ldst_is_rs1 = issue_slots_5_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_in_uop_bits_ldst = issue_slots_5_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_in_uop_bits_lrs1 = issue_slots_5_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_in_uop_bits_lrs2 = issue_slots_5_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_in_uop_bits_lrs3 = issue_slots_5_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_ldst_val = issue_slots_5_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_dst_rtype = issue_slots_5_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_lrs1_rtype = issue_slots_5_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_lrs2_rtype = issue_slots_5_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_frs3_en = issue_slots_5_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_fp_val = issue_slots_5_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_fp_single = issue_slots_5_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_xcpt_pf_if = issue_slots_5_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_xcpt_ae_if = issue_slots_5_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_xcpt_ma_if = issue_slots_5_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_bp_debug_if = issue_slots_5_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_bits_bp_xcpt_if = issue_slots_5_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_debug_fsrc = issue_slots_5_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_in_uop_bits_debug_tsrc = issue_slots_5_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire _issue_slots_6_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire [6:0] issue_slots_7_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_7_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_7_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_7_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_7_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_7_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_7_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_7_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_out_uop_prs3; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_7_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_in_uop_bits_uopc = issue_slots_6_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_5_in_uop_bits_inst = issue_slots_6_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_5_in_uop_bits_debug_inst = issue_slots_6_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_rvc = issue_slots_6_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_5_in_uop_bits_debug_pc = issue_slots_6_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_in_uop_bits_iq_type = issue_slots_6_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_5_in_uop_bits_fu_code = issue_slots_6_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_in_uop_bits_ctrl_br_type = issue_slots_6_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_ctrl_op1_sel = issue_slots_6_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_in_uop_bits_ctrl_op2_sel = issue_slots_6_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_in_uop_bits_ctrl_imm_sel = issue_slots_6_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_in_uop_bits_ctrl_op_fcn = issue_slots_6_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_ctrl_fcn_dw = issue_slots_6_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_in_uop_bits_ctrl_csr_cmd = issue_slots_6_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_ctrl_is_load = issue_slots_6_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_ctrl_is_sta = issue_slots_6_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_ctrl_is_std = issue_slots_6_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_iw_state = issue_slots_6_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_iw_p1_poisoned = issue_slots_6_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_iw_p2_poisoned = issue_slots_6_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_br = issue_slots_6_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_jalr = issue_slots_6_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_jal = issue_slots_6_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_sfb = issue_slots_6_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_5_in_uop_bits_br_mask = issue_slots_6_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_in_uop_bits_br_tag = issue_slots_6_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_in_uop_bits_ftq_idx = issue_slots_6_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_edge_inst = issue_slots_6_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_in_uop_bits_pc_lob = issue_slots_6_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_taken = issue_slots_6_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_5_in_uop_bits_imm_packed = issue_slots_6_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_5_in_uop_bits_csr_addr = issue_slots_6_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_in_uop_bits_rob_idx = issue_slots_6_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_in_uop_bits_ldq_idx = issue_slots_6_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_in_uop_bits_stq_idx = issue_slots_6_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_rxq_idx = issue_slots_6_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_in_uop_bits_pdst = issue_slots_6_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_in_uop_bits_prs1 = issue_slots_6_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_in_uop_bits_prs2 = issue_slots_6_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_in_uop_bits_prs3 = issue_slots_6_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_in_uop_bits_ppred = issue_slots_6_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_prs1_busy = issue_slots_6_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_prs2_busy = issue_slots_6_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_prs3_busy = issue_slots_6_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_ppred_busy = issue_slots_6_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_in_uop_bits_stale_pdst = issue_slots_6_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_exception = issue_slots_6_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_5_in_uop_bits_exc_cause = issue_slots_6_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_bypassable = issue_slots_6_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_in_uop_bits_mem_cmd = issue_slots_6_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_mem_size = issue_slots_6_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_mem_signed = issue_slots_6_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_fence = issue_slots_6_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_fencei = issue_slots_6_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_amo = issue_slots_6_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_uses_ldq = issue_slots_6_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_uses_stq = issue_slots_6_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_sys_pc2epc = issue_slots_6_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_is_unique = issue_slots_6_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_flush_on_commit = issue_slots_6_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_ldst_is_rs1 = issue_slots_6_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_in_uop_bits_ldst = issue_slots_6_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_in_uop_bits_lrs1 = issue_slots_6_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_in_uop_bits_lrs2 = issue_slots_6_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_in_uop_bits_lrs3 = issue_slots_6_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_ldst_val = issue_slots_6_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_dst_rtype = issue_slots_6_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_lrs1_rtype = issue_slots_6_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_lrs2_rtype = issue_slots_6_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_frs3_en = issue_slots_6_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_fp_val = issue_slots_6_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_fp_single = issue_slots_6_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_xcpt_pf_if = issue_slots_6_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_xcpt_ae_if = issue_slots_6_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_xcpt_ma_if = issue_slots_6_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_bp_debug_if = issue_slots_6_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_bits_bp_xcpt_if = issue_slots_6_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_debug_fsrc = issue_slots_6_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_in_uop_bits_debug_tsrc = issue_slots_6_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire _issue_slots_7_clear_T; // @[issue-unit-age-ordered.scala:76:49]
wire [6:0] issue_slots_6_in_uop_bits_uopc = issue_slots_7_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_6_in_uop_bits_inst = issue_slots_7_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_6_in_uop_bits_debug_inst = issue_slots_7_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_rvc = issue_slots_7_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_6_in_uop_bits_debug_pc = issue_slots_7_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_in_uop_bits_iq_type = issue_slots_7_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_6_in_uop_bits_fu_code = issue_slots_7_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_in_uop_bits_ctrl_br_type = issue_slots_7_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_ctrl_op1_sel = issue_slots_7_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_in_uop_bits_ctrl_op2_sel = issue_slots_7_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_in_uop_bits_ctrl_imm_sel = issue_slots_7_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_in_uop_bits_ctrl_op_fcn = issue_slots_7_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_ctrl_fcn_dw = issue_slots_7_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_in_uop_bits_ctrl_csr_cmd = issue_slots_7_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_ctrl_is_load = issue_slots_7_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_ctrl_is_sta = issue_slots_7_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_ctrl_is_std = issue_slots_7_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_iw_state = issue_slots_7_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_iw_p1_poisoned = issue_slots_7_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_iw_p2_poisoned = issue_slots_7_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_br = issue_slots_7_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_jalr = issue_slots_7_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_jal = issue_slots_7_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_sfb = issue_slots_7_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_6_in_uop_bits_br_mask = issue_slots_7_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_in_uop_bits_br_tag = issue_slots_7_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_in_uop_bits_ftq_idx = issue_slots_7_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_edge_inst = issue_slots_7_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_in_uop_bits_pc_lob = issue_slots_7_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_taken = issue_slots_7_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_6_in_uop_bits_imm_packed = issue_slots_7_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_6_in_uop_bits_csr_addr = issue_slots_7_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_in_uop_bits_rob_idx = issue_slots_7_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_in_uop_bits_ldq_idx = issue_slots_7_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_in_uop_bits_stq_idx = issue_slots_7_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_rxq_idx = issue_slots_7_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_in_uop_bits_pdst = issue_slots_7_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_in_uop_bits_prs1 = issue_slots_7_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_in_uop_bits_prs2 = issue_slots_7_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_in_uop_bits_prs3 = issue_slots_7_out_uop_prs3; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_prs1_busy = issue_slots_7_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_prs2_busy = issue_slots_7_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_prs3_busy = issue_slots_7_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_ppred_busy = issue_slots_7_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_in_uop_bits_stale_pdst = issue_slots_7_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_exception = issue_slots_7_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_6_in_uop_bits_exc_cause = issue_slots_7_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_bypassable = issue_slots_7_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_in_uop_bits_mem_cmd = issue_slots_7_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_mem_size = issue_slots_7_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_mem_signed = issue_slots_7_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_fence = issue_slots_7_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_fencei = issue_slots_7_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_amo = issue_slots_7_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_uses_ldq = issue_slots_7_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_uses_stq = issue_slots_7_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_sys_pc2epc = issue_slots_7_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_is_unique = issue_slots_7_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_flush_on_commit = issue_slots_7_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_ldst_is_rs1 = issue_slots_7_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_in_uop_bits_ldst = issue_slots_7_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_in_uop_bits_lrs1 = issue_slots_7_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_in_uop_bits_lrs2 = issue_slots_7_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_in_uop_bits_lrs3 = issue_slots_7_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_ldst_val = issue_slots_7_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_dst_rtype = issue_slots_7_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_lrs1_rtype = issue_slots_7_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_lrs2_rtype = issue_slots_7_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_frs3_en = issue_slots_7_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_fp_val = issue_slots_7_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_fp_single = issue_slots_7_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_xcpt_pf_if = issue_slots_7_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_xcpt_ae_if = issue_slots_7_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_xcpt_ma_if = issue_slots_7_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_bp_debug_if = issue_slots_7_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_bits_bp_xcpt_if = issue_slots_7_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_debug_fsrc = issue_slots_7_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_in_uop_bits_debug_tsrc = issue_slots_7_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_0_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_0_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_out_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_0_out_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_0_out_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_0_out_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_out_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_0_out_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_0_out_uop_br_mask; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_out_uop_br_tag; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_0_out_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_out_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_0_out_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_0_out_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_out_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_out_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_out_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_out_uop_pdst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_out_uop_prs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_out_uop_prs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_out_uop_prs3; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_0_out_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_out_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_0_out_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_out_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_out_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_out_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_out_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_out_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_out_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_0_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_0_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_0_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_0_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_0_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_0_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_0_uop_br_mask; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_uop_br_tag; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_0_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_0_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_0_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_0_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_uop_pdst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_uop_prs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_uop_prs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_uop_prs3; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_0_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_0_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_0_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_0_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_0_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_0_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_0_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_0_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_0_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_0_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_0_valid; // @[issue-unit.scala:154:28]
wire issue_slots_0_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_0_request; // @[issue-unit.scala:154:28]
wire issue_slots_0_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_0_grant; // @[issue-unit.scala:154:28]
wire issue_slots_1_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_1_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_1_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_1_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_1_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_1_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_1_uop_br_mask; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_uop_br_tag; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_1_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_1_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_1_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_uop_pdst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_uop_prs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_uop_prs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_uop_prs3; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_1_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_1_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_1_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_1_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_1_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_1_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_1_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_1_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_1_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_1_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_1_valid; // @[issue-unit.scala:154:28]
wire issue_slots_1_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_1_request; // @[issue-unit.scala:154:28]
wire issue_slots_1_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_1_grant; // @[issue-unit.scala:154:28]
wire issue_slots_1_clear; // @[issue-unit.scala:154:28]
wire issue_slots_2_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_2_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_2_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_2_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_2_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_2_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_2_uop_br_mask; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_uop_br_tag; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_2_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_2_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_2_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_uop_pdst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_uop_prs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_uop_prs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_uop_prs3; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_2_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_2_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_2_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_2_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_2_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_2_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_2_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_2_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_2_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_2_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_2_valid; // @[issue-unit.scala:154:28]
wire issue_slots_2_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_2_request; // @[issue-unit.scala:154:28]
wire issue_slots_2_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_2_grant; // @[issue-unit.scala:154:28]
wire issue_slots_2_clear; // @[issue-unit.scala:154:28]
wire issue_slots_3_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_3_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_3_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_3_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_3_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_3_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_3_uop_br_mask; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_uop_br_tag; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_3_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_3_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_3_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_uop_pdst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_uop_prs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_uop_prs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_uop_prs3; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_3_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_3_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_3_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_3_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_3_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_3_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_3_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_3_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_3_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_3_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_3_valid; // @[issue-unit.scala:154:28]
wire issue_slots_3_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_3_request; // @[issue-unit.scala:154:28]
wire issue_slots_3_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_3_grant; // @[issue-unit.scala:154:28]
wire issue_slots_3_clear; // @[issue-unit.scala:154:28]
wire issue_slots_4_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_4_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_4_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_4_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_4_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_4_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_4_uop_br_mask; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_uop_br_tag; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_4_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_4_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_4_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_uop_pdst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_uop_prs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_uop_prs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_uop_prs3; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_4_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_4_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_4_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_4_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_4_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_4_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_4_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_4_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_4_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_4_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_4_valid; // @[issue-unit.scala:154:28]
wire issue_slots_4_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_4_request; // @[issue-unit.scala:154:28]
wire issue_slots_4_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_4_grant; // @[issue-unit.scala:154:28]
wire issue_slots_4_clear; // @[issue-unit.scala:154:28]
wire issue_slots_5_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_5_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_5_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_5_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_5_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_5_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_5_uop_br_mask; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_uop_br_tag; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_5_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_5_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_5_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_uop_pdst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_uop_prs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_uop_prs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_uop_prs3; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_5_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_5_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_5_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_5_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_5_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_5_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_5_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_5_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_5_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_5_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_5_valid; // @[issue-unit.scala:154:28]
wire issue_slots_5_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_5_request; // @[issue-unit.scala:154:28]
wire issue_slots_5_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_5_grant; // @[issue-unit.scala:154:28]
wire issue_slots_5_clear; // @[issue-unit.scala:154:28]
wire issue_slots_6_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_6_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_6_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_6_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_6_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_6_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_6_uop_br_mask; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_uop_br_tag; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_6_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_6_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_6_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_uop_pdst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_uop_prs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_uop_prs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_uop_prs3; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_6_uop_ppred; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_prs3_busy; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_ppred_busy; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_6_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_6_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_6_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_6_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_6_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_6_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_6_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_6_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_6_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_6_valid; // @[issue-unit.scala:154:28]
wire issue_slots_6_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_6_request; // @[issue-unit.scala:154:28]
wire issue_slots_6_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_6_grant; // @[issue-unit.scala:154:28]
wire issue_slots_6_clear; // @[issue-unit.scala:154:28]
wire issue_slots_7_in_uop_valid; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_uop_ctrl_br_type; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_ctrl_is_load; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_ctrl_is_sta; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_ctrl_is_std; // @[issue-unit.scala:154:28]
wire [6:0] issue_slots_7_uop_uopc; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_7_uop_inst; // @[issue-unit.scala:154:28]
wire [31:0] issue_slots_7_uop_debug_inst; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_rvc; // @[issue-unit.scala:154:28]
wire [39:0] issue_slots_7_uop_debug_pc; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_uop_iq_type; // @[issue-unit.scala:154:28]
wire [9:0] issue_slots_7_uop_fu_code; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_iw_state; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_br; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_jalr; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_jal; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_sfb; // @[issue-unit.scala:154:28]
wire [7:0] issue_slots_7_uop_br_mask; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_uop_br_tag; // @[issue-unit.scala:154:28]
wire [3:0] issue_slots_7_uop_ftq_idx; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_edge_inst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_uop_pc_lob; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_taken; // @[issue-unit.scala:154:28]
wire [19:0] issue_slots_7_uop_imm_packed; // @[issue-unit.scala:154:28]
wire [11:0] issue_slots_7_uop_csr_addr; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_uop_rob_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_uop_ldq_idx; // @[issue-unit.scala:154:28]
wire [2:0] issue_slots_7_uop_stq_idx; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_rxq_idx; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_uop_pdst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_uop_prs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_uop_prs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_uop_prs3; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_prs1_busy; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_prs2_busy; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_uop_stale_pdst; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_exception; // @[issue-unit.scala:154:28]
wire [63:0] issue_slots_7_uop_exc_cause; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_bypassable; // @[issue-unit.scala:154:28]
wire [4:0] issue_slots_7_uop_mem_cmd; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_mem_size; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_mem_signed; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_fence; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_fencei; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_amo; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_uses_ldq; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_uses_stq; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_is_unique; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_flush_on_commit; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_ldst_is_rs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_uop_ldst; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_uop_lrs1; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_uop_lrs2; // @[issue-unit.scala:154:28]
wire [5:0] issue_slots_7_uop_lrs3; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_ldst_val; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_dst_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_lrs1_rtype; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_lrs2_rtype; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_frs3_en; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_fp_val; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_fp_single; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_xcpt_pf_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_xcpt_ae_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_xcpt_ma_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_bp_debug_if; // @[issue-unit.scala:154:28]
wire issue_slots_7_uop_bp_xcpt_if; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_debug_fsrc; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_uop_debug_tsrc; // @[issue-unit.scala:154:28]
wire issue_slots_7_debug_p1; // @[issue-unit.scala:154:28]
wire issue_slots_7_debug_p2; // @[issue-unit.scala:154:28]
wire issue_slots_7_debug_p3; // @[issue-unit.scala:154:28]
wire issue_slots_7_debug_ppred; // @[issue-unit.scala:154:28]
wire [1:0] issue_slots_7_debug_state; // @[issue-unit.scala:154:28]
wire issue_slots_7_valid; // @[issue-unit.scala:154:28]
wire issue_slots_7_will_be_valid; // @[issue-unit.scala:154:28]
wire issue_slots_7_request; // @[issue-unit.scala:154:28]
wire issue_slots_7_request_hp; // @[issue-unit.scala:154:28]
wire issue_slots_7_grant; // @[issue-unit.scala:154:28]
wire issue_slots_7_clear; // @[issue-unit.scala:154:28]
wire _io_event_empty_T = issue_slots_0_valid | issue_slots_1_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_1 = _io_event_empty_T | issue_slots_2_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_2 = _io_event_empty_T_1 | issue_slots_3_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_3 = _io_event_empty_T_2 | issue_slots_4_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_4 = _io_event_empty_T_3 | issue_slots_5_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_5 = _io_event_empty_T_4 | issue_slots_6_valid; // @[issue-unit.scala:154:28, :165:61]
wire _io_event_empty_T_6 = _io_event_empty_T_5 | issue_slots_7_valid; // @[issue-unit.scala:154:28, :165:61]
assign _io_event_empty_T_7 = ~_io_event_empty_T_6; // @[issue-unit.scala:165:{21,61}]
assign io_event_empty = _io_event_empty_T_7; // @[issue-unit.scala:165:21]
wire [1:0] _count_T = {1'h0, _slots_0_io_valid} + {1'h0, _slots_1_io_valid}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_1 = _count_T; // @[issue-unit.scala:167:23]
wire [1:0] _count_T_2 = {1'h0, _slots_2_io_valid} + {1'h0, _slots_3_io_valid}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_3 = _count_T_2; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_4 = {1'h0, _count_T_1} + {1'h0, _count_T_3}; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_5 = _count_T_4; // @[issue-unit.scala:167:23]
wire [1:0] _count_T_6 = {1'h0, _slots_4_io_valid} + {1'h0, _slots_5_io_valid}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_7 = _count_T_6; // @[issue-unit.scala:167:23]
wire [1:0] _count_T_8 = {1'h0, _slots_6_io_valid} + {1'h0, _slots_7_io_valid}; // @[issue-unit.scala:153:73, :167:23]
wire [1:0] _count_T_9 = _count_T_8; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_10 = {1'h0, _count_T_7} + {1'h0, _count_T_9}; // @[issue-unit.scala:167:23]
wire [2:0] _count_T_11 = _count_T_10; // @[issue-unit.scala:167:23]
wire [3:0] _count_T_12 = {1'h0, _count_T_5} + {1'h0, _count_T_11}; // @[issue-unit.scala:167:23]
wire [3:0] count = _count_T_12; // @[issue-unit.scala:167:23] |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_43 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_43( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24 :
output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}}
node rawA_exp = bits(io.a, 31, 23)
node _rawA_isZero_T = bits(rawA_exp, 8, 6)
node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0))
node _rawA_isSpecial_T = bits(rawA_exp, 8, 7)
node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3))
wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6)
node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T)
connect rawA.isNaN, _rawA_out_isNaN_T_1
node _rawA_out_isInf_T = bits(rawA_exp, 6, 6)
node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0))
node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1)
connect rawA.isInf, _rawA_out_isInf_T_2
connect rawA.isZero, rawA_isZero
node _rawA_out_sign_T = bits(io.a, 32, 32)
connect rawA.sign, _rawA_out_sign_T
node _rawA_out_sExp_T = cvt(rawA_exp)
connect rawA.sExp, _rawA_out_sExp_T
node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0))
node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T)
node _rawA_out_sig_T_2 = bits(io.a, 22, 0)
node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2)
connect rawA.sig, _rawA_out_sig_T_3
node rawB_exp = bits(io.b, 31, 23)
node _rawB_isZero_T = bits(rawB_exp, 8, 6)
node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0))
node _rawB_isSpecial_T = bits(rawB_exp, 8, 7)
node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3))
wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6)
node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T)
connect rawB.isNaN, _rawB_out_isNaN_T_1
node _rawB_out_isInf_T = bits(rawB_exp, 6, 6)
node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0))
node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1)
connect rawB.isInf, _rawB_out_isInf_T_2
connect rawB.isZero, rawB_isZero
node _rawB_out_sign_T = bits(io.b, 32, 32)
connect rawB.sign, _rawB_out_sign_T
node _rawB_out_sExp_T = cvt(rawB_exp)
connect rawB.sExp, _rawB_out_sExp_T
node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0))
node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T)
node _rawB_out_sig_T_2 = bits(io.b, 22, 0)
node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2)
connect rawB.sig, _rawB_out_sig_T_3
node rawC_exp = bits(io.c, 31, 23)
node _rawC_isZero_T = bits(rawC_exp, 8, 6)
node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0))
node _rawC_isSpecial_T = bits(rawC_exp, 8, 7)
node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3))
wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6)
node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T)
connect rawC.isNaN, _rawC_out_isNaN_T_1
node _rawC_out_isInf_T = bits(rawC_exp, 6, 6)
node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0))
node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1)
connect rawC.isInf, _rawC_out_isInf_T_2
connect rawC.isZero, rawC_isZero
node _rawC_out_sign_T = bits(io.c, 32, 32)
connect rawC.sign, _rawC_out_sign_T
node _rawC_out_sExp_T = cvt(rawC_exp)
connect rawC.sExp, _rawC_out_sExp_T
node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0))
node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T)
node _rawC_out_sig_T_2 = bits(io.c, 22, 0)
node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2)
connect rawC.sig, _rawC_out_sig_T_3
node _signProd_T = xor(rawA.sign, rawB.sign)
node _signProd_T_1 = bits(io.op, 1, 1)
node signProd = xor(_signProd_T, _signProd_T_1)
node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp)
node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b)))
node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1)
node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2)
node _doSubMags_T = xor(signProd, rawC.sign)
node _doSubMags_T_1 = bits(io.op, 0, 0)
node doSubMags = xor(_doSubMags_T, _doSubMags_T_1)
node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp)
node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1)
node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1)
node posNatCAlignDist = bits(sNatCAlignDist, 9, 0)
node _isMinCAlign_T = or(rawA.isZero, rawB.isZero)
node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0)))
node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1)
node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0))
node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18))
node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1)
node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2)
node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a))
node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0)
node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a))
node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2)
node _mainAlignedSigC_T = not(rawC.sig)
node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig)
node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0))
node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2)
node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3)
node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist)
node _reduced4CExtra_T = shl(rawC.sig, 2)
wire reduced4CExtra_reducedVec : UInt<1>[7]
node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0)
node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T)
connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1
node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4)
node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T)
connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1
node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8)
node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T)
connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1
node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12)
node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T)
connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1
node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16)
node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T)
connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1
node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20)
node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T)
connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1
node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24)
node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T)
connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1
node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1])
node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0])
node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3])
node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5])
node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo)
node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo)
node _reduced4CExtra_T_2 = shr(CAlignDist, 2)
node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2)
node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14)
node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0)
node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0)
node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0)
node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1)
node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7)
node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2)
node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0)
node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1)
node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11)
node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12)
node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4)
node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0)
node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1)
node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16)
node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17)
node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18)
node reduced4CExtra = orr(_reduced4CExtra_T_19)
node _alignedSigC_T = shr(mainAlignedSigC, 3)
node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_2 = andr(_alignedSigC_T_1)
node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0))
node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3)
node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_6 = orr(_alignedSigC_T_5)
node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra)
node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7)
node alignedSigC_hi = asUInt(_alignedSigC_T)
node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8)
connect io.mulAddA, rawA.sig
connect io.mulAddB, rawB.sig
node _io_mulAddC_T = bits(alignedSigC, 48, 1)
connect io.mulAddC, _io_mulAddC_T
node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1)
node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4)
node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5)
node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8)
node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9)
connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10
node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN)
connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T
connect io.toPostMul.isInfA, rawA.isInf
connect io.toPostMul.isZeroA, rawA.isZero
connect io.toPostMul.isInfB, rawB.isInf
connect io.toPostMul.isZeroB, rawB.isZero
connect io.toPostMul.signProd, signProd
connect io.toPostMul.isNaNC, rawC.isNaN
connect io.toPostMul.isInfC, rawC.isInf
connect io.toPostMul.isZeroC, rawC.isZero
node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18)))
node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1)
node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1)
node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2)
connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3
connect io.toPostMul.doSubMags, doSubMags
connect io.toPostMul.CIsDominant, CIsDominant
node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0)
connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T
node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49)
connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T
node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0)
connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T | module MulAddRecFNToRaw_preMul_e8_s24( // @[MulAddRecFN.scala:71:7]
input [1:0] io_op, // @[MulAddRecFN.scala:74:16]
input [32:0] io_a, // @[MulAddRecFN.scala:74:16]
input [32:0] io_b, // @[MulAddRecFN.scala:74:16]
input [32:0] io_c, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16]
output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16]
output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16]
output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16]
output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire [1:0] io_op_0 = io_op; // @[MulAddRecFN.scala:71:7]
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7]
wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7]
wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7]
wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30]
wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58]
wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42]
wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire signProd; // @[MulAddRecFN.scala:97:42]
wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire doSubMags; // @[MulAddRecFN.scala:102:42]
wire CIsDominant; // @[MulAddRecFN.scala:110:23]
wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47]
wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20]
wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48]
wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _signProd_T_1 = io_op_0[1]; // @[MulAddRecFN.scala:71:7, :97:49]
assign signProd = _signProd_T ^ _signProd_T_1; // @[MulAddRecFN.scala:97:{30,42,49}]
assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42]
wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}]
wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32]
wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32]
wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _doSubMags_T_1 = io_op_0[0]; // @[MulAddRecFN.scala:71:7, :102:49]
assign doSubMags = _doSubMags_T ^ _doSubMags_T_1; // @[MulAddRecFN.scala:102:{30,42,49}]
assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42]
wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42]
wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42]
wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42]
wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42]
wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69]
wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}]
wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60]
wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}]
assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}]
assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23]
wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34]
wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33]
wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33]
wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16]
wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53]
wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}]
wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}]
wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}]
wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23]
wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15]
assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20]
wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28]
wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56]
wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20]
wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22]
wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20]
wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20]
wire reduced4CExtra = |_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11]
wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28]
wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}]
wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32]
wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32]
wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}]
wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47]
wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}]
wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}]
wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}]
wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44]
wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16]
assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23]
assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23]
assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30]
assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30]
wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46]
wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23]
assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46]
assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58]
assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42]
wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53]
wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12]
assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47]
assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47]
assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20]
assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20]
assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48]
assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48]
assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ProbePicker :
input clock : Clock
input reset : Reset
output auto : { flip in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
wire nodeIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn_1.d.bits.corrupt
invalidate nodeIn_1.d.bits.data
invalidate nodeIn_1.d.bits.denied
invalidate nodeIn_1.d.bits.sink
invalidate nodeIn_1.d.bits.source
invalidate nodeIn_1.d.bits.size
invalidate nodeIn_1.d.bits.param
invalidate nodeIn_1.d.bits.opcode
invalidate nodeIn_1.d.valid
invalidate nodeIn_1.d.ready
invalidate nodeIn_1.a.bits.corrupt
invalidate nodeIn_1.a.bits.data
invalidate nodeIn_1.a.bits.mask
invalidate nodeIn_1.a.bits.address
invalidate nodeIn_1.a.bits.source
invalidate nodeIn_1.a.bits.size
invalidate nodeIn_1.a.bits.param
invalidate nodeIn_1.a.bits.opcode
invalidate nodeIn_1.a.valid
invalidate nodeIn_1.a.ready
inst monitor of TLMonitor_32
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
inst monitor_1 of TLMonitor_33
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.d.bits.corrupt, nodeIn_1.d.bits.corrupt
connect monitor_1.io.in.d.bits.data, nodeIn_1.d.bits.data
connect monitor_1.io.in.d.bits.denied, nodeIn_1.d.bits.denied
connect monitor_1.io.in.d.bits.sink, nodeIn_1.d.bits.sink
connect monitor_1.io.in.d.bits.source, nodeIn_1.d.bits.source
connect monitor_1.io.in.d.bits.size, nodeIn_1.d.bits.size
connect monitor_1.io.in.d.bits.param, nodeIn_1.d.bits.param
connect monitor_1.io.in.d.bits.opcode, nodeIn_1.d.bits.opcode
connect monitor_1.io.in.d.valid, nodeIn_1.d.valid
connect monitor_1.io.in.d.ready, nodeIn_1.d.ready
connect monitor_1.io.in.a.bits.corrupt, nodeIn_1.a.bits.corrupt
connect monitor_1.io.in.a.bits.data, nodeIn_1.a.bits.data
connect monitor_1.io.in.a.bits.mask, nodeIn_1.a.bits.mask
connect monitor_1.io.in.a.bits.address, nodeIn_1.a.bits.address
connect monitor_1.io.in.a.bits.source, nodeIn_1.a.bits.source
connect monitor_1.io.in.a.bits.size, nodeIn_1.a.bits.size
connect monitor_1.io.in.a.bits.param, nodeIn_1.a.bits.param
connect monitor_1.io.in.a.bits.opcode, nodeIn_1.a.bits.opcode
connect monitor_1.io.in.a.valid, nodeIn_1.a.valid
connect monitor_1.io.in.a.ready, nodeIn_1.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_nodeOut.d.bits.corrupt
invalidate x1_nodeOut.d.bits.data
invalidate x1_nodeOut.d.bits.denied
invalidate x1_nodeOut.d.bits.sink
invalidate x1_nodeOut.d.bits.source
invalidate x1_nodeOut.d.bits.size
invalidate x1_nodeOut.d.bits.param
invalidate x1_nodeOut.d.bits.opcode
invalidate x1_nodeOut.d.valid
invalidate x1_nodeOut.d.ready
invalidate x1_nodeOut.a.bits.corrupt
invalidate x1_nodeOut.a.bits.data
invalidate x1_nodeOut.a.bits.mask
invalidate x1_nodeOut.a.bits.address
invalidate x1_nodeOut.a.bits.source
invalidate x1_nodeOut.a.bits.size
invalidate x1_nodeOut.a.bits.param
invalidate x1_nodeOut.a.bits.opcode
invalidate x1_nodeOut.a.valid
invalidate x1_nodeOut.a.ready
connect auto.out_0, nodeOut
connect auto.out_1, x1_nodeOut
connect nodeIn, auto.in_0
connect nodeIn_1, auto.in_1
connect nodeOut, nodeIn
connect x1_nodeOut, nodeIn_1 | module ProbePicker( // @[ProbePicker.scala:42:9]
input clock, // @[ProbePicker.scala:42:9]
input reset, // @[ProbePicker.scala:42:9]
output auto_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [27:0] auto_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [27:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_1_a_valid_0 = auto_in_1_a_valid; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_1_a_bits_opcode_0 = auto_in_1_a_bits_opcode; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_1_a_bits_param_0 = auto_in_1_a_bits_param; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_1_a_bits_size_0 = auto_in_1_a_bits_size; // @[ProbePicker.scala:42:9]
wire [4:0] auto_in_1_a_bits_source_0 = auto_in_1_a_bits_source; // @[ProbePicker.scala:42:9]
wire [27:0] auto_in_1_a_bits_address_0 = auto_in_1_a_bits_address; // @[ProbePicker.scala:42:9]
wire [7:0] auto_in_1_a_bits_mask_0 = auto_in_1_a_bits_mask; // @[ProbePicker.scala:42:9]
wire [63:0] auto_in_1_a_bits_data_0 = auto_in_1_a_bits_data; // @[ProbePicker.scala:42:9]
wire auto_in_1_a_bits_corrupt_0 = auto_in_1_a_bits_corrupt; // @[ProbePicker.scala:42:9]
wire auto_in_1_d_ready_0 = auto_in_1_d_ready; // @[ProbePicker.scala:42:9]
wire auto_in_0_a_valid_0 = auto_in_0_a_valid; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_0_a_bits_opcode_0 = auto_in_0_a_bits_opcode; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_0_a_bits_param_0 = auto_in_0_a_bits_param; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_0_a_bits_size_0 = auto_in_0_a_bits_size; // @[ProbePicker.scala:42:9]
wire [4:0] auto_in_0_a_bits_source_0 = auto_in_0_a_bits_source; // @[ProbePicker.scala:42:9]
wire [31:0] auto_in_0_a_bits_address_0 = auto_in_0_a_bits_address; // @[ProbePicker.scala:42:9]
wire [7:0] auto_in_0_a_bits_mask_0 = auto_in_0_a_bits_mask; // @[ProbePicker.scala:42:9]
wire [63:0] auto_in_0_a_bits_data_0 = auto_in_0_a_bits_data; // @[ProbePicker.scala:42:9]
wire auto_in_0_a_bits_corrupt_0 = auto_in_0_a_bits_corrupt; // @[ProbePicker.scala:42:9]
wire auto_in_0_d_ready_0 = auto_in_0_d_ready; // @[ProbePicker.scala:42:9]
wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[ProbePicker.scala:42:9]
wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[ProbePicker.scala:42:9]
wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[ProbePicker.scala:42:9]
wire [4:0] auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[ProbePicker.scala:42:9]
wire auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink; // @[ProbePicker.scala:42:9]
wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[ProbePicker.scala:42:9]
wire [63:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[ProbePicker.scala:42:9]
wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[ProbePicker.scala:42:9]
wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[ProbePicker.scala:42:9]
wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[ProbePicker.scala:42:9]
wire [4:0] auto_out_0_d_bits_source_0 = auto_out_0_d_bits_source; // @[ProbePicker.scala:42:9]
wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[ProbePicker.scala:42:9]
wire [63:0] auto_out_0_d_bits_data_0 = auto_out_0_d_bits_data; // @[ProbePicker.scala:42:9]
wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[ProbePicker.scala:42:9]
wire auto_in_0_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire auto_out_0_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire nodeIn_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire nodeOut_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire [1:0] auto_in_0_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire [1:0] auto_out_0_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire [1:0] nodeIn_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire nodeIn_1_a_ready; // @[MixedNode.scala:551:17]
wire [1:0] nodeOut_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire nodeIn_1_a_valid = auto_in_1_a_valid_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_1_a_bits_opcode = auto_in_1_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_1_a_bits_param = auto_in_1_a_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_1_a_bits_size = auto_in_1_a_bits_size_0; // @[ProbePicker.scala:42:9]
wire [4:0] nodeIn_1_a_bits_source = auto_in_1_a_bits_source_0; // @[ProbePicker.scala:42:9]
wire [27:0] nodeIn_1_a_bits_address = auto_in_1_a_bits_address_0; // @[ProbePicker.scala:42:9]
wire [7:0] nodeIn_1_a_bits_mask = auto_in_1_a_bits_mask_0; // @[ProbePicker.scala:42:9]
wire [63:0] nodeIn_1_a_bits_data = auto_in_1_a_bits_data_0; // @[ProbePicker.scala:42:9]
wire nodeIn_1_a_bits_corrupt = auto_in_1_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire nodeIn_1_d_ready = auto_in_1_d_ready_0; // @[ProbePicker.scala:42:9]
wire nodeIn_1_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_1_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_1_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_1_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] nodeIn_1_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_1_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_1_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_1_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_0_a_valid_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_0_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_a_bits_param = auto_in_0_a_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_a_bits_size = auto_in_0_a_bits_size_0; // @[ProbePicker.scala:42:9]
wire [4:0] nodeIn_a_bits_source = auto_in_0_a_bits_source_0; // @[ProbePicker.scala:42:9]
wire [31:0] nodeIn_a_bits_address = auto_in_0_a_bits_address_0; // @[ProbePicker.scala:42:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_0_a_bits_mask_0; // @[ProbePicker.scala:42:9]
wire [63:0] nodeIn_a_bits_data = auto_in_0_a_bits_data_0; // @[ProbePicker.scala:42:9]
wire nodeIn_a_bits_corrupt = auto_in_0_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire nodeIn_d_ready = auto_in_0_d_ready_0; // @[ProbePicker.scala:42:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [27:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[ProbePicker.scala:42:9]
wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[ProbePicker.scala:42:9]
wire [4:0] x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[ProbePicker.scala:42:9]
wire [63:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[ProbePicker.scala:42:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[ProbePicker.scala:42:9]
wire [4:0] nodeOut_d_bits_source = auto_out_0_d_bits_source_0; // @[ProbePicker.scala:42:9]
wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[ProbePicker.scala:42:9]
wire [63:0] nodeOut_d_bits_data = auto_out_0_d_bits_data_0; // @[ProbePicker.scala:42:9]
wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire auto_in_1_a_ready_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_1_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [1:0] auto_in_1_d_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_1_d_bits_size_0; // @[ProbePicker.scala:42:9]
wire [4:0] auto_in_1_d_bits_source_0; // @[ProbePicker.scala:42:9]
wire auto_in_1_d_bits_sink_0; // @[ProbePicker.scala:42:9]
wire auto_in_1_d_bits_denied_0; // @[ProbePicker.scala:42:9]
wire [63:0] auto_in_1_d_bits_data_0; // @[ProbePicker.scala:42:9]
wire auto_in_1_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire auto_in_1_d_valid_0; // @[ProbePicker.scala:42:9]
wire auto_in_0_a_ready_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_0_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_0_d_bits_size_0; // @[ProbePicker.scala:42:9]
wire [4:0] auto_in_0_d_bits_source_0; // @[ProbePicker.scala:42:9]
wire auto_in_0_d_bits_denied_0; // @[ProbePicker.scala:42:9]
wire [63:0] auto_in_0_d_bits_data_0; // @[ProbePicker.scala:42:9]
wire auto_in_0_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire auto_in_0_d_valid_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_1_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_1_a_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_1_a_bits_size_0; // @[ProbePicker.scala:42:9]
wire [4:0] auto_out_1_a_bits_source_0; // @[ProbePicker.scala:42:9]
wire [27:0] auto_out_1_a_bits_address_0; // @[ProbePicker.scala:42:9]
wire [7:0] auto_out_1_a_bits_mask_0; // @[ProbePicker.scala:42:9]
wire [63:0] auto_out_1_a_bits_data_0; // @[ProbePicker.scala:42:9]
wire auto_out_1_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire auto_out_1_a_valid_0; // @[ProbePicker.scala:42:9]
wire auto_out_1_d_ready_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_0_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_0_a_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_0_a_bits_size_0; // @[ProbePicker.scala:42:9]
wire [4:0] auto_out_0_a_bits_source_0; // @[ProbePicker.scala:42:9]
wire [31:0] auto_out_0_a_bits_address_0; // @[ProbePicker.scala:42:9]
wire [7:0] auto_out_0_a_bits_mask_0; // @[ProbePicker.scala:42:9]
wire [63:0] auto_out_0_a_bits_data_0; // @[ProbePicker.scala:42:9]
wire auto_out_0_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire auto_out_0_a_valid_0; // @[ProbePicker.scala:42:9]
wire auto_out_0_d_ready_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_a_ready_0 = nodeIn_a_ready; // @[ProbePicker.scala:42:9]
assign nodeOut_a_valid = nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_param = nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_size = nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_source = nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_mask = nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_corrupt = nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_d_ready = nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_in_0_d_valid_0 = nodeIn_d_valid; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_size_0 = nodeIn_d_bits_size; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_source_0 = nodeIn_d_bits_source; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_denied_0 = nodeIn_d_bits_denied; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_data_0 = nodeIn_d_bits_data; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[ProbePicker.scala:42:9]
assign auto_in_1_a_ready_0 = nodeIn_1_a_ready; // @[ProbePicker.scala:42:9]
assign x1_nodeOut_a_valid = nodeIn_1_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_opcode = nodeIn_1_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_param = nodeIn_1_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_size = nodeIn_1_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_source = nodeIn_1_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_address = nodeIn_1_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_mask = nodeIn_1_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_data = nodeIn_1_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_corrupt = nodeIn_1_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_d_ready = nodeIn_1_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_in_1_d_valid_0 = nodeIn_1_d_valid; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_opcode_0 = nodeIn_1_d_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_param_0 = nodeIn_1_d_bits_param; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_size_0 = nodeIn_1_d_bits_size; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_source_0 = nodeIn_1_d_bits_source; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_sink_0 = nodeIn_1_d_bits_sink; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_denied_0 = nodeIn_1_d_bits_denied; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_data_0 = nodeIn_1_d_bits_data; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_corrupt_0 = nodeIn_1_d_bits_corrupt; // @[ProbePicker.scala:42:9]
assign nodeIn_a_ready = nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_param_0 = nodeOut_a_bits_param; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_size_0 = nodeOut_a_bits_size; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_source_0 = nodeOut_a_bits_source; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_mask_0 = nodeOut_a_bits_mask; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[ProbePicker.scala:42:9]
assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[ProbePicker.scala:42:9]
assign nodeIn_d_valid = nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_opcode = nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_denied = nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_data = nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_corrupt = nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_a_ready = x1_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_param_0 = x1_nodeOut_a_bits_param; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_size_0 = x1_nodeOut_a_bits_size; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_source_0 = x1_nodeOut_a_bits_source; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_mask_0 = x1_nodeOut_a_bits_mask; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_corrupt_0 = x1_nodeOut_a_bits_corrupt; // @[ProbePicker.scala:42:9]
assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[ProbePicker.scala:42:9]
assign nodeIn_1_d_valid = x1_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_opcode = x1_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_param = x1_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_size = x1_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_source = x1_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_sink = x1_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_denied = x1_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_data = x1_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_corrupt = x1_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
TLMonitor_32 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
TLMonitor_33 monitor_1 ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_1_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_1_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_1_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_1_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_1_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_1_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_1_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_1_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_1_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_1_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_1_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_1_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_1_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_1_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_1_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_1_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_1_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_1_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_1_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_1_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
assign auto_in_1_a_ready = auto_in_1_a_ready_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_valid = auto_in_1_d_valid_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_opcode = auto_in_1_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_param = auto_in_1_d_bits_param_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_size = auto_in_1_d_bits_size_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_source = auto_in_1_d_bits_source_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_sink = auto_in_1_d_bits_sink_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_denied = auto_in_1_d_bits_denied_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_data = auto_in_1_d_bits_data_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_corrupt = auto_in_1_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_a_ready = auto_in_0_a_ready_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_valid = auto_in_0_d_valid_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_opcode = auto_in_0_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_size = auto_in_0_d_bits_size_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_source = auto_in_0_d_bits_source_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_denied = auto_in_0_d_bits_denied_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_data = auto_in_0_d_bits_data_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_corrupt = auto_in_0_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_valid = auto_out_1_a_valid_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_param = auto_out_1_a_bits_param_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_size = auto_out_1_a_bits_size_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_source = auto_out_1_a_bits_source_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_mask = auto_out_1_a_bits_mask_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_corrupt = auto_out_1_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_d_ready = auto_out_1_d_ready_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_valid = auto_out_0_a_valid_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_param = auto_out_0_a_bits_param_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_size = auto_out_0_a_bits_size_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_source = auto_out_0_a_bits_source_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_mask = auto_out_0_a_bits_mask_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_corrupt = auto_out_0_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_d_ready = auto_out_0_d_ready_0; // @[ProbePicker.scala:42:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_24 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 2)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<4>(0ha))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<2>(0h2))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_33 = shr(io.in.a.bits.source, 2)
node _source_ok_T_34 = eq(_source_ok_T_33, UInt<4>(0h8))
node _source_ok_T_35 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_T_37 = leq(source_ok_uncommonBits_5, UInt<2>(0h2))
node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37)
node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[12]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_31
connect _source_ok_WIRE[7], _source_ok_T_32
connect _source_ok_WIRE[8], _source_ok_T_38
connect _source_ok_WIRE[9], _source_ok_T_39
connect _source_ok_WIRE[10], _source_ok_T_40
connect _source_ok_WIRE[11], _source_ok_T_41
node _source_ok_T_42 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[2])
node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[3])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[4])
node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[5])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[6])
node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[7])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[8])
node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[9])
node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[10])
node source_ok = or(_source_ok_T_51, _source_ok_WIRE[11])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_64 = shr(io.in.a.bits.source, 2)
node _T_65 = eq(_T_64, UInt<4>(0ha))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<2>(0h2))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_80 = cvt(_T_79)
node _T_81 = and(_T_80, asSInt(UInt<1>(0h0)))
node _T_82 = asSInt(_T_81)
node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0)))
node _T_84 = or(_T_78, _T_83)
node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_88 = cvt(_T_87)
node _T_89 = and(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = asSInt(_T_89)
node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0)))
node _T_92 = or(_T_86, _T_91)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_93 = shr(io.in.a.bits.source, 2)
node _T_94 = eq(_T_93, UInt<4>(0h8))
node _T_95 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_96 = and(_T_94, _T_95)
node _T_97 = leq(uncommonBits_5, UInt<2>(0h2))
node _T_98 = and(_T_96, _T_97)
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = or(_T_99, _T_104)
node _T_106 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_107 = eq(_T_106, UInt<1>(0h0))
node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_109 = cvt(_T_108)
node _T_110 = and(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = asSInt(_T_110)
node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0)))
node _T_113 = or(_T_107, _T_112)
node _T_114 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_115 = eq(_T_114, UInt<1>(0h0))
node _T_116 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_117 = cvt(_T_116)
node _T_118 = and(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = asSInt(_T_118)
node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0)))
node _T_121 = or(_T_115, _T_120)
node _T_122 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_123 = eq(_T_122, UInt<1>(0h0))
node _T_124 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_125 = cvt(_T_124)
node _T_126 = and(_T_125, asSInt(UInt<1>(0h0)))
node _T_127 = asSInt(_T_126)
node _T_128 = eq(_T_127, asSInt(UInt<1>(0h0)))
node _T_129 = or(_T_123, _T_128)
node _T_130 = and(_T_11, _T_24)
node _T_131 = and(_T_130, _T_37)
node _T_132 = and(_T_131, _T_50)
node _T_133 = and(_T_132, _T_63)
node _T_134 = and(_T_133, _T_76)
node _T_135 = and(_T_134, _T_84)
node _T_136 = and(_T_135, _T_92)
node _T_137 = and(_T_136, _T_105)
node _T_138 = and(_T_137, _T_113)
node _T_139 = and(_T_138, _T_121)
node _T_140 = and(_T_139, _T_129)
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_140, UInt<1>(0h1), "") : assert_1
node _T_144 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_144 :
node _T_145 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_146 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_149 = shr(io.in.a.bits.source, 2)
node _T_150 = eq(_T_149, UInt<1>(0h0))
node _T_151 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_152 = and(_T_150, _T_151)
node _T_153 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_154 = and(_T_152, _T_153)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_155 = shr(io.in.a.bits.source, 2)
node _T_156 = eq(_T_155, UInt<1>(0h1))
node _T_157 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_158 = and(_T_156, _T_157)
node _T_159 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_160 = and(_T_158, _T_159)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_161 = shr(io.in.a.bits.source, 2)
node _T_162 = eq(_T_161, UInt<2>(0h2))
node _T_163 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_164 = and(_T_162, _T_163)
node _T_165 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_166 = and(_T_164, _T_165)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_167 = shr(io.in.a.bits.source, 2)
node _T_168 = eq(_T_167, UInt<2>(0h3))
node _T_169 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_170 = and(_T_168, _T_169)
node _T_171 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_172 = and(_T_170, _T_171)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_173 = shr(io.in.a.bits.source, 2)
node _T_174 = eq(_T_173, UInt<4>(0ha))
node _T_175 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_176 = and(_T_174, _T_175)
node _T_177 = leq(uncommonBits_10, UInt<2>(0h2))
node _T_178 = and(_T_176, _T_177)
node _T_179 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_180 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_181 = shr(io.in.a.bits.source, 2)
node _T_182 = eq(_T_181, UInt<4>(0h8))
node _T_183 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_184 = and(_T_182, _T_183)
node _T_185 = leq(uncommonBits_11, UInt<2>(0h2))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_188 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_189 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_190 = or(_T_148, _T_154)
node _T_191 = or(_T_190, _T_160)
node _T_192 = or(_T_191, _T_166)
node _T_193 = or(_T_192, _T_172)
node _T_194 = or(_T_193, _T_178)
node _T_195 = or(_T_194, _T_179)
node _T_196 = or(_T_195, _T_180)
node _T_197 = or(_T_196, _T_186)
node _T_198 = or(_T_197, _T_187)
node _T_199 = or(_T_198, _T_188)
node _T_200 = or(_T_199, _T_189)
node _T_201 = and(_T_147, _T_200)
node _T_202 = or(UInt<1>(0h0), _T_201)
node _T_203 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_204 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_205 = cvt(_T_204)
node _T_206 = and(_T_205, asSInt(UInt<17>(0h10000)))
node _T_207 = asSInt(_T_206)
node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0)))
node _T_209 = and(_T_203, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = and(_T_202, _T_210)
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_211, UInt<1>(0h1), "") : assert_2
node _T_215 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_216 = shr(io.in.a.bits.source, 2)
node _T_217 = eq(_T_216, UInt<1>(0h0))
node _T_218 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_219 = and(_T_217, _T_218)
node _T_220 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_221 = and(_T_219, _T_220)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_222 = shr(io.in.a.bits.source, 2)
node _T_223 = eq(_T_222, UInt<1>(0h1))
node _T_224 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_225 = and(_T_223, _T_224)
node _T_226 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_227 = and(_T_225, _T_226)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_228 = shr(io.in.a.bits.source, 2)
node _T_229 = eq(_T_228, UInt<2>(0h2))
node _T_230 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_231 = and(_T_229, _T_230)
node _T_232 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_233 = and(_T_231, _T_232)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_234 = shr(io.in.a.bits.source, 2)
node _T_235 = eq(_T_234, UInt<2>(0h3))
node _T_236 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_237 = and(_T_235, _T_236)
node _T_238 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_240 = shr(io.in.a.bits.source, 2)
node _T_241 = eq(_T_240, UInt<4>(0ha))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_16, UInt<2>(0h2))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_247 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_248 = shr(io.in.a.bits.source, 2)
node _T_249 = eq(_T_248, UInt<4>(0h8))
node _T_250 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_251 = and(_T_249, _T_250)
node _T_252 = leq(uncommonBits_17, UInt<2>(0h2))
node _T_253 = and(_T_251, _T_252)
node _T_254 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_255 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_256 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[12]
connect _WIRE[0], _T_215
connect _WIRE[1], _T_221
connect _WIRE[2], _T_227
connect _WIRE[3], _T_233
connect _WIRE[4], _T_239
connect _WIRE[5], _T_245
connect _WIRE[6], _T_246
connect _WIRE[7], _T_247
connect _WIRE[8], _T_253
connect _WIRE[9], _T_254
connect _WIRE[10], _T_255
connect _WIRE[11], _T_256
node _T_257 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_258 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_259 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_260 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_261 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_262 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_263 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_264 = mux(_WIRE[5], _T_257, UInt<1>(0h0))
node _T_265 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_266 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_267 = mux(_WIRE[8], _T_258, UInt<1>(0h0))
node _T_268 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_269 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_270 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0))
node _T_271 = or(_T_259, _T_260)
node _T_272 = or(_T_271, _T_261)
node _T_273 = or(_T_272, _T_262)
node _T_274 = or(_T_273, _T_263)
node _T_275 = or(_T_274, _T_264)
node _T_276 = or(_T_275, _T_265)
node _T_277 = or(_T_276, _T_266)
node _T_278 = or(_T_277, _T_267)
node _T_279 = or(_T_278, _T_268)
node _T_280 = or(_T_279, _T_269)
node _T_281 = or(_T_280, _T_270)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_281
node _T_282 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_283 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_284 = and(_T_282, _T_283)
node _T_285 = or(UInt<1>(0h0), _T_284)
node _T_286 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_287 = cvt(_T_286)
node _T_288 = and(_T_287, asSInt(UInt<17>(0h10000)))
node _T_289 = asSInt(_T_288)
node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0)))
node _T_291 = and(_T_285, _T_290)
node _T_292 = or(UInt<1>(0h0), _T_291)
node _T_293 = and(_WIRE_1, _T_292)
node _T_294 = asUInt(reset)
node _T_295 = eq(_T_294, UInt<1>(0h0))
when _T_295 :
node _T_296 = eq(_T_293, UInt<1>(0h0))
when _T_296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_293, UInt<1>(0h1), "") : assert_3
node _T_297 = asUInt(reset)
node _T_298 = eq(_T_297, UInt<1>(0h0))
when _T_298 :
node _T_299 = eq(source_ok, UInt<1>(0h0))
when _T_299 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_300 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_301 = asUInt(reset)
node _T_302 = eq(_T_301, UInt<1>(0h0))
when _T_302 :
node _T_303 = eq(_T_300, UInt<1>(0h0))
when _T_303 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_300, UInt<1>(0h1), "") : assert_5
node _T_304 = asUInt(reset)
node _T_305 = eq(_T_304, UInt<1>(0h0))
when _T_305 :
node _T_306 = eq(is_aligned, UInt<1>(0h0))
when _T_306 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_307 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_308 = asUInt(reset)
node _T_309 = eq(_T_308, UInt<1>(0h0))
when _T_309 :
node _T_310 = eq(_T_307, UInt<1>(0h0))
when _T_310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_307, UInt<1>(0h1), "") : assert_7
node _T_311 = not(io.in.a.bits.mask)
node _T_312 = eq(_T_311, UInt<1>(0h0))
node _T_313 = asUInt(reset)
node _T_314 = eq(_T_313, UInt<1>(0h0))
when _T_314 :
node _T_315 = eq(_T_312, UInt<1>(0h0))
when _T_315 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_312, UInt<1>(0h1), "") : assert_8
node _T_316 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_317 = asUInt(reset)
node _T_318 = eq(_T_317, UInt<1>(0h0))
when _T_318 :
node _T_319 = eq(_T_316, UInt<1>(0h0))
when _T_319 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_316, UInt<1>(0h1), "") : assert_9
node _T_320 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_320 :
node _T_321 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_322 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_323 = and(_T_321, _T_322)
node _T_324 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_325 = shr(io.in.a.bits.source, 2)
node _T_326 = eq(_T_325, UInt<1>(0h0))
node _T_327 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_328 = and(_T_326, _T_327)
node _T_329 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_330 = and(_T_328, _T_329)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_331 = shr(io.in.a.bits.source, 2)
node _T_332 = eq(_T_331, UInt<1>(0h1))
node _T_333 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_334 = and(_T_332, _T_333)
node _T_335 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_336 = and(_T_334, _T_335)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_337 = shr(io.in.a.bits.source, 2)
node _T_338 = eq(_T_337, UInt<2>(0h2))
node _T_339 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_340 = and(_T_338, _T_339)
node _T_341 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_342 = and(_T_340, _T_341)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_343 = shr(io.in.a.bits.source, 2)
node _T_344 = eq(_T_343, UInt<2>(0h3))
node _T_345 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_346 = and(_T_344, _T_345)
node _T_347 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_348 = and(_T_346, _T_347)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_349 = shr(io.in.a.bits.source, 2)
node _T_350 = eq(_T_349, UInt<4>(0ha))
node _T_351 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_352 = and(_T_350, _T_351)
node _T_353 = leq(uncommonBits_22, UInt<2>(0h2))
node _T_354 = and(_T_352, _T_353)
node _T_355 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_356 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_357 = shr(io.in.a.bits.source, 2)
node _T_358 = eq(_T_357, UInt<4>(0h8))
node _T_359 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_360 = and(_T_358, _T_359)
node _T_361 = leq(uncommonBits_23, UInt<2>(0h2))
node _T_362 = and(_T_360, _T_361)
node _T_363 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_364 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_365 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_366 = or(_T_324, _T_330)
node _T_367 = or(_T_366, _T_336)
node _T_368 = or(_T_367, _T_342)
node _T_369 = or(_T_368, _T_348)
node _T_370 = or(_T_369, _T_354)
node _T_371 = or(_T_370, _T_355)
node _T_372 = or(_T_371, _T_356)
node _T_373 = or(_T_372, _T_362)
node _T_374 = or(_T_373, _T_363)
node _T_375 = or(_T_374, _T_364)
node _T_376 = or(_T_375, _T_365)
node _T_377 = and(_T_323, _T_376)
node _T_378 = or(UInt<1>(0h0), _T_377)
node _T_379 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_380 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_381 = cvt(_T_380)
node _T_382 = and(_T_381, asSInt(UInt<17>(0h10000)))
node _T_383 = asSInt(_T_382)
node _T_384 = eq(_T_383, asSInt(UInt<1>(0h0)))
node _T_385 = and(_T_379, _T_384)
node _T_386 = or(UInt<1>(0h0), _T_385)
node _T_387 = and(_T_378, _T_386)
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_387, UInt<1>(0h1), "") : assert_10
node _T_391 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_392 = shr(io.in.a.bits.source, 2)
node _T_393 = eq(_T_392, UInt<1>(0h0))
node _T_394 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_395 = and(_T_393, _T_394)
node _T_396 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_397 = and(_T_395, _T_396)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_398 = shr(io.in.a.bits.source, 2)
node _T_399 = eq(_T_398, UInt<1>(0h1))
node _T_400 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_401 = and(_T_399, _T_400)
node _T_402 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_403 = and(_T_401, _T_402)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_404 = shr(io.in.a.bits.source, 2)
node _T_405 = eq(_T_404, UInt<2>(0h2))
node _T_406 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_407 = and(_T_405, _T_406)
node _T_408 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_409 = and(_T_407, _T_408)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_410 = shr(io.in.a.bits.source, 2)
node _T_411 = eq(_T_410, UInt<2>(0h3))
node _T_412 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_413 = and(_T_411, _T_412)
node _T_414 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_415 = and(_T_413, _T_414)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_416 = shr(io.in.a.bits.source, 2)
node _T_417 = eq(_T_416, UInt<4>(0ha))
node _T_418 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_419 = and(_T_417, _T_418)
node _T_420 = leq(uncommonBits_28, UInt<2>(0h2))
node _T_421 = and(_T_419, _T_420)
node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_423 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_424 = shr(io.in.a.bits.source, 2)
node _T_425 = eq(_T_424, UInt<4>(0h8))
node _T_426 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_427 = and(_T_425, _T_426)
node _T_428 = leq(uncommonBits_29, UInt<2>(0h2))
node _T_429 = and(_T_427, _T_428)
node _T_430 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_431 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_432 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[12]
connect _WIRE_2[0], _T_391
connect _WIRE_2[1], _T_397
connect _WIRE_2[2], _T_403
connect _WIRE_2[3], _T_409
connect _WIRE_2[4], _T_415
connect _WIRE_2[5], _T_421
connect _WIRE_2[6], _T_422
connect _WIRE_2[7], _T_423
connect _WIRE_2[8], _T_429
connect _WIRE_2[9], _T_430
connect _WIRE_2[10], _T_431
connect _WIRE_2[11], _T_432
node _T_433 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_434 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_435 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_436 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_437 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_438 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_439 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_440 = mux(_WIRE_2[5], _T_433, UInt<1>(0h0))
node _T_441 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_442 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_443 = mux(_WIRE_2[8], _T_434, UInt<1>(0h0))
node _T_444 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_445 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_446 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0))
node _T_447 = or(_T_435, _T_436)
node _T_448 = or(_T_447, _T_437)
node _T_449 = or(_T_448, _T_438)
node _T_450 = or(_T_449, _T_439)
node _T_451 = or(_T_450, _T_440)
node _T_452 = or(_T_451, _T_441)
node _T_453 = or(_T_452, _T_442)
node _T_454 = or(_T_453, _T_443)
node _T_455 = or(_T_454, _T_444)
node _T_456 = or(_T_455, _T_445)
node _T_457 = or(_T_456, _T_446)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_457
node _T_458 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_459 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_460 = and(_T_458, _T_459)
node _T_461 = or(UInt<1>(0h0), _T_460)
node _T_462 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_463 = cvt(_T_462)
node _T_464 = and(_T_463, asSInt(UInt<17>(0h10000)))
node _T_465 = asSInt(_T_464)
node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0)))
node _T_467 = and(_T_461, _T_466)
node _T_468 = or(UInt<1>(0h0), _T_467)
node _T_469 = and(_WIRE_3, _T_468)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_469, UInt<1>(0h1), "") : assert_11
node _T_473 = asUInt(reset)
node _T_474 = eq(_T_473, UInt<1>(0h0))
when _T_474 :
node _T_475 = eq(source_ok, UInt<1>(0h0))
when _T_475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_476 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_477 = asUInt(reset)
node _T_478 = eq(_T_477, UInt<1>(0h0))
when _T_478 :
node _T_479 = eq(_T_476, UInt<1>(0h0))
when _T_479 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_476, UInt<1>(0h1), "") : assert_13
node _T_480 = asUInt(reset)
node _T_481 = eq(_T_480, UInt<1>(0h0))
when _T_481 :
node _T_482 = eq(is_aligned, UInt<1>(0h0))
when _T_482 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_483 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_484 = asUInt(reset)
node _T_485 = eq(_T_484, UInt<1>(0h0))
when _T_485 :
node _T_486 = eq(_T_483, UInt<1>(0h0))
when _T_486 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_483, UInt<1>(0h1), "") : assert_15
node _T_487 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_488 = asUInt(reset)
node _T_489 = eq(_T_488, UInt<1>(0h0))
when _T_489 :
node _T_490 = eq(_T_487, UInt<1>(0h0))
when _T_490 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_487, UInt<1>(0h1), "") : assert_16
node _T_491 = not(io.in.a.bits.mask)
node _T_492 = eq(_T_491, UInt<1>(0h0))
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(_T_492, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_492, UInt<1>(0h1), "") : assert_17
node _T_496 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_497 = asUInt(reset)
node _T_498 = eq(_T_497, UInt<1>(0h0))
when _T_498 :
node _T_499 = eq(_T_496, UInt<1>(0h0))
when _T_499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_496, UInt<1>(0h1), "") : assert_18
node _T_500 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_500 :
node _T_501 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_502 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_503 = and(_T_501, _T_502)
node _T_504 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_505 = shr(io.in.a.bits.source, 2)
node _T_506 = eq(_T_505, UInt<1>(0h0))
node _T_507 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_508 = and(_T_506, _T_507)
node _T_509 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_510 = and(_T_508, _T_509)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_511 = shr(io.in.a.bits.source, 2)
node _T_512 = eq(_T_511, UInt<1>(0h1))
node _T_513 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_514 = and(_T_512, _T_513)
node _T_515 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_516 = and(_T_514, _T_515)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_517 = shr(io.in.a.bits.source, 2)
node _T_518 = eq(_T_517, UInt<2>(0h2))
node _T_519 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_520 = and(_T_518, _T_519)
node _T_521 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_522 = and(_T_520, _T_521)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_523 = shr(io.in.a.bits.source, 2)
node _T_524 = eq(_T_523, UInt<2>(0h3))
node _T_525 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_526 = and(_T_524, _T_525)
node _T_527 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_528 = and(_T_526, _T_527)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_529 = shr(io.in.a.bits.source, 2)
node _T_530 = eq(_T_529, UInt<4>(0ha))
node _T_531 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_532 = and(_T_530, _T_531)
node _T_533 = leq(uncommonBits_34, UInt<2>(0h2))
node _T_534 = and(_T_532, _T_533)
node _T_535 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_536 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_537 = shr(io.in.a.bits.source, 2)
node _T_538 = eq(_T_537, UInt<4>(0h8))
node _T_539 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_540 = and(_T_538, _T_539)
node _T_541 = leq(uncommonBits_35, UInt<2>(0h2))
node _T_542 = and(_T_540, _T_541)
node _T_543 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_544 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_545 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_546 = or(_T_504, _T_510)
node _T_547 = or(_T_546, _T_516)
node _T_548 = or(_T_547, _T_522)
node _T_549 = or(_T_548, _T_528)
node _T_550 = or(_T_549, _T_534)
node _T_551 = or(_T_550, _T_535)
node _T_552 = or(_T_551, _T_536)
node _T_553 = or(_T_552, _T_542)
node _T_554 = or(_T_553, _T_543)
node _T_555 = or(_T_554, _T_544)
node _T_556 = or(_T_555, _T_545)
node _T_557 = and(_T_503, _T_556)
node _T_558 = or(UInt<1>(0h0), _T_557)
node _T_559 = asUInt(reset)
node _T_560 = eq(_T_559, UInt<1>(0h0))
when _T_560 :
node _T_561 = eq(_T_558, UInt<1>(0h0))
when _T_561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_558, UInt<1>(0h1), "") : assert_19
node _T_562 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_563 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_564 = and(_T_562, _T_563)
node _T_565 = or(UInt<1>(0h0), _T_564)
node _T_566 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_567 = cvt(_T_566)
node _T_568 = and(_T_567, asSInt(UInt<17>(0h10000)))
node _T_569 = asSInt(_T_568)
node _T_570 = eq(_T_569, asSInt(UInt<1>(0h0)))
node _T_571 = and(_T_565, _T_570)
node _T_572 = or(UInt<1>(0h0), _T_571)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_572, UInt<1>(0h1), "") : assert_20
node _T_576 = asUInt(reset)
node _T_577 = eq(_T_576, UInt<1>(0h0))
when _T_577 :
node _T_578 = eq(source_ok, UInt<1>(0h0))
when _T_578 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_579 = asUInt(reset)
node _T_580 = eq(_T_579, UInt<1>(0h0))
when _T_580 :
node _T_581 = eq(is_aligned, UInt<1>(0h0))
when _T_581 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_582 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_583 = asUInt(reset)
node _T_584 = eq(_T_583, UInt<1>(0h0))
when _T_584 :
node _T_585 = eq(_T_582, UInt<1>(0h0))
when _T_585 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_582, UInt<1>(0h1), "") : assert_23
node _T_586 = eq(io.in.a.bits.mask, mask)
node _T_587 = asUInt(reset)
node _T_588 = eq(_T_587, UInt<1>(0h0))
when _T_588 :
node _T_589 = eq(_T_586, UInt<1>(0h0))
when _T_589 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_586, UInt<1>(0h1), "") : assert_24
node _T_590 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_591 = asUInt(reset)
node _T_592 = eq(_T_591, UInt<1>(0h0))
when _T_592 :
node _T_593 = eq(_T_590, UInt<1>(0h0))
when _T_593 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_590, UInt<1>(0h1), "") : assert_25
node _T_594 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_594 :
node _T_595 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_596 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_597 = and(_T_595, _T_596)
node _T_598 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_599 = shr(io.in.a.bits.source, 2)
node _T_600 = eq(_T_599, UInt<1>(0h0))
node _T_601 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_602 = and(_T_600, _T_601)
node _T_603 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_604 = and(_T_602, _T_603)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_605 = shr(io.in.a.bits.source, 2)
node _T_606 = eq(_T_605, UInt<1>(0h1))
node _T_607 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_608 = and(_T_606, _T_607)
node _T_609 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_610 = and(_T_608, _T_609)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_611 = shr(io.in.a.bits.source, 2)
node _T_612 = eq(_T_611, UInt<2>(0h2))
node _T_613 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_614 = and(_T_612, _T_613)
node _T_615 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_616 = and(_T_614, _T_615)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_617 = shr(io.in.a.bits.source, 2)
node _T_618 = eq(_T_617, UInt<2>(0h3))
node _T_619 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_620 = and(_T_618, _T_619)
node _T_621 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_622 = and(_T_620, _T_621)
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_623 = shr(io.in.a.bits.source, 2)
node _T_624 = eq(_T_623, UInt<4>(0ha))
node _T_625 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_626 = and(_T_624, _T_625)
node _T_627 = leq(uncommonBits_40, UInt<2>(0h2))
node _T_628 = and(_T_626, _T_627)
node _T_629 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_630 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_631 = shr(io.in.a.bits.source, 2)
node _T_632 = eq(_T_631, UInt<4>(0h8))
node _T_633 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_634 = and(_T_632, _T_633)
node _T_635 = leq(uncommonBits_41, UInt<2>(0h2))
node _T_636 = and(_T_634, _T_635)
node _T_637 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_638 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_639 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_640 = or(_T_598, _T_604)
node _T_641 = or(_T_640, _T_610)
node _T_642 = or(_T_641, _T_616)
node _T_643 = or(_T_642, _T_622)
node _T_644 = or(_T_643, _T_628)
node _T_645 = or(_T_644, _T_629)
node _T_646 = or(_T_645, _T_630)
node _T_647 = or(_T_646, _T_636)
node _T_648 = or(_T_647, _T_637)
node _T_649 = or(_T_648, _T_638)
node _T_650 = or(_T_649, _T_639)
node _T_651 = and(_T_597, _T_650)
node _T_652 = or(UInt<1>(0h0), _T_651)
node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_654 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_655 = and(_T_653, _T_654)
node _T_656 = or(UInt<1>(0h0), _T_655)
node _T_657 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_658 = cvt(_T_657)
node _T_659 = and(_T_658, asSInt(UInt<17>(0h10000)))
node _T_660 = asSInt(_T_659)
node _T_661 = eq(_T_660, asSInt(UInt<1>(0h0)))
node _T_662 = and(_T_656, _T_661)
node _T_663 = or(UInt<1>(0h0), _T_662)
node _T_664 = and(_T_652, _T_663)
node _T_665 = asUInt(reset)
node _T_666 = eq(_T_665, UInt<1>(0h0))
when _T_666 :
node _T_667 = eq(_T_664, UInt<1>(0h0))
when _T_667 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_664, UInt<1>(0h1), "") : assert_26
node _T_668 = asUInt(reset)
node _T_669 = eq(_T_668, UInt<1>(0h0))
when _T_669 :
node _T_670 = eq(source_ok, UInt<1>(0h0))
when _T_670 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_671 = asUInt(reset)
node _T_672 = eq(_T_671, UInt<1>(0h0))
when _T_672 :
node _T_673 = eq(is_aligned, UInt<1>(0h0))
when _T_673 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_674 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_675 = asUInt(reset)
node _T_676 = eq(_T_675, UInt<1>(0h0))
when _T_676 :
node _T_677 = eq(_T_674, UInt<1>(0h0))
when _T_677 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_674, UInt<1>(0h1), "") : assert_29
node _T_678 = eq(io.in.a.bits.mask, mask)
node _T_679 = asUInt(reset)
node _T_680 = eq(_T_679, UInt<1>(0h0))
when _T_680 :
node _T_681 = eq(_T_678, UInt<1>(0h0))
when _T_681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_678, UInt<1>(0h1), "") : assert_30
node _T_682 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_682 :
node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_684 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_685 = and(_T_683, _T_684)
node _T_686 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_687 = shr(io.in.a.bits.source, 2)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_690 = and(_T_688, _T_689)
node _T_691 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_692 = and(_T_690, _T_691)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_693 = shr(io.in.a.bits.source, 2)
node _T_694 = eq(_T_693, UInt<1>(0h1))
node _T_695 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_696 = and(_T_694, _T_695)
node _T_697 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_698 = and(_T_696, _T_697)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_699 = shr(io.in.a.bits.source, 2)
node _T_700 = eq(_T_699, UInt<2>(0h2))
node _T_701 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_702 = and(_T_700, _T_701)
node _T_703 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_704 = and(_T_702, _T_703)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_705 = shr(io.in.a.bits.source, 2)
node _T_706 = eq(_T_705, UInt<2>(0h3))
node _T_707 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_708 = and(_T_706, _T_707)
node _T_709 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_710 = and(_T_708, _T_709)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0)
node _T_711 = shr(io.in.a.bits.source, 2)
node _T_712 = eq(_T_711, UInt<4>(0ha))
node _T_713 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_714 = and(_T_712, _T_713)
node _T_715 = leq(uncommonBits_46, UInt<2>(0h2))
node _T_716 = and(_T_714, _T_715)
node _T_717 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_718 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0)
node _T_719 = shr(io.in.a.bits.source, 2)
node _T_720 = eq(_T_719, UInt<4>(0h8))
node _T_721 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_722 = and(_T_720, _T_721)
node _T_723 = leq(uncommonBits_47, UInt<2>(0h2))
node _T_724 = and(_T_722, _T_723)
node _T_725 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_726 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_727 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_728 = or(_T_686, _T_692)
node _T_729 = or(_T_728, _T_698)
node _T_730 = or(_T_729, _T_704)
node _T_731 = or(_T_730, _T_710)
node _T_732 = or(_T_731, _T_716)
node _T_733 = or(_T_732, _T_717)
node _T_734 = or(_T_733, _T_718)
node _T_735 = or(_T_734, _T_724)
node _T_736 = or(_T_735, _T_725)
node _T_737 = or(_T_736, _T_726)
node _T_738 = or(_T_737, _T_727)
node _T_739 = and(_T_685, _T_738)
node _T_740 = or(UInt<1>(0h0), _T_739)
node _T_741 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_742 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_743 = and(_T_741, _T_742)
node _T_744 = or(UInt<1>(0h0), _T_743)
node _T_745 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_746 = cvt(_T_745)
node _T_747 = and(_T_746, asSInt(UInt<17>(0h10000)))
node _T_748 = asSInt(_T_747)
node _T_749 = eq(_T_748, asSInt(UInt<1>(0h0)))
node _T_750 = and(_T_744, _T_749)
node _T_751 = or(UInt<1>(0h0), _T_750)
node _T_752 = and(_T_740, _T_751)
node _T_753 = asUInt(reset)
node _T_754 = eq(_T_753, UInt<1>(0h0))
when _T_754 :
node _T_755 = eq(_T_752, UInt<1>(0h0))
when _T_755 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_752, UInt<1>(0h1), "") : assert_31
node _T_756 = asUInt(reset)
node _T_757 = eq(_T_756, UInt<1>(0h0))
when _T_757 :
node _T_758 = eq(source_ok, UInt<1>(0h0))
when _T_758 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_759 = asUInt(reset)
node _T_760 = eq(_T_759, UInt<1>(0h0))
when _T_760 :
node _T_761 = eq(is_aligned, UInt<1>(0h0))
when _T_761 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_762 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_763 = asUInt(reset)
node _T_764 = eq(_T_763, UInt<1>(0h0))
when _T_764 :
node _T_765 = eq(_T_762, UInt<1>(0h0))
when _T_765 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_762, UInt<1>(0h1), "") : assert_34
node _T_766 = not(mask)
node _T_767 = and(io.in.a.bits.mask, _T_766)
node _T_768 = eq(_T_767, UInt<1>(0h0))
node _T_769 = asUInt(reset)
node _T_770 = eq(_T_769, UInt<1>(0h0))
when _T_770 :
node _T_771 = eq(_T_768, UInt<1>(0h0))
when _T_771 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_768, UInt<1>(0h1), "") : assert_35
node _T_772 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_772 :
node _T_773 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_774 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_775 = and(_T_773, _T_774)
node _T_776 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_777 = shr(io.in.a.bits.source, 2)
node _T_778 = eq(_T_777, UInt<1>(0h0))
node _T_779 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_780 = and(_T_778, _T_779)
node _T_781 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_782 = and(_T_780, _T_781)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_783 = shr(io.in.a.bits.source, 2)
node _T_784 = eq(_T_783, UInt<1>(0h1))
node _T_785 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_786 = and(_T_784, _T_785)
node _T_787 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_788 = and(_T_786, _T_787)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_789 = shr(io.in.a.bits.source, 2)
node _T_790 = eq(_T_789, UInt<2>(0h2))
node _T_791 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_792 = and(_T_790, _T_791)
node _T_793 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_794 = and(_T_792, _T_793)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_795 = shr(io.in.a.bits.source, 2)
node _T_796 = eq(_T_795, UInt<2>(0h3))
node _T_797 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_798 = and(_T_796, _T_797)
node _T_799 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_800 = and(_T_798, _T_799)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0)
node _T_801 = shr(io.in.a.bits.source, 2)
node _T_802 = eq(_T_801, UInt<4>(0ha))
node _T_803 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_804 = and(_T_802, _T_803)
node _T_805 = leq(uncommonBits_52, UInt<2>(0h2))
node _T_806 = and(_T_804, _T_805)
node _T_807 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_808 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0)
node _T_809 = shr(io.in.a.bits.source, 2)
node _T_810 = eq(_T_809, UInt<4>(0h8))
node _T_811 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_812 = and(_T_810, _T_811)
node _T_813 = leq(uncommonBits_53, UInt<2>(0h2))
node _T_814 = and(_T_812, _T_813)
node _T_815 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_816 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_817 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_818 = or(_T_776, _T_782)
node _T_819 = or(_T_818, _T_788)
node _T_820 = or(_T_819, _T_794)
node _T_821 = or(_T_820, _T_800)
node _T_822 = or(_T_821, _T_806)
node _T_823 = or(_T_822, _T_807)
node _T_824 = or(_T_823, _T_808)
node _T_825 = or(_T_824, _T_814)
node _T_826 = or(_T_825, _T_815)
node _T_827 = or(_T_826, _T_816)
node _T_828 = or(_T_827, _T_817)
node _T_829 = and(_T_775, _T_828)
node _T_830 = or(UInt<1>(0h0), _T_829)
node _T_831 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_832 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_833 = cvt(_T_832)
node _T_834 = and(_T_833, asSInt(UInt<17>(0h10000)))
node _T_835 = asSInt(_T_834)
node _T_836 = eq(_T_835, asSInt(UInt<1>(0h0)))
node _T_837 = and(_T_831, _T_836)
node _T_838 = or(UInt<1>(0h0), _T_837)
node _T_839 = and(_T_830, _T_838)
node _T_840 = asUInt(reset)
node _T_841 = eq(_T_840, UInt<1>(0h0))
when _T_841 :
node _T_842 = eq(_T_839, UInt<1>(0h0))
when _T_842 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_839, UInt<1>(0h1), "") : assert_36
node _T_843 = asUInt(reset)
node _T_844 = eq(_T_843, UInt<1>(0h0))
when _T_844 :
node _T_845 = eq(source_ok, UInt<1>(0h0))
when _T_845 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_846 = asUInt(reset)
node _T_847 = eq(_T_846, UInt<1>(0h0))
when _T_847 :
node _T_848 = eq(is_aligned, UInt<1>(0h0))
when _T_848 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_849 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_850 = asUInt(reset)
node _T_851 = eq(_T_850, UInt<1>(0h0))
when _T_851 :
node _T_852 = eq(_T_849, UInt<1>(0h0))
when _T_852 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_849, UInt<1>(0h1), "") : assert_39
node _T_853 = eq(io.in.a.bits.mask, mask)
node _T_854 = asUInt(reset)
node _T_855 = eq(_T_854, UInt<1>(0h0))
when _T_855 :
node _T_856 = eq(_T_853, UInt<1>(0h0))
when _T_856 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_853, UInt<1>(0h1), "") : assert_40
node _T_857 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_857 :
node _T_858 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_859 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_860 = and(_T_858, _T_859)
node _T_861 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0)
node _T_862 = shr(io.in.a.bits.source, 2)
node _T_863 = eq(_T_862, UInt<1>(0h0))
node _T_864 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_865 = and(_T_863, _T_864)
node _T_866 = leq(uncommonBits_54, UInt<2>(0h3))
node _T_867 = and(_T_865, _T_866)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0)
node _T_868 = shr(io.in.a.bits.source, 2)
node _T_869 = eq(_T_868, UInt<1>(0h1))
node _T_870 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_871 = and(_T_869, _T_870)
node _T_872 = leq(uncommonBits_55, UInt<2>(0h3))
node _T_873 = and(_T_871, _T_872)
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_874 = shr(io.in.a.bits.source, 2)
node _T_875 = eq(_T_874, UInt<2>(0h2))
node _T_876 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_877 = and(_T_875, _T_876)
node _T_878 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_879 = and(_T_877, _T_878)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_880 = shr(io.in.a.bits.source, 2)
node _T_881 = eq(_T_880, UInt<2>(0h3))
node _T_882 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_883 = and(_T_881, _T_882)
node _T_884 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_885 = and(_T_883, _T_884)
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0)
node _T_886 = shr(io.in.a.bits.source, 2)
node _T_887 = eq(_T_886, UInt<4>(0ha))
node _T_888 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_889 = and(_T_887, _T_888)
node _T_890 = leq(uncommonBits_58, UInt<2>(0h2))
node _T_891 = and(_T_889, _T_890)
node _T_892 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_893 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0)
node _T_894 = shr(io.in.a.bits.source, 2)
node _T_895 = eq(_T_894, UInt<4>(0h8))
node _T_896 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_897 = and(_T_895, _T_896)
node _T_898 = leq(uncommonBits_59, UInt<2>(0h2))
node _T_899 = and(_T_897, _T_898)
node _T_900 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_901 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_902 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_903 = or(_T_861, _T_867)
node _T_904 = or(_T_903, _T_873)
node _T_905 = or(_T_904, _T_879)
node _T_906 = or(_T_905, _T_885)
node _T_907 = or(_T_906, _T_891)
node _T_908 = or(_T_907, _T_892)
node _T_909 = or(_T_908, _T_893)
node _T_910 = or(_T_909, _T_899)
node _T_911 = or(_T_910, _T_900)
node _T_912 = or(_T_911, _T_901)
node _T_913 = or(_T_912, _T_902)
node _T_914 = and(_T_860, _T_913)
node _T_915 = or(UInt<1>(0h0), _T_914)
node _T_916 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_917 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_918 = cvt(_T_917)
node _T_919 = and(_T_918, asSInt(UInt<17>(0h10000)))
node _T_920 = asSInt(_T_919)
node _T_921 = eq(_T_920, asSInt(UInt<1>(0h0)))
node _T_922 = and(_T_916, _T_921)
node _T_923 = or(UInt<1>(0h0), _T_922)
node _T_924 = and(_T_915, _T_923)
node _T_925 = asUInt(reset)
node _T_926 = eq(_T_925, UInt<1>(0h0))
when _T_926 :
node _T_927 = eq(_T_924, UInt<1>(0h0))
when _T_927 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_924, UInt<1>(0h1), "") : assert_41
node _T_928 = asUInt(reset)
node _T_929 = eq(_T_928, UInt<1>(0h0))
when _T_929 :
node _T_930 = eq(source_ok, UInt<1>(0h0))
when _T_930 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_931 = asUInt(reset)
node _T_932 = eq(_T_931, UInt<1>(0h0))
when _T_932 :
node _T_933 = eq(is_aligned, UInt<1>(0h0))
when _T_933 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_934 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_935 = asUInt(reset)
node _T_936 = eq(_T_935, UInt<1>(0h0))
when _T_936 :
node _T_937 = eq(_T_934, UInt<1>(0h0))
when _T_937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_934, UInt<1>(0h1), "") : assert_44
node _T_938 = eq(io.in.a.bits.mask, mask)
node _T_939 = asUInt(reset)
node _T_940 = eq(_T_939, UInt<1>(0h0))
when _T_940 :
node _T_941 = eq(_T_938, UInt<1>(0h0))
when _T_941 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_938, UInt<1>(0h1), "") : assert_45
node _T_942 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_942 :
node _T_943 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_944 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_945 = and(_T_943, _T_944)
node _T_946 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0)
node _T_947 = shr(io.in.a.bits.source, 2)
node _T_948 = eq(_T_947, UInt<1>(0h0))
node _T_949 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_950 = and(_T_948, _T_949)
node _T_951 = leq(uncommonBits_60, UInt<2>(0h3))
node _T_952 = and(_T_950, _T_951)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0)
node _T_953 = shr(io.in.a.bits.source, 2)
node _T_954 = eq(_T_953, UInt<1>(0h1))
node _T_955 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_956 = and(_T_954, _T_955)
node _T_957 = leq(uncommonBits_61, UInt<2>(0h3))
node _T_958 = and(_T_956, _T_957)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0)
node _T_959 = shr(io.in.a.bits.source, 2)
node _T_960 = eq(_T_959, UInt<2>(0h2))
node _T_961 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_962 = and(_T_960, _T_961)
node _T_963 = leq(uncommonBits_62, UInt<2>(0h3))
node _T_964 = and(_T_962, _T_963)
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_965 = shr(io.in.a.bits.source, 2)
node _T_966 = eq(_T_965, UInt<2>(0h3))
node _T_967 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_968 = and(_T_966, _T_967)
node _T_969 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_970 = and(_T_968, _T_969)
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0)
node _T_971 = shr(io.in.a.bits.source, 2)
node _T_972 = eq(_T_971, UInt<4>(0ha))
node _T_973 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_974 = and(_T_972, _T_973)
node _T_975 = leq(uncommonBits_64, UInt<2>(0h2))
node _T_976 = and(_T_974, _T_975)
node _T_977 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_978 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0)
node _T_979 = shr(io.in.a.bits.source, 2)
node _T_980 = eq(_T_979, UInt<4>(0h8))
node _T_981 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_982 = and(_T_980, _T_981)
node _T_983 = leq(uncommonBits_65, UInt<2>(0h2))
node _T_984 = and(_T_982, _T_983)
node _T_985 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_986 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_987 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_988 = or(_T_946, _T_952)
node _T_989 = or(_T_988, _T_958)
node _T_990 = or(_T_989, _T_964)
node _T_991 = or(_T_990, _T_970)
node _T_992 = or(_T_991, _T_976)
node _T_993 = or(_T_992, _T_977)
node _T_994 = or(_T_993, _T_978)
node _T_995 = or(_T_994, _T_984)
node _T_996 = or(_T_995, _T_985)
node _T_997 = or(_T_996, _T_986)
node _T_998 = or(_T_997, _T_987)
node _T_999 = and(_T_945, _T_998)
node _T_1000 = or(UInt<1>(0h0), _T_999)
node _T_1001 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1002 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1003 = cvt(_T_1002)
node _T_1004 = and(_T_1003, asSInt(UInt<17>(0h10000)))
node _T_1005 = asSInt(_T_1004)
node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0)))
node _T_1007 = and(_T_1001, _T_1006)
node _T_1008 = or(UInt<1>(0h0), _T_1007)
node _T_1009 = and(_T_1000, _T_1008)
node _T_1010 = asUInt(reset)
node _T_1011 = eq(_T_1010, UInt<1>(0h0))
when _T_1011 :
node _T_1012 = eq(_T_1009, UInt<1>(0h0))
when _T_1012 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1009, UInt<1>(0h1), "") : assert_46
node _T_1013 = asUInt(reset)
node _T_1014 = eq(_T_1013, UInt<1>(0h0))
when _T_1014 :
node _T_1015 = eq(source_ok, UInt<1>(0h0))
when _T_1015 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1016 = asUInt(reset)
node _T_1017 = eq(_T_1016, UInt<1>(0h0))
when _T_1017 :
node _T_1018 = eq(is_aligned, UInt<1>(0h0))
when _T_1018 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1019 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1020 = asUInt(reset)
node _T_1021 = eq(_T_1020, UInt<1>(0h0))
when _T_1021 :
node _T_1022 = eq(_T_1019, UInt<1>(0h0))
when _T_1022 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1019, UInt<1>(0h1), "") : assert_49
node _T_1023 = eq(io.in.a.bits.mask, mask)
node _T_1024 = asUInt(reset)
node _T_1025 = eq(_T_1024, UInt<1>(0h0))
when _T_1025 :
node _T_1026 = eq(_T_1023, UInt<1>(0h0))
when _T_1026 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1023, UInt<1>(0h1), "") : assert_50
node _T_1027 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1028 = asUInt(reset)
node _T_1029 = eq(_T_1028, UInt<1>(0h0))
when _T_1029 :
node _T_1030 = eq(_T_1027, UInt<1>(0h0))
when _T_1030 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1027, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1031 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1032 = asUInt(reset)
node _T_1033 = eq(_T_1032, UInt<1>(0h0))
when _T_1033 :
node _T_1034 = eq(_T_1031, UInt<1>(0h0))
when _T_1034 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1031, UInt<1>(0h1), "") : assert_52
node _source_ok_T_52 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_53 = shr(io.in.d.bits.source, 2)
node _source_ok_T_54 = eq(_source_ok_T_53, UInt<1>(0h0))
node _source_ok_T_55 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_T_57 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_59 = shr(io.in.d.bits.source, 2)
node _source_ok_T_60 = eq(_source_ok_T_59, UInt<1>(0h1))
node _source_ok_T_61 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61)
node _source_ok_T_63 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_65 = shr(io.in.d.bits.source, 2)
node _source_ok_T_66 = eq(_source_ok_T_65, UInt<2>(0h2))
node _source_ok_T_67 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67)
node _source_ok_T_69 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_71 = shr(io.in.d.bits.source, 2)
node _source_ok_T_72 = eq(_source_ok_T_71, UInt<2>(0h3))
node _source_ok_T_73 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73)
node _source_ok_T_75 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75)
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0)
node _source_ok_T_77 = shr(io.in.d.bits.source, 2)
node _source_ok_T_78 = eq(_source_ok_T_77, UInt<4>(0ha))
node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79)
node _source_ok_T_81 = leq(source_ok_uncommonBits_10, UInt<2>(0h2))
node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81)
node _source_ok_T_83 = eq(io.in.d.bits.source, UInt<6>(0h2b))
node _source_ok_T_84 = eq(io.in.d.bits.source, UInt<6>(0h2c))
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0)
node _source_ok_T_85 = shr(io.in.d.bits.source, 2)
node _source_ok_T_86 = eq(_source_ok_T_85, UInt<4>(0h8))
node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87)
node _source_ok_T_89 = leq(source_ok_uncommonBits_11, UInt<2>(0h2))
node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89)
node _source_ok_T_91 = eq(io.in.d.bits.source, UInt<6>(0h23))
node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<6>(0h24))
node _source_ok_T_93 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[12]
connect _source_ok_WIRE_1[0], _source_ok_T_52
connect _source_ok_WIRE_1[1], _source_ok_T_58
connect _source_ok_WIRE_1[2], _source_ok_T_64
connect _source_ok_WIRE_1[3], _source_ok_T_70
connect _source_ok_WIRE_1[4], _source_ok_T_76
connect _source_ok_WIRE_1[5], _source_ok_T_82
connect _source_ok_WIRE_1[6], _source_ok_T_83
connect _source_ok_WIRE_1[7], _source_ok_T_84
connect _source_ok_WIRE_1[8], _source_ok_T_90
connect _source_ok_WIRE_1[9], _source_ok_T_91
connect _source_ok_WIRE_1[10], _source_ok_T_92
connect _source_ok_WIRE_1[11], _source_ok_T_93
node _source_ok_T_94 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[2])
node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[3])
node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[4])
node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[5])
node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[6])
node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE_1[7])
node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE_1[8])
node _source_ok_T_102 = or(_source_ok_T_101, _source_ok_WIRE_1[9])
node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[10])
node source_ok_1 = or(_source_ok_T_103, _source_ok_WIRE_1[11])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1035 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1035 :
node _T_1036 = asUInt(reset)
node _T_1037 = eq(_T_1036, UInt<1>(0h0))
when _T_1037 :
node _T_1038 = eq(source_ok_1, UInt<1>(0h0))
when _T_1038 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1039 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1040 = asUInt(reset)
node _T_1041 = eq(_T_1040, UInt<1>(0h0))
when _T_1041 :
node _T_1042 = eq(_T_1039, UInt<1>(0h0))
when _T_1042 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1039, UInt<1>(0h1), "") : assert_54
node _T_1043 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1044 = asUInt(reset)
node _T_1045 = eq(_T_1044, UInt<1>(0h0))
when _T_1045 :
node _T_1046 = eq(_T_1043, UInt<1>(0h0))
when _T_1046 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1043, UInt<1>(0h1), "") : assert_55
node _T_1047 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1048 = asUInt(reset)
node _T_1049 = eq(_T_1048, UInt<1>(0h0))
when _T_1049 :
node _T_1050 = eq(_T_1047, UInt<1>(0h0))
when _T_1050 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1047, UInt<1>(0h1), "") : assert_56
node _T_1051 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1052 = asUInt(reset)
node _T_1053 = eq(_T_1052, UInt<1>(0h0))
when _T_1053 :
node _T_1054 = eq(_T_1051, UInt<1>(0h0))
when _T_1054 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1051, UInt<1>(0h1), "") : assert_57
node _T_1055 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1055 :
node _T_1056 = asUInt(reset)
node _T_1057 = eq(_T_1056, UInt<1>(0h0))
when _T_1057 :
node _T_1058 = eq(source_ok_1, UInt<1>(0h0))
when _T_1058 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1059 = asUInt(reset)
node _T_1060 = eq(_T_1059, UInt<1>(0h0))
when _T_1060 :
node _T_1061 = eq(sink_ok, UInt<1>(0h0))
when _T_1061 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1062 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1063 = asUInt(reset)
node _T_1064 = eq(_T_1063, UInt<1>(0h0))
when _T_1064 :
node _T_1065 = eq(_T_1062, UInt<1>(0h0))
when _T_1065 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1062, UInt<1>(0h1), "") : assert_60
node _T_1066 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1067 = asUInt(reset)
node _T_1068 = eq(_T_1067, UInt<1>(0h0))
when _T_1068 :
node _T_1069 = eq(_T_1066, UInt<1>(0h0))
when _T_1069 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1066, UInt<1>(0h1), "") : assert_61
node _T_1070 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_62
node _T_1074 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1075 = asUInt(reset)
node _T_1076 = eq(_T_1075, UInt<1>(0h0))
when _T_1076 :
node _T_1077 = eq(_T_1074, UInt<1>(0h0))
when _T_1077 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1074, UInt<1>(0h1), "") : assert_63
node _T_1078 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1079 = or(UInt<1>(0h0), _T_1078)
node _T_1080 = asUInt(reset)
node _T_1081 = eq(_T_1080, UInt<1>(0h0))
when _T_1081 :
node _T_1082 = eq(_T_1079, UInt<1>(0h0))
when _T_1082 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1079, UInt<1>(0h1), "") : assert_64
node _T_1083 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1083 :
node _T_1084 = asUInt(reset)
node _T_1085 = eq(_T_1084, UInt<1>(0h0))
when _T_1085 :
node _T_1086 = eq(source_ok_1, UInt<1>(0h0))
when _T_1086 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1087 = asUInt(reset)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = eq(sink_ok, UInt<1>(0h0))
when _T_1089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1090 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1091 = asUInt(reset)
node _T_1092 = eq(_T_1091, UInt<1>(0h0))
when _T_1092 :
node _T_1093 = eq(_T_1090, UInt<1>(0h0))
when _T_1093 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1090, UInt<1>(0h1), "") : assert_67
node _T_1094 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1095 = asUInt(reset)
node _T_1096 = eq(_T_1095, UInt<1>(0h0))
when _T_1096 :
node _T_1097 = eq(_T_1094, UInt<1>(0h0))
when _T_1097 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1094, UInt<1>(0h1), "") : assert_68
node _T_1098 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1099 = asUInt(reset)
node _T_1100 = eq(_T_1099, UInt<1>(0h0))
when _T_1100 :
node _T_1101 = eq(_T_1098, UInt<1>(0h0))
when _T_1101 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1098, UInt<1>(0h1), "") : assert_69
node _T_1102 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1103 = or(_T_1102, io.in.d.bits.corrupt)
node _T_1104 = asUInt(reset)
node _T_1105 = eq(_T_1104, UInt<1>(0h0))
when _T_1105 :
node _T_1106 = eq(_T_1103, UInt<1>(0h0))
when _T_1106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1103, UInt<1>(0h1), "") : assert_70
node _T_1107 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1108 = or(UInt<1>(0h0), _T_1107)
node _T_1109 = asUInt(reset)
node _T_1110 = eq(_T_1109, UInt<1>(0h0))
when _T_1110 :
node _T_1111 = eq(_T_1108, UInt<1>(0h0))
when _T_1111 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1108, UInt<1>(0h1), "") : assert_71
node _T_1112 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(source_ok_1, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1116 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1117 = asUInt(reset)
node _T_1118 = eq(_T_1117, UInt<1>(0h0))
when _T_1118 :
node _T_1119 = eq(_T_1116, UInt<1>(0h0))
when _T_1119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1116, UInt<1>(0h1), "") : assert_73
node _T_1120 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1121 = asUInt(reset)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
when _T_1122 :
node _T_1123 = eq(_T_1120, UInt<1>(0h0))
when _T_1123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1120, UInt<1>(0h1), "") : assert_74
node _T_1124 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1125 = or(UInt<1>(0h0), _T_1124)
node _T_1126 = asUInt(reset)
node _T_1127 = eq(_T_1126, UInt<1>(0h0))
when _T_1127 :
node _T_1128 = eq(_T_1125, UInt<1>(0h0))
when _T_1128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1125, UInt<1>(0h1), "") : assert_75
node _T_1129 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1129 :
node _T_1130 = asUInt(reset)
node _T_1131 = eq(_T_1130, UInt<1>(0h0))
when _T_1131 :
node _T_1132 = eq(source_ok_1, UInt<1>(0h0))
when _T_1132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1133 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1134 = asUInt(reset)
node _T_1135 = eq(_T_1134, UInt<1>(0h0))
when _T_1135 :
node _T_1136 = eq(_T_1133, UInt<1>(0h0))
when _T_1136 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1133, UInt<1>(0h1), "") : assert_77
node _T_1137 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1138 = or(_T_1137, io.in.d.bits.corrupt)
node _T_1139 = asUInt(reset)
node _T_1140 = eq(_T_1139, UInt<1>(0h0))
when _T_1140 :
node _T_1141 = eq(_T_1138, UInt<1>(0h0))
when _T_1141 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1138, UInt<1>(0h1), "") : assert_78
node _T_1142 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1143 = or(UInt<1>(0h0), _T_1142)
node _T_1144 = asUInt(reset)
node _T_1145 = eq(_T_1144, UInt<1>(0h0))
when _T_1145 :
node _T_1146 = eq(_T_1143, UInt<1>(0h0))
when _T_1146 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1143, UInt<1>(0h1), "") : assert_79
node _T_1147 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1147 :
node _T_1148 = asUInt(reset)
node _T_1149 = eq(_T_1148, UInt<1>(0h0))
when _T_1149 :
node _T_1150 = eq(source_ok_1, UInt<1>(0h0))
when _T_1150 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1151 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1152 = asUInt(reset)
node _T_1153 = eq(_T_1152, UInt<1>(0h0))
when _T_1153 :
node _T_1154 = eq(_T_1151, UInt<1>(0h0))
when _T_1154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1151, UInt<1>(0h1), "") : assert_81
node _T_1155 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1156 = asUInt(reset)
node _T_1157 = eq(_T_1156, UInt<1>(0h0))
when _T_1157 :
node _T_1158 = eq(_T_1155, UInt<1>(0h0))
when _T_1158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1155, UInt<1>(0h1), "") : assert_82
node _T_1159 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1160 = or(UInt<1>(0h0), _T_1159)
node _T_1161 = asUInt(reset)
node _T_1162 = eq(_T_1161, UInt<1>(0h0))
when _T_1162 :
node _T_1163 = eq(_T_1160, UInt<1>(0h0))
when _T_1163 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1160, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<26>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1164 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1165 = asUInt(reset)
node _T_1166 = eq(_T_1165, UInt<1>(0h0))
when _T_1166 :
node _T_1167 = eq(_T_1164, UInt<1>(0h0))
when _T_1167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1164, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<26>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1168 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1169 = asUInt(reset)
node _T_1170 = eq(_T_1169, UInt<1>(0h0))
when _T_1170 :
node _T_1171 = eq(_T_1168, UInt<1>(0h0))
when _T_1171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1168, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1172 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1173 = asUInt(reset)
node _T_1174 = eq(_T_1173, UInt<1>(0h0))
when _T_1174 :
node _T_1175 = eq(_T_1172, UInt<1>(0h0))
when _T_1175 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1172, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1176 = eq(a_first, UInt<1>(0h0))
node _T_1177 = and(io.in.a.valid, _T_1176)
when _T_1177 :
node _T_1178 = eq(io.in.a.bits.opcode, opcode)
node _T_1179 = asUInt(reset)
node _T_1180 = eq(_T_1179, UInt<1>(0h0))
when _T_1180 :
node _T_1181 = eq(_T_1178, UInt<1>(0h0))
when _T_1181 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1178, UInt<1>(0h1), "") : assert_87
node _T_1182 = eq(io.in.a.bits.param, param)
node _T_1183 = asUInt(reset)
node _T_1184 = eq(_T_1183, UInt<1>(0h0))
when _T_1184 :
node _T_1185 = eq(_T_1182, UInt<1>(0h0))
when _T_1185 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1182, UInt<1>(0h1), "") : assert_88
node _T_1186 = eq(io.in.a.bits.size, size)
node _T_1187 = asUInt(reset)
node _T_1188 = eq(_T_1187, UInt<1>(0h0))
when _T_1188 :
node _T_1189 = eq(_T_1186, UInt<1>(0h0))
when _T_1189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1186, UInt<1>(0h1), "") : assert_89
node _T_1190 = eq(io.in.a.bits.source, source)
node _T_1191 = asUInt(reset)
node _T_1192 = eq(_T_1191, UInt<1>(0h0))
when _T_1192 :
node _T_1193 = eq(_T_1190, UInt<1>(0h0))
when _T_1193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1190, UInt<1>(0h1), "") : assert_90
node _T_1194 = eq(io.in.a.bits.address, address)
node _T_1195 = asUInt(reset)
node _T_1196 = eq(_T_1195, UInt<1>(0h0))
when _T_1196 :
node _T_1197 = eq(_T_1194, UInt<1>(0h0))
when _T_1197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1194, UInt<1>(0h1), "") : assert_91
node _T_1198 = and(io.in.a.ready, io.in.a.valid)
node _T_1199 = and(_T_1198, a_first)
when _T_1199 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1200 = eq(d_first, UInt<1>(0h0))
node _T_1201 = and(io.in.d.valid, _T_1200)
when _T_1201 :
node _T_1202 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1203 = asUInt(reset)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
when _T_1204 :
node _T_1205 = eq(_T_1202, UInt<1>(0h0))
when _T_1205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1202, UInt<1>(0h1), "") : assert_92
node _T_1206 = eq(io.in.d.bits.param, param_1)
node _T_1207 = asUInt(reset)
node _T_1208 = eq(_T_1207, UInt<1>(0h0))
when _T_1208 :
node _T_1209 = eq(_T_1206, UInt<1>(0h0))
when _T_1209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1206, UInt<1>(0h1), "") : assert_93
node _T_1210 = eq(io.in.d.bits.size, size_1)
node _T_1211 = asUInt(reset)
node _T_1212 = eq(_T_1211, UInt<1>(0h0))
when _T_1212 :
node _T_1213 = eq(_T_1210, UInt<1>(0h0))
when _T_1213 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1210, UInt<1>(0h1), "") : assert_94
node _T_1214 = eq(io.in.d.bits.source, source_1)
node _T_1215 = asUInt(reset)
node _T_1216 = eq(_T_1215, UInt<1>(0h0))
when _T_1216 :
node _T_1217 = eq(_T_1214, UInt<1>(0h0))
when _T_1217 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1214, UInt<1>(0h1), "") : assert_95
node _T_1218 = eq(io.in.d.bits.sink, sink)
node _T_1219 = asUInt(reset)
node _T_1220 = eq(_T_1219, UInt<1>(0h0))
when _T_1220 :
node _T_1221 = eq(_T_1218, UInt<1>(0h0))
when _T_1221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1218, UInt<1>(0h1), "") : assert_96
node _T_1222 = eq(io.in.d.bits.denied, denied)
node _T_1223 = asUInt(reset)
node _T_1224 = eq(_T_1223, UInt<1>(0h0))
when _T_1224 :
node _T_1225 = eq(_T_1222, UInt<1>(0h0))
when _T_1225 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1222, UInt<1>(0h1), "") : assert_97
node _T_1226 = and(io.in.d.ready, io.in.d.valid)
node _T_1227 = and(_T_1226, d_first)
when _T_1227 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<260>
connect a_sizes_set, UInt<260>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1228 = and(io.in.a.valid, a_first_1)
node _T_1229 = and(_T_1228, UInt<1>(0h1))
when _T_1229 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1230 = and(io.in.a.ready, io.in.a.valid)
node _T_1231 = and(_T_1230, a_first_1)
node _T_1232 = and(_T_1231, UInt<1>(0h1))
when _T_1232 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1233 = dshr(inflight, io.in.a.bits.source)
node _T_1234 = bits(_T_1233, 0, 0)
node _T_1235 = eq(_T_1234, UInt<1>(0h0))
node _T_1236 = asUInt(reset)
node _T_1237 = eq(_T_1236, UInt<1>(0h0))
when _T_1237 :
node _T_1238 = eq(_T_1235, UInt<1>(0h0))
when _T_1238 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1235, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<260>
connect d_sizes_clr, UInt<260>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1239 = and(io.in.d.valid, d_first_1)
node _T_1240 = and(_T_1239, UInt<1>(0h1))
node _T_1241 = eq(d_release_ack, UInt<1>(0h0))
node _T_1242 = and(_T_1240, _T_1241)
when _T_1242 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1243 = and(io.in.d.ready, io.in.d.valid)
node _T_1244 = and(_T_1243, d_first_1)
node _T_1245 = and(_T_1244, UInt<1>(0h1))
node _T_1246 = eq(d_release_ack, UInt<1>(0h0))
node _T_1247 = and(_T_1245, _T_1246)
when _T_1247 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1248 = and(io.in.d.valid, d_first_1)
node _T_1249 = and(_T_1248, UInt<1>(0h1))
node _T_1250 = eq(d_release_ack, UInt<1>(0h0))
node _T_1251 = and(_T_1249, _T_1250)
when _T_1251 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1252 = dshr(inflight, io.in.d.bits.source)
node _T_1253 = bits(_T_1252, 0, 0)
node _T_1254 = or(_T_1253, same_cycle_resp)
node _T_1255 = asUInt(reset)
node _T_1256 = eq(_T_1255, UInt<1>(0h0))
when _T_1256 :
node _T_1257 = eq(_T_1254, UInt<1>(0h0))
when _T_1257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1254, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1258 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1259 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1260 = or(_T_1258, _T_1259)
node _T_1261 = asUInt(reset)
node _T_1262 = eq(_T_1261, UInt<1>(0h0))
when _T_1262 :
node _T_1263 = eq(_T_1260, UInt<1>(0h0))
when _T_1263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1260, UInt<1>(0h1), "") : assert_100
node _T_1264 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1265 = asUInt(reset)
node _T_1266 = eq(_T_1265, UInt<1>(0h0))
when _T_1266 :
node _T_1267 = eq(_T_1264, UInt<1>(0h0))
when _T_1267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1264, UInt<1>(0h1), "") : assert_101
else :
node _T_1268 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1269 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1270 = or(_T_1268, _T_1269)
node _T_1271 = asUInt(reset)
node _T_1272 = eq(_T_1271, UInt<1>(0h0))
when _T_1272 :
node _T_1273 = eq(_T_1270, UInt<1>(0h0))
when _T_1273 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1270, UInt<1>(0h1), "") : assert_102
node _T_1274 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1275 = asUInt(reset)
node _T_1276 = eq(_T_1275, UInt<1>(0h0))
when _T_1276 :
node _T_1277 = eq(_T_1274, UInt<1>(0h0))
when _T_1277 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1274, UInt<1>(0h1), "") : assert_103
node _T_1278 = and(io.in.d.valid, d_first_1)
node _T_1279 = and(_T_1278, a_first_1)
node _T_1280 = and(_T_1279, io.in.a.valid)
node _T_1281 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1282 = and(_T_1280, _T_1281)
node _T_1283 = eq(d_release_ack, UInt<1>(0h0))
node _T_1284 = and(_T_1282, _T_1283)
when _T_1284 :
node _T_1285 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1286 = or(_T_1285, io.in.a.ready)
node _T_1287 = asUInt(reset)
node _T_1288 = eq(_T_1287, UInt<1>(0h0))
when _T_1288 :
node _T_1289 = eq(_T_1286, UInt<1>(0h0))
when _T_1289 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1286, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_48
node _T_1290 = orr(inflight)
node _T_1291 = eq(_T_1290, UInt<1>(0h0))
node _T_1292 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1293 = or(_T_1291, _T_1292)
node _T_1294 = lt(watchdog, plusarg_reader.out)
node _T_1295 = or(_T_1293, _T_1294)
node _T_1296 = asUInt(reset)
node _T_1297 = eq(_T_1296, UInt<1>(0h0))
when _T_1297 :
node _T_1298 = eq(_T_1295, UInt<1>(0h0))
when _T_1298 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1295, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1299 = and(io.in.a.ready, io.in.a.valid)
node _T_1300 = and(io.in.d.ready, io.in.d.valid)
node _T_1301 = or(_T_1299, _T_1300)
when _T_1301 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<26>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<26>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<260>
connect c_sizes_set, UInt<260>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<26>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1302 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<26>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1303 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1304 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1305 = and(_T_1303, _T_1304)
node _T_1306 = and(_T_1302, _T_1305)
when _T_1306 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<26>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1307 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1308 = and(_T_1307, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<26>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1309 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1310 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1311 = and(_T_1309, _T_1310)
node _T_1312 = and(_T_1308, _T_1311)
when _T_1312 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<26>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1313 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1314 = bits(_T_1313, 0, 0)
node _T_1315 = eq(_T_1314, UInt<1>(0h0))
node _T_1316 = asUInt(reset)
node _T_1317 = eq(_T_1316, UInt<1>(0h0))
when _T_1317 :
node _T_1318 = eq(_T_1315, UInt<1>(0h0))
when _T_1318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1315, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<260>
connect d_sizes_clr_1, UInt<260>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1319 = and(io.in.d.valid, d_first_2)
node _T_1320 = and(_T_1319, UInt<1>(0h1))
node _T_1321 = and(_T_1320, d_release_ack_1)
when _T_1321 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1322 = and(io.in.d.ready, io.in.d.valid)
node _T_1323 = and(_T_1322, d_first_2)
node _T_1324 = and(_T_1323, UInt<1>(0h1))
node _T_1325 = and(_T_1324, d_release_ack_1)
when _T_1325 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1326 = and(io.in.d.valid, d_first_2)
node _T_1327 = and(_T_1326, UInt<1>(0h1))
node _T_1328 = and(_T_1327, d_release_ack_1)
when _T_1328 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1329 = dshr(inflight_1, io.in.d.bits.source)
node _T_1330 = bits(_T_1329, 0, 0)
node _T_1331 = or(_T_1330, same_cycle_resp_1)
node _T_1332 = asUInt(reset)
node _T_1333 = eq(_T_1332, UInt<1>(0h0))
when _T_1333 :
node _T_1334 = eq(_T_1331, UInt<1>(0h0))
when _T_1334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1331, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<26>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1335 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1336 = asUInt(reset)
node _T_1337 = eq(_T_1336, UInt<1>(0h0))
when _T_1337 :
node _T_1338 = eq(_T_1335, UInt<1>(0h0))
when _T_1338 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1335, UInt<1>(0h1), "") : assert_108
else :
node _T_1339 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1340 = asUInt(reset)
node _T_1341 = eq(_T_1340, UInt<1>(0h0))
when _T_1341 :
node _T_1342 = eq(_T_1339, UInt<1>(0h0))
when _T_1342 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1339, UInt<1>(0h1), "") : assert_109
node _T_1343 = and(io.in.d.valid, d_first_2)
node _T_1344 = and(_T_1343, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<26>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1345 = and(_T_1344, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<26>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1346 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1347 = and(_T_1345, _T_1346)
node _T_1348 = and(_T_1347, d_release_ack_1)
node _T_1349 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1350 = and(_T_1348, _T_1349)
when _T_1350 :
node _T_1351 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<26>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1352 = or(_T_1351, _WIRE_27.ready)
node _T_1353 = asUInt(reset)
node _T_1354 = eq(_T_1353, UInt<1>(0h0))
when _T_1354 :
node _T_1355 = eq(_T_1352, UInt<1>(0h0))
when _T_1355 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1352, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_49
node _T_1356 = orr(inflight_1)
node _T_1357 = eq(_T_1356, UInt<1>(0h0))
node _T_1358 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1359 = or(_T_1357, _T_1358)
node _T_1360 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1361 = or(_T_1359, _T_1360)
node _T_1362 = asUInt(reset)
node _T_1363 = eq(_T_1362, UInt<1>(0h0))
when _T_1363 :
node _T_1364 = eq(_T_1361, UInt<1>(0h0))
when _T_1364 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1361, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<26>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1365 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1366 = and(io.in.d.ready, io.in.d.valid)
node _T_1367 = or(_T_1365, _T_1366)
when _T_1367 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_24( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_33 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_26 = _source_ok_T_25 == 5'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_29 = source_ok_uncommonBits_4 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_34 = _source_ok_T_33 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_37 = source_ok_uncommonBits_5 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_38 = _source_ok_T_36 & _source_ok_T_37; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 7'h23; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire _source_ok_T_41 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_11 = _source_ok_T_41; // @[Parameters.scala:1138:31]
wire _source_ok_T_42 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_51 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [25:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_52 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_52; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_59 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_65 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_71 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_77 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_85 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_54 = _source_ok_T_53 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_58; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_60 = _source_ok_T_59 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_64; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_66 = _source_ok_T_65 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_70; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_72 = _source_ok_T_71 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_76; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_78 = _source_ok_T_77 == 5'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_81 = source_ok_uncommonBits_10 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_82 = _source_ok_T_80 & _source_ok_T_81; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_5 = _source_ok_T_82; // @[Parameters.scala:1138:31]
wire _source_ok_T_83 = io_in_d_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_83; // @[Parameters.scala:1138:31]
wire _source_ok_T_84 = io_in_d_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_84; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_86 = _source_ok_T_85 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_89 = source_ok_uncommonBits_11 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_90 = _source_ok_T_88 & _source_ok_T_89; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_8 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = io_in_d_bits_source_0 == 7'h23; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_91; // @[Parameters.scala:1138:31]
wire _source_ok_T_92 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_92; // @[Parameters.scala:1138:31]
wire _source_ok_T_93 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_11 = _source_ok_T_93; // @[Parameters.scala:1138:31]
wire _source_ok_T_94 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_100 = _source_ok_T_99 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_101 = _source_ok_T_100 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_102 = _source_ok_T_101 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_103 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1299 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1299; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1299; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [25:0] address; // @[Monitor.scala:391:22]
wire _T_1367 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1367; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1367; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1367; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1232 = _T_1299 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1232 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1232 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1232 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1232 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1232 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1278 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1278 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1247 = _T_1367 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1247 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1247 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1247 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1343 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1343 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1325 = _T_1367 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1325 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1325 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1325 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_52 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0)
node _source_ok_T = shr(io.in.a.bits.source, 4)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits = bits(_uncommonBits_T, 3, 0)
node _T_4 = shr(io.in.a.bits.source, 4)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<4>(0h9))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0)
node _T_24 = shr(io.in.a.bits.source, 4)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<4>(0h9))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0)
node _T_86 = shr(io.in.a.bits.source, 4)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<4>(0h9))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0)
node _T_152 = shr(io.in.a.bits.source, 4)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<4>(0h9))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0)
node _T_199 = shr(io.in.a.bits.source, 4)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<4>(0h9))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0)
node _T_240 = shr(io.in.a.bits.source, 4)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<4>(0h9))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0)
node _T_283 = shr(io.in.a.bits.source, 4)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<4>(0h9))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0)
node _T_321 = shr(io.in.a.bits.source, 4)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<4>(0h9))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0)
node _T_359 = shr(io.in.a.bits.source, 4)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<4>(0h9))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 4)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<28>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<28>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<10>
connect a_set, UInt<10>(0h0)
wire a_set_wo_ready : UInt<10>
connect a_set_wo_ready, UInt<10>(0h0)
wire a_opcodes_set : UInt<40>
connect a_opcodes_set, UInt<40>(0h0)
wire a_sizes_set : UInt<40>
connect a_sizes_set, UInt<40>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<10>
connect d_clr, UInt<10>(0h0)
wire d_clr_wo_ready : UInt<10>
connect d_clr_wo_ready, UInt<10>(0h0)
wire d_opcodes_clr : UInt<40>
connect d_opcodes_clr, UInt<40>(0h0)
wire d_sizes_clr : UInt<40>
connect d_sizes_clr, UInt<40>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_657 = orr(a_set_wo_ready)
node _T_658 = eq(_T_657, UInt<1>(0h0))
node _T_659 = or(_T_656, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_659, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_105
node _T_663 = orr(inflight)
node _T_664 = eq(_T_663, UInt<1>(0h0))
node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_666 = or(_T_664, _T_665)
node _T_667 = lt(watchdog, plusarg_reader.out)
node _T_668 = or(_T_666, _T_667)
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(_T_668, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_668, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_672 = and(io.in.a.ready, io.in.a.valid)
node _T_673 = and(io.in.d.ready, io.in.d.valid)
node _T_674 = or(_T_672, _T_673)
when _T_674 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<28>(0h0)
connect _c_first_WIRE.bits.source, UInt<4>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<10>
connect c_set, UInt<10>(0h0)
wire c_set_wo_ready : UInt<10>
connect c_set_wo_ready, UInt<10>(0h0)
wire c_opcodes_set : UInt<40>
connect c_opcodes_set, UInt<40>(0h0)
wire c_sizes_set : UInt<40>
connect c_sizes_set, UInt<40>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<28>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_675 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<28>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_678 = and(_T_676, _T_677)
node _T_679 = and(_T_675, _T_678)
when _T_679 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<28>(0h0)
connect _WIRE_10.bits.source, UInt<4>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_681 = and(_T_680, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<28>(0h0)
connect _WIRE_12.bits.source, UInt<4>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_684 = and(_T_682, _T_683)
node _T_685 = and(_T_681, _T_684)
when _T_685 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<28>(0h0)
connect _WIRE_14.bits.source, UInt<4>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_686 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_687 = bits(_T_686, 0, 0)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_688, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<10>
connect d_clr_1, UInt<10>(0h0)
wire d_clr_wo_ready_1 : UInt<10>
connect d_clr_wo_ready_1, UInt<10>(0h0)
wire d_opcodes_clr_1 : UInt<40>
connect d_opcodes_clr_1, UInt<40>(0h0)
wire d_sizes_clr_1 : UInt<40>
connect d_sizes_clr_1, UInt<40>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_695 = and(io.in.d.ready, io.in.d.valid)
node _T_696 = and(_T_695, d_first_2)
node _T_697 = and(_T_696, UInt<1>(0h1))
node _T_698 = and(_T_697, d_release_ack_1)
when _T_698 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_699 = and(io.in.d.valid, d_first_2)
node _T_700 = and(_T_699, UInt<1>(0h1))
node _T_701 = and(_T_700, d_release_ack_1)
when _T_701 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_702 = dshr(inflight_1, io.in.d.bits.source)
node _T_703 = bits(_T_702, 0, 0)
node _T_704 = or(_T_703, same_cycle_resp_1)
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_704, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<28>(0h0)
connect _WIRE_16.bits.source, UInt<4>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_709 = asUInt(reset)
node _T_710 = eq(_T_709, UInt<1>(0h0))
when _T_710 :
node _T_711 = eq(_T_708, UInt<1>(0h0))
when _T_711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_708, UInt<1>(0h1), "") : assert_109
else :
node _T_712 = eq(io.in.d.bits.size, c_size_lookup)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _T_716 = and(io.in.d.valid, d_first_2)
node _T_717 = and(_T_716, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<28>(0h0)
connect _WIRE_18.bits.source, UInt<4>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_718 = and(_T_717, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<28>(0h0)
connect _WIRE_20.bits.source, UInt<4>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_720 = and(_T_718, _T_719)
node _T_721 = and(_T_720, d_release_ack_1)
node _T_722 = eq(c_probe_ack, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
when _T_723 :
node _T_724 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<28>(0h0)
connect _WIRE_22.bits.source, UInt<4>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_725 = or(_T_724, _WIRE_23.ready)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_725, UInt<1>(0h1), "") : assert_111
node _T_729 = orr(c_set_wo_ready)
when _T_729 :
node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_730, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_106
node _T_734 = orr(inflight_1)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_737 = or(_T_735, _T_736)
node _T_738 = lt(watchdog_1, plusarg_reader_1.out)
node _T_739 = or(_T_737, _T_738)
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_739, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<28>(0h0)
connect _WIRE_24.bits.source, UInt<4>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_744 = and(io.in.d.ready, io.in.d.valid)
node _T_745 = or(_T_743, _T_744)
when _T_745 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_52( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg [9:0] inflight; // @[Monitor.scala:614:27]
reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [39:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [15:0] _GEN_0 = {12'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [15:0] _GEN_3 = {12'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [9:0] inflight_1; // @[Monitor.scala:726:35]
reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_59 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 2, 0)
node _source_ok_T = shr(io.in.a.bits.source, 3)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<3>(0h4))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits = bits(_uncommonBits_T, 2, 0)
node _T_4 = shr(io.in.a.bits.source, 3)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<3>(0h4))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 2, 0)
node _T_24 = shr(io.in.a.bits.source, 3)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<3>(0h4))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_33 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_34 = and(_T_32, _T_33)
node _T_35 = or(UInt<1>(0h0), _T_34)
node _T_36 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_37 = cvt(_T_36)
node _T_38 = and(_T_37, asSInt(UInt<17>(0h100c0)))
node _T_39 = asSInt(_T_38)
node _T_40 = eq(_T_39, asSInt(UInt<1>(0h0)))
node _T_41 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_42 = cvt(_T_41)
node _T_43 = and(_T_42, asSInt(UInt<29>(0h100000c0)))
node _T_44 = asSInt(_T_43)
node _T_45 = eq(_T_44, asSInt(UInt<1>(0h0)))
node _T_46 = or(_T_40, _T_45)
node _T_47 = and(_T_35, _T_46)
node _T_48 = or(UInt<1>(0h0), _T_47)
node _T_49 = and(_T_31, _T_48)
node _T_50 = asUInt(reset)
node _T_51 = eq(_T_50, UInt<1>(0h0))
when _T_51 :
node _T_52 = eq(_T_49, UInt<1>(0h0))
when _T_52 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_49, UInt<1>(0h1), "") : assert_2
node _T_53 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_54 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_55 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_56 = and(_T_54, _T_55)
node _T_57 = or(UInt<1>(0h0), _T_56)
node _T_58 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<17>(0h100c0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_64 = cvt(_T_63)
node _T_65 = and(_T_64, asSInt(UInt<29>(0h100000c0)))
node _T_66 = asSInt(_T_65)
node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0)))
node _T_68 = or(_T_62, _T_67)
node _T_69 = and(_T_57, _T_68)
node _T_70 = or(UInt<1>(0h0), _T_69)
node _T_71 = and(_T_53, _T_70)
node _T_72 = asUInt(reset)
node _T_73 = eq(_T_72, UInt<1>(0h0))
when _T_73 :
node _T_74 = eq(_T_71, UInt<1>(0h0))
when _T_74 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_71, UInt<1>(0h1), "") : assert_3
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_78 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_78, UInt<1>(0h1), "") : assert_5
node _T_82 = asUInt(reset)
node _T_83 = eq(_T_82, UInt<1>(0h0))
when _T_83 :
node _T_84 = eq(is_aligned, UInt<1>(0h0))
when _T_84 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_85 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_86 = asUInt(reset)
node _T_87 = eq(_T_86, UInt<1>(0h0))
when _T_87 :
node _T_88 = eq(_T_85, UInt<1>(0h0))
when _T_88 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_85, UInt<1>(0h1), "") : assert_7
node _T_89 = not(io.in.a.bits.mask)
node _T_90 = eq(_T_89, UInt<1>(0h0))
node _T_91 = asUInt(reset)
node _T_92 = eq(_T_91, UInt<1>(0h0))
when _T_92 :
node _T_93 = eq(_T_90, UInt<1>(0h0))
when _T_93 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_90, UInt<1>(0h1), "") : assert_8
node _T_94 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_95 = asUInt(reset)
node _T_96 = eq(_T_95, UInt<1>(0h0))
when _T_96 :
node _T_97 = eq(_T_94, UInt<1>(0h0))
when _T_97 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_94, UInt<1>(0h1), "") : assert_9
node _T_98 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_98 :
node _T_99 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_100 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_101 = and(_T_99, _T_100)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 2, 0)
node _T_102 = shr(io.in.a.bits.source, 3)
node _T_103 = eq(_T_102, UInt<1>(0h0))
node _T_104 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_105 = and(_T_103, _T_104)
node _T_106 = leq(uncommonBits_2, UInt<3>(0h4))
node _T_107 = and(_T_105, _T_106)
node _T_108 = and(_T_101, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_111 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_112 = and(_T_110, _T_111)
node _T_113 = or(UInt<1>(0h0), _T_112)
node _T_114 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_115 = cvt(_T_114)
node _T_116 = and(_T_115, asSInt(UInt<17>(0h100c0)))
node _T_117 = asSInt(_T_116)
node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_120 = cvt(_T_119)
node _T_121 = and(_T_120, asSInt(UInt<29>(0h100000c0)))
node _T_122 = asSInt(_T_121)
node _T_123 = eq(_T_122, asSInt(UInt<1>(0h0)))
node _T_124 = or(_T_118, _T_123)
node _T_125 = and(_T_113, _T_124)
node _T_126 = or(UInt<1>(0h0), _T_125)
node _T_127 = and(_T_109, _T_126)
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(_T_127, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_127, UInt<1>(0h1), "") : assert_10
node _T_131 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_132 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_133 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_134 = and(_T_132, _T_133)
node _T_135 = or(UInt<1>(0h0), _T_134)
node _T_136 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_137 = cvt(_T_136)
node _T_138 = and(_T_137, asSInt(UInt<17>(0h100c0)))
node _T_139 = asSInt(_T_138)
node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_142 = cvt(_T_141)
node _T_143 = and(_T_142, asSInt(UInt<29>(0h100000c0)))
node _T_144 = asSInt(_T_143)
node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0)))
node _T_146 = or(_T_140, _T_145)
node _T_147 = and(_T_135, _T_146)
node _T_148 = or(UInt<1>(0h0), _T_147)
node _T_149 = and(_T_131, _T_148)
node _T_150 = asUInt(reset)
node _T_151 = eq(_T_150, UInt<1>(0h0))
when _T_151 :
node _T_152 = eq(_T_149, UInt<1>(0h0))
when _T_152 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_149, UInt<1>(0h1), "") : assert_11
node _T_153 = asUInt(reset)
node _T_154 = eq(_T_153, UInt<1>(0h0))
when _T_154 :
node _T_155 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_155 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_156 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_157 = asUInt(reset)
node _T_158 = eq(_T_157, UInt<1>(0h0))
when _T_158 :
node _T_159 = eq(_T_156, UInt<1>(0h0))
when _T_159 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_156, UInt<1>(0h1), "") : assert_13
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(is_aligned, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_163 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_164 = asUInt(reset)
node _T_165 = eq(_T_164, UInt<1>(0h0))
when _T_165 :
node _T_166 = eq(_T_163, UInt<1>(0h0))
when _T_166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_163, UInt<1>(0h1), "") : assert_15
node _T_167 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_168 = asUInt(reset)
node _T_169 = eq(_T_168, UInt<1>(0h0))
when _T_169 :
node _T_170 = eq(_T_167, UInt<1>(0h0))
when _T_170 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_167, UInt<1>(0h1), "") : assert_16
node _T_171 = not(io.in.a.bits.mask)
node _T_172 = eq(_T_171, UInt<1>(0h0))
node _T_173 = asUInt(reset)
node _T_174 = eq(_T_173, UInt<1>(0h0))
when _T_174 :
node _T_175 = eq(_T_172, UInt<1>(0h0))
when _T_175 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_172, UInt<1>(0h1), "") : assert_17
node _T_176 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_176, UInt<1>(0h1), "") : assert_18
node _T_180 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_180 :
node _T_181 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_182 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_183 = and(_T_181, _T_182)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 2, 0)
node _T_184 = shr(io.in.a.bits.source, 3)
node _T_185 = eq(_T_184, UInt<1>(0h0))
node _T_186 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_187 = and(_T_185, _T_186)
node _T_188 = leq(uncommonBits_3, UInt<3>(0h4))
node _T_189 = and(_T_187, _T_188)
node _T_190 = and(_T_183, _T_189)
node _T_191 = or(UInt<1>(0h0), _T_190)
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_191, UInt<1>(0h1), "") : assert_19
node _T_195 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_196 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_197 = and(_T_195, _T_196)
node _T_198 = or(UInt<1>(0h0), _T_197)
node _T_199 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_200 = cvt(_T_199)
node _T_201 = and(_T_200, asSInt(UInt<17>(0h100c0)))
node _T_202 = asSInt(_T_201)
node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0)))
node _T_204 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_205 = cvt(_T_204)
node _T_206 = and(_T_205, asSInt(UInt<29>(0h100000c0)))
node _T_207 = asSInt(_T_206)
node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0)))
node _T_209 = or(_T_203, _T_208)
node _T_210 = and(_T_198, _T_209)
node _T_211 = or(UInt<1>(0h0), _T_210)
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_211, UInt<1>(0h1), "") : assert_20
node _T_215 = asUInt(reset)
node _T_216 = eq(_T_215, UInt<1>(0h0))
when _T_216 :
node _T_217 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_217 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_218 = asUInt(reset)
node _T_219 = eq(_T_218, UInt<1>(0h0))
when _T_219 :
node _T_220 = eq(is_aligned, UInt<1>(0h0))
when _T_220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_221 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_T_221, UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_221, UInt<1>(0h1), "") : assert_23
node _T_225 = eq(io.in.a.bits.mask, mask)
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_225, UInt<1>(0h1), "") : assert_24
node _T_229 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_230 = asUInt(reset)
node _T_231 = eq(_T_230, UInt<1>(0h0))
when _T_231 :
node _T_232 = eq(_T_229, UInt<1>(0h0))
when _T_232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_229, UInt<1>(0h1), "") : assert_25
node _T_233 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_233 :
node _T_234 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_235 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_236 = and(_T_234, _T_235)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0)
node _T_237 = shr(io.in.a.bits.source, 3)
node _T_238 = eq(_T_237, UInt<1>(0h0))
node _T_239 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_240 = and(_T_238, _T_239)
node _T_241 = leq(uncommonBits_4, UInt<3>(0h4))
node _T_242 = and(_T_240, _T_241)
node _T_243 = and(_T_236, _T_242)
node _T_244 = or(UInt<1>(0h0), _T_243)
node _T_245 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_246 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_247 = and(_T_245, _T_246)
node _T_248 = or(UInt<1>(0h0), _T_247)
node _T_249 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_250 = cvt(_T_249)
node _T_251 = and(_T_250, asSInt(UInt<17>(0h100c0)))
node _T_252 = asSInt(_T_251)
node _T_253 = eq(_T_252, asSInt(UInt<1>(0h0)))
node _T_254 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_255 = cvt(_T_254)
node _T_256 = and(_T_255, asSInt(UInt<29>(0h100000c0)))
node _T_257 = asSInt(_T_256)
node _T_258 = eq(_T_257, asSInt(UInt<1>(0h0)))
node _T_259 = or(_T_253, _T_258)
node _T_260 = and(_T_248, _T_259)
node _T_261 = or(UInt<1>(0h0), _T_260)
node _T_262 = and(_T_244, _T_261)
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_T_262, UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_262, UInt<1>(0h1), "") : assert_26
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_269 = asUInt(reset)
node _T_270 = eq(_T_269, UInt<1>(0h0))
when _T_270 :
node _T_271 = eq(is_aligned, UInt<1>(0h0))
when _T_271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_272 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_273 = asUInt(reset)
node _T_274 = eq(_T_273, UInt<1>(0h0))
when _T_274 :
node _T_275 = eq(_T_272, UInt<1>(0h0))
when _T_275 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_272, UInt<1>(0h1), "") : assert_29
node _T_276 = eq(io.in.a.bits.mask, mask)
node _T_277 = asUInt(reset)
node _T_278 = eq(_T_277, UInt<1>(0h0))
when _T_278 :
node _T_279 = eq(_T_276, UInt<1>(0h0))
when _T_279 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_276, UInt<1>(0h1), "") : assert_30
node _T_280 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_280 :
node _T_281 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_282 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_283 = and(_T_281, _T_282)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0)
node _T_284 = shr(io.in.a.bits.source, 3)
node _T_285 = eq(_T_284, UInt<1>(0h0))
node _T_286 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_287 = and(_T_285, _T_286)
node _T_288 = leq(uncommonBits_5, UInt<3>(0h4))
node _T_289 = and(_T_287, _T_288)
node _T_290 = and(_T_283, _T_289)
node _T_291 = or(UInt<1>(0h0), _T_290)
node _T_292 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_293 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_294 = and(_T_292, _T_293)
node _T_295 = or(UInt<1>(0h0), _T_294)
node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_297 = cvt(_T_296)
node _T_298 = and(_T_297, asSInt(UInt<17>(0h100c0)))
node _T_299 = asSInt(_T_298)
node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0)))
node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_302 = cvt(_T_301)
node _T_303 = and(_T_302, asSInt(UInt<29>(0h100000c0)))
node _T_304 = asSInt(_T_303)
node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0)))
node _T_306 = or(_T_300, _T_305)
node _T_307 = and(_T_295, _T_306)
node _T_308 = or(UInt<1>(0h0), _T_307)
node _T_309 = and(_T_291, _T_308)
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_309, UInt<1>(0h1), "") : assert_31
node _T_313 = asUInt(reset)
node _T_314 = eq(_T_313, UInt<1>(0h0))
when _T_314 :
node _T_315 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_315 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_316 = asUInt(reset)
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(is_aligned, UInt<1>(0h0))
when _T_318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_319 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_320 = asUInt(reset)
node _T_321 = eq(_T_320, UInt<1>(0h0))
when _T_321 :
node _T_322 = eq(_T_319, UInt<1>(0h0))
when _T_322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_319, UInt<1>(0h1), "") : assert_34
node _T_323 = not(mask)
node _T_324 = and(io.in.a.bits.mask, _T_323)
node _T_325 = eq(_T_324, UInt<1>(0h0))
node _T_326 = asUInt(reset)
node _T_327 = eq(_T_326, UInt<1>(0h0))
when _T_327 :
node _T_328 = eq(_T_325, UInt<1>(0h0))
when _T_328 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_325, UInt<1>(0h1), "") : assert_35
node _T_329 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_329 :
node _T_330 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_331 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_332 = and(_T_330, _T_331)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0)
node _T_333 = shr(io.in.a.bits.source, 3)
node _T_334 = eq(_T_333, UInt<1>(0h0))
node _T_335 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_336 = and(_T_334, _T_335)
node _T_337 = leq(uncommonBits_6, UInt<3>(0h4))
node _T_338 = and(_T_336, _T_337)
node _T_339 = and(_T_332, _T_338)
node _T_340 = or(UInt<1>(0h0), _T_339)
node _T_341 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_342 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_343 = cvt(_T_342)
node _T_344 = and(_T_343, asSInt(UInt<17>(0h100c0)))
node _T_345 = asSInt(_T_344)
node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0)))
node _T_347 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_348 = cvt(_T_347)
node _T_349 = and(_T_348, asSInt(UInt<29>(0h100000c0)))
node _T_350 = asSInt(_T_349)
node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0)))
node _T_352 = or(_T_346, _T_351)
node _T_353 = and(_T_341, _T_352)
node _T_354 = or(UInt<1>(0h0), _T_353)
node _T_355 = and(_T_340, _T_354)
node _T_356 = asUInt(reset)
node _T_357 = eq(_T_356, UInt<1>(0h0))
when _T_357 :
node _T_358 = eq(_T_355, UInt<1>(0h0))
when _T_358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_355, UInt<1>(0h1), "") : assert_36
node _T_359 = asUInt(reset)
node _T_360 = eq(_T_359, UInt<1>(0h0))
when _T_360 :
node _T_361 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(is_aligned, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_365 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_366 = asUInt(reset)
node _T_367 = eq(_T_366, UInt<1>(0h0))
when _T_367 :
node _T_368 = eq(_T_365, UInt<1>(0h0))
when _T_368 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_365, UInt<1>(0h1), "") : assert_39
node _T_369 = eq(io.in.a.bits.mask, mask)
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(_T_369, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_369, UInt<1>(0h1), "") : assert_40
node _T_373 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_373 :
node _T_374 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_375 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_376 = and(_T_374, _T_375)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 2, 0)
node _T_377 = shr(io.in.a.bits.source, 3)
node _T_378 = eq(_T_377, UInt<1>(0h0))
node _T_379 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_380 = and(_T_378, _T_379)
node _T_381 = leq(uncommonBits_7, UInt<3>(0h4))
node _T_382 = and(_T_380, _T_381)
node _T_383 = and(_T_376, _T_382)
node _T_384 = or(UInt<1>(0h0), _T_383)
node _T_385 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_386 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_387 = cvt(_T_386)
node _T_388 = and(_T_387, asSInt(UInt<17>(0h100c0)))
node _T_389 = asSInt(_T_388)
node _T_390 = eq(_T_389, asSInt(UInt<1>(0h0)))
node _T_391 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_392 = cvt(_T_391)
node _T_393 = and(_T_392, asSInt(UInt<29>(0h100000c0)))
node _T_394 = asSInt(_T_393)
node _T_395 = eq(_T_394, asSInt(UInt<1>(0h0)))
node _T_396 = or(_T_390, _T_395)
node _T_397 = and(_T_385, _T_396)
node _T_398 = or(UInt<1>(0h0), _T_397)
node _T_399 = and(_T_384, _T_398)
node _T_400 = asUInt(reset)
node _T_401 = eq(_T_400, UInt<1>(0h0))
when _T_401 :
node _T_402 = eq(_T_399, UInt<1>(0h0))
when _T_402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_399, UInt<1>(0h1), "") : assert_41
node _T_403 = asUInt(reset)
node _T_404 = eq(_T_403, UInt<1>(0h0))
when _T_404 :
node _T_405 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(is_aligned, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_409 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_409, UInt<1>(0h1), "") : assert_44
node _T_413 = eq(io.in.a.bits.mask, mask)
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_413, UInt<1>(0h1), "") : assert_45
node _T_417 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_417 :
node _T_418 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_419 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_420 = and(_T_418, _T_419)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 2, 0)
node _T_421 = shr(io.in.a.bits.source, 3)
node _T_422 = eq(_T_421, UInt<1>(0h0))
node _T_423 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_424 = and(_T_422, _T_423)
node _T_425 = leq(uncommonBits_8, UInt<3>(0h4))
node _T_426 = and(_T_424, _T_425)
node _T_427 = and(_T_420, _T_426)
node _T_428 = or(UInt<1>(0h0), _T_427)
node _T_429 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_430 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_431 = cvt(_T_430)
node _T_432 = and(_T_431, asSInt(UInt<17>(0h100c0)))
node _T_433 = asSInt(_T_432)
node _T_434 = eq(_T_433, asSInt(UInt<1>(0h0)))
node _T_435 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_436 = cvt(_T_435)
node _T_437 = and(_T_436, asSInt(UInt<29>(0h100000c0)))
node _T_438 = asSInt(_T_437)
node _T_439 = eq(_T_438, asSInt(UInt<1>(0h0)))
node _T_440 = or(_T_434, _T_439)
node _T_441 = and(_T_429, _T_440)
node _T_442 = or(UInt<1>(0h0), _T_441)
node _T_443 = and(_T_428, _T_442)
node _T_444 = asUInt(reset)
node _T_445 = eq(_T_444, UInt<1>(0h0))
when _T_445 :
node _T_446 = eq(_T_443, UInt<1>(0h0))
when _T_446 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_443, UInt<1>(0h1), "") : assert_46
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(is_aligned, UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_453 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_454 = asUInt(reset)
node _T_455 = eq(_T_454, UInt<1>(0h0))
when _T_455 :
node _T_456 = eq(_T_453, UInt<1>(0h0))
when _T_456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_453, UInt<1>(0h1), "") : assert_49
node _T_457 = eq(io.in.a.bits.mask, mask)
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_T_457, UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_457, UInt<1>(0h1), "") : assert_50
node _T_461 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_462 = asUInt(reset)
node _T_463 = eq(_T_462, UInt<1>(0h0))
when _T_463 :
node _T_464 = eq(_T_461, UInt<1>(0h0))
when _T_464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_461, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_465 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_466 = asUInt(reset)
node _T_467 = eq(_T_466, UInt<1>(0h0))
when _T_467 :
node _T_468 = eq(_T_465, UInt<1>(0h0))
when _T_468 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_465, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 2, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 3)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<3>(0h4))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_469 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_469 :
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_473 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_474 = asUInt(reset)
node _T_475 = eq(_T_474, UInt<1>(0h0))
when _T_475 :
node _T_476 = eq(_T_473, UInt<1>(0h0))
when _T_476 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_473, UInt<1>(0h1), "") : assert_54
node _T_477 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_477, UInt<1>(0h1), "") : assert_55
node _T_481 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_481, UInt<1>(0h1), "") : assert_56
node _T_485 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_486 = asUInt(reset)
node _T_487 = eq(_T_486, UInt<1>(0h0))
when _T_487 :
node _T_488 = eq(_T_485, UInt<1>(0h0))
when _T_488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_485, UInt<1>(0h1), "") : assert_57
node _T_489 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_489 :
node _T_490 = asUInt(reset)
node _T_491 = eq(_T_490, UInt<1>(0h0))
when _T_491 :
node _T_492 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_492 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(sink_ok, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_496 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_497 = asUInt(reset)
node _T_498 = eq(_T_497, UInt<1>(0h0))
when _T_498 :
node _T_499 = eq(_T_496, UInt<1>(0h0))
when _T_499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_496, UInt<1>(0h1), "") : assert_60
node _T_500 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_501 = asUInt(reset)
node _T_502 = eq(_T_501, UInt<1>(0h0))
when _T_502 :
node _T_503 = eq(_T_500, UInt<1>(0h0))
when _T_503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_500, UInt<1>(0h1), "") : assert_61
node _T_504 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_504, UInt<1>(0h1), "") : assert_62
node _T_508 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_509 = asUInt(reset)
node _T_510 = eq(_T_509, UInt<1>(0h0))
when _T_510 :
node _T_511 = eq(_T_508, UInt<1>(0h0))
when _T_511 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_508, UInt<1>(0h1), "") : assert_63
node _T_512 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_513 = or(UInt<1>(0h1), _T_512)
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_T_513, UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_513, UInt<1>(0h1), "") : assert_64
node _T_517 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_517 :
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_521 = asUInt(reset)
node _T_522 = eq(_T_521, UInt<1>(0h0))
when _T_522 :
node _T_523 = eq(sink_ok, UInt<1>(0h0))
when _T_523 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_524 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_525 = asUInt(reset)
node _T_526 = eq(_T_525, UInt<1>(0h0))
when _T_526 :
node _T_527 = eq(_T_524, UInt<1>(0h0))
when _T_527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_524, UInt<1>(0h1), "") : assert_67
node _T_528 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_529 = asUInt(reset)
node _T_530 = eq(_T_529, UInt<1>(0h0))
when _T_530 :
node _T_531 = eq(_T_528, UInt<1>(0h0))
when _T_531 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_528, UInt<1>(0h1), "") : assert_68
node _T_532 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_533 = asUInt(reset)
node _T_534 = eq(_T_533, UInt<1>(0h0))
when _T_534 :
node _T_535 = eq(_T_532, UInt<1>(0h0))
when _T_535 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_532, UInt<1>(0h1), "") : assert_69
node _T_536 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_537 = or(_T_536, io.in.d.bits.corrupt)
node _T_538 = asUInt(reset)
node _T_539 = eq(_T_538, UInt<1>(0h0))
when _T_539 :
node _T_540 = eq(_T_537, UInt<1>(0h0))
when _T_540 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_537, UInt<1>(0h1), "") : assert_70
node _T_541 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_542 = or(UInt<1>(0h1), _T_541)
node _T_543 = asUInt(reset)
node _T_544 = eq(_T_543, UInt<1>(0h0))
when _T_544 :
node _T_545 = eq(_T_542, UInt<1>(0h0))
when _T_545 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_542, UInt<1>(0h1), "") : assert_71
node _T_546 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_546 :
node _T_547 = asUInt(reset)
node _T_548 = eq(_T_547, UInt<1>(0h0))
when _T_548 :
node _T_549 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_550 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_551 = asUInt(reset)
node _T_552 = eq(_T_551, UInt<1>(0h0))
when _T_552 :
node _T_553 = eq(_T_550, UInt<1>(0h0))
when _T_553 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_550, UInt<1>(0h1), "") : assert_73
node _T_554 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_555 = asUInt(reset)
node _T_556 = eq(_T_555, UInt<1>(0h0))
when _T_556 :
node _T_557 = eq(_T_554, UInt<1>(0h0))
when _T_557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_554, UInt<1>(0h1), "") : assert_74
node _T_558 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_559 = or(UInt<1>(0h1), _T_558)
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_559, UInt<1>(0h1), "") : assert_75
node _T_563 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_563 :
node _T_564 = asUInt(reset)
node _T_565 = eq(_T_564, UInt<1>(0h0))
when _T_565 :
node _T_566 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_567 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_568 = asUInt(reset)
node _T_569 = eq(_T_568, UInt<1>(0h0))
when _T_569 :
node _T_570 = eq(_T_567, UInt<1>(0h0))
when _T_570 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_567, UInt<1>(0h1), "") : assert_77
node _T_571 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_572 = or(_T_571, io.in.d.bits.corrupt)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_572, UInt<1>(0h1), "") : assert_78
node _T_576 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_577 = or(UInt<1>(0h1), _T_576)
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(_T_577, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_577, UInt<1>(0h1), "") : assert_79
node _T_581 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_581 :
node _T_582 = asUInt(reset)
node _T_583 = eq(_T_582, UInt<1>(0h0))
when _T_583 :
node _T_584 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_585 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_586 = asUInt(reset)
node _T_587 = eq(_T_586, UInt<1>(0h0))
when _T_587 :
node _T_588 = eq(_T_585, UInt<1>(0h0))
when _T_588 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_585, UInt<1>(0h1), "") : assert_81
node _T_589 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_590 = asUInt(reset)
node _T_591 = eq(_T_590, UInt<1>(0h0))
when _T_591 :
node _T_592 = eq(_T_589, UInt<1>(0h0))
when _T_592 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_589, UInt<1>(0h1), "") : assert_82
node _T_593 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_594 = or(UInt<1>(0h1), _T_593)
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_594, UInt<1>(0h1), "") : assert_83
when io.in.b.valid :
node _T_598 = leq(io.in.b.bits.opcode, UInt<3>(0h6))
node _T_599 = asUInt(reset)
node _T_600 = eq(_T_599, UInt<1>(0h0))
when _T_600 :
node _T_601 = eq(_T_598, UInt<1>(0h0))
when _T_601 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_598, UInt<1>(0h1), "") : assert_84
node _uncommonBits_T_9 = or(io.in.b.bits.source, UInt<3>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0)
node _T_602 = shr(io.in.b.bits.source, 3)
node _T_603 = eq(_T_602, UInt<1>(0h0))
node _T_604 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_605 = and(_T_603, _T_604)
node _T_606 = leq(uncommonBits_9, UInt<3>(0h4))
node _T_607 = and(_T_605, _T_606)
node _T_608 = eq(_T_607, UInt<1>(0h0))
node _T_609 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_610 = cvt(_T_609)
node _T_611 = and(_T_610, asSInt(UInt<1>(0h0)))
node _T_612 = asSInt(_T_611)
node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0)))
node _T_614 = or(_T_608, _T_613)
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(_T_614, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_614, UInt<1>(0h1), "") : assert_85
node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000040))
node _address_ok_T_1 = cvt(_address_ok_T)
node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h100c0)))
node _address_ok_T_3 = asSInt(_address_ok_T_2)
node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0)))
node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000040))
node _address_ok_T_6 = cvt(_address_ok_T_5)
node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h100000c0)))
node _address_ok_T_8 = asSInt(_address_ok_T_7)
node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE : UInt<1>[2]
connect _address_ok_WIRE[0], _address_ok_T_4
connect _address_ok_WIRE[1], _address_ok_T_9
node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1])
node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size)
node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0)
node is_aligned_mask_1 = not(_is_aligned_mask_T_3)
node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1)
node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0))
node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0)
node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1)
node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0)
node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1))
node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3))
node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2)
node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2)
node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1)
node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1)
node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1)
node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1)
node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0))
node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1)
node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4)
node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1)
node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5)
node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1)
node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6)
node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1)
node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7)
node mask_size_1 = bits(mask_sizeOH_1, 0, 0)
node mask_bit_1 = bits(io.in.b.bits.address, 0, 0)
node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0))
node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1)
node _mask_acc_T_8 = and(mask_size_1, mask_eq_8)
node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1)
node _mask_acc_T_9 = and(mask_size_1, mask_eq_9)
node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1)
node _mask_acc_T_10 = and(mask_size_1, mask_eq_10)
node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1)
node _mask_acc_T_11 = and(mask_size_1, mask_eq_11)
node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1)
node _mask_acc_T_12 = and(mask_size_1, mask_eq_12)
node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1)
node _mask_acc_T_13 = and(mask_size_1, mask_eq_13)
node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1)
node _mask_acc_T_14 = and(mask_size_1, mask_eq_14)
node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1)
node _mask_acc_T_15 = and(mask_size_1, mask_eq_15)
node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15)
node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8)
node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10)
node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1)
node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14)
node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1)
node mask_1 = cat(mask_hi_1, mask_lo_1)
node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<3>(0h0))
node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 2, 0)
node _legal_source_T = shr(io.in.b.bits.source, 3)
node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0))
node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits)
node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2)
node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<3>(0h4))
node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4)
wire _legal_source_WIRE : UInt<1>[1]
connect _legal_source_WIRE[0], _legal_source_T_5
node legal_source = eq(UInt<1>(0h0), io.in.b.bits.source)
node _T_618 = eq(io.in.b.bits.opcode, UInt<3>(0h6))
when _T_618 :
node _T_619 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_620 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_621 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_622 = and(_T_620, _T_621)
node _T_623 = or(UInt<1>(0h0), _T_622)
node _T_624 = xor(io.in.b.bits.address, UInt<28>(0h8000040))
node _T_625 = cvt(_T_624)
node _T_626 = and(_T_625, asSInt(UInt<17>(0h100c0)))
node _T_627 = asSInt(_T_626)
node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0)))
node _T_629 = xor(io.in.b.bits.address, UInt<32>(0h80000040))
node _T_630 = cvt(_T_629)
node _T_631 = and(_T_630, asSInt(UInt<29>(0h100000c0)))
node _T_632 = asSInt(_T_631)
node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0)))
node _T_634 = or(_T_628, _T_633)
node _T_635 = and(_T_623, _T_634)
node _T_636 = or(UInt<1>(0h0), _T_635)
node _T_637 = and(_T_619, _T_636)
node _T_638 = asUInt(reset)
node _T_639 = eq(_T_638, UInt<1>(0h0))
when _T_639 :
node _T_640 = eq(_T_637, UInt<1>(0h0))
when _T_640 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86
assert(clock, _T_637, UInt<1>(0h1), "") : assert_86
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(address_ok, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87
assert(clock, address_ok, UInt<1>(0h1), "") : assert_87
node _T_644 = asUInt(reset)
node _T_645 = eq(_T_644, UInt<1>(0h0))
when _T_645 :
node _T_646 = eq(legal_source, UInt<1>(0h0))
when _T_646 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88
assert(clock, legal_source, UInt<1>(0h1), "") : assert_88
node _T_647 = asUInt(reset)
node _T_648 = eq(_T_647, UInt<1>(0h0))
when _T_648 :
node _T_649 = eq(is_aligned_1, UInt<1>(0h0))
when _T_649 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89
node _T_650 = leq(io.in.b.bits.param, UInt<2>(0h2))
node _T_651 = asUInt(reset)
node _T_652 = eq(_T_651, UInt<1>(0h0))
when _T_652 :
node _T_653 = eq(_T_650, UInt<1>(0h0))
when _T_653 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90
assert(clock, _T_650, UInt<1>(0h1), "") : assert_90
node _T_654 = eq(io.in.b.bits.mask, mask_1)
node _T_655 = asUInt(reset)
node _T_656 = eq(_T_655, UInt<1>(0h0))
when _T_656 :
node _T_657 = eq(_T_654, UInt<1>(0h0))
when _T_657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91
assert(clock, _T_654, UInt<1>(0h1), "") : assert_91
node _T_658 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_659 = asUInt(reset)
node _T_660 = eq(_T_659, UInt<1>(0h0))
when _T_660 :
node _T_661 = eq(_T_658, UInt<1>(0h0))
when _T_661 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_658, UInt<1>(0h1), "") : assert_92
node _T_662 = eq(io.in.b.bits.opcode, UInt<3>(0h4))
when _T_662 :
node _T_663 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_664 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_665 = and(_T_663, _T_664)
node _T_666 = or(UInt<1>(0h0), _T_665)
node _T_667 = xor(io.in.b.bits.address, UInt<28>(0h8000040))
node _T_668 = cvt(_T_667)
node _T_669 = and(_T_668, asSInt(UInt<17>(0h100c0)))
node _T_670 = asSInt(_T_669)
node _T_671 = eq(_T_670, asSInt(UInt<1>(0h0)))
node _T_672 = xor(io.in.b.bits.address, UInt<32>(0h80000040))
node _T_673 = cvt(_T_672)
node _T_674 = and(_T_673, asSInt(UInt<29>(0h100000c0)))
node _T_675 = asSInt(_T_674)
node _T_676 = eq(_T_675, asSInt(UInt<1>(0h0)))
node _T_677 = or(_T_671, _T_676)
node _T_678 = and(_T_666, _T_677)
node _T_679 = or(UInt<1>(0h0), _T_678)
node _T_680 = and(UInt<1>(0h0), _T_679)
node _T_681 = asUInt(reset)
node _T_682 = eq(_T_681, UInt<1>(0h0))
when _T_682 :
node _T_683 = eq(_T_680, UInt<1>(0h0))
when _T_683 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93
assert(clock, _T_680, UInt<1>(0h1), "") : assert_93
node _T_684 = asUInt(reset)
node _T_685 = eq(_T_684, UInt<1>(0h0))
when _T_685 :
node _T_686 = eq(address_ok, UInt<1>(0h0))
when _T_686 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94
assert(clock, address_ok, UInt<1>(0h1), "") : assert_94
node _T_687 = asUInt(reset)
node _T_688 = eq(_T_687, UInt<1>(0h0))
when _T_688 :
node _T_689 = eq(legal_source, UInt<1>(0h0))
when _T_689 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95
assert(clock, legal_source, UInt<1>(0h1), "") : assert_95
node _T_690 = asUInt(reset)
node _T_691 = eq(_T_690, UInt<1>(0h0))
when _T_691 :
node _T_692 = eq(is_aligned_1, UInt<1>(0h0))
when _T_692 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96
node _T_693 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_694 = asUInt(reset)
node _T_695 = eq(_T_694, UInt<1>(0h0))
when _T_695 :
node _T_696 = eq(_T_693, UInt<1>(0h0))
when _T_696 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97
assert(clock, _T_693, UInt<1>(0h1), "") : assert_97
node _T_697 = eq(io.in.b.bits.mask, mask_1)
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_697, UInt<1>(0h1), "") : assert_98
node _T_701 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_702 = asUInt(reset)
node _T_703 = eq(_T_702, UInt<1>(0h0))
when _T_703 :
node _T_704 = eq(_T_701, UInt<1>(0h0))
when _T_704 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99
assert(clock, _T_701, UInt<1>(0h1), "") : assert_99
node _T_705 = eq(io.in.b.bits.opcode, UInt<1>(0h0))
when _T_705 :
node _T_706 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_707 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_708 = and(_T_706, _T_707)
node _T_709 = or(UInt<1>(0h0), _T_708)
node _T_710 = xor(io.in.b.bits.address, UInt<28>(0h8000040))
node _T_711 = cvt(_T_710)
node _T_712 = and(_T_711, asSInt(UInt<17>(0h100c0)))
node _T_713 = asSInt(_T_712)
node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0)))
node _T_715 = xor(io.in.b.bits.address, UInt<32>(0h80000040))
node _T_716 = cvt(_T_715)
node _T_717 = and(_T_716, asSInt(UInt<29>(0h100000c0)))
node _T_718 = asSInt(_T_717)
node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0)))
node _T_720 = or(_T_714, _T_719)
node _T_721 = and(_T_709, _T_720)
node _T_722 = or(UInt<1>(0h0), _T_721)
node _T_723 = and(UInt<1>(0h0), _T_722)
node _T_724 = asUInt(reset)
node _T_725 = eq(_T_724, UInt<1>(0h0))
when _T_725 :
node _T_726 = eq(_T_723, UInt<1>(0h0))
when _T_726 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100
assert(clock, _T_723, UInt<1>(0h1), "") : assert_100
node _T_727 = asUInt(reset)
node _T_728 = eq(_T_727, UInt<1>(0h0))
when _T_728 :
node _T_729 = eq(address_ok, UInt<1>(0h0))
when _T_729 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101
assert(clock, address_ok, UInt<1>(0h1), "") : assert_101
node _T_730 = asUInt(reset)
node _T_731 = eq(_T_730, UInt<1>(0h0))
when _T_731 :
node _T_732 = eq(legal_source, UInt<1>(0h0))
when _T_732 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102
assert(clock, legal_source, UInt<1>(0h1), "") : assert_102
node _T_733 = asUInt(reset)
node _T_734 = eq(_T_733, UInt<1>(0h0))
when _T_734 :
node _T_735 = eq(is_aligned_1, UInt<1>(0h0))
when _T_735 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103
node _T_736 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_737 = asUInt(reset)
node _T_738 = eq(_T_737, UInt<1>(0h0))
when _T_738 :
node _T_739 = eq(_T_736, UInt<1>(0h0))
when _T_739 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104
assert(clock, _T_736, UInt<1>(0h1), "") : assert_104
node _T_740 = eq(io.in.b.bits.mask, mask_1)
node _T_741 = asUInt(reset)
node _T_742 = eq(_T_741, UInt<1>(0h0))
when _T_742 :
node _T_743 = eq(_T_740, UInt<1>(0h0))
when _T_743 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_740, UInt<1>(0h1), "") : assert_105
node _T_744 = eq(io.in.b.bits.opcode, UInt<1>(0h1))
when _T_744 :
node _T_745 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_746 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_747 = and(_T_745, _T_746)
node _T_748 = or(UInt<1>(0h0), _T_747)
node _T_749 = xor(io.in.b.bits.address, UInt<28>(0h8000040))
node _T_750 = cvt(_T_749)
node _T_751 = and(_T_750, asSInt(UInt<17>(0h100c0)))
node _T_752 = asSInt(_T_751)
node _T_753 = eq(_T_752, asSInt(UInt<1>(0h0)))
node _T_754 = xor(io.in.b.bits.address, UInt<32>(0h80000040))
node _T_755 = cvt(_T_754)
node _T_756 = and(_T_755, asSInt(UInt<29>(0h100000c0)))
node _T_757 = asSInt(_T_756)
node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0)))
node _T_759 = or(_T_753, _T_758)
node _T_760 = and(_T_748, _T_759)
node _T_761 = or(UInt<1>(0h0), _T_760)
node _T_762 = and(UInt<1>(0h0), _T_761)
node _T_763 = asUInt(reset)
node _T_764 = eq(_T_763, UInt<1>(0h0))
when _T_764 :
node _T_765 = eq(_T_762, UInt<1>(0h0))
when _T_765 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_762, UInt<1>(0h1), "") : assert_106
node _T_766 = asUInt(reset)
node _T_767 = eq(_T_766, UInt<1>(0h0))
when _T_767 :
node _T_768 = eq(address_ok, UInt<1>(0h0))
when _T_768 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, address_ok, UInt<1>(0h1), "") : assert_107
node _T_769 = asUInt(reset)
node _T_770 = eq(_T_769, UInt<1>(0h0))
when _T_770 :
node _T_771 = eq(legal_source, UInt<1>(0h0))
when _T_771 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108
assert(clock, legal_source, UInt<1>(0h1), "") : assert_108
node _T_772 = asUInt(reset)
node _T_773 = eq(_T_772, UInt<1>(0h0))
when _T_773 :
node _T_774 = eq(is_aligned_1, UInt<1>(0h0))
when _T_774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109
node _T_775 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_776 = asUInt(reset)
node _T_777 = eq(_T_776, UInt<1>(0h0))
when _T_777 :
node _T_778 = eq(_T_775, UInt<1>(0h0))
when _T_778 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110
assert(clock, _T_775, UInt<1>(0h1), "") : assert_110
node _T_779 = not(mask_1)
node _T_780 = and(io.in.b.bits.mask, _T_779)
node _T_781 = eq(_T_780, UInt<1>(0h0))
node _T_782 = asUInt(reset)
node _T_783 = eq(_T_782, UInt<1>(0h0))
when _T_783 :
node _T_784 = eq(_T_781, UInt<1>(0h0))
when _T_784 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_781, UInt<1>(0h1), "") : assert_111
node _T_785 = eq(io.in.b.bits.opcode, UInt<2>(0h2))
when _T_785 :
node _T_786 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_787 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_788 = and(_T_786, _T_787)
node _T_789 = or(UInt<1>(0h0), _T_788)
node _T_790 = xor(io.in.b.bits.address, UInt<28>(0h8000040))
node _T_791 = cvt(_T_790)
node _T_792 = and(_T_791, asSInt(UInt<17>(0h100c0)))
node _T_793 = asSInt(_T_792)
node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0)))
node _T_795 = xor(io.in.b.bits.address, UInt<32>(0h80000040))
node _T_796 = cvt(_T_795)
node _T_797 = and(_T_796, asSInt(UInt<29>(0h100000c0)))
node _T_798 = asSInt(_T_797)
node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0)))
node _T_800 = or(_T_794, _T_799)
node _T_801 = and(_T_789, _T_800)
node _T_802 = or(UInt<1>(0h0), _T_801)
node _T_803 = and(UInt<1>(0h0), _T_802)
node _T_804 = asUInt(reset)
node _T_805 = eq(_T_804, UInt<1>(0h0))
when _T_805 :
node _T_806 = eq(_T_803, UInt<1>(0h0))
when _T_806 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112
assert(clock, _T_803, UInt<1>(0h1), "") : assert_112
node _T_807 = asUInt(reset)
node _T_808 = eq(_T_807, UInt<1>(0h0))
when _T_808 :
node _T_809 = eq(address_ok, UInt<1>(0h0))
when _T_809 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, address_ok, UInt<1>(0h1), "") : assert_113
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(legal_source, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114
assert(clock, legal_source, UInt<1>(0h1), "") : assert_114
node _T_813 = asUInt(reset)
node _T_814 = eq(_T_813, UInt<1>(0h0))
when _T_814 :
node _T_815 = eq(is_aligned_1, UInt<1>(0h0))
when _T_815 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115
node _T_816 = leq(io.in.b.bits.param, UInt<3>(0h4))
node _T_817 = asUInt(reset)
node _T_818 = eq(_T_817, UInt<1>(0h0))
when _T_818 :
node _T_819 = eq(_T_816, UInt<1>(0h0))
when _T_819 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116
assert(clock, _T_816, UInt<1>(0h1), "") : assert_116
node _T_820 = eq(io.in.b.bits.mask, mask_1)
node _T_821 = asUInt(reset)
node _T_822 = eq(_T_821, UInt<1>(0h0))
when _T_822 :
node _T_823 = eq(_T_820, UInt<1>(0h0))
when _T_823 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117
assert(clock, _T_820, UInt<1>(0h1), "") : assert_117
node _T_824 = eq(io.in.b.bits.opcode, UInt<2>(0h3))
when _T_824 :
node _T_825 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_826 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_827 = and(_T_825, _T_826)
node _T_828 = or(UInt<1>(0h0), _T_827)
node _T_829 = xor(io.in.b.bits.address, UInt<28>(0h8000040))
node _T_830 = cvt(_T_829)
node _T_831 = and(_T_830, asSInt(UInt<17>(0h100c0)))
node _T_832 = asSInt(_T_831)
node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0)))
node _T_834 = xor(io.in.b.bits.address, UInt<32>(0h80000040))
node _T_835 = cvt(_T_834)
node _T_836 = and(_T_835, asSInt(UInt<29>(0h100000c0)))
node _T_837 = asSInt(_T_836)
node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0)))
node _T_839 = or(_T_833, _T_838)
node _T_840 = and(_T_828, _T_839)
node _T_841 = or(UInt<1>(0h0), _T_840)
node _T_842 = and(UInt<1>(0h0), _T_841)
node _T_843 = asUInt(reset)
node _T_844 = eq(_T_843, UInt<1>(0h0))
when _T_844 :
node _T_845 = eq(_T_842, UInt<1>(0h0))
when _T_845 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118
assert(clock, _T_842, UInt<1>(0h1), "") : assert_118
node _T_846 = asUInt(reset)
node _T_847 = eq(_T_846, UInt<1>(0h0))
when _T_847 :
node _T_848 = eq(address_ok, UInt<1>(0h0))
when _T_848 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119
assert(clock, address_ok, UInt<1>(0h1), "") : assert_119
node _T_849 = asUInt(reset)
node _T_850 = eq(_T_849, UInt<1>(0h0))
when _T_850 :
node _T_851 = eq(legal_source, UInt<1>(0h0))
when _T_851 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120
assert(clock, legal_source, UInt<1>(0h1), "") : assert_120
node _T_852 = asUInt(reset)
node _T_853 = eq(_T_852, UInt<1>(0h0))
when _T_853 :
node _T_854 = eq(is_aligned_1, UInt<1>(0h0))
when _T_854 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121
node _T_855 = leq(io.in.b.bits.param, UInt<3>(0h3))
node _T_856 = asUInt(reset)
node _T_857 = eq(_T_856, UInt<1>(0h0))
when _T_857 :
node _T_858 = eq(_T_855, UInt<1>(0h0))
when _T_858 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122
assert(clock, _T_855, UInt<1>(0h1), "") : assert_122
node _T_859 = eq(io.in.b.bits.mask, mask_1)
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(_T_859, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123
assert(clock, _T_859, UInt<1>(0h1), "") : assert_123
node _T_863 = eq(io.in.b.bits.opcode, UInt<3>(0h5))
when _T_863 :
node _T_864 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_865 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_866 = and(_T_864, _T_865)
node _T_867 = or(UInt<1>(0h0), _T_866)
node _T_868 = xor(io.in.b.bits.address, UInt<28>(0h8000040))
node _T_869 = cvt(_T_868)
node _T_870 = and(_T_869, asSInt(UInt<17>(0h100c0)))
node _T_871 = asSInt(_T_870)
node _T_872 = eq(_T_871, asSInt(UInt<1>(0h0)))
node _T_873 = xor(io.in.b.bits.address, UInt<32>(0h80000040))
node _T_874 = cvt(_T_873)
node _T_875 = and(_T_874, asSInt(UInt<29>(0h100000c0)))
node _T_876 = asSInt(_T_875)
node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0)))
node _T_878 = or(_T_872, _T_877)
node _T_879 = and(_T_867, _T_878)
node _T_880 = or(UInt<1>(0h0), _T_879)
node _T_881 = and(UInt<1>(0h0), _T_880)
node _T_882 = asUInt(reset)
node _T_883 = eq(_T_882, UInt<1>(0h0))
when _T_883 :
node _T_884 = eq(_T_881, UInt<1>(0h0))
when _T_884 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124
assert(clock, _T_881, UInt<1>(0h1), "") : assert_124
node _T_885 = asUInt(reset)
node _T_886 = eq(_T_885, UInt<1>(0h0))
when _T_886 :
node _T_887 = eq(address_ok, UInt<1>(0h0))
when _T_887 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125
assert(clock, address_ok, UInt<1>(0h1), "") : assert_125
node _T_888 = asUInt(reset)
node _T_889 = eq(_T_888, UInt<1>(0h0))
when _T_889 :
node _T_890 = eq(legal_source, UInt<1>(0h0))
when _T_890 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126
assert(clock, legal_source, UInt<1>(0h1), "") : assert_126
node _T_891 = asUInt(reset)
node _T_892 = eq(_T_891, UInt<1>(0h0))
when _T_892 :
node _T_893 = eq(is_aligned_1, UInt<1>(0h0))
when _T_893 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127
node _T_894 = eq(io.in.b.bits.mask, mask_1)
node _T_895 = asUInt(reset)
node _T_896 = eq(_T_895, UInt<1>(0h0))
when _T_896 :
node _T_897 = eq(_T_894, UInt<1>(0h0))
when _T_897 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128
assert(clock, _T_894, UInt<1>(0h1), "") : assert_128
node _T_898 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_899 = asUInt(reset)
node _T_900 = eq(_T_899, UInt<1>(0h0))
when _T_900 :
node _T_901 = eq(_T_898, UInt<1>(0h0))
when _T_901 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129
assert(clock, _T_898, UInt<1>(0h1), "") : assert_129
when io.in.c.valid :
node _T_902 = leq(io.in.c.bits.opcode, UInt<3>(0h7))
node _T_903 = asUInt(reset)
node _T_904 = eq(_T_903, UInt<1>(0h0))
when _T_904 :
node _T_905 = eq(_T_902, UInt<1>(0h0))
when _T_905 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130
assert(clock, _T_902, UInt<1>(0h1), "") : assert_130
node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 2, 0)
node _source_ok_T_12 = shr(io.in.c.bits.source, 3)
node _source_ok_T_13 = eq(_source_ok_T_12, UInt<1>(0h0))
node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14)
node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<3>(0h4))
node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16)
wire _source_ok_WIRE_2 : UInt<1>[1]
connect _source_ok_WIRE_2[0], _source_ok_T_17
node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0)
node is_aligned_mask_2 = not(_is_aligned_mask_T_5)
node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2)
node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0))
node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000040))
node _address_ok_T_11 = cvt(_address_ok_T_10)
node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h100c0)))
node _address_ok_T_13 = asSInt(_address_ok_T_12)
node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0)))
node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000040))
node _address_ok_T_16 = cvt(_address_ok_T_15)
node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h100000c0)))
node _address_ok_T_18 = asSInt(_address_ok_T_17)
node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE_1 : UInt<1>[2]
connect _address_ok_WIRE_1[0], _address_ok_T_14
connect _address_ok_WIRE_1[1], _address_ok_T_19
node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1])
node _uncommonBits_T_10 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 2, 0)
node _T_906 = shr(io.in.c.bits.source, 3)
node _T_907 = eq(_T_906, UInt<1>(0h0))
node _T_908 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_909 = and(_T_907, _T_908)
node _T_910 = leq(uncommonBits_10, UInt<3>(0h4))
node _T_911 = and(_T_909, _T_910)
node _T_912 = eq(_T_911, UInt<1>(0h0))
node _T_913 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_914 = cvt(_T_913)
node _T_915 = and(_T_914, asSInt(UInt<1>(0h0)))
node _T_916 = asSInt(_T_915)
node _T_917 = eq(_T_916, asSInt(UInt<1>(0h0)))
node _T_918 = or(_T_912, _T_917)
node _T_919 = asUInt(reset)
node _T_920 = eq(_T_919, UInt<1>(0h0))
when _T_920 :
node _T_921 = eq(_T_918, UInt<1>(0h0))
when _T_921 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131
assert(clock, _T_918, UInt<1>(0h1), "") : assert_131
node _T_922 = eq(io.in.c.bits.opcode, UInt<3>(0h4))
when _T_922 :
node _T_923 = asUInt(reset)
node _T_924 = eq(_T_923, UInt<1>(0h0))
when _T_924 :
node _T_925 = eq(address_ok_1, UInt<1>(0h0))
when _T_925 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132
node _T_926 = asUInt(reset)
node _T_927 = eq(_T_926, UInt<1>(0h0))
when _T_927 :
node _T_928 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_928 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_133
node _T_929 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_T_929, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134
assert(clock, _T_929, UInt<1>(0h1), "") : assert_134
node _T_933 = asUInt(reset)
node _T_934 = eq(_T_933, UInt<1>(0h0))
when _T_934 :
node _T_935 = eq(is_aligned_2, UInt<1>(0h0))
when _T_935 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135
node _T_936 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_937 = asUInt(reset)
node _T_938 = eq(_T_937, UInt<1>(0h0))
when _T_938 :
node _T_939 = eq(_T_936, UInt<1>(0h0))
when _T_939 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136
assert(clock, _T_936, UInt<1>(0h1), "") : assert_136
node _T_940 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_941 = asUInt(reset)
node _T_942 = eq(_T_941, UInt<1>(0h0))
when _T_942 :
node _T_943 = eq(_T_940, UInt<1>(0h0))
when _T_943 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137
assert(clock, _T_940, UInt<1>(0h1), "") : assert_137
node _T_944 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
when _T_944 :
node _T_945 = asUInt(reset)
node _T_946 = eq(_T_945, UInt<1>(0h0))
when _T_946 :
node _T_947 = eq(address_ok_1, UInt<1>(0h0))
when _T_947 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138
node _T_948 = asUInt(reset)
node _T_949 = eq(_T_948, UInt<1>(0h0))
when _T_949 :
node _T_950 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_950 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_139
node _T_951 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_952 = asUInt(reset)
node _T_953 = eq(_T_952, UInt<1>(0h0))
when _T_953 :
node _T_954 = eq(_T_951, UInt<1>(0h0))
when _T_954 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140
assert(clock, _T_951, UInt<1>(0h1), "") : assert_140
node _T_955 = asUInt(reset)
node _T_956 = eq(_T_955, UInt<1>(0h0))
when _T_956 :
node _T_957 = eq(is_aligned_2, UInt<1>(0h0))
when _T_957 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141
node _T_958 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_959 = asUInt(reset)
node _T_960 = eq(_T_959, UInt<1>(0h0))
when _T_960 :
node _T_961 = eq(_T_958, UInt<1>(0h0))
when _T_961 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142
assert(clock, _T_958, UInt<1>(0h1), "") : assert_142
node _T_962 = eq(io.in.c.bits.opcode, UInt<3>(0h6))
when _T_962 :
node _T_963 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_964 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_965 = and(_T_963, _T_964)
node _uncommonBits_T_11 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0)
node _T_966 = shr(io.in.c.bits.source, 3)
node _T_967 = eq(_T_966, UInt<1>(0h0))
node _T_968 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_969 = and(_T_967, _T_968)
node _T_970 = leq(uncommonBits_11, UInt<3>(0h4))
node _T_971 = and(_T_969, _T_970)
node _T_972 = and(_T_965, _T_971)
node _T_973 = or(UInt<1>(0h0), _T_972)
node _T_974 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_975 = leq(io.in.c.bits.size, UInt<3>(0h6))
node _T_976 = and(_T_974, _T_975)
node _T_977 = or(UInt<1>(0h0), _T_976)
node _T_978 = xor(io.in.c.bits.address, UInt<28>(0h8000040))
node _T_979 = cvt(_T_978)
node _T_980 = and(_T_979, asSInt(UInt<17>(0h100c0)))
node _T_981 = asSInt(_T_980)
node _T_982 = eq(_T_981, asSInt(UInt<1>(0h0)))
node _T_983 = xor(io.in.c.bits.address, UInt<32>(0h80000040))
node _T_984 = cvt(_T_983)
node _T_985 = and(_T_984, asSInt(UInt<29>(0h100000c0)))
node _T_986 = asSInt(_T_985)
node _T_987 = eq(_T_986, asSInt(UInt<1>(0h0)))
node _T_988 = or(_T_982, _T_987)
node _T_989 = and(_T_977, _T_988)
node _T_990 = or(UInt<1>(0h0), _T_989)
node _T_991 = and(_T_973, _T_990)
node _T_992 = asUInt(reset)
node _T_993 = eq(_T_992, UInt<1>(0h0))
when _T_993 :
node _T_994 = eq(_T_991, UInt<1>(0h0))
when _T_994 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143
assert(clock, _T_991, UInt<1>(0h1), "") : assert_143
node _T_995 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_996 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_997 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_998 = and(_T_996, _T_997)
node _T_999 = or(UInt<1>(0h0), _T_998)
node _T_1000 = xor(io.in.c.bits.address, UInt<28>(0h8000040))
node _T_1001 = cvt(_T_1000)
node _T_1002 = and(_T_1001, asSInt(UInt<17>(0h100c0)))
node _T_1003 = asSInt(_T_1002)
node _T_1004 = eq(_T_1003, asSInt(UInt<1>(0h0)))
node _T_1005 = xor(io.in.c.bits.address, UInt<32>(0h80000040))
node _T_1006 = cvt(_T_1005)
node _T_1007 = and(_T_1006, asSInt(UInt<29>(0h100000c0)))
node _T_1008 = asSInt(_T_1007)
node _T_1009 = eq(_T_1008, asSInt(UInt<1>(0h0)))
node _T_1010 = or(_T_1004, _T_1009)
node _T_1011 = and(_T_999, _T_1010)
node _T_1012 = or(UInt<1>(0h0), _T_1011)
node _T_1013 = and(_T_995, _T_1012)
node _T_1014 = asUInt(reset)
node _T_1015 = eq(_T_1014, UInt<1>(0h0))
when _T_1015 :
node _T_1016 = eq(_T_1013, UInt<1>(0h0))
when _T_1016 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144
assert(clock, _T_1013, UInt<1>(0h1), "") : assert_144
node _T_1017 = asUInt(reset)
node _T_1018 = eq(_T_1017, UInt<1>(0h0))
when _T_1018 :
node _T_1019 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_1019 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_145
node _T_1020 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1021 = asUInt(reset)
node _T_1022 = eq(_T_1021, UInt<1>(0h0))
when _T_1022 :
node _T_1023 = eq(_T_1020, UInt<1>(0h0))
when _T_1023 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146
assert(clock, _T_1020, UInt<1>(0h1), "") : assert_146
node _T_1024 = asUInt(reset)
node _T_1025 = eq(_T_1024, UInt<1>(0h0))
when _T_1025 :
node _T_1026 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1026 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147
node _T_1027 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1028 = asUInt(reset)
node _T_1029 = eq(_T_1028, UInt<1>(0h0))
when _T_1029 :
node _T_1030 = eq(_T_1027, UInt<1>(0h0))
when _T_1030 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148
assert(clock, _T_1027, UInt<1>(0h1), "") : assert_148
node _T_1031 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1032 = asUInt(reset)
node _T_1033 = eq(_T_1032, UInt<1>(0h0))
when _T_1033 :
node _T_1034 = eq(_T_1031, UInt<1>(0h0))
when _T_1034 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149
assert(clock, _T_1031, UInt<1>(0h1), "") : assert_149
node _T_1035 = eq(io.in.c.bits.opcode, UInt<3>(0h7))
when _T_1035 :
node _T_1036 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1037 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1038 = and(_T_1036, _T_1037)
node _uncommonBits_T_12 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0)
node _T_1039 = shr(io.in.c.bits.source, 3)
node _T_1040 = eq(_T_1039, UInt<1>(0h0))
node _T_1041 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_1042 = and(_T_1040, _T_1041)
node _T_1043 = leq(uncommonBits_12, UInt<3>(0h4))
node _T_1044 = and(_T_1042, _T_1043)
node _T_1045 = and(_T_1038, _T_1044)
node _T_1046 = or(UInt<1>(0h0), _T_1045)
node _T_1047 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1048 = leq(io.in.c.bits.size, UInt<3>(0h6))
node _T_1049 = and(_T_1047, _T_1048)
node _T_1050 = or(UInt<1>(0h0), _T_1049)
node _T_1051 = xor(io.in.c.bits.address, UInt<28>(0h8000040))
node _T_1052 = cvt(_T_1051)
node _T_1053 = and(_T_1052, asSInt(UInt<17>(0h100c0)))
node _T_1054 = asSInt(_T_1053)
node _T_1055 = eq(_T_1054, asSInt(UInt<1>(0h0)))
node _T_1056 = xor(io.in.c.bits.address, UInt<32>(0h80000040))
node _T_1057 = cvt(_T_1056)
node _T_1058 = and(_T_1057, asSInt(UInt<29>(0h100000c0)))
node _T_1059 = asSInt(_T_1058)
node _T_1060 = eq(_T_1059, asSInt(UInt<1>(0h0)))
node _T_1061 = or(_T_1055, _T_1060)
node _T_1062 = and(_T_1050, _T_1061)
node _T_1063 = or(UInt<1>(0h0), _T_1062)
node _T_1064 = and(_T_1046, _T_1063)
node _T_1065 = asUInt(reset)
node _T_1066 = eq(_T_1065, UInt<1>(0h0))
when _T_1066 :
node _T_1067 = eq(_T_1064, UInt<1>(0h0))
when _T_1067 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150
assert(clock, _T_1064, UInt<1>(0h1), "") : assert_150
node _T_1068 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1069 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1070 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1071 = and(_T_1069, _T_1070)
node _T_1072 = or(UInt<1>(0h0), _T_1071)
node _T_1073 = xor(io.in.c.bits.address, UInt<28>(0h8000040))
node _T_1074 = cvt(_T_1073)
node _T_1075 = and(_T_1074, asSInt(UInt<17>(0h100c0)))
node _T_1076 = asSInt(_T_1075)
node _T_1077 = eq(_T_1076, asSInt(UInt<1>(0h0)))
node _T_1078 = xor(io.in.c.bits.address, UInt<32>(0h80000040))
node _T_1079 = cvt(_T_1078)
node _T_1080 = and(_T_1079, asSInt(UInt<29>(0h100000c0)))
node _T_1081 = asSInt(_T_1080)
node _T_1082 = eq(_T_1081, asSInt(UInt<1>(0h0)))
node _T_1083 = or(_T_1077, _T_1082)
node _T_1084 = and(_T_1072, _T_1083)
node _T_1085 = or(UInt<1>(0h0), _T_1084)
node _T_1086 = and(_T_1068, _T_1085)
node _T_1087 = asUInt(reset)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = eq(_T_1086, UInt<1>(0h0))
when _T_1089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151
assert(clock, _T_1086, UInt<1>(0h1), "") : assert_151
node _T_1090 = asUInt(reset)
node _T_1091 = eq(_T_1090, UInt<1>(0h0))
when _T_1091 :
node _T_1092 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_1092 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_152
node _T_1093 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1094 = asUInt(reset)
node _T_1095 = eq(_T_1094, UInt<1>(0h0))
when _T_1095 :
node _T_1096 = eq(_T_1093, UInt<1>(0h0))
when _T_1096 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153
assert(clock, _T_1093, UInt<1>(0h1), "") : assert_153
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154
node _T_1100 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1101 = asUInt(reset)
node _T_1102 = eq(_T_1101, UInt<1>(0h0))
when _T_1102 :
node _T_1103 = eq(_T_1100, UInt<1>(0h0))
when _T_1103 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155
assert(clock, _T_1100, UInt<1>(0h1), "") : assert_155
node _T_1104 = eq(io.in.c.bits.opcode, UInt<1>(0h0))
when _T_1104 :
node _T_1105 = asUInt(reset)
node _T_1106 = eq(_T_1105, UInt<1>(0h0))
when _T_1106 :
node _T_1107 = eq(address_ok_1, UInt<1>(0h0))
when _T_1107 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156
node _T_1108 = asUInt(reset)
node _T_1109 = eq(_T_1108, UInt<1>(0h0))
when _T_1109 :
node _T_1110 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_1110 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_157
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158
node _T_1114 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_1115 = asUInt(reset)
node _T_1116 = eq(_T_1115, UInt<1>(0h0))
when _T_1116 :
node _T_1117 = eq(_T_1114, UInt<1>(0h0))
when _T_1117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159
assert(clock, _T_1114, UInt<1>(0h1), "") : assert_159
node _T_1118 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1119 = asUInt(reset)
node _T_1120 = eq(_T_1119, UInt<1>(0h0))
when _T_1120 :
node _T_1121 = eq(_T_1118, UInt<1>(0h0))
when _T_1121 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160
assert(clock, _T_1118, UInt<1>(0h1), "") : assert_160
node _T_1122 = eq(io.in.c.bits.opcode, UInt<1>(0h1))
when _T_1122 :
node _T_1123 = asUInt(reset)
node _T_1124 = eq(_T_1123, UInt<1>(0h0))
when _T_1124 :
node _T_1125 = eq(address_ok_1, UInt<1>(0h0))
when _T_1125 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161
node _T_1126 = asUInt(reset)
node _T_1127 = eq(_T_1126, UInt<1>(0h0))
when _T_1127 :
node _T_1128 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_1128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_162
node _T_1129 = asUInt(reset)
node _T_1130 = eq(_T_1129, UInt<1>(0h0))
when _T_1130 :
node _T_1131 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1131 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163
node _T_1132 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_1133 = asUInt(reset)
node _T_1134 = eq(_T_1133, UInt<1>(0h0))
when _T_1134 :
node _T_1135 = eq(_T_1132, UInt<1>(0h0))
when _T_1135 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164
assert(clock, _T_1132, UInt<1>(0h1), "") : assert_164
node _T_1136 = eq(io.in.c.bits.opcode, UInt<2>(0h2))
when _T_1136 :
node _T_1137 = asUInt(reset)
node _T_1138 = eq(_T_1137, UInt<1>(0h0))
when _T_1138 :
node _T_1139 = eq(address_ok_1, UInt<1>(0h0))
when _T_1139 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165
node _T_1140 = asUInt(reset)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
when _T_1141 :
node _T_1142 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_1142 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_166
node _T_1143 = asUInt(reset)
node _T_1144 = eq(_T_1143, UInt<1>(0h0))
when _T_1144 :
node _T_1145 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1145 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167
node _T_1146 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_1147 = asUInt(reset)
node _T_1148 = eq(_T_1147, UInt<1>(0h0))
when _T_1148 :
node _T_1149 = eq(_T_1146, UInt<1>(0h0))
when _T_1149 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168
assert(clock, _T_1146, UInt<1>(0h1), "") : assert_168
node _T_1150 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1151 = asUInt(reset)
node _T_1152 = eq(_T_1151, UInt<1>(0h0))
when _T_1152 :
node _T_1153 = eq(_T_1150, UInt<1>(0h0))
when _T_1153 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169
assert(clock, _T_1150, UInt<1>(0h1), "") : assert_169
when io.in.e.valid :
node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8))
node _T_1154 = asUInt(reset)
node _T_1155 = eq(_T_1154, UInt<1>(0h0))
when _T_1155 :
node _T_1156 = eq(sink_ok_1, UInt<1>(0h0))
when _T_1156 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170
assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1157 = eq(a_first, UInt<1>(0h0))
node _T_1158 = and(io.in.a.valid, _T_1157)
when _T_1158 :
node _T_1159 = eq(io.in.a.bits.opcode, opcode)
node _T_1160 = asUInt(reset)
node _T_1161 = eq(_T_1160, UInt<1>(0h0))
when _T_1161 :
node _T_1162 = eq(_T_1159, UInt<1>(0h0))
when _T_1162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171
assert(clock, _T_1159, UInt<1>(0h1), "") : assert_171
node _T_1163 = eq(io.in.a.bits.param, param)
node _T_1164 = asUInt(reset)
node _T_1165 = eq(_T_1164, UInt<1>(0h0))
when _T_1165 :
node _T_1166 = eq(_T_1163, UInt<1>(0h0))
when _T_1166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172
assert(clock, _T_1163, UInt<1>(0h1), "") : assert_172
node _T_1167 = eq(io.in.a.bits.size, size)
node _T_1168 = asUInt(reset)
node _T_1169 = eq(_T_1168, UInt<1>(0h0))
when _T_1169 :
node _T_1170 = eq(_T_1167, UInt<1>(0h0))
when _T_1170 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173
assert(clock, _T_1167, UInt<1>(0h1), "") : assert_173
node _T_1171 = eq(io.in.a.bits.source, source)
node _T_1172 = asUInt(reset)
node _T_1173 = eq(_T_1172, UInt<1>(0h0))
when _T_1173 :
node _T_1174 = eq(_T_1171, UInt<1>(0h0))
when _T_1174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174
assert(clock, _T_1171, UInt<1>(0h1), "") : assert_174
node _T_1175 = eq(io.in.a.bits.address, address)
node _T_1176 = asUInt(reset)
node _T_1177 = eq(_T_1176, UInt<1>(0h0))
when _T_1177 :
node _T_1178 = eq(_T_1175, UInt<1>(0h0))
when _T_1178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175
assert(clock, _T_1175, UInt<1>(0h1), "") : assert_175
node _T_1179 = and(io.in.a.ready, io.in.a.valid)
node _T_1180 = and(_T_1179, a_first)
when _T_1180 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1181 = eq(d_first, UInt<1>(0h0))
node _T_1182 = and(io.in.d.valid, _T_1181)
when _T_1182 :
node _T_1183 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1184 = asUInt(reset)
node _T_1185 = eq(_T_1184, UInt<1>(0h0))
when _T_1185 :
node _T_1186 = eq(_T_1183, UInt<1>(0h0))
when _T_1186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176
assert(clock, _T_1183, UInt<1>(0h1), "") : assert_176
node _T_1187 = eq(io.in.d.bits.param, param_1)
node _T_1188 = asUInt(reset)
node _T_1189 = eq(_T_1188, UInt<1>(0h0))
when _T_1189 :
node _T_1190 = eq(_T_1187, UInt<1>(0h0))
when _T_1190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177
assert(clock, _T_1187, UInt<1>(0h1), "") : assert_177
node _T_1191 = eq(io.in.d.bits.size, size_1)
node _T_1192 = asUInt(reset)
node _T_1193 = eq(_T_1192, UInt<1>(0h0))
when _T_1193 :
node _T_1194 = eq(_T_1191, UInt<1>(0h0))
when _T_1194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178
assert(clock, _T_1191, UInt<1>(0h1), "") : assert_178
node _T_1195 = eq(io.in.d.bits.source, source_1)
node _T_1196 = asUInt(reset)
node _T_1197 = eq(_T_1196, UInt<1>(0h0))
when _T_1197 :
node _T_1198 = eq(_T_1195, UInt<1>(0h0))
when _T_1198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179
assert(clock, _T_1195, UInt<1>(0h1), "") : assert_179
node _T_1199 = eq(io.in.d.bits.sink, sink)
node _T_1200 = asUInt(reset)
node _T_1201 = eq(_T_1200, UInt<1>(0h0))
when _T_1201 :
node _T_1202 = eq(_T_1199, UInt<1>(0h0))
when _T_1202 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180
assert(clock, _T_1199, UInt<1>(0h1), "") : assert_180
node _T_1203 = eq(io.in.d.bits.denied, denied)
node _T_1204 = asUInt(reset)
node _T_1205 = eq(_T_1204, UInt<1>(0h0))
when _T_1205 :
node _T_1206 = eq(_T_1203, UInt<1>(0h0))
when _T_1206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181
assert(clock, _T_1203, UInt<1>(0h1), "") : assert_181
node _T_1207 = and(io.in.d.ready, io.in.d.valid)
node _T_1208 = and(_T_1207, d_first)
when _T_1208 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
node _b_first_T = and(io.in.b.ready, io.in.b.valid)
node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size)
node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0)
node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1)
node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3)
node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2)
node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0))
node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0))
regreset b_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1))
node b_first_counter1 = tail(_b_first_counter1_T, 1)
node b_first = eq(b_first_counter, UInt<1>(0h0))
node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1))
node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0))
node b_first_last = or(_b_first_last_T, _b_first_last_T_1)
node b_first_done = and(b_first_last, _b_first_T)
node _b_first_count_T = not(b_first_counter1)
node b_first_count = and(b_first_beats1, _b_first_count_T)
when _b_first_T :
node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1)
connect b_first_counter, _b_first_counter_T
reg opcode_2 : UInt, clock
reg param_2 : UInt, clock
reg size_2 : UInt, clock
reg source_2 : UInt, clock
reg address_1 : UInt, clock
node _T_1209 = eq(b_first, UInt<1>(0h0))
node _T_1210 = and(io.in.b.valid, _T_1209)
when _T_1210 :
node _T_1211 = eq(io.in.b.bits.opcode, opcode_2)
node _T_1212 = asUInt(reset)
node _T_1213 = eq(_T_1212, UInt<1>(0h0))
when _T_1213 :
node _T_1214 = eq(_T_1211, UInt<1>(0h0))
when _T_1214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182
assert(clock, _T_1211, UInt<1>(0h1), "") : assert_182
node _T_1215 = eq(io.in.b.bits.param, param_2)
node _T_1216 = asUInt(reset)
node _T_1217 = eq(_T_1216, UInt<1>(0h0))
when _T_1217 :
node _T_1218 = eq(_T_1215, UInt<1>(0h0))
when _T_1218 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183
assert(clock, _T_1215, UInt<1>(0h1), "") : assert_183
node _T_1219 = eq(io.in.b.bits.size, size_2)
node _T_1220 = asUInt(reset)
node _T_1221 = eq(_T_1220, UInt<1>(0h0))
when _T_1221 :
node _T_1222 = eq(_T_1219, UInt<1>(0h0))
when _T_1222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184
assert(clock, _T_1219, UInt<1>(0h1), "") : assert_184
node _T_1223 = eq(io.in.b.bits.source, source_2)
node _T_1224 = asUInt(reset)
node _T_1225 = eq(_T_1224, UInt<1>(0h0))
when _T_1225 :
node _T_1226 = eq(_T_1223, UInt<1>(0h0))
when _T_1226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185
assert(clock, _T_1223, UInt<1>(0h1), "") : assert_185
node _T_1227 = eq(io.in.b.bits.address, address_1)
node _T_1228 = asUInt(reset)
node _T_1229 = eq(_T_1228, UInt<1>(0h0))
when _T_1229 :
node _T_1230 = eq(_T_1227, UInt<1>(0h0))
when _T_1230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186
assert(clock, _T_1227, UInt<1>(0h1), "") : assert_186
node _T_1231 = and(io.in.b.ready, io.in.b.valid)
node _T_1232 = and(_T_1231, b_first)
when _T_1232 :
connect opcode_2, io.in.b.bits.opcode
connect param_2, io.in.b.bits.param
connect size_2, io.in.b.bits.size
connect source_2, io.in.b.bits.source
connect address_1, io.in.b.bits.address
node _c_first_T = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
reg opcode_3 : UInt, clock
reg param_3 : UInt, clock
reg size_3 : UInt, clock
reg source_3 : UInt, clock
reg address_2 : UInt, clock
node _T_1233 = eq(c_first, UInt<1>(0h0))
node _T_1234 = and(io.in.c.valid, _T_1233)
when _T_1234 :
node _T_1235 = eq(io.in.c.bits.opcode, opcode_3)
node _T_1236 = asUInt(reset)
node _T_1237 = eq(_T_1236, UInt<1>(0h0))
when _T_1237 :
node _T_1238 = eq(_T_1235, UInt<1>(0h0))
when _T_1238 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187
assert(clock, _T_1235, UInt<1>(0h1), "") : assert_187
node _T_1239 = eq(io.in.c.bits.param, param_3)
node _T_1240 = asUInt(reset)
node _T_1241 = eq(_T_1240, UInt<1>(0h0))
when _T_1241 :
node _T_1242 = eq(_T_1239, UInt<1>(0h0))
when _T_1242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188
assert(clock, _T_1239, UInt<1>(0h1), "") : assert_188
node _T_1243 = eq(io.in.c.bits.size, size_3)
node _T_1244 = asUInt(reset)
node _T_1245 = eq(_T_1244, UInt<1>(0h0))
when _T_1245 :
node _T_1246 = eq(_T_1243, UInt<1>(0h0))
when _T_1246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189
assert(clock, _T_1243, UInt<1>(0h1), "") : assert_189
node _T_1247 = eq(io.in.c.bits.source, source_3)
node _T_1248 = asUInt(reset)
node _T_1249 = eq(_T_1248, UInt<1>(0h0))
when _T_1249 :
node _T_1250 = eq(_T_1247, UInt<1>(0h0))
when _T_1250 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190
assert(clock, _T_1247, UInt<1>(0h1), "") : assert_190
node _T_1251 = eq(io.in.c.bits.address, address_2)
node _T_1252 = asUInt(reset)
node _T_1253 = eq(_T_1252, UInt<1>(0h0))
when _T_1253 :
node _T_1254 = eq(_T_1251, UInt<1>(0h0))
when _T_1254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191
assert(clock, _T_1251, UInt<1>(0h1), "") : assert_191
node _T_1255 = and(io.in.c.ready, io.in.c.valid)
node _T_1256 = and(_T_1255, c_first)
when _T_1256 :
connect opcode_3, io.in.c.bits.opcode
connect param_3, io.in.c.bits.param
connect size_3, io.in.c.bits.size
connect source_3, io.in.c.bits.source
connect address_2, io.in.c.bits.address
regreset inflight : UInt<5>, clock, reset, UInt<5>(0h0)
regreset inflight_opcodes : UInt<20>, clock, reset, UInt<20>(0h0)
regreset inflight_sizes : UInt<20>, clock, reset, UInt<20>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<5>
connect a_set, UInt<5>(0h0)
wire a_set_wo_ready : UInt<5>
connect a_set_wo_ready, UInt<5>(0h0)
wire a_opcodes_set : UInt<20>
connect a_opcodes_set, UInt<20>(0h0)
wire a_sizes_set : UInt<20>
connect a_sizes_set, UInt<20>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1257 = and(io.in.a.valid, a_first_1)
node _T_1258 = and(_T_1257, UInt<1>(0h1))
when _T_1258 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1259 = and(io.in.a.ready, io.in.a.valid)
node _T_1260 = and(_T_1259, a_first_1)
node _T_1261 = and(_T_1260, UInt<1>(0h1))
when _T_1261 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1262 = dshr(inflight, io.in.a.bits.source)
node _T_1263 = bits(_T_1262, 0, 0)
node _T_1264 = eq(_T_1263, UInt<1>(0h0))
node _T_1265 = asUInt(reset)
node _T_1266 = eq(_T_1265, UInt<1>(0h0))
when _T_1266 :
node _T_1267 = eq(_T_1264, UInt<1>(0h0))
when _T_1267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192
assert(clock, _T_1264, UInt<1>(0h1), "") : assert_192
wire d_clr : UInt<5>
connect d_clr, UInt<5>(0h0)
wire d_clr_wo_ready : UInt<5>
connect d_clr_wo_ready, UInt<5>(0h0)
wire d_opcodes_clr : UInt<20>
connect d_opcodes_clr, UInt<20>(0h0)
wire d_sizes_clr : UInt<20>
connect d_sizes_clr, UInt<20>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1268 = and(io.in.d.valid, d_first_1)
node _T_1269 = and(_T_1268, UInt<1>(0h1))
node _T_1270 = eq(d_release_ack, UInt<1>(0h0))
node _T_1271 = and(_T_1269, _T_1270)
when _T_1271 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1272 = and(io.in.d.ready, io.in.d.valid)
node _T_1273 = and(_T_1272, d_first_1)
node _T_1274 = and(_T_1273, UInt<1>(0h1))
node _T_1275 = eq(d_release_ack, UInt<1>(0h0))
node _T_1276 = and(_T_1274, _T_1275)
when _T_1276 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1277 = and(io.in.d.valid, d_first_1)
node _T_1278 = and(_T_1277, UInt<1>(0h1))
node _T_1279 = eq(d_release_ack, UInt<1>(0h0))
node _T_1280 = and(_T_1278, _T_1279)
when _T_1280 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1281 = dshr(inflight, io.in.d.bits.source)
node _T_1282 = bits(_T_1281, 0, 0)
node _T_1283 = or(_T_1282, same_cycle_resp)
node _T_1284 = asUInt(reset)
node _T_1285 = eq(_T_1284, UInt<1>(0h0))
when _T_1285 :
node _T_1286 = eq(_T_1283, UInt<1>(0h0))
when _T_1286 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193
assert(clock, _T_1283, UInt<1>(0h1), "") : assert_193
when same_cycle_resp :
node _T_1287 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1288 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1289 = or(_T_1287, _T_1288)
node _T_1290 = asUInt(reset)
node _T_1291 = eq(_T_1290, UInt<1>(0h0))
when _T_1291 :
node _T_1292 = eq(_T_1289, UInt<1>(0h0))
when _T_1292 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194
assert(clock, _T_1289, UInt<1>(0h1), "") : assert_194
node _T_1293 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1294 = asUInt(reset)
node _T_1295 = eq(_T_1294, UInt<1>(0h0))
when _T_1295 :
node _T_1296 = eq(_T_1293, UInt<1>(0h0))
when _T_1296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195
assert(clock, _T_1293, UInt<1>(0h1), "") : assert_195
else :
node _T_1297 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1298 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1299 = or(_T_1297, _T_1298)
node _T_1300 = asUInt(reset)
node _T_1301 = eq(_T_1300, UInt<1>(0h0))
when _T_1301 :
node _T_1302 = eq(_T_1299, UInt<1>(0h0))
when _T_1302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196
assert(clock, _T_1299, UInt<1>(0h1), "") : assert_196
node _T_1303 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1304 = asUInt(reset)
node _T_1305 = eq(_T_1304, UInt<1>(0h0))
when _T_1305 :
node _T_1306 = eq(_T_1303, UInt<1>(0h0))
when _T_1306 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197
assert(clock, _T_1303, UInt<1>(0h1), "") : assert_197
node _T_1307 = and(io.in.d.valid, d_first_1)
node _T_1308 = and(_T_1307, a_first_1)
node _T_1309 = and(_T_1308, io.in.a.valid)
node _T_1310 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1311 = and(_T_1309, _T_1310)
node _T_1312 = eq(d_release_ack, UInt<1>(0h0))
node _T_1313 = and(_T_1311, _T_1312)
when _T_1313 :
node _T_1314 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1315 = or(_T_1314, io.in.a.ready)
node _T_1316 = asUInt(reset)
node _T_1317 = eq(_T_1316, UInt<1>(0h0))
when _T_1317 :
node _T_1318 = eq(_T_1315, UInt<1>(0h0))
when _T_1318 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198
assert(clock, _T_1315, UInt<1>(0h1), "") : assert_198
node _T_1319 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1320 = orr(a_set_wo_ready)
node _T_1321 = eq(_T_1320, UInt<1>(0h0))
node _T_1322 = or(_T_1319, _T_1321)
node _T_1323 = asUInt(reset)
node _T_1324 = eq(_T_1323, UInt<1>(0h0))
when _T_1324 :
node _T_1325 = eq(_T_1322, UInt<1>(0h0))
when _T_1325 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199
assert(clock, _T_1322, UInt<1>(0h1), "") : assert_199
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_181
node _T_1326 = orr(inflight)
node _T_1327 = eq(_T_1326, UInt<1>(0h0))
node _T_1328 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1329 = or(_T_1327, _T_1328)
node _T_1330 = lt(watchdog, plusarg_reader.out)
node _T_1331 = or(_T_1329, _T_1330)
node _T_1332 = asUInt(reset)
node _T_1333 = eq(_T_1332, UInt<1>(0h0))
when _T_1333 :
node _T_1334 = eq(_T_1331, UInt<1>(0h0))
when _T_1334 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200
assert(clock, _T_1331, UInt<1>(0h1), "") : assert_200
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1335 = and(io.in.a.ready, io.in.a.valid)
node _T_1336 = and(io.in.d.ready, io.in.d.valid)
node _T_1337 = or(_T_1335, _T_1336)
when _T_1337 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<5>, clock, reset, UInt<5>(0h0)
regreset inflight_opcodes_1 : UInt<20>, clock, reset, UInt<20>(0h0)
regreset inflight_sizes_1 : UInt<20>, clock, reset, UInt<20>(0h0)
node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0)
node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4)
node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3)
node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0))
regreset c_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1))
node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1)
node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0))
node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1))
node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0))
node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3)
node c_first_done_1 = and(c_first_last_1, _c_first_T_1)
node _c_first_count_T_1 = not(c_first_counter1_1)
node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1)
when _c_first_T_1 :
node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1)
connect c_first_counter_1, _c_first_counter_T_1
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<5>
connect c_set, UInt<5>(0h0)
wire c_set_wo_ready : UInt<5>
connect c_set_wo_ready, UInt<5>(0h0)
wire c_opcodes_set : UInt<20>
connect c_opcodes_set, UInt<20>(0h0)
wire c_sizes_set : UInt<20>
connect c_sizes_set, UInt<20>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
node _T_1338 = and(io.in.c.valid, c_first_1)
node _T_1339 = bits(io.in.c.bits.opcode, 2, 2)
node _T_1340 = bits(io.in.c.bits.opcode, 1, 1)
node _T_1341 = and(_T_1339, _T_1340)
node _T_1342 = and(_T_1338, _T_1341)
when _T_1342 :
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
node _T_1343 = and(io.in.c.ready, io.in.c.valid)
node _T_1344 = and(_T_1343, c_first_1)
node _T_1345 = bits(io.in.c.bits.opcode, 2, 2)
node _T_1346 = bits(io.in.c.bits.opcode, 1, 1)
node _T_1347 = and(_T_1345, _T_1346)
node _T_1348 = and(_T_1344, _T_1347)
when _T_1348 :
node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set, _c_set_T
node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
node _T_1349 = dshr(inflight_1, io.in.c.bits.source)
node _T_1350 = bits(_T_1349, 0, 0)
node _T_1351 = eq(_T_1350, UInt<1>(0h0))
node _T_1352 = asUInt(reset)
node _T_1353 = eq(_T_1352, UInt<1>(0h0))
when _T_1353 :
node _T_1354 = eq(_T_1351, UInt<1>(0h0))
when _T_1354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201
assert(clock, _T_1351, UInt<1>(0h1), "") : assert_201
node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4))
node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<5>
connect d_clr_1, UInt<5>(0h0)
wire d_clr_wo_ready_1 : UInt<5>
connect d_clr_wo_ready_1, UInt<5>(0h0)
wire d_opcodes_clr_1 : UInt<20>
connect d_opcodes_clr_1, UInt<20>(0h0)
wire d_sizes_clr_1 : UInt<20>
connect d_sizes_clr_1, UInt<20>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1355 = and(io.in.d.valid, d_first_2)
node _T_1356 = and(_T_1355, UInt<1>(0h1))
node _T_1357 = and(_T_1356, d_release_ack_1)
when _T_1357 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1358 = and(io.in.d.ready, io.in.d.valid)
node _T_1359 = and(_T_1358, d_first_2)
node _T_1360 = and(_T_1359, UInt<1>(0h1))
node _T_1361 = and(_T_1360, d_release_ack_1)
when _T_1361 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1362 = and(io.in.d.valid, d_first_2)
node _T_1363 = and(_T_1362, UInt<1>(0h1))
node _T_1364 = and(_T_1363, d_release_ack_1)
when _T_1364 :
node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1)
node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1365 = dshr(inflight_1, io.in.d.bits.source)
node _T_1366 = bits(_T_1365, 0, 0)
node _T_1367 = or(_T_1366, same_cycle_resp_1)
node _T_1368 = asUInt(reset)
node _T_1369 = eq(_T_1368, UInt<1>(0h0))
when _T_1369 :
node _T_1370 = eq(_T_1367, UInt<1>(0h0))
when _T_1370 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202
assert(clock, _T_1367, UInt<1>(0h1), "") : assert_202
when same_cycle_resp_1 :
node _T_1371 = eq(io.in.d.bits.size, io.in.c.bits.size)
node _T_1372 = asUInt(reset)
node _T_1373 = eq(_T_1372, UInt<1>(0h0))
when _T_1373 :
node _T_1374 = eq(_T_1371, UInt<1>(0h0))
when _T_1374 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203
assert(clock, _T_1371, UInt<1>(0h1), "") : assert_203
else :
node _T_1375 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1376 = asUInt(reset)
node _T_1377 = eq(_T_1376, UInt<1>(0h0))
when _T_1377 :
node _T_1378 = eq(_T_1375, UInt<1>(0h0))
when _T_1378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204
assert(clock, _T_1375, UInt<1>(0h1), "") : assert_204
node _T_1379 = and(io.in.d.valid, d_first_2)
node _T_1380 = and(_T_1379, c_first_1)
node _T_1381 = and(_T_1380, io.in.c.valid)
node _T_1382 = eq(io.in.c.bits.source, io.in.d.bits.source)
node _T_1383 = and(_T_1381, _T_1382)
node _T_1384 = and(_T_1383, d_release_ack_1)
node _T_1385 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1386 = and(_T_1384, _T_1385)
when _T_1386 :
node _T_1387 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1388 = or(_T_1387, io.in.c.ready)
node _T_1389 = asUInt(reset)
node _T_1390 = eq(_T_1389, UInt<1>(0h0))
when _T_1390 :
node _T_1391 = eq(_T_1388, UInt<1>(0h0))
when _T_1391 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205
assert(clock, _T_1388, UInt<1>(0h1), "") : assert_205
node _T_1392 = orr(c_set_wo_ready)
when _T_1392 :
node _T_1393 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1394 = asUInt(reset)
node _T_1395 = eq(_T_1394, UInt<1>(0h0))
when _T_1395 :
node _T_1396 = eq(_T_1393, UInt<1>(0h0))
when _T_1396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206
assert(clock, _T_1393, UInt<1>(0h1), "") : assert_206
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_182
node _T_1397 = orr(inflight_1)
node _T_1398 = eq(_T_1397, UInt<1>(0h0))
node _T_1399 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1400 = or(_T_1398, _T_1399)
node _T_1401 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1402 = or(_T_1400, _T_1401)
node _T_1403 = asUInt(reset)
node _T_1404 = eq(_T_1403, UInt<1>(0h0))
when _T_1404 :
node _T_1405 = eq(_T_1402, UInt<1>(0h0))
when _T_1405 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207
assert(clock, _T_1402, UInt<1>(0h1), "") : assert_207
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
node _T_1406 = and(io.in.c.ready, io.in.c.valid)
node _T_1407 = and(io.in.d.ready, io.in.d.valid)
node _T_1408 = or(_T_1406, _T_1407)
when _T_1408 :
connect watchdog_1, UInt<1>(0h0)
regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0)
node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10)
node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3)
node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0))
regreset d_first_counter_3 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1))
node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1)
node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0))
node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1))
node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0))
node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7)
node d_first_done_3 = and(d_first_last_3, _d_first_T_3)
node _d_first_count_T_3 = not(d_first_counter1_3)
node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3)
when _d_first_T_3 :
node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3)
connect d_first_counter_3, _d_first_counter_T_3
wire d_set : UInt<8>
connect d_set, UInt<8>(0h0)
node _T_1409 = and(io.in.d.ready, io.in.d.valid)
node _T_1410 = and(_T_1409, d_first_3)
node _T_1411 = bits(io.in.d.bits.opcode, 2, 2)
node _T_1412 = bits(io.in.d.bits.opcode, 1, 1)
node _T_1413 = eq(_T_1412, UInt<1>(0h0))
node _T_1414 = and(_T_1411, _T_1413)
node _T_1415 = and(_T_1410, _T_1414)
when _T_1415 :
node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink)
connect d_set, _d_set_T
node _T_1416 = dshr(inflight_2, io.in.d.bits.sink)
node _T_1417 = bits(_T_1416, 0, 0)
node _T_1418 = eq(_T_1417, UInt<1>(0h0))
node _T_1419 = asUInt(reset)
node _T_1420 = eq(_T_1419, UInt<1>(0h0))
when _T_1420 :
node _T_1421 = eq(_T_1418, UInt<1>(0h0))
when _T_1421 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208
assert(clock, _T_1418, UInt<1>(0h1), "") : assert_208
wire e_clr : UInt<8>
connect e_clr, UInt<8>(0h0)
node _T_1422 = and(io.in.e.ready, io.in.e.valid)
node _T_1423 = and(_T_1422, UInt<1>(0h1))
node _T_1424 = and(_T_1423, UInt<1>(0h1))
when _T_1424 :
node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink)
connect e_clr, _e_clr_T
node _T_1425 = or(d_set, inflight_2)
node _T_1426 = dshr(_T_1425, io.in.e.bits.sink)
node _T_1427 = bits(_T_1426, 0, 0)
node _T_1428 = asUInt(reset)
node _T_1429 = eq(_T_1428, UInt<1>(0h0))
when _T_1429 :
node _T_1430 = eq(_T_1427, UInt<1>(0h0))
when _T_1430 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209
assert(clock, _T_1427, UInt<1>(0h1), "") : assert_209
node _inflight_T_6 = or(inflight_2, d_set)
node _inflight_T_7 = not(e_clr)
node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7)
connect inflight_2, _inflight_T_8
extmodule plusarg_reader_183 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_184 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_59( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire [12:0] _GEN_0 = {10'h0, io_in_c_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [2:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [2:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35]
reg [2:0] c_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [2:0] size_3; // @[Monitor.scala:517:22]
reg [2:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [4:0] inflight; // @[Monitor.scala:614:27]
reg [19:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [19:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [7:0] _GEN_1 = {5'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [7:0] _GEN_4 = {5'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [4:0] inflight_1; // @[Monitor.scala:726:35]
reg [19:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] c_first_counter_1; // @[Edges.scala:229:27]
wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}]
wire [7:0] _GEN_6 = {5'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
reg [7:0] inflight_2; // @[Monitor.scala:828:27]
reg [2:0] d_first_counter_3; // @[Edges.scala:229:27]
wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35]
wire [7:0] _GEN_9 = {5'h0, io_in_d_bits_sink}; // @[OneHot.scala:58:35]
wire [7:0] d_set = _GEN_8 ? 8'h1 << _GEN_9 : 8'h0; // @[OneHot.scala:58:35]
wire [7:0] _GEN_10 = {5'h0, io_in_e_bits_sink}; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to this FIRRTL code module DTLB_12 :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip kill : UInt<1>}
invalidate io.ptw.customCSRs.csrs[0].sdata
invalidate io.ptw.customCSRs.csrs[0].set
invalidate io.ptw.customCSRs.csrs[0].stall
invalidate io.ptw.customCSRs.csrs[0].value
invalidate io.ptw.customCSRs.csrs[0].wdata
invalidate io.ptw.customCSRs.csrs[0].wen
invalidate io.ptw.customCSRs.csrs[0].ren
invalidate io.ptw.customCSRs.csrs[1].sdata
invalidate io.ptw.customCSRs.csrs[1].set
invalidate io.ptw.customCSRs.csrs[1].stall
invalidate io.ptw.customCSRs.csrs[1].value
invalidate io.ptw.customCSRs.csrs[1].wdata
invalidate io.ptw.customCSRs.csrs[1].wen
invalidate io.ptw.customCSRs.csrs[1].ren
invalidate io.ptw.customCSRs.csrs[2].sdata
invalidate io.ptw.customCSRs.csrs[2].set
invalidate io.ptw.customCSRs.csrs[2].stall
invalidate io.ptw.customCSRs.csrs[2].value
invalidate io.ptw.customCSRs.csrs[2].wdata
invalidate io.ptw.customCSRs.csrs[2].wen
invalidate io.ptw.customCSRs.csrs[2].ren
invalidate io.ptw.customCSRs.csrs[3].sdata
invalidate io.ptw.customCSRs.csrs[3].set
invalidate io.ptw.customCSRs.csrs[3].stall
invalidate io.ptw.customCSRs.csrs[3].value
invalidate io.ptw.customCSRs.csrs[3].wdata
invalidate io.ptw.customCSRs.csrs[3].wen
invalidate io.ptw.customCSRs.csrs[3].ren
node vpn = bits(io.req.bits.vaddr, 38, 12)
reg sectored_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[4], valid : UInt<1>[4]}[8][1], clock
reg superpage_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[4], clock
reg special_entry : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}, clock
regreset state : UInt<2>, clock, reset, UInt<2>(0h0)
reg r_refill_tag : UInt<27>, clock
reg r_superpage_repl_addr : UInt<2>, clock
reg r_sectored_repl_addr : UInt<3>, clock
reg r_sectored_hit : { valid : UInt<1>, bits : UInt<3>}, clock
reg r_superpage_hit : { valid : UInt<1>, bits : UInt<2>}, clock
reg r_vstage1_en : UInt<1>, clock
reg r_stage2_en : UInt<1>, clock
reg r_need_gpa : UInt<1>, clock
reg r_gpa_valid : UInt<1>, clock
reg r_gpa : UInt<39>, clock
reg r_gpa_vpn : UInt<27>, clock
reg r_gpa_is_pte : UInt<1>, clock
node priv_v = and(UInt<1>(0h0), io.req.bits.v)
node priv_s = bits(io.req.bits.prv, 0, 0)
node priv_uses_vm = leq(io.req.bits.prv, UInt<1>(0h1))
node satp = mux(priv_v, io.ptw.vsatp, io.ptw.ptbr)
node _stage1_en_T = bits(satp.mode, 3, 3)
node stage1_en = and(UInt<1>(0h1), _stage1_en_T)
node _vstage1_en_T = and(UInt<1>(0h0), priv_v)
node _vstage1_en_T_1 = bits(io.ptw.vsatp.mode, 3, 3)
node vstage1_en = and(_vstage1_en_T, _vstage1_en_T_1)
node _stage2_en_T = and(UInt<1>(0h0), priv_v)
node _stage2_en_T_1 = bits(io.ptw.hgatp.mode, 3, 3)
node stage2_en = and(_stage2_en_T, _stage2_en_T_1)
node _vm_enabled_T = or(stage1_en, stage2_en)
node _vm_enabled_T_1 = and(_vm_enabled_T, priv_uses_vm)
node _vm_enabled_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0))
node vm_enabled = and(_vm_enabled_T_1, _vm_enabled_T_2)
regreset v_entries_use_stage1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _vsatp_mode_mismatch_T = neq(vstage1_en, v_entries_use_stage1)
node _vsatp_mode_mismatch_T_1 = and(priv_v, _vsatp_mode_mismatch_T)
node _vsatp_mode_mismatch_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0))
node vsatp_mode_mismatch = and(_vsatp_mode_mismatch_T_1, _vsatp_mode_mismatch_T_2)
node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0)
node do_refill = and(UInt<1>(0h1), io.ptw.resp.valid)
node _invalidate_refill_T = eq(state, UInt<2>(0h1))
node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3))
node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1)
node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid)
node _mpu_ppn_T = and(vm_enabled, UInt<1>(0h1))
wire _mpu_ppn_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _mpu_ppn_WIRE_1 : UInt<42>
connect _mpu_ppn_WIRE_1, special_entry.data[0]
node _mpu_ppn_T_1 = bits(_mpu_ppn_WIRE_1, 0, 0)
connect _mpu_ppn_WIRE.fragmented_superpage, _mpu_ppn_T_1
node _mpu_ppn_T_2 = bits(_mpu_ppn_WIRE_1, 1, 1)
connect _mpu_ppn_WIRE.c, _mpu_ppn_T_2
node _mpu_ppn_T_3 = bits(_mpu_ppn_WIRE_1, 2, 2)
connect _mpu_ppn_WIRE.eff, _mpu_ppn_T_3
node _mpu_ppn_T_4 = bits(_mpu_ppn_WIRE_1, 3, 3)
connect _mpu_ppn_WIRE.paa, _mpu_ppn_T_4
node _mpu_ppn_T_5 = bits(_mpu_ppn_WIRE_1, 4, 4)
connect _mpu_ppn_WIRE.pal, _mpu_ppn_T_5
node _mpu_ppn_T_6 = bits(_mpu_ppn_WIRE_1, 5, 5)
connect _mpu_ppn_WIRE.ppp, _mpu_ppn_T_6
node _mpu_ppn_T_7 = bits(_mpu_ppn_WIRE_1, 6, 6)
connect _mpu_ppn_WIRE.pr, _mpu_ppn_T_7
node _mpu_ppn_T_8 = bits(_mpu_ppn_WIRE_1, 7, 7)
connect _mpu_ppn_WIRE.px, _mpu_ppn_T_8
node _mpu_ppn_T_9 = bits(_mpu_ppn_WIRE_1, 8, 8)
connect _mpu_ppn_WIRE.pw, _mpu_ppn_T_9
node _mpu_ppn_T_10 = bits(_mpu_ppn_WIRE_1, 9, 9)
connect _mpu_ppn_WIRE.hr, _mpu_ppn_T_10
node _mpu_ppn_T_11 = bits(_mpu_ppn_WIRE_1, 10, 10)
connect _mpu_ppn_WIRE.hx, _mpu_ppn_T_11
node _mpu_ppn_T_12 = bits(_mpu_ppn_WIRE_1, 11, 11)
connect _mpu_ppn_WIRE.hw, _mpu_ppn_T_12
node _mpu_ppn_T_13 = bits(_mpu_ppn_WIRE_1, 12, 12)
connect _mpu_ppn_WIRE.sr, _mpu_ppn_T_13
node _mpu_ppn_T_14 = bits(_mpu_ppn_WIRE_1, 13, 13)
connect _mpu_ppn_WIRE.sx, _mpu_ppn_T_14
node _mpu_ppn_T_15 = bits(_mpu_ppn_WIRE_1, 14, 14)
connect _mpu_ppn_WIRE.sw, _mpu_ppn_T_15
node _mpu_ppn_T_16 = bits(_mpu_ppn_WIRE_1, 15, 15)
connect _mpu_ppn_WIRE.gf, _mpu_ppn_T_16
node _mpu_ppn_T_17 = bits(_mpu_ppn_WIRE_1, 16, 16)
connect _mpu_ppn_WIRE.pf, _mpu_ppn_T_17
node _mpu_ppn_T_18 = bits(_mpu_ppn_WIRE_1, 17, 17)
connect _mpu_ppn_WIRE.ae_stage2, _mpu_ppn_T_18
node _mpu_ppn_T_19 = bits(_mpu_ppn_WIRE_1, 18, 18)
connect _mpu_ppn_WIRE.ae_final, _mpu_ppn_T_19
node _mpu_ppn_T_20 = bits(_mpu_ppn_WIRE_1, 19, 19)
connect _mpu_ppn_WIRE.ae_ptw, _mpu_ppn_T_20
node _mpu_ppn_T_21 = bits(_mpu_ppn_WIRE_1, 20, 20)
connect _mpu_ppn_WIRE.g, _mpu_ppn_T_21
node _mpu_ppn_T_22 = bits(_mpu_ppn_WIRE_1, 21, 21)
connect _mpu_ppn_WIRE.u, _mpu_ppn_T_22
node _mpu_ppn_T_23 = bits(_mpu_ppn_WIRE_1, 41, 22)
connect _mpu_ppn_WIRE.ppn, _mpu_ppn_T_23
inst mpu_ppn_barrier of OptimizationBarrier_TLBEntryData_252
connect mpu_ppn_barrier.clock, clock
connect mpu_ppn_barrier.reset, reset
connect mpu_ppn_barrier.io.x.fragmented_superpage, _mpu_ppn_WIRE.fragmented_superpage
connect mpu_ppn_barrier.io.x.c, _mpu_ppn_WIRE.c
connect mpu_ppn_barrier.io.x.eff, _mpu_ppn_WIRE.eff
connect mpu_ppn_barrier.io.x.paa, _mpu_ppn_WIRE.paa
connect mpu_ppn_barrier.io.x.pal, _mpu_ppn_WIRE.pal
connect mpu_ppn_barrier.io.x.ppp, _mpu_ppn_WIRE.ppp
connect mpu_ppn_barrier.io.x.pr, _mpu_ppn_WIRE.pr
connect mpu_ppn_barrier.io.x.px, _mpu_ppn_WIRE.px
connect mpu_ppn_barrier.io.x.pw, _mpu_ppn_WIRE.pw
connect mpu_ppn_barrier.io.x.hr, _mpu_ppn_WIRE.hr
connect mpu_ppn_barrier.io.x.hx, _mpu_ppn_WIRE.hx
connect mpu_ppn_barrier.io.x.hw, _mpu_ppn_WIRE.hw
connect mpu_ppn_barrier.io.x.sr, _mpu_ppn_WIRE.sr
connect mpu_ppn_barrier.io.x.sx, _mpu_ppn_WIRE.sx
connect mpu_ppn_barrier.io.x.sw, _mpu_ppn_WIRE.sw
connect mpu_ppn_barrier.io.x.gf, _mpu_ppn_WIRE.gf
connect mpu_ppn_barrier.io.x.pf, _mpu_ppn_WIRE.pf
connect mpu_ppn_barrier.io.x.ae_stage2, _mpu_ppn_WIRE.ae_stage2
connect mpu_ppn_barrier.io.x.ae_final, _mpu_ppn_WIRE.ae_final
connect mpu_ppn_barrier.io.x.ae_ptw, _mpu_ppn_WIRE.ae_ptw
connect mpu_ppn_barrier.io.x.g, _mpu_ppn_WIRE.g
connect mpu_ppn_barrier.io.x.u, _mpu_ppn_WIRE.u
connect mpu_ppn_barrier.io.x.ppn, _mpu_ppn_WIRE.ppn
node mpu_ppn_res = shr(mpu_ppn_barrier.io.y.ppn, 18)
node _mpu_ppn_ignore_T = lt(special_entry.level, UInt<1>(0h1))
node mpu_ppn_ignore = or(_mpu_ppn_ignore_T, UInt<1>(0h0))
node _mpu_ppn_T_24 = mux(mpu_ppn_ignore, vpn, UInt<1>(0h0))
node _mpu_ppn_T_25 = or(_mpu_ppn_T_24, mpu_ppn_barrier.io.y.ppn)
node _mpu_ppn_T_26 = bits(_mpu_ppn_T_25, 17, 9)
node _mpu_ppn_T_27 = cat(mpu_ppn_res, _mpu_ppn_T_26)
node _mpu_ppn_ignore_T_1 = lt(special_entry.level, UInt<2>(0h2))
node mpu_ppn_ignore_1 = or(_mpu_ppn_ignore_T_1, UInt<1>(0h0))
node _mpu_ppn_T_28 = mux(mpu_ppn_ignore_1, vpn, UInt<1>(0h0))
node _mpu_ppn_T_29 = or(_mpu_ppn_T_28, mpu_ppn_barrier.io.y.ppn)
node _mpu_ppn_T_30 = bits(_mpu_ppn_T_29, 8, 0)
node _mpu_ppn_T_31 = cat(_mpu_ppn_T_27, _mpu_ppn_T_30)
node _mpu_ppn_T_32 = shr(io.req.bits.vaddr, 12)
node _mpu_ppn_T_33 = mux(_mpu_ppn_T, _mpu_ppn_T_31, _mpu_ppn_T_32)
node mpu_ppn = mux(do_refill, refill_ppn, _mpu_ppn_T_33)
node _mpu_physaddr_T = bits(io.req.bits.vaddr, 11, 0)
node mpu_physaddr = cat(mpu_ppn, _mpu_physaddr_T)
node _mpu_priv_T = or(do_refill, io.req.bits.passthrough)
node _mpu_priv_T_1 = and(UInt<1>(0h1), _mpu_priv_T)
node _mpu_priv_T_2 = cat(io.ptw.status.debug, io.req.bits.prv)
node mpu_priv = mux(_mpu_priv_T_1, UInt<1>(0h1), _mpu_priv_T_2)
inst pmp of PMPChecker_s3_12
connect pmp.clock, clock
connect pmp.reset, reset
connect pmp.io.addr, mpu_physaddr
connect pmp.io.size, io.req.bits.size
connect pmp.io.pmp[0].mask, io.ptw.pmp[0].mask
connect pmp.io.pmp[0].addr, io.ptw.pmp[0].addr
connect pmp.io.pmp[0].cfg.r, io.ptw.pmp[0].cfg.r
connect pmp.io.pmp[0].cfg.w, io.ptw.pmp[0].cfg.w
connect pmp.io.pmp[0].cfg.x, io.ptw.pmp[0].cfg.x
connect pmp.io.pmp[0].cfg.a, io.ptw.pmp[0].cfg.a
connect pmp.io.pmp[0].cfg.res, io.ptw.pmp[0].cfg.res
connect pmp.io.pmp[0].cfg.l, io.ptw.pmp[0].cfg.l
connect pmp.io.pmp[1].mask, io.ptw.pmp[1].mask
connect pmp.io.pmp[1].addr, io.ptw.pmp[1].addr
connect pmp.io.pmp[1].cfg.r, io.ptw.pmp[1].cfg.r
connect pmp.io.pmp[1].cfg.w, io.ptw.pmp[1].cfg.w
connect pmp.io.pmp[1].cfg.x, io.ptw.pmp[1].cfg.x
connect pmp.io.pmp[1].cfg.a, io.ptw.pmp[1].cfg.a
connect pmp.io.pmp[1].cfg.res, io.ptw.pmp[1].cfg.res
connect pmp.io.pmp[1].cfg.l, io.ptw.pmp[1].cfg.l
connect pmp.io.pmp[2].mask, io.ptw.pmp[2].mask
connect pmp.io.pmp[2].addr, io.ptw.pmp[2].addr
connect pmp.io.pmp[2].cfg.r, io.ptw.pmp[2].cfg.r
connect pmp.io.pmp[2].cfg.w, io.ptw.pmp[2].cfg.w
connect pmp.io.pmp[2].cfg.x, io.ptw.pmp[2].cfg.x
connect pmp.io.pmp[2].cfg.a, io.ptw.pmp[2].cfg.a
connect pmp.io.pmp[2].cfg.res, io.ptw.pmp[2].cfg.res
connect pmp.io.pmp[2].cfg.l, io.ptw.pmp[2].cfg.l
connect pmp.io.pmp[3].mask, io.ptw.pmp[3].mask
connect pmp.io.pmp[3].addr, io.ptw.pmp[3].addr
connect pmp.io.pmp[3].cfg.r, io.ptw.pmp[3].cfg.r
connect pmp.io.pmp[3].cfg.w, io.ptw.pmp[3].cfg.w
connect pmp.io.pmp[3].cfg.x, io.ptw.pmp[3].cfg.x
connect pmp.io.pmp[3].cfg.a, io.ptw.pmp[3].cfg.a
connect pmp.io.pmp[3].cfg.res, io.ptw.pmp[3].cfg.res
connect pmp.io.pmp[3].cfg.l, io.ptw.pmp[3].cfg.l
connect pmp.io.pmp[4].mask, io.ptw.pmp[4].mask
connect pmp.io.pmp[4].addr, io.ptw.pmp[4].addr
connect pmp.io.pmp[4].cfg.r, io.ptw.pmp[4].cfg.r
connect pmp.io.pmp[4].cfg.w, io.ptw.pmp[4].cfg.w
connect pmp.io.pmp[4].cfg.x, io.ptw.pmp[4].cfg.x
connect pmp.io.pmp[4].cfg.a, io.ptw.pmp[4].cfg.a
connect pmp.io.pmp[4].cfg.res, io.ptw.pmp[4].cfg.res
connect pmp.io.pmp[4].cfg.l, io.ptw.pmp[4].cfg.l
connect pmp.io.pmp[5].mask, io.ptw.pmp[5].mask
connect pmp.io.pmp[5].addr, io.ptw.pmp[5].addr
connect pmp.io.pmp[5].cfg.r, io.ptw.pmp[5].cfg.r
connect pmp.io.pmp[5].cfg.w, io.ptw.pmp[5].cfg.w
connect pmp.io.pmp[5].cfg.x, io.ptw.pmp[5].cfg.x
connect pmp.io.pmp[5].cfg.a, io.ptw.pmp[5].cfg.a
connect pmp.io.pmp[5].cfg.res, io.ptw.pmp[5].cfg.res
connect pmp.io.pmp[5].cfg.l, io.ptw.pmp[5].cfg.l
connect pmp.io.pmp[6].mask, io.ptw.pmp[6].mask
connect pmp.io.pmp[6].addr, io.ptw.pmp[6].addr
connect pmp.io.pmp[6].cfg.r, io.ptw.pmp[6].cfg.r
connect pmp.io.pmp[6].cfg.w, io.ptw.pmp[6].cfg.w
connect pmp.io.pmp[6].cfg.x, io.ptw.pmp[6].cfg.x
connect pmp.io.pmp[6].cfg.a, io.ptw.pmp[6].cfg.a
connect pmp.io.pmp[6].cfg.res, io.ptw.pmp[6].cfg.res
connect pmp.io.pmp[6].cfg.l, io.ptw.pmp[6].cfg.l
connect pmp.io.pmp[7].mask, io.ptw.pmp[7].mask
connect pmp.io.pmp[7].addr, io.ptw.pmp[7].addr
connect pmp.io.pmp[7].cfg.r, io.ptw.pmp[7].cfg.r
connect pmp.io.pmp[7].cfg.w, io.ptw.pmp[7].cfg.w
connect pmp.io.pmp[7].cfg.x, io.ptw.pmp[7].cfg.x
connect pmp.io.pmp[7].cfg.a, io.ptw.pmp[7].cfg.a
connect pmp.io.pmp[7].cfg.res, io.ptw.pmp[7].cfg.res
connect pmp.io.pmp[7].cfg.l, io.ptw.pmp[7].cfg.l
connect pmp.io.prv, mpu_priv
inst pma of PMAChecker_18
connect pma.clock, clock
connect pma.reset, reset
connect pma.io.paddr, mpu_physaddr
node cacheable = and(pma.io.resp.cacheable, UInt<1>(0h1))
node _homogeneous_T = xor(mpu_physaddr, UInt<1>(0h0))
node _homogeneous_T_1 = cvt(_homogeneous_T)
node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<14>(0h2000)))
node _homogeneous_T_3 = asSInt(_homogeneous_T_2)
node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0)))
node _homogeneous_T_5 = xor(mpu_physaddr, UInt<14>(0h3000))
node _homogeneous_T_6 = cvt(_homogeneous_T_5)
node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<13>(0h1000)))
node _homogeneous_T_8 = asSInt(_homogeneous_T_7)
node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0)))
node _homogeneous_T_10 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_11 = cvt(_homogeneous_T_10)
node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<17>(0h10000)))
node _homogeneous_T_13 = asSInt(_homogeneous_T_12)
node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0)))
node _homogeneous_T_15 = xor(mpu_physaddr, UInt<21>(0h100000))
node _homogeneous_T_16 = cvt(_homogeneous_T_15)
node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<18>(0h2f000)))
node _homogeneous_T_18 = asSInt(_homogeneous_T_17)
node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0)))
node _homogeneous_T_20 = xor(mpu_physaddr, UInt<26>(0h2000000))
node _homogeneous_T_21 = cvt(_homogeneous_T_20)
node _homogeneous_T_22 = and(_homogeneous_T_21, asSInt(UInt<17>(0h10000)))
node _homogeneous_T_23 = asSInt(_homogeneous_T_22)
node _homogeneous_T_24 = eq(_homogeneous_T_23, asSInt(UInt<1>(0h0)))
node _homogeneous_T_25 = xor(mpu_physaddr, UInt<26>(0h2010000))
node _homogeneous_T_26 = cvt(_homogeneous_T_25)
node _homogeneous_T_27 = and(_homogeneous_T_26, asSInt(UInt<13>(0h1000)))
node _homogeneous_T_28 = asSInt(_homogeneous_T_27)
node _homogeneous_T_29 = eq(_homogeneous_T_28, asSInt(UInt<1>(0h0)))
node _homogeneous_T_30 = xor(mpu_physaddr, UInt<28>(0h8000000))
node _homogeneous_T_31 = cvt(_homogeneous_T_30)
node _homogeneous_T_32 = and(_homogeneous_T_31, asSInt(UInt<17>(0h10000)))
node _homogeneous_T_33 = asSInt(_homogeneous_T_32)
node _homogeneous_T_34 = eq(_homogeneous_T_33, asSInt(UInt<1>(0h0)))
node _homogeneous_T_35 = xor(mpu_physaddr, UInt<28>(0hc000000))
node _homogeneous_T_36 = cvt(_homogeneous_T_35)
node _homogeneous_T_37 = and(_homogeneous_T_36, asSInt(UInt<27>(0h4000000)))
node _homogeneous_T_38 = asSInt(_homogeneous_T_37)
node _homogeneous_T_39 = eq(_homogeneous_T_38, asSInt(UInt<1>(0h0)))
node _homogeneous_T_40 = xor(mpu_physaddr, UInt<29>(0h10020000))
node _homogeneous_T_41 = cvt(_homogeneous_T_40)
node _homogeneous_T_42 = and(_homogeneous_T_41, asSInt(UInt<13>(0h1000)))
node _homogeneous_T_43 = asSInt(_homogeneous_T_42)
node _homogeneous_T_44 = eq(_homogeneous_T_43, asSInt(UInt<1>(0h0)))
node _homogeneous_T_45 = xor(mpu_physaddr, UInt<32>(0h80000000))
node _homogeneous_T_46 = cvt(_homogeneous_T_45)
node _homogeneous_T_47 = and(_homogeneous_T_46, asSInt(UInt<29>(0h10000000)))
node _homogeneous_T_48 = asSInt(_homogeneous_T_47)
node _homogeneous_T_49 = eq(_homogeneous_T_48, asSInt(UInt<1>(0h0)))
node _homogeneous_T_50 = or(UInt<1>(0h0), _homogeneous_T_4)
node _homogeneous_T_51 = or(_homogeneous_T_50, _homogeneous_T_9)
node _homogeneous_T_52 = or(_homogeneous_T_51, _homogeneous_T_14)
node _homogeneous_T_53 = or(_homogeneous_T_52, _homogeneous_T_19)
node _homogeneous_T_54 = or(_homogeneous_T_53, _homogeneous_T_24)
node _homogeneous_T_55 = or(_homogeneous_T_54, _homogeneous_T_29)
node _homogeneous_T_56 = or(_homogeneous_T_55, _homogeneous_T_34)
node _homogeneous_T_57 = or(_homogeneous_T_56, _homogeneous_T_39)
node _homogeneous_T_58 = or(_homogeneous_T_57, _homogeneous_T_44)
node homogeneous = or(_homogeneous_T_58, _homogeneous_T_49)
node _homogeneous_T_59 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _homogeneous_T_60 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_61 = cvt(_homogeneous_T_60)
node _homogeneous_T_62 = and(_homogeneous_T_61, asSInt(UInt<33>(0h8a110000)))
node _homogeneous_T_63 = asSInt(_homogeneous_T_62)
node _homogeneous_T_64 = eq(_homogeneous_T_63, asSInt(UInt<1>(0h0)))
node _homogeneous_T_65 = or(UInt<1>(0h0), _homogeneous_T_64)
node _homogeneous_T_66 = eq(_homogeneous_T_65, UInt<1>(0h0))
node _homogeneous_T_67 = xor(mpu_physaddr, UInt<1>(0h0))
node _homogeneous_T_68 = cvt(_homogeneous_T_67)
node _homogeneous_T_69 = and(_homogeneous_T_68, asSInt(UInt<33>(0h9e113000)))
node _homogeneous_T_70 = asSInt(_homogeneous_T_69)
node _homogeneous_T_71 = eq(_homogeneous_T_70, asSInt(UInt<1>(0h0)))
node _homogeneous_T_72 = xor(mpu_physaddr, UInt<14>(0h3000))
node _homogeneous_T_73 = cvt(_homogeneous_T_72)
node _homogeneous_T_74 = and(_homogeneous_T_73, asSInt(UInt<33>(0h9e113000)))
node _homogeneous_T_75 = asSInt(_homogeneous_T_74)
node _homogeneous_T_76 = eq(_homogeneous_T_75, asSInt(UInt<1>(0h0)))
node _homogeneous_T_77 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_78 = cvt(_homogeneous_T_77)
node _homogeneous_T_79 = and(_homogeneous_T_78, asSInt(UInt<33>(0h9e110000)))
node _homogeneous_T_80 = asSInt(_homogeneous_T_79)
node _homogeneous_T_81 = eq(_homogeneous_T_80, asSInt(UInt<1>(0h0)))
node _homogeneous_T_82 = xor(mpu_physaddr, UInt<28>(0h8000000))
node _homogeneous_T_83 = cvt(_homogeneous_T_82)
node _homogeneous_T_84 = and(_homogeneous_T_83, asSInt(UInt<33>(0h9e110000)))
node _homogeneous_T_85 = asSInt(_homogeneous_T_84)
node _homogeneous_T_86 = eq(_homogeneous_T_85, asSInt(UInt<1>(0h0)))
node _homogeneous_T_87 = xor(mpu_physaddr, UInt<32>(0h80000000))
node _homogeneous_T_88 = cvt(_homogeneous_T_87)
node _homogeneous_T_89 = and(_homogeneous_T_88, asSInt(UInt<33>(0h90000000)))
node _homogeneous_T_90 = asSInt(_homogeneous_T_89)
node _homogeneous_T_91 = eq(_homogeneous_T_90, asSInt(UInt<1>(0h0)))
node _homogeneous_T_92 = or(UInt<1>(0h0), _homogeneous_T_71)
node _homogeneous_T_93 = or(_homogeneous_T_92, _homogeneous_T_76)
node _homogeneous_T_94 = or(_homogeneous_T_93, _homogeneous_T_81)
node _homogeneous_T_95 = or(_homogeneous_T_94, _homogeneous_T_86)
node _homogeneous_T_96 = or(_homogeneous_T_95, _homogeneous_T_91)
node _homogeneous_T_97 = xor(mpu_physaddr, UInt<28>(0h8000000))
node _homogeneous_T_98 = cvt(_homogeneous_T_97)
node _homogeneous_T_99 = and(_homogeneous_T_98, asSInt(UInt<33>(0h8e000000)))
node _homogeneous_T_100 = asSInt(_homogeneous_T_99)
node _homogeneous_T_101 = eq(_homogeneous_T_100, asSInt(UInt<1>(0h0)))
node _homogeneous_T_102 = xor(mpu_physaddr, UInt<32>(0h80000000))
node _homogeneous_T_103 = cvt(_homogeneous_T_102)
node _homogeneous_T_104 = and(_homogeneous_T_103, asSInt(UInt<33>(0h80000000)))
node _homogeneous_T_105 = asSInt(_homogeneous_T_104)
node _homogeneous_T_106 = eq(_homogeneous_T_105, asSInt(UInt<1>(0h0)))
node _homogeneous_T_107 = or(UInt<1>(0h0), _homogeneous_T_101)
node _homogeneous_T_108 = or(_homogeneous_T_107, _homogeneous_T_106)
node _homogeneous_T_109 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_110 = cvt(_homogeneous_T_109)
node _homogeneous_T_111 = and(_homogeneous_T_110, asSInt(UInt<33>(0h8a110000)))
node _homogeneous_T_112 = asSInt(_homogeneous_T_111)
node _homogeneous_T_113 = eq(_homogeneous_T_112, asSInt(UInt<1>(0h0)))
node _homogeneous_T_114 = or(UInt<1>(0h0), _homogeneous_T_113)
node _homogeneous_T_115 = eq(_homogeneous_T_114, UInt<1>(0h0))
node _homogeneous_T_116 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_117 = cvt(_homogeneous_T_116)
node _homogeneous_T_118 = and(_homogeneous_T_117, asSInt(UInt<33>(0h8a110000)))
node _homogeneous_T_119 = asSInt(_homogeneous_T_118)
node _homogeneous_T_120 = eq(_homogeneous_T_119, asSInt(UInt<1>(0h0)))
node _homogeneous_T_121 = or(UInt<1>(0h0), _homogeneous_T_120)
node _homogeneous_T_122 = eq(_homogeneous_T_121, UInt<1>(0h0))
node _deny_access_to_debug_T = leq(mpu_priv, UInt<2>(0h3))
node _deny_access_to_debug_T_1 = xor(mpu_physaddr, UInt<1>(0h0))
node _deny_access_to_debug_T_2 = cvt(_deny_access_to_debug_T_1)
node _deny_access_to_debug_T_3 = and(_deny_access_to_debug_T_2, asSInt(UInt<13>(0h1000)))
node _deny_access_to_debug_T_4 = asSInt(_deny_access_to_debug_T_3)
node _deny_access_to_debug_T_5 = eq(_deny_access_to_debug_T_4, asSInt(UInt<1>(0h0)))
node deny_access_to_debug = and(_deny_access_to_debug_T, _deny_access_to_debug_T_5)
node _prot_r_T = eq(deny_access_to_debug, UInt<1>(0h0))
node _prot_r_T_1 = and(pma.io.resp.r, _prot_r_T)
node prot_r = and(_prot_r_T_1, pmp.io.r)
node _prot_w_T = eq(deny_access_to_debug, UInt<1>(0h0))
node _prot_w_T_1 = and(pma.io.resp.w, _prot_w_T)
node prot_w = and(_prot_w_T_1, pmp.io.w)
node _prot_x_T = eq(deny_access_to_debug, UInt<1>(0h0))
node _prot_x_T_1 = and(pma.io.resp.x, _prot_x_T)
node prot_x = and(_prot_x_T_1, pmp.io.x)
node _sector_hits_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1])
node _sector_hits_T_1 = or(_sector_hits_T, sectored_entries[0][0].valid[2])
node _sector_hits_T_2 = or(_sector_hits_T_1, sectored_entries[0][0].valid[3])
node _sector_hits_T_3 = xor(sectored_entries[0][0].tag_vpn, vpn)
node _sector_hits_T_4 = shr(_sector_hits_T_3, 2)
node _sector_hits_T_5 = eq(_sector_hits_T_4, UInt<1>(0h0))
node _sector_hits_T_6 = eq(sectored_entries[0][0].tag_v, priv_v)
node _sector_hits_T_7 = and(_sector_hits_T_5, _sector_hits_T_6)
node sector_hits_0 = and(_sector_hits_T_2, _sector_hits_T_7)
node _sector_hits_T_8 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1])
node _sector_hits_T_9 = or(_sector_hits_T_8, sectored_entries[0][1].valid[2])
node _sector_hits_T_10 = or(_sector_hits_T_9, sectored_entries[0][1].valid[3])
node _sector_hits_T_11 = xor(sectored_entries[0][1].tag_vpn, vpn)
node _sector_hits_T_12 = shr(_sector_hits_T_11, 2)
node _sector_hits_T_13 = eq(_sector_hits_T_12, UInt<1>(0h0))
node _sector_hits_T_14 = eq(sectored_entries[0][1].tag_v, priv_v)
node _sector_hits_T_15 = and(_sector_hits_T_13, _sector_hits_T_14)
node sector_hits_1 = and(_sector_hits_T_10, _sector_hits_T_15)
node _sector_hits_T_16 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1])
node _sector_hits_T_17 = or(_sector_hits_T_16, sectored_entries[0][2].valid[2])
node _sector_hits_T_18 = or(_sector_hits_T_17, sectored_entries[0][2].valid[3])
node _sector_hits_T_19 = xor(sectored_entries[0][2].tag_vpn, vpn)
node _sector_hits_T_20 = shr(_sector_hits_T_19, 2)
node _sector_hits_T_21 = eq(_sector_hits_T_20, UInt<1>(0h0))
node _sector_hits_T_22 = eq(sectored_entries[0][2].tag_v, priv_v)
node _sector_hits_T_23 = and(_sector_hits_T_21, _sector_hits_T_22)
node sector_hits_2 = and(_sector_hits_T_18, _sector_hits_T_23)
node _sector_hits_T_24 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1])
node _sector_hits_T_25 = or(_sector_hits_T_24, sectored_entries[0][3].valid[2])
node _sector_hits_T_26 = or(_sector_hits_T_25, sectored_entries[0][3].valid[3])
node _sector_hits_T_27 = xor(sectored_entries[0][3].tag_vpn, vpn)
node _sector_hits_T_28 = shr(_sector_hits_T_27, 2)
node _sector_hits_T_29 = eq(_sector_hits_T_28, UInt<1>(0h0))
node _sector_hits_T_30 = eq(sectored_entries[0][3].tag_v, priv_v)
node _sector_hits_T_31 = and(_sector_hits_T_29, _sector_hits_T_30)
node sector_hits_3 = and(_sector_hits_T_26, _sector_hits_T_31)
node _sector_hits_T_32 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1])
node _sector_hits_T_33 = or(_sector_hits_T_32, sectored_entries[0][4].valid[2])
node _sector_hits_T_34 = or(_sector_hits_T_33, sectored_entries[0][4].valid[3])
node _sector_hits_T_35 = xor(sectored_entries[0][4].tag_vpn, vpn)
node _sector_hits_T_36 = shr(_sector_hits_T_35, 2)
node _sector_hits_T_37 = eq(_sector_hits_T_36, UInt<1>(0h0))
node _sector_hits_T_38 = eq(sectored_entries[0][4].tag_v, priv_v)
node _sector_hits_T_39 = and(_sector_hits_T_37, _sector_hits_T_38)
node sector_hits_4 = and(_sector_hits_T_34, _sector_hits_T_39)
node _sector_hits_T_40 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1])
node _sector_hits_T_41 = or(_sector_hits_T_40, sectored_entries[0][5].valid[2])
node _sector_hits_T_42 = or(_sector_hits_T_41, sectored_entries[0][5].valid[3])
node _sector_hits_T_43 = xor(sectored_entries[0][5].tag_vpn, vpn)
node _sector_hits_T_44 = shr(_sector_hits_T_43, 2)
node _sector_hits_T_45 = eq(_sector_hits_T_44, UInt<1>(0h0))
node _sector_hits_T_46 = eq(sectored_entries[0][5].tag_v, priv_v)
node _sector_hits_T_47 = and(_sector_hits_T_45, _sector_hits_T_46)
node sector_hits_5 = and(_sector_hits_T_42, _sector_hits_T_47)
node _sector_hits_T_48 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1])
node _sector_hits_T_49 = or(_sector_hits_T_48, sectored_entries[0][6].valid[2])
node _sector_hits_T_50 = or(_sector_hits_T_49, sectored_entries[0][6].valid[3])
node _sector_hits_T_51 = xor(sectored_entries[0][6].tag_vpn, vpn)
node _sector_hits_T_52 = shr(_sector_hits_T_51, 2)
node _sector_hits_T_53 = eq(_sector_hits_T_52, UInt<1>(0h0))
node _sector_hits_T_54 = eq(sectored_entries[0][6].tag_v, priv_v)
node _sector_hits_T_55 = and(_sector_hits_T_53, _sector_hits_T_54)
node sector_hits_6 = and(_sector_hits_T_50, _sector_hits_T_55)
node _sector_hits_T_56 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1])
node _sector_hits_T_57 = or(_sector_hits_T_56, sectored_entries[0][7].valid[2])
node _sector_hits_T_58 = or(_sector_hits_T_57, sectored_entries[0][7].valid[3])
node _sector_hits_T_59 = xor(sectored_entries[0][7].tag_vpn, vpn)
node _sector_hits_T_60 = shr(_sector_hits_T_59, 2)
node _sector_hits_T_61 = eq(_sector_hits_T_60, UInt<1>(0h0))
node _sector_hits_T_62 = eq(sectored_entries[0][7].tag_v, priv_v)
node _sector_hits_T_63 = and(_sector_hits_T_61, _sector_hits_T_62)
node sector_hits_7 = and(_sector_hits_T_58, _sector_hits_T_63)
node _superpage_hits_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v)
node superpage_hits_tagMatch = and(superpage_entries[0].valid[0], _superpage_hits_tagMatch_T)
node _superpage_hits_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0))
node superpage_hits_ignore = or(_superpage_hits_ignore_T, UInt<1>(0h0))
node _superpage_hits_T = xor(superpage_entries[0].tag_vpn, vpn)
node _superpage_hits_T_1 = bits(_superpage_hits_T, 26, 18)
node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0))
node _superpage_hits_T_3 = or(superpage_hits_ignore, _superpage_hits_T_2)
node _superpage_hits_T_4 = and(superpage_hits_tagMatch, _superpage_hits_T_3)
node _superpage_hits_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1))
node superpage_hits_ignore_1 = or(_superpage_hits_ignore_T_1, UInt<1>(0h0))
node _superpage_hits_T_5 = xor(superpage_entries[0].tag_vpn, vpn)
node _superpage_hits_T_6 = bits(_superpage_hits_T_5, 17, 9)
node _superpage_hits_T_7 = eq(_superpage_hits_T_6, UInt<1>(0h0))
node _superpage_hits_T_8 = or(superpage_hits_ignore_1, _superpage_hits_T_7)
node _superpage_hits_T_9 = and(_superpage_hits_T_4, _superpage_hits_T_8)
node _superpage_hits_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2))
node superpage_hits_ignore_2 = or(_superpage_hits_ignore_T_2, UInt<1>(0h1))
node _superpage_hits_T_10 = xor(superpage_entries[0].tag_vpn, vpn)
node _superpage_hits_T_11 = bits(_superpage_hits_T_10, 8, 0)
node _superpage_hits_T_12 = eq(_superpage_hits_T_11, UInt<1>(0h0))
node _superpage_hits_T_13 = or(superpage_hits_ignore_2, _superpage_hits_T_12)
node superpage_hits_0 = and(_superpage_hits_T_9, _superpage_hits_T_13)
node _superpage_hits_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v)
node superpage_hits_tagMatch_1 = and(superpage_entries[1].valid[0], _superpage_hits_tagMatch_T_1)
node _superpage_hits_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0))
node superpage_hits_ignore_3 = or(_superpage_hits_ignore_T_3, UInt<1>(0h0))
node _superpage_hits_T_14 = xor(superpage_entries[1].tag_vpn, vpn)
node _superpage_hits_T_15 = bits(_superpage_hits_T_14, 26, 18)
node _superpage_hits_T_16 = eq(_superpage_hits_T_15, UInt<1>(0h0))
node _superpage_hits_T_17 = or(superpage_hits_ignore_3, _superpage_hits_T_16)
node _superpage_hits_T_18 = and(superpage_hits_tagMatch_1, _superpage_hits_T_17)
node _superpage_hits_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1))
node superpage_hits_ignore_4 = or(_superpage_hits_ignore_T_4, UInt<1>(0h0))
node _superpage_hits_T_19 = xor(superpage_entries[1].tag_vpn, vpn)
node _superpage_hits_T_20 = bits(_superpage_hits_T_19, 17, 9)
node _superpage_hits_T_21 = eq(_superpage_hits_T_20, UInt<1>(0h0))
node _superpage_hits_T_22 = or(superpage_hits_ignore_4, _superpage_hits_T_21)
node _superpage_hits_T_23 = and(_superpage_hits_T_18, _superpage_hits_T_22)
node _superpage_hits_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2))
node superpage_hits_ignore_5 = or(_superpage_hits_ignore_T_5, UInt<1>(0h1))
node _superpage_hits_T_24 = xor(superpage_entries[1].tag_vpn, vpn)
node _superpage_hits_T_25 = bits(_superpage_hits_T_24, 8, 0)
node _superpage_hits_T_26 = eq(_superpage_hits_T_25, UInt<1>(0h0))
node _superpage_hits_T_27 = or(superpage_hits_ignore_5, _superpage_hits_T_26)
node superpage_hits_1 = and(_superpage_hits_T_23, _superpage_hits_T_27)
node _superpage_hits_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v)
node superpage_hits_tagMatch_2 = and(superpage_entries[2].valid[0], _superpage_hits_tagMatch_T_2)
node _superpage_hits_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0))
node superpage_hits_ignore_6 = or(_superpage_hits_ignore_T_6, UInt<1>(0h0))
node _superpage_hits_T_28 = xor(superpage_entries[2].tag_vpn, vpn)
node _superpage_hits_T_29 = bits(_superpage_hits_T_28, 26, 18)
node _superpage_hits_T_30 = eq(_superpage_hits_T_29, UInt<1>(0h0))
node _superpage_hits_T_31 = or(superpage_hits_ignore_6, _superpage_hits_T_30)
node _superpage_hits_T_32 = and(superpage_hits_tagMatch_2, _superpage_hits_T_31)
node _superpage_hits_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1))
node superpage_hits_ignore_7 = or(_superpage_hits_ignore_T_7, UInt<1>(0h0))
node _superpage_hits_T_33 = xor(superpage_entries[2].tag_vpn, vpn)
node _superpage_hits_T_34 = bits(_superpage_hits_T_33, 17, 9)
node _superpage_hits_T_35 = eq(_superpage_hits_T_34, UInt<1>(0h0))
node _superpage_hits_T_36 = or(superpage_hits_ignore_7, _superpage_hits_T_35)
node _superpage_hits_T_37 = and(_superpage_hits_T_32, _superpage_hits_T_36)
node _superpage_hits_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2))
node superpage_hits_ignore_8 = or(_superpage_hits_ignore_T_8, UInt<1>(0h1))
node _superpage_hits_T_38 = xor(superpage_entries[2].tag_vpn, vpn)
node _superpage_hits_T_39 = bits(_superpage_hits_T_38, 8, 0)
node _superpage_hits_T_40 = eq(_superpage_hits_T_39, UInt<1>(0h0))
node _superpage_hits_T_41 = or(superpage_hits_ignore_8, _superpage_hits_T_40)
node superpage_hits_2 = and(_superpage_hits_T_37, _superpage_hits_T_41)
node _superpage_hits_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v)
node superpage_hits_tagMatch_3 = and(superpage_entries[3].valid[0], _superpage_hits_tagMatch_T_3)
node _superpage_hits_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0))
node superpage_hits_ignore_9 = or(_superpage_hits_ignore_T_9, UInt<1>(0h0))
node _superpage_hits_T_42 = xor(superpage_entries[3].tag_vpn, vpn)
node _superpage_hits_T_43 = bits(_superpage_hits_T_42, 26, 18)
node _superpage_hits_T_44 = eq(_superpage_hits_T_43, UInt<1>(0h0))
node _superpage_hits_T_45 = or(superpage_hits_ignore_9, _superpage_hits_T_44)
node _superpage_hits_T_46 = and(superpage_hits_tagMatch_3, _superpage_hits_T_45)
node _superpage_hits_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1))
node superpage_hits_ignore_10 = or(_superpage_hits_ignore_T_10, UInt<1>(0h0))
node _superpage_hits_T_47 = xor(superpage_entries[3].tag_vpn, vpn)
node _superpage_hits_T_48 = bits(_superpage_hits_T_47, 17, 9)
node _superpage_hits_T_49 = eq(_superpage_hits_T_48, UInt<1>(0h0))
node _superpage_hits_T_50 = or(superpage_hits_ignore_10, _superpage_hits_T_49)
node _superpage_hits_T_51 = and(_superpage_hits_T_46, _superpage_hits_T_50)
node _superpage_hits_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2))
node superpage_hits_ignore_11 = or(_superpage_hits_ignore_T_11, UInt<1>(0h1))
node _superpage_hits_T_52 = xor(superpage_entries[3].tag_vpn, vpn)
node _superpage_hits_T_53 = bits(_superpage_hits_T_52, 8, 0)
node _superpage_hits_T_54 = eq(_superpage_hits_T_53, UInt<1>(0h0))
node _superpage_hits_T_55 = or(superpage_hits_ignore_11, _superpage_hits_T_54)
node superpage_hits_3 = and(_superpage_hits_T_51, _superpage_hits_T_55)
node hitsVec_idx = bits(vpn, 1, 0)
node _hitsVec_T = xor(sectored_entries[0][0].tag_vpn, vpn)
node _hitsVec_T_1 = shr(_hitsVec_T, 2)
node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0))
node _hitsVec_T_3 = eq(sectored_entries[0][0].tag_v, priv_v)
node _hitsVec_T_4 = and(_hitsVec_T_2, _hitsVec_T_3)
node _hitsVec_T_5 = and(sectored_entries[0][0].valid[hitsVec_idx], _hitsVec_T_4)
node hitsVec_0 = and(vm_enabled, _hitsVec_T_5)
node hitsVec_idx_1 = bits(vpn, 1, 0)
node _hitsVec_T_6 = xor(sectored_entries[0][1].tag_vpn, vpn)
node _hitsVec_T_7 = shr(_hitsVec_T_6, 2)
node _hitsVec_T_8 = eq(_hitsVec_T_7, UInt<1>(0h0))
node _hitsVec_T_9 = eq(sectored_entries[0][1].tag_v, priv_v)
node _hitsVec_T_10 = and(_hitsVec_T_8, _hitsVec_T_9)
node _hitsVec_T_11 = and(sectored_entries[0][1].valid[hitsVec_idx_1], _hitsVec_T_10)
node hitsVec_1 = and(vm_enabled, _hitsVec_T_11)
node hitsVec_idx_2 = bits(vpn, 1, 0)
node _hitsVec_T_12 = xor(sectored_entries[0][2].tag_vpn, vpn)
node _hitsVec_T_13 = shr(_hitsVec_T_12, 2)
node _hitsVec_T_14 = eq(_hitsVec_T_13, UInt<1>(0h0))
node _hitsVec_T_15 = eq(sectored_entries[0][2].tag_v, priv_v)
node _hitsVec_T_16 = and(_hitsVec_T_14, _hitsVec_T_15)
node _hitsVec_T_17 = and(sectored_entries[0][2].valid[hitsVec_idx_2], _hitsVec_T_16)
node hitsVec_2 = and(vm_enabled, _hitsVec_T_17)
node hitsVec_idx_3 = bits(vpn, 1, 0)
node _hitsVec_T_18 = xor(sectored_entries[0][3].tag_vpn, vpn)
node _hitsVec_T_19 = shr(_hitsVec_T_18, 2)
node _hitsVec_T_20 = eq(_hitsVec_T_19, UInt<1>(0h0))
node _hitsVec_T_21 = eq(sectored_entries[0][3].tag_v, priv_v)
node _hitsVec_T_22 = and(_hitsVec_T_20, _hitsVec_T_21)
node _hitsVec_T_23 = and(sectored_entries[0][3].valid[hitsVec_idx_3], _hitsVec_T_22)
node hitsVec_3 = and(vm_enabled, _hitsVec_T_23)
node hitsVec_idx_4 = bits(vpn, 1, 0)
node _hitsVec_T_24 = xor(sectored_entries[0][4].tag_vpn, vpn)
node _hitsVec_T_25 = shr(_hitsVec_T_24, 2)
node _hitsVec_T_26 = eq(_hitsVec_T_25, UInt<1>(0h0))
node _hitsVec_T_27 = eq(sectored_entries[0][4].tag_v, priv_v)
node _hitsVec_T_28 = and(_hitsVec_T_26, _hitsVec_T_27)
node _hitsVec_T_29 = and(sectored_entries[0][4].valid[hitsVec_idx_4], _hitsVec_T_28)
node hitsVec_4 = and(vm_enabled, _hitsVec_T_29)
node hitsVec_idx_5 = bits(vpn, 1, 0)
node _hitsVec_T_30 = xor(sectored_entries[0][5].tag_vpn, vpn)
node _hitsVec_T_31 = shr(_hitsVec_T_30, 2)
node _hitsVec_T_32 = eq(_hitsVec_T_31, UInt<1>(0h0))
node _hitsVec_T_33 = eq(sectored_entries[0][5].tag_v, priv_v)
node _hitsVec_T_34 = and(_hitsVec_T_32, _hitsVec_T_33)
node _hitsVec_T_35 = and(sectored_entries[0][5].valid[hitsVec_idx_5], _hitsVec_T_34)
node hitsVec_5 = and(vm_enabled, _hitsVec_T_35)
node hitsVec_idx_6 = bits(vpn, 1, 0)
node _hitsVec_T_36 = xor(sectored_entries[0][6].tag_vpn, vpn)
node _hitsVec_T_37 = shr(_hitsVec_T_36, 2)
node _hitsVec_T_38 = eq(_hitsVec_T_37, UInt<1>(0h0))
node _hitsVec_T_39 = eq(sectored_entries[0][6].tag_v, priv_v)
node _hitsVec_T_40 = and(_hitsVec_T_38, _hitsVec_T_39)
node _hitsVec_T_41 = and(sectored_entries[0][6].valid[hitsVec_idx_6], _hitsVec_T_40)
node hitsVec_6 = and(vm_enabled, _hitsVec_T_41)
node hitsVec_idx_7 = bits(vpn, 1, 0)
node _hitsVec_T_42 = xor(sectored_entries[0][7].tag_vpn, vpn)
node _hitsVec_T_43 = shr(_hitsVec_T_42, 2)
node _hitsVec_T_44 = eq(_hitsVec_T_43, UInt<1>(0h0))
node _hitsVec_T_45 = eq(sectored_entries[0][7].tag_v, priv_v)
node _hitsVec_T_46 = and(_hitsVec_T_44, _hitsVec_T_45)
node _hitsVec_T_47 = and(sectored_entries[0][7].valid[hitsVec_idx_7], _hitsVec_T_46)
node hitsVec_7 = and(vm_enabled, _hitsVec_T_47)
node _hitsVec_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v)
node hitsVec_tagMatch = and(superpage_entries[0].valid[0], _hitsVec_tagMatch_T)
node _hitsVec_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0))
node hitsVec_ignore = or(_hitsVec_ignore_T, UInt<1>(0h0))
node _hitsVec_T_48 = xor(superpage_entries[0].tag_vpn, vpn)
node _hitsVec_T_49 = bits(_hitsVec_T_48, 26, 18)
node _hitsVec_T_50 = eq(_hitsVec_T_49, UInt<1>(0h0))
node _hitsVec_T_51 = or(hitsVec_ignore, _hitsVec_T_50)
node _hitsVec_T_52 = and(hitsVec_tagMatch, _hitsVec_T_51)
node _hitsVec_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1))
node hitsVec_ignore_1 = or(_hitsVec_ignore_T_1, UInt<1>(0h0))
node _hitsVec_T_53 = xor(superpage_entries[0].tag_vpn, vpn)
node _hitsVec_T_54 = bits(_hitsVec_T_53, 17, 9)
node _hitsVec_T_55 = eq(_hitsVec_T_54, UInt<1>(0h0))
node _hitsVec_T_56 = or(hitsVec_ignore_1, _hitsVec_T_55)
node _hitsVec_T_57 = and(_hitsVec_T_52, _hitsVec_T_56)
node _hitsVec_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2))
node hitsVec_ignore_2 = or(_hitsVec_ignore_T_2, UInt<1>(0h1))
node _hitsVec_T_58 = xor(superpage_entries[0].tag_vpn, vpn)
node _hitsVec_T_59 = bits(_hitsVec_T_58, 8, 0)
node _hitsVec_T_60 = eq(_hitsVec_T_59, UInt<1>(0h0))
node _hitsVec_T_61 = or(hitsVec_ignore_2, _hitsVec_T_60)
node _hitsVec_T_62 = and(_hitsVec_T_57, _hitsVec_T_61)
node hitsVec_8 = and(vm_enabled, _hitsVec_T_62)
node _hitsVec_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v)
node hitsVec_tagMatch_1 = and(superpage_entries[1].valid[0], _hitsVec_tagMatch_T_1)
node _hitsVec_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0))
node hitsVec_ignore_3 = or(_hitsVec_ignore_T_3, UInt<1>(0h0))
node _hitsVec_T_63 = xor(superpage_entries[1].tag_vpn, vpn)
node _hitsVec_T_64 = bits(_hitsVec_T_63, 26, 18)
node _hitsVec_T_65 = eq(_hitsVec_T_64, UInt<1>(0h0))
node _hitsVec_T_66 = or(hitsVec_ignore_3, _hitsVec_T_65)
node _hitsVec_T_67 = and(hitsVec_tagMatch_1, _hitsVec_T_66)
node _hitsVec_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1))
node hitsVec_ignore_4 = or(_hitsVec_ignore_T_4, UInt<1>(0h0))
node _hitsVec_T_68 = xor(superpage_entries[1].tag_vpn, vpn)
node _hitsVec_T_69 = bits(_hitsVec_T_68, 17, 9)
node _hitsVec_T_70 = eq(_hitsVec_T_69, UInt<1>(0h0))
node _hitsVec_T_71 = or(hitsVec_ignore_4, _hitsVec_T_70)
node _hitsVec_T_72 = and(_hitsVec_T_67, _hitsVec_T_71)
node _hitsVec_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2))
node hitsVec_ignore_5 = or(_hitsVec_ignore_T_5, UInt<1>(0h1))
node _hitsVec_T_73 = xor(superpage_entries[1].tag_vpn, vpn)
node _hitsVec_T_74 = bits(_hitsVec_T_73, 8, 0)
node _hitsVec_T_75 = eq(_hitsVec_T_74, UInt<1>(0h0))
node _hitsVec_T_76 = or(hitsVec_ignore_5, _hitsVec_T_75)
node _hitsVec_T_77 = and(_hitsVec_T_72, _hitsVec_T_76)
node hitsVec_9 = and(vm_enabled, _hitsVec_T_77)
node _hitsVec_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v)
node hitsVec_tagMatch_2 = and(superpage_entries[2].valid[0], _hitsVec_tagMatch_T_2)
node _hitsVec_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0))
node hitsVec_ignore_6 = or(_hitsVec_ignore_T_6, UInt<1>(0h0))
node _hitsVec_T_78 = xor(superpage_entries[2].tag_vpn, vpn)
node _hitsVec_T_79 = bits(_hitsVec_T_78, 26, 18)
node _hitsVec_T_80 = eq(_hitsVec_T_79, UInt<1>(0h0))
node _hitsVec_T_81 = or(hitsVec_ignore_6, _hitsVec_T_80)
node _hitsVec_T_82 = and(hitsVec_tagMatch_2, _hitsVec_T_81)
node _hitsVec_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1))
node hitsVec_ignore_7 = or(_hitsVec_ignore_T_7, UInt<1>(0h0))
node _hitsVec_T_83 = xor(superpage_entries[2].tag_vpn, vpn)
node _hitsVec_T_84 = bits(_hitsVec_T_83, 17, 9)
node _hitsVec_T_85 = eq(_hitsVec_T_84, UInt<1>(0h0))
node _hitsVec_T_86 = or(hitsVec_ignore_7, _hitsVec_T_85)
node _hitsVec_T_87 = and(_hitsVec_T_82, _hitsVec_T_86)
node _hitsVec_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2))
node hitsVec_ignore_8 = or(_hitsVec_ignore_T_8, UInt<1>(0h1))
node _hitsVec_T_88 = xor(superpage_entries[2].tag_vpn, vpn)
node _hitsVec_T_89 = bits(_hitsVec_T_88, 8, 0)
node _hitsVec_T_90 = eq(_hitsVec_T_89, UInt<1>(0h0))
node _hitsVec_T_91 = or(hitsVec_ignore_8, _hitsVec_T_90)
node _hitsVec_T_92 = and(_hitsVec_T_87, _hitsVec_T_91)
node hitsVec_10 = and(vm_enabled, _hitsVec_T_92)
node _hitsVec_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v)
node hitsVec_tagMatch_3 = and(superpage_entries[3].valid[0], _hitsVec_tagMatch_T_3)
node _hitsVec_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0))
node hitsVec_ignore_9 = or(_hitsVec_ignore_T_9, UInt<1>(0h0))
node _hitsVec_T_93 = xor(superpage_entries[3].tag_vpn, vpn)
node _hitsVec_T_94 = bits(_hitsVec_T_93, 26, 18)
node _hitsVec_T_95 = eq(_hitsVec_T_94, UInt<1>(0h0))
node _hitsVec_T_96 = or(hitsVec_ignore_9, _hitsVec_T_95)
node _hitsVec_T_97 = and(hitsVec_tagMatch_3, _hitsVec_T_96)
node _hitsVec_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1))
node hitsVec_ignore_10 = or(_hitsVec_ignore_T_10, UInt<1>(0h0))
node _hitsVec_T_98 = xor(superpage_entries[3].tag_vpn, vpn)
node _hitsVec_T_99 = bits(_hitsVec_T_98, 17, 9)
node _hitsVec_T_100 = eq(_hitsVec_T_99, UInt<1>(0h0))
node _hitsVec_T_101 = or(hitsVec_ignore_10, _hitsVec_T_100)
node _hitsVec_T_102 = and(_hitsVec_T_97, _hitsVec_T_101)
node _hitsVec_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2))
node hitsVec_ignore_11 = or(_hitsVec_ignore_T_11, UInt<1>(0h1))
node _hitsVec_T_103 = xor(superpage_entries[3].tag_vpn, vpn)
node _hitsVec_T_104 = bits(_hitsVec_T_103, 8, 0)
node _hitsVec_T_105 = eq(_hitsVec_T_104, UInt<1>(0h0))
node _hitsVec_T_106 = or(hitsVec_ignore_11, _hitsVec_T_105)
node _hitsVec_T_107 = and(_hitsVec_T_102, _hitsVec_T_106)
node hitsVec_11 = and(vm_enabled, _hitsVec_T_107)
node _hitsVec_tagMatch_T_4 = eq(special_entry.tag_v, priv_v)
node hitsVec_tagMatch_4 = and(special_entry.valid[0], _hitsVec_tagMatch_T_4)
node _hitsVec_ignore_T_12 = lt(special_entry.level, UInt<1>(0h0))
node hitsVec_ignore_12 = or(_hitsVec_ignore_T_12, UInt<1>(0h0))
node _hitsVec_T_108 = xor(special_entry.tag_vpn, vpn)
node _hitsVec_T_109 = bits(_hitsVec_T_108, 26, 18)
node _hitsVec_T_110 = eq(_hitsVec_T_109, UInt<1>(0h0))
node _hitsVec_T_111 = or(hitsVec_ignore_12, _hitsVec_T_110)
node _hitsVec_T_112 = and(hitsVec_tagMatch_4, _hitsVec_T_111)
node _hitsVec_ignore_T_13 = lt(special_entry.level, UInt<1>(0h1))
node hitsVec_ignore_13 = or(_hitsVec_ignore_T_13, UInt<1>(0h0))
node _hitsVec_T_113 = xor(special_entry.tag_vpn, vpn)
node _hitsVec_T_114 = bits(_hitsVec_T_113, 17, 9)
node _hitsVec_T_115 = eq(_hitsVec_T_114, UInt<1>(0h0))
node _hitsVec_T_116 = or(hitsVec_ignore_13, _hitsVec_T_115)
node _hitsVec_T_117 = and(_hitsVec_T_112, _hitsVec_T_116)
node _hitsVec_ignore_T_14 = lt(special_entry.level, UInt<2>(0h2))
node hitsVec_ignore_14 = or(_hitsVec_ignore_T_14, UInt<1>(0h0))
node _hitsVec_T_118 = xor(special_entry.tag_vpn, vpn)
node _hitsVec_T_119 = bits(_hitsVec_T_118, 8, 0)
node _hitsVec_T_120 = eq(_hitsVec_T_119, UInt<1>(0h0))
node _hitsVec_T_121 = or(hitsVec_ignore_14, _hitsVec_T_120)
node _hitsVec_T_122 = and(_hitsVec_T_117, _hitsVec_T_121)
node hitsVec_12 = and(vm_enabled, _hitsVec_T_122)
node real_hits_lo_lo_hi = cat(hitsVec_2, hitsVec_1)
node real_hits_lo_lo = cat(real_hits_lo_lo_hi, hitsVec_0)
node real_hits_lo_hi_hi = cat(hitsVec_5, hitsVec_4)
node real_hits_lo_hi = cat(real_hits_lo_hi_hi, hitsVec_3)
node real_hits_lo = cat(real_hits_lo_hi, real_hits_lo_lo)
node real_hits_hi_lo_hi = cat(hitsVec_8, hitsVec_7)
node real_hits_hi_lo = cat(real_hits_hi_lo_hi, hitsVec_6)
node real_hits_hi_hi_lo = cat(hitsVec_10, hitsVec_9)
node real_hits_hi_hi_hi = cat(hitsVec_12, hitsVec_11)
node real_hits_hi_hi = cat(real_hits_hi_hi_hi, real_hits_hi_hi_lo)
node real_hits_hi = cat(real_hits_hi_hi, real_hits_hi_lo)
node real_hits = cat(real_hits_hi, real_hits_lo)
node _hits_T = eq(vm_enabled, UInt<1>(0h0))
node hits = cat(_hits_T, real_hits)
when do_refill :
node refill_v = or(r_vstage1_en, r_stage2_en)
wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
connect newEntry.ppn, io.ptw.resp.bits.pte.ppn
connect newEntry.c, cacheable
connect newEntry.u, io.ptw.resp.bits.pte.u
node _newEntry_g_T = and(io.ptw.resp.bits.pte.g, io.ptw.resp.bits.pte.v)
connect newEntry.g, _newEntry_g_T
connect newEntry.ae_ptw, io.ptw.resp.bits.ae_ptw
connect newEntry.ae_final, io.ptw.resp.bits.ae_final
node _newEntry_ae_stage2_T = and(io.ptw.resp.bits.ae_final, io.ptw.resp.bits.gpa_is_pte)
node _newEntry_ae_stage2_T_1 = and(_newEntry_ae_stage2_T, r_stage2_en)
connect newEntry.ae_stage2, _newEntry_ae_stage2_T_1
connect newEntry.pf, io.ptw.resp.bits.pf
connect newEntry.gf, io.ptw.resp.bits.gf
connect newEntry.hr, io.ptw.resp.bits.hr
connect newEntry.hw, io.ptw.resp.bits.hw
connect newEntry.hx, io.ptw.resp.bits.hx
node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0))
node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T)
node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1)
node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2)
node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a)
node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r)
connect newEntry.sr, _newEntry_sr_T_5
node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0))
node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T)
node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1)
node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2)
node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a)
node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w)
node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d)
connect newEntry.sw, _newEntry_sw_T_6
node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0))
node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T)
node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1)
node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2)
node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a)
node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x)
connect newEntry.sx, _newEntry_sx_T_5
connect newEntry.pr, prot_r
connect newEntry.pw, prot_w
connect newEntry.px, prot_x
connect newEntry.ppp, pma.io.resp.pp
connect newEntry.pal, pma.io.resp.al
connect newEntry.paa, pma.io.resp.aa
connect newEntry.eff, pma.io.resp.eff
connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage
node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
when _T_1 :
connect special_entry.tag_vpn, r_refill_tag
connect special_entry.tag_v, refill_v
node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0)
connect special_entry.level, _special_entry_level_T
connect special_entry.valid[0], UInt<1>(0h1)
node special_entry_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node special_entry_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node special_entry_data_0_lo_lo_hi = cat(special_entry_data_0_lo_lo_hi_hi, newEntry.eff)
node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo)
node special_entry_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node special_entry_data_0_lo_hi_lo = cat(special_entry_data_0_lo_hi_lo_hi, newEntry.ppp)
node special_entry_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node special_entry_data_0_lo_hi_hi = cat(special_entry_data_0_lo_hi_hi_hi, newEntry.pw)
node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo)
node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo)
node special_entry_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node special_entry_data_0_hi_lo_lo = cat(special_entry_data_0_hi_lo_lo_hi, newEntry.hw)
node special_entry_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node special_entry_data_0_hi_lo_hi = cat(special_entry_data_0_hi_lo_hi_hi, newEntry.sw)
node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo)
node special_entry_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node special_entry_data_0_hi_hi_lo = cat(special_entry_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node special_entry_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node special_entry_data_0_hi_hi_hi = cat(special_entry_data_0_hi_hi_hi_hi, newEntry.g)
node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo)
node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo)
node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo)
connect special_entry.data[0], _special_entry_data_0_T
else :
node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2))
when _T_2 :
node _waddr_T = and(r_superpage_hit.valid, UInt<1>(0h0))
node waddr = mux(_waddr_T, r_superpage_hit.bits, r_superpage_repl_addr)
node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0))
when _T_3 :
connect superpage_entries[0].tag_vpn, r_refill_tag
connect superpage_entries[0].tag_v, refill_v
node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[0].level, _superpage_entries_0_level_T
connect superpage_entries[0].valid[0], UInt<1>(0h1)
node superpage_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node superpage_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node superpage_entries_0_data_0_lo_lo_hi = cat(superpage_entries_0_data_0_lo_lo_hi_hi, newEntry.eff)
node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo)
node superpage_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_0_data_0_lo_hi_lo = cat(superpage_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp)
node superpage_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node superpage_entries_0_data_0_lo_hi_hi = cat(superpage_entries_0_data_0_lo_hi_hi_hi, newEntry.pw)
node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo)
node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo)
node superpage_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node superpage_entries_0_data_0_hi_lo_lo = cat(superpage_entries_0_data_0_hi_lo_lo_hi, newEntry.hw)
node superpage_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node superpage_entries_0_data_0_hi_lo_hi = cat(superpage_entries_0_data_0_hi_lo_hi_hi, newEntry.sw)
node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo)
node superpage_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node superpage_entries_0_data_0_hi_hi_lo = cat(superpage_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node superpage_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_0_data_0_hi_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi_hi, newEntry.g)
node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo)
node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo)
node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo)
connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T
when invalidate_refill :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
node _T_4 = eq(r_superpage_repl_addr, UInt<1>(0h1))
when _T_4 :
connect superpage_entries[1].tag_vpn, r_refill_tag
connect superpage_entries[1].tag_v, refill_v
node _superpage_entries_1_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[1].level, _superpage_entries_1_level_T
connect superpage_entries[1].valid[0], UInt<1>(0h1)
node superpage_entries_1_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node superpage_entries_1_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node superpage_entries_1_data_0_lo_lo_hi = cat(superpage_entries_1_data_0_lo_lo_hi_hi, newEntry.eff)
node superpage_entries_1_data_0_lo_lo = cat(superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo)
node superpage_entries_1_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_1_data_0_lo_hi_lo = cat(superpage_entries_1_data_0_lo_hi_lo_hi, newEntry.ppp)
node superpage_entries_1_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node superpage_entries_1_data_0_lo_hi_hi = cat(superpage_entries_1_data_0_lo_hi_hi_hi, newEntry.pw)
node superpage_entries_1_data_0_lo_hi = cat(superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo)
node superpage_entries_1_data_0_lo = cat(superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo)
node superpage_entries_1_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node superpage_entries_1_data_0_hi_lo_lo = cat(superpage_entries_1_data_0_hi_lo_lo_hi, newEntry.hw)
node superpage_entries_1_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node superpage_entries_1_data_0_hi_lo_hi = cat(superpage_entries_1_data_0_hi_lo_hi_hi, newEntry.sw)
node superpage_entries_1_data_0_hi_lo = cat(superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo)
node superpage_entries_1_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node superpage_entries_1_data_0_hi_hi_lo = cat(superpage_entries_1_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node superpage_entries_1_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_1_data_0_hi_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi_hi, newEntry.g)
node superpage_entries_1_data_0_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo)
node superpage_entries_1_data_0_hi = cat(superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo)
node _superpage_entries_1_data_0_T = cat(superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo)
connect superpage_entries[1].data[0], _superpage_entries_1_data_0_T
when invalidate_refill :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
node _T_5 = eq(r_superpage_repl_addr, UInt<2>(0h2))
when _T_5 :
connect superpage_entries[2].tag_vpn, r_refill_tag
connect superpage_entries[2].tag_v, refill_v
node _superpage_entries_2_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[2].level, _superpage_entries_2_level_T
connect superpage_entries[2].valid[0], UInt<1>(0h1)
node superpage_entries_2_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node superpage_entries_2_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node superpage_entries_2_data_0_lo_lo_hi = cat(superpage_entries_2_data_0_lo_lo_hi_hi, newEntry.eff)
node superpage_entries_2_data_0_lo_lo = cat(superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo)
node superpage_entries_2_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_2_data_0_lo_hi_lo = cat(superpage_entries_2_data_0_lo_hi_lo_hi, newEntry.ppp)
node superpage_entries_2_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node superpage_entries_2_data_0_lo_hi_hi = cat(superpage_entries_2_data_0_lo_hi_hi_hi, newEntry.pw)
node superpage_entries_2_data_0_lo_hi = cat(superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo)
node superpage_entries_2_data_0_lo = cat(superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo)
node superpage_entries_2_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node superpage_entries_2_data_0_hi_lo_lo = cat(superpage_entries_2_data_0_hi_lo_lo_hi, newEntry.hw)
node superpage_entries_2_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node superpage_entries_2_data_0_hi_lo_hi = cat(superpage_entries_2_data_0_hi_lo_hi_hi, newEntry.sw)
node superpage_entries_2_data_0_hi_lo = cat(superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo)
node superpage_entries_2_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node superpage_entries_2_data_0_hi_hi_lo = cat(superpage_entries_2_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node superpage_entries_2_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_2_data_0_hi_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi_hi, newEntry.g)
node superpage_entries_2_data_0_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo)
node superpage_entries_2_data_0_hi = cat(superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo)
node _superpage_entries_2_data_0_T = cat(superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo)
connect superpage_entries[2].data[0], _superpage_entries_2_data_0_T
when invalidate_refill :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
node _T_6 = eq(r_superpage_repl_addr, UInt<2>(0h3))
when _T_6 :
connect superpage_entries[3].tag_vpn, r_refill_tag
connect superpage_entries[3].tag_v, refill_v
node _superpage_entries_3_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[3].level, _superpage_entries_3_level_T
connect superpage_entries[3].valid[0], UInt<1>(0h1)
node superpage_entries_3_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node superpage_entries_3_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node superpage_entries_3_data_0_lo_lo_hi = cat(superpage_entries_3_data_0_lo_lo_hi_hi, newEntry.eff)
node superpage_entries_3_data_0_lo_lo = cat(superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo)
node superpage_entries_3_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_3_data_0_lo_hi_lo = cat(superpage_entries_3_data_0_lo_hi_lo_hi, newEntry.ppp)
node superpage_entries_3_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node superpage_entries_3_data_0_lo_hi_hi = cat(superpage_entries_3_data_0_lo_hi_hi_hi, newEntry.pw)
node superpage_entries_3_data_0_lo_hi = cat(superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo)
node superpage_entries_3_data_0_lo = cat(superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo)
node superpage_entries_3_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node superpage_entries_3_data_0_hi_lo_lo = cat(superpage_entries_3_data_0_hi_lo_lo_hi, newEntry.hw)
node superpage_entries_3_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node superpage_entries_3_data_0_hi_lo_hi = cat(superpage_entries_3_data_0_hi_lo_hi_hi, newEntry.sw)
node superpage_entries_3_data_0_hi_lo = cat(superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo)
node superpage_entries_3_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node superpage_entries_3_data_0_hi_hi_lo = cat(superpage_entries_3_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node superpage_entries_3_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_3_data_0_hi_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi_hi, newEntry.g)
node superpage_entries_3_data_0_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo)
node superpage_entries_3_data_0_hi = cat(superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo)
node _superpage_entries_3_data_0_T = cat(superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo)
connect superpage_entries[3].data[0], _superpage_entries_3_data_0_T
when invalidate_refill :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
else :
node waddr_1 = mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr)
node _T_7 = eq(waddr_1, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_8 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
connect sectored_entries[0][0].tag_vpn, r_refill_tag
connect sectored_entries[0][0].tag_v, refill_v
connect sectored_entries[0][0].level, UInt<2>(0h0)
node idx = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][0].valid[idx], UInt<1>(0h1)
node sectored_entries_0_0_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_0_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_0_data_lo_lo_hi = cat(sectored_entries_0_0_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_0_data_lo_lo = cat(sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo)
node sectored_entries_0_0_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_0_data_lo_hi_lo = cat(sectored_entries_0_0_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_0_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_0_data_lo_hi_hi = cat(sectored_entries_0_0_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_0_data_lo_hi = cat(sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo)
node sectored_entries_0_0_data_lo = cat(sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo)
node sectored_entries_0_0_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_0_data_hi_lo_lo = cat(sectored_entries_0_0_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_0_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_0_data_hi_lo_hi = cat(sectored_entries_0_0_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_0_data_hi_lo = cat(sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo)
node sectored_entries_0_0_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_0_data_hi_hi_lo = cat(sectored_entries_0_0_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_0_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_0_data_hi_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_0_data_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo)
node sectored_entries_0_0_data_hi = cat(sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo)
node _sectored_entries_0_0_data_T = cat(sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo)
connect sectored_entries[0][0].data[idx], _sectored_entries_0_0_data_T
when invalidate_refill :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
node _T_9 = eq(waddr_1, UInt<1>(0h1))
when _T_9 :
node _T_10 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_10 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
connect sectored_entries[0][1].tag_vpn, r_refill_tag
connect sectored_entries[0][1].tag_v, refill_v
connect sectored_entries[0][1].level, UInt<2>(0h0)
node idx_1 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][1].valid[idx_1], UInt<1>(0h1)
node sectored_entries_0_1_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_1_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_1_data_lo_lo_hi = cat(sectored_entries_0_1_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_1_data_lo_lo = cat(sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo)
node sectored_entries_0_1_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_1_data_lo_hi_lo = cat(sectored_entries_0_1_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_1_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_1_data_lo_hi_hi = cat(sectored_entries_0_1_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_1_data_lo_hi = cat(sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo)
node sectored_entries_0_1_data_lo = cat(sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo)
node sectored_entries_0_1_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_1_data_hi_lo_lo = cat(sectored_entries_0_1_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_1_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_1_data_hi_lo_hi = cat(sectored_entries_0_1_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_1_data_hi_lo = cat(sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo)
node sectored_entries_0_1_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_1_data_hi_hi_lo = cat(sectored_entries_0_1_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_1_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_1_data_hi_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_1_data_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo)
node sectored_entries_0_1_data_hi = cat(sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo)
node _sectored_entries_0_1_data_T = cat(sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo)
connect sectored_entries[0][1].data[idx_1], _sectored_entries_0_1_data_T
when invalidate_refill :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
node _T_11 = eq(waddr_1, UInt<2>(0h2))
when _T_11 :
node _T_12 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_12 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
connect sectored_entries[0][2].tag_vpn, r_refill_tag
connect sectored_entries[0][2].tag_v, refill_v
connect sectored_entries[0][2].level, UInt<2>(0h0)
node idx_2 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][2].valid[idx_2], UInt<1>(0h1)
node sectored_entries_0_2_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_2_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_2_data_lo_lo_hi = cat(sectored_entries_0_2_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_2_data_lo_lo = cat(sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo)
node sectored_entries_0_2_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_2_data_lo_hi_lo = cat(sectored_entries_0_2_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_2_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_2_data_lo_hi_hi = cat(sectored_entries_0_2_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_2_data_lo_hi = cat(sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo)
node sectored_entries_0_2_data_lo = cat(sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo)
node sectored_entries_0_2_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_2_data_hi_lo_lo = cat(sectored_entries_0_2_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_2_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_2_data_hi_lo_hi = cat(sectored_entries_0_2_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_2_data_hi_lo = cat(sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo)
node sectored_entries_0_2_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_2_data_hi_hi_lo = cat(sectored_entries_0_2_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_2_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_2_data_hi_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_2_data_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo)
node sectored_entries_0_2_data_hi = cat(sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo)
node _sectored_entries_0_2_data_T = cat(sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo)
connect sectored_entries[0][2].data[idx_2], _sectored_entries_0_2_data_T
when invalidate_refill :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
node _T_13 = eq(waddr_1, UInt<2>(0h3))
when _T_13 :
node _T_14 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_14 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
connect sectored_entries[0][3].tag_vpn, r_refill_tag
connect sectored_entries[0][3].tag_v, refill_v
connect sectored_entries[0][3].level, UInt<2>(0h0)
node idx_3 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][3].valid[idx_3], UInt<1>(0h1)
node sectored_entries_0_3_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_3_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_3_data_lo_lo_hi = cat(sectored_entries_0_3_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_3_data_lo_lo = cat(sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo)
node sectored_entries_0_3_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_3_data_lo_hi_lo = cat(sectored_entries_0_3_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_3_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_3_data_lo_hi_hi = cat(sectored_entries_0_3_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_3_data_lo_hi = cat(sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo)
node sectored_entries_0_3_data_lo = cat(sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo)
node sectored_entries_0_3_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_3_data_hi_lo_lo = cat(sectored_entries_0_3_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_3_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_3_data_hi_lo_hi = cat(sectored_entries_0_3_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_3_data_hi_lo = cat(sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo)
node sectored_entries_0_3_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_3_data_hi_hi_lo = cat(sectored_entries_0_3_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_3_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_3_data_hi_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_3_data_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo)
node sectored_entries_0_3_data_hi = cat(sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo)
node _sectored_entries_0_3_data_T = cat(sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo)
connect sectored_entries[0][3].data[idx_3], _sectored_entries_0_3_data_T
when invalidate_refill :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
node _T_15 = eq(waddr_1, UInt<3>(0h4))
when _T_15 :
node _T_16 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_16 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
connect sectored_entries[0][4].tag_vpn, r_refill_tag
connect sectored_entries[0][4].tag_v, refill_v
connect sectored_entries[0][4].level, UInt<2>(0h0)
node idx_4 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][4].valid[idx_4], UInt<1>(0h1)
node sectored_entries_0_4_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_4_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_4_data_lo_lo_hi = cat(sectored_entries_0_4_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_4_data_lo_lo = cat(sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo)
node sectored_entries_0_4_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_4_data_lo_hi_lo = cat(sectored_entries_0_4_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_4_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_4_data_lo_hi_hi = cat(sectored_entries_0_4_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_4_data_lo_hi = cat(sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo)
node sectored_entries_0_4_data_lo = cat(sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo)
node sectored_entries_0_4_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_4_data_hi_lo_lo = cat(sectored_entries_0_4_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_4_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_4_data_hi_lo_hi = cat(sectored_entries_0_4_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_4_data_hi_lo = cat(sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo)
node sectored_entries_0_4_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_4_data_hi_hi_lo = cat(sectored_entries_0_4_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_4_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_4_data_hi_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_4_data_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo)
node sectored_entries_0_4_data_hi = cat(sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo)
node _sectored_entries_0_4_data_T = cat(sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo)
connect sectored_entries[0][4].data[idx_4], _sectored_entries_0_4_data_T
when invalidate_refill :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
node _T_17 = eq(waddr_1, UInt<3>(0h5))
when _T_17 :
node _T_18 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_18 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
connect sectored_entries[0][5].tag_vpn, r_refill_tag
connect sectored_entries[0][5].tag_v, refill_v
connect sectored_entries[0][5].level, UInt<2>(0h0)
node idx_5 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][5].valid[idx_5], UInt<1>(0h1)
node sectored_entries_0_5_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_5_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_5_data_lo_lo_hi = cat(sectored_entries_0_5_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_5_data_lo_lo = cat(sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo)
node sectored_entries_0_5_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_5_data_lo_hi_lo = cat(sectored_entries_0_5_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_5_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_5_data_lo_hi_hi = cat(sectored_entries_0_5_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_5_data_lo_hi = cat(sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo)
node sectored_entries_0_5_data_lo = cat(sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo)
node sectored_entries_0_5_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_5_data_hi_lo_lo = cat(sectored_entries_0_5_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_5_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_5_data_hi_lo_hi = cat(sectored_entries_0_5_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_5_data_hi_lo = cat(sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo)
node sectored_entries_0_5_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_5_data_hi_hi_lo = cat(sectored_entries_0_5_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_5_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_5_data_hi_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_5_data_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo)
node sectored_entries_0_5_data_hi = cat(sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo)
node _sectored_entries_0_5_data_T = cat(sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo)
connect sectored_entries[0][5].data[idx_5], _sectored_entries_0_5_data_T
when invalidate_refill :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
node _T_19 = eq(waddr_1, UInt<3>(0h6))
when _T_19 :
node _T_20 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_20 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
connect sectored_entries[0][6].tag_vpn, r_refill_tag
connect sectored_entries[0][6].tag_v, refill_v
connect sectored_entries[0][6].level, UInt<2>(0h0)
node idx_6 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][6].valid[idx_6], UInt<1>(0h1)
node sectored_entries_0_6_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_6_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_6_data_lo_lo_hi = cat(sectored_entries_0_6_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_6_data_lo_lo = cat(sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo)
node sectored_entries_0_6_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_6_data_lo_hi_lo = cat(sectored_entries_0_6_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_6_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_6_data_lo_hi_hi = cat(sectored_entries_0_6_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_6_data_lo_hi = cat(sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo)
node sectored_entries_0_6_data_lo = cat(sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo)
node sectored_entries_0_6_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_6_data_hi_lo_lo = cat(sectored_entries_0_6_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_6_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_6_data_hi_lo_hi = cat(sectored_entries_0_6_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_6_data_hi_lo = cat(sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo)
node sectored_entries_0_6_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_6_data_hi_hi_lo = cat(sectored_entries_0_6_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_6_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_6_data_hi_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_6_data_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo)
node sectored_entries_0_6_data_hi = cat(sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo)
node _sectored_entries_0_6_data_T = cat(sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo)
connect sectored_entries[0][6].data[idx_6], _sectored_entries_0_6_data_T
when invalidate_refill :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
node _T_21 = eq(waddr_1, UInt<3>(0h7))
when _T_21 :
node _T_22 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_22 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
connect sectored_entries[0][7].tag_vpn, r_refill_tag
connect sectored_entries[0][7].tag_v, refill_v
connect sectored_entries[0][7].level, UInt<2>(0h0)
node idx_7 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][7].valid[idx_7], UInt<1>(0h1)
node sectored_entries_0_7_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_7_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_7_data_lo_lo_hi = cat(sectored_entries_0_7_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_7_data_lo_lo = cat(sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo)
node sectored_entries_0_7_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_7_data_lo_hi_lo = cat(sectored_entries_0_7_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_7_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_7_data_lo_hi_hi = cat(sectored_entries_0_7_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_7_data_lo_hi = cat(sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo)
node sectored_entries_0_7_data_lo = cat(sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo)
node sectored_entries_0_7_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_7_data_hi_lo_lo = cat(sectored_entries_0_7_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_7_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_7_data_hi_lo_hi = cat(sectored_entries_0_7_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_7_data_hi_lo = cat(sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo)
node sectored_entries_0_7_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_7_data_hi_hi_lo = cat(sectored_entries_0_7_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_7_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_7_data_hi_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_7_data_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo)
node sectored_entries_0_7_data_hi = cat(sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo)
node _sectored_entries_0_7_data_T = cat(sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo)
connect sectored_entries[0][7].data[idx_7], _sectored_entries_0_7_data_T
when invalidate_refill :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
connect r_gpa_valid, io.ptw.resp.bits.gpa.valid
connect r_gpa, io.ptw.resp.bits.gpa.bits
connect r_gpa_is_pte, io.ptw.resp.bits.gpa_is_pte
node _entries_T = bits(vpn, 1, 0)
wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_1 : UInt<42>
connect _entries_WIRE_1, sectored_entries[0][0].data[_entries_T]
node _entries_T_1 = bits(_entries_WIRE_1, 0, 0)
connect _entries_WIRE.fragmented_superpage, _entries_T_1
node _entries_T_2 = bits(_entries_WIRE_1, 1, 1)
connect _entries_WIRE.c, _entries_T_2
node _entries_T_3 = bits(_entries_WIRE_1, 2, 2)
connect _entries_WIRE.eff, _entries_T_3
node _entries_T_4 = bits(_entries_WIRE_1, 3, 3)
connect _entries_WIRE.paa, _entries_T_4
node _entries_T_5 = bits(_entries_WIRE_1, 4, 4)
connect _entries_WIRE.pal, _entries_T_5
node _entries_T_6 = bits(_entries_WIRE_1, 5, 5)
connect _entries_WIRE.ppp, _entries_T_6
node _entries_T_7 = bits(_entries_WIRE_1, 6, 6)
connect _entries_WIRE.pr, _entries_T_7
node _entries_T_8 = bits(_entries_WIRE_1, 7, 7)
connect _entries_WIRE.px, _entries_T_8
node _entries_T_9 = bits(_entries_WIRE_1, 8, 8)
connect _entries_WIRE.pw, _entries_T_9
node _entries_T_10 = bits(_entries_WIRE_1, 9, 9)
connect _entries_WIRE.hr, _entries_T_10
node _entries_T_11 = bits(_entries_WIRE_1, 10, 10)
connect _entries_WIRE.hx, _entries_T_11
node _entries_T_12 = bits(_entries_WIRE_1, 11, 11)
connect _entries_WIRE.hw, _entries_T_12
node _entries_T_13 = bits(_entries_WIRE_1, 12, 12)
connect _entries_WIRE.sr, _entries_T_13
node _entries_T_14 = bits(_entries_WIRE_1, 13, 13)
connect _entries_WIRE.sx, _entries_T_14
node _entries_T_15 = bits(_entries_WIRE_1, 14, 14)
connect _entries_WIRE.sw, _entries_T_15
node _entries_T_16 = bits(_entries_WIRE_1, 15, 15)
connect _entries_WIRE.gf, _entries_T_16
node _entries_T_17 = bits(_entries_WIRE_1, 16, 16)
connect _entries_WIRE.pf, _entries_T_17
node _entries_T_18 = bits(_entries_WIRE_1, 17, 17)
connect _entries_WIRE.ae_stage2, _entries_T_18
node _entries_T_19 = bits(_entries_WIRE_1, 18, 18)
connect _entries_WIRE.ae_final, _entries_T_19
node _entries_T_20 = bits(_entries_WIRE_1, 19, 19)
connect _entries_WIRE.ae_ptw, _entries_T_20
node _entries_T_21 = bits(_entries_WIRE_1, 20, 20)
connect _entries_WIRE.g, _entries_T_21
node _entries_T_22 = bits(_entries_WIRE_1, 21, 21)
connect _entries_WIRE.u, _entries_T_22
node _entries_T_23 = bits(_entries_WIRE_1, 41, 22)
connect _entries_WIRE.ppn, _entries_T_23
inst entries_barrier of OptimizationBarrier_TLBEntryData_253
connect entries_barrier.clock, clock
connect entries_barrier.reset, reset
connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage
connect entries_barrier.io.x.c, _entries_WIRE.c
connect entries_barrier.io.x.eff, _entries_WIRE.eff
connect entries_barrier.io.x.paa, _entries_WIRE.paa
connect entries_barrier.io.x.pal, _entries_WIRE.pal
connect entries_barrier.io.x.ppp, _entries_WIRE.ppp
connect entries_barrier.io.x.pr, _entries_WIRE.pr
connect entries_barrier.io.x.px, _entries_WIRE.px
connect entries_barrier.io.x.pw, _entries_WIRE.pw
connect entries_barrier.io.x.hr, _entries_WIRE.hr
connect entries_barrier.io.x.hx, _entries_WIRE.hx
connect entries_barrier.io.x.hw, _entries_WIRE.hw
connect entries_barrier.io.x.sr, _entries_WIRE.sr
connect entries_barrier.io.x.sx, _entries_WIRE.sx
connect entries_barrier.io.x.sw, _entries_WIRE.sw
connect entries_barrier.io.x.gf, _entries_WIRE.gf
connect entries_barrier.io.x.pf, _entries_WIRE.pf
connect entries_barrier.io.x.ae_stage2, _entries_WIRE.ae_stage2
connect entries_barrier.io.x.ae_final, _entries_WIRE.ae_final
connect entries_barrier.io.x.ae_ptw, _entries_WIRE.ae_ptw
connect entries_barrier.io.x.g, _entries_WIRE.g
connect entries_barrier.io.x.u, _entries_WIRE.u
connect entries_barrier.io.x.ppn, _entries_WIRE.ppn
node _entries_T_24 = bits(vpn, 1, 0)
wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_3 : UInt<42>
connect _entries_WIRE_3, sectored_entries[0][1].data[_entries_T_24]
node _entries_T_25 = bits(_entries_WIRE_3, 0, 0)
connect _entries_WIRE_2.fragmented_superpage, _entries_T_25
node _entries_T_26 = bits(_entries_WIRE_3, 1, 1)
connect _entries_WIRE_2.c, _entries_T_26
node _entries_T_27 = bits(_entries_WIRE_3, 2, 2)
connect _entries_WIRE_2.eff, _entries_T_27
node _entries_T_28 = bits(_entries_WIRE_3, 3, 3)
connect _entries_WIRE_2.paa, _entries_T_28
node _entries_T_29 = bits(_entries_WIRE_3, 4, 4)
connect _entries_WIRE_2.pal, _entries_T_29
node _entries_T_30 = bits(_entries_WIRE_3, 5, 5)
connect _entries_WIRE_2.ppp, _entries_T_30
node _entries_T_31 = bits(_entries_WIRE_3, 6, 6)
connect _entries_WIRE_2.pr, _entries_T_31
node _entries_T_32 = bits(_entries_WIRE_3, 7, 7)
connect _entries_WIRE_2.px, _entries_T_32
node _entries_T_33 = bits(_entries_WIRE_3, 8, 8)
connect _entries_WIRE_2.pw, _entries_T_33
node _entries_T_34 = bits(_entries_WIRE_3, 9, 9)
connect _entries_WIRE_2.hr, _entries_T_34
node _entries_T_35 = bits(_entries_WIRE_3, 10, 10)
connect _entries_WIRE_2.hx, _entries_T_35
node _entries_T_36 = bits(_entries_WIRE_3, 11, 11)
connect _entries_WIRE_2.hw, _entries_T_36
node _entries_T_37 = bits(_entries_WIRE_3, 12, 12)
connect _entries_WIRE_2.sr, _entries_T_37
node _entries_T_38 = bits(_entries_WIRE_3, 13, 13)
connect _entries_WIRE_2.sx, _entries_T_38
node _entries_T_39 = bits(_entries_WIRE_3, 14, 14)
connect _entries_WIRE_2.sw, _entries_T_39
node _entries_T_40 = bits(_entries_WIRE_3, 15, 15)
connect _entries_WIRE_2.gf, _entries_T_40
node _entries_T_41 = bits(_entries_WIRE_3, 16, 16)
connect _entries_WIRE_2.pf, _entries_T_41
node _entries_T_42 = bits(_entries_WIRE_3, 17, 17)
connect _entries_WIRE_2.ae_stage2, _entries_T_42
node _entries_T_43 = bits(_entries_WIRE_3, 18, 18)
connect _entries_WIRE_2.ae_final, _entries_T_43
node _entries_T_44 = bits(_entries_WIRE_3, 19, 19)
connect _entries_WIRE_2.ae_ptw, _entries_T_44
node _entries_T_45 = bits(_entries_WIRE_3, 20, 20)
connect _entries_WIRE_2.g, _entries_T_45
node _entries_T_46 = bits(_entries_WIRE_3, 21, 21)
connect _entries_WIRE_2.u, _entries_T_46
node _entries_T_47 = bits(_entries_WIRE_3, 41, 22)
connect _entries_WIRE_2.ppn, _entries_T_47
inst entries_barrier_1 of OptimizationBarrier_TLBEntryData_254
connect entries_barrier_1.clock, clock
connect entries_barrier_1.reset, reset
connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage
connect entries_barrier_1.io.x.c, _entries_WIRE_2.c
connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff
connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa
connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal
connect entries_barrier_1.io.x.ppp, _entries_WIRE_2.ppp
connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr
connect entries_barrier_1.io.x.px, _entries_WIRE_2.px
connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw
connect entries_barrier_1.io.x.hr, _entries_WIRE_2.hr
connect entries_barrier_1.io.x.hx, _entries_WIRE_2.hx
connect entries_barrier_1.io.x.hw, _entries_WIRE_2.hw
connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr
connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx
connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw
connect entries_barrier_1.io.x.gf, _entries_WIRE_2.gf
connect entries_barrier_1.io.x.pf, _entries_WIRE_2.pf
connect entries_barrier_1.io.x.ae_stage2, _entries_WIRE_2.ae_stage2
connect entries_barrier_1.io.x.ae_final, _entries_WIRE_2.ae_final
connect entries_barrier_1.io.x.ae_ptw, _entries_WIRE_2.ae_ptw
connect entries_barrier_1.io.x.g, _entries_WIRE_2.g
connect entries_barrier_1.io.x.u, _entries_WIRE_2.u
connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn
node _entries_T_48 = bits(vpn, 1, 0)
wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_5 : UInt<42>
connect _entries_WIRE_5, sectored_entries[0][2].data[_entries_T_48]
node _entries_T_49 = bits(_entries_WIRE_5, 0, 0)
connect _entries_WIRE_4.fragmented_superpage, _entries_T_49
node _entries_T_50 = bits(_entries_WIRE_5, 1, 1)
connect _entries_WIRE_4.c, _entries_T_50
node _entries_T_51 = bits(_entries_WIRE_5, 2, 2)
connect _entries_WIRE_4.eff, _entries_T_51
node _entries_T_52 = bits(_entries_WIRE_5, 3, 3)
connect _entries_WIRE_4.paa, _entries_T_52
node _entries_T_53 = bits(_entries_WIRE_5, 4, 4)
connect _entries_WIRE_4.pal, _entries_T_53
node _entries_T_54 = bits(_entries_WIRE_5, 5, 5)
connect _entries_WIRE_4.ppp, _entries_T_54
node _entries_T_55 = bits(_entries_WIRE_5, 6, 6)
connect _entries_WIRE_4.pr, _entries_T_55
node _entries_T_56 = bits(_entries_WIRE_5, 7, 7)
connect _entries_WIRE_4.px, _entries_T_56
node _entries_T_57 = bits(_entries_WIRE_5, 8, 8)
connect _entries_WIRE_4.pw, _entries_T_57
node _entries_T_58 = bits(_entries_WIRE_5, 9, 9)
connect _entries_WIRE_4.hr, _entries_T_58
node _entries_T_59 = bits(_entries_WIRE_5, 10, 10)
connect _entries_WIRE_4.hx, _entries_T_59
node _entries_T_60 = bits(_entries_WIRE_5, 11, 11)
connect _entries_WIRE_4.hw, _entries_T_60
node _entries_T_61 = bits(_entries_WIRE_5, 12, 12)
connect _entries_WIRE_4.sr, _entries_T_61
node _entries_T_62 = bits(_entries_WIRE_5, 13, 13)
connect _entries_WIRE_4.sx, _entries_T_62
node _entries_T_63 = bits(_entries_WIRE_5, 14, 14)
connect _entries_WIRE_4.sw, _entries_T_63
node _entries_T_64 = bits(_entries_WIRE_5, 15, 15)
connect _entries_WIRE_4.gf, _entries_T_64
node _entries_T_65 = bits(_entries_WIRE_5, 16, 16)
connect _entries_WIRE_4.pf, _entries_T_65
node _entries_T_66 = bits(_entries_WIRE_5, 17, 17)
connect _entries_WIRE_4.ae_stage2, _entries_T_66
node _entries_T_67 = bits(_entries_WIRE_5, 18, 18)
connect _entries_WIRE_4.ae_final, _entries_T_67
node _entries_T_68 = bits(_entries_WIRE_5, 19, 19)
connect _entries_WIRE_4.ae_ptw, _entries_T_68
node _entries_T_69 = bits(_entries_WIRE_5, 20, 20)
connect _entries_WIRE_4.g, _entries_T_69
node _entries_T_70 = bits(_entries_WIRE_5, 21, 21)
connect _entries_WIRE_4.u, _entries_T_70
node _entries_T_71 = bits(_entries_WIRE_5, 41, 22)
connect _entries_WIRE_4.ppn, _entries_T_71
inst entries_barrier_2 of OptimizationBarrier_TLBEntryData_255
connect entries_barrier_2.clock, clock
connect entries_barrier_2.reset, reset
connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage
connect entries_barrier_2.io.x.c, _entries_WIRE_4.c
connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff
connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa
connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal
connect entries_barrier_2.io.x.ppp, _entries_WIRE_4.ppp
connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr
connect entries_barrier_2.io.x.px, _entries_WIRE_4.px
connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw
connect entries_barrier_2.io.x.hr, _entries_WIRE_4.hr
connect entries_barrier_2.io.x.hx, _entries_WIRE_4.hx
connect entries_barrier_2.io.x.hw, _entries_WIRE_4.hw
connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr
connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx
connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw
connect entries_barrier_2.io.x.gf, _entries_WIRE_4.gf
connect entries_barrier_2.io.x.pf, _entries_WIRE_4.pf
connect entries_barrier_2.io.x.ae_stage2, _entries_WIRE_4.ae_stage2
connect entries_barrier_2.io.x.ae_final, _entries_WIRE_4.ae_final
connect entries_barrier_2.io.x.ae_ptw, _entries_WIRE_4.ae_ptw
connect entries_barrier_2.io.x.g, _entries_WIRE_4.g
connect entries_barrier_2.io.x.u, _entries_WIRE_4.u
connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn
node _entries_T_72 = bits(vpn, 1, 0)
wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_7 : UInt<42>
connect _entries_WIRE_7, sectored_entries[0][3].data[_entries_T_72]
node _entries_T_73 = bits(_entries_WIRE_7, 0, 0)
connect _entries_WIRE_6.fragmented_superpage, _entries_T_73
node _entries_T_74 = bits(_entries_WIRE_7, 1, 1)
connect _entries_WIRE_6.c, _entries_T_74
node _entries_T_75 = bits(_entries_WIRE_7, 2, 2)
connect _entries_WIRE_6.eff, _entries_T_75
node _entries_T_76 = bits(_entries_WIRE_7, 3, 3)
connect _entries_WIRE_6.paa, _entries_T_76
node _entries_T_77 = bits(_entries_WIRE_7, 4, 4)
connect _entries_WIRE_6.pal, _entries_T_77
node _entries_T_78 = bits(_entries_WIRE_7, 5, 5)
connect _entries_WIRE_6.ppp, _entries_T_78
node _entries_T_79 = bits(_entries_WIRE_7, 6, 6)
connect _entries_WIRE_6.pr, _entries_T_79
node _entries_T_80 = bits(_entries_WIRE_7, 7, 7)
connect _entries_WIRE_6.px, _entries_T_80
node _entries_T_81 = bits(_entries_WIRE_7, 8, 8)
connect _entries_WIRE_6.pw, _entries_T_81
node _entries_T_82 = bits(_entries_WIRE_7, 9, 9)
connect _entries_WIRE_6.hr, _entries_T_82
node _entries_T_83 = bits(_entries_WIRE_7, 10, 10)
connect _entries_WIRE_6.hx, _entries_T_83
node _entries_T_84 = bits(_entries_WIRE_7, 11, 11)
connect _entries_WIRE_6.hw, _entries_T_84
node _entries_T_85 = bits(_entries_WIRE_7, 12, 12)
connect _entries_WIRE_6.sr, _entries_T_85
node _entries_T_86 = bits(_entries_WIRE_7, 13, 13)
connect _entries_WIRE_6.sx, _entries_T_86
node _entries_T_87 = bits(_entries_WIRE_7, 14, 14)
connect _entries_WIRE_6.sw, _entries_T_87
node _entries_T_88 = bits(_entries_WIRE_7, 15, 15)
connect _entries_WIRE_6.gf, _entries_T_88
node _entries_T_89 = bits(_entries_WIRE_7, 16, 16)
connect _entries_WIRE_6.pf, _entries_T_89
node _entries_T_90 = bits(_entries_WIRE_7, 17, 17)
connect _entries_WIRE_6.ae_stage2, _entries_T_90
node _entries_T_91 = bits(_entries_WIRE_7, 18, 18)
connect _entries_WIRE_6.ae_final, _entries_T_91
node _entries_T_92 = bits(_entries_WIRE_7, 19, 19)
connect _entries_WIRE_6.ae_ptw, _entries_T_92
node _entries_T_93 = bits(_entries_WIRE_7, 20, 20)
connect _entries_WIRE_6.g, _entries_T_93
node _entries_T_94 = bits(_entries_WIRE_7, 21, 21)
connect _entries_WIRE_6.u, _entries_T_94
node _entries_T_95 = bits(_entries_WIRE_7, 41, 22)
connect _entries_WIRE_6.ppn, _entries_T_95
inst entries_barrier_3 of OptimizationBarrier_TLBEntryData_256
connect entries_barrier_3.clock, clock
connect entries_barrier_3.reset, reset
connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage
connect entries_barrier_3.io.x.c, _entries_WIRE_6.c
connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff
connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa
connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal
connect entries_barrier_3.io.x.ppp, _entries_WIRE_6.ppp
connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr
connect entries_barrier_3.io.x.px, _entries_WIRE_6.px
connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw
connect entries_barrier_3.io.x.hr, _entries_WIRE_6.hr
connect entries_barrier_3.io.x.hx, _entries_WIRE_6.hx
connect entries_barrier_3.io.x.hw, _entries_WIRE_6.hw
connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr
connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx
connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw
connect entries_barrier_3.io.x.gf, _entries_WIRE_6.gf
connect entries_barrier_3.io.x.pf, _entries_WIRE_6.pf
connect entries_barrier_3.io.x.ae_stage2, _entries_WIRE_6.ae_stage2
connect entries_barrier_3.io.x.ae_final, _entries_WIRE_6.ae_final
connect entries_barrier_3.io.x.ae_ptw, _entries_WIRE_6.ae_ptw
connect entries_barrier_3.io.x.g, _entries_WIRE_6.g
connect entries_barrier_3.io.x.u, _entries_WIRE_6.u
connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn
node _entries_T_96 = bits(vpn, 1, 0)
wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_9 : UInt<42>
connect _entries_WIRE_9, sectored_entries[0][4].data[_entries_T_96]
node _entries_T_97 = bits(_entries_WIRE_9, 0, 0)
connect _entries_WIRE_8.fragmented_superpage, _entries_T_97
node _entries_T_98 = bits(_entries_WIRE_9, 1, 1)
connect _entries_WIRE_8.c, _entries_T_98
node _entries_T_99 = bits(_entries_WIRE_9, 2, 2)
connect _entries_WIRE_8.eff, _entries_T_99
node _entries_T_100 = bits(_entries_WIRE_9, 3, 3)
connect _entries_WIRE_8.paa, _entries_T_100
node _entries_T_101 = bits(_entries_WIRE_9, 4, 4)
connect _entries_WIRE_8.pal, _entries_T_101
node _entries_T_102 = bits(_entries_WIRE_9, 5, 5)
connect _entries_WIRE_8.ppp, _entries_T_102
node _entries_T_103 = bits(_entries_WIRE_9, 6, 6)
connect _entries_WIRE_8.pr, _entries_T_103
node _entries_T_104 = bits(_entries_WIRE_9, 7, 7)
connect _entries_WIRE_8.px, _entries_T_104
node _entries_T_105 = bits(_entries_WIRE_9, 8, 8)
connect _entries_WIRE_8.pw, _entries_T_105
node _entries_T_106 = bits(_entries_WIRE_9, 9, 9)
connect _entries_WIRE_8.hr, _entries_T_106
node _entries_T_107 = bits(_entries_WIRE_9, 10, 10)
connect _entries_WIRE_8.hx, _entries_T_107
node _entries_T_108 = bits(_entries_WIRE_9, 11, 11)
connect _entries_WIRE_8.hw, _entries_T_108
node _entries_T_109 = bits(_entries_WIRE_9, 12, 12)
connect _entries_WIRE_8.sr, _entries_T_109
node _entries_T_110 = bits(_entries_WIRE_9, 13, 13)
connect _entries_WIRE_8.sx, _entries_T_110
node _entries_T_111 = bits(_entries_WIRE_9, 14, 14)
connect _entries_WIRE_8.sw, _entries_T_111
node _entries_T_112 = bits(_entries_WIRE_9, 15, 15)
connect _entries_WIRE_8.gf, _entries_T_112
node _entries_T_113 = bits(_entries_WIRE_9, 16, 16)
connect _entries_WIRE_8.pf, _entries_T_113
node _entries_T_114 = bits(_entries_WIRE_9, 17, 17)
connect _entries_WIRE_8.ae_stage2, _entries_T_114
node _entries_T_115 = bits(_entries_WIRE_9, 18, 18)
connect _entries_WIRE_8.ae_final, _entries_T_115
node _entries_T_116 = bits(_entries_WIRE_9, 19, 19)
connect _entries_WIRE_8.ae_ptw, _entries_T_116
node _entries_T_117 = bits(_entries_WIRE_9, 20, 20)
connect _entries_WIRE_8.g, _entries_T_117
node _entries_T_118 = bits(_entries_WIRE_9, 21, 21)
connect _entries_WIRE_8.u, _entries_T_118
node _entries_T_119 = bits(_entries_WIRE_9, 41, 22)
connect _entries_WIRE_8.ppn, _entries_T_119
inst entries_barrier_4 of OptimizationBarrier_TLBEntryData_257
connect entries_barrier_4.clock, clock
connect entries_barrier_4.reset, reset
connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage
connect entries_barrier_4.io.x.c, _entries_WIRE_8.c
connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff
connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa
connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal
connect entries_barrier_4.io.x.ppp, _entries_WIRE_8.ppp
connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr
connect entries_barrier_4.io.x.px, _entries_WIRE_8.px
connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw
connect entries_barrier_4.io.x.hr, _entries_WIRE_8.hr
connect entries_barrier_4.io.x.hx, _entries_WIRE_8.hx
connect entries_barrier_4.io.x.hw, _entries_WIRE_8.hw
connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr
connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx
connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw
connect entries_barrier_4.io.x.gf, _entries_WIRE_8.gf
connect entries_barrier_4.io.x.pf, _entries_WIRE_8.pf
connect entries_barrier_4.io.x.ae_stage2, _entries_WIRE_8.ae_stage2
connect entries_barrier_4.io.x.ae_final, _entries_WIRE_8.ae_final
connect entries_barrier_4.io.x.ae_ptw, _entries_WIRE_8.ae_ptw
connect entries_barrier_4.io.x.g, _entries_WIRE_8.g
connect entries_barrier_4.io.x.u, _entries_WIRE_8.u
connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn
node _entries_T_120 = bits(vpn, 1, 0)
wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_11 : UInt<42>
connect _entries_WIRE_11, sectored_entries[0][5].data[_entries_T_120]
node _entries_T_121 = bits(_entries_WIRE_11, 0, 0)
connect _entries_WIRE_10.fragmented_superpage, _entries_T_121
node _entries_T_122 = bits(_entries_WIRE_11, 1, 1)
connect _entries_WIRE_10.c, _entries_T_122
node _entries_T_123 = bits(_entries_WIRE_11, 2, 2)
connect _entries_WIRE_10.eff, _entries_T_123
node _entries_T_124 = bits(_entries_WIRE_11, 3, 3)
connect _entries_WIRE_10.paa, _entries_T_124
node _entries_T_125 = bits(_entries_WIRE_11, 4, 4)
connect _entries_WIRE_10.pal, _entries_T_125
node _entries_T_126 = bits(_entries_WIRE_11, 5, 5)
connect _entries_WIRE_10.ppp, _entries_T_126
node _entries_T_127 = bits(_entries_WIRE_11, 6, 6)
connect _entries_WIRE_10.pr, _entries_T_127
node _entries_T_128 = bits(_entries_WIRE_11, 7, 7)
connect _entries_WIRE_10.px, _entries_T_128
node _entries_T_129 = bits(_entries_WIRE_11, 8, 8)
connect _entries_WIRE_10.pw, _entries_T_129
node _entries_T_130 = bits(_entries_WIRE_11, 9, 9)
connect _entries_WIRE_10.hr, _entries_T_130
node _entries_T_131 = bits(_entries_WIRE_11, 10, 10)
connect _entries_WIRE_10.hx, _entries_T_131
node _entries_T_132 = bits(_entries_WIRE_11, 11, 11)
connect _entries_WIRE_10.hw, _entries_T_132
node _entries_T_133 = bits(_entries_WIRE_11, 12, 12)
connect _entries_WIRE_10.sr, _entries_T_133
node _entries_T_134 = bits(_entries_WIRE_11, 13, 13)
connect _entries_WIRE_10.sx, _entries_T_134
node _entries_T_135 = bits(_entries_WIRE_11, 14, 14)
connect _entries_WIRE_10.sw, _entries_T_135
node _entries_T_136 = bits(_entries_WIRE_11, 15, 15)
connect _entries_WIRE_10.gf, _entries_T_136
node _entries_T_137 = bits(_entries_WIRE_11, 16, 16)
connect _entries_WIRE_10.pf, _entries_T_137
node _entries_T_138 = bits(_entries_WIRE_11, 17, 17)
connect _entries_WIRE_10.ae_stage2, _entries_T_138
node _entries_T_139 = bits(_entries_WIRE_11, 18, 18)
connect _entries_WIRE_10.ae_final, _entries_T_139
node _entries_T_140 = bits(_entries_WIRE_11, 19, 19)
connect _entries_WIRE_10.ae_ptw, _entries_T_140
node _entries_T_141 = bits(_entries_WIRE_11, 20, 20)
connect _entries_WIRE_10.g, _entries_T_141
node _entries_T_142 = bits(_entries_WIRE_11, 21, 21)
connect _entries_WIRE_10.u, _entries_T_142
node _entries_T_143 = bits(_entries_WIRE_11, 41, 22)
connect _entries_WIRE_10.ppn, _entries_T_143
inst entries_barrier_5 of OptimizationBarrier_TLBEntryData_258
connect entries_barrier_5.clock, clock
connect entries_barrier_5.reset, reset
connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage
connect entries_barrier_5.io.x.c, _entries_WIRE_10.c
connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff
connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa
connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal
connect entries_barrier_5.io.x.ppp, _entries_WIRE_10.ppp
connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr
connect entries_barrier_5.io.x.px, _entries_WIRE_10.px
connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw
connect entries_barrier_5.io.x.hr, _entries_WIRE_10.hr
connect entries_barrier_5.io.x.hx, _entries_WIRE_10.hx
connect entries_barrier_5.io.x.hw, _entries_WIRE_10.hw
connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr
connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx
connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw
connect entries_barrier_5.io.x.gf, _entries_WIRE_10.gf
connect entries_barrier_5.io.x.pf, _entries_WIRE_10.pf
connect entries_barrier_5.io.x.ae_stage2, _entries_WIRE_10.ae_stage2
connect entries_barrier_5.io.x.ae_final, _entries_WIRE_10.ae_final
connect entries_barrier_5.io.x.ae_ptw, _entries_WIRE_10.ae_ptw
connect entries_barrier_5.io.x.g, _entries_WIRE_10.g
connect entries_barrier_5.io.x.u, _entries_WIRE_10.u
connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn
node _entries_T_144 = bits(vpn, 1, 0)
wire _entries_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_13 : UInt<42>
connect _entries_WIRE_13, sectored_entries[0][6].data[_entries_T_144]
node _entries_T_145 = bits(_entries_WIRE_13, 0, 0)
connect _entries_WIRE_12.fragmented_superpage, _entries_T_145
node _entries_T_146 = bits(_entries_WIRE_13, 1, 1)
connect _entries_WIRE_12.c, _entries_T_146
node _entries_T_147 = bits(_entries_WIRE_13, 2, 2)
connect _entries_WIRE_12.eff, _entries_T_147
node _entries_T_148 = bits(_entries_WIRE_13, 3, 3)
connect _entries_WIRE_12.paa, _entries_T_148
node _entries_T_149 = bits(_entries_WIRE_13, 4, 4)
connect _entries_WIRE_12.pal, _entries_T_149
node _entries_T_150 = bits(_entries_WIRE_13, 5, 5)
connect _entries_WIRE_12.ppp, _entries_T_150
node _entries_T_151 = bits(_entries_WIRE_13, 6, 6)
connect _entries_WIRE_12.pr, _entries_T_151
node _entries_T_152 = bits(_entries_WIRE_13, 7, 7)
connect _entries_WIRE_12.px, _entries_T_152
node _entries_T_153 = bits(_entries_WIRE_13, 8, 8)
connect _entries_WIRE_12.pw, _entries_T_153
node _entries_T_154 = bits(_entries_WIRE_13, 9, 9)
connect _entries_WIRE_12.hr, _entries_T_154
node _entries_T_155 = bits(_entries_WIRE_13, 10, 10)
connect _entries_WIRE_12.hx, _entries_T_155
node _entries_T_156 = bits(_entries_WIRE_13, 11, 11)
connect _entries_WIRE_12.hw, _entries_T_156
node _entries_T_157 = bits(_entries_WIRE_13, 12, 12)
connect _entries_WIRE_12.sr, _entries_T_157
node _entries_T_158 = bits(_entries_WIRE_13, 13, 13)
connect _entries_WIRE_12.sx, _entries_T_158
node _entries_T_159 = bits(_entries_WIRE_13, 14, 14)
connect _entries_WIRE_12.sw, _entries_T_159
node _entries_T_160 = bits(_entries_WIRE_13, 15, 15)
connect _entries_WIRE_12.gf, _entries_T_160
node _entries_T_161 = bits(_entries_WIRE_13, 16, 16)
connect _entries_WIRE_12.pf, _entries_T_161
node _entries_T_162 = bits(_entries_WIRE_13, 17, 17)
connect _entries_WIRE_12.ae_stage2, _entries_T_162
node _entries_T_163 = bits(_entries_WIRE_13, 18, 18)
connect _entries_WIRE_12.ae_final, _entries_T_163
node _entries_T_164 = bits(_entries_WIRE_13, 19, 19)
connect _entries_WIRE_12.ae_ptw, _entries_T_164
node _entries_T_165 = bits(_entries_WIRE_13, 20, 20)
connect _entries_WIRE_12.g, _entries_T_165
node _entries_T_166 = bits(_entries_WIRE_13, 21, 21)
connect _entries_WIRE_12.u, _entries_T_166
node _entries_T_167 = bits(_entries_WIRE_13, 41, 22)
connect _entries_WIRE_12.ppn, _entries_T_167
inst entries_barrier_6 of OptimizationBarrier_TLBEntryData_259
connect entries_barrier_6.clock, clock
connect entries_barrier_6.reset, reset
connect entries_barrier_6.io.x.fragmented_superpage, _entries_WIRE_12.fragmented_superpage
connect entries_barrier_6.io.x.c, _entries_WIRE_12.c
connect entries_barrier_6.io.x.eff, _entries_WIRE_12.eff
connect entries_barrier_6.io.x.paa, _entries_WIRE_12.paa
connect entries_barrier_6.io.x.pal, _entries_WIRE_12.pal
connect entries_barrier_6.io.x.ppp, _entries_WIRE_12.ppp
connect entries_barrier_6.io.x.pr, _entries_WIRE_12.pr
connect entries_barrier_6.io.x.px, _entries_WIRE_12.px
connect entries_barrier_6.io.x.pw, _entries_WIRE_12.pw
connect entries_barrier_6.io.x.hr, _entries_WIRE_12.hr
connect entries_barrier_6.io.x.hx, _entries_WIRE_12.hx
connect entries_barrier_6.io.x.hw, _entries_WIRE_12.hw
connect entries_barrier_6.io.x.sr, _entries_WIRE_12.sr
connect entries_barrier_6.io.x.sx, _entries_WIRE_12.sx
connect entries_barrier_6.io.x.sw, _entries_WIRE_12.sw
connect entries_barrier_6.io.x.gf, _entries_WIRE_12.gf
connect entries_barrier_6.io.x.pf, _entries_WIRE_12.pf
connect entries_barrier_6.io.x.ae_stage2, _entries_WIRE_12.ae_stage2
connect entries_barrier_6.io.x.ae_final, _entries_WIRE_12.ae_final
connect entries_barrier_6.io.x.ae_ptw, _entries_WIRE_12.ae_ptw
connect entries_barrier_6.io.x.g, _entries_WIRE_12.g
connect entries_barrier_6.io.x.u, _entries_WIRE_12.u
connect entries_barrier_6.io.x.ppn, _entries_WIRE_12.ppn
node _entries_T_168 = bits(vpn, 1, 0)
wire _entries_WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_15 : UInt<42>
connect _entries_WIRE_15, sectored_entries[0][7].data[_entries_T_168]
node _entries_T_169 = bits(_entries_WIRE_15, 0, 0)
connect _entries_WIRE_14.fragmented_superpage, _entries_T_169
node _entries_T_170 = bits(_entries_WIRE_15, 1, 1)
connect _entries_WIRE_14.c, _entries_T_170
node _entries_T_171 = bits(_entries_WIRE_15, 2, 2)
connect _entries_WIRE_14.eff, _entries_T_171
node _entries_T_172 = bits(_entries_WIRE_15, 3, 3)
connect _entries_WIRE_14.paa, _entries_T_172
node _entries_T_173 = bits(_entries_WIRE_15, 4, 4)
connect _entries_WIRE_14.pal, _entries_T_173
node _entries_T_174 = bits(_entries_WIRE_15, 5, 5)
connect _entries_WIRE_14.ppp, _entries_T_174
node _entries_T_175 = bits(_entries_WIRE_15, 6, 6)
connect _entries_WIRE_14.pr, _entries_T_175
node _entries_T_176 = bits(_entries_WIRE_15, 7, 7)
connect _entries_WIRE_14.px, _entries_T_176
node _entries_T_177 = bits(_entries_WIRE_15, 8, 8)
connect _entries_WIRE_14.pw, _entries_T_177
node _entries_T_178 = bits(_entries_WIRE_15, 9, 9)
connect _entries_WIRE_14.hr, _entries_T_178
node _entries_T_179 = bits(_entries_WIRE_15, 10, 10)
connect _entries_WIRE_14.hx, _entries_T_179
node _entries_T_180 = bits(_entries_WIRE_15, 11, 11)
connect _entries_WIRE_14.hw, _entries_T_180
node _entries_T_181 = bits(_entries_WIRE_15, 12, 12)
connect _entries_WIRE_14.sr, _entries_T_181
node _entries_T_182 = bits(_entries_WIRE_15, 13, 13)
connect _entries_WIRE_14.sx, _entries_T_182
node _entries_T_183 = bits(_entries_WIRE_15, 14, 14)
connect _entries_WIRE_14.sw, _entries_T_183
node _entries_T_184 = bits(_entries_WIRE_15, 15, 15)
connect _entries_WIRE_14.gf, _entries_T_184
node _entries_T_185 = bits(_entries_WIRE_15, 16, 16)
connect _entries_WIRE_14.pf, _entries_T_185
node _entries_T_186 = bits(_entries_WIRE_15, 17, 17)
connect _entries_WIRE_14.ae_stage2, _entries_T_186
node _entries_T_187 = bits(_entries_WIRE_15, 18, 18)
connect _entries_WIRE_14.ae_final, _entries_T_187
node _entries_T_188 = bits(_entries_WIRE_15, 19, 19)
connect _entries_WIRE_14.ae_ptw, _entries_T_188
node _entries_T_189 = bits(_entries_WIRE_15, 20, 20)
connect _entries_WIRE_14.g, _entries_T_189
node _entries_T_190 = bits(_entries_WIRE_15, 21, 21)
connect _entries_WIRE_14.u, _entries_T_190
node _entries_T_191 = bits(_entries_WIRE_15, 41, 22)
connect _entries_WIRE_14.ppn, _entries_T_191
inst entries_barrier_7 of OptimizationBarrier_TLBEntryData_260
connect entries_barrier_7.clock, clock
connect entries_barrier_7.reset, reset
connect entries_barrier_7.io.x.fragmented_superpage, _entries_WIRE_14.fragmented_superpage
connect entries_barrier_7.io.x.c, _entries_WIRE_14.c
connect entries_barrier_7.io.x.eff, _entries_WIRE_14.eff
connect entries_barrier_7.io.x.paa, _entries_WIRE_14.paa
connect entries_barrier_7.io.x.pal, _entries_WIRE_14.pal
connect entries_barrier_7.io.x.ppp, _entries_WIRE_14.ppp
connect entries_barrier_7.io.x.pr, _entries_WIRE_14.pr
connect entries_barrier_7.io.x.px, _entries_WIRE_14.px
connect entries_barrier_7.io.x.pw, _entries_WIRE_14.pw
connect entries_barrier_7.io.x.hr, _entries_WIRE_14.hr
connect entries_barrier_7.io.x.hx, _entries_WIRE_14.hx
connect entries_barrier_7.io.x.hw, _entries_WIRE_14.hw
connect entries_barrier_7.io.x.sr, _entries_WIRE_14.sr
connect entries_barrier_7.io.x.sx, _entries_WIRE_14.sx
connect entries_barrier_7.io.x.sw, _entries_WIRE_14.sw
connect entries_barrier_7.io.x.gf, _entries_WIRE_14.gf
connect entries_barrier_7.io.x.pf, _entries_WIRE_14.pf
connect entries_barrier_7.io.x.ae_stage2, _entries_WIRE_14.ae_stage2
connect entries_barrier_7.io.x.ae_final, _entries_WIRE_14.ae_final
connect entries_barrier_7.io.x.ae_ptw, _entries_WIRE_14.ae_ptw
connect entries_barrier_7.io.x.g, _entries_WIRE_14.g
connect entries_barrier_7.io.x.u, _entries_WIRE_14.u
connect entries_barrier_7.io.x.ppn, _entries_WIRE_14.ppn
wire _entries_WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_17 : UInt<42>
connect _entries_WIRE_17, superpage_entries[0].data[0]
node _entries_T_192 = bits(_entries_WIRE_17, 0, 0)
connect _entries_WIRE_16.fragmented_superpage, _entries_T_192
node _entries_T_193 = bits(_entries_WIRE_17, 1, 1)
connect _entries_WIRE_16.c, _entries_T_193
node _entries_T_194 = bits(_entries_WIRE_17, 2, 2)
connect _entries_WIRE_16.eff, _entries_T_194
node _entries_T_195 = bits(_entries_WIRE_17, 3, 3)
connect _entries_WIRE_16.paa, _entries_T_195
node _entries_T_196 = bits(_entries_WIRE_17, 4, 4)
connect _entries_WIRE_16.pal, _entries_T_196
node _entries_T_197 = bits(_entries_WIRE_17, 5, 5)
connect _entries_WIRE_16.ppp, _entries_T_197
node _entries_T_198 = bits(_entries_WIRE_17, 6, 6)
connect _entries_WIRE_16.pr, _entries_T_198
node _entries_T_199 = bits(_entries_WIRE_17, 7, 7)
connect _entries_WIRE_16.px, _entries_T_199
node _entries_T_200 = bits(_entries_WIRE_17, 8, 8)
connect _entries_WIRE_16.pw, _entries_T_200
node _entries_T_201 = bits(_entries_WIRE_17, 9, 9)
connect _entries_WIRE_16.hr, _entries_T_201
node _entries_T_202 = bits(_entries_WIRE_17, 10, 10)
connect _entries_WIRE_16.hx, _entries_T_202
node _entries_T_203 = bits(_entries_WIRE_17, 11, 11)
connect _entries_WIRE_16.hw, _entries_T_203
node _entries_T_204 = bits(_entries_WIRE_17, 12, 12)
connect _entries_WIRE_16.sr, _entries_T_204
node _entries_T_205 = bits(_entries_WIRE_17, 13, 13)
connect _entries_WIRE_16.sx, _entries_T_205
node _entries_T_206 = bits(_entries_WIRE_17, 14, 14)
connect _entries_WIRE_16.sw, _entries_T_206
node _entries_T_207 = bits(_entries_WIRE_17, 15, 15)
connect _entries_WIRE_16.gf, _entries_T_207
node _entries_T_208 = bits(_entries_WIRE_17, 16, 16)
connect _entries_WIRE_16.pf, _entries_T_208
node _entries_T_209 = bits(_entries_WIRE_17, 17, 17)
connect _entries_WIRE_16.ae_stage2, _entries_T_209
node _entries_T_210 = bits(_entries_WIRE_17, 18, 18)
connect _entries_WIRE_16.ae_final, _entries_T_210
node _entries_T_211 = bits(_entries_WIRE_17, 19, 19)
connect _entries_WIRE_16.ae_ptw, _entries_T_211
node _entries_T_212 = bits(_entries_WIRE_17, 20, 20)
connect _entries_WIRE_16.g, _entries_T_212
node _entries_T_213 = bits(_entries_WIRE_17, 21, 21)
connect _entries_WIRE_16.u, _entries_T_213
node _entries_T_214 = bits(_entries_WIRE_17, 41, 22)
connect _entries_WIRE_16.ppn, _entries_T_214
inst entries_barrier_8 of OptimizationBarrier_TLBEntryData_261
connect entries_barrier_8.clock, clock
connect entries_barrier_8.reset, reset
connect entries_barrier_8.io.x.fragmented_superpage, _entries_WIRE_16.fragmented_superpage
connect entries_barrier_8.io.x.c, _entries_WIRE_16.c
connect entries_barrier_8.io.x.eff, _entries_WIRE_16.eff
connect entries_barrier_8.io.x.paa, _entries_WIRE_16.paa
connect entries_barrier_8.io.x.pal, _entries_WIRE_16.pal
connect entries_barrier_8.io.x.ppp, _entries_WIRE_16.ppp
connect entries_barrier_8.io.x.pr, _entries_WIRE_16.pr
connect entries_barrier_8.io.x.px, _entries_WIRE_16.px
connect entries_barrier_8.io.x.pw, _entries_WIRE_16.pw
connect entries_barrier_8.io.x.hr, _entries_WIRE_16.hr
connect entries_barrier_8.io.x.hx, _entries_WIRE_16.hx
connect entries_barrier_8.io.x.hw, _entries_WIRE_16.hw
connect entries_barrier_8.io.x.sr, _entries_WIRE_16.sr
connect entries_barrier_8.io.x.sx, _entries_WIRE_16.sx
connect entries_barrier_8.io.x.sw, _entries_WIRE_16.sw
connect entries_barrier_8.io.x.gf, _entries_WIRE_16.gf
connect entries_barrier_8.io.x.pf, _entries_WIRE_16.pf
connect entries_barrier_8.io.x.ae_stage2, _entries_WIRE_16.ae_stage2
connect entries_barrier_8.io.x.ae_final, _entries_WIRE_16.ae_final
connect entries_barrier_8.io.x.ae_ptw, _entries_WIRE_16.ae_ptw
connect entries_barrier_8.io.x.g, _entries_WIRE_16.g
connect entries_barrier_8.io.x.u, _entries_WIRE_16.u
connect entries_barrier_8.io.x.ppn, _entries_WIRE_16.ppn
wire _entries_WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_19 : UInt<42>
connect _entries_WIRE_19, superpage_entries[1].data[0]
node _entries_T_215 = bits(_entries_WIRE_19, 0, 0)
connect _entries_WIRE_18.fragmented_superpage, _entries_T_215
node _entries_T_216 = bits(_entries_WIRE_19, 1, 1)
connect _entries_WIRE_18.c, _entries_T_216
node _entries_T_217 = bits(_entries_WIRE_19, 2, 2)
connect _entries_WIRE_18.eff, _entries_T_217
node _entries_T_218 = bits(_entries_WIRE_19, 3, 3)
connect _entries_WIRE_18.paa, _entries_T_218
node _entries_T_219 = bits(_entries_WIRE_19, 4, 4)
connect _entries_WIRE_18.pal, _entries_T_219
node _entries_T_220 = bits(_entries_WIRE_19, 5, 5)
connect _entries_WIRE_18.ppp, _entries_T_220
node _entries_T_221 = bits(_entries_WIRE_19, 6, 6)
connect _entries_WIRE_18.pr, _entries_T_221
node _entries_T_222 = bits(_entries_WIRE_19, 7, 7)
connect _entries_WIRE_18.px, _entries_T_222
node _entries_T_223 = bits(_entries_WIRE_19, 8, 8)
connect _entries_WIRE_18.pw, _entries_T_223
node _entries_T_224 = bits(_entries_WIRE_19, 9, 9)
connect _entries_WIRE_18.hr, _entries_T_224
node _entries_T_225 = bits(_entries_WIRE_19, 10, 10)
connect _entries_WIRE_18.hx, _entries_T_225
node _entries_T_226 = bits(_entries_WIRE_19, 11, 11)
connect _entries_WIRE_18.hw, _entries_T_226
node _entries_T_227 = bits(_entries_WIRE_19, 12, 12)
connect _entries_WIRE_18.sr, _entries_T_227
node _entries_T_228 = bits(_entries_WIRE_19, 13, 13)
connect _entries_WIRE_18.sx, _entries_T_228
node _entries_T_229 = bits(_entries_WIRE_19, 14, 14)
connect _entries_WIRE_18.sw, _entries_T_229
node _entries_T_230 = bits(_entries_WIRE_19, 15, 15)
connect _entries_WIRE_18.gf, _entries_T_230
node _entries_T_231 = bits(_entries_WIRE_19, 16, 16)
connect _entries_WIRE_18.pf, _entries_T_231
node _entries_T_232 = bits(_entries_WIRE_19, 17, 17)
connect _entries_WIRE_18.ae_stage2, _entries_T_232
node _entries_T_233 = bits(_entries_WIRE_19, 18, 18)
connect _entries_WIRE_18.ae_final, _entries_T_233
node _entries_T_234 = bits(_entries_WIRE_19, 19, 19)
connect _entries_WIRE_18.ae_ptw, _entries_T_234
node _entries_T_235 = bits(_entries_WIRE_19, 20, 20)
connect _entries_WIRE_18.g, _entries_T_235
node _entries_T_236 = bits(_entries_WIRE_19, 21, 21)
connect _entries_WIRE_18.u, _entries_T_236
node _entries_T_237 = bits(_entries_WIRE_19, 41, 22)
connect _entries_WIRE_18.ppn, _entries_T_237
inst entries_barrier_9 of OptimizationBarrier_TLBEntryData_262
connect entries_barrier_9.clock, clock
connect entries_barrier_9.reset, reset
connect entries_barrier_9.io.x.fragmented_superpage, _entries_WIRE_18.fragmented_superpage
connect entries_barrier_9.io.x.c, _entries_WIRE_18.c
connect entries_barrier_9.io.x.eff, _entries_WIRE_18.eff
connect entries_barrier_9.io.x.paa, _entries_WIRE_18.paa
connect entries_barrier_9.io.x.pal, _entries_WIRE_18.pal
connect entries_barrier_9.io.x.ppp, _entries_WIRE_18.ppp
connect entries_barrier_9.io.x.pr, _entries_WIRE_18.pr
connect entries_barrier_9.io.x.px, _entries_WIRE_18.px
connect entries_barrier_9.io.x.pw, _entries_WIRE_18.pw
connect entries_barrier_9.io.x.hr, _entries_WIRE_18.hr
connect entries_barrier_9.io.x.hx, _entries_WIRE_18.hx
connect entries_barrier_9.io.x.hw, _entries_WIRE_18.hw
connect entries_barrier_9.io.x.sr, _entries_WIRE_18.sr
connect entries_barrier_9.io.x.sx, _entries_WIRE_18.sx
connect entries_barrier_9.io.x.sw, _entries_WIRE_18.sw
connect entries_barrier_9.io.x.gf, _entries_WIRE_18.gf
connect entries_barrier_9.io.x.pf, _entries_WIRE_18.pf
connect entries_barrier_9.io.x.ae_stage2, _entries_WIRE_18.ae_stage2
connect entries_barrier_9.io.x.ae_final, _entries_WIRE_18.ae_final
connect entries_barrier_9.io.x.ae_ptw, _entries_WIRE_18.ae_ptw
connect entries_barrier_9.io.x.g, _entries_WIRE_18.g
connect entries_barrier_9.io.x.u, _entries_WIRE_18.u
connect entries_barrier_9.io.x.ppn, _entries_WIRE_18.ppn
wire _entries_WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_21 : UInt<42>
connect _entries_WIRE_21, superpage_entries[2].data[0]
node _entries_T_238 = bits(_entries_WIRE_21, 0, 0)
connect _entries_WIRE_20.fragmented_superpage, _entries_T_238
node _entries_T_239 = bits(_entries_WIRE_21, 1, 1)
connect _entries_WIRE_20.c, _entries_T_239
node _entries_T_240 = bits(_entries_WIRE_21, 2, 2)
connect _entries_WIRE_20.eff, _entries_T_240
node _entries_T_241 = bits(_entries_WIRE_21, 3, 3)
connect _entries_WIRE_20.paa, _entries_T_241
node _entries_T_242 = bits(_entries_WIRE_21, 4, 4)
connect _entries_WIRE_20.pal, _entries_T_242
node _entries_T_243 = bits(_entries_WIRE_21, 5, 5)
connect _entries_WIRE_20.ppp, _entries_T_243
node _entries_T_244 = bits(_entries_WIRE_21, 6, 6)
connect _entries_WIRE_20.pr, _entries_T_244
node _entries_T_245 = bits(_entries_WIRE_21, 7, 7)
connect _entries_WIRE_20.px, _entries_T_245
node _entries_T_246 = bits(_entries_WIRE_21, 8, 8)
connect _entries_WIRE_20.pw, _entries_T_246
node _entries_T_247 = bits(_entries_WIRE_21, 9, 9)
connect _entries_WIRE_20.hr, _entries_T_247
node _entries_T_248 = bits(_entries_WIRE_21, 10, 10)
connect _entries_WIRE_20.hx, _entries_T_248
node _entries_T_249 = bits(_entries_WIRE_21, 11, 11)
connect _entries_WIRE_20.hw, _entries_T_249
node _entries_T_250 = bits(_entries_WIRE_21, 12, 12)
connect _entries_WIRE_20.sr, _entries_T_250
node _entries_T_251 = bits(_entries_WIRE_21, 13, 13)
connect _entries_WIRE_20.sx, _entries_T_251
node _entries_T_252 = bits(_entries_WIRE_21, 14, 14)
connect _entries_WIRE_20.sw, _entries_T_252
node _entries_T_253 = bits(_entries_WIRE_21, 15, 15)
connect _entries_WIRE_20.gf, _entries_T_253
node _entries_T_254 = bits(_entries_WIRE_21, 16, 16)
connect _entries_WIRE_20.pf, _entries_T_254
node _entries_T_255 = bits(_entries_WIRE_21, 17, 17)
connect _entries_WIRE_20.ae_stage2, _entries_T_255
node _entries_T_256 = bits(_entries_WIRE_21, 18, 18)
connect _entries_WIRE_20.ae_final, _entries_T_256
node _entries_T_257 = bits(_entries_WIRE_21, 19, 19)
connect _entries_WIRE_20.ae_ptw, _entries_T_257
node _entries_T_258 = bits(_entries_WIRE_21, 20, 20)
connect _entries_WIRE_20.g, _entries_T_258
node _entries_T_259 = bits(_entries_WIRE_21, 21, 21)
connect _entries_WIRE_20.u, _entries_T_259
node _entries_T_260 = bits(_entries_WIRE_21, 41, 22)
connect _entries_WIRE_20.ppn, _entries_T_260
inst entries_barrier_10 of OptimizationBarrier_TLBEntryData_263
connect entries_barrier_10.clock, clock
connect entries_barrier_10.reset, reset
connect entries_barrier_10.io.x.fragmented_superpage, _entries_WIRE_20.fragmented_superpage
connect entries_barrier_10.io.x.c, _entries_WIRE_20.c
connect entries_barrier_10.io.x.eff, _entries_WIRE_20.eff
connect entries_barrier_10.io.x.paa, _entries_WIRE_20.paa
connect entries_barrier_10.io.x.pal, _entries_WIRE_20.pal
connect entries_barrier_10.io.x.ppp, _entries_WIRE_20.ppp
connect entries_barrier_10.io.x.pr, _entries_WIRE_20.pr
connect entries_barrier_10.io.x.px, _entries_WIRE_20.px
connect entries_barrier_10.io.x.pw, _entries_WIRE_20.pw
connect entries_barrier_10.io.x.hr, _entries_WIRE_20.hr
connect entries_barrier_10.io.x.hx, _entries_WIRE_20.hx
connect entries_barrier_10.io.x.hw, _entries_WIRE_20.hw
connect entries_barrier_10.io.x.sr, _entries_WIRE_20.sr
connect entries_barrier_10.io.x.sx, _entries_WIRE_20.sx
connect entries_barrier_10.io.x.sw, _entries_WIRE_20.sw
connect entries_barrier_10.io.x.gf, _entries_WIRE_20.gf
connect entries_barrier_10.io.x.pf, _entries_WIRE_20.pf
connect entries_barrier_10.io.x.ae_stage2, _entries_WIRE_20.ae_stage2
connect entries_barrier_10.io.x.ae_final, _entries_WIRE_20.ae_final
connect entries_barrier_10.io.x.ae_ptw, _entries_WIRE_20.ae_ptw
connect entries_barrier_10.io.x.g, _entries_WIRE_20.g
connect entries_barrier_10.io.x.u, _entries_WIRE_20.u
connect entries_barrier_10.io.x.ppn, _entries_WIRE_20.ppn
wire _entries_WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_23 : UInt<42>
connect _entries_WIRE_23, superpage_entries[3].data[0]
node _entries_T_261 = bits(_entries_WIRE_23, 0, 0)
connect _entries_WIRE_22.fragmented_superpage, _entries_T_261
node _entries_T_262 = bits(_entries_WIRE_23, 1, 1)
connect _entries_WIRE_22.c, _entries_T_262
node _entries_T_263 = bits(_entries_WIRE_23, 2, 2)
connect _entries_WIRE_22.eff, _entries_T_263
node _entries_T_264 = bits(_entries_WIRE_23, 3, 3)
connect _entries_WIRE_22.paa, _entries_T_264
node _entries_T_265 = bits(_entries_WIRE_23, 4, 4)
connect _entries_WIRE_22.pal, _entries_T_265
node _entries_T_266 = bits(_entries_WIRE_23, 5, 5)
connect _entries_WIRE_22.ppp, _entries_T_266
node _entries_T_267 = bits(_entries_WIRE_23, 6, 6)
connect _entries_WIRE_22.pr, _entries_T_267
node _entries_T_268 = bits(_entries_WIRE_23, 7, 7)
connect _entries_WIRE_22.px, _entries_T_268
node _entries_T_269 = bits(_entries_WIRE_23, 8, 8)
connect _entries_WIRE_22.pw, _entries_T_269
node _entries_T_270 = bits(_entries_WIRE_23, 9, 9)
connect _entries_WIRE_22.hr, _entries_T_270
node _entries_T_271 = bits(_entries_WIRE_23, 10, 10)
connect _entries_WIRE_22.hx, _entries_T_271
node _entries_T_272 = bits(_entries_WIRE_23, 11, 11)
connect _entries_WIRE_22.hw, _entries_T_272
node _entries_T_273 = bits(_entries_WIRE_23, 12, 12)
connect _entries_WIRE_22.sr, _entries_T_273
node _entries_T_274 = bits(_entries_WIRE_23, 13, 13)
connect _entries_WIRE_22.sx, _entries_T_274
node _entries_T_275 = bits(_entries_WIRE_23, 14, 14)
connect _entries_WIRE_22.sw, _entries_T_275
node _entries_T_276 = bits(_entries_WIRE_23, 15, 15)
connect _entries_WIRE_22.gf, _entries_T_276
node _entries_T_277 = bits(_entries_WIRE_23, 16, 16)
connect _entries_WIRE_22.pf, _entries_T_277
node _entries_T_278 = bits(_entries_WIRE_23, 17, 17)
connect _entries_WIRE_22.ae_stage2, _entries_T_278
node _entries_T_279 = bits(_entries_WIRE_23, 18, 18)
connect _entries_WIRE_22.ae_final, _entries_T_279
node _entries_T_280 = bits(_entries_WIRE_23, 19, 19)
connect _entries_WIRE_22.ae_ptw, _entries_T_280
node _entries_T_281 = bits(_entries_WIRE_23, 20, 20)
connect _entries_WIRE_22.g, _entries_T_281
node _entries_T_282 = bits(_entries_WIRE_23, 21, 21)
connect _entries_WIRE_22.u, _entries_T_282
node _entries_T_283 = bits(_entries_WIRE_23, 41, 22)
connect _entries_WIRE_22.ppn, _entries_T_283
inst entries_barrier_11 of OptimizationBarrier_TLBEntryData_264
connect entries_barrier_11.clock, clock
connect entries_barrier_11.reset, reset
connect entries_barrier_11.io.x.fragmented_superpage, _entries_WIRE_22.fragmented_superpage
connect entries_barrier_11.io.x.c, _entries_WIRE_22.c
connect entries_barrier_11.io.x.eff, _entries_WIRE_22.eff
connect entries_barrier_11.io.x.paa, _entries_WIRE_22.paa
connect entries_barrier_11.io.x.pal, _entries_WIRE_22.pal
connect entries_barrier_11.io.x.ppp, _entries_WIRE_22.ppp
connect entries_barrier_11.io.x.pr, _entries_WIRE_22.pr
connect entries_barrier_11.io.x.px, _entries_WIRE_22.px
connect entries_barrier_11.io.x.pw, _entries_WIRE_22.pw
connect entries_barrier_11.io.x.hr, _entries_WIRE_22.hr
connect entries_barrier_11.io.x.hx, _entries_WIRE_22.hx
connect entries_barrier_11.io.x.hw, _entries_WIRE_22.hw
connect entries_barrier_11.io.x.sr, _entries_WIRE_22.sr
connect entries_barrier_11.io.x.sx, _entries_WIRE_22.sx
connect entries_barrier_11.io.x.sw, _entries_WIRE_22.sw
connect entries_barrier_11.io.x.gf, _entries_WIRE_22.gf
connect entries_barrier_11.io.x.pf, _entries_WIRE_22.pf
connect entries_barrier_11.io.x.ae_stage2, _entries_WIRE_22.ae_stage2
connect entries_barrier_11.io.x.ae_final, _entries_WIRE_22.ae_final
connect entries_barrier_11.io.x.ae_ptw, _entries_WIRE_22.ae_ptw
connect entries_barrier_11.io.x.g, _entries_WIRE_22.g
connect entries_barrier_11.io.x.u, _entries_WIRE_22.u
connect entries_barrier_11.io.x.ppn, _entries_WIRE_22.ppn
wire _entries_WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_25 : UInt<42>
connect _entries_WIRE_25, special_entry.data[0]
node _entries_T_284 = bits(_entries_WIRE_25, 0, 0)
connect _entries_WIRE_24.fragmented_superpage, _entries_T_284
node _entries_T_285 = bits(_entries_WIRE_25, 1, 1)
connect _entries_WIRE_24.c, _entries_T_285
node _entries_T_286 = bits(_entries_WIRE_25, 2, 2)
connect _entries_WIRE_24.eff, _entries_T_286
node _entries_T_287 = bits(_entries_WIRE_25, 3, 3)
connect _entries_WIRE_24.paa, _entries_T_287
node _entries_T_288 = bits(_entries_WIRE_25, 4, 4)
connect _entries_WIRE_24.pal, _entries_T_288
node _entries_T_289 = bits(_entries_WIRE_25, 5, 5)
connect _entries_WIRE_24.ppp, _entries_T_289
node _entries_T_290 = bits(_entries_WIRE_25, 6, 6)
connect _entries_WIRE_24.pr, _entries_T_290
node _entries_T_291 = bits(_entries_WIRE_25, 7, 7)
connect _entries_WIRE_24.px, _entries_T_291
node _entries_T_292 = bits(_entries_WIRE_25, 8, 8)
connect _entries_WIRE_24.pw, _entries_T_292
node _entries_T_293 = bits(_entries_WIRE_25, 9, 9)
connect _entries_WIRE_24.hr, _entries_T_293
node _entries_T_294 = bits(_entries_WIRE_25, 10, 10)
connect _entries_WIRE_24.hx, _entries_T_294
node _entries_T_295 = bits(_entries_WIRE_25, 11, 11)
connect _entries_WIRE_24.hw, _entries_T_295
node _entries_T_296 = bits(_entries_WIRE_25, 12, 12)
connect _entries_WIRE_24.sr, _entries_T_296
node _entries_T_297 = bits(_entries_WIRE_25, 13, 13)
connect _entries_WIRE_24.sx, _entries_T_297
node _entries_T_298 = bits(_entries_WIRE_25, 14, 14)
connect _entries_WIRE_24.sw, _entries_T_298
node _entries_T_299 = bits(_entries_WIRE_25, 15, 15)
connect _entries_WIRE_24.gf, _entries_T_299
node _entries_T_300 = bits(_entries_WIRE_25, 16, 16)
connect _entries_WIRE_24.pf, _entries_T_300
node _entries_T_301 = bits(_entries_WIRE_25, 17, 17)
connect _entries_WIRE_24.ae_stage2, _entries_T_301
node _entries_T_302 = bits(_entries_WIRE_25, 18, 18)
connect _entries_WIRE_24.ae_final, _entries_T_302
node _entries_T_303 = bits(_entries_WIRE_25, 19, 19)
connect _entries_WIRE_24.ae_ptw, _entries_T_303
node _entries_T_304 = bits(_entries_WIRE_25, 20, 20)
connect _entries_WIRE_24.g, _entries_T_304
node _entries_T_305 = bits(_entries_WIRE_25, 21, 21)
connect _entries_WIRE_24.u, _entries_T_305
node _entries_T_306 = bits(_entries_WIRE_25, 41, 22)
connect _entries_WIRE_24.ppn, _entries_T_306
inst entries_barrier_12 of OptimizationBarrier_TLBEntryData_265
connect entries_barrier_12.clock, clock
connect entries_barrier_12.reset, reset
connect entries_barrier_12.io.x.fragmented_superpage, _entries_WIRE_24.fragmented_superpage
connect entries_barrier_12.io.x.c, _entries_WIRE_24.c
connect entries_barrier_12.io.x.eff, _entries_WIRE_24.eff
connect entries_barrier_12.io.x.paa, _entries_WIRE_24.paa
connect entries_barrier_12.io.x.pal, _entries_WIRE_24.pal
connect entries_barrier_12.io.x.ppp, _entries_WIRE_24.ppp
connect entries_barrier_12.io.x.pr, _entries_WIRE_24.pr
connect entries_barrier_12.io.x.px, _entries_WIRE_24.px
connect entries_barrier_12.io.x.pw, _entries_WIRE_24.pw
connect entries_barrier_12.io.x.hr, _entries_WIRE_24.hr
connect entries_barrier_12.io.x.hx, _entries_WIRE_24.hx
connect entries_barrier_12.io.x.hw, _entries_WIRE_24.hw
connect entries_barrier_12.io.x.sr, _entries_WIRE_24.sr
connect entries_barrier_12.io.x.sx, _entries_WIRE_24.sx
connect entries_barrier_12.io.x.sw, _entries_WIRE_24.sw
connect entries_barrier_12.io.x.gf, _entries_WIRE_24.gf
connect entries_barrier_12.io.x.pf, _entries_WIRE_24.pf
connect entries_barrier_12.io.x.ae_stage2, _entries_WIRE_24.ae_stage2
connect entries_barrier_12.io.x.ae_final, _entries_WIRE_24.ae_final
connect entries_barrier_12.io.x.ae_ptw, _entries_WIRE_24.ae_ptw
connect entries_barrier_12.io.x.g, _entries_WIRE_24.g
connect entries_barrier_12.io.x.u, _entries_WIRE_24.u
connect entries_barrier_12.io.x.ppn, _entries_WIRE_24.ppn
node _ppn_T = eq(vm_enabled, UInt<1>(0h0))
node ppn_res = shr(entries_barrier_8.io.y.ppn, 18)
node _ppn_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h1))
node ppn_ignore = or(_ppn_ignore_T, UInt<1>(0h0))
node _ppn_T_1 = mux(ppn_ignore, vpn, UInt<1>(0h0))
node _ppn_T_2 = or(_ppn_T_1, entries_barrier_8.io.y.ppn)
node _ppn_T_3 = bits(_ppn_T_2, 17, 9)
node _ppn_T_4 = cat(ppn_res, _ppn_T_3)
node _ppn_ignore_T_1 = lt(superpage_entries[0].level, UInt<2>(0h2))
node ppn_ignore_1 = or(_ppn_ignore_T_1, UInt<1>(0h1))
node _ppn_T_5 = mux(ppn_ignore_1, vpn, UInt<1>(0h0))
node _ppn_T_6 = or(_ppn_T_5, entries_barrier_8.io.y.ppn)
node _ppn_T_7 = bits(_ppn_T_6, 8, 0)
node _ppn_T_8 = cat(_ppn_T_4, _ppn_T_7)
node ppn_res_1 = shr(entries_barrier_9.io.y.ppn, 18)
node _ppn_ignore_T_2 = lt(superpage_entries[1].level, UInt<1>(0h1))
node ppn_ignore_2 = or(_ppn_ignore_T_2, UInt<1>(0h0))
node _ppn_T_9 = mux(ppn_ignore_2, vpn, UInt<1>(0h0))
node _ppn_T_10 = or(_ppn_T_9, entries_barrier_9.io.y.ppn)
node _ppn_T_11 = bits(_ppn_T_10, 17, 9)
node _ppn_T_12 = cat(ppn_res_1, _ppn_T_11)
node _ppn_ignore_T_3 = lt(superpage_entries[1].level, UInt<2>(0h2))
node ppn_ignore_3 = or(_ppn_ignore_T_3, UInt<1>(0h1))
node _ppn_T_13 = mux(ppn_ignore_3, vpn, UInt<1>(0h0))
node _ppn_T_14 = or(_ppn_T_13, entries_barrier_9.io.y.ppn)
node _ppn_T_15 = bits(_ppn_T_14, 8, 0)
node _ppn_T_16 = cat(_ppn_T_12, _ppn_T_15)
node ppn_res_2 = shr(entries_barrier_10.io.y.ppn, 18)
node _ppn_ignore_T_4 = lt(superpage_entries[2].level, UInt<1>(0h1))
node ppn_ignore_4 = or(_ppn_ignore_T_4, UInt<1>(0h0))
node _ppn_T_17 = mux(ppn_ignore_4, vpn, UInt<1>(0h0))
node _ppn_T_18 = or(_ppn_T_17, entries_barrier_10.io.y.ppn)
node _ppn_T_19 = bits(_ppn_T_18, 17, 9)
node _ppn_T_20 = cat(ppn_res_2, _ppn_T_19)
node _ppn_ignore_T_5 = lt(superpage_entries[2].level, UInt<2>(0h2))
node ppn_ignore_5 = or(_ppn_ignore_T_5, UInt<1>(0h1))
node _ppn_T_21 = mux(ppn_ignore_5, vpn, UInt<1>(0h0))
node _ppn_T_22 = or(_ppn_T_21, entries_barrier_10.io.y.ppn)
node _ppn_T_23 = bits(_ppn_T_22, 8, 0)
node _ppn_T_24 = cat(_ppn_T_20, _ppn_T_23)
node ppn_res_3 = shr(entries_barrier_11.io.y.ppn, 18)
node _ppn_ignore_T_6 = lt(superpage_entries[3].level, UInt<1>(0h1))
node ppn_ignore_6 = or(_ppn_ignore_T_6, UInt<1>(0h0))
node _ppn_T_25 = mux(ppn_ignore_6, vpn, UInt<1>(0h0))
node _ppn_T_26 = or(_ppn_T_25, entries_barrier_11.io.y.ppn)
node _ppn_T_27 = bits(_ppn_T_26, 17, 9)
node _ppn_T_28 = cat(ppn_res_3, _ppn_T_27)
node _ppn_ignore_T_7 = lt(superpage_entries[3].level, UInt<2>(0h2))
node ppn_ignore_7 = or(_ppn_ignore_T_7, UInt<1>(0h1))
node _ppn_T_29 = mux(ppn_ignore_7, vpn, UInt<1>(0h0))
node _ppn_T_30 = or(_ppn_T_29, entries_barrier_11.io.y.ppn)
node _ppn_T_31 = bits(_ppn_T_30, 8, 0)
node _ppn_T_32 = cat(_ppn_T_28, _ppn_T_31)
node ppn_res_4 = shr(entries_barrier_12.io.y.ppn, 18)
node _ppn_ignore_T_8 = lt(special_entry.level, UInt<1>(0h1))
node ppn_ignore_8 = or(_ppn_ignore_T_8, UInt<1>(0h0))
node _ppn_T_33 = mux(ppn_ignore_8, vpn, UInt<1>(0h0))
node _ppn_T_34 = or(_ppn_T_33, entries_barrier_12.io.y.ppn)
node _ppn_T_35 = bits(_ppn_T_34, 17, 9)
node _ppn_T_36 = cat(ppn_res_4, _ppn_T_35)
node _ppn_ignore_T_9 = lt(special_entry.level, UInt<2>(0h2))
node ppn_ignore_9 = or(_ppn_ignore_T_9, UInt<1>(0h0))
node _ppn_T_37 = mux(ppn_ignore_9, vpn, UInt<1>(0h0))
node _ppn_T_38 = or(_ppn_T_37, entries_barrier_12.io.y.ppn)
node _ppn_T_39 = bits(_ppn_T_38, 8, 0)
node _ppn_T_40 = cat(_ppn_T_36, _ppn_T_39)
node _ppn_T_41 = bits(vpn, 19, 0)
node _ppn_T_42 = mux(hitsVec_0, entries_barrier.io.y.ppn, UInt<1>(0h0))
node _ppn_T_43 = mux(hitsVec_1, entries_barrier_1.io.y.ppn, UInt<1>(0h0))
node _ppn_T_44 = mux(hitsVec_2, entries_barrier_2.io.y.ppn, UInt<1>(0h0))
node _ppn_T_45 = mux(hitsVec_3, entries_barrier_3.io.y.ppn, UInt<1>(0h0))
node _ppn_T_46 = mux(hitsVec_4, entries_barrier_4.io.y.ppn, UInt<1>(0h0))
node _ppn_T_47 = mux(hitsVec_5, entries_barrier_5.io.y.ppn, UInt<1>(0h0))
node _ppn_T_48 = mux(hitsVec_6, entries_barrier_6.io.y.ppn, UInt<1>(0h0))
node _ppn_T_49 = mux(hitsVec_7, entries_barrier_7.io.y.ppn, UInt<1>(0h0))
node _ppn_T_50 = mux(hitsVec_8, _ppn_T_8, UInt<1>(0h0))
node _ppn_T_51 = mux(hitsVec_9, _ppn_T_16, UInt<1>(0h0))
node _ppn_T_52 = mux(hitsVec_10, _ppn_T_24, UInt<1>(0h0))
node _ppn_T_53 = mux(hitsVec_11, _ppn_T_32, UInt<1>(0h0))
node _ppn_T_54 = mux(hitsVec_12, _ppn_T_40, UInt<1>(0h0))
node _ppn_T_55 = mux(_ppn_T, _ppn_T_41, UInt<1>(0h0))
node _ppn_T_56 = or(_ppn_T_42, _ppn_T_43)
node _ppn_T_57 = or(_ppn_T_56, _ppn_T_44)
node _ppn_T_58 = or(_ppn_T_57, _ppn_T_45)
node _ppn_T_59 = or(_ppn_T_58, _ppn_T_46)
node _ppn_T_60 = or(_ppn_T_59, _ppn_T_47)
node _ppn_T_61 = or(_ppn_T_60, _ppn_T_48)
node _ppn_T_62 = or(_ppn_T_61, _ppn_T_49)
node _ppn_T_63 = or(_ppn_T_62, _ppn_T_50)
node _ppn_T_64 = or(_ppn_T_63, _ppn_T_51)
node _ppn_T_65 = or(_ppn_T_64, _ppn_T_52)
node _ppn_T_66 = or(_ppn_T_65, _ppn_T_53)
node _ppn_T_67 = or(_ppn_T_66, _ppn_T_54)
node _ppn_T_68 = or(_ppn_T_67, _ppn_T_55)
wire ppn : UInt<20>
connect ppn, _ppn_T_68
node ptw_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_ptw, entries_barrier_1.io.y.ae_ptw)
node ptw_ae_array_lo_lo = cat(ptw_ae_array_lo_lo_hi, entries_barrier.io.y.ae_ptw)
node ptw_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_ptw, entries_barrier_4.io.y.ae_ptw)
node ptw_ae_array_lo_hi = cat(ptw_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_ptw)
node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, ptw_ae_array_lo_lo)
node ptw_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_ptw, entries_barrier_7.io.y.ae_ptw)
node ptw_ae_array_hi_lo = cat(ptw_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_ptw)
node ptw_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_ptw, entries_barrier_9.io.y.ae_ptw)
node ptw_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_ptw, entries_barrier_11.io.y.ae_ptw)
node ptw_ae_array_hi_hi = cat(ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo)
node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, ptw_ae_array_hi_lo)
node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo)
node ptw_ae_array = cat(UInt<1>(0h0), _ptw_ae_array_T)
node final_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_final, entries_barrier_1.io.y.ae_final)
node final_ae_array_lo_lo = cat(final_ae_array_lo_lo_hi, entries_barrier.io.y.ae_final)
node final_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_final, entries_barrier_4.io.y.ae_final)
node final_ae_array_lo_hi = cat(final_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_final)
node final_ae_array_lo = cat(final_ae_array_lo_hi, final_ae_array_lo_lo)
node final_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_final, entries_barrier_7.io.y.ae_final)
node final_ae_array_hi_lo = cat(final_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_final)
node final_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_final, entries_barrier_9.io.y.ae_final)
node final_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_final, entries_barrier_11.io.y.ae_final)
node final_ae_array_hi_hi = cat(final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo)
node final_ae_array_hi = cat(final_ae_array_hi_hi, final_ae_array_hi_lo)
node _final_ae_array_T = cat(final_ae_array_hi, final_ae_array_lo)
node final_ae_array = cat(UInt<1>(0h0), _final_ae_array_T)
node ptw_pf_array_lo_lo_hi = cat(entries_barrier_2.io.y.pf, entries_barrier_1.io.y.pf)
node ptw_pf_array_lo_lo = cat(ptw_pf_array_lo_lo_hi, entries_barrier.io.y.pf)
node ptw_pf_array_lo_hi_hi = cat(entries_barrier_5.io.y.pf, entries_barrier_4.io.y.pf)
node ptw_pf_array_lo_hi = cat(ptw_pf_array_lo_hi_hi, entries_barrier_3.io.y.pf)
node ptw_pf_array_lo = cat(ptw_pf_array_lo_hi, ptw_pf_array_lo_lo)
node ptw_pf_array_hi_lo_hi = cat(entries_barrier_8.io.y.pf, entries_barrier_7.io.y.pf)
node ptw_pf_array_hi_lo = cat(ptw_pf_array_hi_lo_hi, entries_barrier_6.io.y.pf)
node ptw_pf_array_hi_hi_lo = cat(entries_barrier_10.io.y.pf, entries_barrier_9.io.y.pf)
node ptw_pf_array_hi_hi_hi = cat(entries_barrier_12.io.y.pf, entries_barrier_11.io.y.pf)
node ptw_pf_array_hi_hi = cat(ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo)
node ptw_pf_array_hi = cat(ptw_pf_array_hi_hi, ptw_pf_array_hi_lo)
node _ptw_pf_array_T = cat(ptw_pf_array_hi, ptw_pf_array_lo)
node ptw_pf_array = cat(UInt<1>(0h0), _ptw_pf_array_T)
node ptw_gf_array_lo_lo_hi = cat(entries_barrier_2.io.y.gf, entries_barrier_1.io.y.gf)
node ptw_gf_array_lo_lo = cat(ptw_gf_array_lo_lo_hi, entries_barrier.io.y.gf)
node ptw_gf_array_lo_hi_hi = cat(entries_barrier_5.io.y.gf, entries_barrier_4.io.y.gf)
node ptw_gf_array_lo_hi = cat(ptw_gf_array_lo_hi_hi, entries_barrier_3.io.y.gf)
node ptw_gf_array_lo = cat(ptw_gf_array_lo_hi, ptw_gf_array_lo_lo)
node ptw_gf_array_hi_lo_hi = cat(entries_barrier_8.io.y.gf, entries_barrier_7.io.y.gf)
node ptw_gf_array_hi_lo = cat(ptw_gf_array_hi_lo_hi, entries_barrier_6.io.y.gf)
node ptw_gf_array_hi_hi_lo = cat(entries_barrier_10.io.y.gf, entries_barrier_9.io.y.gf)
node ptw_gf_array_hi_hi_hi = cat(entries_barrier_12.io.y.gf, entries_barrier_11.io.y.gf)
node ptw_gf_array_hi_hi = cat(ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo)
node ptw_gf_array_hi = cat(ptw_gf_array_hi_hi, ptw_gf_array_hi_lo)
node _ptw_gf_array_T = cat(ptw_gf_array_hi, ptw_gf_array_lo)
node ptw_gf_array = cat(UInt<1>(0h0), _ptw_gf_array_T)
node sum = mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum)
node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0))
node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, sum)
node priv_rw_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u)
node priv_rw_ok_lo_lo = cat(priv_rw_ok_lo_lo_hi, entries_barrier.io.y.u)
node priv_rw_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u)
node priv_rw_ok_lo_hi = cat(priv_rw_ok_lo_hi_hi, entries_barrier_3.io.y.u)
node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, priv_rw_ok_lo_lo)
node priv_rw_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u)
node priv_rw_ok_hi_lo = cat(priv_rw_ok_hi_lo_hi, entries_barrier_6.io.y.u)
node priv_rw_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u)
node priv_rw_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u)
node priv_rw_ok_hi_hi = cat(priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo)
node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, priv_rw_ok_hi_lo)
node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo)
node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0))
node priv_rw_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u)
node priv_rw_ok_lo_lo_1 = cat(priv_rw_ok_lo_lo_hi_1, entries_barrier.io.y.u)
node priv_rw_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u)
node priv_rw_ok_lo_hi_1 = cat(priv_rw_ok_lo_hi_hi_1, entries_barrier_3.io.y.u)
node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1)
node priv_rw_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u)
node priv_rw_ok_hi_lo_1 = cat(priv_rw_ok_hi_lo_hi_1, entries_barrier_6.io.y.u)
node priv_rw_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u)
node priv_rw_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u)
node priv_rw_ok_hi_hi_1 = cat(priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1)
node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1)
node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1)
node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4)
node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0))
node priv_rw_ok = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6)
node priv_x_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u)
node priv_x_ok_lo_lo = cat(priv_x_ok_lo_lo_hi, entries_barrier.io.y.u)
node priv_x_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u)
node priv_x_ok_lo_hi = cat(priv_x_ok_lo_hi_hi, entries_barrier_3.io.y.u)
node priv_x_ok_lo = cat(priv_x_ok_lo_hi, priv_x_ok_lo_lo)
node priv_x_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u)
node priv_x_ok_hi_lo = cat(priv_x_ok_hi_lo_hi, entries_barrier_6.io.y.u)
node priv_x_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u)
node priv_x_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u)
node priv_x_ok_hi_hi = cat(priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo)
node priv_x_ok_hi = cat(priv_x_ok_hi_hi, priv_x_ok_hi_lo)
node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo)
node _priv_x_ok_T_1 = not(_priv_x_ok_T)
node priv_x_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u)
node priv_x_ok_lo_lo_1 = cat(priv_x_ok_lo_lo_hi_1, entries_barrier.io.y.u)
node priv_x_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u)
node priv_x_ok_lo_hi_1 = cat(priv_x_ok_lo_hi_hi_1, entries_barrier_3.io.y.u)
node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1)
node priv_x_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u)
node priv_x_ok_hi_lo_1 = cat(priv_x_ok_hi_lo_hi_1, entries_barrier_6.io.y.u)
node priv_x_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u)
node priv_x_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u)
node priv_x_ok_hi_hi_1 = cat(priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1)
node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1)
node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1)
node priv_x_ok = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2)
node _stage1_bypass_T = mux(UInt<1>(0h0), UInt<13>(0h1fff), UInt<13>(0h0))
node _stage1_bypass_T_1 = eq(stage1_en, UInt<1>(0h0))
node _stage1_bypass_T_2 = mux(_stage1_bypass_T_1, UInt<13>(0h1fff), UInt<13>(0h0))
node stage1_bypass_lo_lo_hi = cat(entries_barrier_2.io.y.ae_stage2, entries_barrier_1.io.y.ae_stage2)
node stage1_bypass_lo_lo = cat(stage1_bypass_lo_lo_hi, entries_barrier.io.y.ae_stage2)
node stage1_bypass_lo_hi_hi = cat(entries_barrier_5.io.y.ae_stage2, entries_barrier_4.io.y.ae_stage2)
node stage1_bypass_lo_hi = cat(stage1_bypass_lo_hi_hi, entries_barrier_3.io.y.ae_stage2)
node stage1_bypass_lo = cat(stage1_bypass_lo_hi, stage1_bypass_lo_lo)
node stage1_bypass_hi_lo_hi = cat(entries_barrier_8.io.y.ae_stage2, entries_barrier_7.io.y.ae_stage2)
node stage1_bypass_hi_lo = cat(stage1_bypass_hi_lo_hi, entries_barrier_6.io.y.ae_stage2)
node stage1_bypass_hi_hi_lo = cat(entries_barrier_10.io.y.ae_stage2, entries_barrier_9.io.y.ae_stage2)
node stage1_bypass_hi_hi_hi = cat(entries_barrier_12.io.y.ae_stage2, entries_barrier_11.io.y.ae_stage2)
node stage1_bypass_hi_hi = cat(stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo)
node stage1_bypass_hi = cat(stage1_bypass_hi_hi, stage1_bypass_hi_lo)
node _stage1_bypass_T_3 = cat(stage1_bypass_hi, stage1_bypass_lo)
node _stage1_bypass_T_4 = or(_stage1_bypass_T_2, _stage1_bypass_T_3)
node stage1_bypass = and(_stage1_bypass_T, _stage1_bypass_T_4)
node _mxr_T = mux(priv_v, io.ptw.gstatus.mxr, UInt<1>(0h0))
node mxr = or(io.ptw.status.mxr, _mxr_T)
node r_array_lo_lo_hi = cat(entries_barrier_2.io.y.sr, entries_barrier_1.io.y.sr)
node r_array_lo_lo = cat(r_array_lo_lo_hi, entries_barrier.io.y.sr)
node r_array_lo_hi_hi = cat(entries_barrier_5.io.y.sr, entries_barrier_4.io.y.sr)
node r_array_lo_hi = cat(r_array_lo_hi_hi, entries_barrier_3.io.y.sr)
node r_array_lo = cat(r_array_lo_hi, r_array_lo_lo)
node r_array_hi_lo_hi = cat(entries_barrier_8.io.y.sr, entries_barrier_7.io.y.sr)
node r_array_hi_lo = cat(r_array_hi_lo_hi, entries_barrier_6.io.y.sr)
node r_array_hi_hi_lo = cat(entries_barrier_10.io.y.sr, entries_barrier_9.io.y.sr)
node r_array_hi_hi_hi = cat(entries_barrier_12.io.y.sr, entries_barrier_11.io.y.sr)
node r_array_hi_hi = cat(r_array_hi_hi_hi, r_array_hi_hi_lo)
node r_array_hi = cat(r_array_hi_hi, r_array_hi_lo)
node _r_array_T = cat(r_array_hi, r_array_lo)
node r_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx)
node r_array_lo_lo_1 = cat(r_array_lo_lo_hi_1, entries_barrier.io.y.sx)
node r_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx)
node r_array_lo_hi_1 = cat(r_array_lo_hi_hi_1, entries_barrier_3.io.y.sx)
node r_array_lo_1 = cat(r_array_lo_hi_1, r_array_lo_lo_1)
node r_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx)
node r_array_hi_lo_1 = cat(r_array_hi_lo_hi_1, entries_barrier_6.io.y.sx)
node r_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx)
node r_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx)
node r_array_hi_hi_1 = cat(r_array_hi_hi_hi_1, r_array_hi_hi_lo_1)
node r_array_hi_1 = cat(r_array_hi_hi_1, r_array_hi_lo_1)
node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1)
node _r_array_T_2 = mux(mxr, _r_array_T_1, UInt<1>(0h0))
node _r_array_T_3 = or(_r_array_T, _r_array_T_2)
node _r_array_T_4 = and(priv_rw_ok, _r_array_T_3)
node _r_array_T_5 = or(_r_array_T_4, stage1_bypass)
node r_array = cat(UInt<1>(0h1), _r_array_T_5)
node w_array_lo_lo_hi = cat(entries_barrier_2.io.y.sw, entries_barrier_1.io.y.sw)
node w_array_lo_lo = cat(w_array_lo_lo_hi, entries_barrier.io.y.sw)
node w_array_lo_hi_hi = cat(entries_barrier_5.io.y.sw, entries_barrier_4.io.y.sw)
node w_array_lo_hi = cat(w_array_lo_hi_hi, entries_barrier_3.io.y.sw)
node w_array_lo = cat(w_array_lo_hi, w_array_lo_lo)
node w_array_hi_lo_hi = cat(entries_barrier_8.io.y.sw, entries_barrier_7.io.y.sw)
node w_array_hi_lo = cat(w_array_hi_lo_hi, entries_barrier_6.io.y.sw)
node w_array_hi_hi_lo = cat(entries_barrier_10.io.y.sw, entries_barrier_9.io.y.sw)
node w_array_hi_hi_hi = cat(entries_barrier_12.io.y.sw, entries_barrier_11.io.y.sw)
node w_array_hi_hi = cat(w_array_hi_hi_hi, w_array_hi_hi_lo)
node w_array_hi = cat(w_array_hi_hi, w_array_hi_lo)
node _w_array_T = cat(w_array_hi, w_array_lo)
node _w_array_T_1 = and(priv_rw_ok, _w_array_T)
node _w_array_T_2 = or(_w_array_T_1, stage1_bypass)
node w_array = cat(UInt<1>(0h1), _w_array_T_2)
node x_array_lo_lo_hi = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx)
node x_array_lo_lo = cat(x_array_lo_lo_hi, entries_barrier.io.y.sx)
node x_array_lo_hi_hi = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx)
node x_array_lo_hi = cat(x_array_lo_hi_hi, entries_barrier_3.io.y.sx)
node x_array_lo = cat(x_array_lo_hi, x_array_lo_lo)
node x_array_hi_lo_hi = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx)
node x_array_hi_lo = cat(x_array_hi_lo_hi, entries_barrier_6.io.y.sx)
node x_array_hi_hi_lo = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx)
node x_array_hi_hi_hi = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx)
node x_array_hi_hi = cat(x_array_hi_hi_hi, x_array_hi_hi_lo)
node x_array_hi = cat(x_array_hi_hi, x_array_hi_lo)
node _x_array_T = cat(x_array_hi, x_array_lo)
node _x_array_T_1 = and(priv_x_ok, _x_array_T)
node _x_array_T_2 = or(_x_array_T_1, stage1_bypass)
node x_array = cat(UInt<1>(0h1), _x_array_T_2)
node _stage2_bypass_T = eq(stage2_en, UInt<1>(0h0))
node stage2_bypass = mux(_stage2_bypass_T, UInt<13>(0h1fff), UInt<13>(0h0))
node hr_array_lo_lo_hi = cat(entries_barrier_2.io.y.hr, entries_barrier_1.io.y.hr)
node hr_array_lo_lo = cat(hr_array_lo_lo_hi, entries_barrier.io.y.hr)
node hr_array_lo_hi_hi = cat(entries_barrier_5.io.y.hr, entries_barrier_4.io.y.hr)
node hr_array_lo_hi = cat(hr_array_lo_hi_hi, entries_barrier_3.io.y.hr)
node hr_array_lo = cat(hr_array_lo_hi, hr_array_lo_lo)
node hr_array_hi_lo_hi = cat(entries_barrier_8.io.y.hr, entries_barrier_7.io.y.hr)
node hr_array_hi_lo = cat(hr_array_hi_lo_hi, entries_barrier_6.io.y.hr)
node hr_array_hi_hi_lo = cat(entries_barrier_10.io.y.hr, entries_barrier_9.io.y.hr)
node hr_array_hi_hi_hi = cat(entries_barrier_12.io.y.hr, entries_barrier_11.io.y.hr)
node hr_array_hi_hi = cat(hr_array_hi_hi_hi, hr_array_hi_hi_lo)
node hr_array_hi = cat(hr_array_hi_hi, hr_array_hi_lo)
node _hr_array_T = cat(hr_array_hi, hr_array_lo)
node hr_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx)
node hr_array_lo_lo_1 = cat(hr_array_lo_lo_hi_1, entries_barrier.io.y.hx)
node hr_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx)
node hr_array_lo_hi_1 = cat(hr_array_lo_hi_hi_1, entries_barrier_3.io.y.hx)
node hr_array_lo_1 = cat(hr_array_lo_hi_1, hr_array_lo_lo_1)
node hr_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx)
node hr_array_hi_lo_1 = cat(hr_array_hi_lo_hi_1, entries_barrier_6.io.y.hx)
node hr_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx)
node hr_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx)
node hr_array_hi_hi_1 = cat(hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1)
node hr_array_hi_1 = cat(hr_array_hi_hi_1, hr_array_hi_lo_1)
node _hr_array_T_1 = cat(hr_array_hi_1, hr_array_lo_1)
node _hr_array_T_2 = mux(io.ptw.status.mxr, _hr_array_T_1, UInt<1>(0h0))
node _hr_array_T_3 = or(_hr_array_T, _hr_array_T_2)
node _hr_array_T_4 = or(_hr_array_T_3, stage2_bypass)
node hr_array = cat(UInt<1>(0h1), _hr_array_T_4)
node hw_array_lo_lo_hi = cat(entries_barrier_2.io.y.hw, entries_barrier_1.io.y.hw)
node hw_array_lo_lo = cat(hw_array_lo_lo_hi, entries_barrier.io.y.hw)
node hw_array_lo_hi_hi = cat(entries_barrier_5.io.y.hw, entries_barrier_4.io.y.hw)
node hw_array_lo_hi = cat(hw_array_lo_hi_hi, entries_barrier_3.io.y.hw)
node hw_array_lo = cat(hw_array_lo_hi, hw_array_lo_lo)
node hw_array_hi_lo_hi = cat(entries_barrier_8.io.y.hw, entries_barrier_7.io.y.hw)
node hw_array_hi_lo = cat(hw_array_hi_lo_hi, entries_barrier_6.io.y.hw)
node hw_array_hi_hi_lo = cat(entries_barrier_10.io.y.hw, entries_barrier_9.io.y.hw)
node hw_array_hi_hi_hi = cat(entries_barrier_12.io.y.hw, entries_barrier_11.io.y.hw)
node hw_array_hi_hi = cat(hw_array_hi_hi_hi, hw_array_hi_hi_lo)
node hw_array_hi = cat(hw_array_hi_hi, hw_array_hi_lo)
node _hw_array_T = cat(hw_array_hi, hw_array_lo)
node _hw_array_T_1 = or(_hw_array_T, stage2_bypass)
node hw_array = cat(UInt<1>(0h1), _hw_array_T_1)
node hx_array_lo_lo_hi = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx)
node hx_array_lo_lo = cat(hx_array_lo_lo_hi, entries_barrier.io.y.hx)
node hx_array_lo_hi_hi = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx)
node hx_array_lo_hi = cat(hx_array_lo_hi_hi, entries_barrier_3.io.y.hx)
node hx_array_lo = cat(hx_array_lo_hi, hx_array_lo_lo)
node hx_array_hi_lo_hi = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx)
node hx_array_hi_lo = cat(hx_array_hi_lo_hi, entries_barrier_6.io.y.hx)
node hx_array_hi_hi_lo = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx)
node hx_array_hi_hi_hi = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx)
node hx_array_hi_hi = cat(hx_array_hi_hi_hi, hx_array_hi_hi_lo)
node hx_array_hi = cat(hx_array_hi_hi, hx_array_hi_lo)
node _hx_array_T = cat(hx_array_hi, hx_array_lo)
node _hx_array_T_1 = or(_hx_array_T, stage2_bypass)
node hx_array = cat(UInt<1>(0h1), _hx_array_T_1)
node _pr_array_T = mux(prot_r, UInt<2>(0h3), UInt<2>(0h0))
node pr_array_lo_lo_hi = cat(entries_barrier_2.io.y.pr, entries_barrier_1.io.y.pr)
node pr_array_lo_lo = cat(pr_array_lo_lo_hi, entries_barrier.io.y.pr)
node pr_array_lo_hi_hi = cat(entries_barrier_5.io.y.pr, entries_barrier_4.io.y.pr)
node pr_array_lo_hi = cat(pr_array_lo_hi_hi, entries_barrier_3.io.y.pr)
node pr_array_lo = cat(pr_array_lo_hi, pr_array_lo_lo)
node pr_array_hi_lo_hi = cat(entries_barrier_8.io.y.pr, entries_barrier_7.io.y.pr)
node pr_array_hi_lo = cat(pr_array_hi_lo_hi, entries_barrier_6.io.y.pr)
node pr_array_hi_hi_hi = cat(entries_barrier_11.io.y.pr, entries_barrier_10.io.y.pr)
node pr_array_hi_hi = cat(pr_array_hi_hi_hi, entries_barrier_9.io.y.pr)
node pr_array_hi = cat(pr_array_hi_hi, pr_array_hi_lo)
node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo)
node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1)
node _pr_array_T_3 = or(ptw_ae_array, final_ae_array)
node _pr_array_T_4 = not(_pr_array_T_3)
node pr_array = and(_pr_array_T_2, _pr_array_T_4)
node _pw_array_T = mux(prot_w, UInt<2>(0h3), UInt<2>(0h0))
node pw_array_lo_lo_hi = cat(entries_barrier_2.io.y.pw, entries_barrier_1.io.y.pw)
node pw_array_lo_lo = cat(pw_array_lo_lo_hi, entries_barrier.io.y.pw)
node pw_array_lo_hi_hi = cat(entries_barrier_5.io.y.pw, entries_barrier_4.io.y.pw)
node pw_array_lo_hi = cat(pw_array_lo_hi_hi, entries_barrier_3.io.y.pw)
node pw_array_lo = cat(pw_array_lo_hi, pw_array_lo_lo)
node pw_array_hi_lo_hi = cat(entries_barrier_8.io.y.pw, entries_barrier_7.io.y.pw)
node pw_array_hi_lo = cat(pw_array_hi_lo_hi, entries_barrier_6.io.y.pw)
node pw_array_hi_hi_hi = cat(entries_barrier_11.io.y.pw, entries_barrier_10.io.y.pw)
node pw_array_hi_hi = cat(pw_array_hi_hi_hi, entries_barrier_9.io.y.pw)
node pw_array_hi = cat(pw_array_hi_hi, pw_array_hi_lo)
node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo)
node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1)
node _pw_array_T_3 = or(ptw_ae_array, final_ae_array)
node _pw_array_T_4 = not(_pw_array_T_3)
node pw_array = and(_pw_array_T_2, _pw_array_T_4)
node _px_array_T = mux(prot_x, UInt<2>(0h3), UInt<2>(0h0))
node px_array_lo_lo_hi = cat(entries_barrier_2.io.y.px, entries_barrier_1.io.y.px)
node px_array_lo_lo = cat(px_array_lo_lo_hi, entries_barrier.io.y.px)
node px_array_lo_hi_hi = cat(entries_barrier_5.io.y.px, entries_barrier_4.io.y.px)
node px_array_lo_hi = cat(px_array_lo_hi_hi, entries_barrier_3.io.y.px)
node px_array_lo = cat(px_array_lo_hi, px_array_lo_lo)
node px_array_hi_lo_hi = cat(entries_barrier_8.io.y.px, entries_barrier_7.io.y.px)
node px_array_hi_lo = cat(px_array_hi_lo_hi, entries_barrier_6.io.y.px)
node px_array_hi_hi_hi = cat(entries_barrier_11.io.y.px, entries_barrier_10.io.y.px)
node px_array_hi_hi = cat(px_array_hi_hi_hi, entries_barrier_9.io.y.px)
node px_array_hi = cat(px_array_hi_hi, px_array_hi_lo)
node _px_array_T_1 = cat(px_array_hi, px_array_lo)
node _px_array_T_2 = cat(_px_array_T, _px_array_T_1)
node _px_array_T_3 = or(ptw_ae_array, final_ae_array)
node _px_array_T_4 = not(_px_array_T_3)
node px_array = and(_px_array_T_2, _px_array_T_4)
node _eff_array_T = mux(pma.io.resp.eff, UInt<2>(0h3), UInt<2>(0h0))
node eff_array_lo_lo_hi = cat(entries_barrier_2.io.y.eff, entries_barrier_1.io.y.eff)
node eff_array_lo_lo = cat(eff_array_lo_lo_hi, entries_barrier.io.y.eff)
node eff_array_lo_hi_hi = cat(entries_barrier_5.io.y.eff, entries_barrier_4.io.y.eff)
node eff_array_lo_hi = cat(eff_array_lo_hi_hi, entries_barrier_3.io.y.eff)
node eff_array_lo = cat(eff_array_lo_hi, eff_array_lo_lo)
node eff_array_hi_lo_hi = cat(entries_barrier_8.io.y.eff, entries_barrier_7.io.y.eff)
node eff_array_hi_lo = cat(eff_array_hi_lo_hi, entries_barrier_6.io.y.eff)
node eff_array_hi_hi_hi = cat(entries_barrier_11.io.y.eff, entries_barrier_10.io.y.eff)
node eff_array_hi_hi = cat(eff_array_hi_hi_hi, entries_barrier_9.io.y.eff)
node eff_array_hi = cat(eff_array_hi_hi, eff_array_hi_lo)
node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo)
node eff_array = cat(_eff_array_T, _eff_array_T_1)
node _c_array_T = mux(cacheable, UInt<2>(0h3), UInt<2>(0h0))
node c_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c)
node c_array_lo_lo = cat(c_array_lo_lo_hi, entries_barrier.io.y.c)
node c_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c)
node c_array_lo_hi = cat(c_array_lo_hi_hi, entries_barrier_3.io.y.c)
node c_array_lo = cat(c_array_lo_hi, c_array_lo_lo)
node c_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c)
node c_array_hi_lo = cat(c_array_hi_lo_hi, entries_barrier_6.io.y.c)
node c_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c)
node c_array_hi_hi = cat(c_array_hi_hi_hi, entries_barrier_9.io.y.c)
node c_array_hi = cat(c_array_hi_hi, c_array_hi_lo)
node _c_array_T_1 = cat(c_array_hi, c_array_lo)
node c_array = cat(_c_array_T, _c_array_T_1)
node _ppp_array_T = mux(pma.io.resp.pp, UInt<2>(0h3), UInt<2>(0h0))
node ppp_array_lo_lo_hi = cat(entries_barrier_2.io.y.ppp, entries_barrier_1.io.y.ppp)
node ppp_array_lo_lo = cat(ppp_array_lo_lo_hi, entries_barrier.io.y.ppp)
node ppp_array_lo_hi_hi = cat(entries_barrier_5.io.y.ppp, entries_barrier_4.io.y.ppp)
node ppp_array_lo_hi = cat(ppp_array_lo_hi_hi, entries_barrier_3.io.y.ppp)
node ppp_array_lo = cat(ppp_array_lo_hi, ppp_array_lo_lo)
node ppp_array_hi_lo_hi = cat(entries_barrier_8.io.y.ppp, entries_barrier_7.io.y.ppp)
node ppp_array_hi_lo = cat(ppp_array_hi_lo_hi, entries_barrier_6.io.y.ppp)
node ppp_array_hi_hi_hi = cat(entries_barrier_11.io.y.ppp, entries_barrier_10.io.y.ppp)
node ppp_array_hi_hi = cat(ppp_array_hi_hi_hi, entries_barrier_9.io.y.ppp)
node ppp_array_hi = cat(ppp_array_hi_hi, ppp_array_hi_lo)
node _ppp_array_T_1 = cat(ppp_array_hi, ppp_array_lo)
node ppp_array = cat(_ppp_array_T, _ppp_array_T_1)
node _paa_array_T = mux(pma.io.resp.aa, UInt<2>(0h3), UInt<2>(0h0))
node paa_array_lo_lo_hi = cat(entries_barrier_2.io.y.paa, entries_barrier_1.io.y.paa)
node paa_array_lo_lo = cat(paa_array_lo_lo_hi, entries_barrier.io.y.paa)
node paa_array_lo_hi_hi = cat(entries_barrier_5.io.y.paa, entries_barrier_4.io.y.paa)
node paa_array_lo_hi = cat(paa_array_lo_hi_hi, entries_barrier_3.io.y.paa)
node paa_array_lo = cat(paa_array_lo_hi, paa_array_lo_lo)
node paa_array_hi_lo_hi = cat(entries_barrier_8.io.y.paa, entries_barrier_7.io.y.paa)
node paa_array_hi_lo = cat(paa_array_hi_lo_hi, entries_barrier_6.io.y.paa)
node paa_array_hi_hi_hi = cat(entries_barrier_11.io.y.paa, entries_barrier_10.io.y.paa)
node paa_array_hi_hi = cat(paa_array_hi_hi_hi, entries_barrier_9.io.y.paa)
node paa_array_hi = cat(paa_array_hi_hi, paa_array_hi_lo)
node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo)
node paa_array = cat(_paa_array_T, _paa_array_T_1)
node _pal_array_T = mux(pma.io.resp.al, UInt<2>(0h3), UInt<2>(0h0))
node pal_array_lo_lo_hi = cat(entries_barrier_2.io.y.pal, entries_barrier_1.io.y.pal)
node pal_array_lo_lo = cat(pal_array_lo_lo_hi, entries_barrier.io.y.pal)
node pal_array_lo_hi_hi = cat(entries_barrier_5.io.y.pal, entries_barrier_4.io.y.pal)
node pal_array_lo_hi = cat(pal_array_lo_hi_hi, entries_barrier_3.io.y.pal)
node pal_array_lo = cat(pal_array_lo_hi, pal_array_lo_lo)
node pal_array_hi_lo_hi = cat(entries_barrier_8.io.y.pal, entries_barrier_7.io.y.pal)
node pal_array_hi_lo = cat(pal_array_hi_lo_hi, entries_barrier_6.io.y.pal)
node pal_array_hi_hi_hi = cat(entries_barrier_11.io.y.pal, entries_barrier_10.io.y.pal)
node pal_array_hi_hi = cat(pal_array_hi_hi_hi, entries_barrier_9.io.y.pal)
node pal_array_hi = cat(pal_array_hi_hi, pal_array_hi_lo)
node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo)
node pal_array = cat(_pal_array_T, _pal_array_T_1)
node ppp_array_if_cached = or(ppp_array, c_array)
node paa_array_if_cached = or(paa_array, c_array)
node pal_array_if_cached = or(pal_array, c_array)
node _prefetchable_array_T = and(cacheable, homogeneous)
node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1)
node prefetchable_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c)
node prefetchable_array_lo_lo = cat(prefetchable_array_lo_lo_hi, entries_barrier.io.y.c)
node prefetchable_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c)
node prefetchable_array_lo_hi = cat(prefetchable_array_lo_hi_hi, entries_barrier_3.io.y.c)
node prefetchable_array_lo = cat(prefetchable_array_lo_hi, prefetchable_array_lo_lo)
node prefetchable_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c)
node prefetchable_array_hi_lo = cat(prefetchable_array_hi_lo_hi, entries_barrier_6.io.y.c)
node prefetchable_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c)
node prefetchable_array_hi_hi = cat(prefetchable_array_hi_hi_hi, entries_barrier_9.io.y.c)
node prefetchable_array_hi = cat(prefetchable_array_hi_hi, prefetchable_array_hi_lo)
node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo)
node prefetchable_array = cat(_prefetchable_array_T_1, _prefetchable_array_T_2)
node _misaligned_T = dshl(UInt<1>(0h1), io.req.bits.size)
node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1))
node _misaligned_T_2 = tail(_misaligned_T_1, 1)
node _misaligned_T_3 = and(io.req.bits.vaddr, _misaligned_T_2)
node misaligned = orr(_misaligned_T_3)
node _bad_va_T = and(vm_enabled, stage1_en)
node bad_va_maskedVAddr = and(io.req.bits.vaddr, UInt<40>(0hc000000000))
node _bad_va_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _bad_va_T_2 = eq(bad_va_maskedVAddr, UInt<1>(0h0))
node _bad_va_T_3 = eq(bad_va_maskedVAddr, UInt<40>(0hc000000000))
node _bad_va_T_4 = and(UInt<1>(0h1), _bad_va_T_3)
node _bad_va_T_5 = or(_bad_va_T_2, _bad_va_T_4)
node _bad_va_T_6 = eq(_bad_va_T_5, UInt<1>(0h0))
node _bad_va_T_7 = and(_bad_va_T_1, _bad_va_T_6)
node bad_va = and(_bad_va_T, _bad_va_T_7)
node _cmd_lrsc_T = eq(io.req.bits.cmd, UInt<3>(0h6))
node _cmd_lrsc_T_1 = eq(io.req.bits.cmd, UInt<3>(0h7))
node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1)
node cmd_lrsc = and(UInt<1>(0h1), _cmd_lrsc_T_2)
node _cmd_amo_logical_T = eq(io.req.bits.cmd, UInt<3>(0h4))
node _cmd_amo_logical_T_1 = eq(io.req.bits.cmd, UInt<4>(0h9))
node _cmd_amo_logical_T_2 = eq(io.req.bits.cmd, UInt<4>(0ha))
node _cmd_amo_logical_T_3 = eq(io.req.bits.cmd, UInt<4>(0hb))
node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1)
node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2)
node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3)
node cmd_amo_logical = and(UInt<1>(0h1), _cmd_amo_logical_T_6)
node _cmd_amo_arithmetic_T = eq(io.req.bits.cmd, UInt<4>(0h8))
node _cmd_amo_arithmetic_T_1 = eq(io.req.bits.cmd, UInt<4>(0hc))
node _cmd_amo_arithmetic_T_2 = eq(io.req.bits.cmd, UInt<4>(0hd))
node _cmd_amo_arithmetic_T_3 = eq(io.req.bits.cmd, UInt<4>(0he))
node _cmd_amo_arithmetic_T_4 = eq(io.req.bits.cmd, UInt<4>(0hf))
node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1)
node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2)
node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3)
node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4)
node cmd_amo_arithmetic = and(UInt<1>(0h1), _cmd_amo_arithmetic_T_8)
node cmd_put_partial = eq(io.req.bits.cmd, UInt<5>(0h11))
node _cmd_read_T = eq(io.req.bits.cmd, UInt<1>(0h0))
node _cmd_read_T_1 = eq(io.req.bits.cmd, UInt<5>(0h10))
node _cmd_read_T_2 = eq(io.req.bits.cmd, UInt<3>(0h6))
node _cmd_read_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7))
node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1)
node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2)
node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3)
node _cmd_read_T_7 = eq(io.req.bits.cmd, UInt<3>(0h4))
node _cmd_read_T_8 = eq(io.req.bits.cmd, UInt<4>(0h9))
node _cmd_read_T_9 = eq(io.req.bits.cmd, UInt<4>(0ha))
node _cmd_read_T_10 = eq(io.req.bits.cmd, UInt<4>(0hb))
node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8)
node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9)
node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10)
node _cmd_read_T_14 = eq(io.req.bits.cmd, UInt<4>(0h8))
node _cmd_read_T_15 = eq(io.req.bits.cmd, UInt<4>(0hc))
node _cmd_read_T_16 = eq(io.req.bits.cmd, UInt<4>(0hd))
node _cmd_read_T_17 = eq(io.req.bits.cmd, UInt<4>(0he))
node _cmd_read_T_18 = eq(io.req.bits.cmd, UInt<4>(0hf))
node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15)
node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16)
node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17)
node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18)
node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22)
node cmd_read = or(_cmd_read_T_6, _cmd_read_T_23)
node _cmd_readx_T = eq(io.req.bits.cmd, UInt<5>(0h10))
node cmd_readx = and(UInt<1>(0h0), _cmd_readx_T)
node _cmd_write_T = eq(io.req.bits.cmd, UInt<1>(0h1))
node _cmd_write_T_1 = eq(io.req.bits.cmd, UInt<5>(0h11))
node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1)
node _cmd_write_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7))
node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3)
node _cmd_write_T_5 = eq(io.req.bits.cmd, UInt<3>(0h4))
node _cmd_write_T_6 = eq(io.req.bits.cmd, UInt<4>(0h9))
node _cmd_write_T_7 = eq(io.req.bits.cmd, UInt<4>(0ha))
node _cmd_write_T_8 = eq(io.req.bits.cmd, UInt<4>(0hb))
node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6)
node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7)
node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8)
node _cmd_write_T_12 = eq(io.req.bits.cmd, UInt<4>(0h8))
node _cmd_write_T_13 = eq(io.req.bits.cmd, UInt<4>(0hc))
node _cmd_write_T_14 = eq(io.req.bits.cmd, UInt<4>(0hd))
node _cmd_write_T_15 = eq(io.req.bits.cmd, UInt<4>(0he))
node _cmd_write_T_16 = eq(io.req.bits.cmd, UInt<4>(0hf))
node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13)
node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14)
node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15)
node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16)
node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20)
node cmd_write = or(_cmd_write_T_4, _cmd_write_T_21)
node _cmd_write_perms_T = eq(io.req.bits.cmd, UInt<3>(0h5))
node _cmd_write_perms_T_1 = eq(io.req.bits.cmd, UInt<5>(0h17))
node _cmd_write_perms_T_2 = or(_cmd_write_perms_T, _cmd_write_perms_T_1)
node cmd_write_perms = or(cmd_write, _cmd_write_perms_T_2)
node lrscAllowed = mux(UInt<1>(0h0), UInt<1>(0h0), c_array)
node _ae_array_T = mux(misaligned, eff_array, UInt<1>(0h0))
node _ae_array_T_1 = not(lrscAllowed)
node _ae_array_T_2 = mux(cmd_lrsc, _ae_array_T_1, UInt<1>(0h0))
node ae_array = or(_ae_array_T, _ae_array_T_2)
node _ae_ld_array_T = not(pr_array)
node _ae_ld_array_T_1 = or(ae_array, _ae_ld_array_T)
node ae_ld_array = mux(cmd_read, _ae_ld_array_T_1, UInt<1>(0h0))
node _ae_st_array_T = not(pw_array)
node _ae_st_array_T_1 = or(ae_array, _ae_st_array_T)
node _ae_st_array_T_2 = mux(cmd_write_perms, _ae_st_array_T_1, UInt<1>(0h0))
node _ae_st_array_T_3 = not(ppp_array_if_cached)
node _ae_st_array_T_4 = mux(cmd_put_partial, _ae_st_array_T_3, UInt<1>(0h0))
node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4)
node _ae_st_array_T_6 = not(pal_array_if_cached)
node _ae_st_array_T_7 = mux(cmd_amo_logical, _ae_st_array_T_6, UInt<1>(0h0))
node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7)
node _ae_st_array_T_9 = not(paa_array_if_cached)
node _ae_st_array_T_10 = mux(cmd_amo_arithmetic, _ae_st_array_T_9, UInt<1>(0h0))
node ae_st_array = or(_ae_st_array_T_8, _ae_st_array_T_10)
node _must_alloc_array_T = not(ppp_array)
node _must_alloc_array_T_1 = mux(cmd_put_partial, _must_alloc_array_T, UInt<1>(0h0))
node _must_alloc_array_T_2 = not(pal_array)
node _must_alloc_array_T_3 = mux(cmd_amo_logical, _must_alloc_array_T_2, UInt<1>(0h0))
node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3)
node _must_alloc_array_T_5 = not(paa_array)
node _must_alloc_array_T_6 = mux(cmd_amo_arithmetic, _must_alloc_array_T_5, UInt<1>(0h0))
node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6)
node _must_alloc_array_T_8 = not(UInt<14>(0h0))
node _must_alloc_array_T_9 = mux(cmd_lrsc, _must_alloc_array_T_8, UInt<1>(0h0))
node must_alloc_array = or(_must_alloc_array_T_7, _must_alloc_array_T_9)
node _pf_ld_array_T = mux(cmd_readx, x_array, r_array)
node _pf_ld_array_T_1 = not(_pf_ld_array_T)
node _pf_ld_array_T_2 = not(ptw_ae_array)
node _pf_ld_array_T_3 = and(_pf_ld_array_T_1, _pf_ld_array_T_2)
node _pf_ld_array_T_4 = or(_pf_ld_array_T_3, ptw_pf_array)
node _pf_ld_array_T_5 = not(ptw_gf_array)
node _pf_ld_array_T_6 = and(_pf_ld_array_T_4, _pf_ld_array_T_5)
node pf_ld_array = mux(cmd_read, _pf_ld_array_T_6, UInt<1>(0h0))
node _pf_st_array_T = not(w_array)
node _pf_st_array_T_1 = not(ptw_ae_array)
node _pf_st_array_T_2 = and(_pf_st_array_T, _pf_st_array_T_1)
node _pf_st_array_T_3 = or(_pf_st_array_T_2, ptw_pf_array)
node _pf_st_array_T_4 = not(ptw_gf_array)
node _pf_st_array_T_5 = and(_pf_st_array_T_3, _pf_st_array_T_4)
node pf_st_array = mux(cmd_write_perms, _pf_st_array_T_5, UInt<1>(0h0))
node _pf_inst_array_T = not(x_array)
node _pf_inst_array_T_1 = not(ptw_ae_array)
node _pf_inst_array_T_2 = and(_pf_inst_array_T, _pf_inst_array_T_1)
node _pf_inst_array_T_3 = or(_pf_inst_array_T_2, ptw_pf_array)
node _pf_inst_array_T_4 = not(ptw_gf_array)
node pf_inst_array = and(_pf_inst_array_T_3, _pf_inst_array_T_4)
node _gf_ld_array_T = and(priv_v, cmd_read)
node _gf_ld_array_T_1 = mux(cmd_readx, hx_array, hr_array)
node _gf_ld_array_T_2 = not(_gf_ld_array_T_1)
node _gf_ld_array_T_3 = or(_gf_ld_array_T_2, ptw_gf_array)
node _gf_ld_array_T_4 = not(ptw_ae_array)
node _gf_ld_array_T_5 = and(_gf_ld_array_T_3, _gf_ld_array_T_4)
node gf_ld_array = mux(_gf_ld_array_T, _gf_ld_array_T_5, UInt<1>(0h0))
node _gf_st_array_T = and(priv_v, cmd_write_perms)
node _gf_st_array_T_1 = not(hw_array)
node _gf_st_array_T_2 = or(_gf_st_array_T_1, ptw_gf_array)
node _gf_st_array_T_3 = not(ptw_ae_array)
node _gf_st_array_T_4 = and(_gf_st_array_T_2, _gf_st_array_T_3)
node gf_st_array = mux(_gf_st_array_T, _gf_st_array_T_4, UInt<1>(0h0))
node _gf_inst_array_T = not(hx_array)
node _gf_inst_array_T_1 = or(_gf_inst_array_T, ptw_gf_array)
node _gf_inst_array_T_2 = not(ptw_ae_array)
node _gf_inst_array_T_3 = and(_gf_inst_array_T_1, _gf_inst_array_T_2)
node gf_inst_array = mux(priv_v, _gf_inst_array_T_3, UInt<1>(0h0))
node gpa_hits_need_gpa_mask = or(gf_ld_array, gf_st_array)
node _gpa_hits_hit_mask_T = eq(r_gpa_vpn, vpn)
node _gpa_hits_hit_mask_T_1 = and(r_gpa_valid, _gpa_hits_hit_mask_T)
node _gpa_hits_hit_mask_T_2 = mux(_gpa_hits_hit_mask_T_1, UInt<12>(0hfff), UInt<12>(0h0))
node _gpa_hits_hit_mask_T_3 = eq(vstage1_en, UInt<1>(0h0))
node _gpa_hits_hit_mask_T_4 = mux(_gpa_hits_hit_mask_T_3, UInt<13>(0h1fff), UInt<13>(0h0))
node gpa_hits_hit_mask = or(_gpa_hits_hit_mask_T_2, _gpa_hits_hit_mask_T_4)
node _gpa_hits_T = bits(gpa_hits_need_gpa_mask, 12, 0)
node _gpa_hits_T_1 = not(_gpa_hits_T)
node gpa_hits = or(gpa_hits_hit_mask, _gpa_hits_T_1)
node tlb_hit_if_not_gpa_miss = orr(real_hits)
node _tlb_hit_T = and(real_hits, gpa_hits)
node tlb_hit = orr(_tlb_hit_T)
node _tlb_miss_T = eq(vsatp_mode_mismatch, UInt<1>(0h0))
node _tlb_miss_T_1 = and(vm_enabled, _tlb_miss_T)
node _tlb_miss_T_2 = eq(bad_va, UInt<1>(0h0))
node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2)
node _tlb_miss_T_4 = eq(tlb_hit, UInt<1>(0h0))
node tlb_miss = and(_tlb_miss_T_3, _tlb_miss_T_4)
regreset state_reg : UInt<7>, clock, reset, UInt<7>(0h0)
wire _state_vec_WIRE : UInt<7>[1]
connect _state_vec_WIRE[0], UInt<7>(0h0)
regreset state_vec : UInt<7>[1], clock, reset, _state_vec_WIRE
regreset state_reg_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _T_23 = and(io.req.valid, vm_enabled)
when _T_23 :
node _T_24 = or(sector_hits_0, sector_hits_1)
node _T_25 = or(_T_24, sector_hits_2)
node _T_26 = or(_T_25, sector_hits_3)
node _T_27 = or(_T_26, sector_hits_4)
node _T_28 = or(_T_27, sector_hits_5)
node _T_29 = or(_T_28, sector_hits_6)
node _T_30 = or(_T_29, sector_hits_7)
when _T_30 :
node lo_lo = cat(sector_hits_1, sector_hits_0)
node lo_hi = cat(sector_hits_3, sector_hits_2)
node lo = cat(lo_hi, lo_lo)
node hi_lo = cat(sector_hits_5, sector_hits_4)
node hi_hi = cat(sector_hits_7, sector_hits_6)
node hi = cat(hi_hi, hi_lo)
node _T_31 = cat(hi, lo)
node hi_1 = bits(_T_31, 7, 4)
node lo_1 = bits(_T_31, 3, 0)
node _T_32 = orr(hi_1)
node _T_33 = or(hi_1, lo_1)
node hi_2 = bits(_T_33, 3, 2)
node lo_2 = bits(_T_33, 1, 0)
node _T_34 = orr(hi_2)
node _T_35 = or(hi_2, lo_2)
node _T_36 = bits(_T_35, 1, 1)
node _T_37 = cat(_T_34, _T_36)
node _T_38 = cat(_T_32, _T_37)
node state_vec_0_touch_way_sized = bits(_T_38, 2, 0)
node _state_vec_0_set_left_older_T = bits(state_vec_0_touch_way_sized, 2, 2)
node state_vec_0_set_left_older = eq(_state_vec_0_set_left_older_T, UInt<1>(0h0))
node state_vec_0_left_subtree_state = bits(state_vec[0], 5, 3)
node state_vec_0_right_subtree_state = bits(state_vec[0], 2, 0)
node _state_vec_0_T = bits(state_vec_0_touch_way_sized, 1, 0)
node _state_vec_0_set_left_older_T_1 = bits(_state_vec_0_T, 1, 1)
node state_vec_0_set_left_older_1 = eq(_state_vec_0_set_left_older_T_1, UInt<1>(0h0))
node state_vec_0_left_subtree_state_1 = bits(state_vec_0_left_subtree_state, 1, 1)
node state_vec_0_right_subtree_state_1 = bits(state_vec_0_left_subtree_state, 0, 0)
node _state_vec_0_T_1 = bits(_state_vec_0_T, 0, 0)
node _state_vec_0_T_2 = bits(_state_vec_0_T_1, 0, 0)
node _state_vec_0_T_3 = eq(_state_vec_0_T_2, UInt<1>(0h0))
node _state_vec_0_T_4 = mux(state_vec_0_set_left_older_1, state_vec_0_left_subtree_state_1, _state_vec_0_T_3)
node _state_vec_0_T_5 = bits(_state_vec_0_T, 0, 0)
node _state_vec_0_T_6 = bits(_state_vec_0_T_5, 0, 0)
node _state_vec_0_T_7 = eq(_state_vec_0_T_6, UInt<1>(0h0))
node _state_vec_0_T_8 = mux(state_vec_0_set_left_older_1, _state_vec_0_T_7, state_vec_0_right_subtree_state_1)
node state_vec_0_hi = cat(state_vec_0_set_left_older_1, _state_vec_0_T_4)
node _state_vec_0_T_9 = cat(state_vec_0_hi, _state_vec_0_T_8)
node _state_vec_0_T_10 = mux(state_vec_0_set_left_older, state_vec_0_left_subtree_state, _state_vec_0_T_9)
node _state_vec_0_T_11 = bits(state_vec_0_touch_way_sized, 1, 0)
node _state_vec_0_set_left_older_T_2 = bits(_state_vec_0_T_11, 1, 1)
node state_vec_0_set_left_older_2 = eq(_state_vec_0_set_left_older_T_2, UInt<1>(0h0))
node state_vec_0_left_subtree_state_2 = bits(state_vec_0_right_subtree_state, 1, 1)
node state_vec_0_right_subtree_state_2 = bits(state_vec_0_right_subtree_state, 0, 0)
node _state_vec_0_T_12 = bits(_state_vec_0_T_11, 0, 0)
node _state_vec_0_T_13 = bits(_state_vec_0_T_12, 0, 0)
node _state_vec_0_T_14 = eq(_state_vec_0_T_13, UInt<1>(0h0))
node _state_vec_0_T_15 = mux(state_vec_0_set_left_older_2, state_vec_0_left_subtree_state_2, _state_vec_0_T_14)
node _state_vec_0_T_16 = bits(_state_vec_0_T_11, 0, 0)
node _state_vec_0_T_17 = bits(_state_vec_0_T_16, 0, 0)
node _state_vec_0_T_18 = eq(_state_vec_0_T_17, UInt<1>(0h0))
node _state_vec_0_T_19 = mux(state_vec_0_set_left_older_2, _state_vec_0_T_18, state_vec_0_right_subtree_state_2)
node state_vec_0_hi_1 = cat(state_vec_0_set_left_older_2, _state_vec_0_T_15)
node _state_vec_0_T_20 = cat(state_vec_0_hi_1, _state_vec_0_T_19)
node _state_vec_0_T_21 = mux(state_vec_0_set_left_older, _state_vec_0_T_20, state_vec_0_right_subtree_state)
node state_vec_0_hi_2 = cat(state_vec_0_set_left_older, _state_vec_0_T_10)
node _state_vec_0_T_22 = cat(state_vec_0_hi_2, _state_vec_0_T_21)
connect state_vec[0], _state_vec_0_T_22
node _T_39 = or(superpage_hits_0, superpage_hits_1)
node _T_40 = or(_T_39, superpage_hits_2)
node _T_41 = or(_T_40, superpage_hits_3)
when _T_41 :
node lo_3 = cat(superpage_hits_1, superpage_hits_0)
node hi_3 = cat(superpage_hits_3, superpage_hits_2)
node _T_42 = cat(hi_3, lo_3)
node hi_4 = bits(_T_42, 3, 2)
node lo_4 = bits(_T_42, 1, 0)
node _T_43 = orr(hi_4)
node _T_44 = or(hi_4, lo_4)
node _T_45 = bits(_T_44, 1, 1)
node _T_46 = cat(_T_43, _T_45)
node state_reg_touch_way_sized = bits(_T_46, 1, 0)
node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 1, 1)
node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0))
node state_reg_left_subtree_state = bits(state_reg_1, 1, 1)
node state_reg_right_subtree_state = bits(state_reg_1, 0, 0)
node _state_reg_T = bits(state_reg_touch_way_sized, 0, 0)
node _state_reg_T_1 = bits(_state_reg_T, 0, 0)
node _state_reg_T_2 = eq(_state_reg_T_1, UInt<1>(0h0))
node _state_reg_T_3 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_2)
node _state_reg_T_4 = bits(state_reg_touch_way_sized, 0, 0)
node _state_reg_T_5 = bits(_state_reg_T_4, 0, 0)
node _state_reg_T_6 = eq(_state_reg_T_5, UInt<1>(0h0))
node _state_reg_T_7 = mux(state_reg_set_left_older, _state_reg_T_6, state_reg_right_subtree_state)
node state_reg_hi = cat(state_reg_set_left_older, _state_reg_T_3)
node _state_reg_T_8 = cat(state_reg_hi, _state_reg_T_7)
connect state_reg_1, _state_reg_T_8
node _multipleHits_T = bits(real_hits, 5, 0)
node _multipleHits_T_1 = bits(_multipleHits_T, 2, 0)
node _multipleHits_T_2 = bits(_multipleHits_T_1, 0, 0)
node multipleHits_leftOne = bits(_multipleHits_T_2, 0, 0)
node _multipleHits_T_3 = bits(_multipleHits_T_1, 2, 1)
node _multipleHits_T_4 = bits(_multipleHits_T_3, 0, 0)
node multipleHits_leftOne_1 = bits(_multipleHits_T_4, 0, 0)
node _multipleHits_T_5 = bits(_multipleHits_T_3, 1, 1)
node multipleHits_rightOne = bits(_multipleHits_T_5, 0, 0)
node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne)
node _multipleHits_T_6 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_7 = and(multipleHits_leftOne_1, multipleHits_rightOne)
node multipleHits_rightTwo = or(_multipleHits_T_6, _multipleHits_T_7)
node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1)
node _multipleHits_T_8 = or(UInt<1>(0h0), multipleHits_rightTwo)
node _multipleHits_T_9 = and(multipleHits_leftOne, multipleHits_rightOne_1)
node multipleHits_leftTwo = or(_multipleHits_T_8, _multipleHits_T_9)
node _multipleHits_T_10 = bits(_multipleHits_T, 5, 3)
node _multipleHits_T_11 = bits(_multipleHits_T_10, 0, 0)
node multipleHits_leftOne_3 = bits(_multipleHits_T_11, 0, 0)
node _multipleHits_T_12 = bits(_multipleHits_T_10, 2, 1)
node _multipleHits_T_13 = bits(_multipleHits_T_12, 0, 0)
node multipleHits_leftOne_4 = bits(_multipleHits_T_13, 0, 0)
node _multipleHits_T_14 = bits(_multipleHits_T_12, 1, 1)
node multipleHits_rightOne_2 = bits(_multipleHits_T_14, 0, 0)
node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2)
node _multipleHits_T_15 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_16 = and(multipleHits_leftOne_4, multipleHits_rightOne_2)
node multipleHits_rightTwo_1 = or(_multipleHits_T_15, _multipleHits_T_16)
node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3)
node _multipleHits_T_17 = or(UInt<1>(0h0), multipleHits_rightTwo_1)
node _multipleHits_T_18 = and(multipleHits_leftOne_3, multipleHits_rightOne_3)
node multipleHits_rightTwo_2 = or(_multipleHits_T_17, _multipleHits_T_18)
node multipleHits_leftOne_5 = or(multipleHits_leftOne_2, multipleHits_rightOne_4)
node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2)
node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4)
node multipleHits_leftTwo_1 = or(_multipleHits_T_19, _multipleHits_T_20)
node _multipleHits_T_21 = bits(real_hits, 12, 6)
node _multipleHits_T_22 = bits(_multipleHits_T_21, 2, 0)
node _multipleHits_T_23 = bits(_multipleHits_T_22, 0, 0)
node multipleHits_leftOne_6 = bits(_multipleHits_T_23, 0, 0)
node _multipleHits_T_24 = bits(_multipleHits_T_22, 2, 1)
node _multipleHits_T_25 = bits(_multipleHits_T_24, 0, 0)
node multipleHits_leftOne_7 = bits(_multipleHits_T_25, 0, 0)
node _multipleHits_T_26 = bits(_multipleHits_T_24, 1, 1)
node multipleHits_rightOne_5 = bits(_multipleHits_T_26, 0, 0)
node multipleHits_rightOne_6 = or(multipleHits_leftOne_7, multipleHits_rightOne_5)
node _multipleHits_T_27 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_28 = and(multipleHits_leftOne_7, multipleHits_rightOne_5)
node multipleHits_rightTwo_3 = or(_multipleHits_T_27, _multipleHits_T_28)
node multipleHits_leftOne_8 = or(multipleHits_leftOne_6, multipleHits_rightOne_6)
node _multipleHits_T_29 = or(UInt<1>(0h0), multipleHits_rightTwo_3)
node _multipleHits_T_30 = and(multipleHits_leftOne_6, multipleHits_rightOne_6)
node multipleHits_leftTwo_2 = or(_multipleHits_T_29, _multipleHits_T_30)
node _multipleHits_T_31 = bits(_multipleHits_T_21, 6, 3)
node _multipleHits_T_32 = bits(_multipleHits_T_31, 1, 0)
node _multipleHits_T_33 = bits(_multipleHits_T_32, 0, 0)
node multipleHits_leftOne_9 = bits(_multipleHits_T_33, 0, 0)
node _multipleHits_T_34 = bits(_multipleHits_T_32, 1, 1)
node multipleHits_rightOne_7 = bits(_multipleHits_T_34, 0, 0)
node multipleHits_leftOne_10 = or(multipleHits_leftOne_9, multipleHits_rightOne_7)
node _multipleHits_T_35 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_36 = and(multipleHits_leftOne_9, multipleHits_rightOne_7)
node multipleHits_leftTwo_3 = or(_multipleHits_T_35, _multipleHits_T_36)
node _multipleHits_T_37 = bits(_multipleHits_T_31, 3, 2)
node _multipleHits_T_38 = bits(_multipleHits_T_37, 0, 0)
node multipleHits_leftOne_11 = bits(_multipleHits_T_38, 0, 0)
node _multipleHits_T_39 = bits(_multipleHits_T_37, 1, 1)
node multipleHits_rightOne_8 = bits(_multipleHits_T_39, 0, 0)
node multipleHits_rightOne_9 = or(multipleHits_leftOne_11, multipleHits_rightOne_8)
node _multipleHits_T_40 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_41 = and(multipleHits_leftOne_11, multipleHits_rightOne_8)
node multipleHits_rightTwo_4 = or(_multipleHits_T_40, _multipleHits_T_41)
node multipleHits_rightOne_10 = or(multipleHits_leftOne_10, multipleHits_rightOne_9)
node _multipleHits_T_42 = or(multipleHits_leftTwo_3, multipleHits_rightTwo_4)
node _multipleHits_T_43 = and(multipleHits_leftOne_10, multipleHits_rightOne_9)
node multipleHits_rightTwo_5 = or(_multipleHits_T_42, _multipleHits_T_43)
node multipleHits_rightOne_11 = or(multipleHits_leftOne_8, multipleHits_rightOne_10)
node _multipleHits_T_44 = or(multipleHits_leftTwo_2, multipleHits_rightTwo_5)
node _multipleHits_T_45 = and(multipleHits_leftOne_8, multipleHits_rightOne_10)
node multipleHits_rightTwo_6 = or(_multipleHits_T_44, _multipleHits_T_45)
node _multipleHits_T_46 = or(multipleHits_leftOne_5, multipleHits_rightOne_11)
node _multipleHits_T_47 = or(multipleHits_leftTwo_1, multipleHits_rightTwo_6)
node _multipleHits_T_48 = and(multipleHits_leftOne_5, multipleHits_rightOne_11)
node multipleHits = or(_multipleHits_T_47, _multipleHits_T_48)
node _io_req_ready_T = eq(state, UInt<2>(0h0))
connect io.req.ready, _io_req_ready_T
node _io_resp_pf_ld_T = and(bad_va, cmd_read)
node _io_resp_pf_ld_T_1 = and(pf_ld_array, hits)
node _io_resp_pf_ld_T_2 = orr(_io_resp_pf_ld_T_1)
node _io_resp_pf_ld_T_3 = or(_io_resp_pf_ld_T, _io_resp_pf_ld_T_2)
connect io.resp.pf.ld, _io_resp_pf_ld_T_3
node _io_resp_pf_st_T = and(bad_va, cmd_write_perms)
node _io_resp_pf_st_T_1 = and(pf_st_array, hits)
node _io_resp_pf_st_T_2 = orr(_io_resp_pf_st_T_1)
node _io_resp_pf_st_T_3 = or(_io_resp_pf_st_T, _io_resp_pf_st_T_2)
connect io.resp.pf.st, _io_resp_pf_st_T_3
node _io_resp_pf_inst_T = and(pf_inst_array, hits)
node _io_resp_pf_inst_T_1 = orr(_io_resp_pf_inst_T)
node _io_resp_pf_inst_T_2 = or(bad_va, _io_resp_pf_inst_T_1)
connect io.resp.pf.inst, _io_resp_pf_inst_T_2
node _io_resp_gf_ld_T = and(UInt<1>(0h0), cmd_read)
node _io_resp_gf_ld_T_1 = and(gf_ld_array, hits)
node _io_resp_gf_ld_T_2 = orr(_io_resp_gf_ld_T_1)
node _io_resp_gf_ld_T_3 = or(_io_resp_gf_ld_T, _io_resp_gf_ld_T_2)
connect io.resp.gf.ld, _io_resp_gf_ld_T_3
node _io_resp_gf_st_T = and(UInt<1>(0h0), cmd_write_perms)
node _io_resp_gf_st_T_1 = and(gf_st_array, hits)
node _io_resp_gf_st_T_2 = orr(_io_resp_gf_st_T_1)
node _io_resp_gf_st_T_3 = or(_io_resp_gf_st_T, _io_resp_gf_st_T_2)
connect io.resp.gf.st, _io_resp_gf_st_T_3
node _io_resp_gf_inst_T = and(gf_inst_array, hits)
node _io_resp_gf_inst_T_1 = orr(_io_resp_gf_inst_T)
node _io_resp_gf_inst_T_2 = or(UInt<1>(0h0), _io_resp_gf_inst_T_1)
connect io.resp.gf.inst, _io_resp_gf_inst_T_2
node _io_resp_ae_ld_T = and(ae_ld_array, hits)
node _io_resp_ae_ld_T_1 = orr(_io_resp_ae_ld_T)
connect io.resp.ae.ld, _io_resp_ae_ld_T_1
node _io_resp_ae_st_T = and(ae_st_array, hits)
node _io_resp_ae_st_T_1 = orr(_io_resp_ae_st_T)
connect io.resp.ae.st, _io_resp_ae_st_T_1
node _io_resp_ae_inst_T = not(px_array)
node _io_resp_ae_inst_T_1 = and(_io_resp_ae_inst_T, hits)
node _io_resp_ae_inst_T_2 = orr(_io_resp_ae_inst_T_1)
connect io.resp.ae.inst, _io_resp_ae_inst_T_2
node _io_resp_ma_ld_T = and(misaligned, cmd_read)
connect io.resp.ma.ld, _io_resp_ma_ld_T
node _io_resp_ma_st_T = and(misaligned, cmd_write)
connect io.resp.ma.st, _io_resp_ma_st_T
connect io.resp.ma.inst, UInt<1>(0h0)
node _io_resp_cacheable_T = and(c_array, hits)
node _io_resp_cacheable_T_1 = orr(_io_resp_cacheable_T)
connect io.resp.cacheable, _io_resp_cacheable_T_1
node _io_resp_must_alloc_T = and(must_alloc_array, hits)
node _io_resp_must_alloc_T_1 = orr(_io_resp_must_alloc_T)
connect io.resp.must_alloc, _io_resp_must_alloc_T_1
node _io_resp_prefetchable_T = and(prefetchable_array, hits)
node _io_resp_prefetchable_T_1 = orr(_io_resp_prefetchable_T)
node _io_resp_prefetchable_T_2 = and(_io_resp_prefetchable_T_1, UInt<1>(0h1))
connect io.resp.prefetchable, _io_resp_prefetchable_T_2
node _io_resp_miss_T = or(do_refill, vsatp_mode_mismatch)
node _io_resp_miss_T_1 = or(_io_resp_miss_T, tlb_miss)
node _io_resp_miss_T_2 = or(_io_resp_miss_T_1, multipleHits)
connect io.resp.miss, _io_resp_miss_T_2
node _io_resp_paddr_T = bits(io.req.bits.vaddr, 11, 0)
node _io_resp_paddr_T_1 = cat(ppn, _io_resp_paddr_T)
connect io.resp.paddr, _io_resp_paddr_T_1
connect io.resp.size, io.req.bits.size
connect io.resp.cmd, io.req.bits.cmd
node _io_resp_gpa_is_pte_T = and(vstage1_en, r_gpa_is_pte)
connect io.resp.gpa_is_pte, _io_resp_gpa_is_pte_T
node _io_resp_gpa_page_T = eq(vstage1_en, UInt<1>(0h0))
node _io_resp_gpa_page_T_1 = cat(UInt<1>(0h0), vpn)
node _io_resp_gpa_page_T_2 = shr(r_gpa, 12)
node io_resp_gpa_page = mux(_io_resp_gpa_page_T, _io_resp_gpa_page_T_1, _io_resp_gpa_page_T_2)
node _io_resp_gpa_offset_T = bits(r_gpa, 11, 0)
node _io_resp_gpa_offset_T_1 = bits(io.req.bits.vaddr, 11, 0)
node io_resp_gpa_offset = mux(io.resp.gpa_is_pte, _io_resp_gpa_offset_T, _io_resp_gpa_offset_T_1)
node _io_resp_gpa_T = cat(io_resp_gpa_page, io_resp_gpa_offset)
connect io.resp.gpa, _io_resp_gpa_T
node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1))
connect io.ptw.req.valid, _io_ptw_req_valid_T
node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0))
connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T
connect io.ptw.req.bits.bits.addr, r_refill_tag
connect io.ptw.req.bits.bits.vstage1, r_vstage1_en
connect io.ptw.req.bits.bits.stage2, r_stage2_en
connect io.ptw.req.bits.bits.need_gpa, r_need_gpa
node _T_47 = and(io.ptw.req.ready, io.ptw.req.valid)
node _T_48 = and(_T_47, io.ptw.req.bits.valid)
when _T_48 :
connect r_gpa_valid, UInt<1>(0h0)
connect r_gpa_vpn, r_refill_tag
node _T_49 = and(io.req.ready, io.req.valid)
node _T_50 = and(_T_49, tlb_miss)
when _T_50 :
connect state, UInt<2>(0h1)
connect r_refill_tag, vpn
connect r_need_gpa, tlb_hit_if_not_gpa_miss
connect r_vstage1_en, vstage1_en
connect r_stage2_en, stage2_en
node r_superpage_repl_addr_left_subtree_older = bits(state_reg_1, 2, 2)
node r_superpage_repl_addr_left_subtree_state = bits(state_reg_1, 1, 1)
node r_superpage_repl_addr_right_subtree_state = bits(state_reg_1, 0, 0)
node _r_superpage_repl_addr_T = bits(r_superpage_repl_addr_left_subtree_state, 0, 0)
node _r_superpage_repl_addr_T_1 = bits(r_superpage_repl_addr_right_subtree_state, 0, 0)
node _r_superpage_repl_addr_T_2 = mux(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T, _r_superpage_repl_addr_T_1)
node _r_superpage_repl_addr_T_3 = cat(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2)
node r_superpage_repl_addr_valids_lo = cat(superpage_entries[1].valid[0], superpage_entries[0].valid[0])
node r_superpage_repl_addr_valids_hi = cat(superpage_entries[3].valid[0], superpage_entries[2].valid[0])
node r_superpage_repl_addr_valids = cat(r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo)
node _r_superpage_repl_addr_T_4 = andr(r_superpage_repl_addr_valids)
node _r_superpage_repl_addr_T_5 = not(r_superpage_repl_addr_valids)
node _r_superpage_repl_addr_T_6 = bits(_r_superpage_repl_addr_T_5, 0, 0)
node _r_superpage_repl_addr_T_7 = bits(_r_superpage_repl_addr_T_5, 1, 1)
node _r_superpage_repl_addr_T_8 = bits(_r_superpage_repl_addr_T_5, 2, 2)
node _r_superpage_repl_addr_T_9 = bits(_r_superpage_repl_addr_T_5, 3, 3)
node _r_superpage_repl_addr_T_10 = mux(_r_superpage_repl_addr_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _r_superpage_repl_addr_T_11 = mux(_r_superpage_repl_addr_T_7, UInt<1>(0h1), _r_superpage_repl_addr_T_10)
node _r_superpage_repl_addr_T_12 = mux(_r_superpage_repl_addr_T_6, UInt<1>(0h0), _r_superpage_repl_addr_T_11)
node _r_superpage_repl_addr_T_13 = mux(_r_superpage_repl_addr_T_4, _r_superpage_repl_addr_T_3, _r_superpage_repl_addr_T_12)
connect r_superpage_repl_addr, _r_superpage_repl_addr_T_13
node r_sectored_repl_addr_left_subtree_older = bits(state_vec[0], 6, 6)
node r_sectored_repl_addr_left_subtree_state = bits(state_vec[0], 5, 3)
node r_sectored_repl_addr_right_subtree_state = bits(state_vec[0], 2, 0)
node r_sectored_repl_addr_left_subtree_older_1 = bits(r_sectored_repl_addr_left_subtree_state, 2, 2)
node r_sectored_repl_addr_left_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 1, 1)
node r_sectored_repl_addr_right_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 0, 0)
node _r_sectored_repl_addr_T = bits(r_sectored_repl_addr_left_subtree_state_1, 0, 0)
node _r_sectored_repl_addr_T_1 = bits(r_sectored_repl_addr_right_subtree_state_1, 0, 0)
node _r_sectored_repl_addr_T_2 = mux(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T, _r_sectored_repl_addr_T_1)
node _r_sectored_repl_addr_T_3 = cat(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2)
node r_sectored_repl_addr_left_subtree_older_2 = bits(r_sectored_repl_addr_right_subtree_state, 2, 2)
node r_sectored_repl_addr_left_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 1, 1)
node r_sectored_repl_addr_right_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 0, 0)
node _r_sectored_repl_addr_T_4 = bits(r_sectored_repl_addr_left_subtree_state_2, 0, 0)
node _r_sectored_repl_addr_T_5 = bits(r_sectored_repl_addr_right_subtree_state_2, 0, 0)
node _r_sectored_repl_addr_T_6 = mux(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_4, _r_sectored_repl_addr_T_5)
node _r_sectored_repl_addr_T_7 = cat(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6)
node _r_sectored_repl_addr_T_8 = mux(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_3, _r_sectored_repl_addr_T_7)
node _r_sectored_repl_addr_T_9 = cat(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8)
node _r_sectored_repl_addr_valids_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1])
node _r_sectored_repl_addr_valids_T_1 = or(_r_sectored_repl_addr_valids_T, sectored_entries[0][0].valid[2])
node _r_sectored_repl_addr_valids_T_2 = or(_r_sectored_repl_addr_valids_T_1, sectored_entries[0][0].valid[3])
node _r_sectored_repl_addr_valids_T_3 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1])
node _r_sectored_repl_addr_valids_T_4 = or(_r_sectored_repl_addr_valids_T_3, sectored_entries[0][1].valid[2])
node _r_sectored_repl_addr_valids_T_5 = or(_r_sectored_repl_addr_valids_T_4, sectored_entries[0][1].valid[3])
node _r_sectored_repl_addr_valids_T_6 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1])
node _r_sectored_repl_addr_valids_T_7 = or(_r_sectored_repl_addr_valids_T_6, sectored_entries[0][2].valid[2])
node _r_sectored_repl_addr_valids_T_8 = or(_r_sectored_repl_addr_valids_T_7, sectored_entries[0][2].valid[3])
node _r_sectored_repl_addr_valids_T_9 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1])
node _r_sectored_repl_addr_valids_T_10 = or(_r_sectored_repl_addr_valids_T_9, sectored_entries[0][3].valid[2])
node _r_sectored_repl_addr_valids_T_11 = or(_r_sectored_repl_addr_valids_T_10, sectored_entries[0][3].valid[3])
node _r_sectored_repl_addr_valids_T_12 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1])
node _r_sectored_repl_addr_valids_T_13 = or(_r_sectored_repl_addr_valids_T_12, sectored_entries[0][4].valid[2])
node _r_sectored_repl_addr_valids_T_14 = or(_r_sectored_repl_addr_valids_T_13, sectored_entries[0][4].valid[3])
node _r_sectored_repl_addr_valids_T_15 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1])
node _r_sectored_repl_addr_valids_T_16 = or(_r_sectored_repl_addr_valids_T_15, sectored_entries[0][5].valid[2])
node _r_sectored_repl_addr_valids_T_17 = or(_r_sectored_repl_addr_valids_T_16, sectored_entries[0][5].valid[3])
node _r_sectored_repl_addr_valids_T_18 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1])
node _r_sectored_repl_addr_valids_T_19 = or(_r_sectored_repl_addr_valids_T_18, sectored_entries[0][6].valid[2])
node _r_sectored_repl_addr_valids_T_20 = or(_r_sectored_repl_addr_valids_T_19, sectored_entries[0][6].valid[3])
node _r_sectored_repl_addr_valids_T_21 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1])
node _r_sectored_repl_addr_valids_T_22 = or(_r_sectored_repl_addr_valids_T_21, sectored_entries[0][7].valid[2])
node _r_sectored_repl_addr_valids_T_23 = or(_r_sectored_repl_addr_valids_T_22, sectored_entries[0][7].valid[3])
node r_sectored_repl_addr_valids_lo_lo = cat(_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2)
node r_sectored_repl_addr_valids_lo_hi = cat(_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8)
node r_sectored_repl_addr_valids_lo = cat(r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo)
node r_sectored_repl_addr_valids_hi_lo = cat(_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14)
node r_sectored_repl_addr_valids_hi_hi = cat(_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20)
node r_sectored_repl_addr_valids_hi = cat(r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo)
node r_sectored_repl_addr_valids = cat(r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo)
node _r_sectored_repl_addr_T_10 = andr(r_sectored_repl_addr_valids)
node _r_sectored_repl_addr_T_11 = not(r_sectored_repl_addr_valids)
node _r_sectored_repl_addr_T_12 = bits(_r_sectored_repl_addr_T_11, 0, 0)
node _r_sectored_repl_addr_T_13 = bits(_r_sectored_repl_addr_T_11, 1, 1)
node _r_sectored_repl_addr_T_14 = bits(_r_sectored_repl_addr_T_11, 2, 2)
node _r_sectored_repl_addr_T_15 = bits(_r_sectored_repl_addr_T_11, 3, 3)
node _r_sectored_repl_addr_T_16 = bits(_r_sectored_repl_addr_T_11, 4, 4)
node _r_sectored_repl_addr_T_17 = bits(_r_sectored_repl_addr_T_11, 5, 5)
node _r_sectored_repl_addr_T_18 = bits(_r_sectored_repl_addr_T_11, 6, 6)
node _r_sectored_repl_addr_T_19 = bits(_r_sectored_repl_addr_T_11, 7, 7)
node _r_sectored_repl_addr_T_20 = mux(_r_sectored_repl_addr_T_18, UInt<3>(0h6), UInt<3>(0h7))
node _r_sectored_repl_addr_T_21 = mux(_r_sectored_repl_addr_T_17, UInt<3>(0h5), _r_sectored_repl_addr_T_20)
node _r_sectored_repl_addr_T_22 = mux(_r_sectored_repl_addr_T_16, UInt<3>(0h4), _r_sectored_repl_addr_T_21)
node _r_sectored_repl_addr_T_23 = mux(_r_sectored_repl_addr_T_15, UInt<2>(0h3), _r_sectored_repl_addr_T_22)
node _r_sectored_repl_addr_T_24 = mux(_r_sectored_repl_addr_T_14, UInt<2>(0h2), _r_sectored_repl_addr_T_23)
node _r_sectored_repl_addr_T_25 = mux(_r_sectored_repl_addr_T_13, UInt<1>(0h1), _r_sectored_repl_addr_T_24)
node _r_sectored_repl_addr_T_26 = mux(_r_sectored_repl_addr_T_12, UInt<1>(0h0), _r_sectored_repl_addr_T_25)
node _r_sectored_repl_addr_T_27 = mux(_r_sectored_repl_addr_T_10, _r_sectored_repl_addr_T_9, _r_sectored_repl_addr_T_26)
connect r_sectored_repl_addr, _r_sectored_repl_addr_T_27
node _r_sectored_hit_valid_T = or(sector_hits_0, sector_hits_1)
node _r_sectored_hit_valid_T_1 = or(_r_sectored_hit_valid_T, sector_hits_2)
node _r_sectored_hit_valid_T_2 = or(_r_sectored_hit_valid_T_1, sector_hits_3)
node _r_sectored_hit_valid_T_3 = or(_r_sectored_hit_valid_T_2, sector_hits_4)
node _r_sectored_hit_valid_T_4 = or(_r_sectored_hit_valid_T_3, sector_hits_5)
node _r_sectored_hit_valid_T_5 = or(_r_sectored_hit_valid_T_4, sector_hits_6)
node _r_sectored_hit_valid_T_6 = or(_r_sectored_hit_valid_T_5, sector_hits_7)
connect r_sectored_hit.valid, _r_sectored_hit_valid_T_6
node r_sectored_hit_bits_lo_lo = cat(sector_hits_1, sector_hits_0)
node r_sectored_hit_bits_lo_hi = cat(sector_hits_3, sector_hits_2)
node r_sectored_hit_bits_lo = cat(r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo)
node r_sectored_hit_bits_hi_lo = cat(sector_hits_5, sector_hits_4)
node r_sectored_hit_bits_hi_hi = cat(sector_hits_7, sector_hits_6)
node r_sectored_hit_bits_hi = cat(r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo)
node _r_sectored_hit_bits_T = cat(r_sectored_hit_bits_hi, r_sectored_hit_bits_lo)
node r_sectored_hit_bits_hi_1 = bits(_r_sectored_hit_bits_T, 7, 4)
node r_sectored_hit_bits_lo_1 = bits(_r_sectored_hit_bits_T, 3, 0)
node _r_sectored_hit_bits_T_1 = orr(r_sectored_hit_bits_hi_1)
node _r_sectored_hit_bits_T_2 = or(r_sectored_hit_bits_hi_1, r_sectored_hit_bits_lo_1)
node r_sectored_hit_bits_hi_2 = bits(_r_sectored_hit_bits_T_2, 3, 2)
node r_sectored_hit_bits_lo_2 = bits(_r_sectored_hit_bits_T_2, 1, 0)
node _r_sectored_hit_bits_T_3 = orr(r_sectored_hit_bits_hi_2)
node _r_sectored_hit_bits_T_4 = or(r_sectored_hit_bits_hi_2, r_sectored_hit_bits_lo_2)
node _r_sectored_hit_bits_T_5 = bits(_r_sectored_hit_bits_T_4, 1, 1)
node _r_sectored_hit_bits_T_6 = cat(_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5)
node _r_sectored_hit_bits_T_7 = cat(_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6)
connect r_sectored_hit.bits, _r_sectored_hit_bits_T_7
node _r_superpage_hit_valid_T = or(superpage_hits_0, superpage_hits_1)
node _r_superpage_hit_valid_T_1 = or(_r_superpage_hit_valid_T, superpage_hits_2)
node _r_superpage_hit_valid_T_2 = or(_r_superpage_hit_valid_T_1, superpage_hits_3)
connect r_superpage_hit.valid, _r_superpage_hit_valid_T_2
node r_superpage_hit_bits_lo = cat(superpage_hits_1, superpage_hits_0)
node r_superpage_hit_bits_hi = cat(superpage_hits_3, superpage_hits_2)
node _r_superpage_hit_bits_T = cat(r_superpage_hit_bits_hi, r_superpage_hit_bits_lo)
node r_superpage_hit_bits_hi_1 = bits(_r_superpage_hit_bits_T, 3, 2)
node r_superpage_hit_bits_lo_1 = bits(_r_superpage_hit_bits_T, 1, 0)
node _r_superpage_hit_bits_T_1 = orr(r_superpage_hit_bits_hi_1)
node _r_superpage_hit_bits_T_2 = or(r_superpage_hit_bits_hi_1, r_superpage_hit_bits_lo_1)
node _r_superpage_hit_bits_T_3 = bits(_r_superpage_hit_bits_T_2, 1, 1)
node _r_superpage_hit_bits_T_4 = cat(_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3)
connect r_superpage_hit.bits, _r_superpage_hit_bits_T_4
node _T_51 = eq(state, UInt<2>(0h1))
when _T_51 :
when io.sfence.valid :
connect state, UInt<2>(0h0)
when io.ptw.req.ready :
node _state_T = mux(io.sfence.valid, UInt<2>(0h3), UInt<2>(0h2))
connect state, _state_T
when io.kill :
connect state, UInt<2>(0h0)
node _T_52 = eq(state, UInt<2>(0h2))
node _T_53 = and(_T_52, io.sfence.valid)
when _T_53 :
connect state, UInt<2>(0h3)
when io.ptw.resp.valid :
connect state, UInt<2>(0h0)
when io.sfence.valid :
node _T_54 = eq(io.sfence.bits.rs1, UInt<1>(0h0))
node _T_55 = shr(io.sfence.bits.addr, 12)
node _T_56 = eq(_T_55, vpn)
node _T_57 = or(_T_54, _T_56)
node _T_58 = asUInt(reset)
node _T_59 = eq(_T_58, UInt<1>(0h0))
when _T_59 :
node _T_60 = eq(_T_57, UInt<1>(0h0))
when _T_60 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at TLB.scala:719 assert(!io.sfence.bits.rs1 || (io.sfence.bits.addr >> pgIdxBits) === vpn)\n") : printf
assert(clock, _T_57, UInt<1>(0h1), "") : assert
node hv = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_61 = eq(hg, UInt<1>(0h0))
node _T_62 = and(_T_61, io.sfence.bits.rs1)
when _T_62 :
node _T_63 = xor(sectored_entries[0][0].tag_vpn, vpn)
node _T_64 = shr(_T_63, 2)
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = eq(sectored_entries[0][0].tag_v, hv)
node _T_67 = and(_T_65, _T_66)
when _T_67 :
wire _WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_1 : UInt<42>
connect _WIRE_1, sectored_entries[0][0].data[0]
node _T_68 = bits(_WIRE_1, 0, 0)
connect _WIRE.fragmented_superpage, _T_68
node _T_69 = bits(_WIRE_1, 1, 1)
connect _WIRE.c, _T_69
node _T_70 = bits(_WIRE_1, 2, 2)
connect _WIRE.eff, _T_70
node _T_71 = bits(_WIRE_1, 3, 3)
connect _WIRE.paa, _T_71
node _T_72 = bits(_WIRE_1, 4, 4)
connect _WIRE.pal, _T_72
node _T_73 = bits(_WIRE_1, 5, 5)
connect _WIRE.ppp, _T_73
node _T_74 = bits(_WIRE_1, 6, 6)
connect _WIRE.pr, _T_74
node _T_75 = bits(_WIRE_1, 7, 7)
connect _WIRE.px, _T_75
node _T_76 = bits(_WIRE_1, 8, 8)
connect _WIRE.pw, _T_76
node _T_77 = bits(_WIRE_1, 9, 9)
connect _WIRE.hr, _T_77
node _T_78 = bits(_WIRE_1, 10, 10)
connect _WIRE.hx, _T_78
node _T_79 = bits(_WIRE_1, 11, 11)
connect _WIRE.hw, _T_79
node _T_80 = bits(_WIRE_1, 12, 12)
connect _WIRE.sr, _T_80
node _T_81 = bits(_WIRE_1, 13, 13)
connect _WIRE.sx, _T_81
node _T_82 = bits(_WIRE_1, 14, 14)
connect _WIRE.sw, _T_82
node _T_83 = bits(_WIRE_1, 15, 15)
connect _WIRE.gf, _T_83
node _T_84 = bits(_WIRE_1, 16, 16)
connect _WIRE.pf, _T_84
node _T_85 = bits(_WIRE_1, 17, 17)
connect _WIRE.ae_stage2, _T_85
node _T_86 = bits(_WIRE_1, 18, 18)
connect _WIRE.ae_final, _T_86
node _T_87 = bits(_WIRE_1, 19, 19)
connect _WIRE.ae_ptw, _T_87
node _T_88 = bits(_WIRE_1, 20, 20)
connect _WIRE.g, _T_88
node _T_89 = bits(_WIRE_1, 21, 21)
connect _WIRE.u, _T_89
node _T_90 = bits(_WIRE_1, 41, 22)
connect _WIRE.ppn, _T_90
wire _WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_3 : UInt<42>
connect _WIRE_3, sectored_entries[0][0].data[1]
node _T_91 = bits(_WIRE_3, 0, 0)
connect _WIRE_2.fragmented_superpage, _T_91
node _T_92 = bits(_WIRE_3, 1, 1)
connect _WIRE_2.c, _T_92
node _T_93 = bits(_WIRE_3, 2, 2)
connect _WIRE_2.eff, _T_93
node _T_94 = bits(_WIRE_3, 3, 3)
connect _WIRE_2.paa, _T_94
node _T_95 = bits(_WIRE_3, 4, 4)
connect _WIRE_2.pal, _T_95
node _T_96 = bits(_WIRE_3, 5, 5)
connect _WIRE_2.ppp, _T_96
node _T_97 = bits(_WIRE_3, 6, 6)
connect _WIRE_2.pr, _T_97
node _T_98 = bits(_WIRE_3, 7, 7)
connect _WIRE_2.px, _T_98
node _T_99 = bits(_WIRE_3, 8, 8)
connect _WIRE_2.pw, _T_99
node _T_100 = bits(_WIRE_3, 9, 9)
connect _WIRE_2.hr, _T_100
node _T_101 = bits(_WIRE_3, 10, 10)
connect _WIRE_2.hx, _T_101
node _T_102 = bits(_WIRE_3, 11, 11)
connect _WIRE_2.hw, _T_102
node _T_103 = bits(_WIRE_3, 12, 12)
connect _WIRE_2.sr, _T_103
node _T_104 = bits(_WIRE_3, 13, 13)
connect _WIRE_2.sx, _T_104
node _T_105 = bits(_WIRE_3, 14, 14)
connect _WIRE_2.sw, _T_105
node _T_106 = bits(_WIRE_3, 15, 15)
connect _WIRE_2.gf, _T_106
node _T_107 = bits(_WIRE_3, 16, 16)
connect _WIRE_2.pf, _T_107
node _T_108 = bits(_WIRE_3, 17, 17)
connect _WIRE_2.ae_stage2, _T_108
node _T_109 = bits(_WIRE_3, 18, 18)
connect _WIRE_2.ae_final, _T_109
node _T_110 = bits(_WIRE_3, 19, 19)
connect _WIRE_2.ae_ptw, _T_110
node _T_111 = bits(_WIRE_3, 20, 20)
connect _WIRE_2.g, _T_111
node _T_112 = bits(_WIRE_3, 21, 21)
connect _WIRE_2.u, _T_112
node _T_113 = bits(_WIRE_3, 41, 22)
connect _WIRE_2.ppn, _T_113
wire _WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_5 : UInt<42>
connect _WIRE_5, sectored_entries[0][0].data[2]
node _T_114 = bits(_WIRE_5, 0, 0)
connect _WIRE_4.fragmented_superpage, _T_114
node _T_115 = bits(_WIRE_5, 1, 1)
connect _WIRE_4.c, _T_115
node _T_116 = bits(_WIRE_5, 2, 2)
connect _WIRE_4.eff, _T_116
node _T_117 = bits(_WIRE_5, 3, 3)
connect _WIRE_4.paa, _T_117
node _T_118 = bits(_WIRE_5, 4, 4)
connect _WIRE_4.pal, _T_118
node _T_119 = bits(_WIRE_5, 5, 5)
connect _WIRE_4.ppp, _T_119
node _T_120 = bits(_WIRE_5, 6, 6)
connect _WIRE_4.pr, _T_120
node _T_121 = bits(_WIRE_5, 7, 7)
connect _WIRE_4.px, _T_121
node _T_122 = bits(_WIRE_5, 8, 8)
connect _WIRE_4.pw, _T_122
node _T_123 = bits(_WIRE_5, 9, 9)
connect _WIRE_4.hr, _T_123
node _T_124 = bits(_WIRE_5, 10, 10)
connect _WIRE_4.hx, _T_124
node _T_125 = bits(_WIRE_5, 11, 11)
connect _WIRE_4.hw, _T_125
node _T_126 = bits(_WIRE_5, 12, 12)
connect _WIRE_4.sr, _T_126
node _T_127 = bits(_WIRE_5, 13, 13)
connect _WIRE_4.sx, _T_127
node _T_128 = bits(_WIRE_5, 14, 14)
connect _WIRE_4.sw, _T_128
node _T_129 = bits(_WIRE_5, 15, 15)
connect _WIRE_4.gf, _T_129
node _T_130 = bits(_WIRE_5, 16, 16)
connect _WIRE_4.pf, _T_130
node _T_131 = bits(_WIRE_5, 17, 17)
connect _WIRE_4.ae_stage2, _T_131
node _T_132 = bits(_WIRE_5, 18, 18)
connect _WIRE_4.ae_final, _T_132
node _T_133 = bits(_WIRE_5, 19, 19)
connect _WIRE_4.ae_ptw, _T_133
node _T_134 = bits(_WIRE_5, 20, 20)
connect _WIRE_4.g, _T_134
node _T_135 = bits(_WIRE_5, 21, 21)
connect _WIRE_4.u, _T_135
node _T_136 = bits(_WIRE_5, 41, 22)
connect _WIRE_4.ppn, _T_136
wire _WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_7 : UInt<42>
connect _WIRE_7, sectored_entries[0][0].data[3]
node _T_137 = bits(_WIRE_7, 0, 0)
connect _WIRE_6.fragmented_superpage, _T_137
node _T_138 = bits(_WIRE_7, 1, 1)
connect _WIRE_6.c, _T_138
node _T_139 = bits(_WIRE_7, 2, 2)
connect _WIRE_6.eff, _T_139
node _T_140 = bits(_WIRE_7, 3, 3)
connect _WIRE_6.paa, _T_140
node _T_141 = bits(_WIRE_7, 4, 4)
connect _WIRE_6.pal, _T_141
node _T_142 = bits(_WIRE_7, 5, 5)
connect _WIRE_6.ppp, _T_142
node _T_143 = bits(_WIRE_7, 6, 6)
connect _WIRE_6.pr, _T_143
node _T_144 = bits(_WIRE_7, 7, 7)
connect _WIRE_6.px, _T_144
node _T_145 = bits(_WIRE_7, 8, 8)
connect _WIRE_6.pw, _T_145
node _T_146 = bits(_WIRE_7, 9, 9)
connect _WIRE_6.hr, _T_146
node _T_147 = bits(_WIRE_7, 10, 10)
connect _WIRE_6.hx, _T_147
node _T_148 = bits(_WIRE_7, 11, 11)
connect _WIRE_6.hw, _T_148
node _T_149 = bits(_WIRE_7, 12, 12)
connect _WIRE_6.sr, _T_149
node _T_150 = bits(_WIRE_7, 13, 13)
connect _WIRE_6.sx, _T_150
node _T_151 = bits(_WIRE_7, 14, 14)
connect _WIRE_6.sw, _T_151
node _T_152 = bits(_WIRE_7, 15, 15)
connect _WIRE_6.gf, _T_152
node _T_153 = bits(_WIRE_7, 16, 16)
connect _WIRE_6.pf, _T_153
node _T_154 = bits(_WIRE_7, 17, 17)
connect _WIRE_6.ae_stage2, _T_154
node _T_155 = bits(_WIRE_7, 18, 18)
connect _WIRE_6.ae_final, _T_155
node _T_156 = bits(_WIRE_7, 19, 19)
connect _WIRE_6.ae_ptw, _T_156
node _T_157 = bits(_WIRE_7, 20, 20)
connect _WIRE_6.g, _T_157
node _T_158 = bits(_WIRE_7, 21, 21)
connect _WIRE_6.u, _T_158
node _T_159 = bits(_WIRE_7, 41, 22)
connect _WIRE_6.ppn, _T_159
node _T_160 = eq(sectored_entries[0][0].tag_v, hv)
node _T_161 = bits(vpn, 1, 0)
node _T_162 = eq(UInt<1>(0h0), _T_161)
node _T_163 = and(_T_160, _T_162)
when _T_163 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
node _T_164 = eq(sectored_entries[0][0].tag_v, hv)
node _T_165 = bits(vpn, 1, 0)
node _T_166 = eq(UInt<1>(0h1), _T_165)
node _T_167 = and(_T_164, _T_166)
when _T_167 :
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
node _T_168 = eq(sectored_entries[0][0].tag_v, hv)
node _T_169 = bits(vpn, 1, 0)
node _T_170 = eq(UInt<2>(0h2), _T_169)
node _T_171 = and(_T_168, _T_170)
when _T_171 :
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
node _T_172 = eq(sectored_entries[0][0].tag_v, hv)
node _T_173 = bits(vpn, 1, 0)
node _T_174 = eq(UInt<2>(0h3), _T_173)
node _T_175 = and(_T_172, _T_174)
when _T_175 :
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
node _T_176 = xor(sectored_entries[0][0].tag_vpn, vpn)
node _T_177 = shr(_T_176, 18)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
wire _WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_9 : UInt<42>
connect _WIRE_9, sectored_entries[0][0].data[0]
node _T_179 = bits(_WIRE_9, 0, 0)
connect _WIRE_8.fragmented_superpage, _T_179
node _T_180 = bits(_WIRE_9, 1, 1)
connect _WIRE_8.c, _T_180
node _T_181 = bits(_WIRE_9, 2, 2)
connect _WIRE_8.eff, _T_181
node _T_182 = bits(_WIRE_9, 3, 3)
connect _WIRE_8.paa, _T_182
node _T_183 = bits(_WIRE_9, 4, 4)
connect _WIRE_8.pal, _T_183
node _T_184 = bits(_WIRE_9, 5, 5)
connect _WIRE_8.ppp, _T_184
node _T_185 = bits(_WIRE_9, 6, 6)
connect _WIRE_8.pr, _T_185
node _T_186 = bits(_WIRE_9, 7, 7)
connect _WIRE_8.px, _T_186
node _T_187 = bits(_WIRE_9, 8, 8)
connect _WIRE_8.pw, _T_187
node _T_188 = bits(_WIRE_9, 9, 9)
connect _WIRE_8.hr, _T_188
node _T_189 = bits(_WIRE_9, 10, 10)
connect _WIRE_8.hx, _T_189
node _T_190 = bits(_WIRE_9, 11, 11)
connect _WIRE_8.hw, _T_190
node _T_191 = bits(_WIRE_9, 12, 12)
connect _WIRE_8.sr, _T_191
node _T_192 = bits(_WIRE_9, 13, 13)
connect _WIRE_8.sx, _T_192
node _T_193 = bits(_WIRE_9, 14, 14)
connect _WIRE_8.sw, _T_193
node _T_194 = bits(_WIRE_9, 15, 15)
connect _WIRE_8.gf, _T_194
node _T_195 = bits(_WIRE_9, 16, 16)
connect _WIRE_8.pf, _T_195
node _T_196 = bits(_WIRE_9, 17, 17)
connect _WIRE_8.ae_stage2, _T_196
node _T_197 = bits(_WIRE_9, 18, 18)
connect _WIRE_8.ae_final, _T_197
node _T_198 = bits(_WIRE_9, 19, 19)
connect _WIRE_8.ae_ptw, _T_198
node _T_199 = bits(_WIRE_9, 20, 20)
connect _WIRE_8.g, _T_199
node _T_200 = bits(_WIRE_9, 21, 21)
connect _WIRE_8.u, _T_200
node _T_201 = bits(_WIRE_9, 41, 22)
connect _WIRE_8.ppn, _T_201
wire _WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_11 : UInt<42>
connect _WIRE_11, sectored_entries[0][0].data[1]
node _T_202 = bits(_WIRE_11, 0, 0)
connect _WIRE_10.fragmented_superpage, _T_202
node _T_203 = bits(_WIRE_11, 1, 1)
connect _WIRE_10.c, _T_203
node _T_204 = bits(_WIRE_11, 2, 2)
connect _WIRE_10.eff, _T_204
node _T_205 = bits(_WIRE_11, 3, 3)
connect _WIRE_10.paa, _T_205
node _T_206 = bits(_WIRE_11, 4, 4)
connect _WIRE_10.pal, _T_206
node _T_207 = bits(_WIRE_11, 5, 5)
connect _WIRE_10.ppp, _T_207
node _T_208 = bits(_WIRE_11, 6, 6)
connect _WIRE_10.pr, _T_208
node _T_209 = bits(_WIRE_11, 7, 7)
connect _WIRE_10.px, _T_209
node _T_210 = bits(_WIRE_11, 8, 8)
connect _WIRE_10.pw, _T_210
node _T_211 = bits(_WIRE_11, 9, 9)
connect _WIRE_10.hr, _T_211
node _T_212 = bits(_WIRE_11, 10, 10)
connect _WIRE_10.hx, _T_212
node _T_213 = bits(_WIRE_11, 11, 11)
connect _WIRE_10.hw, _T_213
node _T_214 = bits(_WIRE_11, 12, 12)
connect _WIRE_10.sr, _T_214
node _T_215 = bits(_WIRE_11, 13, 13)
connect _WIRE_10.sx, _T_215
node _T_216 = bits(_WIRE_11, 14, 14)
connect _WIRE_10.sw, _T_216
node _T_217 = bits(_WIRE_11, 15, 15)
connect _WIRE_10.gf, _T_217
node _T_218 = bits(_WIRE_11, 16, 16)
connect _WIRE_10.pf, _T_218
node _T_219 = bits(_WIRE_11, 17, 17)
connect _WIRE_10.ae_stage2, _T_219
node _T_220 = bits(_WIRE_11, 18, 18)
connect _WIRE_10.ae_final, _T_220
node _T_221 = bits(_WIRE_11, 19, 19)
connect _WIRE_10.ae_ptw, _T_221
node _T_222 = bits(_WIRE_11, 20, 20)
connect _WIRE_10.g, _T_222
node _T_223 = bits(_WIRE_11, 21, 21)
connect _WIRE_10.u, _T_223
node _T_224 = bits(_WIRE_11, 41, 22)
connect _WIRE_10.ppn, _T_224
wire _WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_13 : UInt<42>
connect _WIRE_13, sectored_entries[0][0].data[2]
node _T_225 = bits(_WIRE_13, 0, 0)
connect _WIRE_12.fragmented_superpage, _T_225
node _T_226 = bits(_WIRE_13, 1, 1)
connect _WIRE_12.c, _T_226
node _T_227 = bits(_WIRE_13, 2, 2)
connect _WIRE_12.eff, _T_227
node _T_228 = bits(_WIRE_13, 3, 3)
connect _WIRE_12.paa, _T_228
node _T_229 = bits(_WIRE_13, 4, 4)
connect _WIRE_12.pal, _T_229
node _T_230 = bits(_WIRE_13, 5, 5)
connect _WIRE_12.ppp, _T_230
node _T_231 = bits(_WIRE_13, 6, 6)
connect _WIRE_12.pr, _T_231
node _T_232 = bits(_WIRE_13, 7, 7)
connect _WIRE_12.px, _T_232
node _T_233 = bits(_WIRE_13, 8, 8)
connect _WIRE_12.pw, _T_233
node _T_234 = bits(_WIRE_13, 9, 9)
connect _WIRE_12.hr, _T_234
node _T_235 = bits(_WIRE_13, 10, 10)
connect _WIRE_12.hx, _T_235
node _T_236 = bits(_WIRE_13, 11, 11)
connect _WIRE_12.hw, _T_236
node _T_237 = bits(_WIRE_13, 12, 12)
connect _WIRE_12.sr, _T_237
node _T_238 = bits(_WIRE_13, 13, 13)
connect _WIRE_12.sx, _T_238
node _T_239 = bits(_WIRE_13, 14, 14)
connect _WIRE_12.sw, _T_239
node _T_240 = bits(_WIRE_13, 15, 15)
connect _WIRE_12.gf, _T_240
node _T_241 = bits(_WIRE_13, 16, 16)
connect _WIRE_12.pf, _T_241
node _T_242 = bits(_WIRE_13, 17, 17)
connect _WIRE_12.ae_stage2, _T_242
node _T_243 = bits(_WIRE_13, 18, 18)
connect _WIRE_12.ae_final, _T_243
node _T_244 = bits(_WIRE_13, 19, 19)
connect _WIRE_12.ae_ptw, _T_244
node _T_245 = bits(_WIRE_13, 20, 20)
connect _WIRE_12.g, _T_245
node _T_246 = bits(_WIRE_13, 21, 21)
connect _WIRE_12.u, _T_246
node _T_247 = bits(_WIRE_13, 41, 22)
connect _WIRE_12.ppn, _T_247
wire _WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_15 : UInt<42>
connect _WIRE_15, sectored_entries[0][0].data[3]
node _T_248 = bits(_WIRE_15, 0, 0)
connect _WIRE_14.fragmented_superpage, _T_248
node _T_249 = bits(_WIRE_15, 1, 1)
connect _WIRE_14.c, _T_249
node _T_250 = bits(_WIRE_15, 2, 2)
connect _WIRE_14.eff, _T_250
node _T_251 = bits(_WIRE_15, 3, 3)
connect _WIRE_14.paa, _T_251
node _T_252 = bits(_WIRE_15, 4, 4)
connect _WIRE_14.pal, _T_252
node _T_253 = bits(_WIRE_15, 5, 5)
connect _WIRE_14.ppp, _T_253
node _T_254 = bits(_WIRE_15, 6, 6)
connect _WIRE_14.pr, _T_254
node _T_255 = bits(_WIRE_15, 7, 7)
connect _WIRE_14.px, _T_255
node _T_256 = bits(_WIRE_15, 8, 8)
connect _WIRE_14.pw, _T_256
node _T_257 = bits(_WIRE_15, 9, 9)
connect _WIRE_14.hr, _T_257
node _T_258 = bits(_WIRE_15, 10, 10)
connect _WIRE_14.hx, _T_258
node _T_259 = bits(_WIRE_15, 11, 11)
connect _WIRE_14.hw, _T_259
node _T_260 = bits(_WIRE_15, 12, 12)
connect _WIRE_14.sr, _T_260
node _T_261 = bits(_WIRE_15, 13, 13)
connect _WIRE_14.sx, _T_261
node _T_262 = bits(_WIRE_15, 14, 14)
connect _WIRE_14.sw, _T_262
node _T_263 = bits(_WIRE_15, 15, 15)
connect _WIRE_14.gf, _T_263
node _T_264 = bits(_WIRE_15, 16, 16)
connect _WIRE_14.pf, _T_264
node _T_265 = bits(_WIRE_15, 17, 17)
connect _WIRE_14.ae_stage2, _T_265
node _T_266 = bits(_WIRE_15, 18, 18)
connect _WIRE_14.ae_final, _T_266
node _T_267 = bits(_WIRE_15, 19, 19)
connect _WIRE_14.ae_ptw, _T_267
node _T_268 = bits(_WIRE_15, 20, 20)
connect _WIRE_14.g, _T_268
node _T_269 = bits(_WIRE_15, 21, 21)
connect _WIRE_14.u, _T_269
node _T_270 = bits(_WIRE_15, 41, 22)
connect _WIRE_14.ppn, _T_270
node _T_271 = eq(sectored_entries[0][0].tag_v, hv)
node _T_272 = and(_T_271, _WIRE_8.fragmented_superpage)
when _T_272 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
node _T_273 = eq(sectored_entries[0][0].tag_v, hv)
node _T_274 = and(_T_273, _WIRE_10.fragmented_superpage)
when _T_274 :
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
node _T_275 = eq(sectored_entries[0][0].tag_v, hv)
node _T_276 = and(_T_275, _WIRE_12.fragmented_superpage)
when _T_276 :
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
node _T_277 = eq(sectored_entries[0][0].tag_v, hv)
node _T_278 = and(_T_277, _WIRE_14.fragmented_superpage)
when _T_278 :
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
else :
node _T_279 = eq(hg, UInt<1>(0h0))
node _T_280 = and(_T_279, io.sfence.bits.rs2)
when _T_280 :
wire _WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_17 : UInt<42>
connect _WIRE_17, sectored_entries[0][0].data[0]
node _T_281 = bits(_WIRE_17, 0, 0)
connect _WIRE_16.fragmented_superpage, _T_281
node _T_282 = bits(_WIRE_17, 1, 1)
connect _WIRE_16.c, _T_282
node _T_283 = bits(_WIRE_17, 2, 2)
connect _WIRE_16.eff, _T_283
node _T_284 = bits(_WIRE_17, 3, 3)
connect _WIRE_16.paa, _T_284
node _T_285 = bits(_WIRE_17, 4, 4)
connect _WIRE_16.pal, _T_285
node _T_286 = bits(_WIRE_17, 5, 5)
connect _WIRE_16.ppp, _T_286
node _T_287 = bits(_WIRE_17, 6, 6)
connect _WIRE_16.pr, _T_287
node _T_288 = bits(_WIRE_17, 7, 7)
connect _WIRE_16.px, _T_288
node _T_289 = bits(_WIRE_17, 8, 8)
connect _WIRE_16.pw, _T_289
node _T_290 = bits(_WIRE_17, 9, 9)
connect _WIRE_16.hr, _T_290
node _T_291 = bits(_WIRE_17, 10, 10)
connect _WIRE_16.hx, _T_291
node _T_292 = bits(_WIRE_17, 11, 11)
connect _WIRE_16.hw, _T_292
node _T_293 = bits(_WIRE_17, 12, 12)
connect _WIRE_16.sr, _T_293
node _T_294 = bits(_WIRE_17, 13, 13)
connect _WIRE_16.sx, _T_294
node _T_295 = bits(_WIRE_17, 14, 14)
connect _WIRE_16.sw, _T_295
node _T_296 = bits(_WIRE_17, 15, 15)
connect _WIRE_16.gf, _T_296
node _T_297 = bits(_WIRE_17, 16, 16)
connect _WIRE_16.pf, _T_297
node _T_298 = bits(_WIRE_17, 17, 17)
connect _WIRE_16.ae_stage2, _T_298
node _T_299 = bits(_WIRE_17, 18, 18)
connect _WIRE_16.ae_final, _T_299
node _T_300 = bits(_WIRE_17, 19, 19)
connect _WIRE_16.ae_ptw, _T_300
node _T_301 = bits(_WIRE_17, 20, 20)
connect _WIRE_16.g, _T_301
node _T_302 = bits(_WIRE_17, 21, 21)
connect _WIRE_16.u, _T_302
node _T_303 = bits(_WIRE_17, 41, 22)
connect _WIRE_16.ppn, _T_303
wire _WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_19 : UInt<42>
connect _WIRE_19, sectored_entries[0][0].data[1]
node _T_304 = bits(_WIRE_19, 0, 0)
connect _WIRE_18.fragmented_superpage, _T_304
node _T_305 = bits(_WIRE_19, 1, 1)
connect _WIRE_18.c, _T_305
node _T_306 = bits(_WIRE_19, 2, 2)
connect _WIRE_18.eff, _T_306
node _T_307 = bits(_WIRE_19, 3, 3)
connect _WIRE_18.paa, _T_307
node _T_308 = bits(_WIRE_19, 4, 4)
connect _WIRE_18.pal, _T_308
node _T_309 = bits(_WIRE_19, 5, 5)
connect _WIRE_18.ppp, _T_309
node _T_310 = bits(_WIRE_19, 6, 6)
connect _WIRE_18.pr, _T_310
node _T_311 = bits(_WIRE_19, 7, 7)
connect _WIRE_18.px, _T_311
node _T_312 = bits(_WIRE_19, 8, 8)
connect _WIRE_18.pw, _T_312
node _T_313 = bits(_WIRE_19, 9, 9)
connect _WIRE_18.hr, _T_313
node _T_314 = bits(_WIRE_19, 10, 10)
connect _WIRE_18.hx, _T_314
node _T_315 = bits(_WIRE_19, 11, 11)
connect _WIRE_18.hw, _T_315
node _T_316 = bits(_WIRE_19, 12, 12)
connect _WIRE_18.sr, _T_316
node _T_317 = bits(_WIRE_19, 13, 13)
connect _WIRE_18.sx, _T_317
node _T_318 = bits(_WIRE_19, 14, 14)
connect _WIRE_18.sw, _T_318
node _T_319 = bits(_WIRE_19, 15, 15)
connect _WIRE_18.gf, _T_319
node _T_320 = bits(_WIRE_19, 16, 16)
connect _WIRE_18.pf, _T_320
node _T_321 = bits(_WIRE_19, 17, 17)
connect _WIRE_18.ae_stage2, _T_321
node _T_322 = bits(_WIRE_19, 18, 18)
connect _WIRE_18.ae_final, _T_322
node _T_323 = bits(_WIRE_19, 19, 19)
connect _WIRE_18.ae_ptw, _T_323
node _T_324 = bits(_WIRE_19, 20, 20)
connect _WIRE_18.g, _T_324
node _T_325 = bits(_WIRE_19, 21, 21)
connect _WIRE_18.u, _T_325
node _T_326 = bits(_WIRE_19, 41, 22)
connect _WIRE_18.ppn, _T_326
wire _WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_21 : UInt<42>
connect _WIRE_21, sectored_entries[0][0].data[2]
node _T_327 = bits(_WIRE_21, 0, 0)
connect _WIRE_20.fragmented_superpage, _T_327
node _T_328 = bits(_WIRE_21, 1, 1)
connect _WIRE_20.c, _T_328
node _T_329 = bits(_WIRE_21, 2, 2)
connect _WIRE_20.eff, _T_329
node _T_330 = bits(_WIRE_21, 3, 3)
connect _WIRE_20.paa, _T_330
node _T_331 = bits(_WIRE_21, 4, 4)
connect _WIRE_20.pal, _T_331
node _T_332 = bits(_WIRE_21, 5, 5)
connect _WIRE_20.ppp, _T_332
node _T_333 = bits(_WIRE_21, 6, 6)
connect _WIRE_20.pr, _T_333
node _T_334 = bits(_WIRE_21, 7, 7)
connect _WIRE_20.px, _T_334
node _T_335 = bits(_WIRE_21, 8, 8)
connect _WIRE_20.pw, _T_335
node _T_336 = bits(_WIRE_21, 9, 9)
connect _WIRE_20.hr, _T_336
node _T_337 = bits(_WIRE_21, 10, 10)
connect _WIRE_20.hx, _T_337
node _T_338 = bits(_WIRE_21, 11, 11)
connect _WIRE_20.hw, _T_338
node _T_339 = bits(_WIRE_21, 12, 12)
connect _WIRE_20.sr, _T_339
node _T_340 = bits(_WIRE_21, 13, 13)
connect _WIRE_20.sx, _T_340
node _T_341 = bits(_WIRE_21, 14, 14)
connect _WIRE_20.sw, _T_341
node _T_342 = bits(_WIRE_21, 15, 15)
connect _WIRE_20.gf, _T_342
node _T_343 = bits(_WIRE_21, 16, 16)
connect _WIRE_20.pf, _T_343
node _T_344 = bits(_WIRE_21, 17, 17)
connect _WIRE_20.ae_stage2, _T_344
node _T_345 = bits(_WIRE_21, 18, 18)
connect _WIRE_20.ae_final, _T_345
node _T_346 = bits(_WIRE_21, 19, 19)
connect _WIRE_20.ae_ptw, _T_346
node _T_347 = bits(_WIRE_21, 20, 20)
connect _WIRE_20.g, _T_347
node _T_348 = bits(_WIRE_21, 21, 21)
connect _WIRE_20.u, _T_348
node _T_349 = bits(_WIRE_21, 41, 22)
connect _WIRE_20.ppn, _T_349
wire _WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_23 : UInt<42>
connect _WIRE_23, sectored_entries[0][0].data[3]
node _T_350 = bits(_WIRE_23, 0, 0)
connect _WIRE_22.fragmented_superpage, _T_350
node _T_351 = bits(_WIRE_23, 1, 1)
connect _WIRE_22.c, _T_351
node _T_352 = bits(_WIRE_23, 2, 2)
connect _WIRE_22.eff, _T_352
node _T_353 = bits(_WIRE_23, 3, 3)
connect _WIRE_22.paa, _T_353
node _T_354 = bits(_WIRE_23, 4, 4)
connect _WIRE_22.pal, _T_354
node _T_355 = bits(_WIRE_23, 5, 5)
connect _WIRE_22.ppp, _T_355
node _T_356 = bits(_WIRE_23, 6, 6)
connect _WIRE_22.pr, _T_356
node _T_357 = bits(_WIRE_23, 7, 7)
connect _WIRE_22.px, _T_357
node _T_358 = bits(_WIRE_23, 8, 8)
connect _WIRE_22.pw, _T_358
node _T_359 = bits(_WIRE_23, 9, 9)
connect _WIRE_22.hr, _T_359
node _T_360 = bits(_WIRE_23, 10, 10)
connect _WIRE_22.hx, _T_360
node _T_361 = bits(_WIRE_23, 11, 11)
connect _WIRE_22.hw, _T_361
node _T_362 = bits(_WIRE_23, 12, 12)
connect _WIRE_22.sr, _T_362
node _T_363 = bits(_WIRE_23, 13, 13)
connect _WIRE_22.sx, _T_363
node _T_364 = bits(_WIRE_23, 14, 14)
connect _WIRE_22.sw, _T_364
node _T_365 = bits(_WIRE_23, 15, 15)
connect _WIRE_22.gf, _T_365
node _T_366 = bits(_WIRE_23, 16, 16)
connect _WIRE_22.pf, _T_366
node _T_367 = bits(_WIRE_23, 17, 17)
connect _WIRE_22.ae_stage2, _T_367
node _T_368 = bits(_WIRE_23, 18, 18)
connect _WIRE_22.ae_final, _T_368
node _T_369 = bits(_WIRE_23, 19, 19)
connect _WIRE_22.ae_ptw, _T_369
node _T_370 = bits(_WIRE_23, 20, 20)
connect _WIRE_22.g, _T_370
node _T_371 = bits(_WIRE_23, 21, 21)
connect _WIRE_22.u, _T_371
node _T_372 = bits(_WIRE_23, 41, 22)
connect _WIRE_22.ppn, _T_372
node _T_373 = eq(sectored_entries[0][0].tag_v, hv)
node _T_374 = eq(_WIRE_16.g, UInt<1>(0h0))
node _T_375 = and(_T_373, _T_374)
when _T_375 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
node _T_376 = eq(sectored_entries[0][0].tag_v, hv)
node _T_377 = eq(_WIRE_18.g, UInt<1>(0h0))
node _T_378 = and(_T_376, _T_377)
when _T_378 :
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
node _T_379 = eq(sectored_entries[0][0].tag_v, hv)
node _T_380 = eq(_WIRE_20.g, UInt<1>(0h0))
node _T_381 = and(_T_379, _T_380)
when _T_381 :
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
node _T_382 = eq(sectored_entries[0][0].tag_v, hv)
node _T_383 = eq(_WIRE_22.g, UInt<1>(0h0))
node _T_384 = and(_T_382, _T_383)
when _T_384 :
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
else :
node _T_385 = or(hv, hg)
wire _WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_25 : UInt<42>
connect _WIRE_25, sectored_entries[0][0].data[0]
node _T_386 = bits(_WIRE_25, 0, 0)
connect _WIRE_24.fragmented_superpage, _T_386
node _T_387 = bits(_WIRE_25, 1, 1)
connect _WIRE_24.c, _T_387
node _T_388 = bits(_WIRE_25, 2, 2)
connect _WIRE_24.eff, _T_388
node _T_389 = bits(_WIRE_25, 3, 3)
connect _WIRE_24.paa, _T_389
node _T_390 = bits(_WIRE_25, 4, 4)
connect _WIRE_24.pal, _T_390
node _T_391 = bits(_WIRE_25, 5, 5)
connect _WIRE_24.ppp, _T_391
node _T_392 = bits(_WIRE_25, 6, 6)
connect _WIRE_24.pr, _T_392
node _T_393 = bits(_WIRE_25, 7, 7)
connect _WIRE_24.px, _T_393
node _T_394 = bits(_WIRE_25, 8, 8)
connect _WIRE_24.pw, _T_394
node _T_395 = bits(_WIRE_25, 9, 9)
connect _WIRE_24.hr, _T_395
node _T_396 = bits(_WIRE_25, 10, 10)
connect _WIRE_24.hx, _T_396
node _T_397 = bits(_WIRE_25, 11, 11)
connect _WIRE_24.hw, _T_397
node _T_398 = bits(_WIRE_25, 12, 12)
connect _WIRE_24.sr, _T_398
node _T_399 = bits(_WIRE_25, 13, 13)
connect _WIRE_24.sx, _T_399
node _T_400 = bits(_WIRE_25, 14, 14)
connect _WIRE_24.sw, _T_400
node _T_401 = bits(_WIRE_25, 15, 15)
connect _WIRE_24.gf, _T_401
node _T_402 = bits(_WIRE_25, 16, 16)
connect _WIRE_24.pf, _T_402
node _T_403 = bits(_WIRE_25, 17, 17)
connect _WIRE_24.ae_stage2, _T_403
node _T_404 = bits(_WIRE_25, 18, 18)
connect _WIRE_24.ae_final, _T_404
node _T_405 = bits(_WIRE_25, 19, 19)
connect _WIRE_24.ae_ptw, _T_405
node _T_406 = bits(_WIRE_25, 20, 20)
connect _WIRE_24.g, _T_406
node _T_407 = bits(_WIRE_25, 21, 21)
connect _WIRE_24.u, _T_407
node _T_408 = bits(_WIRE_25, 41, 22)
connect _WIRE_24.ppn, _T_408
wire _WIRE_26 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_27 : UInt<42>
connect _WIRE_27, sectored_entries[0][0].data[1]
node _T_409 = bits(_WIRE_27, 0, 0)
connect _WIRE_26.fragmented_superpage, _T_409
node _T_410 = bits(_WIRE_27, 1, 1)
connect _WIRE_26.c, _T_410
node _T_411 = bits(_WIRE_27, 2, 2)
connect _WIRE_26.eff, _T_411
node _T_412 = bits(_WIRE_27, 3, 3)
connect _WIRE_26.paa, _T_412
node _T_413 = bits(_WIRE_27, 4, 4)
connect _WIRE_26.pal, _T_413
node _T_414 = bits(_WIRE_27, 5, 5)
connect _WIRE_26.ppp, _T_414
node _T_415 = bits(_WIRE_27, 6, 6)
connect _WIRE_26.pr, _T_415
node _T_416 = bits(_WIRE_27, 7, 7)
connect _WIRE_26.px, _T_416
node _T_417 = bits(_WIRE_27, 8, 8)
connect _WIRE_26.pw, _T_417
node _T_418 = bits(_WIRE_27, 9, 9)
connect _WIRE_26.hr, _T_418
node _T_419 = bits(_WIRE_27, 10, 10)
connect _WIRE_26.hx, _T_419
node _T_420 = bits(_WIRE_27, 11, 11)
connect _WIRE_26.hw, _T_420
node _T_421 = bits(_WIRE_27, 12, 12)
connect _WIRE_26.sr, _T_421
node _T_422 = bits(_WIRE_27, 13, 13)
connect _WIRE_26.sx, _T_422
node _T_423 = bits(_WIRE_27, 14, 14)
connect _WIRE_26.sw, _T_423
node _T_424 = bits(_WIRE_27, 15, 15)
connect _WIRE_26.gf, _T_424
node _T_425 = bits(_WIRE_27, 16, 16)
connect _WIRE_26.pf, _T_425
node _T_426 = bits(_WIRE_27, 17, 17)
connect _WIRE_26.ae_stage2, _T_426
node _T_427 = bits(_WIRE_27, 18, 18)
connect _WIRE_26.ae_final, _T_427
node _T_428 = bits(_WIRE_27, 19, 19)
connect _WIRE_26.ae_ptw, _T_428
node _T_429 = bits(_WIRE_27, 20, 20)
connect _WIRE_26.g, _T_429
node _T_430 = bits(_WIRE_27, 21, 21)
connect _WIRE_26.u, _T_430
node _T_431 = bits(_WIRE_27, 41, 22)
connect _WIRE_26.ppn, _T_431
wire _WIRE_28 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_29 : UInt<42>
connect _WIRE_29, sectored_entries[0][0].data[2]
node _T_432 = bits(_WIRE_29, 0, 0)
connect _WIRE_28.fragmented_superpage, _T_432
node _T_433 = bits(_WIRE_29, 1, 1)
connect _WIRE_28.c, _T_433
node _T_434 = bits(_WIRE_29, 2, 2)
connect _WIRE_28.eff, _T_434
node _T_435 = bits(_WIRE_29, 3, 3)
connect _WIRE_28.paa, _T_435
node _T_436 = bits(_WIRE_29, 4, 4)
connect _WIRE_28.pal, _T_436
node _T_437 = bits(_WIRE_29, 5, 5)
connect _WIRE_28.ppp, _T_437
node _T_438 = bits(_WIRE_29, 6, 6)
connect _WIRE_28.pr, _T_438
node _T_439 = bits(_WIRE_29, 7, 7)
connect _WIRE_28.px, _T_439
node _T_440 = bits(_WIRE_29, 8, 8)
connect _WIRE_28.pw, _T_440
node _T_441 = bits(_WIRE_29, 9, 9)
connect _WIRE_28.hr, _T_441
node _T_442 = bits(_WIRE_29, 10, 10)
connect _WIRE_28.hx, _T_442
node _T_443 = bits(_WIRE_29, 11, 11)
connect _WIRE_28.hw, _T_443
node _T_444 = bits(_WIRE_29, 12, 12)
connect _WIRE_28.sr, _T_444
node _T_445 = bits(_WIRE_29, 13, 13)
connect _WIRE_28.sx, _T_445
node _T_446 = bits(_WIRE_29, 14, 14)
connect _WIRE_28.sw, _T_446
node _T_447 = bits(_WIRE_29, 15, 15)
connect _WIRE_28.gf, _T_447
node _T_448 = bits(_WIRE_29, 16, 16)
connect _WIRE_28.pf, _T_448
node _T_449 = bits(_WIRE_29, 17, 17)
connect _WIRE_28.ae_stage2, _T_449
node _T_450 = bits(_WIRE_29, 18, 18)
connect _WIRE_28.ae_final, _T_450
node _T_451 = bits(_WIRE_29, 19, 19)
connect _WIRE_28.ae_ptw, _T_451
node _T_452 = bits(_WIRE_29, 20, 20)
connect _WIRE_28.g, _T_452
node _T_453 = bits(_WIRE_29, 21, 21)
connect _WIRE_28.u, _T_453
node _T_454 = bits(_WIRE_29, 41, 22)
connect _WIRE_28.ppn, _T_454
wire _WIRE_30 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_31 : UInt<42>
connect _WIRE_31, sectored_entries[0][0].data[3]
node _T_455 = bits(_WIRE_31, 0, 0)
connect _WIRE_30.fragmented_superpage, _T_455
node _T_456 = bits(_WIRE_31, 1, 1)
connect _WIRE_30.c, _T_456
node _T_457 = bits(_WIRE_31, 2, 2)
connect _WIRE_30.eff, _T_457
node _T_458 = bits(_WIRE_31, 3, 3)
connect _WIRE_30.paa, _T_458
node _T_459 = bits(_WIRE_31, 4, 4)
connect _WIRE_30.pal, _T_459
node _T_460 = bits(_WIRE_31, 5, 5)
connect _WIRE_30.ppp, _T_460
node _T_461 = bits(_WIRE_31, 6, 6)
connect _WIRE_30.pr, _T_461
node _T_462 = bits(_WIRE_31, 7, 7)
connect _WIRE_30.px, _T_462
node _T_463 = bits(_WIRE_31, 8, 8)
connect _WIRE_30.pw, _T_463
node _T_464 = bits(_WIRE_31, 9, 9)
connect _WIRE_30.hr, _T_464
node _T_465 = bits(_WIRE_31, 10, 10)
connect _WIRE_30.hx, _T_465
node _T_466 = bits(_WIRE_31, 11, 11)
connect _WIRE_30.hw, _T_466
node _T_467 = bits(_WIRE_31, 12, 12)
connect _WIRE_30.sr, _T_467
node _T_468 = bits(_WIRE_31, 13, 13)
connect _WIRE_30.sx, _T_468
node _T_469 = bits(_WIRE_31, 14, 14)
connect _WIRE_30.sw, _T_469
node _T_470 = bits(_WIRE_31, 15, 15)
connect _WIRE_30.gf, _T_470
node _T_471 = bits(_WIRE_31, 16, 16)
connect _WIRE_30.pf, _T_471
node _T_472 = bits(_WIRE_31, 17, 17)
connect _WIRE_30.ae_stage2, _T_472
node _T_473 = bits(_WIRE_31, 18, 18)
connect _WIRE_30.ae_final, _T_473
node _T_474 = bits(_WIRE_31, 19, 19)
connect _WIRE_30.ae_ptw, _T_474
node _T_475 = bits(_WIRE_31, 20, 20)
connect _WIRE_30.g, _T_475
node _T_476 = bits(_WIRE_31, 21, 21)
connect _WIRE_30.u, _T_476
node _T_477 = bits(_WIRE_31, 41, 22)
connect _WIRE_30.ppn, _T_477
node _T_478 = eq(sectored_entries[0][0].tag_v, _T_385)
when _T_478 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
node _T_479 = eq(sectored_entries[0][0].tag_v, _T_385)
when _T_479 :
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
node _T_480 = eq(sectored_entries[0][0].tag_v, _T_385)
when _T_480 :
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
node _T_481 = eq(sectored_entries[0][0].tag_v, _T_385)
when _T_481 :
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
node hv_1 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_1 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_482 = eq(hg_1, UInt<1>(0h0))
node _T_483 = and(_T_482, io.sfence.bits.rs1)
when _T_483 :
node _T_484 = xor(sectored_entries[0][1].tag_vpn, vpn)
node _T_485 = shr(_T_484, 2)
node _T_486 = eq(_T_485, UInt<1>(0h0))
node _T_487 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_488 = and(_T_486, _T_487)
when _T_488 :
wire _WIRE_32 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_33 : UInt<42>
connect _WIRE_33, sectored_entries[0][1].data[0]
node _T_489 = bits(_WIRE_33, 0, 0)
connect _WIRE_32.fragmented_superpage, _T_489
node _T_490 = bits(_WIRE_33, 1, 1)
connect _WIRE_32.c, _T_490
node _T_491 = bits(_WIRE_33, 2, 2)
connect _WIRE_32.eff, _T_491
node _T_492 = bits(_WIRE_33, 3, 3)
connect _WIRE_32.paa, _T_492
node _T_493 = bits(_WIRE_33, 4, 4)
connect _WIRE_32.pal, _T_493
node _T_494 = bits(_WIRE_33, 5, 5)
connect _WIRE_32.ppp, _T_494
node _T_495 = bits(_WIRE_33, 6, 6)
connect _WIRE_32.pr, _T_495
node _T_496 = bits(_WIRE_33, 7, 7)
connect _WIRE_32.px, _T_496
node _T_497 = bits(_WIRE_33, 8, 8)
connect _WIRE_32.pw, _T_497
node _T_498 = bits(_WIRE_33, 9, 9)
connect _WIRE_32.hr, _T_498
node _T_499 = bits(_WIRE_33, 10, 10)
connect _WIRE_32.hx, _T_499
node _T_500 = bits(_WIRE_33, 11, 11)
connect _WIRE_32.hw, _T_500
node _T_501 = bits(_WIRE_33, 12, 12)
connect _WIRE_32.sr, _T_501
node _T_502 = bits(_WIRE_33, 13, 13)
connect _WIRE_32.sx, _T_502
node _T_503 = bits(_WIRE_33, 14, 14)
connect _WIRE_32.sw, _T_503
node _T_504 = bits(_WIRE_33, 15, 15)
connect _WIRE_32.gf, _T_504
node _T_505 = bits(_WIRE_33, 16, 16)
connect _WIRE_32.pf, _T_505
node _T_506 = bits(_WIRE_33, 17, 17)
connect _WIRE_32.ae_stage2, _T_506
node _T_507 = bits(_WIRE_33, 18, 18)
connect _WIRE_32.ae_final, _T_507
node _T_508 = bits(_WIRE_33, 19, 19)
connect _WIRE_32.ae_ptw, _T_508
node _T_509 = bits(_WIRE_33, 20, 20)
connect _WIRE_32.g, _T_509
node _T_510 = bits(_WIRE_33, 21, 21)
connect _WIRE_32.u, _T_510
node _T_511 = bits(_WIRE_33, 41, 22)
connect _WIRE_32.ppn, _T_511
wire _WIRE_34 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_35 : UInt<42>
connect _WIRE_35, sectored_entries[0][1].data[1]
node _T_512 = bits(_WIRE_35, 0, 0)
connect _WIRE_34.fragmented_superpage, _T_512
node _T_513 = bits(_WIRE_35, 1, 1)
connect _WIRE_34.c, _T_513
node _T_514 = bits(_WIRE_35, 2, 2)
connect _WIRE_34.eff, _T_514
node _T_515 = bits(_WIRE_35, 3, 3)
connect _WIRE_34.paa, _T_515
node _T_516 = bits(_WIRE_35, 4, 4)
connect _WIRE_34.pal, _T_516
node _T_517 = bits(_WIRE_35, 5, 5)
connect _WIRE_34.ppp, _T_517
node _T_518 = bits(_WIRE_35, 6, 6)
connect _WIRE_34.pr, _T_518
node _T_519 = bits(_WIRE_35, 7, 7)
connect _WIRE_34.px, _T_519
node _T_520 = bits(_WIRE_35, 8, 8)
connect _WIRE_34.pw, _T_520
node _T_521 = bits(_WIRE_35, 9, 9)
connect _WIRE_34.hr, _T_521
node _T_522 = bits(_WIRE_35, 10, 10)
connect _WIRE_34.hx, _T_522
node _T_523 = bits(_WIRE_35, 11, 11)
connect _WIRE_34.hw, _T_523
node _T_524 = bits(_WIRE_35, 12, 12)
connect _WIRE_34.sr, _T_524
node _T_525 = bits(_WIRE_35, 13, 13)
connect _WIRE_34.sx, _T_525
node _T_526 = bits(_WIRE_35, 14, 14)
connect _WIRE_34.sw, _T_526
node _T_527 = bits(_WIRE_35, 15, 15)
connect _WIRE_34.gf, _T_527
node _T_528 = bits(_WIRE_35, 16, 16)
connect _WIRE_34.pf, _T_528
node _T_529 = bits(_WIRE_35, 17, 17)
connect _WIRE_34.ae_stage2, _T_529
node _T_530 = bits(_WIRE_35, 18, 18)
connect _WIRE_34.ae_final, _T_530
node _T_531 = bits(_WIRE_35, 19, 19)
connect _WIRE_34.ae_ptw, _T_531
node _T_532 = bits(_WIRE_35, 20, 20)
connect _WIRE_34.g, _T_532
node _T_533 = bits(_WIRE_35, 21, 21)
connect _WIRE_34.u, _T_533
node _T_534 = bits(_WIRE_35, 41, 22)
connect _WIRE_34.ppn, _T_534
wire _WIRE_36 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_37 : UInt<42>
connect _WIRE_37, sectored_entries[0][1].data[2]
node _T_535 = bits(_WIRE_37, 0, 0)
connect _WIRE_36.fragmented_superpage, _T_535
node _T_536 = bits(_WIRE_37, 1, 1)
connect _WIRE_36.c, _T_536
node _T_537 = bits(_WIRE_37, 2, 2)
connect _WIRE_36.eff, _T_537
node _T_538 = bits(_WIRE_37, 3, 3)
connect _WIRE_36.paa, _T_538
node _T_539 = bits(_WIRE_37, 4, 4)
connect _WIRE_36.pal, _T_539
node _T_540 = bits(_WIRE_37, 5, 5)
connect _WIRE_36.ppp, _T_540
node _T_541 = bits(_WIRE_37, 6, 6)
connect _WIRE_36.pr, _T_541
node _T_542 = bits(_WIRE_37, 7, 7)
connect _WIRE_36.px, _T_542
node _T_543 = bits(_WIRE_37, 8, 8)
connect _WIRE_36.pw, _T_543
node _T_544 = bits(_WIRE_37, 9, 9)
connect _WIRE_36.hr, _T_544
node _T_545 = bits(_WIRE_37, 10, 10)
connect _WIRE_36.hx, _T_545
node _T_546 = bits(_WIRE_37, 11, 11)
connect _WIRE_36.hw, _T_546
node _T_547 = bits(_WIRE_37, 12, 12)
connect _WIRE_36.sr, _T_547
node _T_548 = bits(_WIRE_37, 13, 13)
connect _WIRE_36.sx, _T_548
node _T_549 = bits(_WIRE_37, 14, 14)
connect _WIRE_36.sw, _T_549
node _T_550 = bits(_WIRE_37, 15, 15)
connect _WIRE_36.gf, _T_550
node _T_551 = bits(_WIRE_37, 16, 16)
connect _WIRE_36.pf, _T_551
node _T_552 = bits(_WIRE_37, 17, 17)
connect _WIRE_36.ae_stage2, _T_552
node _T_553 = bits(_WIRE_37, 18, 18)
connect _WIRE_36.ae_final, _T_553
node _T_554 = bits(_WIRE_37, 19, 19)
connect _WIRE_36.ae_ptw, _T_554
node _T_555 = bits(_WIRE_37, 20, 20)
connect _WIRE_36.g, _T_555
node _T_556 = bits(_WIRE_37, 21, 21)
connect _WIRE_36.u, _T_556
node _T_557 = bits(_WIRE_37, 41, 22)
connect _WIRE_36.ppn, _T_557
wire _WIRE_38 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_39 : UInt<42>
connect _WIRE_39, sectored_entries[0][1].data[3]
node _T_558 = bits(_WIRE_39, 0, 0)
connect _WIRE_38.fragmented_superpage, _T_558
node _T_559 = bits(_WIRE_39, 1, 1)
connect _WIRE_38.c, _T_559
node _T_560 = bits(_WIRE_39, 2, 2)
connect _WIRE_38.eff, _T_560
node _T_561 = bits(_WIRE_39, 3, 3)
connect _WIRE_38.paa, _T_561
node _T_562 = bits(_WIRE_39, 4, 4)
connect _WIRE_38.pal, _T_562
node _T_563 = bits(_WIRE_39, 5, 5)
connect _WIRE_38.ppp, _T_563
node _T_564 = bits(_WIRE_39, 6, 6)
connect _WIRE_38.pr, _T_564
node _T_565 = bits(_WIRE_39, 7, 7)
connect _WIRE_38.px, _T_565
node _T_566 = bits(_WIRE_39, 8, 8)
connect _WIRE_38.pw, _T_566
node _T_567 = bits(_WIRE_39, 9, 9)
connect _WIRE_38.hr, _T_567
node _T_568 = bits(_WIRE_39, 10, 10)
connect _WIRE_38.hx, _T_568
node _T_569 = bits(_WIRE_39, 11, 11)
connect _WIRE_38.hw, _T_569
node _T_570 = bits(_WIRE_39, 12, 12)
connect _WIRE_38.sr, _T_570
node _T_571 = bits(_WIRE_39, 13, 13)
connect _WIRE_38.sx, _T_571
node _T_572 = bits(_WIRE_39, 14, 14)
connect _WIRE_38.sw, _T_572
node _T_573 = bits(_WIRE_39, 15, 15)
connect _WIRE_38.gf, _T_573
node _T_574 = bits(_WIRE_39, 16, 16)
connect _WIRE_38.pf, _T_574
node _T_575 = bits(_WIRE_39, 17, 17)
connect _WIRE_38.ae_stage2, _T_575
node _T_576 = bits(_WIRE_39, 18, 18)
connect _WIRE_38.ae_final, _T_576
node _T_577 = bits(_WIRE_39, 19, 19)
connect _WIRE_38.ae_ptw, _T_577
node _T_578 = bits(_WIRE_39, 20, 20)
connect _WIRE_38.g, _T_578
node _T_579 = bits(_WIRE_39, 21, 21)
connect _WIRE_38.u, _T_579
node _T_580 = bits(_WIRE_39, 41, 22)
connect _WIRE_38.ppn, _T_580
node _T_581 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_582 = bits(vpn, 1, 0)
node _T_583 = eq(UInt<1>(0h0), _T_582)
node _T_584 = and(_T_581, _T_583)
when _T_584 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
node _T_585 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_586 = bits(vpn, 1, 0)
node _T_587 = eq(UInt<1>(0h1), _T_586)
node _T_588 = and(_T_585, _T_587)
when _T_588 :
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
node _T_589 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_590 = bits(vpn, 1, 0)
node _T_591 = eq(UInt<2>(0h2), _T_590)
node _T_592 = and(_T_589, _T_591)
when _T_592 :
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
node _T_593 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_594 = bits(vpn, 1, 0)
node _T_595 = eq(UInt<2>(0h3), _T_594)
node _T_596 = and(_T_593, _T_595)
when _T_596 :
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
node _T_597 = xor(sectored_entries[0][1].tag_vpn, vpn)
node _T_598 = shr(_T_597, 18)
node _T_599 = eq(_T_598, UInt<1>(0h0))
when _T_599 :
wire _WIRE_40 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_41 : UInt<42>
connect _WIRE_41, sectored_entries[0][1].data[0]
node _T_600 = bits(_WIRE_41, 0, 0)
connect _WIRE_40.fragmented_superpage, _T_600
node _T_601 = bits(_WIRE_41, 1, 1)
connect _WIRE_40.c, _T_601
node _T_602 = bits(_WIRE_41, 2, 2)
connect _WIRE_40.eff, _T_602
node _T_603 = bits(_WIRE_41, 3, 3)
connect _WIRE_40.paa, _T_603
node _T_604 = bits(_WIRE_41, 4, 4)
connect _WIRE_40.pal, _T_604
node _T_605 = bits(_WIRE_41, 5, 5)
connect _WIRE_40.ppp, _T_605
node _T_606 = bits(_WIRE_41, 6, 6)
connect _WIRE_40.pr, _T_606
node _T_607 = bits(_WIRE_41, 7, 7)
connect _WIRE_40.px, _T_607
node _T_608 = bits(_WIRE_41, 8, 8)
connect _WIRE_40.pw, _T_608
node _T_609 = bits(_WIRE_41, 9, 9)
connect _WIRE_40.hr, _T_609
node _T_610 = bits(_WIRE_41, 10, 10)
connect _WIRE_40.hx, _T_610
node _T_611 = bits(_WIRE_41, 11, 11)
connect _WIRE_40.hw, _T_611
node _T_612 = bits(_WIRE_41, 12, 12)
connect _WIRE_40.sr, _T_612
node _T_613 = bits(_WIRE_41, 13, 13)
connect _WIRE_40.sx, _T_613
node _T_614 = bits(_WIRE_41, 14, 14)
connect _WIRE_40.sw, _T_614
node _T_615 = bits(_WIRE_41, 15, 15)
connect _WIRE_40.gf, _T_615
node _T_616 = bits(_WIRE_41, 16, 16)
connect _WIRE_40.pf, _T_616
node _T_617 = bits(_WIRE_41, 17, 17)
connect _WIRE_40.ae_stage2, _T_617
node _T_618 = bits(_WIRE_41, 18, 18)
connect _WIRE_40.ae_final, _T_618
node _T_619 = bits(_WIRE_41, 19, 19)
connect _WIRE_40.ae_ptw, _T_619
node _T_620 = bits(_WIRE_41, 20, 20)
connect _WIRE_40.g, _T_620
node _T_621 = bits(_WIRE_41, 21, 21)
connect _WIRE_40.u, _T_621
node _T_622 = bits(_WIRE_41, 41, 22)
connect _WIRE_40.ppn, _T_622
wire _WIRE_42 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_43 : UInt<42>
connect _WIRE_43, sectored_entries[0][1].data[1]
node _T_623 = bits(_WIRE_43, 0, 0)
connect _WIRE_42.fragmented_superpage, _T_623
node _T_624 = bits(_WIRE_43, 1, 1)
connect _WIRE_42.c, _T_624
node _T_625 = bits(_WIRE_43, 2, 2)
connect _WIRE_42.eff, _T_625
node _T_626 = bits(_WIRE_43, 3, 3)
connect _WIRE_42.paa, _T_626
node _T_627 = bits(_WIRE_43, 4, 4)
connect _WIRE_42.pal, _T_627
node _T_628 = bits(_WIRE_43, 5, 5)
connect _WIRE_42.ppp, _T_628
node _T_629 = bits(_WIRE_43, 6, 6)
connect _WIRE_42.pr, _T_629
node _T_630 = bits(_WIRE_43, 7, 7)
connect _WIRE_42.px, _T_630
node _T_631 = bits(_WIRE_43, 8, 8)
connect _WIRE_42.pw, _T_631
node _T_632 = bits(_WIRE_43, 9, 9)
connect _WIRE_42.hr, _T_632
node _T_633 = bits(_WIRE_43, 10, 10)
connect _WIRE_42.hx, _T_633
node _T_634 = bits(_WIRE_43, 11, 11)
connect _WIRE_42.hw, _T_634
node _T_635 = bits(_WIRE_43, 12, 12)
connect _WIRE_42.sr, _T_635
node _T_636 = bits(_WIRE_43, 13, 13)
connect _WIRE_42.sx, _T_636
node _T_637 = bits(_WIRE_43, 14, 14)
connect _WIRE_42.sw, _T_637
node _T_638 = bits(_WIRE_43, 15, 15)
connect _WIRE_42.gf, _T_638
node _T_639 = bits(_WIRE_43, 16, 16)
connect _WIRE_42.pf, _T_639
node _T_640 = bits(_WIRE_43, 17, 17)
connect _WIRE_42.ae_stage2, _T_640
node _T_641 = bits(_WIRE_43, 18, 18)
connect _WIRE_42.ae_final, _T_641
node _T_642 = bits(_WIRE_43, 19, 19)
connect _WIRE_42.ae_ptw, _T_642
node _T_643 = bits(_WIRE_43, 20, 20)
connect _WIRE_42.g, _T_643
node _T_644 = bits(_WIRE_43, 21, 21)
connect _WIRE_42.u, _T_644
node _T_645 = bits(_WIRE_43, 41, 22)
connect _WIRE_42.ppn, _T_645
wire _WIRE_44 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_45 : UInt<42>
connect _WIRE_45, sectored_entries[0][1].data[2]
node _T_646 = bits(_WIRE_45, 0, 0)
connect _WIRE_44.fragmented_superpage, _T_646
node _T_647 = bits(_WIRE_45, 1, 1)
connect _WIRE_44.c, _T_647
node _T_648 = bits(_WIRE_45, 2, 2)
connect _WIRE_44.eff, _T_648
node _T_649 = bits(_WIRE_45, 3, 3)
connect _WIRE_44.paa, _T_649
node _T_650 = bits(_WIRE_45, 4, 4)
connect _WIRE_44.pal, _T_650
node _T_651 = bits(_WIRE_45, 5, 5)
connect _WIRE_44.ppp, _T_651
node _T_652 = bits(_WIRE_45, 6, 6)
connect _WIRE_44.pr, _T_652
node _T_653 = bits(_WIRE_45, 7, 7)
connect _WIRE_44.px, _T_653
node _T_654 = bits(_WIRE_45, 8, 8)
connect _WIRE_44.pw, _T_654
node _T_655 = bits(_WIRE_45, 9, 9)
connect _WIRE_44.hr, _T_655
node _T_656 = bits(_WIRE_45, 10, 10)
connect _WIRE_44.hx, _T_656
node _T_657 = bits(_WIRE_45, 11, 11)
connect _WIRE_44.hw, _T_657
node _T_658 = bits(_WIRE_45, 12, 12)
connect _WIRE_44.sr, _T_658
node _T_659 = bits(_WIRE_45, 13, 13)
connect _WIRE_44.sx, _T_659
node _T_660 = bits(_WIRE_45, 14, 14)
connect _WIRE_44.sw, _T_660
node _T_661 = bits(_WIRE_45, 15, 15)
connect _WIRE_44.gf, _T_661
node _T_662 = bits(_WIRE_45, 16, 16)
connect _WIRE_44.pf, _T_662
node _T_663 = bits(_WIRE_45, 17, 17)
connect _WIRE_44.ae_stage2, _T_663
node _T_664 = bits(_WIRE_45, 18, 18)
connect _WIRE_44.ae_final, _T_664
node _T_665 = bits(_WIRE_45, 19, 19)
connect _WIRE_44.ae_ptw, _T_665
node _T_666 = bits(_WIRE_45, 20, 20)
connect _WIRE_44.g, _T_666
node _T_667 = bits(_WIRE_45, 21, 21)
connect _WIRE_44.u, _T_667
node _T_668 = bits(_WIRE_45, 41, 22)
connect _WIRE_44.ppn, _T_668
wire _WIRE_46 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_47 : UInt<42>
connect _WIRE_47, sectored_entries[0][1].data[3]
node _T_669 = bits(_WIRE_47, 0, 0)
connect _WIRE_46.fragmented_superpage, _T_669
node _T_670 = bits(_WIRE_47, 1, 1)
connect _WIRE_46.c, _T_670
node _T_671 = bits(_WIRE_47, 2, 2)
connect _WIRE_46.eff, _T_671
node _T_672 = bits(_WIRE_47, 3, 3)
connect _WIRE_46.paa, _T_672
node _T_673 = bits(_WIRE_47, 4, 4)
connect _WIRE_46.pal, _T_673
node _T_674 = bits(_WIRE_47, 5, 5)
connect _WIRE_46.ppp, _T_674
node _T_675 = bits(_WIRE_47, 6, 6)
connect _WIRE_46.pr, _T_675
node _T_676 = bits(_WIRE_47, 7, 7)
connect _WIRE_46.px, _T_676
node _T_677 = bits(_WIRE_47, 8, 8)
connect _WIRE_46.pw, _T_677
node _T_678 = bits(_WIRE_47, 9, 9)
connect _WIRE_46.hr, _T_678
node _T_679 = bits(_WIRE_47, 10, 10)
connect _WIRE_46.hx, _T_679
node _T_680 = bits(_WIRE_47, 11, 11)
connect _WIRE_46.hw, _T_680
node _T_681 = bits(_WIRE_47, 12, 12)
connect _WIRE_46.sr, _T_681
node _T_682 = bits(_WIRE_47, 13, 13)
connect _WIRE_46.sx, _T_682
node _T_683 = bits(_WIRE_47, 14, 14)
connect _WIRE_46.sw, _T_683
node _T_684 = bits(_WIRE_47, 15, 15)
connect _WIRE_46.gf, _T_684
node _T_685 = bits(_WIRE_47, 16, 16)
connect _WIRE_46.pf, _T_685
node _T_686 = bits(_WIRE_47, 17, 17)
connect _WIRE_46.ae_stage2, _T_686
node _T_687 = bits(_WIRE_47, 18, 18)
connect _WIRE_46.ae_final, _T_687
node _T_688 = bits(_WIRE_47, 19, 19)
connect _WIRE_46.ae_ptw, _T_688
node _T_689 = bits(_WIRE_47, 20, 20)
connect _WIRE_46.g, _T_689
node _T_690 = bits(_WIRE_47, 21, 21)
connect _WIRE_46.u, _T_690
node _T_691 = bits(_WIRE_47, 41, 22)
connect _WIRE_46.ppn, _T_691
node _T_692 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_693 = and(_T_692, _WIRE_40.fragmented_superpage)
when _T_693 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
node _T_694 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_695 = and(_T_694, _WIRE_42.fragmented_superpage)
when _T_695 :
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
node _T_696 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_697 = and(_T_696, _WIRE_44.fragmented_superpage)
when _T_697 :
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
node _T_698 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_699 = and(_T_698, _WIRE_46.fragmented_superpage)
when _T_699 :
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
else :
node _T_700 = eq(hg_1, UInt<1>(0h0))
node _T_701 = and(_T_700, io.sfence.bits.rs2)
when _T_701 :
wire _WIRE_48 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_49 : UInt<42>
connect _WIRE_49, sectored_entries[0][1].data[0]
node _T_702 = bits(_WIRE_49, 0, 0)
connect _WIRE_48.fragmented_superpage, _T_702
node _T_703 = bits(_WIRE_49, 1, 1)
connect _WIRE_48.c, _T_703
node _T_704 = bits(_WIRE_49, 2, 2)
connect _WIRE_48.eff, _T_704
node _T_705 = bits(_WIRE_49, 3, 3)
connect _WIRE_48.paa, _T_705
node _T_706 = bits(_WIRE_49, 4, 4)
connect _WIRE_48.pal, _T_706
node _T_707 = bits(_WIRE_49, 5, 5)
connect _WIRE_48.ppp, _T_707
node _T_708 = bits(_WIRE_49, 6, 6)
connect _WIRE_48.pr, _T_708
node _T_709 = bits(_WIRE_49, 7, 7)
connect _WIRE_48.px, _T_709
node _T_710 = bits(_WIRE_49, 8, 8)
connect _WIRE_48.pw, _T_710
node _T_711 = bits(_WIRE_49, 9, 9)
connect _WIRE_48.hr, _T_711
node _T_712 = bits(_WIRE_49, 10, 10)
connect _WIRE_48.hx, _T_712
node _T_713 = bits(_WIRE_49, 11, 11)
connect _WIRE_48.hw, _T_713
node _T_714 = bits(_WIRE_49, 12, 12)
connect _WIRE_48.sr, _T_714
node _T_715 = bits(_WIRE_49, 13, 13)
connect _WIRE_48.sx, _T_715
node _T_716 = bits(_WIRE_49, 14, 14)
connect _WIRE_48.sw, _T_716
node _T_717 = bits(_WIRE_49, 15, 15)
connect _WIRE_48.gf, _T_717
node _T_718 = bits(_WIRE_49, 16, 16)
connect _WIRE_48.pf, _T_718
node _T_719 = bits(_WIRE_49, 17, 17)
connect _WIRE_48.ae_stage2, _T_719
node _T_720 = bits(_WIRE_49, 18, 18)
connect _WIRE_48.ae_final, _T_720
node _T_721 = bits(_WIRE_49, 19, 19)
connect _WIRE_48.ae_ptw, _T_721
node _T_722 = bits(_WIRE_49, 20, 20)
connect _WIRE_48.g, _T_722
node _T_723 = bits(_WIRE_49, 21, 21)
connect _WIRE_48.u, _T_723
node _T_724 = bits(_WIRE_49, 41, 22)
connect _WIRE_48.ppn, _T_724
wire _WIRE_50 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_51 : UInt<42>
connect _WIRE_51, sectored_entries[0][1].data[1]
node _T_725 = bits(_WIRE_51, 0, 0)
connect _WIRE_50.fragmented_superpage, _T_725
node _T_726 = bits(_WIRE_51, 1, 1)
connect _WIRE_50.c, _T_726
node _T_727 = bits(_WIRE_51, 2, 2)
connect _WIRE_50.eff, _T_727
node _T_728 = bits(_WIRE_51, 3, 3)
connect _WIRE_50.paa, _T_728
node _T_729 = bits(_WIRE_51, 4, 4)
connect _WIRE_50.pal, _T_729
node _T_730 = bits(_WIRE_51, 5, 5)
connect _WIRE_50.ppp, _T_730
node _T_731 = bits(_WIRE_51, 6, 6)
connect _WIRE_50.pr, _T_731
node _T_732 = bits(_WIRE_51, 7, 7)
connect _WIRE_50.px, _T_732
node _T_733 = bits(_WIRE_51, 8, 8)
connect _WIRE_50.pw, _T_733
node _T_734 = bits(_WIRE_51, 9, 9)
connect _WIRE_50.hr, _T_734
node _T_735 = bits(_WIRE_51, 10, 10)
connect _WIRE_50.hx, _T_735
node _T_736 = bits(_WIRE_51, 11, 11)
connect _WIRE_50.hw, _T_736
node _T_737 = bits(_WIRE_51, 12, 12)
connect _WIRE_50.sr, _T_737
node _T_738 = bits(_WIRE_51, 13, 13)
connect _WIRE_50.sx, _T_738
node _T_739 = bits(_WIRE_51, 14, 14)
connect _WIRE_50.sw, _T_739
node _T_740 = bits(_WIRE_51, 15, 15)
connect _WIRE_50.gf, _T_740
node _T_741 = bits(_WIRE_51, 16, 16)
connect _WIRE_50.pf, _T_741
node _T_742 = bits(_WIRE_51, 17, 17)
connect _WIRE_50.ae_stage2, _T_742
node _T_743 = bits(_WIRE_51, 18, 18)
connect _WIRE_50.ae_final, _T_743
node _T_744 = bits(_WIRE_51, 19, 19)
connect _WIRE_50.ae_ptw, _T_744
node _T_745 = bits(_WIRE_51, 20, 20)
connect _WIRE_50.g, _T_745
node _T_746 = bits(_WIRE_51, 21, 21)
connect _WIRE_50.u, _T_746
node _T_747 = bits(_WIRE_51, 41, 22)
connect _WIRE_50.ppn, _T_747
wire _WIRE_52 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_53 : UInt<42>
connect _WIRE_53, sectored_entries[0][1].data[2]
node _T_748 = bits(_WIRE_53, 0, 0)
connect _WIRE_52.fragmented_superpage, _T_748
node _T_749 = bits(_WIRE_53, 1, 1)
connect _WIRE_52.c, _T_749
node _T_750 = bits(_WIRE_53, 2, 2)
connect _WIRE_52.eff, _T_750
node _T_751 = bits(_WIRE_53, 3, 3)
connect _WIRE_52.paa, _T_751
node _T_752 = bits(_WIRE_53, 4, 4)
connect _WIRE_52.pal, _T_752
node _T_753 = bits(_WIRE_53, 5, 5)
connect _WIRE_52.ppp, _T_753
node _T_754 = bits(_WIRE_53, 6, 6)
connect _WIRE_52.pr, _T_754
node _T_755 = bits(_WIRE_53, 7, 7)
connect _WIRE_52.px, _T_755
node _T_756 = bits(_WIRE_53, 8, 8)
connect _WIRE_52.pw, _T_756
node _T_757 = bits(_WIRE_53, 9, 9)
connect _WIRE_52.hr, _T_757
node _T_758 = bits(_WIRE_53, 10, 10)
connect _WIRE_52.hx, _T_758
node _T_759 = bits(_WIRE_53, 11, 11)
connect _WIRE_52.hw, _T_759
node _T_760 = bits(_WIRE_53, 12, 12)
connect _WIRE_52.sr, _T_760
node _T_761 = bits(_WIRE_53, 13, 13)
connect _WIRE_52.sx, _T_761
node _T_762 = bits(_WIRE_53, 14, 14)
connect _WIRE_52.sw, _T_762
node _T_763 = bits(_WIRE_53, 15, 15)
connect _WIRE_52.gf, _T_763
node _T_764 = bits(_WIRE_53, 16, 16)
connect _WIRE_52.pf, _T_764
node _T_765 = bits(_WIRE_53, 17, 17)
connect _WIRE_52.ae_stage2, _T_765
node _T_766 = bits(_WIRE_53, 18, 18)
connect _WIRE_52.ae_final, _T_766
node _T_767 = bits(_WIRE_53, 19, 19)
connect _WIRE_52.ae_ptw, _T_767
node _T_768 = bits(_WIRE_53, 20, 20)
connect _WIRE_52.g, _T_768
node _T_769 = bits(_WIRE_53, 21, 21)
connect _WIRE_52.u, _T_769
node _T_770 = bits(_WIRE_53, 41, 22)
connect _WIRE_52.ppn, _T_770
wire _WIRE_54 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_55 : UInt<42>
connect _WIRE_55, sectored_entries[0][1].data[3]
node _T_771 = bits(_WIRE_55, 0, 0)
connect _WIRE_54.fragmented_superpage, _T_771
node _T_772 = bits(_WIRE_55, 1, 1)
connect _WIRE_54.c, _T_772
node _T_773 = bits(_WIRE_55, 2, 2)
connect _WIRE_54.eff, _T_773
node _T_774 = bits(_WIRE_55, 3, 3)
connect _WIRE_54.paa, _T_774
node _T_775 = bits(_WIRE_55, 4, 4)
connect _WIRE_54.pal, _T_775
node _T_776 = bits(_WIRE_55, 5, 5)
connect _WIRE_54.ppp, _T_776
node _T_777 = bits(_WIRE_55, 6, 6)
connect _WIRE_54.pr, _T_777
node _T_778 = bits(_WIRE_55, 7, 7)
connect _WIRE_54.px, _T_778
node _T_779 = bits(_WIRE_55, 8, 8)
connect _WIRE_54.pw, _T_779
node _T_780 = bits(_WIRE_55, 9, 9)
connect _WIRE_54.hr, _T_780
node _T_781 = bits(_WIRE_55, 10, 10)
connect _WIRE_54.hx, _T_781
node _T_782 = bits(_WIRE_55, 11, 11)
connect _WIRE_54.hw, _T_782
node _T_783 = bits(_WIRE_55, 12, 12)
connect _WIRE_54.sr, _T_783
node _T_784 = bits(_WIRE_55, 13, 13)
connect _WIRE_54.sx, _T_784
node _T_785 = bits(_WIRE_55, 14, 14)
connect _WIRE_54.sw, _T_785
node _T_786 = bits(_WIRE_55, 15, 15)
connect _WIRE_54.gf, _T_786
node _T_787 = bits(_WIRE_55, 16, 16)
connect _WIRE_54.pf, _T_787
node _T_788 = bits(_WIRE_55, 17, 17)
connect _WIRE_54.ae_stage2, _T_788
node _T_789 = bits(_WIRE_55, 18, 18)
connect _WIRE_54.ae_final, _T_789
node _T_790 = bits(_WIRE_55, 19, 19)
connect _WIRE_54.ae_ptw, _T_790
node _T_791 = bits(_WIRE_55, 20, 20)
connect _WIRE_54.g, _T_791
node _T_792 = bits(_WIRE_55, 21, 21)
connect _WIRE_54.u, _T_792
node _T_793 = bits(_WIRE_55, 41, 22)
connect _WIRE_54.ppn, _T_793
node _T_794 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_795 = eq(_WIRE_48.g, UInt<1>(0h0))
node _T_796 = and(_T_794, _T_795)
when _T_796 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
node _T_797 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_798 = eq(_WIRE_50.g, UInt<1>(0h0))
node _T_799 = and(_T_797, _T_798)
when _T_799 :
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
node _T_800 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_801 = eq(_WIRE_52.g, UInt<1>(0h0))
node _T_802 = and(_T_800, _T_801)
when _T_802 :
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
node _T_803 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_804 = eq(_WIRE_54.g, UInt<1>(0h0))
node _T_805 = and(_T_803, _T_804)
when _T_805 :
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
else :
node _T_806 = or(hv_1, hg_1)
wire _WIRE_56 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_57 : UInt<42>
connect _WIRE_57, sectored_entries[0][1].data[0]
node _T_807 = bits(_WIRE_57, 0, 0)
connect _WIRE_56.fragmented_superpage, _T_807
node _T_808 = bits(_WIRE_57, 1, 1)
connect _WIRE_56.c, _T_808
node _T_809 = bits(_WIRE_57, 2, 2)
connect _WIRE_56.eff, _T_809
node _T_810 = bits(_WIRE_57, 3, 3)
connect _WIRE_56.paa, _T_810
node _T_811 = bits(_WIRE_57, 4, 4)
connect _WIRE_56.pal, _T_811
node _T_812 = bits(_WIRE_57, 5, 5)
connect _WIRE_56.ppp, _T_812
node _T_813 = bits(_WIRE_57, 6, 6)
connect _WIRE_56.pr, _T_813
node _T_814 = bits(_WIRE_57, 7, 7)
connect _WIRE_56.px, _T_814
node _T_815 = bits(_WIRE_57, 8, 8)
connect _WIRE_56.pw, _T_815
node _T_816 = bits(_WIRE_57, 9, 9)
connect _WIRE_56.hr, _T_816
node _T_817 = bits(_WIRE_57, 10, 10)
connect _WIRE_56.hx, _T_817
node _T_818 = bits(_WIRE_57, 11, 11)
connect _WIRE_56.hw, _T_818
node _T_819 = bits(_WIRE_57, 12, 12)
connect _WIRE_56.sr, _T_819
node _T_820 = bits(_WIRE_57, 13, 13)
connect _WIRE_56.sx, _T_820
node _T_821 = bits(_WIRE_57, 14, 14)
connect _WIRE_56.sw, _T_821
node _T_822 = bits(_WIRE_57, 15, 15)
connect _WIRE_56.gf, _T_822
node _T_823 = bits(_WIRE_57, 16, 16)
connect _WIRE_56.pf, _T_823
node _T_824 = bits(_WIRE_57, 17, 17)
connect _WIRE_56.ae_stage2, _T_824
node _T_825 = bits(_WIRE_57, 18, 18)
connect _WIRE_56.ae_final, _T_825
node _T_826 = bits(_WIRE_57, 19, 19)
connect _WIRE_56.ae_ptw, _T_826
node _T_827 = bits(_WIRE_57, 20, 20)
connect _WIRE_56.g, _T_827
node _T_828 = bits(_WIRE_57, 21, 21)
connect _WIRE_56.u, _T_828
node _T_829 = bits(_WIRE_57, 41, 22)
connect _WIRE_56.ppn, _T_829
wire _WIRE_58 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_59 : UInt<42>
connect _WIRE_59, sectored_entries[0][1].data[1]
node _T_830 = bits(_WIRE_59, 0, 0)
connect _WIRE_58.fragmented_superpage, _T_830
node _T_831 = bits(_WIRE_59, 1, 1)
connect _WIRE_58.c, _T_831
node _T_832 = bits(_WIRE_59, 2, 2)
connect _WIRE_58.eff, _T_832
node _T_833 = bits(_WIRE_59, 3, 3)
connect _WIRE_58.paa, _T_833
node _T_834 = bits(_WIRE_59, 4, 4)
connect _WIRE_58.pal, _T_834
node _T_835 = bits(_WIRE_59, 5, 5)
connect _WIRE_58.ppp, _T_835
node _T_836 = bits(_WIRE_59, 6, 6)
connect _WIRE_58.pr, _T_836
node _T_837 = bits(_WIRE_59, 7, 7)
connect _WIRE_58.px, _T_837
node _T_838 = bits(_WIRE_59, 8, 8)
connect _WIRE_58.pw, _T_838
node _T_839 = bits(_WIRE_59, 9, 9)
connect _WIRE_58.hr, _T_839
node _T_840 = bits(_WIRE_59, 10, 10)
connect _WIRE_58.hx, _T_840
node _T_841 = bits(_WIRE_59, 11, 11)
connect _WIRE_58.hw, _T_841
node _T_842 = bits(_WIRE_59, 12, 12)
connect _WIRE_58.sr, _T_842
node _T_843 = bits(_WIRE_59, 13, 13)
connect _WIRE_58.sx, _T_843
node _T_844 = bits(_WIRE_59, 14, 14)
connect _WIRE_58.sw, _T_844
node _T_845 = bits(_WIRE_59, 15, 15)
connect _WIRE_58.gf, _T_845
node _T_846 = bits(_WIRE_59, 16, 16)
connect _WIRE_58.pf, _T_846
node _T_847 = bits(_WIRE_59, 17, 17)
connect _WIRE_58.ae_stage2, _T_847
node _T_848 = bits(_WIRE_59, 18, 18)
connect _WIRE_58.ae_final, _T_848
node _T_849 = bits(_WIRE_59, 19, 19)
connect _WIRE_58.ae_ptw, _T_849
node _T_850 = bits(_WIRE_59, 20, 20)
connect _WIRE_58.g, _T_850
node _T_851 = bits(_WIRE_59, 21, 21)
connect _WIRE_58.u, _T_851
node _T_852 = bits(_WIRE_59, 41, 22)
connect _WIRE_58.ppn, _T_852
wire _WIRE_60 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_61 : UInt<42>
connect _WIRE_61, sectored_entries[0][1].data[2]
node _T_853 = bits(_WIRE_61, 0, 0)
connect _WIRE_60.fragmented_superpage, _T_853
node _T_854 = bits(_WIRE_61, 1, 1)
connect _WIRE_60.c, _T_854
node _T_855 = bits(_WIRE_61, 2, 2)
connect _WIRE_60.eff, _T_855
node _T_856 = bits(_WIRE_61, 3, 3)
connect _WIRE_60.paa, _T_856
node _T_857 = bits(_WIRE_61, 4, 4)
connect _WIRE_60.pal, _T_857
node _T_858 = bits(_WIRE_61, 5, 5)
connect _WIRE_60.ppp, _T_858
node _T_859 = bits(_WIRE_61, 6, 6)
connect _WIRE_60.pr, _T_859
node _T_860 = bits(_WIRE_61, 7, 7)
connect _WIRE_60.px, _T_860
node _T_861 = bits(_WIRE_61, 8, 8)
connect _WIRE_60.pw, _T_861
node _T_862 = bits(_WIRE_61, 9, 9)
connect _WIRE_60.hr, _T_862
node _T_863 = bits(_WIRE_61, 10, 10)
connect _WIRE_60.hx, _T_863
node _T_864 = bits(_WIRE_61, 11, 11)
connect _WIRE_60.hw, _T_864
node _T_865 = bits(_WIRE_61, 12, 12)
connect _WIRE_60.sr, _T_865
node _T_866 = bits(_WIRE_61, 13, 13)
connect _WIRE_60.sx, _T_866
node _T_867 = bits(_WIRE_61, 14, 14)
connect _WIRE_60.sw, _T_867
node _T_868 = bits(_WIRE_61, 15, 15)
connect _WIRE_60.gf, _T_868
node _T_869 = bits(_WIRE_61, 16, 16)
connect _WIRE_60.pf, _T_869
node _T_870 = bits(_WIRE_61, 17, 17)
connect _WIRE_60.ae_stage2, _T_870
node _T_871 = bits(_WIRE_61, 18, 18)
connect _WIRE_60.ae_final, _T_871
node _T_872 = bits(_WIRE_61, 19, 19)
connect _WIRE_60.ae_ptw, _T_872
node _T_873 = bits(_WIRE_61, 20, 20)
connect _WIRE_60.g, _T_873
node _T_874 = bits(_WIRE_61, 21, 21)
connect _WIRE_60.u, _T_874
node _T_875 = bits(_WIRE_61, 41, 22)
connect _WIRE_60.ppn, _T_875
wire _WIRE_62 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_63 : UInt<42>
connect _WIRE_63, sectored_entries[0][1].data[3]
node _T_876 = bits(_WIRE_63, 0, 0)
connect _WIRE_62.fragmented_superpage, _T_876
node _T_877 = bits(_WIRE_63, 1, 1)
connect _WIRE_62.c, _T_877
node _T_878 = bits(_WIRE_63, 2, 2)
connect _WIRE_62.eff, _T_878
node _T_879 = bits(_WIRE_63, 3, 3)
connect _WIRE_62.paa, _T_879
node _T_880 = bits(_WIRE_63, 4, 4)
connect _WIRE_62.pal, _T_880
node _T_881 = bits(_WIRE_63, 5, 5)
connect _WIRE_62.ppp, _T_881
node _T_882 = bits(_WIRE_63, 6, 6)
connect _WIRE_62.pr, _T_882
node _T_883 = bits(_WIRE_63, 7, 7)
connect _WIRE_62.px, _T_883
node _T_884 = bits(_WIRE_63, 8, 8)
connect _WIRE_62.pw, _T_884
node _T_885 = bits(_WIRE_63, 9, 9)
connect _WIRE_62.hr, _T_885
node _T_886 = bits(_WIRE_63, 10, 10)
connect _WIRE_62.hx, _T_886
node _T_887 = bits(_WIRE_63, 11, 11)
connect _WIRE_62.hw, _T_887
node _T_888 = bits(_WIRE_63, 12, 12)
connect _WIRE_62.sr, _T_888
node _T_889 = bits(_WIRE_63, 13, 13)
connect _WIRE_62.sx, _T_889
node _T_890 = bits(_WIRE_63, 14, 14)
connect _WIRE_62.sw, _T_890
node _T_891 = bits(_WIRE_63, 15, 15)
connect _WIRE_62.gf, _T_891
node _T_892 = bits(_WIRE_63, 16, 16)
connect _WIRE_62.pf, _T_892
node _T_893 = bits(_WIRE_63, 17, 17)
connect _WIRE_62.ae_stage2, _T_893
node _T_894 = bits(_WIRE_63, 18, 18)
connect _WIRE_62.ae_final, _T_894
node _T_895 = bits(_WIRE_63, 19, 19)
connect _WIRE_62.ae_ptw, _T_895
node _T_896 = bits(_WIRE_63, 20, 20)
connect _WIRE_62.g, _T_896
node _T_897 = bits(_WIRE_63, 21, 21)
connect _WIRE_62.u, _T_897
node _T_898 = bits(_WIRE_63, 41, 22)
connect _WIRE_62.ppn, _T_898
node _T_899 = eq(sectored_entries[0][1].tag_v, _T_806)
when _T_899 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
node _T_900 = eq(sectored_entries[0][1].tag_v, _T_806)
when _T_900 :
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
node _T_901 = eq(sectored_entries[0][1].tag_v, _T_806)
when _T_901 :
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
node _T_902 = eq(sectored_entries[0][1].tag_v, _T_806)
when _T_902 :
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
node hv_2 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_2 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_903 = eq(hg_2, UInt<1>(0h0))
node _T_904 = and(_T_903, io.sfence.bits.rs1)
when _T_904 :
node _T_905 = xor(sectored_entries[0][2].tag_vpn, vpn)
node _T_906 = shr(_T_905, 2)
node _T_907 = eq(_T_906, UInt<1>(0h0))
node _T_908 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_909 = and(_T_907, _T_908)
when _T_909 :
wire _WIRE_64 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_65 : UInt<42>
connect _WIRE_65, sectored_entries[0][2].data[0]
node _T_910 = bits(_WIRE_65, 0, 0)
connect _WIRE_64.fragmented_superpage, _T_910
node _T_911 = bits(_WIRE_65, 1, 1)
connect _WIRE_64.c, _T_911
node _T_912 = bits(_WIRE_65, 2, 2)
connect _WIRE_64.eff, _T_912
node _T_913 = bits(_WIRE_65, 3, 3)
connect _WIRE_64.paa, _T_913
node _T_914 = bits(_WIRE_65, 4, 4)
connect _WIRE_64.pal, _T_914
node _T_915 = bits(_WIRE_65, 5, 5)
connect _WIRE_64.ppp, _T_915
node _T_916 = bits(_WIRE_65, 6, 6)
connect _WIRE_64.pr, _T_916
node _T_917 = bits(_WIRE_65, 7, 7)
connect _WIRE_64.px, _T_917
node _T_918 = bits(_WIRE_65, 8, 8)
connect _WIRE_64.pw, _T_918
node _T_919 = bits(_WIRE_65, 9, 9)
connect _WIRE_64.hr, _T_919
node _T_920 = bits(_WIRE_65, 10, 10)
connect _WIRE_64.hx, _T_920
node _T_921 = bits(_WIRE_65, 11, 11)
connect _WIRE_64.hw, _T_921
node _T_922 = bits(_WIRE_65, 12, 12)
connect _WIRE_64.sr, _T_922
node _T_923 = bits(_WIRE_65, 13, 13)
connect _WIRE_64.sx, _T_923
node _T_924 = bits(_WIRE_65, 14, 14)
connect _WIRE_64.sw, _T_924
node _T_925 = bits(_WIRE_65, 15, 15)
connect _WIRE_64.gf, _T_925
node _T_926 = bits(_WIRE_65, 16, 16)
connect _WIRE_64.pf, _T_926
node _T_927 = bits(_WIRE_65, 17, 17)
connect _WIRE_64.ae_stage2, _T_927
node _T_928 = bits(_WIRE_65, 18, 18)
connect _WIRE_64.ae_final, _T_928
node _T_929 = bits(_WIRE_65, 19, 19)
connect _WIRE_64.ae_ptw, _T_929
node _T_930 = bits(_WIRE_65, 20, 20)
connect _WIRE_64.g, _T_930
node _T_931 = bits(_WIRE_65, 21, 21)
connect _WIRE_64.u, _T_931
node _T_932 = bits(_WIRE_65, 41, 22)
connect _WIRE_64.ppn, _T_932
wire _WIRE_66 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_67 : UInt<42>
connect _WIRE_67, sectored_entries[0][2].data[1]
node _T_933 = bits(_WIRE_67, 0, 0)
connect _WIRE_66.fragmented_superpage, _T_933
node _T_934 = bits(_WIRE_67, 1, 1)
connect _WIRE_66.c, _T_934
node _T_935 = bits(_WIRE_67, 2, 2)
connect _WIRE_66.eff, _T_935
node _T_936 = bits(_WIRE_67, 3, 3)
connect _WIRE_66.paa, _T_936
node _T_937 = bits(_WIRE_67, 4, 4)
connect _WIRE_66.pal, _T_937
node _T_938 = bits(_WIRE_67, 5, 5)
connect _WIRE_66.ppp, _T_938
node _T_939 = bits(_WIRE_67, 6, 6)
connect _WIRE_66.pr, _T_939
node _T_940 = bits(_WIRE_67, 7, 7)
connect _WIRE_66.px, _T_940
node _T_941 = bits(_WIRE_67, 8, 8)
connect _WIRE_66.pw, _T_941
node _T_942 = bits(_WIRE_67, 9, 9)
connect _WIRE_66.hr, _T_942
node _T_943 = bits(_WIRE_67, 10, 10)
connect _WIRE_66.hx, _T_943
node _T_944 = bits(_WIRE_67, 11, 11)
connect _WIRE_66.hw, _T_944
node _T_945 = bits(_WIRE_67, 12, 12)
connect _WIRE_66.sr, _T_945
node _T_946 = bits(_WIRE_67, 13, 13)
connect _WIRE_66.sx, _T_946
node _T_947 = bits(_WIRE_67, 14, 14)
connect _WIRE_66.sw, _T_947
node _T_948 = bits(_WIRE_67, 15, 15)
connect _WIRE_66.gf, _T_948
node _T_949 = bits(_WIRE_67, 16, 16)
connect _WIRE_66.pf, _T_949
node _T_950 = bits(_WIRE_67, 17, 17)
connect _WIRE_66.ae_stage2, _T_950
node _T_951 = bits(_WIRE_67, 18, 18)
connect _WIRE_66.ae_final, _T_951
node _T_952 = bits(_WIRE_67, 19, 19)
connect _WIRE_66.ae_ptw, _T_952
node _T_953 = bits(_WIRE_67, 20, 20)
connect _WIRE_66.g, _T_953
node _T_954 = bits(_WIRE_67, 21, 21)
connect _WIRE_66.u, _T_954
node _T_955 = bits(_WIRE_67, 41, 22)
connect _WIRE_66.ppn, _T_955
wire _WIRE_68 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_69 : UInt<42>
connect _WIRE_69, sectored_entries[0][2].data[2]
node _T_956 = bits(_WIRE_69, 0, 0)
connect _WIRE_68.fragmented_superpage, _T_956
node _T_957 = bits(_WIRE_69, 1, 1)
connect _WIRE_68.c, _T_957
node _T_958 = bits(_WIRE_69, 2, 2)
connect _WIRE_68.eff, _T_958
node _T_959 = bits(_WIRE_69, 3, 3)
connect _WIRE_68.paa, _T_959
node _T_960 = bits(_WIRE_69, 4, 4)
connect _WIRE_68.pal, _T_960
node _T_961 = bits(_WIRE_69, 5, 5)
connect _WIRE_68.ppp, _T_961
node _T_962 = bits(_WIRE_69, 6, 6)
connect _WIRE_68.pr, _T_962
node _T_963 = bits(_WIRE_69, 7, 7)
connect _WIRE_68.px, _T_963
node _T_964 = bits(_WIRE_69, 8, 8)
connect _WIRE_68.pw, _T_964
node _T_965 = bits(_WIRE_69, 9, 9)
connect _WIRE_68.hr, _T_965
node _T_966 = bits(_WIRE_69, 10, 10)
connect _WIRE_68.hx, _T_966
node _T_967 = bits(_WIRE_69, 11, 11)
connect _WIRE_68.hw, _T_967
node _T_968 = bits(_WIRE_69, 12, 12)
connect _WIRE_68.sr, _T_968
node _T_969 = bits(_WIRE_69, 13, 13)
connect _WIRE_68.sx, _T_969
node _T_970 = bits(_WIRE_69, 14, 14)
connect _WIRE_68.sw, _T_970
node _T_971 = bits(_WIRE_69, 15, 15)
connect _WIRE_68.gf, _T_971
node _T_972 = bits(_WIRE_69, 16, 16)
connect _WIRE_68.pf, _T_972
node _T_973 = bits(_WIRE_69, 17, 17)
connect _WIRE_68.ae_stage2, _T_973
node _T_974 = bits(_WIRE_69, 18, 18)
connect _WIRE_68.ae_final, _T_974
node _T_975 = bits(_WIRE_69, 19, 19)
connect _WIRE_68.ae_ptw, _T_975
node _T_976 = bits(_WIRE_69, 20, 20)
connect _WIRE_68.g, _T_976
node _T_977 = bits(_WIRE_69, 21, 21)
connect _WIRE_68.u, _T_977
node _T_978 = bits(_WIRE_69, 41, 22)
connect _WIRE_68.ppn, _T_978
wire _WIRE_70 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_71 : UInt<42>
connect _WIRE_71, sectored_entries[0][2].data[3]
node _T_979 = bits(_WIRE_71, 0, 0)
connect _WIRE_70.fragmented_superpage, _T_979
node _T_980 = bits(_WIRE_71, 1, 1)
connect _WIRE_70.c, _T_980
node _T_981 = bits(_WIRE_71, 2, 2)
connect _WIRE_70.eff, _T_981
node _T_982 = bits(_WIRE_71, 3, 3)
connect _WIRE_70.paa, _T_982
node _T_983 = bits(_WIRE_71, 4, 4)
connect _WIRE_70.pal, _T_983
node _T_984 = bits(_WIRE_71, 5, 5)
connect _WIRE_70.ppp, _T_984
node _T_985 = bits(_WIRE_71, 6, 6)
connect _WIRE_70.pr, _T_985
node _T_986 = bits(_WIRE_71, 7, 7)
connect _WIRE_70.px, _T_986
node _T_987 = bits(_WIRE_71, 8, 8)
connect _WIRE_70.pw, _T_987
node _T_988 = bits(_WIRE_71, 9, 9)
connect _WIRE_70.hr, _T_988
node _T_989 = bits(_WIRE_71, 10, 10)
connect _WIRE_70.hx, _T_989
node _T_990 = bits(_WIRE_71, 11, 11)
connect _WIRE_70.hw, _T_990
node _T_991 = bits(_WIRE_71, 12, 12)
connect _WIRE_70.sr, _T_991
node _T_992 = bits(_WIRE_71, 13, 13)
connect _WIRE_70.sx, _T_992
node _T_993 = bits(_WIRE_71, 14, 14)
connect _WIRE_70.sw, _T_993
node _T_994 = bits(_WIRE_71, 15, 15)
connect _WIRE_70.gf, _T_994
node _T_995 = bits(_WIRE_71, 16, 16)
connect _WIRE_70.pf, _T_995
node _T_996 = bits(_WIRE_71, 17, 17)
connect _WIRE_70.ae_stage2, _T_996
node _T_997 = bits(_WIRE_71, 18, 18)
connect _WIRE_70.ae_final, _T_997
node _T_998 = bits(_WIRE_71, 19, 19)
connect _WIRE_70.ae_ptw, _T_998
node _T_999 = bits(_WIRE_71, 20, 20)
connect _WIRE_70.g, _T_999
node _T_1000 = bits(_WIRE_71, 21, 21)
connect _WIRE_70.u, _T_1000
node _T_1001 = bits(_WIRE_71, 41, 22)
connect _WIRE_70.ppn, _T_1001
node _T_1002 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1003 = bits(vpn, 1, 0)
node _T_1004 = eq(UInt<1>(0h0), _T_1003)
node _T_1005 = and(_T_1002, _T_1004)
when _T_1005 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
node _T_1006 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1007 = bits(vpn, 1, 0)
node _T_1008 = eq(UInt<1>(0h1), _T_1007)
node _T_1009 = and(_T_1006, _T_1008)
when _T_1009 :
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
node _T_1010 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1011 = bits(vpn, 1, 0)
node _T_1012 = eq(UInt<2>(0h2), _T_1011)
node _T_1013 = and(_T_1010, _T_1012)
when _T_1013 :
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
node _T_1014 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1015 = bits(vpn, 1, 0)
node _T_1016 = eq(UInt<2>(0h3), _T_1015)
node _T_1017 = and(_T_1014, _T_1016)
when _T_1017 :
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
node _T_1018 = xor(sectored_entries[0][2].tag_vpn, vpn)
node _T_1019 = shr(_T_1018, 18)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
wire _WIRE_72 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_73 : UInt<42>
connect _WIRE_73, sectored_entries[0][2].data[0]
node _T_1021 = bits(_WIRE_73, 0, 0)
connect _WIRE_72.fragmented_superpage, _T_1021
node _T_1022 = bits(_WIRE_73, 1, 1)
connect _WIRE_72.c, _T_1022
node _T_1023 = bits(_WIRE_73, 2, 2)
connect _WIRE_72.eff, _T_1023
node _T_1024 = bits(_WIRE_73, 3, 3)
connect _WIRE_72.paa, _T_1024
node _T_1025 = bits(_WIRE_73, 4, 4)
connect _WIRE_72.pal, _T_1025
node _T_1026 = bits(_WIRE_73, 5, 5)
connect _WIRE_72.ppp, _T_1026
node _T_1027 = bits(_WIRE_73, 6, 6)
connect _WIRE_72.pr, _T_1027
node _T_1028 = bits(_WIRE_73, 7, 7)
connect _WIRE_72.px, _T_1028
node _T_1029 = bits(_WIRE_73, 8, 8)
connect _WIRE_72.pw, _T_1029
node _T_1030 = bits(_WIRE_73, 9, 9)
connect _WIRE_72.hr, _T_1030
node _T_1031 = bits(_WIRE_73, 10, 10)
connect _WIRE_72.hx, _T_1031
node _T_1032 = bits(_WIRE_73, 11, 11)
connect _WIRE_72.hw, _T_1032
node _T_1033 = bits(_WIRE_73, 12, 12)
connect _WIRE_72.sr, _T_1033
node _T_1034 = bits(_WIRE_73, 13, 13)
connect _WIRE_72.sx, _T_1034
node _T_1035 = bits(_WIRE_73, 14, 14)
connect _WIRE_72.sw, _T_1035
node _T_1036 = bits(_WIRE_73, 15, 15)
connect _WIRE_72.gf, _T_1036
node _T_1037 = bits(_WIRE_73, 16, 16)
connect _WIRE_72.pf, _T_1037
node _T_1038 = bits(_WIRE_73, 17, 17)
connect _WIRE_72.ae_stage2, _T_1038
node _T_1039 = bits(_WIRE_73, 18, 18)
connect _WIRE_72.ae_final, _T_1039
node _T_1040 = bits(_WIRE_73, 19, 19)
connect _WIRE_72.ae_ptw, _T_1040
node _T_1041 = bits(_WIRE_73, 20, 20)
connect _WIRE_72.g, _T_1041
node _T_1042 = bits(_WIRE_73, 21, 21)
connect _WIRE_72.u, _T_1042
node _T_1043 = bits(_WIRE_73, 41, 22)
connect _WIRE_72.ppn, _T_1043
wire _WIRE_74 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_75 : UInt<42>
connect _WIRE_75, sectored_entries[0][2].data[1]
node _T_1044 = bits(_WIRE_75, 0, 0)
connect _WIRE_74.fragmented_superpage, _T_1044
node _T_1045 = bits(_WIRE_75, 1, 1)
connect _WIRE_74.c, _T_1045
node _T_1046 = bits(_WIRE_75, 2, 2)
connect _WIRE_74.eff, _T_1046
node _T_1047 = bits(_WIRE_75, 3, 3)
connect _WIRE_74.paa, _T_1047
node _T_1048 = bits(_WIRE_75, 4, 4)
connect _WIRE_74.pal, _T_1048
node _T_1049 = bits(_WIRE_75, 5, 5)
connect _WIRE_74.ppp, _T_1049
node _T_1050 = bits(_WIRE_75, 6, 6)
connect _WIRE_74.pr, _T_1050
node _T_1051 = bits(_WIRE_75, 7, 7)
connect _WIRE_74.px, _T_1051
node _T_1052 = bits(_WIRE_75, 8, 8)
connect _WIRE_74.pw, _T_1052
node _T_1053 = bits(_WIRE_75, 9, 9)
connect _WIRE_74.hr, _T_1053
node _T_1054 = bits(_WIRE_75, 10, 10)
connect _WIRE_74.hx, _T_1054
node _T_1055 = bits(_WIRE_75, 11, 11)
connect _WIRE_74.hw, _T_1055
node _T_1056 = bits(_WIRE_75, 12, 12)
connect _WIRE_74.sr, _T_1056
node _T_1057 = bits(_WIRE_75, 13, 13)
connect _WIRE_74.sx, _T_1057
node _T_1058 = bits(_WIRE_75, 14, 14)
connect _WIRE_74.sw, _T_1058
node _T_1059 = bits(_WIRE_75, 15, 15)
connect _WIRE_74.gf, _T_1059
node _T_1060 = bits(_WIRE_75, 16, 16)
connect _WIRE_74.pf, _T_1060
node _T_1061 = bits(_WIRE_75, 17, 17)
connect _WIRE_74.ae_stage2, _T_1061
node _T_1062 = bits(_WIRE_75, 18, 18)
connect _WIRE_74.ae_final, _T_1062
node _T_1063 = bits(_WIRE_75, 19, 19)
connect _WIRE_74.ae_ptw, _T_1063
node _T_1064 = bits(_WIRE_75, 20, 20)
connect _WIRE_74.g, _T_1064
node _T_1065 = bits(_WIRE_75, 21, 21)
connect _WIRE_74.u, _T_1065
node _T_1066 = bits(_WIRE_75, 41, 22)
connect _WIRE_74.ppn, _T_1066
wire _WIRE_76 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_77 : UInt<42>
connect _WIRE_77, sectored_entries[0][2].data[2]
node _T_1067 = bits(_WIRE_77, 0, 0)
connect _WIRE_76.fragmented_superpage, _T_1067
node _T_1068 = bits(_WIRE_77, 1, 1)
connect _WIRE_76.c, _T_1068
node _T_1069 = bits(_WIRE_77, 2, 2)
connect _WIRE_76.eff, _T_1069
node _T_1070 = bits(_WIRE_77, 3, 3)
connect _WIRE_76.paa, _T_1070
node _T_1071 = bits(_WIRE_77, 4, 4)
connect _WIRE_76.pal, _T_1071
node _T_1072 = bits(_WIRE_77, 5, 5)
connect _WIRE_76.ppp, _T_1072
node _T_1073 = bits(_WIRE_77, 6, 6)
connect _WIRE_76.pr, _T_1073
node _T_1074 = bits(_WIRE_77, 7, 7)
connect _WIRE_76.px, _T_1074
node _T_1075 = bits(_WIRE_77, 8, 8)
connect _WIRE_76.pw, _T_1075
node _T_1076 = bits(_WIRE_77, 9, 9)
connect _WIRE_76.hr, _T_1076
node _T_1077 = bits(_WIRE_77, 10, 10)
connect _WIRE_76.hx, _T_1077
node _T_1078 = bits(_WIRE_77, 11, 11)
connect _WIRE_76.hw, _T_1078
node _T_1079 = bits(_WIRE_77, 12, 12)
connect _WIRE_76.sr, _T_1079
node _T_1080 = bits(_WIRE_77, 13, 13)
connect _WIRE_76.sx, _T_1080
node _T_1081 = bits(_WIRE_77, 14, 14)
connect _WIRE_76.sw, _T_1081
node _T_1082 = bits(_WIRE_77, 15, 15)
connect _WIRE_76.gf, _T_1082
node _T_1083 = bits(_WIRE_77, 16, 16)
connect _WIRE_76.pf, _T_1083
node _T_1084 = bits(_WIRE_77, 17, 17)
connect _WIRE_76.ae_stage2, _T_1084
node _T_1085 = bits(_WIRE_77, 18, 18)
connect _WIRE_76.ae_final, _T_1085
node _T_1086 = bits(_WIRE_77, 19, 19)
connect _WIRE_76.ae_ptw, _T_1086
node _T_1087 = bits(_WIRE_77, 20, 20)
connect _WIRE_76.g, _T_1087
node _T_1088 = bits(_WIRE_77, 21, 21)
connect _WIRE_76.u, _T_1088
node _T_1089 = bits(_WIRE_77, 41, 22)
connect _WIRE_76.ppn, _T_1089
wire _WIRE_78 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_79 : UInt<42>
connect _WIRE_79, sectored_entries[0][2].data[3]
node _T_1090 = bits(_WIRE_79, 0, 0)
connect _WIRE_78.fragmented_superpage, _T_1090
node _T_1091 = bits(_WIRE_79, 1, 1)
connect _WIRE_78.c, _T_1091
node _T_1092 = bits(_WIRE_79, 2, 2)
connect _WIRE_78.eff, _T_1092
node _T_1093 = bits(_WIRE_79, 3, 3)
connect _WIRE_78.paa, _T_1093
node _T_1094 = bits(_WIRE_79, 4, 4)
connect _WIRE_78.pal, _T_1094
node _T_1095 = bits(_WIRE_79, 5, 5)
connect _WIRE_78.ppp, _T_1095
node _T_1096 = bits(_WIRE_79, 6, 6)
connect _WIRE_78.pr, _T_1096
node _T_1097 = bits(_WIRE_79, 7, 7)
connect _WIRE_78.px, _T_1097
node _T_1098 = bits(_WIRE_79, 8, 8)
connect _WIRE_78.pw, _T_1098
node _T_1099 = bits(_WIRE_79, 9, 9)
connect _WIRE_78.hr, _T_1099
node _T_1100 = bits(_WIRE_79, 10, 10)
connect _WIRE_78.hx, _T_1100
node _T_1101 = bits(_WIRE_79, 11, 11)
connect _WIRE_78.hw, _T_1101
node _T_1102 = bits(_WIRE_79, 12, 12)
connect _WIRE_78.sr, _T_1102
node _T_1103 = bits(_WIRE_79, 13, 13)
connect _WIRE_78.sx, _T_1103
node _T_1104 = bits(_WIRE_79, 14, 14)
connect _WIRE_78.sw, _T_1104
node _T_1105 = bits(_WIRE_79, 15, 15)
connect _WIRE_78.gf, _T_1105
node _T_1106 = bits(_WIRE_79, 16, 16)
connect _WIRE_78.pf, _T_1106
node _T_1107 = bits(_WIRE_79, 17, 17)
connect _WIRE_78.ae_stage2, _T_1107
node _T_1108 = bits(_WIRE_79, 18, 18)
connect _WIRE_78.ae_final, _T_1108
node _T_1109 = bits(_WIRE_79, 19, 19)
connect _WIRE_78.ae_ptw, _T_1109
node _T_1110 = bits(_WIRE_79, 20, 20)
connect _WIRE_78.g, _T_1110
node _T_1111 = bits(_WIRE_79, 21, 21)
connect _WIRE_78.u, _T_1111
node _T_1112 = bits(_WIRE_79, 41, 22)
connect _WIRE_78.ppn, _T_1112
node _T_1113 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1114 = and(_T_1113, _WIRE_72.fragmented_superpage)
when _T_1114 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
node _T_1115 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1116 = and(_T_1115, _WIRE_74.fragmented_superpage)
when _T_1116 :
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
node _T_1117 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1118 = and(_T_1117, _WIRE_76.fragmented_superpage)
when _T_1118 :
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
node _T_1119 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1120 = and(_T_1119, _WIRE_78.fragmented_superpage)
when _T_1120 :
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
else :
node _T_1121 = eq(hg_2, UInt<1>(0h0))
node _T_1122 = and(_T_1121, io.sfence.bits.rs2)
when _T_1122 :
wire _WIRE_80 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_81 : UInt<42>
connect _WIRE_81, sectored_entries[0][2].data[0]
node _T_1123 = bits(_WIRE_81, 0, 0)
connect _WIRE_80.fragmented_superpage, _T_1123
node _T_1124 = bits(_WIRE_81, 1, 1)
connect _WIRE_80.c, _T_1124
node _T_1125 = bits(_WIRE_81, 2, 2)
connect _WIRE_80.eff, _T_1125
node _T_1126 = bits(_WIRE_81, 3, 3)
connect _WIRE_80.paa, _T_1126
node _T_1127 = bits(_WIRE_81, 4, 4)
connect _WIRE_80.pal, _T_1127
node _T_1128 = bits(_WIRE_81, 5, 5)
connect _WIRE_80.ppp, _T_1128
node _T_1129 = bits(_WIRE_81, 6, 6)
connect _WIRE_80.pr, _T_1129
node _T_1130 = bits(_WIRE_81, 7, 7)
connect _WIRE_80.px, _T_1130
node _T_1131 = bits(_WIRE_81, 8, 8)
connect _WIRE_80.pw, _T_1131
node _T_1132 = bits(_WIRE_81, 9, 9)
connect _WIRE_80.hr, _T_1132
node _T_1133 = bits(_WIRE_81, 10, 10)
connect _WIRE_80.hx, _T_1133
node _T_1134 = bits(_WIRE_81, 11, 11)
connect _WIRE_80.hw, _T_1134
node _T_1135 = bits(_WIRE_81, 12, 12)
connect _WIRE_80.sr, _T_1135
node _T_1136 = bits(_WIRE_81, 13, 13)
connect _WIRE_80.sx, _T_1136
node _T_1137 = bits(_WIRE_81, 14, 14)
connect _WIRE_80.sw, _T_1137
node _T_1138 = bits(_WIRE_81, 15, 15)
connect _WIRE_80.gf, _T_1138
node _T_1139 = bits(_WIRE_81, 16, 16)
connect _WIRE_80.pf, _T_1139
node _T_1140 = bits(_WIRE_81, 17, 17)
connect _WIRE_80.ae_stage2, _T_1140
node _T_1141 = bits(_WIRE_81, 18, 18)
connect _WIRE_80.ae_final, _T_1141
node _T_1142 = bits(_WIRE_81, 19, 19)
connect _WIRE_80.ae_ptw, _T_1142
node _T_1143 = bits(_WIRE_81, 20, 20)
connect _WIRE_80.g, _T_1143
node _T_1144 = bits(_WIRE_81, 21, 21)
connect _WIRE_80.u, _T_1144
node _T_1145 = bits(_WIRE_81, 41, 22)
connect _WIRE_80.ppn, _T_1145
wire _WIRE_82 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_83 : UInt<42>
connect _WIRE_83, sectored_entries[0][2].data[1]
node _T_1146 = bits(_WIRE_83, 0, 0)
connect _WIRE_82.fragmented_superpage, _T_1146
node _T_1147 = bits(_WIRE_83, 1, 1)
connect _WIRE_82.c, _T_1147
node _T_1148 = bits(_WIRE_83, 2, 2)
connect _WIRE_82.eff, _T_1148
node _T_1149 = bits(_WIRE_83, 3, 3)
connect _WIRE_82.paa, _T_1149
node _T_1150 = bits(_WIRE_83, 4, 4)
connect _WIRE_82.pal, _T_1150
node _T_1151 = bits(_WIRE_83, 5, 5)
connect _WIRE_82.ppp, _T_1151
node _T_1152 = bits(_WIRE_83, 6, 6)
connect _WIRE_82.pr, _T_1152
node _T_1153 = bits(_WIRE_83, 7, 7)
connect _WIRE_82.px, _T_1153
node _T_1154 = bits(_WIRE_83, 8, 8)
connect _WIRE_82.pw, _T_1154
node _T_1155 = bits(_WIRE_83, 9, 9)
connect _WIRE_82.hr, _T_1155
node _T_1156 = bits(_WIRE_83, 10, 10)
connect _WIRE_82.hx, _T_1156
node _T_1157 = bits(_WIRE_83, 11, 11)
connect _WIRE_82.hw, _T_1157
node _T_1158 = bits(_WIRE_83, 12, 12)
connect _WIRE_82.sr, _T_1158
node _T_1159 = bits(_WIRE_83, 13, 13)
connect _WIRE_82.sx, _T_1159
node _T_1160 = bits(_WIRE_83, 14, 14)
connect _WIRE_82.sw, _T_1160
node _T_1161 = bits(_WIRE_83, 15, 15)
connect _WIRE_82.gf, _T_1161
node _T_1162 = bits(_WIRE_83, 16, 16)
connect _WIRE_82.pf, _T_1162
node _T_1163 = bits(_WIRE_83, 17, 17)
connect _WIRE_82.ae_stage2, _T_1163
node _T_1164 = bits(_WIRE_83, 18, 18)
connect _WIRE_82.ae_final, _T_1164
node _T_1165 = bits(_WIRE_83, 19, 19)
connect _WIRE_82.ae_ptw, _T_1165
node _T_1166 = bits(_WIRE_83, 20, 20)
connect _WIRE_82.g, _T_1166
node _T_1167 = bits(_WIRE_83, 21, 21)
connect _WIRE_82.u, _T_1167
node _T_1168 = bits(_WIRE_83, 41, 22)
connect _WIRE_82.ppn, _T_1168
wire _WIRE_84 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_85 : UInt<42>
connect _WIRE_85, sectored_entries[0][2].data[2]
node _T_1169 = bits(_WIRE_85, 0, 0)
connect _WIRE_84.fragmented_superpage, _T_1169
node _T_1170 = bits(_WIRE_85, 1, 1)
connect _WIRE_84.c, _T_1170
node _T_1171 = bits(_WIRE_85, 2, 2)
connect _WIRE_84.eff, _T_1171
node _T_1172 = bits(_WIRE_85, 3, 3)
connect _WIRE_84.paa, _T_1172
node _T_1173 = bits(_WIRE_85, 4, 4)
connect _WIRE_84.pal, _T_1173
node _T_1174 = bits(_WIRE_85, 5, 5)
connect _WIRE_84.ppp, _T_1174
node _T_1175 = bits(_WIRE_85, 6, 6)
connect _WIRE_84.pr, _T_1175
node _T_1176 = bits(_WIRE_85, 7, 7)
connect _WIRE_84.px, _T_1176
node _T_1177 = bits(_WIRE_85, 8, 8)
connect _WIRE_84.pw, _T_1177
node _T_1178 = bits(_WIRE_85, 9, 9)
connect _WIRE_84.hr, _T_1178
node _T_1179 = bits(_WIRE_85, 10, 10)
connect _WIRE_84.hx, _T_1179
node _T_1180 = bits(_WIRE_85, 11, 11)
connect _WIRE_84.hw, _T_1180
node _T_1181 = bits(_WIRE_85, 12, 12)
connect _WIRE_84.sr, _T_1181
node _T_1182 = bits(_WIRE_85, 13, 13)
connect _WIRE_84.sx, _T_1182
node _T_1183 = bits(_WIRE_85, 14, 14)
connect _WIRE_84.sw, _T_1183
node _T_1184 = bits(_WIRE_85, 15, 15)
connect _WIRE_84.gf, _T_1184
node _T_1185 = bits(_WIRE_85, 16, 16)
connect _WIRE_84.pf, _T_1185
node _T_1186 = bits(_WIRE_85, 17, 17)
connect _WIRE_84.ae_stage2, _T_1186
node _T_1187 = bits(_WIRE_85, 18, 18)
connect _WIRE_84.ae_final, _T_1187
node _T_1188 = bits(_WIRE_85, 19, 19)
connect _WIRE_84.ae_ptw, _T_1188
node _T_1189 = bits(_WIRE_85, 20, 20)
connect _WIRE_84.g, _T_1189
node _T_1190 = bits(_WIRE_85, 21, 21)
connect _WIRE_84.u, _T_1190
node _T_1191 = bits(_WIRE_85, 41, 22)
connect _WIRE_84.ppn, _T_1191
wire _WIRE_86 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_87 : UInt<42>
connect _WIRE_87, sectored_entries[0][2].data[3]
node _T_1192 = bits(_WIRE_87, 0, 0)
connect _WIRE_86.fragmented_superpage, _T_1192
node _T_1193 = bits(_WIRE_87, 1, 1)
connect _WIRE_86.c, _T_1193
node _T_1194 = bits(_WIRE_87, 2, 2)
connect _WIRE_86.eff, _T_1194
node _T_1195 = bits(_WIRE_87, 3, 3)
connect _WIRE_86.paa, _T_1195
node _T_1196 = bits(_WIRE_87, 4, 4)
connect _WIRE_86.pal, _T_1196
node _T_1197 = bits(_WIRE_87, 5, 5)
connect _WIRE_86.ppp, _T_1197
node _T_1198 = bits(_WIRE_87, 6, 6)
connect _WIRE_86.pr, _T_1198
node _T_1199 = bits(_WIRE_87, 7, 7)
connect _WIRE_86.px, _T_1199
node _T_1200 = bits(_WIRE_87, 8, 8)
connect _WIRE_86.pw, _T_1200
node _T_1201 = bits(_WIRE_87, 9, 9)
connect _WIRE_86.hr, _T_1201
node _T_1202 = bits(_WIRE_87, 10, 10)
connect _WIRE_86.hx, _T_1202
node _T_1203 = bits(_WIRE_87, 11, 11)
connect _WIRE_86.hw, _T_1203
node _T_1204 = bits(_WIRE_87, 12, 12)
connect _WIRE_86.sr, _T_1204
node _T_1205 = bits(_WIRE_87, 13, 13)
connect _WIRE_86.sx, _T_1205
node _T_1206 = bits(_WIRE_87, 14, 14)
connect _WIRE_86.sw, _T_1206
node _T_1207 = bits(_WIRE_87, 15, 15)
connect _WIRE_86.gf, _T_1207
node _T_1208 = bits(_WIRE_87, 16, 16)
connect _WIRE_86.pf, _T_1208
node _T_1209 = bits(_WIRE_87, 17, 17)
connect _WIRE_86.ae_stage2, _T_1209
node _T_1210 = bits(_WIRE_87, 18, 18)
connect _WIRE_86.ae_final, _T_1210
node _T_1211 = bits(_WIRE_87, 19, 19)
connect _WIRE_86.ae_ptw, _T_1211
node _T_1212 = bits(_WIRE_87, 20, 20)
connect _WIRE_86.g, _T_1212
node _T_1213 = bits(_WIRE_87, 21, 21)
connect _WIRE_86.u, _T_1213
node _T_1214 = bits(_WIRE_87, 41, 22)
connect _WIRE_86.ppn, _T_1214
node _T_1215 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1216 = eq(_WIRE_80.g, UInt<1>(0h0))
node _T_1217 = and(_T_1215, _T_1216)
when _T_1217 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
node _T_1218 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1219 = eq(_WIRE_82.g, UInt<1>(0h0))
node _T_1220 = and(_T_1218, _T_1219)
when _T_1220 :
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
node _T_1221 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1222 = eq(_WIRE_84.g, UInt<1>(0h0))
node _T_1223 = and(_T_1221, _T_1222)
when _T_1223 :
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
node _T_1224 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1225 = eq(_WIRE_86.g, UInt<1>(0h0))
node _T_1226 = and(_T_1224, _T_1225)
when _T_1226 :
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
else :
node _T_1227 = or(hv_2, hg_2)
wire _WIRE_88 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_89 : UInt<42>
connect _WIRE_89, sectored_entries[0][2].data[0]
node _T_1228 = bits(_WIRE_89, 0, 0)
connect _WIRE_88.fragmented_superpage, _T_1228
node _T_1229 = bits(_WIRE_89, 1, 1)
connect _WIRE_88.c, _T_1229
node _T_1230 = bits(_WIRE_89, 2, 2)
connect _WIRE_88.eff, _T_1230
node _T_1231 = bits(_WIRE_89, 3, 3)
connect _WIRE_88.paa, _T_1231
node _T_1232 = bits(_WIRE_89, 4, 4)
connect _WIRE_88.pal, _T_1232
node _T_1233 = bits(_WIRE_89, 5, 5)
connect _WIRE_88.ppp, _T_1233
node _T_1234 = bits(_WIRE_89, 6, 6)
connect _WIRE_88.pr, _T_1234
node _T_1235 = bits(_WIRE_89, 7, 7)
connect _WIRE_88.px, _T_1235
node _T_1236 = bits(_WIRE_89, 8, 8)
connect _WIRE_88.pw, _T_1236
node _T_1237 = bits(_WIRE_89, 9, 9)
connect _WIRE_88.hr, _T_1237
node _T_1238 = bits(_WIRE_89, 10, 10)
connect _WIRE_88.hx, _T_1238
node _T_1239 = bits(_WIRE_89, 11, 11)
connect _WIRE_88.hw, _T_1239
node _T_1240 = bits(_WIRE_89, 12, 12)
connect _WIRE_88.sr, _T_1240
node _T_1241 = bits(_WIRE_89, 13, 13)
connect _WIRE_88.sx, _T_1241
node _T_1242 = bits(_WIRE_89, 14, 14)
connect _WIRE_88.sw, _T_1242
node _T_1243 = bits(_WIRE_89, 15, 15)
connect _WIRE_88.gf, _T_1243
node _T_1244 = bits(_WIRE_89, 16, 16)
connect _WIRE_88.pf, _T_1244
node _T_1245 = bits(_WIRE_89, 17, 17)
connect _WIRE_88.ae_stage2, _T_1245
node _T_1246 = bits(_WIRE_89, 18, 18)
connect _WIRE_88.ae_final, _T_1246
node _T_1247 = bits(_WIRE_89, 19, 19)
connect _WIRE_88.ae_ptw, _T_1247
node _T_1248 = bits(_WIRE_89, 20, 20)
connect _WIRE_88.g, _T_1248
node _T_1249 = bits(_WIRE_89, 21, 21)
connect _WIRE_88.u, _T_1249
node _T_1250 = bits(_WIRE_89, 41, 22)
connect _WIRE_88.ppn, _T_1250
wire _WIRE_90 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_91 : UInt<42>
connect _WIRE_91, sectored_entries[0][2].data[1]
node _T_1251 = bits(_WIRE_91, 0, 0)
connect _WIRE_90.fragmented_superpage, _T_1251
node _T_1252 = bits(_WIRE_91, 1, 1)
connect _WIRE_90.c, _T_1252
node _T_1253 = bits(_WIRE_91, 2, 2)
connect _WIRE_90.eff, _T_1253
node _T_1254 = bits(_WIRE_91, 3, 3)
connect _WIRE_90.paa, _T_1254
node _T_1255 = bits(_WIRE_91, 4, 4)
connect _WIRE_90.pal, _T_1255
node _T_1256 = bits(_WIRE_91, 5, 5)
connect _WIRE_90.ppp, _T_1256
node _T_1257 = bits(_WIRE_91, 6, 6)
connect _WIRE_90.pr, _T_1257
node _T_1258 = bits(_WIRE_91, 7, 7)
connect _WIRE_90.px, _T_1258
node _T_1259 = bits(_WIRE_91, 8, 8)
connect _WIRE_90.pw, _T_1259
node _T_1260 = bits(_WIRE_91, 9, 9)
connect _WIRE_90.hr, _T_1260
node _T_1261 = bits(_WIRE_91, 10, 10)
connect _WIRE_90.hx, _T_1261
node _T_1262 = bits(_WIRE_91, 11, 11)
connect _WIRE_90.hw, _T_1262
node _T_1263 = bits(_WIRE_91, 12, 12)
connect _WIRE_90.sr, _T_1263
node _T_1264 = bits(_WIRE_91, 13, 13)
connect _WIRE_90.sx, _T_1264
node _T_1265 = bits(_WIRE_91, 14, 14)
connect _WIRE_90.sw, _T_1265
node _T_1266 = bits(_WIRE_91, 15, 15)
connect _WIRE_90.gf, _T_1266
node _T_1267 = bits(_WIRE_91, 16, 16)
connect _WIRE_90.pf, _T_1267
node _T_1268 = bits(_WIRE_91, 17, 17)
connect _WIRE_90.ae_stage2, _T_1268
node _T_1269 = bits(_WIRE_91, 18, 18)
connect _WIRE_90.ae_final, _T_1269
node _T_1270 = bits(_WIRE_91, 19, 19)
connect _WIRE_90.ae_ptw, _T_1270
node _T_1271 = bits(_WIRE_91, 20, 20)
connect _WIRE_90.g, _T_1271
node _T_1272 = bits(_WIRE_91, 21, 21)
connect _WIRE_90.u, _T_1272
node _T_1273 = bits(_WIRE_91, 41, 22)
connect _WIRE_90.ppn, _T_1273
wire _WIRE_92 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_93 : UInt<42>
connect _WIRE_93, sectored_entries[0][2].data[2]
node _T_1274 = bits(_WIRE_93, 0, 0)
connect _WIRE_92.fragmented_superpage, _T_1274
node _T_1275 = bits(_WIRE_93, 1, 1)
connect _WIRE_92.c, _T_1275
node _T_1276 = bits(_WIRE_93, 2, 2)
connect _WIRE_92.eff, _T_1276
node _T_1277 = bits(_WIRE_93, 3, 3)
connect _WIRE_92.paa, _T_1277
node _T_1278 = bits(_WIRE_93, 4, 4)
connect _WIRE_92.pal, _T_1278
node _T_1279 = bits(_WIRE_93, 5, 5)
connect _WIRE_92.ppp, _T_1279
node _T_1280 = bits(_WIRE_93, 6, 6)
connect _WIRE_92.pr, _T_1280
node _T_1281 = bits(_WIRE_93, 7, 7)
connect _WIRE_92.px, _T_1281
node _T_1282 = bits(_WIRE_93, 8, 8)
connect _WIRE_92.pw, _T_1282
node _T_1283 = bits(_WIRE_93, 9, 9)
connect _WIRE_92.hr, _T_1283
node _T_1284 = bits(_WIRE_93, 10, 10)
connect _WIRE_92.hx, _T_1284
node _T_1285 = bits(_WIRE_93, 11, 11)
connect _WIRE_92.hw, _T_1285
node _T_1286 = bits(_WIRE_93, 12, 12)
connect _WIRE_92.sr, _T_1286
node _T_1287 = bits(_WIRE_93, 13, 13)
connect _WIRE_92.sx, _T_1287
node _T_1288 = bits(_WIRE_93, 14, 14)
connect _WIRE_92.sw, _T_1288
node _T_1289 = bits(_WIRE_93, 15, 15)
connect _WIRE_92.gf, _T_1289
node _T_1290 = bits(_WIRE_93, 16, 16)
connect _WIRE_92.pf, _T_1290
node _T_1291 = bits(_WIRE_93, 17, 17)
connect _WIRE_92.ae_stage2, _T_1291
node _T_1292 = bits(_WIRE_93, 18, 18)
connect _WIRE_92.ae_final, _T_1292
node _T_1293 = bits(_WIRE_93, 19, 19)
connect _WIRE_92.ae_ptw, _T_1293
node _T_1294 = bits(_WIRE_93, 20, 20)
connect _WIRE_92.g, _T_1294
node _T_1295 = bits(_WIRE_93, 21, 21)
connect _WIRE_92.u, _T_1295
node _T_1296 = bits(_WIRE_93, 41, 22)
connect _WIRE_92.ppn, _T_1296
wire _WIRE_94 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_95 : UInt<42>
connect _WIRE_95, sectored_entries[0][2].data[3]
node _T_1297 = bits(_WIRE_95, 0, 0)
connect _WIRE_94.fragmented_superpage, _T_1297
node _T_1298 = bits(_WIRE_95, 1, 1)
connect _WIRE_94.c, _T_1298
node _T_1299 = bits(_WIRE_95, 2, 2)
connect _WIRE_94.eff, _T_1299
node _T_1300 = bits(_WIRE_95, 3, 3)
connect _WIRE_94.paa, _T_1300
node _T_1301 = bits(_WIRE_95, 4, 4)
connect _WIRE_94.pal, _T_1301
node _T_1302 = bits(_WIRE_95, 5, 5)
connect _WIRE_94.ppp, _T_1302
node _T_1303 = bits(_WIRE_95, 6, 6)
connect _WIRE_94.pr, _T_1303
node _T_1304 = bits(_WIRE_95, 7, 7)
connect _WIRE_94.px, _T_1304
node _T_1305 = bits(_WIRE_95, 8, 8)
connect _WIRE_94.pw, _T_1305
node _T_1306 = bits(_WIRE_95, 9, 9)
connect _WIRE_94.hr, _T_1306
node _T_1307 = bits(_WIRE_95, 10, 10)
connect _WIRE_94.hx, _T_1307
node _T_1308 = bits(_WIRE_95, 11, 11)
connect _WIRE_94.hw, _T_1308
node _T_1309 = bits(_WIRE_95, 12, 12)
connect _WIRE_94.sr, _T_1309
node _T_1310 = bits(_WIRE_95, 13, 13)
connect _WIRE_94.sx, _T_1310
node _T_1311 = bits(_WIRE_95, 14, 14)
connect _WIRE_94.sw, _T_1311
node _T_1312 = bits(_WIRE_95, 15, 15)
connect _WIRE_94.gf, _T_1312
node _T_1313 = bits(_WIRE_95, 16, 16)
connect _WIRE_94.pf, _T_1313
node _T_1314 = bits(_WIRE_95, 17, 17)
connect _WIRE_94.ae_stage2, _T_1314
node _T_1315 = bits(_WIRE_95, 18, 18)
connect _WIRE_94.ae_final, _T_1315
node _T_1316 = bits(_WIRE_95, 19, 19)
connect _WIRE_94.ae_ptw, _T_1316
node _T_1317 = bits(_WIRE_95, 20, 20)
connect _WIRE_94.g, _T_1317
node _T_1318 = bits(_WIRE_95, 21, 21)
connect _WIRE_94.u, _T_1318
node _T_1319 = bits(_WIRE_95, 41, 22)
connect _WIRE_94.ppn, _T_1319
node _T_1320 = eq(sectored_entries[0][2].tag_v, _T_1227)
when _T_1320 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
node _T_1321 = eq(sectored_entries[0][2].tag_v, _T_1227)
when _T_1321 :
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
node _T_1322 = eq(sectored_entries[0][2].tag_v, _T_1227)
when _T_1322 :
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
node _T_1323 = eq(sectored_entries[0][2].tag_v, _T_1227)
when _T_1323 :
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
node hv_3 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_3 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_1324 = eq(hg_3, UInt<1>(0h0))
node _T_1325 = and(_T_1324, io.sfence.bits.rs1)
when _T_1325 :
node _T_1326 = xor(sectored_entries[0][3].tag_vpn, vpn)
node _T_1327 = shr(_T_1326, 2)
node _T_1328 = eq(_T_1327, UInt<1>(0h0))
node _T_1329 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1330 = and(_T_1328, _T_1329)
when _T_1330 :
wire _WIRE_96 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_97 : UInt<42>
connect _WIRE_97, sectored_entries[0][3].data[0]
node _T_1331 = bits(_WIRE_97, 0, 0)
connect _WIRE_96.fragmented_superpage, _T_1331
node _T_1332 = bits(_WIRE_97, 1, 1)
connect _WIRE_96.c, _T_1332
node _T_1333 = bits(_WIRE_97, 2, 2)
connect _WIRE_96.eff, _T_1333
node _T_1334 = bits(_WIRE_97, 3, 3)
connect _WIRE_96.paa, _T_1334
node _T_1335 = bits(_WIRE_97, 4, 4)
connect _WIRE_96.pal, _T_1335
node _T_1336 = bits(_WIRE_97, 5, 5)
connect _WIRE_96.ppp, _T_1336
node _T_1337 = bits(_WIRE_97, 6, 6)
connect _WIRE_96.pr, _T_1337
node _T_1338 = bits(_WIRE_97, 7, 7)
connect _WIRE_96.px, _T_1338
node _T_1339 = bits(_WIRE_97, 8, 8)
connect _WIRE_96.pw, _T_1339
node _T_1340 = bits(_WIRE_97, 9, 9)
connect _WIRE_96.hr, _T_1340
node _T_1341 = bits(_WIRE_97, 10, 10)
connect _WIRE_96.hx, _T_1341
node _T_1342 = bits(_WIRE_97, 11, 11)
connect _WIRE_96.hw, _T_1342
node _T_1343 = bits(_WIRE_97, 12, 12)
connect _WIRE_96.sr, _T_1343
node _T_1344 = bits(_WIRE_97, 13, 13)
connect _WIRE_96.sx, _T_1344
node _T_1345 = bits(_WIRE_97, 14, 14)
connect _WIRE_96.sw, _T_1345
node _T_1346 = bits(_WIRE_97, 15, 15)
connect _WIRE_96.gf, _T_1346
node _T_1347 = bits(_WIRE_97, 16, 16)
connect _WIRE_96.pf, _T_1347
node _T_1348 = bits(_WIRE_97, 17, 17)
connect _WIRE_96.ae_stage2, _T_1348
node _T_1349 = bits(_WIRE_97, 18, 18)
connect _WIRE_96.ae_final, _T_1349
node _T_1350 = bits(_WIRE_97, 19, 19)
connect _WIRE_96.ae_ptw, _T_1350
node _T_1351 = bits(_WIRE_97, 20, 20)
connect _WIRE_96.g, _T_1351
node _T_1352 = bits(_WIRE_97, 21, 21)
connect _WIRE_96.u, _T_1352
node _T_1353 = bits(_WIRE_97, 41, 22)
connect _WIRE_96.ppn, _T_1353
wire _WIRE_98 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_99 : UInt<42>
connect _WIRE_99, sectored_entries[0][3].data[1]
node _T_1354 = bits(_WIRE_99, 0, 0)
connect _WIRE_98.fragmented_superpage, _T_1354
node _T_1355 = bits(_WIRE_99, 1, 1)
connect _WIRE_98.c, _T_1355
node _T_1356 = bits(_WIRE_99, 2, 2)
connect _WIRE_98.eff, _T_1356
node _T_1357 = bits(_WIRE_99, 3, 3)
connect _WIRE_98.paa, _T_1357
node _T_1358 = bits(_WIRE_99, 4, 4)
connect _WIRE_98.pal, _T_1358
node _T_1359 = bits(_WIRE_99, 5, 5)
connect _WIRE_98.ppp, _T_1359
node _T_1360 = bits(_WIRE_99, 6, 6)
connect _WIRE_98.pr, _T_1360
node _T_1361 = bits(_WIRE_99, 7, 7)
connect _WIRE_98.px, _T_1361
node _T_1362 = bits(_WIRE_99, 8, 8)
connect _WIRE_98.pw, _T_1362
node _T_1363 = bits(_WIRE_99, 9, 9)
connect _WIRE_98.hr, _T_1363
node _T_1364 = bits(_WIRE_99, 10, 10)
connect _WIRE_98.hx, _T_1364
node _T_1365 = bits(_WIRE_99, 11, 11)
connect _WIRE_98.hw, _T_1365
node _T_1366 = bits(_WIRE_99, 12, 12)
connect _WIRE_98.sr, _T_1366
node _T_1367 = bits(_WIRE_99, 13, 13)
connect _WIRE_98.sx, _T_1367
node _T_1368 = bits(_WIRE_99, 14, 14)
connect _WIRE_98.sw, _T_1368
node _T_1369 = bits(_WIRE_99, 15, 15)
connect _WIRE_98.gf, _T_1369
node _T_1370 = bits(_WIRE_99, 16, 16)
connect _WIRE_98.pf, _T_1370
node _T_1371 = bits(_WIRE_99, 17, 17)
connect _WIRE_98.ae_stage2, _T_1371
node _T_1372 = bits(_WIRE_99, 18, 18)
connect _WIRE_98.ae_final, _T_1372
node _T_1373 = bits(_WIRE_99, 19, 19)
connect _WIRE_98.ae_ptw, _T_1373
node _T_1374 = bits(_WIRE_99, 20, 20)
connect _WIRE_98.g, _T_1374
node _T_1375 = bits(_WIRE_99, 21, 21)
connect _WIRE_98.u, _T_1375
node _T_1376 = bits(_WIRE_99, 41, 22)
connect _WIRE_98.ppn, _T_1376
wire _WIRE_100 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_101 : UInt<42>
connect _WIRE_101, sectored_entries[0][3].data[2]
node _T_1377 = bits(_WIRE_101, 0, 0)
connect _WIRE_100.fragmented_superpage, _T_1377
node _T_1378 = bits(_WIRE_101, 1, 1)
connect _WIRE_100.c, _T_1378
node _T_1379 = bits(_WIRE_101, 2, 2)
connect _WIRE_100.eff, _T_1379
node _T_1380 = bits(_WIRE_101, 3, 3)
connect _WIRE_100.paa, _T_1380
node _T_1381 = bits(_WIRE_101, 4, 4)
connect _WIRE_100.pal, _T_1381
node _T_1382 = bits(_WIRE_101, 5, 5)
connect _WIRE_100.ppp, _T_1382
node _T_1383 = bits(_WIRE_101, 6, 6)
connect _WIRE_100.pr, _T_1383
node _T_1384 = bits(_WIRE_101, 7, 7)
connect _WIRE_100.px, _T_1384
node _T_1385 = bits(_WIRE_101, 8, 8)
connect _WIRE_100.pw, _T_1385
node _T_1386 = bits(_WIRE_101, 9, 9)
connect _WIRE_100.hr, _T_1386
node _T_1387 = bits(_WIRE_101, 10, 10)
connect _WIRE_100.hx, _T_1387
node _T_1388 = bits(_WIRE_101, 11, 11)
connect _WIRE_100.hw, _T_1388
node _T_1389 = bits(_WIRE_101, 12, 12)
connect _WIRE_100.sr, _T_1389
node _T_1390 = bits(_WIRE_101, 13, 13)
connect _WIRE_100.sx, _T_1390
node _T_1391 = bits(_WIRE_101, 14, 14)
connect _WIRE_100.sw, _T_1391
node _T_1392 = bits(_WIRE_101, 15, 15)
connect _WIRE_100.gf, _T_1392
node _T_1393 = bits(_WIRE_101, 16, 16)
connect _WIRE_100.pf, _T_1393
node _T_1394 = bits(_WIRE_101, 17, 17)
connect _WIRE_100.ae_stage2, _T_1394
node _T_1395 = bits(_WIRE_101, 18, 18)
connect _WIRE_100.ae_final, _T_1395
node _T_1396 = bits(_WIRE_101, 19, 19)
connect _WIRE_100.ae_ptw, _T_1396
node _T_1397 = bits(_WIRE_101, 20, 20)
connect _WIRE_100.g, _T_1397
node _T_1398 = bits(_WIRE_101, 21, 21)
connect _WIRE_100.u, _T_1398
node _T_1399 = bits(_WIRE_101, 41, 22)
connect _WIRE_100.ppn, _T_1399
wire _WIRE_102 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_103 : UInt<42>
connect _WIRE_103, sectored_entries[0][3].data[3]
node _T_1400 = bits(_WIRE_103, 0, 0)
connect _WIRE_102.fragmented_superpage, _T_1400
node _T_1401 = bits(_WIRE_103, 1, 1)
connect _WIRE_102.c, _T_1401
node _T_1402 = bits(_WIRE_103, 2, 2)
connect _WIRE_102.eff, _T_1402
node _T_1403 = bits(_WIRE_103, 3, 3)
connect _WIRE_102.paa, _T_1403
node _T_1404 = bits(_WIRE_103, 4, 4)
connect _WIRE_102.pal, _T_1404
node _T_1405 = bits(_WIRE_103, 5, 5)
connect _WIRE_102.ppp, _T_1405
node _T_1406 = bits(_WIRE_103, 6, 6)
connect _WIRE_102.pr, _T_1406
node _T_1407 = bits(_WIRE_103, 7, 7)
connect _WIRE_102.px, _T_1407
node _T_1408 = bits(_WIRE_103, 8, 8)
connect _WIRE_102.pw, _T_1408
node _T_1409 = bits(_WIRE_103, 9, 9)
connect _WIRE_102.hr, _T_1409
node _T_1410 = bits(_WIRE_103, 10, 10)
connect _WIRE_102.hx, _T_1410
node _T_1411 = bits(_WIRE_103, 11, 11)
connect _WIRE_102.hw, _T_1411
node _T_1412 = bits(_WIRE_103, 12, 12)
connect _WIRE_102.sr, _T_1412
node _T_1413 = bits(_WIRE_103, 13, 13)
connect _WIRE_102.sx, _T_1413
node _T_1414 = bits(_WIRE_103, 14, 14)
connect _WIRE_102.sw, _T_1414
node _T_1415 = bits(_WIRE_103, 15, 15)
connect _WIRE_102.gf, _T_1415
node _T_1416 = bits(_WIRE_103, 16, 16)
connect _WIRE_102.pf, _T_1416
node _T_1417 = bits(_WIRE_103, 17, 17)
connect _WIRE_102.ae_stage2, _T_1417
node _T_1418 = bits(_WIRE_103, 18, 18)
connect _WIRE_102.ae_final, _T_1418
node _T_1419 = bits(_WIRE_103, 19, 19)
connect _WIRE_102.ae_ptw, _T_1419
node _T_1420 = bits(_WIRE_103, 20, 20)
connect _WIRE_102.g, _T_1420
node _T_1421 = bits(_WIRE_103, 21, 21)
connect _WIRE_102.u, _T_1421
node _T_1422 = bits(_WIRE_103, 41, 22)
connect _WIRE_102.ppn, _T_1422
node _T_1423 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1424 = bits(vpn, 1, 0)
node _T_1425 = eq(UInt<1>(0h0), _T_1424)
node _T_1426 = and(_T_1423, _T_1425)
when _T_1426 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
node _T_1427 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1428 = bits(vpn, 1, 0)
node _T_1429 = eq(UInt<1>(0h1), _T_1428)
node _T_1430 = and(_T_1427, _T_1429)
when _T_1430 :
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
node _T_1431 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1432 = bits(vpn, 1, 0)
node _T_1433 = eq(UInt<2>(0h2), _T_1432)
node _T_1434 = and(_T_1431, _T_1433)
when _T_1434 :
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
node _T_1435 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1436 = bits(vpn, 1, 0)
node _T_1437 = eq(UInt<2>(0h3), _T_1436)
node _T_1438 = and(_T_1435, _T_1437)
when _T_1438 :
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
node _T_1439 = xor(sectored_entries[0][3].tag_vpn, vpn)
node _T_1440 = shr(_T_1439, 18)
node _T_1441 = eq(_T_1440, UInt<1>(0h0))
when _T_1441 :
wire _WIRE_104 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_105 : UInt<42>
connect _WIRE_105, sectored_entries[0][3].data[0]
node _T_1442 = bits(_WIRE_105, 0, 0)
connect _WIRE_104.fragmented_superpage, _T_1442
node _T_1443 = bits(_WIRE_105, 1, 1)
connect _WIRE_104.c, _T_1443
node _T_1444 = bits(_WIRE_105, 2, 2)
connect _WIRE_104.eff, _T_1444
node _T_1445 = bits(_WIRE_105, 3, 3)
connect _WIRE_104.paa, _T_1445
node _T_1446 = bits(_WIRE_105, 4, 4)
connect _WIRE_104.pal, _T_1446
node _T_1447 = bits(_WIRE_105, 5, 5)
connect _WIRE_104.ppp, _T_1447
node _T_1448 = bits(_WIRE_105, 6, 6)
connect _WIRE_104.pr, _T_1448
node _T_1449 = bits(_WIRE_105, 7, 7)
connect _WIRE_104.px, _T_1449
node _T_1450 = bits(_WIRE_105, 8, 8)
connect _WIRE_104.pw, _T_1450
node _T_1451 = bits(_WIRE_105, 9, 9)
connect _WIRE_104.hr, _T_1451
node _T_1452 = bits(_WIRE_105, 10, 10)
connect _WIRE_104.hx, _T_1452
node _T_1453 = bits(_WIRE_105, 11, 11)
connect _WIRE_104.hw, _T_1453
node _T_1454 = bits(_WIRE_105, 12, 12)
connect _WIRE_104.sr, _T_1454
node _T_1455 = bits(_WIRE_105, 13, 13)
connect _WIRE_104.sx, _T_1455
node _T_1456 = bits(_WIRE_105, 14, 14)
connect _WIRE_104.sw, _T_1456
node _T_1457 = bits(_WIRE_105, 15, 15)
connect _WIRE_104.gf, _T_1457
node _T_1458 = bits(_WIRE_105, 16, 16)
connect _WIRE_104.pf, _T_1458
node _T_1459 = bits(_WIRE_105, 17, 17)
connect _WIRE_104.ae_stage2, _T_1459
node _T_1460 = bits(_WIRE_105, 18, 18)
connect _WIRE_104.ae_final, _T_1460
node _T_1461 = bits(_WIRE_105, 19, 19)
connect _WIRE_104.ae_ptw, _T_1461
node _T_1462 = bits(_WIRE_105, 20, 20)
connect _WIRE_104.g, _T_1462
node _T_1463 = bits(_WIRE_105, 21, 21)
connect _WIRE_104.u, _T_1463
node _T_1464 = bits(_WIRE_105, 41, 22)
connect _WIRE_104.ppn, _T_1464
wire _WIRE_106 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_107 : UInt<42>
connect _WIRE_107, sectored_entries[0][3].data[1]
node _T_1465 = bits(_WIRE_107, 0, 0)
connect _WIRE_106.fragmented_superpage, _T_1465
node _T_1466 = bits(_WIRE_107, 1, 1)
connect _WIRE_106.c, _T_1466
node _T_1467 = bits(_WIRE_107, 2, 2)
connect _WIRE_106.eff, _T_1467
node _T_1468 = bits(_WIRE_107, 3, 3)
connect _WIRE_106.paa, _T_1468
node _T_1469 = bits(_WIRE_107, 4, 4)
connect _WIRE_106.pal, _T_1469
node _T_1470 = bits(_WIRE_107, 5, 5)
connect _WIRE_106.ppp, _T_1470
node _T_1471 = bits(_WIRE_107, 6, 6)
connect _WIRE_106.pr, _T_1471
node _T_1472 = bits(_WIRE_107, 7, 7)
connect _WIRE_106.px, _T_1472
node _T_1473 = bits(_WIRE_107, 8, 8)
connect _WIRE_106.pw, _T_1473
node _T_1474 = bits(_WIRE_107, 9, 9)
connect _WIRE_106.hr, _T_1474
node _T_1475 = bits(_WIRE_107, 10, 10)
connect _WIRE_106.hx, _T_1475
node _T_1476 = bits(_WIRE_107, 11, 11)
connect _WIRE_106.hw, _T_1476
node _T_1477 = bits(_WIRE_107, 12, 12)
connect _WIRE_106.sr, _T_1477
node _T_1478 = bits(_WIRE_107, 13, 13)
connect _WIRE_106.sx, _T_1478
node _T_1479 = bits(_WIRE_107, 14, 14)
connect _WIRE_106.sw, _T_1479
node _T_1480 = bits(_WIRE_107, 15, 15)
connect _WIRE_106.gf, _T_1480
node _T_1481 = bits(_WIRE_107, 16, 16)
connect _WIRE_106.pf, _T_1481
node _T_1482 = bits(_WIRE_107, 17, 17)
connect _WIRE_106.ae_stage2, _T_1482
node _T_1483 = bits(_WIRE_107, 18, 18)
connect _WIRE_106.ae_final, _T_1483
node _T_1484 = bits(_WIRE_107, 19, 19)
connect _WIRE_106.ae_ptw, _T_1484
node _T_1485 = bits(_WIRE_107, 20, 20)
connect _WIRE_106.g, _T_1485
node _T_1486 = bits(_WIRE_107, 21, 21)
connect _WIRE_106.u, _T_1486
node _T_1487 = bits(_WIRE_107, 41, 22)
connect _WIRE_106.ppn, _T_1487
wire _WIRE_108 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_109 : UInt<42>
connect _WIRE_109, sectored_entries[0][3].data[2]
node _T_1488 = bits(_WIRE_109, 0, 0)
connect _WIRE_108.fragmented_superpage, _T_1488
node _T_1489 = bits(_WIRE_109, 1, 1)
connect _WIRE_108.c, _T_1489
node _T_1490 = bits(_WIRE_109, 2, 2)
connect _WIRE_108.eff, _T_1490
node _T_1491 = bits(_WIRE_109, 3, 3)
connect _WIRE_108.paa, _T_1491
node _T_1492 = bits(_WIRE_109, 4, 4)
connect _WIRE_108.pal, _T_1492
node _T_1493 = bits(_WIRE_109, 5, 5)
connect _WIRE_108.ppp, _T_1493
node _T_1494 = bits(_WIRE_109, 6, 6)
connect _WIRE_108.pr, _T_1494
node _T_1495 = bits(_WIRE_109, 7, 7)
connect _WIRE_108.px, _T_1495
node _T_1496 = bits(_WIRE_109, 8, 8)
connect _WIRE_108.pw, _T_1496
node _T_1497 = bits(_WIRE_109, 9, 9)
connect _WIRE_108.hr, _T_1497
node _T_1498 = bits(_WIRE_109, 10, 10)
connect _WIRE_108.hx, _T_1498
node _T_1499 = bits(_WIRE_109, 11, 11)
connect _WIRE_108.hw, _T_1499
node _T_1500 = bits(_WIRE_109, 12, 12)
connect _WIRE_108.sr, _T_1500
node _T_1501 = bits(_WIRE_109, 13, 13)
connect _WIRE_108.sx, _T_1501
node _T_1502 = bits(_WIRE_109, 14, 14)
connect _WIRE_108.sw, _T_1502
node _T_1503 = bits(_WIRE_109, 15, 15)
connect _WIRE_108.gf, _T_1503
node _T_1504 = bits(_WIRE_109, 16, 16)
connect _WIRE_108.pf, _T_1504
node _T_1505 = bits(_WIRE_109, 17, 17)
connect _WIRE_108.ae_stage2, _T_1505
node _T_1506 = bits(_WIRE_109, 18, 18)
connect _WIRE_108.ae_final, _T_1506
node _T_1507 = bits(_WIRE_109, 19, 19)
connect _WIRE_108.ae_ptw, _T_1507
node _T_1508 = bits(_WIRE_109, 20, 20)
connect _WIRE_108.g, _T_1508
node _T_1509 = bits(_WIRE_109, 21, 21)
connect _WIRE_108.u, _T_1509
node _T_1510 = bits(_WIRE_109, 41, 22)
connect _WIRE_108.ppn, _T_1510
wire _WIRE_110 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_111 : UInt<42>
connect _WIRE_111, sectored_entries[0][3].data[3]
node _T_1511 = bits(_WIRE_111, 0, 0)
connect _WIRE_110.fragmented_superpage, _T_1511
node _T_1512 = bits(_WIRE_111, 1, 1)
connect _WIRE_110.c, _T_1512
node _T_1513 = bits(_WIRE_111, 2, 2)
connect _WIRE_110.eff, _T_1513
node _T_1514 = bits(_WIRE_111, 3, 3)
connect _WIRE_110.paa, _T_1514
node _T_1515 = bits(_WIRE_111, 4, 4)
connect _WIRE_110.pal, _T_1515
node _T_1516 = bits(_WIRE_111, 5, 5)
connect _WIRE_110.ppp, _T_1516
node _T_1517 = bits(_WIRE_111, 6, 6)
connect _WIRE_110.pr, _T_1517
node _T_1518 = bits(_WIRE_111, 7, 7)
connect _WIRE_110.px, _T_1518
node _T_1519 = bits(_WIRE_111, 8, 8)
connect _WIRE_110.pw, _T_1519
node _T_1520 = bits(_WIRE_111, 9, 9)
connect _WIRE_110.hr, _T_1520
node _T_1521 = bits(_WIRE_111, 10, 10)
connect _WIRE_110.hx, _T_1521
node _T_1522 = bits(_WIRE_111, 11, 11)
connect _WIRE_110.hw, _T_1522
node _T_1523 = bits(_WIRE_111, 12, 12)
connect _WIRE_110.sr, _T_1523
node _T_1524 = bits(_WIRE_111, 13, 13)
connect _WIRE_110.sx, _T_1524
node _T_1525 = bits(_WIRE_111, 14, 14)
connect _WIRE_110.sw, _T_1525
node _T_1526 = bits(_WIRE_111, 15, 15)
connect _WIRE_110.gf, _T_1526
node _T_1527 = bits(_WIRE_111, 16, 16)
connect _WIRE_110.pf, _T_1527
node _T_1528 = bits(_WIRE_111, 17, 17)
connect _WIRE_110.ae_stage2, _T_1528
node _T_1529 = bits(_WIRE_111, 18, 18)
connect _WIRE_110.ae_final, _T_1529
node _T_1530 = bits(_WIRE_111, 19, 19)
connect _WIRE_110.ae_ptw, _T_1530
node _T_1531 = bits(_WIRE_111, 20, 20)
connect _WIRE_110.g, _T_1531
node _T_1532 = bits(_WIRE_111, 21, 21)
connect _WIRE_110.u, _T_1532
node _T_1533 = bits(_WIRE_111, 41, 22)
connect _WIRE_110.ppn, _T_1533
node _T_1534 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1535 = and(_T_1534, _WIRE_104.fragmented_superpage)
when _T_1535 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
node _T_1536 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1537 = and(_T_1536, _WIRE_106.fragmented_superpage)
when _T_1537 :
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
node _T_1538 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1539 = and(_T_1538, _WIRE_108.fragmented_superpage)
when _T_1539 :
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
node _T_1540 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1541 = and(_T_1540, _WIRE_110.fragmented_superpage)
when _T_1541 :
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
else :
node _T_1542 = eq(hg_3, UInt<1>(0h0))
node _T_1543 = and(_T_1542, io.sfence.bits.rs2)
when _T_1543 :
wire _WIRE_112 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_113 : UInt<42>
connect _WIRE_113, sectored_entries[0][3].data[0]
node _T_1544 = bits(_WIRE_113, 0, 0)
connect _WIRE_112.fragmented_superpage, _T_1544
node _T_1545 = bits(_WIRE_113, 1, 1)
connect _WIRE_112.c, _T_1545
node _T_1546 = bits(_WIRE_113, 2, 2)
connect _WIRE_112.eff, _T_1546
node _T_1547 = bits(_WIRE_113, 3, 3)
connect _WIRE_112.paa, _T_1547
node _T_1548 = bits(_WIRE_113, 4, 4)
connect _WIRE_112.pal, _T_1548
node _T_1549 = bits(_WIRE_113, 5, 5)
connect _WIRE_112.ppp, _T_1549
node _T_1550 = bits(_WIRE_113, 6, 6)
connect _WIRE_112.pr, _T_1550
node _T_1551 = bits(_WIRE_113, 7, 7)
connect _WIRE_112.px, _T_1551
node _T_1552 = bits(_WIRE_113, 8, 8)
connect _WIRE_112.pw, _T_1552
node _T_1553 = bits(_WIRE_113, 9, 9)
connect _WIRE_112.hr, _T_1553
node _T_1554 = bits(_WIRE_113, 10, 10)
connect _WIRE_112.hx, _T_1554
node _T_1555 = bits(_WIRE_113, 11, 11)
connect _WIRE_112.hw, _T_1555
node _T_1556 = bits(_WIRE_113, 12, 12)
connect _WIRE_112.sr, _T_1556
node _T_1557 = bits(_WIRE_113, 13, 13)
connect _WIRE_112.sx, _T_1557
node _T_1558 = bits(_WIRE_113, 14, 14)
connect _WIRE_112.sw, _T_1558
node _T_1559 = bits(_WIRE_113, 15, 15)
connect _WIRE_112.gf, _T_1559
node _T_1560 = bits(_WIRE_113, 16, 16)
connect _WIRE_112.pf, _T_1560
node _T_1561 = bits(_WIRE_113, 17, 17)
connect _WIRE_112.ae_stage2, _T_1561
node _T_1562 = bits(_WIRE_113, 18, 18)
connect _WIRE_112.ae_final, _T_1562
node _T_1563 = bits(_WIRE_113, 19, 19)
connect _WIRE_112.ae_ptw, _T_1563
node _T_1564 = bits(_WIRE_113, 20, 20)
connect _WIRE_112.g, _T_1564
node _T_1565 = bits(_WIRE_113, 21, 21)
connect _WIRE_112.u, _T_1565
node _T_1566 = bits(_WIRE_113, 41, 22)
connect _WIRE_112.ppn, _T_1566
wire _WIRE_114 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_115 : UInt<42>
connect _WIRE_115, sectored_entries[0][3].data[1]
node _T_1567 = bits(_WIRE_115, 0, 0)
connect _WIRE_114.fragmented_superpage, _T_1567
node _T_1568 = bits(_WIRE_115, 1, 1)
connect _WIRE_114.c, _T_1568
node _T_1569 = bits(_WIRE_115, 2, 2)
connect _WIRE_114.eff, _T_1569
node _T_1570 = bits(_WIRE_115, 3, 3)
connect _WIRE_114.paa, _T_1570
node _T_1571 = bits(_WIRE_115, 4, 4)
connect _WIRE_114.pal, _T_1571
node _T_1572 = bits(_WIRE_115, 5, 5)
connect _WIRE_114.ppp, _T_1572
node _T_1573 = bits(_WIRE_115, 6, 6)
connect _WIRE_114.pr, _T_1573
node _T_1574 = bits(_WIRE_115, 7, 7)
connect _WIRE_114.px, _T_1574
node _T_1575 = bits(_WIRE_115, 8, 8)
connect _WIRE_114.pw, _T_1575
node _T_1576 = bits(_WIRE_115, 9, 9)
connect _WIRE_114.hr, _T_1576
node _T_1577 = bits(_WIRE_115, 10, 10)
connect _WIRE_114.hx, _T_1577
node _T_1578 = bits(_WIRE_115, 11, 11)
connect _WIRE_114.hw, _T_1578
node _T_1579 = bits(_WIRE_115, 12, 12)
connect _WIRE_114.sr, _T_1579
node _T_1580 = bits(_WIRE_115, 13, 13)
connect _WIRE_114.sx, _T_1580
node _T_1581 = bits(_WIRE_115, 14, 14)
connect _WIRE_114.sw, _T_1581
node _T_1582 = bits(_WIRE_115, 15, 15)
connect _WIRE_114.gf, _T_1582
node _T_1583 = bits(_WIRE_115, 16, 16)
connect _WIRE_114.pf, _T_1583
node _T_1584 = bits(_WIRE_115, 17, 17)
connect _WIRE_114.ae_stage2, _T_1584
node _T_1585 = bits(_WIRE_115, 18, 18)
connect _WIRE_114.ae_final, _T_1585
node _T_1586 = bits(_WIRE_115, 19, 19)
connect _WIRE_114.ae_ptw, _T_1586
node _T_1587 = bits(_WIRE_115, 20, 20)
connect _WIRE_114.g, _T_1587
node _T_1588 = bits(_WIRE_115, 21, 21)
connect _WIRE_114.u, _T_1588
node _T_1589 = bits(_WIRE_115, 41, 22)
connect _WIRE_114.ppn, _T_1589
wire _WIRE_116 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_117 : UInt<42>
connect _WIRE_117, sectored_entries[0][3].data[2]
node _T_1590 = bits(_WIRE_117, 0, 0)
connect _WIRE_116.fragmented_superpage, _T_1590
node _T_1591 = bits(_WIRE_117, 1, 1)
connect _WIRE_116.c, _T_1591
node _T_1592 = bits(_WIRE_117, 2, 2)
connect _WIRE_116.eff, _T_1592
node _T_1593 = bits(_WIRE_117, 3, 3)
connect _WIRE_116.paa, _T_1593
node _T_1594 = bits(_WIRE_117, 4, 4)
connect _WIRE_116.pal, _T_1594
node _T_1595 = bits(_WIRE_117, 5, 5)
connect _WIRE_116.ppp, _T_1595
node _T_1596 = bits(_WIRE_117, 6, 6)
connect _WIRE_116.pr, _T_1596
node _T_1597 = bits(_WIRE_117, 7, 7)
connect _WIRE_116.px, _T_1597
node _T_1598 = bits(_WIRE_117, 8, 8)
connect _WIRE_116.pw, _T_1598
node _T_1599 = bits(_WIRE_117, 9, 9)
connect _WIRE_116.hr, _T_1599
node _T_1600 = bits(_WIRE_117, 10, 10)
connect _WIRE_116.hx, _T_1600
node _T_1601 = bits(_WIRE_117, 11, 11)
connect _WIRE_116.hw, _T_1601
node _T_1602 = bits(_WIRE_117, 12, 12)
connect _WIRE_116.sr, _T_1602
node _T_1603 = bits(_WIRE_117, 13, 13)
connect _WIRE_116.sx, _T_1603
node _T_1604 = bits(_WIRE_117, 14, 14)
connect _WIRE_116.sw, _T_1604
node _T_1605 = bits(_WIRE_117, 15, 15)
connect _WIRE_116.gf, _T_1605
node _T_1606 = bits(_WIRE_117, 16, 16)
connect _WIRE_116.pf, _T_1606
node _T_1607 = bits(_WIRE_117, 17, 17)
connect _WIRE_116.ae_stage2, _T_1607
node _T_1608 = bits(_WIRE_117, 18, 18)
connect _WIRE_116.ae_final, _T_1608
node _T_1609 = bits(_WIRE_117, 19, 19)
connect _WIRE_116.ae_ptw, _T_1609
node _T_1610 = bits(_WIRE_117, 20, 20)
connect _WIRE_116.g, _T_1610
node _T_1611 = bits(_WIRE_117, 21, 21)
connect _WIRE_116.u, _T_1611
node _T_1612 = bits(_WIRE_117, 41, 22)
connect _WIRE_116.ppn, _T_1612
wire _WIRE_118 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_119 : UInt<42>
connect _WIRE_119, sectored_entries[0][3].data[3]
node _T_1613 = bits(_WIRE_119, 0, 0)
connect _WIRE_118.fragmented_superpage, _T_1613
node _T_1614 = bits(_WIRE_119, 1, 1)
connect _WIRE_118.c, _T_1614
node _T_1615 = bits(_WIRE_119, 2, 2)
connect _WIRE_118.eff, _T_1615
node _T_1616 = bits(_WIRE_119, 3, 3)
connect _WIRE_118.paa, _T_1616
node _T_1617 = bits(_WIRE_119, 4, 4)
connect _WIRE_118.pal, _T_1617
node _T_1618 = bits(_WIRE_119, 5, 5)
connect _WIRE_118.ppp, _T_1618
node _T_1619 = bits(_WIRE_119, 6, 6)
connect _WIRE_118.pr, _T_1619
node _T_1620 = bits(_WIRE_119, 7, 7)
connect _WIRE_118.px, _T_1620
node _T_1621 = bits(_WIRE_119, 8, 8)
connect _WIRE_118.pw, _T_1621
node _T_1622 = bits(_WIRE_119, 9, 9)
connect _WIRE_118.hr, _T_1622
node _T_1623 = bits(_WIRE_119, 10, 10)
connect _WIRE_118.hx, _T_1623
node _T_1624 = bits(_WIRE_119, 11, 11)
connect _WIRE_118.hw, _T_1624
node _T_1625 = bits(_WIRE_119, 12, 12)
connect _WIRE_118.sr, _T_1625
node _T_1626 = bits(_WIRE_119, 13, 13)
connect _WIRE_118.sx, _T_1626
node _T_1627 = bits(_WIRE_119, 14, 14)
connect _WIRE_118.sw, _T_1627
node _T_1628 = bits(_WIRE_119, 15, 15)
connect _WIRE_118.gf, _T_1628
node _T_1629 = bits(_WIRE_119, 16, 16)
connect _WIRE_118.pf, _T_1629
node _T_1630 = bits(_WIRE_119, 17, 17)
connect _WIRE_118.ae_stage2, _T_1630
node _T_1631 = bits(_WIRE_119, 18, 18)
connect _WIRE_118.ae_final, _T_1631
node _T_1632 = bits(_WIRE_119, 19, 19)
connect _WIRE_118.ae_ptw, _T_1632
node _T_1633 = bits(_WIRE_119, 20, 20)
connect _WIRE_118.g, _T_1633
node _T_1634 = bits(_WIRE_119, 21, 21)
connect _WIRE_118.u, _T_1634
node _T_1635 = bits(_WIRE_119, 41, 22)
connect _WIRE_118.ppn, _T_1635
node _T_1636 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1637 = eq(_WIRE_112.g, UInt<1>(0h0))
node _T_1638 = and(_T_1636, _T_1637)
when _T_1638 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
node _T_1639 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1640 = eq(_WIRE_114.g, UInt<1>(0h0))
node _T_1641 = and(_T_1639, _T_1640)
when _T_1641 :
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
node _T_1642 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1643 = eq(_WIRE_116.g, UInt<1>(0h0))
node _T_1644 = and(_T_1642, _T_1643)
when _T_1644 :
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
node _T_1645 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1646 = eq(_WIRE_118.g, UInt<1>(0h0))
node _T_1647 = and(_T_1645, _T_1646)
when _T_1647 :
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
else :
node _T_1648 = or(hv_3, hg_3)
wire _WIRE_120 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_121 : UInt<42>
connect _WIRE_121, sectored_entries[0][3].data[0]
node _T_1649 = bits(_WIRE_121, 0, 0)
connect _WIRE_120.fragmented_superpage, _T_1649
node _T_1650 = bits(_WIRE_121, 1, 1)
connect _WIRE_120.c, _T_1650
node _T_1651 = bits(_WIRE_121, 2, 2)
connect _WIRE_120.eff, _T_1651
node _T_1652 = bits(_WIRE_121, 3, 3)
connect _WIRE_120.paa, _T_1652
node _T_1653 = bits(_WIRE_121, 4, 4)
connect _WIRE_120.pal, _T_1653
node _T_1654 = bits(_WIRE_121, 5, 5)
connect _WIRE_120.ppp, _T_1654
node _T_1655 = bits(_WIRE_121, 6, 6)
connect _WIRE_120.pr, _T_1655
node _T_1656 = bits(_WIRE_121, 7, 7)
connect _WIRE_120.px, _T_1656
node _T_1657 = bits(_WIRE_121, 8, 8)
connect _WIRE_120.pw, _T_1657
node _T_1658 = bits(_WIRE_121, 9, 9)
connect _WIRE_120.hr, _T_1658
node _T_1659 = bits(_WIRE_121, 10, 10)
connect _WIRE_120.hx, _T_1659
node _T_1660 = bits(_WIRE_121, 11, 11)
connect _WIRE_120.hw, _T_1660
node _T_1661 = bits(_WIRE_121, 12, 12)
connect _WIRE_120.sr, _T_1661
node _T_1662 = bits(_WIRE_121, 13, 13)
connect _WIRE_120.sx, _T_1662
node _T_1663 = bits(_WIRE_121, 14, 14)
connect _WIRE_120.sw, _T_1663
node _T_1664 = bits(_WIRE_121, 15, 15)
connect _WIRE_120.gf, _T_1664
node _T_1665 = bits(_WIRE_121, 16, 16)
connect _WIRE_120.pf, _T_1665
node _T_1666 = bits(_WIRE_121, 17, 17)
connect _WIRE_120.ae_stage2, _T_1666
node _T_1667 = bits(_WIRE_121, 18, 18)
connect _WIRE_120.ae_final, _T_1667
node _T_1668 = bits(_WIRE_121, 19, 19)
connect _WIRE_120.ae_ptw, _T_1668
node _T_1669 = bits(_WIRE_121, 20, 20)
connect _WIRE_120.g, _T_1669
node _T_1670 = bits(_WIRE_121, 21, 21)
connect _WIRE_120.u, _T_1670
node _T_1671 = bits(_WIRE_121, 41, 22)
connect _WIRE_120.ppn, _T_1671
wire _WIRE_122 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_123 : UInt<42>
connect _WIRE_123, sectored_entries[0][3].data[1]
node _T_1672 = bits(_WIRE_123, 0, 0)
connect _WIRE_122.fragmented_superpage, _T_1672
node _T_1673 = bits(_WIRE_123, 1, 1)
connect _WIRE_122.c, _T_1673
node _T_1674 = bits(_WIRE_123, 2, 2)
connect _WIRE_122.eff, _T_1674
node _T_1675 = bits(_WIRE_123, 3, 3)
connect _WIRE_122.paa, _T_1675
node _T_1676 = bits(_WIRE_123, 4, 4)
connect _WIRE_122.pal, _T_1676
node _T_1677 = bits(_WIRE_123, 5, 5)
connect _WIRE_122.ppp, _T_1677
node _T_1678 = bits(_WIRE_123, 6, 6)
connect _WIRE_122.pr, _T_1678
node _T_1679 = bits(_WIRE_123, 7, 7)
connect _WIRE_122.px, _T_1679
node _T_1680 = bits(_WIRE_123, 8, 8)
connect _WIRE_122.pw, _T_1680
node _T_1681 = bits(_WIRE_123, 9, 9)
connect _WIRE_122.hr, _T_1681
node _T_1682 = bits(_WIRE_123, 10, 10)
connect _WIRE_122.hx, _T_1682
node _T_1683 = bits(_WIRE_123, 11, 11)
connect _WIRE_122.hw, _T_1683
node _T_1684 = bits(_WIRE_123, 12, 12)
connect _WIRE_122.sr, _T_1684
node _T_1685 = bits(_WIRE_123, 13, 13)
connect _WIRE_122.sx, _T_1685
node _T_1686 = bits(_WIRE_123, 14, 14)
connect _WIRE_122.sw, _T_1686
node _T_1687 = bits(_WIRE_123, 15, 15)
connect _WIRE_122.gf, _T_1687
node _T_1688 = bits(_WIRE_123, 16, 16)
connect _WIRE_122.pf, _T_1688
node _T_1689 = bits(_WIRE_123, 17, 17)
connect _WIRE_122.ae_stage2, _T_1689
node _T_1690 = bits(_WIRE_123, 18, 18)
connect _WIRE_122.ae_final, _T_1690
node _T_1691 = bits(_WIRE_123, 19, 19)
connect _WIRE_122.ae_ptw, _T_1691
node _T_1692 = bits(_WIRE_123, 20, 20)
connect _WIRE_122.g, _T_1692
node _T_1693 = bits(_WIRE_123, 21, 21)
connect _WIRE_122.u, _T_1693
node _T_1694 = bits(_WIRE_123, 41, 22)
connect _WIRE_122.ppn, _T_1694
wire _WIRE_124 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_125 : UInt<42>
connect _WIRE_125, sectored_entries[0][3].data[2]
node _T_1695 = bits(_WIRE_125, 0, 0)
connect _WIRE_124.fragmented_superpage, _T_1695
node _T_1696 = bits(_WIRE_125, 1, 1)
connect _WIRE_124.c, _T_1696
node _T_1697 = bits(_WIRE_125, 2, 2)
connect _WIRE_124.eff, _T_1697
node _T_1698 = bits(_WIRE_125, 3, 3)
connect _WIRE_124.paa, _T_1698
node _T_1699 = bits(_WIRE_125, 4, 4)
connect _WIRE_124.pal, _T_1699
node _T_1700 = bits(_WIRE_125, 5, 5)
connect _WIRE_124.ppp, _T_1700
node _T_1701 = bits(_WIRE_125, 6, 6)
connect _WIRE_124.pr, _T_1701
node _T_1702 = bits(_WIRE_125, 7, 7)
connect _WIRE_124.px, _T_1702
node _T_1703 = bits(_WIRE_125, 8, 8)
connect _WIRE_124.pw, _T_1703
node _T_1704 = bits(_WIRE_125, 9, 9)
connect _WIRE_124.hr, _T_1704
node _T_1705 = bits(_WIRE_125, 10, 10)
connect _WIRE_124.hx, _T_1705
node _T_1706 = bits(_WIRE_125, 11, 11)
connect _WIRE_124.hw, _T_1706
node _T_1707 = bits(_WIRE_125, 12, 12)
connect _WIRE_124.sr, _T_1707
node _T_1708 = bits(_WIRE_125, 13, 13)
connect _WIRE_124.sx, _T_1708
node _T_1709 = bits(_WIRE_125, 14, 14)
connect _WIRE_124.sw, _T_1709
node _T_1710 = bits(_WIRE_125, 15, 15)
connect _WIRE_124.gf, _T_1710
node _T_1711 = bits(_WIRE_125, 16, 16)
connect _WIRE_124.pf, _T_1711
node _T_1712 = bits(_WIRE_125, 17, 17)
connect _WIRE_124.ae_stage2, _T_1712
node _T_1713 = bits(_WIRE_125, 18, 18)
connect _WIRE_124.ae_final, _T_1713
node _T_1714 = bits(_WIRE_125, 19, 19)
connect _WIRE_124.ae_ptw, _T_1714
node _T_1715 = bits(_WIRE_125, 20, 20)
connect _WIRE_124.g, _T_1715
node _T_1716 = bits(_WIRE_125, 21, 21)
connect _WIRE_124.u, _T_1716
node _T_1717 = bits(_WIRE_125, 41, 22)
connect _WIRE_124.ppn, _T_1717
wire _WIRE_126 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_127 : UInt<42>
connect _WIRE_127, sectored_entries[0][3].data[3]
node _T_1718 = bits(_WIRE_127, 0, 0)
connect _WIRE_126.fragmented_superpage, _T_1718
node _T_1719 = bits(_WIRE_127, 1, 1)
connect _WIRE_126.c, _T_1719
node _T_1720 = bits(_WIRE_127, 2, 2)
connect _WIRE_126.eff, _T_1720
node _T_1721 = bits(_WIRE_127, 3, 3)
connect _WIRE_126.paa, _T_1721
node _T_1722 = bits(_WIRE_127, 4, 4)
connect _WIRE_126.pal, _T_1722
node _T_1723 = bits(_WIRE_127, 5, 5)
connect _WIRE_126.ppp, _T_1723
node _T_1724 = bits(_WIRE_127, 6, 6)
connect _WIRE_126.pr, _T_1724
node _T_1725 = bits(_WIRE_127, 7, 7)
connect _WIRE_126.px, _T_1725
node _T_1726 = bits(_WIRE_127, 8, 8)
connect _WIRE_126.pw, _T_1726
node _T_1727 = bits(_WIRE_127, 9, 9)
connect _WIRE_126.hr, _T_1727
node _T_1728 = bits(_WIRE_127, 10, 10)
connect _WIRE_126.hx, _T_1728
node _T_1729 = bits(_WIRE_127, 11, 11)
connect _WIRE_126.hw, _T_1729
node _T_1730 = bits(_WIRE_127, 12, 12)
connect _WIRE_126.sr, _T_1730
node _T_1731 = bits(_WIRE_127, 13, 13)
connect _WIRE_126.sx, _T_1731
node _T_1732 = bits(_WIRE_127, 14, 14)
connect _WIRE_126.sw, _T_1732
node _T_1733 = bits(_WIRE_127, 15, 15)
connect _WIRE_126.gf, _T_1733
node _T_1734 = bits(_WIRE_127, 16, 16)
connect _WIRE_126.pf, _T_1734
node _T_1735 = bits(_WIRE_127, 17, 17)
connect _WIRE_126.ae_stage2, _T_1735
node _T_1736 = bits(_WIRE_127, 18, 18)
connect _WIRE_126.ae_final, _T_1736
node _T_1737 = bits(_WIRE_127, 19, 19)
connect _WIRE_126.ae_ptw, _T_1737
node _T_1738 = bits(_WIRE_127, 20, 20)
connect _WIRE_126.g, _T_1738
node _T_1739 = bits(_WIRE_127, 21, 21)
connect _WIRE_126.u, _T_1739
node _T_1740 = bits(_WIRE_127, 41, 22)
connect _WIRE_126.ppn, _T_1740
node _T_1741 = eq(sectored_entries[0][3].tag_v, _T_1648)
when _T_1741 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
node _T_1742 = eq(sectored_entries[0][3].tag_v, _T_1648)
when _T_1742 :
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
node _T_1743 = eq(sectored_entries[0][3].tag_v, _T_1648)
when _T_1743 :
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
node _T_1744 = eq(sectored_entries[0][3].tag_v, _T_1648)
when _T_1744 :
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
node hv_4 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_4 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_1745 = eq(hg_4, UInt<1>(0h0))
node _T_1746 = and(_T_1745, io.sfence.bits.rs1)
when _T_1746 :
node _T_1747 = xor(sectored_entries[0][4].tag_vpn, vpn)
node _T_1748 = shr(_T_1747, 2)
node _T_1749 = eq(_T_1748, UInt<1>(0h0))
node _T_1750 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1751 = and(_T_1749, _T_1750)
when _T_1751 :
wire _WIRE_128 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_129 : UInt<42>
connect _WIRE_129, sectored_entries[0][4].data[0]
node _T_1752 = bits(_WIRE_129, 0, 0)
connect _WIRE_128.fragmented_superpage, _T_1752
node _T_1753 = bits(_WIRE_129, 1, 1)
connect _WIRE_128.c, _T_1753
node _T_1754 = bits(_WIRE_129, 2, 2)
connect _WIRE_128.eff, _T_1754
node _T_1755 = bits(_WIRE_129, 3, 3)
connect _WIRE_128.paa, _T_1755
node _T_1756 = bits(_WIRE_129, 4, 4)
connect _WIRE_128.pal, _T_1756
node _T_1757 = bits(_WIRE_129, 5, 5)
connect _WIRE_128.ppp, _T_1757
node _T_1758 = bits(_WIRE_129, 6, 6)
connect _WIRE_128.pr, _T_1758
node _T_1759 = bits(_WIRE_129, 7, 7)
connect _WIRE_128.px, _T_1759
node _T_1760 = bits(_WIRE_129, 8, 8)
connect _WIRE_128.pw, _T_1760
node _T_1761 = bits(_WIRE_129, 9, 9)
connect _WIRE_128.hr, _T_1761
node _T_1762 = bits(_WIRE_129, 10, 10)
connect _WIRE_128.hx, _T_1762
node _T_1763 = bits(_WIRE_129, 11, 11)
connect _WIRE_128.hw, _T_1763
node _T_1764 = bits(_WIRE_129, 12, 12)
connect _WIRE_128.sr, _T_1764
node _T_1765 = bits(_WIRE_129, 13, 13)
connect _WIRE_128.sx, _T_1765
node _T_1766 = bits(_WIRE_129, 14, 14)
connect _WIRE_128.sw, _T_1766
node _T_1767 = bits(_WIRE_129, 15, 15)
connect _WIRE_128.gf, _T_1767
node _T_1768 = bits(_WIRE_129, 16, 16)
connect _WIRE_128.pf, _T_1768
node _T_1769 = bits(_WIRE_129, 17, 17)
connect _WIRE_128.ae_stage2, _T_1769
node _T_1770 = bits(_WIRE_129, 18, 18)
connect _WIRE_128.ae_final, _T_1770
node _T_1771 = bits(_WIRE_129, 19, 19)
connect _WIRE_128.ae_ptw, _T_1771
node _T_1772 = bits(_WIRE_129, 20, 20)
connect _WIRE_128.g, _T_1772
node _T_1773 = bits(_WIRE_129, 21, 21)
connect _WIRE_128.u, _T_1773
node _T_1774 = bits(_WIRE_129, 41, 22)
connect _WIRE_128.ppn, _T_1774
wire _WIRE_130 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_131 : UInt<42>
connect _WIRE_131, sectored_entries[0][4].data[1]
node _T_1775 = bits(_WIRE_131, 0, 0)
connect _WIRE_130.fragmented_superpage, _T_1775
node _T_1776 = bits(_WIRE_131, 1, 1)
connect _WIRE_130.c, _T_1776
node _T_1777 = bits(_WIRE_131, 2, 2)
connect _WIRE_130.eff, _T_1777
node _T_1778 = bits(_WIRE_131, 3, 3)
connect _WIRE_130.paa, _T_1778
node _T_1779 = bits(_WIRE_131, 4, 4)
connect _WIRE_130.pal, _T_1779
node _T_1780 = bits(_WIRE_131, 5, 5)
connect _WIRE_130.ppp, _T_1780
node _T_1781 = bits(_WIRE_131, 6, 6)
connect _WIRE_130.pr, _T_1781
node _T_1782 = bits(_WIRE_131, 7, 7)
connect _WIRE_130.px, _T_1782
node _T_1783 = bits(_WIRE_131, 8, 8)
connect _WIRE_130.pw, _T_1783
node _T_1784 = bits(_WIRE_131, 9, 9)
connect _WIRE_130.hr, _T_1784
node _T_1785 = bits(_WIRE_131, 10, 10)
connect _WIRE_130.hx, _T_1785
node _T_1786 = bits(_WIRE_131, 11, 11)
connect _WIRE_130.hw, _T_1786
node _T_1787 = bits(_WIRE_131, 12, 12)
connect _WIRE_130.sr, _T_1787
node _T_1788 = bits(_WIRE_131, 13, 13)
connect _WIRE_130.sx, _T_1788
node _T_1789 = bits(_WIRE_131, 14, 14)
connect _WIRE_130.sw, _T_1789
node _T_1790 = bits(_WIRE_131, 15, 15)
connect _WIRE_130.gf, _T_1790
node _T_1791 = bits(_WIRE_131, 16, 16)
connect _WIRE_130.pf, _T_1791
node _T_1792 = bits(_WIRE_131, 17, 17)
connect _WIRE_130.ae_stage2, _T_1792
node _T_1793 = bits(_WIRE_131, 18, 18)
connect _WIRE_130.ae_final, _T_1793
node _T_1794 = bits(_WIRE_131, 19, 19)
connect _WIRE_130.ae_ptw, _T_1794
node _T_1795 = bits(_WIRE_131, 20, 20)
connect _WIRE_130.g, _T_1795
node _T_1796 = bits(_WIRE_131, 21, 21)
connect _WIRE_130.u, _T_1796
node _T_1797 = bits(_WIRE_131, 41, 22)
connect _WIRE_130.ppn, _T_1797
wire _WIRE_132 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_133 : UInt<42>
connect _WIRE_133, sectored_entries[0][4].data[2]
node _T_1798 = bits(_WIRE_133, 0, 0)
connect _WIRE_132.fragmented_superpage, _T_1798
node _T_1799 = bits(_WIRE_133, 1, 1)
connect _WIRE_132.c, _T_1799
node _T_1800 = bits(_WIRE_133, 2, 2)
connect _WIRE_132.eff, _T_1800
node _T_1801 = bits(_WIRE_133, 3, 3)
connect _WIRE_132.paa, _T_1801
node _T_1802 = bits(_WIRE_133, 4, 4)
connect _WIRE_132.pal, _T_1802
node _T_1803 = bits(_WIRE_133, 5, 5)
connect _WIRE_132.ppp, _T_1803
node _T_1804 = bits(_WIRE_133, 6, 6)
connect _WIRE_132.pr, _T_1804
node _T_1805 = bits(_WIRE_133, 7, 7)
connect _WIRE_132.px, _T_1805
node _T_1806 = bits(_WIRE_133, 8, 8)
connect _WIRE_132.pw, _T_1806
node _T_1807 = bits(_WIRE_133, 9, 9)
connect _WIRE_132.hr, _T_1807
node _T_1808 = bits(_WIRE_133, 10, 10)
connect _WIRE_132.hx, _T_1808
node _T_1809 = bits(_WIRE_133, 11, 11)
connect _WIRE_132.hw, _T_1809
node _T_1810 = bits(_WIRE_133, 12, 12)
connect _WIRE_132.sr, _T_1810
node _T_1811 = bits(_WIRE_133, 13, 13)
connect _WIRE_132.sx, _T_1811
node _T_1812 = bits(_WIRE_133, 14, 14)
connect _WIRE_132.sw, _T_1812
node _T_1813 = bits(_WIRE_133, 15, 15)
connect _WIRE_132.gf, _T_1813
node _T_1814 = bits(_WIRE_133, 16, 16)
connect _WIRE_132.pf, _T_1814
node _T_1815 = bits(_WIRE_133, 17, 17)
connect _WIRE_132.ae_stage2, _T_1815
node _T_1816 = bits(_WIRE_133, 18, 18)
connect _WIRE_132.ae_final, _T_1816
node _T_1817 = bits(_WIRE_133, 19, 19)
connect _WIRE_132.ae_ptw, _T_1817
node _T_1818 = bits(_WIRE_133, 20, 20)
connect _WIRE_132.g, _T_1818
node _T_1819 = bits(_WIRE_133, 21, 21)
connect _WIRE_132.u, _T_1819
node _T_1820 = bits(_WIRE_133, 41, 22)
connect _WIRE_132.ppn, _T_1820
wire _WIRE_134 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_135 : UInt<42>
connect _WIRE_135, sectored_entries[0][4].data[3]
node _T_1821 = bits(_WIRE_135, 0, 0)
connect _WIRE_134.fragmented_superpage, _T_1821
node _T_1822 = bits(_WIRE_135, 1, 1)
connect _WIRE_134.c, _T_1822
node _T_1823 = bits(_WIRE_135, 2, 2)
connect _WIRE_134.eff, _T_1823
node _T_1824 = bits(_WIRE_135, 3, 3)
connect _WIRE_134.paa, _T_1824
node _T_1825 = bits(_WIRE_135, 4, 4)
connect _WIRE_134.pal, _T_1825
node _T_1826 = bits(_WIRE_135, 5, 5)
connect _WIRE_134.ppp, _T_1826
node _T_1827 = bits(_WIRE_135, 6, 6)
connect _WIRE_134.pr, _T_1827
node _T_1828 = bits(_WIRE_135, 7, 7)
connect _WIRE_134.px, _T_1828
node _T_1829 = bits(_WIRE_135, 8, 8)
connect _WIRE_134.pw, _T_1829
node _T_1830 = bits(_WIRE_135, 9, 9)
connect _WIRE_134.hr, _T_1830
node _T_1831 = bits(_WIRE_135, 10, 10)
connect _WIRE_134.hx, _T_1831
node _T_1832 = bits(_WIRE_135, 11, 11)
connect _WIRE_134.hw, _T_1832
node _T_1833 = bits(_WIRE_135, 12, 12)
connect _WIRE_134.sr, _T_1833
node _T_1834 = bits(_WIRE_135, 13, 13)
connect _WIRE_134.sx, _T_1834
node _T_1835 = bits(_WIRE_135, 14, 14)
connect _WIRE_134.sw, _T_1835
node _T_1836 = bits(_WIRE_135, 15, 15)
connect _WIRE_134.gf, _T_1836
node _T_1837 = bits(_WIRE_135, 16, 16)
connect _WIRE_134.pf, _T_1837
node _T_1838 = bits(_WIRE_135, 17, 17)
connect _WIRE_134.ae_stage2, _T_1838
node _T_1839 = bits(_WIRE_135, 18, 18)
connect _WIRE_134.ae_final, _T_1839
node _T_1840 = bits(_WIRE_135, 19, 19)
connect _WIRE_134.ae_ptw, _T_1840
node _T_1841 = bits(_WIRE_135, 20, 20)
connect _WIRE_134.g, _T_1841
node _T_1842 = bits(_WIRE_135, 21, 21)
connect _WIRE_134.u, _T_1842
node _T_1843 = bits(_WIRE_135, 41, 22)
connect _WIRE_134.ppn, _T_1843
node _T_1844 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1845 = bits(vpn, 1, 0)
node _T_1846 = eq(UInt<1>(0h0), _T_1845)
node _T_1847 = and(_T_1844, _T_1846)
when _T_1847 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
node _T_1848 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1849 = bits(vpn, 1, 0)
node _T_1850 = eq(UInt<1>(0h1), _T_1849)
node _T_1851 = and(_T_1848, _T_1850)
when _T_1851 :
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
node _T_1852 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1853 = bits(vpn, 1, 0)
node _T_1854 = eq(UInt<2>(0h2), _T_1853)
node _T_1855 = and(_T_1852, _T_1854)
when _T_1855 :
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
node _T_1856 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1857 = bits(vpn, 1, 0)
node _T_1858 = eq(UInt<2>(0h3), _T_1857)
node _T_1859 = and(_T_1856, _T_1858)
when _T_1859 :
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
node _T_1860 = xor(sectored_entries[0][4].tag_vpn, vpn)
node _T_1861 = shr(_T_1860, 18)
node _T_1862 = eq(_T_1861, UInt<1>(0h0))
when _T_1862 :
wire _WIRE_136 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_137 : UInt<42>
connect _WIRE_137, sectored_entries[0][4].data[0]
node _T_1863 = bits(_WIRE_137, 0, 0)
connect _WIRE_136.fragmented_superpage, _T_1863
node _T_1864 = bits(_WIRE_137, 1, 1)
connect _WIRE_136.c, _T_1864
node _T_1865 = bits(_WIRE_137, 2, 2)
connect _WIRE_136.eff, _T_1865
node _T_1866 = bits(_WIRE_137, 3, 3)
connect _WIRE_136.paa, _T_1866
node _T_1867 = bits(_WIRE_137, 4, 4)
connect _WIRE_136.pal, _T_1867
node _T_1868 = bits(_WIRE_137, 5, 5)
connect _WIRE_136.ppp, _T_1868
node _T_1869 = bits(_WIRE_137, 6, 6)
connect _WIRE_136.pr, _T_1869
node _T_1870 = bits(_WIRE_137, 7, 7)
connect _WIRE_136.px, _T_1870
node _T_1871 = bits(_WIRE_137, 8, 8)
connect _WIRE_136.pw, _T_1871
node _T_1872 = bits(_WIRE_137, 9, 9)
connect _WIRE_136.hr, _T_1872
node _T_1873 = bits(_WIRE_137, 10, 10)
connect _WIRE_136.hx, _T_1873
node _T_1874 = bits(_WIRE_137, 11, 11)
connect _WIRE_136.hw, _T_1874
node _T_1875 = bits(_WIRE_137, 12, 12)
connect _WIRE_136.sr, _T_1875
node _T_1876 = bits(_WIRE_137, 13, 13)
connect _WIRE_136.sx, _T_1876
node _T_1877 = bits(_WIRE_137, 14, 14)
connect _WIRE_136.sw, _T_1877
node _T_1878 = bits(_WIRE_137, 15, 15)
connect _WIRE_136.gf, _T_1878
node _T_1879 = bits(_WIRE_137, 16, 16)
connect _WIRE_136.pf, _T_1879
node _T_1880 = bits(_WIRE_137, 17, 17)
connect _WIRE_136.ae_stage2, _T_1880
node _T_1881 = bits(_WIRE_137, 18, 18)
connect _WIRE_136.ae_final, _T_1881
node _T_1882 = bits(_WIRE_137, 19, 19)
connect _WIRE_136.ae_ptw, _T_1882
node _T_1883 = bits(_WIRE_137, 20, 20)
connect _WIRE_136.g, _T_1883
node _T_1884 = bits(_WIRE_137, 21, 21)
connect _WIRE_136.u, _T_1884
node _T_1885 = bits(_WIRE_137, 41, 22)
connect _WIRE_136.ppn, _T_1885
wire _WIRE_138 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_139 : UInt<42>
connect _WIRE_139, sectored_entries[0][4].data[1]
node _T_1886 = bits(_WIRE_139, 0, 0)
connect _WIRE_138.fragmented_superpage, _T_1886
node _T_1887 = bits(_WIRE_139, 1, 1)
connect _WIRE_138.c, _T_1887
node _T_1888 = bits(_WIRE_139, 2, 2)
connect _WIRE_138.eff, _T_1888
node _T_1889 = bits(_WIRE_139, 3, 3)
connect _WIRE_138.paa, _T_1889
node _T_1890 = bits(_WIRE_139, 4, 4)
connect _WIRE_138.pal, _T_1890
node _T_1891 = bits(_WIRE_139, 5, 5)
connect _WIRE_138.ppp, _T_1891
node _T_1892 = bits(_WIRE_139, 6, 6)
connect _WIRE_138.pr, _T_1892
node _T_1893 = bits(_WIRE_139, 7, 7)
connect _WIRE_138.px, _T_1893
node _T_1894 = bits(_WIRE_139, 8, 8)
connect _WIRE_138.pw, _T_1894
node _T_1895 = bits(_WIRE_139, 9, 9)
connect _WIRE_138.hr, _T_1895
node _T_1896 = bits(_WIRE_139, 10, 10)
connect _WIRE_138.hx, _T_1896
node _T_1897 = bits(_WIRE_139, 11, 11)
connect _WIRE_138.hw, _T_1897
node _T_1898 = bits(_WIRE_139, 12, 12)
connect _WIRE_138.sr, _T_1898
node _T_1899 = bits(_WIRE_139, 13, 13)
connect _WIRE_138.sx, _T_1899
node _T_1900 = bits(_WIRE_139, 14, 14)
connect _WIRE_138.sw, _T_1900
node _T_1901 = bits(_WIRE_139, 15, 15)
connect _WIRE_138.gf, _T_1901
node _T_1902 = bits(_WIRE_139, 16, 16)
connect _WIRE_138.pf, _T_1902
node _T_1903 = bits(_WIRE_139, 17, 17)
connect _WIRE_138.ae_stage2, _T_1903
node _T_1904 = bits(_WIRE_139, 18, 18)
connect _WIRE_138.ae_final, _T_1904
node _T_1905 = bits(_WIRE_139, 19, 19)
connect _WIRE_138.ae_ptw, _T_1905
node _T_1906 = bits(_WIRE_139, 20, 20)
connect _WIRE_138.g, _T_1906
node _T_1907 = bits(_WIRE_139, 21, 21)
connect _WIRE_138.u, _T_1907
node _T_1908 = bits(_WIRE_139, 41, 22)
connect _WIRE_138.ppn, _T_1908
wire _WIRE_140 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_141 : UInt<42>
connect _WIRE_141, sectored_entries[0][4].data[2]
node _T_1909 = bits(_WIRE_141, 0, 0)
connect _WIRE_140.fragmented_superpage, _T_1909
node _T_1910 = bits(_WIRE_141, 1, 1)
connect _WIRE_140.c, _T_1910
node _T_1911 = bits(_WIRE_141, 2, 2)
connect _WIRE_140.eff, _T_1911
node _T_1912 = bits(_WIRE_141, 3, 3)
connect _WIRE_140.paa, _T_1912
node _T_1913 = bits(_WIRE_141, 4, 4)
connect _WIRE_140.pal, _T_1913
node _T_1914 = bits(_WIRE_141, 5, 5)
connect _WIRE_140.ppp, _T_1914
node _T_1915 = bits(_WIRE_141, 6, 6)
connect _WIRE_140.pr, _T_1915
node _T_1916 = bits(_WIRE_141, 7, 7)
connect _WIRE_140.px, _T_1916
node _T_1917 = bits(_WIRE_141, 8, 8)
connect _WIRE_140.pw, _T_1917
node _T_1918 = bits(_WIRE_141, 9, 9)
connect _WIRE_140.hr, _T_1918
node _T_1919 = bits(_WIRE_141, 10, 10)
connect _WIRE_140.hx, _T_1919
node _T_1920 = bits(_WIRE_141, 11, 11)
connect _WIRE_140.hw, _T_1920
node _T_1921 = bits(_WIRE_141, 12, 12)
connect _WIRE_140.sr, _T_1921
node _T_1922 = bits(_WIRE_141, 13, 13)
connect _WIRE_140.sx, _T_1922
node _T_1923 = bits(_WIRE_141, 14, 14)
connect _WIRE_140.sw, _T_1923
node _T_1924 = bits(_WIRE_141, 15, 15)
connect _WIRE_140.gf, _T_1924
node _T_1925 = bits(_WIRE_141, 16, 16)
connect _WIRE_140.pf, _T_1925
node _T_1926 = bits(_WIRE_141, 17, 17)
connect _WIRE_140.ae_stage2, _T_1926
node _T_1927 = bits(_WIRE_141, 18, 18)
connect _WIRE_140.ae_final, _T_1927
node _T_1928 = bits(_WIRE_141, 19, 19)
connect _WIRE_140.ae_ptw, _T_1928
node _T_1929 = bits(_WIRE_141, 20, 20)
connect _WIRE_140.g, _T_1929
node _T_1930 = bits(_WIRE_141, 21, 21)
connect _WIRE_140.u, _T_1930
node _T_1931 = bits(_WIRE_141, 41, 22)
connect _WIRE_140.ppn, _T_1931
wire _WIRE_142 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_143 : UInt<42>
connect _WIRE_143, sectored_entries[0][4].data[3]
node _T_1932 = bits(_WIRE_143, 0, 0)
connect _WIRE_142.fragmented_superpage, _T_1932
node _T_1933 = bits(_WIRE_143, 1, 1)
connect _WIRE_142.c, _T_1933
node _T_1934 = bits(_WIRE_143, 2, 2)
connect _WIRE_142.eff, _T_1934
node _T_1935 = bits(_WIRE_143, 3, 3)
connect _WIRE_142.paa, _T_1935
node _T_1936 = bits(_WIRE_143, 4, 4)
connect _WIRE_142.pal, _T_1936
node _T_1937 = bits(_WIRE_143, 5, 5)
connect _WIRE_142.ppp, _T_1937
node _T_1938 = bits(_WIRE_143, 6, 6)
connect _WIRE_142.pr, _T_1938
node _T_1939 = bits(_WIRE_143, 7, 7)
connect _WIRE_142.px, _T_1939
node _T_1940 = bits(_WIRE_143, 8, 8)
connect _WIRE_142.pw, _T_1940
node _T_1941 = bits(_WIRE_143, 9, 9)
connect _WIRE_142.hr, _T_1941
node _T_1942 = bits(_WIRE_143, 10, 10)
connect _WIRE_142.hx, _T_1942
node _T_1943 = bits(_WIRE_143, 11, 11)
connect _WIRE_142.hw, _T_1943
node _T_1944 = bits(_WIRE_143, 12, 12)
connect _WIRE_142.sr, _T_1944
node _T_1945 = bits(_WIRE_143, 13, 13)
connect _WIRE_142.sx, _T_1945
node _T_1946 = bits(_WIRE_143, 14, 14)
connect _WIRE_142.sw, _T_1946
node _T_1947 = bits(_WIRE_143, 15, 15)
connect _WIRE_142.gf, _T_1947
node _T_1948 = bits(_WIRE_143, 16, 16)
connect _WIRE_142.pf, _T_1948
node _T_1949 = bits(_WIRE_143, 17, 17)
connect _WIRE_142.ae_stage2, _T_1949
node _T_1950 = bits(_WIRE_143, 18, 18)
connect _WIRE_142.ae_final, _T_1950
node _T_1951 = bits(_WIRE_143, 19, 19)
connect _WIRE_142.ae_ptw, _T_1951
node _T_1952 = bits(_WIRE_143, 20, 20)
connect _WIRE_142.g, _T_1952
node _T_1953 = bits(_WIRE_143, 21, 21)
connect _WIRE_142.u, _T_1953
node _T_1954 = bits(_WIRE_143, 41, 22)
connect _WIRE_142.ppn, _T_1954
node _T_1955 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1956 = and(_T_1955, _WIRE_136.fragmented_superpage)
when _T_1956 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
node _T_1957 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1958 = and(_T_1957, _WIRE_138.fragmented_superpage)
when _T_1958 :
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
node _T_1959 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1960 = and(_T_1959, _WIRE_140.fragmented_superpage)
when _T_1960 :
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
node _T_1961 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1962 = and(_T_1961, _WIRE_142.fragmented_superpage)
when _T_1962 :
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
else :
node _T_1963 = eq(hg_4, UInt<1>(0h0))
node _T_1964 = and(_T_1963, io.sfence.bits.rs2)
when _T_1964 :
wire _WIRE_144 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_145 : UInt<42>
connect _WIRE_145, sectored_entries[0][4].data[0]
node _T_1965 = bits(_WIRE_145, 0, 0)
connect _WIRE_144.fragmented_superpage, _T_1965
node _T_1966 = bits(_WIRE_145, 1, 1)
connect _WIRE_144.c, _T_1966
node _T_1967 = bits(_WIRE_145, 2, 2)
connect _WIRE_144.eff, _T_1967
node _T_1968 = bits(_WIRE_145, 3, 3)
connect _WIRE_144.paa, _T_1968
node _T_1969 = bits(_WIRE_145, 4, 4)
connect _WIRE_144.pal, _T_1969
node _T_1970 = bits(_WIRE_145, 5, 5)
connect _WIRE_144.ppp, _T_1970
node _T_1971 = bits(_WIRE_145, 6, 6)
connect _WIRE_144.pr, _T_1971
node _T_1972 = bits(_WIRE_145, 7, 7)
connect _WIRE_144.px, _T_1972
node _T_1973 = bits(_WIRE_145, 8, 8)
connect _WIRE_144.pw, _T_1973
node _T_1974 = bits(_WIRE_145, 9, 9)
connect _WIRE_144.hr, _T_1974
node _T_1975 = bits(_WIRE_145, 10, 10)
connect _WIRE_144.hx, _T_1975
node _T_1976 = bits(_WIRE_145, 11, 11)
connect _WIRE_144.hw, _T_1976
node _T_1977 = bits(_WIRE_145, 12, 12)
connect _WIRE_144.sr, _T_1977
node _T_1978 = bits(_WIRE_145, 13, 13)
connect _WIRE_144.sx, _T_1978
node _T_1979 = bits(_WIRE_145, 14, 14)
connect _WIRE_144.sw, _T_1979
node _T_1980 = bits(_WIRE_145, 15, 15)
connect _WIRE_144.gf, _T_1980
node _T_1981 = bits(_WIRE_145, 16, 16)
connect _WIRE_144.pf, _T_1981
node _T_1982 = bits(_WIRE_145, 17, 17)
connect _WIRE_144.ae_stage2, _T_1982
node _T_1983 = bits(_WIRE_145, 18, 18)
connect _WIRE_144.ae_final, _T_1983
node _T_1984 = bits(_WIRE_145, 19, 19)
connect _WIRE_144.ae_ptw, _T_1984
node _T_1985 = bits(_WIRE_145, 20, 20)
connect _WIRE_144.g, _T_1985
node _T_1986 = bits(_WIRE_145, 21, 21)
connect _WIRE_144.u, _T_1986
node _T_1987 = bits(_WIRE_145, 41, 22)
connect _WIRE_144.ppn, _T_1987
wire _WIRE_146 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_147 : UInt<42>
connect _WIRE_147, sectored_entries[0][4].data[1]
node _T_1988 = bits(_WIRE_147, 0, 0)
connect _WIRE_146.fragmented_superpage, _T_1988
node _T_1989 = bits(_WIRE_147, 1, 1)
connect _WIRE_146.c, _T_1989
node _T_1990 = bits(_WIRE_147, 2, 2)
connect _WIRE_146.eff, _T_1990
node _T_1991 = bits(_WIRE_147, 3, 3)
connect _WIRE_146.paa, _T_1991
node _T_1992 = bits(_WIRE_147, 4, 4)
connect _WIRE_146.pal, _T_1992
node _T_1993 = bits(_WIRE_147, 5, 5)
connect _WIRE_146.ppp, _T_1993
node _T_1994 = bits(_WIRE_147, 6, 6)
connect _WIRE_146.pr, _T_1994
node _T_1995 = bits(_WIRE_147, 7, 7)
connect _WIRE_146.px, _T_1995
node _T_1996 = bits(_WIRE_147, 8, 8)
connect _WIRE_146.pw, _T_1996
node _T_1997 = bits(_WIRE_147, 9, 9)
connect _WIRE_146.hr, _T_1997
node _T_1998 = bits(_WIRE_147, 10, 10)
connect _WIRE_146.hx, _T_1998
node _T_1999 = bits(_WIRE_147, 11, 11)
connect _WIRE_146.hw, _T_1999
node _T_2000 = bits(_WIRE_147, 12, 12)
connect _WIRE_146.sr, _T_2000
node _T_2001 = bits(_WIRE_147, 13, 13)
connect _WIRE_146.sx, _T_2001
node _T_2002 = bits(_WIRE_147, 14, 14)
connect _WIRE_146.sw, _T_2002
node _T_2003 = bits(_WIRE_147, 15, 15)
connect _WIRE_146.gf, _T_2003
node _T_2004 = bits(_WIRE_147, 16, 16)
connect _WIRE_146.pf, _T_2004
node _T_2005 = bits(_WIRE_147, 17, 17)
connect _WIRE_146.ae_stage2, _T_2005
node _T_2006 = bits(_WIRE_147, 18, 18)
connect _WIRE_146.ae_final, _T_2006
node _T_2007 = bits(_WIRE_147, 19, 19)
connect _WIRE_146.ae_ptw, _T_2007
node _T_2008 = bits(_WIRE_147, 20, 20)
connect _WIRE_146.g, _T_2008
node _T_2009 = bits(_WIRE_147, 21, 21)
connect _WIRE_146.u, _T_2009
node _T_2010 = bits(_WIRE_147, 41, 22)
connect _WIRE_146.ppn, _T_2010
wire _WIRE_148 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_149 : UInt<42>
connect _WIRE_149, sectored_entries[0][4].data[2]
node _T_2011 = bits(_WIRE_149, 0, 0)
connect _WIRE_148.fragmented_superpage, _T_2011
node _T_2012 = bits(_WIRE_149, 1, 1)
connect _WIRE_148.c, _T_2012
node _T_2013 = bits(_WIRE_149, 2, 2)
connect _WIRE_148.eff, _T_2013
node _T_2014 = bits(_WIRE_149, 3, 3)
connect _WIRE_148.paa, _T_2014
node _T_2015 = bits(_WIRE_149, 4, 4)
connect _WIRE_148.pal, _T_2015
node _T_2016 = bits(_WIRE_149, 5, 5)
connect _WIRE_148.ppp, _T_2016
node _T_2017 = bits(_WIRE_149, 6, 6)
connect _WIRE_148.pr, _T_2017
node _T_2018 = bits(_WIRE_149, 7, 7)
connect _WIRE_148.px, _T_2018
node _T_2019 = bits(_WIRE_149, 8, 8)
connect _WIRE_148.pw, _T_2019
node _T_2020 = bits(_WIRE_149, 9, 9)
connect _WIRE_148.hr, _T_2020
node _T_2021 = bits(_WIRE_149, 10, 10)
connect _WIRE_148.hx, _T_2021
node _T_2022 = bits(_WIRE_149, 11, 11)
connect _WIRE_148.hw, _T_2022
node _T_2023 = bits(_WIRE_149, 12, 12)
connect _WIRE_148.sr, _T_2023
node _T_2024 = bits(_WIRE_149, 13, 13)
connect _WIRE_148.sx, _T_2024
node _T_2025 = bits(_WIRE_149, 14, 14)
connect _WIRE_148.sw, _T_2025
node _T_2026 = bits(_WIRE_149, 15, 15)
connect _WIRE_148.gf, _T_2026
node _T_2027 = bits(_WIRE_149, 16, 16)
connect _WIRE_148.pf, _T_2027
node _T_2028 = bits(_WIRE_149, 17, 17)
connect _WIRE_148.ae_stage2, _T_2028
node _T_2029 = bits(_WIRE_149, 18, 18)
connect _WIRE_148.ae_final, _T_2029
node _T_2030 = bits(_WIRE_149, 19, 19)
connect _WIRE_148.ae_ptw, _T_2030
node _T_2031 = bits(_WIRE_149, 20, 20)
connect _WIRE_148.g, _T_2031
node _T_2032 = bits(_WIRE_149, 21, 21)
connect _WIRE_148.u, _T_2032
node _T_2033 = bits(_WIRE_149, 41, 22)
connect _WIRE_148.ppn, _T_2033
wire _WIRE_150 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_151 : UInt<42>
connect _WIRE_151, sectored_entries[0][4].data[3]
node _T_2034 = bits(_WIRE_151, 0, 0)
connect _WIRE_150.fragmented_superpage, _T_2034
node _T_2035 = bits(_WIRE_151, 1, 1)
connect _WIRE_150.c, _T_2035
node _T_2036 = bits(_WIRE_151, 2, 2)
connect _WIRE_150.eff, _T_2036
node _T_2037 = bits(_WIRE_151, 3, 3)
connect _WIRE_150.paa, _T_2037
node _T_2038 = bits(_WIRE_151, 4, 4)
connect _WIRE_150.pal, _T_2038
node _T_2039 = bits(_WIRE_151, 5, 5)
connect _WIRE_150.ppp, _T_2039
node _T_2040 = bits(_WIRE_151, 6, 6)
connect _WIRE_150.pr, _T_2040
node _T_2041 = bits(_WIRE_151, 7, 7)
connect _WIRE_150.px, _T_2041
node _T_2042 = bits(_WIRE_151, 8, 8)
connect _WIRE_150.pw, _T_2042
node _T_2043 = bits(_WIRE_151, 9, 9)
connect _WIRE_150.hr, _T_2043
node _T_2044 = bits(_WIRE_151, 10, 10)
connect _WIRE_150.hx, _T_2044
node _T_2045 = bits(_WIRE_151, 11, 11)
connect _WIRE_150.hw, _T_2045
node _T_2046 = bits(_WIRE_151, 12, 12)
connect _WIRE_150.sr, _T_2046
node _T_2047 = bits(_WIRE_151, 13, 13)
connect _WIRE_150.sx, _T_2047
node _T_2048 = bits(_WIRE_151, 14, 14)
connect _WIRE_150.sw, _T_2048
node _T_2049 = bits(_WIRE_151, 15, 15)
connect _WIRE_150.gf, _T_2049
node _T_2050 = bits(_WIRE_151, 16, 16)
connect _WIRE_150.pf, _T_2050
node _T_2051 = bits(_WIRE_151, 17, 17)
connect _WIRE_150.ae_stage2, _T_2051
node _T_2052 = bits(_WIRE_151, 18, 18)
connect _WIRE_150.ae_final, _T_2052
node _T_2053 = bits(_WIRE_151, 19, 19)
connect _WIRE_150.ae_ptw, _T_2053
node _T_2054 = bits(_WIRE_151, 20, 20)
connect _WIRE_150.g, _T_2054
node _T_2055 = bits(_WIRE_151, 21, 21)
connect _WIRE_150.u, _T_2055
node _T_2056 = bits(_WIRE_151, 41, 22)
connect _WIRE_150.ppn, _T_2056
node _T_2057 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_2058 = eq(_WIRE_144.g, UInt<1>(0h0))
node _T_2059 = and(_T_2057, _T_2058)
when _T_2059 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
node _T_2060 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_2061 = eq(_WIRE_146.g, UInt<1>(0h0))
node _T_2062 = and(_T_2060, _T_2061)
when _T_2062 :
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
node _T_2063 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_2064 = eq(_WIRE_148.g, UInt<1>(0h0))
node _T_2065 = and(_T_2063, _T_2064)
when _T_2065 :
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
node _T_2066 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_2067 = eq(_WIRE_150.g, UInt<1>(0h0))
node _T_2068 = and(_T_2066, _T_2067)
when _T_2068 :
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
else :
node _T_2069 = or(hv_4, hg_4)
wire _WIRE_152 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_153 : UInt<42>
connect _WIRE_153, sectored_entries[0][4].data[0]
node _T_2070 = bits(_WIRE_153, 0, 0)
connect _WIRE_152.fragmented_superpage, _T_2070
node _T_2071 = bits(_WIRE_153, 1, 1)
connect _WIRE_152.c, _T_2071
node _T_2072 = bits(_WIRE_153, 2, 2)
connect _WIRE_152.eff, _T_2072
node _T_2073 = bits(_WIRE_153, 3, 3)
connect _WIRE_152.paa, _T_2073
node _T_2074 = bits(_WIRE_153, 4, 4)
connect _WIRE_152.pal, _T_2074
node _T_2075 = bits(_WIRE_153, 5, 5)
connect _WIRE_152.ppp, _T_2075
node _T_2076 = bits(_WIRE_153, 6, 6)
connect _WIRE_152.pr, _T_2076
node _T_2077 = bits(_WIRE_153, 7, 7)
connect _WIRE_152.px, _T_2077
node _T_2078 = bits(_WIRE_153, 8, 8)
connect _WIRE_152.pw, _T_2078
node _T_2079 = bits(_WIRE_153, 9, 9)
connect _WIRE_152.hr, _T_2079
node _T_2080 = bits(_WIRE_153, 10, 10)
connect _WIRE_152.hx, _T_2080
node _T_2081 = bits(_WIRE_153, 11, 11)
connect _WIRE_152.hw, _T_2081
node _T_2082 = bits(_WIRE_153, 12, 12)
connect _WIRE_152.sr, _T_2082
node _T_2083 = bits(_WIRE_153, 13, 13)
connect _WIRE_152.sx, _T_2083
node _T_2084 = bits(_WIRE_153, 14, 14)
connect _WIRE_152.sw, _T_2084
node _T_2085 = bits(_WIRE_153, 15, 15)
connect _WIRE_152.gf, _T_2085
node _T_2086 = bits(_WIRE_153, 16, 16)
connect _WIRE_152.pf, _T_2086
node _T_2087 = bits(_WIRE_153, 17, 17)
connect _WIRE_152.ae_stage2, _T_2087
node _T_2088 = bits(_WIRE_153, 18, 18)
connect _WIRE_152.ae_final, _T_2088
node _T_2089 = bits(_WIRE_153, 19, 19)
connect _WIRE_152.ae_ptw, _T_2089
node _T_2090 = bits(_WIRE_153, 20, 20)
connect _WIRE_152.g, _T_2090
node _T_2091 = bits(_WIRE_153, 21, 21)
connect _WIRE_152.u, _T_2091
node _T_2092 = bits(_WIRE_153, 41, 22)
connect _WIRE_152.ppn, _T_2092
wire _WIRE_154 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_155 : UInt<42>
connect _WIRE_155, sectored_entries[0][4].data[1]
node _T_2093 = bits(_WIRE_155, 0, 0)
connect _WIRE_154.fragmented_superpage, _T_2093
node _T_2094 = bits(_WIRE_155, 1, 1)
connect _WIRE_154.c, _T_2094
node _T_2095 = bits(_WIRE_155, 2, 2)
connect _WIRE_154.eff, _T_2095
node _T_2096 = bits(_WIRE_155, 3, 3)
connect _WIRE_154.paa, _T_2096
node _T_2097 = bits(_WIRE_155, 4, 4)
connect _WIRE_154.pal, _T_2097
node _T_2098 = bits(_WIRE_155, 5, 5)
connect _WIRE_154.ppp, _T_2098
node _T_2099 = bits(_WIRE_155, 6, 6)
connect _WIRE_154.pr, _T_2099
node _T_2100 = bits(_WIRE_155, 7, 7)
connect _WIRE_154.px, _T_2100
node _T_2101 = bits(_WIRE_155, 8, 8)
connect _WIRE_154.pw, _T_2101
node _T_2102 = bits(_WIRE_155, 9, 9)
connect _WIRE_154.hr, _T_2102
node _T_2103 = bits(_WIRE_155, 10, 10)
connect _WIRE_154.hx, _T_2103
node _T_2104 = bits(_WIRE_155, 11, 11)
connect _WIRE_154.hw, _T_2104
node _T_2105 = bits(_WIRE_155, 12, 12)
connect _WIRE_154.sr, _T_2105
node _T_2106 = bits(_WIRE_155, 13, 13)
connect _WIRE_154.sx, _T_2106
node _T_2107 = bits(_WIRE_155, 14, 14)
connect _WIRE_154.sw, _T_2107
node _T_2108 = bits(_WIRE_155, 15, 15)
connect _WIRE_154.gf, _T_2108
node _T_2109 = bits(_WIRE_155, 16, 16)
connect _WIRE_154.pf, _T_2109
node _T_2110 = bits(_WIRE_155, 17, 17)
connect _WIRE_154.ae_stage2, _T_2110
node _T_2111 = bits(_WIRE_155, 18, 18)
connect _WIRE_154.ae_final, _T_2111
node _T_2112 = bits(_WIRE_155, 19, 19)
connect _WIRE_154.ae_ptw, _T_2112
node _T_2113 = bits(_WIRE_155, 20, 20)
connect _WIRE_154.g, _T_2113
node _T_2114 = bits(_WIRE_155, 21, 21)
connect _WIRE_154.u, _T_2114
node _T_2115 = bits(_WIRE_155, 41, 22)
connect _WIRE_154.ppn, _T_2115
wire _WIRE_156 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_157 : UInt<42>
connect _WIRE_157, sectored_entries[0][4].data[2]
node _T_2116 = bits(_WIRE_157, 0, 0)
connect _WIRE_156.fragmented_superpage, _T_2116
node _T_2117 = bits(_WIRE_157, 1, 1)
connect _WIRE_156.c, _T_2117
node _T_2118 = bits(_WIRE_157, 2, 2)
connect _WIRE_156.eff, _T_2118
node _T_2119 = bits(_WIRE_157, 3, 3)
connect _WIRE_156.paa, _T_2119
node _T_2120 = bits(_WIRE_157, 4, 4)
connect _WIRE_156.pal, _T_2120
node _T_2121 = bits(_WIRE_157, 5, 5)
connect _WIRE_156.ppp, _T_2121
node _T_2122 = bits(_WIRE_157, 6, 6)
connect _WIRE_156.pr, _T_2122
node _T_2123 = bits(_WIRE_157, 7, 7)
connect _WIRE_156.px, _T_2123
node _T_2124 = bits(_WIRE_157, 8, 8)
connect _WIRE_156.pw, _T_2124
node _T_2125 = bits(_WIRE_157, 9, 9)
connect _WIRE_156.hr, _T_2125
node _T_2126 = bits(_WIRE_157, 10, 10)
connect _WIRE_156.hx, _T_2126
node _T_2127 = bits(_WIRE_157, 11, 11)
connect _WIRE_156.hw, _T_2127
node _T_2128 = bits(_WIRE_157, 12, 12)
connect _WIRE_156.sr, _T_2128
node _T_2129 = bits(_WIRE_157, 13, 13)
connect _WIRE_156.sx, _T_2129
node _T_2130 = bits(_WIRE_157, 14, 14)
connect _WIRE_156.sw, _T_2130
node _T_2131 = bits(_WIRE_157, 15, 15)
connect _WIRE_156.gf, _T_2131
node _T_2132 = bits(_WIRE_157, 16, 16)
connect _WIRE_156.pf, _T_2132
node _T_2133 = bits(_WIRE_157, 17, 17)
connect _WIRE_156.ae_stage2, _T_2133
node _T_2134 = bits(_WIRE_157, 18, 18)
connect _WIRE_156.ae_final, _T_2134
node _T_2135 = bits(_WIRE_157, 19, 19)
connect _WIRE_156.ae_ptw, _T_2135
node _T_2136 = bits(_WIRE_157, 20, 20)
connect _WIRE_156.g, _T_2136
node _T_2137 = bits(_WIRE_157, 21, 21)
connect _WIRE_156.u, _T_2137
node _T_2138 = bits(_WIRE_157, 41, 22)
connect _WIRE_156.ppn, _T_2138
wire _WIRE_158 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_159 : UInt<42>
connect _WIRE_159, sectored_entries[0][4].data[3]
node _T_2139 = bits(_WIRE_159, 0, 0)
connect _WIRE_158.fragmented_superpage, _T_2139
node _T_2140 = bits(_WIRE_159, 1, 1)
connect _WIRE_158.c, _T_2140
node _T_2141 = bits(_WIRE_159, 2, 2)
connect _WIRE_158.eff, _T_2141
node _T_2142 = bits(_WIRE_159, 3, 3)
connect _WIRE_158.paa, _T_2142
node _T_2143 = bits(_WIRE_159, 4, 4)
connect _WIRE_158.pal, _T_2143
node _T_2144 = bits(_WIRE_159, 5, 5)
connect _WIRE_158.ppp, _T_2144
node _T_2145 = bits(_WIRE_159, 6, 6)
connect _WIRE_158.pr, _T_2145
node _T_2146 = bits(_WIRE_159, 7, 7)
connect _WIRE_158.px, _T_2146
node _T_2147 = bits(_WIRE_159, 8, 8)
connect _WIRE_158.pw, _T_2147
node _T_2148 = bits(_WIRE_159, 9, 9)
connect _WIRE_158.hr, _T_2148
node _T_2149 = bits(_WIRE_159, 10, 10)
connect _WIRE_158.hx, _T_2149
node _T_2150 = bits(_WIRE_159, 11, 11)
connect _WIRE_158.hw, _T_2150
node _T_2151 = bits(_WIRE_159, 12, 12)
connect _WIRE_158.sr, _T_2151
node _T_2152 = bits(_WIRE_159, 13, 13)
connect _WIRE_158.sx, _T_2152
node _T_2153 = bits(_WIRE_159, 14, 14)
connect _WIRE_158.sw, _T_2153
node _T_2154 = bits(_WIRE_159, 15, 15)
connect _WIRE_158.gf, _T_2154
node _T_2155 = bits(_WIRE_159, 16, 16)
connect _WIRE_158.pf, _T_2155
node _T_2156 = bits(_WIRE_159, 17, 17)
connect _WIRE_158.ae_stage2, _T_2156
node _T_2157 = bits(_WIRE_159, 18, 18)
connect _WIRE_158.ae_final, _T_2157
node _T_2158 = bits(_WIRE_159, 19, 19)
connect _WIRE_158.ae_ptw, _T_2158
node _T_2159 = bits(_WIRE_159, 20, 20)
connect _WIRE_158.g, _T_2159
node _T_2160 = bits(_WIRE_159, 21, 21)
connect _WIRE_158.u, _T_2160
node _T_2161 = bits(_WIRE_159, 41, 22)
connect _WIRE_158.ppn, _T_2161
node _T_2162 = eq(sectored_entries[0][4].tag_v, _T_2069)
when _T_2162 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
node _T_2163 = eq(sectored_entries[0][4].tag_v, _T_2069)
when _T_2163 :
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
node _T_2164 = eq(sectored_entries[0][4].tag_v, _T_2069)
when _T_2164 :
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
node _T_2165 = eq(sectored_entries[0][4].tag_v, _T_2069)
when _T_2165 :
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
node hv_5 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_5 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_2166 = eq(hg_5, UInt<1>(0h0))
node _T_2167 = and(_T_2166, io.sfence.bits.rs1)
when _T_2167 :
node _T_2168 = xor(sectored_entries[0][5].tag_vpn, vpn)
node _T_2169 = shr(_T_2168, 2)
node _T_2170 = eq(_T_2169, UInt<1>(0h0))
node _T_2171 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2172 = and(_T_2170, _T_2171)
when _T_2172 :
wire _WIRE_160 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_161 : UInt<42>
connect _WIRE_161, sectored_entries[0][5].data[0]
node _T_2173 = bits(_WIRE_161, 0, 0)
connect _WIRE_160.fragmented_superpage, _T_2173
node _T_2174 = bits(_WIRE_161, 1, 1)
connect _WIRE_160.c, _T_2174
node _T_2175 = bits(_WIRE_161, 2, 2)
connect _WIRE_160.eff, _T_2175
node _T_2176 = bits(_WIRE_161, 3, 3)
connect _WIRE_160.paa, _T_2176
node _T_2177 = bits(_WIRE_161, 4, 4)
connect _WIRE_160.pal, _T_2177
node _T_2178 = bits(_WIRE_161, 5, 5)
connect _WIRE_160.ppp, _T_2178
node _T_2179 = bits(_WIRE_161, 6, 6)
connect _WIRE_160.pr, _T_2179
node _T_2180 = bits(_WIRE_161, 7, 7)
connect _WIRE_160.px, _T_2180
node _T_2181 = bits(_WIRE_161, 8, 8)
connect _WIRE_160.pw, _T_2181
node _T_2182 = bits(_WIRE_161, 9, 9)
connect _WIRE_160.hr, _T_2182
node _T_2183 = bits(_WIRE_161, 10, 10)
connect _WIRE_160.hx, _T_2183
node _T_2184 = bits(_WIRE_161, 11, 11)
connect _WIRE_160.hw, _T_2184
node _T_2185 = bits(_WIRE_161, 12, 12)
connect _WIRE_160.sr, _T_2185
node _T_2186 = bits(_WIRE_161, 13, 13)
connect _WIRE_160.sx, _T_2186
node _T_2187 = bits(_WIRE_161, 14, 14)
connect _WIRE_160.sw, _T_2187
node _T_2188 = bits(_WIRE_161, 15, 15)
connect _WIRE_160.gf, _T_2188
node _T_2189 = bits(_WIRE_161, 16, 16)
connect _WIRE_160.pf, _T_2189
node _T_2190 = bits(_WIRE_161, 17, 17)
connect _WIRE_160.ae_stage2, _T_2190
node _T_2191 = bits(_WIRE_161, 18, 18)
connect _WIRE_160.ae_final, _T_2191
node _T_2192 = bits(_WIRE_161, 19, 19)
connect _WIRE_160.ae_ptw, _T_2192
node _T_2193 = bits(_WIRE_161, 20, 20)
connect _WIRE_160.g, _T_2193
node _T_2194 = bits(_WIRE_161, 21, 21)
connect _WIRE_160.u, _T_2194
node _T_2195 = bits(_WIRE_161, 41, 22)
connect _WIRE_160.ppn, _T_2195
wire _WIRE_162 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_163 : UInt<42>
connect _WIRE_163, sectored_entries[0][5].data[1]
node _T_2196 = bits(_WIRE_163, 0, 0)
connect _WIRE_162.fragmented_superpage, _T_2196
node _T_2197 = bits(_WIRE_163, 1, 1)
connect _WIRE_162.c, _T_2197
node _T_2198 = bits(_WIRE_163, 2, 2)
connect _WIRE_162.eff, _T_2198
node _T_2199 = bits(_WIRE_163, 3, 3)
connect _WIRE_162.paa, _T_2199
node _T_2200 = bits(_WIRE_163, 4, 4)
connect _WIRE_162.pal, _T_2200
node _T_2201 = bits(_WIRE_163, 5, 5)
connect _WIRE_162.ppp, _T_2201
node _T_2202 = bits(_WIRE_163, 6, 6)
connect _WIRE_162.pr, _T_2202
node _T_2203 = bits(_WIRE_163, 7, 7)
connect _WIRE_162.px, _T_2203
node _T_2204 = bits(_WIRE_163, 8, 8)
connect _WIRE_162.pw, _T_2204
node _T_2205 = bits(_WIRE_163, 9, 9)
connect _WIRE_162.hr, _T_2205
node _T_2206 = bits(_WIRE_163, 10, 10)
connect _WIRE_162.hx, _T_2206
node _T_2207 = bits(_WIRE_163, 11, 11)
connect _WIRE_162.hw, _T_2207
node _T_2208 = bits(_WIRE_163, 12, 12)
connect _WIRE_162.sr, _T_2208
node _T_2209 = bits(_WIRE_163, 13, 13)
connect _WIRE_162.sx, _T_2209
node _T_2210 = bits(_WIRE_163, 14, 14)
connect _WIRE_162.sw, _T_2210
node _T_2211 = bits(_WIRE_163, 15, 15)
connect _WIRE_162.gf, _T_2211
node _T_2212 = bits(_WIRE_163, 16, 16)
connect _WIRE_162.pf, _T_2212
node _T_2213 = bits(_WIRE_163, 17, 17)
connect _WIRE_162.ae_stage2, _T_2213
node _T_2214 = bits(_WIRE_163, 18, 18)
connect _WIRE_162.ae_final, _T_2214
node _T_2215 = bits(_WIRE_163, 19, 19)
connect _WIRE_162.ae_ptw, _T_2215
node _T_2216 = bits(_WIRE_163, 20, 20)
connect _WIRE_162.g, _T_2216
node _T_2217 = bits(_WIRE_163, 21, 21)
connect _WIRE_162.u, _T_2217
node _T_2218 = bits(_WIRE_163, 41, 22)
connect _WIRE_162.ppn, _T_2218
wire _WIRE_164 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_165 : UInt<42>
connect _WIRE_165, sectored_entries[0][5].data[2]
node _T_2219 = bits(_WIRE_165, 0, 0)
connect _WIRE_164.fragmented_superpage, _T_2219
node _T_2220 = bits(_WIRE_165, 1, 1)
connect _WIRE_164.c, _T_2220
node _T_2221 = bits(_WIRE_165, 2, 2)
connect _WIRE_164.eff, _T_2221
node _T_2222 = bits(_WIRE_165, 3, 3)
connect _WIRE_164.paa, _T_2222
node _T_2223 = bits(_WIRE_165, 4, 4)
connect _WIRE_164.pal, _T_2223
node _T_2224 = bits(_WIRE_165, 5, 5)
connect _WIRE_164.ppp, _T_2224
node _T_2225 = bits(_WIRE_165, 6, 6)
connect _WIRE_164.pr, _T_2225
node _T_2226 = bits(_WIRE_165, 7, 7)
connect _WIRE_164.px, _T_2226
node _T_2227 = bits(_WIRE_165, 8, 8)
connect _WIRE_164.pw, _T_2227
node _T_2228 = bits(_WIRE_165, 9, 9)
connect _WIRE_164.hr, _T_2228
node _T_2229 = bits(_WIRE_165, 10, 10)
connect _WIRE_164.hx, _T_2229
node _T_2230 = bits(_WIRE_165, 11, 11)
connect _WIRE_164.hw, _T_2230
node _T_2231 = bits(_WIRE_165, 12, 12)
connect _WIRE_164.sr, _T_2231
node _T_2232 = bits(_WIRE_165, 13, 13)
connect _WIRE_164.sx, _T_2232
node _T_2233 = bits(_WIRE_165, 14, 14)
connect _WIRE_164.sw, _T_2233
node _T_2234 = bits(_WIRE_165, 15, 15)
connect _WIRE_164.gf, _T_2234
node _T_2235 = bits(_WIRE_165, 16, 16)
connect _WIRE_164.pf, _T_2235
node _T_2236 = bits(_WIRE_165, 17, 17)
connect _WIRE_164.ae_stage2, _T_2236
node _T_2237 = bits(_WIRE_165, 18, 18)
connect _WIRE_164.ae_final, _T_2237
node _T_2238 = bits(_WIRE_165, 19, 19)
connect _WIRE_164.ae_ptw, _T_2238
node _T_2239 = bits(_WIRE_165, 20, 20)
connect _WIRE_164.g, _T_2239
node _T_2240 = bits(_WIRE_165, 21, 21)
connect _WIRE_164.u, _T_2240
node _T_2241 = bits(_WIRE_165, 41, 22)
connect _WIRE_164.ppn, _T_2241
wire _WIRE_166 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_167 : UInt<42>
connect _WIRE_167, sectored_entries[0][5].data[3]
node _T_2242 = bits(_WIRE_167, 0, 0)
connect _WIRE_166.fragmented_superpage, _T_2242
node _T_2243 = bits(_WIRE_167, 1, 1)
connect _WIRE_166.c, _T_2243
node _T_2244 = bits(_WIRE_167, 2, 2)
connect _WIRE_166.eff, _T_2244
node _T_2245 = bits(_WIRE_167, 3, 3)
connect _WIRE_166.paa, _T_2245
node _T_2246 = bits(_WIRE_167, 4, 4)
connect _WIRE_166.pal, _T_2246
node _T_2247 = bits(_WIRE_167, 5, 5)
connect _WIRE_166.ppp, _T_2247
node _T_2248 = bits(_WIRE_167, 6, 6)
connect _WIRE_166.pr, _T_2248
node _T_2249 = bits(_WIRE_167, 7, 7)
connect _WIRE_166.px, _T_2249
node _T_2250 = bits(_WIRE_167, 8, 8)
connect _WIRE_166.pw, _T_2250
node _T_2251 = bits(_WIRE_167, 9, 9)
connect _WIRE_166.hr, _T_2251
node _T_2252 = bits(_WIRE_167, 10, 10)
connect _WIRE_166.hx, _T_2252
node _T_2253 = bits(_WIRE_167, 11, 11)
connect _WIRE_166.hw, _T_2253
node _T_2254 = bits(_WIRE_167, 12, 12)
connect _WIRE_166.sr, _T_2254
node _T_2255 = bits(_WIRE_167, 13, 13)
connect _WIRE_166.sx, _T_2255
node _T_2256 = bits(_WIRE_167, 14, 14)
connect _WIRE_166.sw, _T_2256
node _T_2257 = bits(_WIRE_167, 15, 15)
connect _WIRE_166.gf, _T_2257
node _T_2258 = bits(_WIRE_167, 16, 16)
connect _WIRE_166.pf, _T_2258
node _T_2259 = bits(_WIRE_167, 17, 17)
connect _WIRE_166.ae_stage2, _T_2259
node _T_2260 = bits(_WIRE_167, 18, 18)
connect _WIRE_166.ae_final, _T_2260
node _T_2261 = bits(_WIRE_167, 19, 19)
connect _WIRE_166.ae_ptw, _T_2261
node _T_2262 = bits(_WIRE_167, 20, 20)
connect _WIRE_166.g, _T_2262
node _T_2263 = bits(_WIRE_167, 21, 21)
connect _WIRE_166.u, _T_2263
node _T_2264 = bits(_WIRE_167, 41, 22)
connect _WIRE_166.ppn, _T_2264
node _T_2265 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2266 = bits(vpn, 1, 0)
node _T_2267 = eq(UInt<1>(0h0), _T_2266)
node _T_2268 = and(_T_2265, _T_2267)
when _T_2268 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
node _T_2269 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2270 = bits(vpn, 1, 0)
node _T_2271 = eq(UInt<1>(0h1), _T_2270)
node _T_2272 = and(_T_2269, _T_2271)
when _T_2272 :
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
node _T_2273 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2274 = bits(vpn, 1, 0)
node _T_2275 = eq(UInt<2>(0h2), _T_2274)
node _T_2276 = and(_T_2273, _T_2275)
when _T_2276 :
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
node _T_2277 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2278 = bits(vpn, 1, 0)
node _T_2279 = eq(UInt<2>(0h3), _T_2278)
node _T_2280 = and(_T_2277, _T_2279)
when _T_2280 :
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
node _T_2281 = xor(sectored_entries[0][5].tag_vpn, vpn)
node _T_2282 = shr(_T_2281, 18)
node _T_2283 = eq(_T_2282, UInt<1>(0h0))
when _T_2283 :
wire _WIRE_168 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_169 : UInt<42>
connect _WIRE_169, sectored_entries[0][5].data[0]
node _T_2284 = bits(_WIRE_169, 0, 0)
connect _WIRE_168.fragmented_superpage, _T_2284
node _T_2285 = bits(_WIRE_169, 1, 1)
connect _WIRE_168.c, _T_2285
node _T_2286 = bits(_WIRE_169, 2, 2)
connect _WIRE_168.eff, _T_2286
node _T_2287 = bits(_WIRE_169, 3, 3)
connect _WIRE_168.paa, _T_2287
node _T_2288 = bits(_WIRE_169, 4, 4)
connect _WIRE_168.pal, _T_2288
node _T_2289 = bits(_WIRE_169, 5, 5)
connect _WIRE_168.ppp, _T_2289
node _T_2290 = bits(_WIRE_169, 6, 6)
connect _WIRE_168.pr, _T_2290
node _T_2291 = bits(_WIRE_169, 7, 7)
connect _WIRE_168.px, _T_2291
node _T_2292 = bits(_WIRE_169, 8, 8)
connect _WIRE_168.pw, _T_2292
node _T_2293 = bits(_WIRE_169, 9, 9)
connect _WIRE_168.hr, _T_2293
node _T_2294 = bits(_WIRE_169, 10, 10)
connect _WIRE_168.hx, _T_2294
node _T_2295 = bits(_WIRE_169, 11, 11)
connect _WIRE_168.hw, _T_2295
node _T_2296 = bits(_WIRE_169, 12, 12)
connect _WIRE_168.sr, _T_2296
node _T_2297 = bits(_WIRE_169, 13, 13)
connect _WIRE_168.sx, _T_2297
node _T_2298 = bits(_WIRE_169, 14, 14)
connect _WIRE_168.sw, _T_2298
node _T_2299 = bits(_WIRE_169, 15, 15)
connect _WIRE_168.gf, _T_2299
node _T_2300 = bits(_WIRE_169, 16, 16)
connect _WIRE_168.pf, _T_2300
node _T_2301 = bits(_WIRE_169, 17, 17)
connect _WIRE_168.ae_stage2, _T_2301
node _T_2302 = bits(_WIRE_169, 18, 18)
connect _WIRE_168.ae_final, _T_2302
node _T_2303 = bits(_WIRE_169, 19, 19)
connect _WIRE_168.ae_ptw, _T_2303
node _T_2304 = bits(_WIRE_169, 20, 20)
connect _WIRE_168.g, _T_2304
node _T_2305 = bits(_WIRE_169, 21, 21)
connect _WIRE_168.u, _T_2305
node _T_2306 = bits(_WIRE_169, 41, 22)
connect _WIRE_168.ppn, _T_2306
wire _WIRE_170 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_171 : UInt<42>
connect _WIRE_171, sectored_entries[0][5].data[1]
node _T_2307 = bits(_WIRE_171, 0, 0)
connect _WIRE_170.fragmented_superpage, _T_2307
node _T_2308 = bits(_WIRE_171, 1, 1)
connect _WIRE_170.c, _T_2308
node _T_2309 = bits(_WIRE_171, 2, 2)
connect _WIRE_170.eff, _T_2309
node _T_2310 = bits(_WIRE_171, 3, 3)
connect _WIRE_170.paa, _T_2310
node _T_2311 = bits(_WIRE_171, 4, 4)
connect _WIRE_170.pal, _T_2311
node _T_2312 = bits(_WIRE_171, 5, 5)
connect _WIRE_170.ppp, _T_2312
node _T_2313 = bits(_WIRE_171, 6, 6)
connect _WIRE_170.pr, _T_2313
node _T_2314 = bits(_WIRE_171, 7, 7)
connect _WIRE_170.px, _T_2314
node _T_2315 = bits(_WIRE_171, 8, 8)
connect _WIRE_170.pw, _T_2315
node _T_2316 = bits(_WIRE_171, 9, 9)
connect _WIRE_170.hr, _T_2316
node _T_2317 = bits(_WIRE_171, 10, 10)
connect _WIRE_170.hx, _T_2317
node _T_2318 = bits(_WIRE_171, 11, 11)
connect _WIRE_170.hw, _T_2318
node _T_2319 = bits(_WIRE_171, 12, 12)
connect _WIRE_170.sr, _T_2319
node _T_2320 = bits(_WIRE_171, 13, 13)
connect _WIRE_170.sx, _T_2320
node _T_2321 = bits(_WIRE_171, 14, 14)
connect _WIRE_170.sw, _T_2321
node _T_2322 = bits(_WIRE_171, 15, 15)
connect _WIRE_170.gf, _T_2322
node _T_2323 = bits(_WIRE_171, 16, 16)
connect _WIRE_170.pf, _T_2323
node _T_2324 = bits(_WIRE_171, 17, 17)
connect _WIRE_170.ae_stage2, _T_2324
node _T_2325 = bits(_WIRE_171, 18, 18)
connect _WIRE_170.ae_final, _T_2325
node _T_2326 = bits(_WIRE_171, 19, 19)
connect _WIRE_170.ae_ptw, _T_2326
node _T_2327 = bits(_WIRE_171, 20, 20)
connect _WIRE_170.g, _T_2327
node _T_2328 = bits(_WIRE_171, 21, 21)
connect _WIRE_170.u, _T_2328
node _T_2329 = bits(_WIRE_171, 41, 22)
connect _WIRE_170.ppn, _T_2329
wire _WIRE_172 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_173 : UInt<42>
connect _WIRE_173, sectored_entries[0][5].data[2]
node _T_2330 = bits(_WIRE_173, 0, 0)
connect _WIRE_172.fragmented_superpage, _T_2330
node _T_2331 = bits(_WIRE_173, 1, 1)
connect _WIRE_172.c, _T_2331
node _T_2332 = bits(_WIRE_173, 2, 2)
connect _WIRE_172.eff, _T_2332
node _T_2333 = bits(_WIRE_173, 3, 3)
connect _WIRE_172.paa, _T_2333
node _T_2334 = bits(_WIRE_173, 4, 4)
connect _WIRE_172.pal, _T_2334
node _T_2335 = bits(_WIRE_173, 5, 5)
connect _WIRE_172.ppp, _T_2335
node _T_2336 = bits(_WIRE_173, 6, 6)
connect _WIRE_172.pr, _T_2336
node _T_2337 = bits(_WIRE_173, 7, 7)
connect _WIRE_172.px, _T_2337
node _T_2338 = bits(_WIRE_173, 8, 8)
connect _WIRE_172.pw, _T_2338
node _T_2339 = bits(_WIRE_173, 9, 9)
connect _WIRE_172.hr, _T_2339
node _T_2340 = bits(_WIRE_173, 10, 10)
connect _WIRE_172.hx, _T_2340
node _T_2341 = bits(_WIRE_173, 11, 11)
connect _WIRE_172.hw, _T_2341
node _T_2342 = bits(_WIRE_173, 12, 12)
connect _WIRE_172.sr, _T_2342
node _T_2343 = bits(_WIRE_173, 13, 13)
connect _WIRE_172.sx, _T_2343
node _T_2344 = bits(_WIRE_173, 14, 14)
connect _WIRE_172.sw, _T_2344
node _T_2345 = bits(_WIRE_173, 15, 15)
connect _WIRE_172.gf, _T_2345
node _T_2346 = bits(_WIRE_173, 16, 16)
connect _WIRE_172.pf, _T_2346
node _T_2347 = bits(_WIRE_173, 17, 17)
connect _WIRE_172.ae_stage2, _T_2347
node _T_2348 = bits(_WIRE_173, 18, 18)
connect _WIRE_172.ae_final, _T_2348
node _T_2349 = bits(_WIRE_173, 19, 19)
connect _WIRE_172.ae_ptw, _T_2349
node _T_2350 = bits(_WIRE_173, 20, 20)
connect _WIRE_172.g, _T_2350
node _T_2351 = bits(_WIRE_173, 21, 21)
connect _WIRE_172.u, _T_2351
node _T_2352 = bits(_WIRE_173, 41, 22)
connect _WIRE_172.ppn, _T_2352
wire _WIRE_174 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_175 : UInt<42>
connect _WIRE_175, sectored_entries[0][5].data[3]
node _T_2353 = bits(_WIRE_175, 0, 0)
connect _WIRE_174.fragmented_superpage, _T_2353
node _T_2354 = bits(_WIRE_175, 1, 1)
connect _WIRE_174.c, _T_2354
node _T_2355 = bits(_WIRE_175, 2, 2)
connect _WIRE_174.eff, _T_2355
node _T_2356 = bits(_WIRE_175, 3, 3)
connect _WIRE_174.paa, _T_2356
node _T_2357 = bits(_WIRE_175, 4, 4)
connect _WIRE_174.pal, _T_2357
node _T_2358 = bits(_WIRE_175, 5, 5)
connect _WIRE_174.ppp, _T_2358
node _T_2359 = bits(_WIRE_175, 6, 6)
connect _WIRE_174.pr, _T_2359
node _T_2360 = bits(_WIRE_175, 7, 7)
connect _WIRE_174.px, _T_2360
node _T_2361 = bits(_WIRE_175, 8, 8)
connect _WIRE_174.pw, _T_2361
node _T_2362 = bits(_WIRE_175, 9, 9)
connect _WIRE_174.hr, _T_2362
node _T_2363 = bits(_WIRE_175, 10, 10)
connect _WIRE_174.hx, _T_2363
node _T_2364 = bits(_WIRE_175, 11, 11)
connect _WIRE_174.hw, _T_2364
node _T_2365 = bits(_WIRE_175, 12, 12)
connect _WIRE_174.sr, _T_2365
node _T_2366 = bits(_WIRE_175, 13, 13)
connect _WIRE_174.sx, _T_2366
node _T_2367 = bits(_WIRE_175, 14, 14)
connect _WIRE_174.sw, _T_2367
node _T_2368 = bits(_WIRE_175, 15, 15)
connect _WIRE_174.gf, _T_2368
node _T_2369 = bits(_WIRE_175, 16, 16)
connect _WIRE_174.pf, _T_2369
node _T_2370 = bits(_WIRE_175, 17, 17)
connect _WIRE_174.ae_stage2, _T_2370
node _T_2371 = bits(_WIRE_175, 18, 18)
connect _WIRE_174.ae_final, _T_2371
node _T_2372 = bits(_WIRE_175, 19, 19)
connect _WIRE_174.ae_ptw, _T_2372
node _T_2373 = bits(_WIRE_175, 20, 20)
connect _WIRE_174.g, _T_2373
node _T_2374 = bits(_WIRE_175, 21, 21)
connect _WIRE_174.u, _T_2374
node _T_2375 = bits(_WIRE_175, 41, 22)
connect _WIRE_174.ppn, _T_2375
node _T_2376 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2377 = and(_T_2376, _WIRE_168.fragmented_superpage)
when _T_2377 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
node _T_2378 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2379 = and(_T_2378, _WIRE_170.fragmented_superpage)
when _T_2379 :
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
node _T_2380 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2381 = and(_T_2380, _WIRE_172.fragmented_superpage)
when _T_2381 :
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
node _T_2382 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2383 = and(_T_2382, _WIRE_174.fragmented_superpage)
when _T_2383 :
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
else :
node _T_2384 = eq(hg_5, UInt<1>(0h0))
node _T_2385 = and(_T_2384, io.sfence.bits.rs2)
when _T_2385 :
wire _WIRE_176 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_177 : UInt<42>
connect _WIRE_177, sectored_entries[0][5].data[0]
node _T_2386 = bits(_WIRE_177, 0, 0)
connect _WIRE_176.fragmented_superpage, _T_2386
node _T_2387 = bits(_WIRE_177, 1, 1)
connect _WIRE_176.c, _T_2387
node _T_2388 = bits(_WIRE_177, 2, 2)
connect _WIRE_176.eff, _T_2388
node _T_2389 = bits(_WIRE_177, 3, 3)
connect _WIRE_176.paa, _T_2389
node _T_2390 = bits(_WIRE_177, 4, 4)
connect _WIRE_176.pal, _T_2390
node _T_2391 = bits(_WIRE_177, 5, 5)
connect _WIRE_176.ppp, _T_2391
node _T_2392 = bits(_WIRE_177, 6, 6)
connect _WIRE_176.pr, _T_2392
node _T_2393 = bits(_WIRE_177, 7, 7)
connect _WIRE_176.px, _T_2393
node _T_2394 = bits(_WIRE_177, 8, 8)
connect _WIRE_176.pw, _T_2394
node _T_2395 = bits(_WIRE_177, 9, 9)
connect _WIRE_176.hr, _T_2395
node _T_2396 = bits(_WIRE_177, 10, 10)
connect _WIRE_176.hx, _T_2396
node _T_2397 = bits(_WIRE_177, 11, 11)
connect _WIRE_176.hw, _T_2397
node _T_2398 = bits(_WIRE_177, 12, 12)
connect _WIRE_176.sr, _T_2398
node _T_2399 = bits(_WIRE_177, 13, 13)
connect _WIRE_176.sx, _T_2399
node _T_2400 = bits(_WIRE_177, 14, 14)
connect _WIRE_176.sw, _T_2400
node _T_2401 = bits(_WIRE_177, 15, 15)
connect _WIRE_176.gf, _T_2401
node _T_2402 = bits(_WIRE_177, 16, 16)
connect _WIRE_176.pf, _T_2402
node _T_2403 = bits(_WIRE_177, 17, 17)
connect _WIRE_176.ae_stage2, _T_2403
node _T_2404 = bits(_WIRE_177, 18, 18)
connect _WIRE_176.ae_final, _T_2404
node _T_2405 = bits(_WIRE_177, 19, 19)
connect _WIRE_176.ae_ptw, _T_2405
node _T_2406 = bits(_WIRE_177, 20, 20)
connect _WIRE_176.g, _T_2406
node _T_2407 = bits(_WIRE_177, 21, 21)
connect _WIRE_176.u, _T_2407
node _T_2408 = bits(_WIRE_177, 41, 22)
connect _WIRE_176.ppn, _T_2408
wire _WIRE_178 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_179 : UInt<42>
connect _WIRE_179, sectored_entries[0][5].data[1]
node _T_2409 = bits(_WIRE_179, 0, 0)
connect _WIRE_178.fragmented_superpage, _T_2409
node _T_2410 = bits(_WIRE_179, 1, 1)
connect _WIRE_178.c, _T_2410
node _T_2411 = bits(_WIRE_179, 2, 2)
connect _WIRE_178.eff, _T_2411
node _T_2412 = bits(_WIRE_179, 3, 3)
connect _WIRE_178.paa, _T_2412
node _T_2413 = bits(_WIRE_179, 4, 4)
connect _WIRE_178.pal, _T_2413
node _T_2414 = bits(_WIRE_179, 5, 5)
connect _WIRE_178.ppp, _T_2414
node _T_2415 = bits(_WIRE_179, 6, 6)
connect _WIRE_178.pr, _T_2415
node _T_2416 = bits(_WIRE_179, 7, 7)
connect _WIRE_178.px, _T_2416
node _T_2417 = bits(_WIRE_179, 8, 8)
connect _WIRE_178.pw, _T_2417
node _T_2418 = bits(_WIRE_179, 9, 9)
connect _WIRE_178.hr, _T_2418
node _T_2419 = bits(_WIRE_179, 10, 10)
connect _WIRE_178.hx, _T_2419
node _T_2420 = bits(_WIRE_179, 11, 11)
connect _WIRE_178.hw, _T_2420
node _T_2421 = bits(_WIRE_179, 12, 12)
connect _WIRE_178.sr, _T_2421
node _T_2422 = bits(_WIRE_179, 13, 13)
connect _WIRE_178.sx, _T_2422
node _T_2423 = bits(_WIRE_179, 14, 14)
connect _WIRE_178.sw, _T_2423
node _T_2424 = bits(_WIRE_179, 15, 15)
connect _WIRE_178.gf, _T_2424
node _T_2425 = bits(_WIRE_179, 16, 16)
connect _WIRE_178.pf, _T_2425
node _T_2426 = bits(_WIRE_179, 17, 17)
connect _WIRE_178.ae_stage2, _T_2426
node _T_2427 = bits(_WIRE_179, 18, 18)
connect _WIRE_178.ae_final, _T_2427
node _T_2428 = bits(_WIRE_179, 19, 19)
connect _WIRE_178.ae_ptw, _T_2428
node _T_2429 = bits(_WIRE_179, 20, 20)
connect _WIRE_178.g, _T_2429
node _T_2430 = bits(_WIRE_179, 21, 21)
connect _WIRE_178.u, _T_2430
node _T_2431 = bits(_WIRE_179, 41, 22)
connect _WIRE_178.ppn, _T_2431
wire _WIRE_180 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_181 : UInt<42>
connect _WIRE_181, sectored_entries[0][5].data[2]
node _T_2432 = bits(_WIRE_181, 0, 0)
connect _WIRE_180.fragmented_superpage, _T_2432
node _T_2433 = bits(_WIRE_181, 1, 1)
connect _WIRE_180.c, _T_2433
node _T_2434 = bits(_WIRE_181, 2, 2)
connect _WIRE_180.eff, _T_2434
node _T_2435 = bits(_WIRE_181, 3, 3)
connect _WIRE_180.paa, _T_2435
node _T_2436 = bits(_WIRE_181, 4, 4)
connect _WIRE_180.pal, _T_2436
node _T_2437 = bits(_WIRE_181, 5, 5)
connect _WIRE_180.ppp, _T_2437
node _T_2438 = bits(_WIRE_181, 6, 6)
connect _WIRE_180.pr, _T_2438
node _T_2439 = bits(_WIRE_181, 7, 7)
connect _WIRE_180.px, _T_2439
node _T_2440 = bits(_WIRE_181, 8, 8)
connect _WIRE_180.pw, _T_2440
node _T_2441 = bits(_WIRE_181, 9, 9)
connect _WIRE_180.hr, _T_2441
node _T_2442 = bits(_WIRE_181, 10, 10)
connect _WIRE_180.hx, _T_2442
node _T_2443 = bits(_WIRE_181, 11, 11)
connect _WIRE_180.hw, _T_2443
node _T_2444 = bits(_WIRE_181, 12, 12)
connect _WIRE_180.sr, _T_2444
node _T_2445 = bits(_WIRE_181, 13, 13)
connect _WIRE_180.sx, _T_2445
node _T_2446 = bits(_WIRE_181, 14, 14)
connect _WIRE_180.sw, _T_2446
node _T_2447 = bits(_WIRE_181, 15, 15)
connect _WIRE_180.gf, _T_2447
node _T_2448 = bits(_WIRE_181, 16, 16)
connect _WIRE_180.pf, _T_2448
node _T_2449 = bits(_WIRE_181, 17, 17)
connect _WIRE_180.ae_stage2, _T_2449
node _T_2450 = bits(_WIRE_181, 18, 18)
connect _WIRE_180.ae_final, _T_2450
node _T_2451 = bits(_WIRE_181, 19, 19)
connect _WIRE_180.ae_ptw, _T_2451
node _T_2452 = bits(_WIRE_181, 20, 20)
connect _WIRE_180.g, _T_2452
node _T_2453 = bits(_WIRE_181, 21, 21)
connect _WIRE_180.u, _T_2453
node _T_2454 = bits(_WIRE_181, 41, 22)
connect _WIRE_180.ppn, _T_2454
wire _WIRE_182 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_183 : UInt<42>
connect _WIRE_183, sectored_entries[0][5].data[3]
node _T_2455 = bits(_WIRE_183, 0, 0)
connect _WIRE_182.fragmented_superpage, _T_2455
node _T_2456 = bits(_WIRE_183, 1, 1)
connect _WIRE_182.c, _T_2456
node _T_2457 = bits(_WIRE_183, 2, 2)
connect _WIRE_182.eff, _T_2457
node _T_2458 = bits(_WIRE_183, 3, 3)
connect _WIRE_182.paa, _T_2458
node _T_2459 = bits(_WIRE_183, 4, 4)
connect _WIRE_182.pal, _T_2459
node _T_2460 = bits(_WIRE_183, 5, 5)
connect _WIRE_182.ppp, _T_2460
node _T_2461 = bits(_WIRE_183, 6, 6)
connect _WIRE_182.pr, _T_2461
node _T_2462 = bits(_WIRE_183, 7, 7)
connect _WIRE_182.px, _T_2462
node _T_2463 = bits(_WIRE_183, 8, 8)
connect _WIRE_182.pw, _T_2463
node _T_2464 = bits(_WIRE_183, 9, 9)
connect _WIRE_182.hr, _T_2464
node _T_2465 = bits(_WIRE_183, 10, 10)
connect _WIRE_182.hx, _T_2465
node _T_2466 = bits(_WIRE_183, 11, 11)
connect _WIRE_182.hw, _T_2466
node _T_2467 = bits(_WIRE_183, 12, 12)
connect _WIRE_182.sr, _T_2467
node _T_2468 = bits(_WIRE_183, 13, 13)
connect _WIRE_182.sx, _T_2468
node _T_2469 = bits(_WIRE_183, 14, 14)
connect _WIRE_182.sw, _T_2469
node _T_2470 = bits(_WIRE_183, 15, 15)
connect _WIRE_182.gf, _T_2470
node _T_2471 = bits(_WIRE_183, 16, 16)
connect _WIRE_182.pf, _T_2471
node _T_2472 = bits(_WIRE_183, 17, 17)
connect _WIRE_182.ae_stage2, _T_2472
node _T_2473 = bits(_WIRE_183, 18, 18)
connect _WIRE_182.ae_final, _T_2473
node _T_2474 = bits(_WIRE_183, 19, 19)
connect _WIRE_182.ae_ptw, _T_2474
node _T_2475 = bits(_WIRE_183, 20, 20)
connect _WIRE_182.g, _T_2475
node _T_2476 = bits(_WIRE_183, 21, 21)
connect _WIRE_182.u, _T_2476
node _T_2477 = bits(_WIRE_183, 41, 22)
connect _WIRE_182.ppn, _T_2477
node _T_2478 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2479 = eq(_WIRE_176.g, UInt<1>(0h0))
node _T_2480 = and(_T_2478, _T_2479)
when _T_2480 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
node _T_2481 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2482 = eq(_WIRE_178.g, UInt<1>(0h0))
node _T_2483 = and(_T_2481, _T_2482)
when _T_2483 :
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
node _T_2484 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2485 = eq(_WIRE_180.g, UInt<1>(0h0))
node _T_2486 = and(_T_2484, _T_2485)
when _T_2486 :
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
node _T_2487 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2488 = eq(_WIRE_182.g, UInt<1>(0h0))
node _T_2489 = and(_T_2487, _T_2488)
when _T_2489 :
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
else :
node _T_2490 = or(hv_5, hg_5)
wire _WIRE_184 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_185 : UInt<42>
connect _WIRE_185, sectored_entries[0][5].data[0]
node _T_2491 = bits(_WIRE_185, 0, 0)
connect _WIRE_184.fragmented_superpage, _T_2491
node _T_2492 = bits(_WIRE_185, 1, 1)
connect _WIRE_184.c, _T_2492
node _T_2493 = bits(_WIRE_185, 2, 2)
connect _WIRE_184.eff, _T_2493
node _T_2494 = bits(_WIRE_185, 3, 3)
connect _WIRE_184.paa, _T_2494
node _T_2495 = bits(_WIRE_185, 4, 4)
connect _WIRE_184.pal, _T_2495
node _T_2496 = bits(_WIRE_185, 5, 5)
connect _WIRE_184.ppp, _T_2496
node _T_2497 = bits(_WIRE_185, 6, 6)
connect _WIRE_184.pr, _T_2497
node _T_2498 = bits(_WIRE_185, 7, 7)
connect _WIRE_184.px, _T_2498
node _T_2499 = bits(_WIRE_185, 8, 8)
connect _WIRE_184.pw, _T_2499
node _T_2500 = bits(_WIRE_185, 9, 9)
connect _WIRE_184.hr, _T_2500
node _T_2501 = bits(_WIRE_185, 10, 10)
connect _WIRE_184.hx, _T_2501
node _T_2502 = bits(_WIRE_185, 11, 11)
connect _WIRE_184.hw, _T_2502
node _T_2503 = bits(_WIRE_185, 12, 12)
connect _WIRE_184.sr, _T_2503
node _T_2504 = bits(_WIRE_185, 13, 13)
connect _WIRE_184.sx, _T_2504
node _T_2505 = bits(_WIRE_185, 14, 14)
connect _WIRE_184.sw, _T_2505
node _T_2506 = bits(_WIRE_185, 15, 15)
connect _WIRE_184.gf, _T_2506
node _T_2507 = bits(_WIRE_185, 16, 16)
connect _WIRE_184.pf, _T_2507
node _T_2508 = bits(_WIRE_185, 17, 17)
connect _WIRE_184.ae_stage2, _T_2508
node _T_2509 = bits(_WIRE_185, 18, 18)
connect _WIRE_184.ae_final, _T_2509
node _T_2510 = bits(_WIRE_185, 19, 19)
connect _WIRE_184.ae_ptw, _T_2510
node _T_2511 = bits(_WIRE_185, 20, 20)
connect _WIRE_184.g, _T_2511
node _T_2512 = bits(_WIRE_185, 21, 21)
connect _WIRE_184.u, _T_2512
node _T_2513 = bits(_WIRE_185, 41, 22)
connect _WIRE_184.ppn, _T_2513
wire _WIRE_186 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_187 : UInt<42>
connect _WIRE_187, sectored_entries[0][5].data[1]
node _T_2514 = bits(_WIRE_187, 0, 0)
connect _WIRE_186.fragmented_superpage, _T_2514
node _T_2515 = bits(_WIRE_187, 1, 1)
connect _WIRE_186.c, _T_2515
node _T_2516 = bits(_WIRE_187, 2, 2)
connect _WIRE_186.eff, _T_2516
node _T_2517 = bits(_WIRE_187, 3, 3)
connect _WIRE_186.paa, _T_2517
node _T_2518 = bits(_WIRE_187, 4, 4)
connect _WIRE_186.pal, _T_2518
node _T_2519 = bits(_WIRE_187, 5, 5)
connect _WIRE_186.ppp, _T_2519
node _T_2520 = bits(_WIRE_187, 6, 6)
connect _WIRE_186.pr, _T_2520
node _T_2521 = bits(_WIRE_187, 7, 7)
connect _WIRE_186.px, _T_2521
node _T_2522 = bits(_WIRE_187, 8, 8)
connect _WIRE_186.pw, _T_2522
node _T_2523 = bits(_WIRE_187, 9, 9)
connect _WIRE_186.hr, _T_2523
node _T_2524 = bits(_WIRE_187, 10, 10)
connect _WIRE_186.hx, _T_2524
node _T_2525 = bits(_WIRE_187, 11, 11)
connect _WIRE_186.hw, _T_2525
node _T_2526 = bits(_WIRE_187, 12, 12)
connect _WIRE_186.sr, _T_2526
node _T_2527 = bits(_WIRE_187, 13, 13)
connect _WIRE_186.sx, _T_2527
node _T_2528 = bits(_WIRE_187, 14, 14)
connect _WIRE_186.sw, _T_2528
node _T_2529 = bits(_WIRE_187, 15, 15)
connect _WIRE_186.gf, _T_2529
node _T_2530 = bits(_WIRE_187, 16, 16)
connect _WIRE_186.pf, _T_2530
node _T_2531 = bits(_WIRE_187, 17, 17)
connect _WIRE_186.ae_stage2, _T_2531
node _T_2532 = bits(_WIRE_187, 18, 18)
connect _WIRE_186.ae_final, _T_2532
node _T_2533 = bits(_WIRE_187, 19, 19)
connect _WIRE_186.ae_ptw, _T_2533
node _T_2534 = bits(_WIRE_187, 20, 20)
connect _WIRE_186.g, _T_2534
node _T_2535 = bits(_WIRE_187, 21, 21)
connect _WIRE_186.u, _T_2535
node _T_2536 = bits(_WIRE_187, 41, 22)
connect _WIRE_186.ppn, _T_2536
wire _WIRE_188 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_189 : UInt<42>
connect _WIRE_189, sectored_entries[0][5].data[2]
node _T_2537 = bits(_WIRE_189, 0, 0)
connect _WIRE_188.fragmented_superpage, _T_2537
node _T_2538 = bits(_WIRE_189, 1, 1)
connect _WIRE_188.c, _T_2538
node _T_2539 = bits(_WIRE_189, 2, 2)
connect _WIRE_188.eff, _T_2539
node _T_2540 = bits(_WIRE_189, 3, 3)
connect _WIRE_188.paa, _T_2540
node _T_2541 = bits(_WIRE_189, 4, 4)
connect _WIRE_188.pal, _T_2541
node _T_2542 = bits(_WIRE_189, 5, 5)
connect _WIRE_188.ppp, _T_2542
node _T_2543 = bits(_WIRE_189, 6, 6)
connect _WIRE_188.pr, _T_2543
node _T_2544 = bits(_WIRE_189, 7, 7)
connect _WIRE_188.px, _T_2544
node _T_2545 = bits(_WIRE_189, 8, 8)
connect _WIRE_188.pw, _T_2545
node _T_2546 = bits(_WIRE_189, 9, 9)
connect _WIRE_188.hr, _T_2546
node _T_2547 = bits(_WIRE_189, 10, 10)
connect _WIRE_188.hx, _T_2547
node _T_2548 = bits(_WIRE_189, 11, 11)
connect _WIRE_188.hw, _T_2548
node _T_2549 = bits(_WIRE_189, 12, 12)
connect _WIRE_188.sr, _T_2549
node _T_2550 = bits(_WIRE_189, 13, 13)
connect _WIRE_188.sx, _T_2550
node _T_2551 = bits(_WIRE_189, 14, 14)
connect _WIRE_188.sw, _T_2551
node _T_2552 = bits(_WIRE_189, 15, 15)
connect _WIRE_188.gf, _T_2552
node _T_2553 = bits(_WIRE_189, 16, 16)
connect _WIRE_188.pf, _T_2553
node _T_2554 = bits(_WIRE_189, 17, 17)
connect _WIRE_188.ae_stage2, _T_2554
node _T_2555 = bits(_WIRE_189, 18, 18)
connect _WIRE_188.ae_final, _T_2555
node _T_2556 = bits(_WIRE_189, 19, 19)
connect _WIRE_188.ae_ptw, _T_2556
node _T_2557 = bits(_WIRE_189, 20, 20)
connect _WIRE_188.g, _T_2557
node _T_2558 = bits(_WIRE_189, 21, 21)
connect _WIRE_188.u, _T_2558
node _T_2559 = bits(_WIRE_189, 41, 22)
connect _WIRE_188.ppn, _T_2559
wire _WIRE_190 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_191 : UInt<42>
connect _WIRE_191, sectored_entries[0][5].data[3]
node _T_2560 = bits(_WIRE_191, 0, 0)
connect _WIRE_190.fragmented_superpage, _T_2560
node _T_2561 = bits(_WIRE_191, 1, 1)
connect _WIRE_190.c, _T_2561
node _T_2562 = bits(_WIRE_191, 2, 2)
connect _WIRE_190.eff, _T_2562
node _T_2563 = bits(_WIRE_191, 3, 3)
connect _WIRE_190.paa, _T_2563
node _T_2564 = bits(_WIRE_191, 4, 4)
connect _WIRE_190.pal, _T_2564
node _T_2565 = bits(_WIRE_191, 5, 5)
connect _WIRE_190.ppp, _T_2565
node _T_2566 = bits(_WIRE_191, 6, 6)
connect _WIRE_190.pr, _T_2566
node _T_2567 = bits(_WIRE_191, 7, 7)
connect _WIRE_190.px, _T_2567
node _T_2568 = bits(_WIRE_191, 8, 8)
connect _WIRE_190.pw, _T_2568
node _T_2569 = bits(_WIRE_191, 9, 9)
connect _WIRE_190.hr, _T_2569
node _T_2570 = bits(_WIRE_191, 10, 10)
connect _WIRE_190.hx, _T_2570
node _T_2571 = bits(_WIRE_191, 11, 11)
connect _WIRE_190.hw, _T_2571
node _T_2572 = bits(_WIRE_191, 12, 12)
connect _WIRE_190.sr, _T_2572
node _T_2573 = bits(_WIRE_191, 13, 13)
connect _WIRE_190.sx, _T_2573
node _T_2574 = bits(_WIRE_191, 14, 14)
connect _WIRE_190.sw, _T_2574
node _T_2575 = bits(_WIRE_191, 15, 15)
connect _WIRE_190.gf, _T_2575
node _T_2576 = bits(_WIRE_191, 16, 16)
connect _WIRE_190.pf, _T_2576
node _T_2577 = bits(_WIRE_191, 17, 17)
connect _WIRE_190.ae_stage2, _T_2577
node _T_2578 = bits(_WIRE_191, 18, 18)
connect _WIRE_190.ae_final, _T_2578
node _T_2579 = bits(_WIRE_191, 19, 19)
connect _WIRE_190.ae_ptw, _T_2579
node _T_2580 = bits(_WIRE_191, 20, 20)
connect _WIRE_190.g, _T_2580
node _T_2581 = bits(_WIRE_191, 21, 21)
connect _WIRE_190.u, _T_2581
node _T_2582 = bits(_WIRE_191, 41, 22)
connect _WIRE_190.ppn, _T_2582
node _T_2583 = eq(sectored_entries[0][5].tag_v, _T_2490)
when _T_2583 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
node _T_2584 = eq(sectored_entries[0][5].tag_v, _T_2490)
when _T_2584 :
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
node _T_2585 = eq(sectored_entries[0][5].tag_v, _T_2490)
when _T_2585 :
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
node _T_2586 = eq(sectored_entries[0][5].tag_v, _T_2490)
when _T_2586 :
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
node hv_6 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_6 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_2587 = eq(hg_6, UInt<1>(0h0))
node _T_2588 = and(_T_2587, io.sfence.bits.rs1)
when _T_2588 :
node _T_2589 = xor(sectored_entries[0][6].tag_vpn, vpn)
node _T_2590 = shr(_T_2589, 2)
node _T_2591 = eq(_T_2590, UInt<1>(0h0))
node _T_2592 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2593 = and(_T_2591, _T_2592)
when _T_2593 :
wire _WIRE_192 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_193 : UInt<42>
connect _WIRE_193, sectored_entries[0][6].data[0]
node _T_2594 = bits(_WIRE_193, 0, 0)
connect _WIRE_192.fragmented_superpage, _T_2594
node _T_2595 = bits(_WIRE_193, 1, 1)
connect _WIRE_192.c, _T_2595
node _T_2596 = bits(_WIRE_193, 2, 2)
connect _WIRE_192.eff, _T_2596
node _T_2597 = bits(_WIRE_193, 3, 3)
connect _WIRE_192.paa, _T_2597
node _T_2598 = bits(_WIRE_193, 4, 4)
connect _WIRE_192.pal, _T_2598
node _T_2599 = bits(_WIRE_193, 5, 5)
connect _WIRE_192.ppp, _T_2599
node _T_2600 = bits(_WIRE_193, 6, 6)
connect _WIRE_192.pr, _T_2600
node _T_2601 = bits(_WIRE_193, 7, 7)
connect _WIRE_192.px, _T_2601
node _T_2602 = bits(_WIRE_193, 8, 8)
connect _WIRE_192.pw, _T_2602
node _T_2603 = bits(_WIRE_193, 9, 9)
connect _WIRE_192.hr, _T_2603
node _T_2604 = bits(_WIRE_193, 10, 10)
connect _WIRE_192.hx, _T_2604
node _T_2605 = bits(_WIRE_193, 11, 11)
connect _WIRE_192.hw, _T_2605
node _T_2606 = bits(_WIRE_193, 12, 12)
connect _WIRE_192.sr, _T_2606
node _T_2607 = bits(_WIRE_193, 13, 13)
connect _WIRE_192.sx, _T_2607
node _T_2608 = bits(_WIRE_193, 14, 14)
connect _WIRE_192.sw, _T_2608
node _T_2609 = bits(_WIRE_193, 15, 15)
connect _WIRE_192.gf, _T_2609
node _T_2610 = bits(_WIRE_193, 16, 16)
connect _WIRE_192.pf, _T_2610
node _T_2611 = bits(_WIRE_193, 17, 17)
connect _WIRE_192.ae_stage2, _T_2611
node _T_2612 = bits(_WIRE_193, 18, 18)
connect _WIRE_192.ae_final, _T_2612
node _T_2613 = bits(_WIRE_193, 19, 19)
connect _WIRE_192.ae_ptw, _T_2613
node _T_2614 = bits(_WIRE_193, 20, 20)
connect _WIRE_192.g, _T_2614
node _T_2615 = bits(_WIRE_193, 21, 21)
connect _WIRE_192.u, _T_2615
node _T_2616 = bits(_WIRE_193, 41, 22)
connect _WIRE_192.ppn, _T_2616
wire _WIRE_194 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_195 : UInt<42>
connect _WIRE_195, sectored_entries[0][6].data[1]
node _T_2617 = bits(_WIRE_195, 0, 0)
connect _WIRE_194.fragmented_superpage, _T_2617
node _T_2618 = bits(_WIRE_195, 1, 1)
connect _WIRE_194.c, _T_2618
node _T_2619 = bits(_WIRE_195, 2, 2)
connect _WIRE_194.eff, _T_2619
node _T_2620 = bits(_WIRE_195, 3, 3)
connect _WIRE_194.paa, _T_2620
node _T_2621 = bits(_WIRE_195, 4, 4)
connect _WIRE_194.pal, _T_2621
node _T_2622 = bits(_WIRE_195, 5, 5)
connect _WIRE_194.ppp, _T_2622
node _T_2623 = bits(_WIRE_195, 6, 6)
connect _WIRE_194.pr, _T_2623
node _T_2624 = bits(_WIRE_195, 7, 7)
connect _WIRE_194.px, _T_2624
node _T_2625 = bits(_WIRE_195, 8, 8)
connect _WIRE_194.pw, _T_2625
node _T_2626 = bits(_WIRE_195, 9, 9)
connect _WIRE_194.hr, _T_2626
node _T_2627 = bits(_WIRE_195, 10, 10)
connect _WIRE_194.hx, _T_2627
node _T_2628 = bits(_WIRE_195, 11, 11)
connect _WIRE_194.hw, _T_2628
node _T_2629 = bits(_WIRE_195, 12, 12)
connect _WIRE_194.sr, _T_2629
node _T_2630 = bits(_WIRE_195, 13, 13)
connect _WIRE_194.sx, _T_2630
node _T_2631 = bits(_WIRE_195, 14, 14)
connect _WIRE_194.sw, _T_2631
node _T_2632 = bits(_WIRE_195, 15, 15)
connect _WIRE_194.gf, _T_2632
node _T_2633 = bits(_WIRE_195, 16, 16)
connect _WIRE_194.pf, _T_2633
node _T_2634 = bits(_WIRE_195, 17, 17)
connect _WIRE_194.ae_stage2, _T_2634
node _T_2635 = bits(_WIRE_195, 18, 18)
connect _WIRE_194.ae_final, _T_2635
node _T_2636 = bits(_WIRE_195, 19, 19)
connect _WIRE_194.ae_ptw, _T_2636
node _T_2637 = bits(_WIRE_195, 20, 20)
connect _WIRE_194.g, _T_2637
node _T_2638 = bits(_WIRE_195, 21, 21)
connect _WIRE_194.u, _T_2638
node _T_2639 = bits(_WIRE_195, 41, 22)
connect _WIRE_194.ppn, _T_2639
wire _WIRE_196 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_197 : UInt<42>
connect _WIRE_197, sectored_entries[0][6].data[2]
node _T_2640 = bits(_WIRE_197, 0, 0)
connect _WIRE_196.fragmented_superpage, _T_2640
node _T_2641 = bits(_WIRE_197, 1, 1)
connect _WIRE_196.c, _T_2641
node _T_2642 = bits(_WIRE_197, 2, 2)
connect _WIRE_196.eff, _T_2642
node _T_2643 = bits(_WIRE_197, 3, 3)
connect _WIRE_196.paa, _T_2643
node _T_2644 = bits(_WIRE_197, 4, 4)
connect _WIRE_196.pal, _T_2644
node _T_2645 = bits(_WIRE_197, 5, 5)
connect _WIRE_196.ppp, _T_2645
node _T_2646 = bits(_WIRE_197, 6, 6)
connect _WIRE_196.pr, _T_2646
node _T_2647 = bits(_WIRE_197, 7, 7)
connect _WIRE_196.px, _T_2647
node _T_2648 = bits(_WIRE_197, 8, 8)
connect _WIRE_196.pw, _T_2648
node _T_2649 = bits(_WIRE_197, 9, 9)
connect _WIRE_196.hr, _T_2649
node _T_2650 = bits(_WIRE_197, 10, 10)
connect _WIRE_196.hx, _T_2650
node _T_2651 = bits(_WIRE_197, 11, 11)
connect _WIRE_196.hw, _T_2651
node _T_2652 = bits(_WIRE_197, 12, 12)
connect _WIRE_196.sr, _T_2652
node _T_2653 = bits(_WIRE_197, 13, 13)
connect _WIRE_196.sx, _T_2653
node _T_2654 = bits(_WIRE_197, 14, 14)
connect _WIRE_196.sw, _T_2654
node _T_2655 = bits(_WIRE_197, 15, 15)
connect _WIRE_196.gf, _T_2655
node _T_2656 = bits(_WIRE_197, 16, 16)
connect _WIRE_196.pf, _T_2656
node _T_2657 = bits(_WIRE_197, 17, 17)
connect _WIRE_196.ae_stage2, _T_2657
node _T_2658 = bits(_WIRE_197, 18, 18)
connect _WIRE_196.ae_final, _T_2658
node _T_2659 = bits(_WIRE_197, 19, 19)
connect _WIRE_196.ae_ptw, _T_2659
node _T_2660 = bits(_WIRE_197, 20, 20)
connect _WIRE_196.g, _T_2660
node _T_2661 = bits(_WIRE_197, 21, 21)
connect _WIRE_196.u, _T_2661
node _T_2662 = bits(_WIRE_197, 41, 22)
connect _WIRE_196.ppn, _T_2662
wire _WIRE_198 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_199 : UInt<42>
connect _WIRE_199, sectored_entries[0][6].data[3]
node _T_2663 = bits(_WIRE_199, 0, 0)
connect _WIRE_198.fragmented_superpage, _T_2663
node _T_2664 = bits(_WIRE_199, 1, 1)
connect _WIRE_198.c, _T_2664
node _T_2665 = bits(_WIRE_199, 2, 2)
connect _WIRE_198.eff, _T_2665
node _T_2666 = bits(_WIRE_199, 3, 3)
connect _WIRE_198.paa, _T_2666
node _T_2667 = bits(_WIRE_199, 4, 4)
connect _WIRE_198.pal, _T_2667
node _T_2668 = bits(_WIRE_199, 5, 5)
connect _WIRE_198.ppp, _T_2668
node _T_2669 = bits(_WIRE_199, 6, 6)
connect _WIRE_198.pr, _T_2669
node _T_2670 = bits(_WIRE_199, 7, 7)
connect _WIRE_198.px, _T_2670
node _T_2671 = bits(_WIRE_199, 8, 8)
connect _WIRE_198.pw, _T_2671
node _T_2672 = bits(_WIRE_199, 9, 9)
connect _WIRE_198.hr, _T_2672
node _T_2673 = bits(_WIRE_199, 10, 10)
connect _WIRE_198.hx, _T_2673
node _T_2674 = bits(_WIRE_199, 11, 11)
connect _WIRE_198.hw, _T_2674
node _T_2675 = bits(_WIRE_199, 12, 12)
connect _WIRE_198.sr, _T_2675
node _T_2676 = bits(_WIRE_199, 13, 13)
connect _WIRE_198.sx, _T_2676
node _T_2677 = bits(_WIRE_199, 14, 14)
connect _WIRE_198.sw, _T_2677
node _T_2678 = bits(_WIRE_199, 15, 15)
connect _WIRE_198.gf, _T_2678
node _T_2679 = bits(_WIRE_199, 16, 16)
connect _WIRE_198.pf, _T_2679
node _T_2680 = bits(_WIRE_199, 17, 17)
connect _WIRE_198.ae_stage2, _T_2680
node _T_2681 = bits(_WIRE_199, 18, 18)
connect _WIRE_198.ae_final, _T_2681
node _T_2682 = bits(_WIRE_199, 19, 19)
connect _WIRE_198.ae_ptw, _T_2682
node _T_2683 = bits(_WIRE_199, 20, 20)
connect _WIRE_198.g, _T_2683
node _T_2684 = bits(_WIRE_199, 21, 21)
connect _WIRE_198.u, _T_2684
node _T_2685 = bits(_WIRE_199, 41, 22)
connect _WIRE_198.ppn, _T_2685
node _T_2686 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2687 = bits(vpn, 1, 0)
node _T_2688 = eq(UInt<1>(0h0), _T_2687)
node _T_2689 = and(_T_2686, _T_2688)
when _T_2689 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
node _T_2690 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2691 = bits(vpn, 1, 0)
node _T_2692 = eq(UInt<1>(0h1), _T_2691)
node _T_2693 = and(_T_2690, _T_2692)
when _T_2693 :
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
node _T_2694 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2695 = bits(vpn, 1, 0)
node _T_2696 = eq(UInt<2>(0h2), _T_2695)
node _T_2697 = and(_T_2694, _T_2696)
when _T_2697 :
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
node _T_2698 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2699 = bits(vpn, 1, 0)
node _T_2700 = eq(UInt<2>(0h3), _T_2699)
node _T_2701 = and(_T_2698, _T_2700)
when _T_2701 :
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
node _T_2702 = xor(sectored_entries[0][6].tag_vpn, vpn)
node _T_2703 = shr(_T_2702, 18)
node _T_2704 = eq(_T_2703, UInt<1>(0h0))
when _T_2704 :
wire _WIRE_200 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_201 : UInt<42>
connect _WIRE_201, sectored_entries[0][6].data[0]
node _T_2705 = bits(_WIRE_201, 0, 0)
connect _WIRE_200.fragmented_superpage, _T_2705
node _T_2706 = bits(_WIRE_201, 1, 1)
connect _WIRE_200.c, _T_2706
node _T_2707 = bits(_WIRE_201, 2, 2)
connect _WIRE_200.eff, _T_2707
node _T_2708 = bits(_WIRE_201, 3, 3)
connect _WIRE_200.paa, _T_2708
node _T_2709 = bits(_WIRE_201, 4, 4)
connect _WIRE_200.pal, _T_2709
node _T_2710 = bits(_WIRE_201, 5, 5)
connect _WIRE_200.ppp, _T_2710
node _T_2711 = bits(_WIRE_201, 6, 6)
connect _WIRE_200.pr, _T_2711
node _T_2712 = bits(_WIRE_201, 7, 7)
connect _WIRE_200.px, _T_2712
node _T_2713 = bits(_WIRE_201, 8, 8)
connect _WIRE_200.pw, _T_2713
node _T_2714 = bits(_WIRE_201, 9, 9)
connect _WIRE_200.hr, _T_2714
node _T_2715 = bits(_WIRE_201, 10, 10)
connect _WIRE_200.hx, _T_2715
node _T_2716 = bits(_WIRE_201, 11, 11)
connect _WIRE_200.hw, _T_2716
node _T_2717 = bits(_WIRE_201, 12, 12)
connect _WIRE_200.sr, _T_2717
node _T_2718 = bits(_WIRE_201, 13, 13)
connect _WIRE_200.sx, _T_2718
node _T_2719 = bits(_WIRE_201, 14, 14)
connect _WIRE_200.sw, _T_2719
node _T_2720 = bits(_WIRE_201, 15, 15)
connect _WIRE_200.gf, _T_2720
node _T_2721 = bits(_WIRE_201, 16, 16)
connect _WIRE_200.pf, _T_2721
node _T_2722 = bits(_WIRE_201, 17, 17)
connect _WIRE_200.ae_stage2, _T_2722
node _T_2723 = bits(_WIRE_201, 18, 18)
connect _WIRE_200.ae_final, _T_2723
node _T_2724 = bits(_WIRE_201, 19, 19)
connect _WIRE_200.ae_ptw, _T_2724
node _T_2725 = bits(_WIRE_201, 20, 20)
connect _WIRE_200.g, _T_2725
node _T_2726 = bits(_WIRE_201, 21, 21)
connect _WIRE_200.u, _T_2726
node _T_2727 = bits(_WIRE_201, 41, 22)
connect _WIRE_200.ppn, _T_2727
wire _WIRE_202 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_203 : UInt<42>
connect _WIRE_203, sectored_entries[0][6].data[1]
node _T_2728 = bits(_WIRE_203, 0, 0)
connect _WIRE_202.fragmented_superpage, _T_2728
node _T_2729 = bits(_WIRE_203, 1, 1)
connect _WIRE_202.c, _T_2729
node _T_2730 = bits(_WIRE_203, 2, 2)
connect _WIRE_202.eff, _T_2730
node _T_2731 = bits(_WIRE_203, 3, 3)
connect _WIRE_202.paa, _T_2731
node _T_2732 = bits(_WIRE_203, 4, 4)
connect _WIRE_202.pal, _T_2732
node _T_2733 = bits(_WIRE_203, 5, 5)
connect _WIRE_202.ppp, _T_2733
node _T_2734 = bits(_WIRE_203, 6, 6)
connect _WIRE_202.pr, _T_2734
node _T_2735 = bits(_WIRE_203, 7, 7)
connect _WIRE_202.px, _T_2735
node _T_2736 = bits(_WIRE_203, 8, 8)
connect _WIRE_202.pw, _T_2736
node _T_2737 = bits(_WIRE_203, 9, 9)
connect _WIRE_202.hr, _T_2737
node _T_2738 = bits(_WIRE_203, 10, 10)
connect _WIRE_202.hx, _T_2738
node _T_2739 = bits(_WIRE_203, 11, 11)
connect _WIRE_202.hw, _T_2739
node _T_2740 = bits(_WIRE_203, 12, 12)
connect _WIRE_202.sr, _T_2740
node _T_2741 = bits(_WIRE_203, 13, 13)
connect _WIRE_202.sx, _T_2741
node _T_2742 = bits(_WIRE_203, 14, 14)
connect _WIRE_202.sw, _T_2742
node _T_2743 = bits(_WIRE_203, 15, 15)
connect _WIRE_202.gf, _T_2743
node _T_2744 = bits(_WIRE_203, 16, 16)
connect _WIRE_202.pf, _T_2744
node _T_2745 = bits(_WIRE_203, 17, 17)
connect _WIRE_202.ae_stage2, _T_2745
node _T_2746 = bits(_WIRE_203, 18, 18)
connect _WIRE_202.ae_final, _T_2746
node _T_2747 = bits(_WIRE_203, 19, 19)
connect _WIRE_202.ae_ptw, _T_2747
node _T_2748 = bits(_WIRE_203, 20, 20)
connect _WIRE_202.g, _T_2748
node _T_2749 = bits(_WIRE_203, 21, 21)
connect _WIRE_202.u, _T_2749
node _T_2750 = bits(_WIRE_203, 41, 22)
connect _WIRE_202.ppn, _T_2750
wire _WIRE_204 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_205 : UInt<42>
connect _WIRE_205, sectored_entries[0][6].data[2]
node _T_2751 = bits(_WIRE_205, 0, 0)
connect _WIRE_204.fragmented_superpage, _T_2751
node _T_2752 = bits(_WIRE_205, 1, 1)
connect _WIRE_204.c, _T_2752
node _T_2753 = bits(_WIRE_205, 2, 2)
connect _WIRE_204.eff, _T_2753
node _T_2754 = bits(_WIRE_205, 3, 3)
connect _WIRE_204.paa, _T_2754
node _T_2755 = bits(_WIRE_205, 4, 4)
connect _WIRE_204.pal, _T_2755
node _T_2756 = bits(_WIRE_205, 5, 5)
connect _WIRE_204.ppp, _T_2756
node _T_2757 = bits(_WIRE_205, 6, 6)
connect _WIRE_204.pr, _T_2757
node _T_2758 = bits(_WIRE_205, 7, 7)
connect _WIRE_204.px, _T_2758
node _T_2759 = bits(_WIRE_205, 8, 8)
connect _WIRE_204.pw, _T_2759
node _T_2760 = bits(_WIRE_205, 9, 9)
connect _WIRE_204.hr, _T_2760
node _T_2761 = bits(_WIRE_205, 10, 10)
connect _WIRE_204.hx, _T_2761
node _T_2762 = bits(_WIRE_205, 11, 11)
connect _WIRE_204.hw, _T_2762
node _T_2763 = bits(_WIRE_205, 12, 12)
connect _WIRE_204.sr, _T_2763
node _T_2764 = bits(_WIRE_205, 13, 13)
connect _WIRE_204.sx, _T_2764
node _T_2765 = bits(_WIRE_205, 14, 14)
connect _WIRE_204.sw, _T_2765
node _T_2766 = bits(_WIRE_205, 15, 15)
connect _WIRE_204.gf, _T_2766
node _T_2767 = bits(_WIRE_205, 16, 16)
connect _WIRE_204.pf, _T_2767
node _T_2768 = bits(_WIRE_205, 17, 17)
connect _WIRE_204.ae_stage2, _T_2768
node _T_2769 = bits(_WIRE_205, 18, 18)
connect _WIRE_204.ae_final, _T_2769
node _T_2770 = bits(_WIRE_205, 19, 19)
connect _WIRE_204.ae_ptw, _T_2770
node _T_2771 = bits(_WIRE_205, 20, 20)
connect _WIRE_204.g, _T_2771
node _T_2772 = bits(_WIRE_205, 21, 21)
connect _WIRE_204.u, _T_2772
node _T_2773 = bits(_WIRE_205, 41, 22)
connect _WIRE_204.ppn, _T_2773
wire _WIRE_206 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_207 : UInt<42>
connect _WIRE_207, sectored_entries[0][6].data[3]
node _T_2774 = bits(_WIRE_207, 0, 0)
connect _WIRE_206.fragmented_superpage, _T_2774
node _T_2775 = bits(_WIRE_207, 1, 1)
connect _WIRE_206.c, _T_2775
node _T_2776 = bits(_WIRE_207, 2, 2)
connect _WIRE_206.eff, _T_2776
node _T_2777 = bits(_WIRE_207, 3, 3)
connect _WIRE_206.paa, _T_2777
node _T_2778 = bits(_WIRE_207, 4, 4)
connect _WIRE_206.pal, _T_2778
node _T_2779 = bits(_WIRE_207, 5, 5)
connect _WIRE_206.ppp, _T_2779
node _T_2780 = bits(_WIRE_207, 6, 6)
connect _WIRE_206.pr, _T_2780
node _T_2781 = bits(_WIRE_207, 7, 7)
connect _WIRE_206.px, _T_2781
node _T_2782 = bits(_WIRE_207, 8, 8)
connect _WIRE_206.pw, _T_2782
node _T_2783 = bits(_WIRE_207, 9, 9)
connect _WIRE_206.hr, _T_2783
node _T_2784 = bits(_WIRE_207, 10, 10)
connect _WIRE_206.hx, _T_2784
node _T_2785 = bits(_WIRE_207, 11, 11)
connect _WIRE_206.hw, _T_2785
node _T_2786 = bits(_WIRE_207, 12, 12)
connect _WIRE_206.sr, _T_2786
node _T_2787 = bits(_WIRE_207, 13, 13)
connect _WIRE_206.sx, _T_2787
node _T_2788 = bits(_WIRE_207, 14, 14)
connect _WIRE_206.sw, _T_2788
node _T_2789 = bits(_WIRE_207, 15, 15)
connect _WIRE_206.gf, _T_2789
node _T_2790 = bits(_WIRE_207, 16, 16)
connect _WIRE_206.pf, _T_2790
node _T_2791 = bits(_WIRE_207, 17, 17)
connect _WIRE_206.ae_stage2, _T_2791
node _T_2792 = bits(_WIRE_207, 18, 18)
connect _WIRE_206.ae_final, _T_2792
node _T_2793 = bits(_WIRE_207, 19, 19)
connect _WIRE_206.ae_ptw, _T_2793
node _T_2794 = bits(_WIRE_207, 20, 20)
connect _WIRE_206.g, _T_2794
node _T_2795 = bits(_WIRE_207, 21, 21)
connect _WIRE_206.u, _T_2795
node _T_2796 = bits(_WIRE_207, 41, 22)
connect _WIRE_206.ppn, _T_2796
node _T_2797 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2798 = and(_T_2797, _WIRE_200.fragmented_superpage)
when _T_2798 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
node _T_2799 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2800 = and(_T_2799, _WIRE_202.fragmented_superpage)
when _T_2800 :
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
node _T_2801 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2802 = and(_T_2801, _WIRE_204.fragmented_superpage)
when _T_2802 :
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
node _T_2803 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2804 = and(_T_2803, _WIRE_206.fragmented_superpage)
when _T_2804 :
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
else :
node _T_2805 = eq(hg_6, UInt<1>(0h0))
node _T_2806 = and(_T_2805, io.sfence.bits.rs2)
when _T_2806 :
wire _WIRE_208 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_209 : UInt<42>
connect _WIRE_209, sectored_entries[0][6].data[0]
node _T_2807 = bits(_WIRE_209, 0, 0)
connect _WIRE_208.fragmented_superpage, _T_2807
node _T_2808 = bits(_WIRE_209, 1, 1)
connect _WIRE_208.c, _T_2808
node _T_2809 = bits(_WIRE_209, 2, 2)
connect _WIRE_208.eff, _T_2809
node _T_2810 = bits(_WIRE_209, 3, 3)
connect _WIRE_208.paa, _T_2810
node _T_2811 = bits(_WIRE_209, 4, 4)
connect _WIRE_208.pal, _T_2811
node _T_2812 = bits(_WIRE_209, 5, 5)
connect _WIRE_208.ppp, _T_2812
node _T_2813 = bits(_WIRE_209, 6, 6)
connect _WIRE_208.pr, _T_2813
node _T_2814 = bits(_WIRE_209, 7, 7)
connect _WIRE_208.px, _T_2814
node _T_2815 = bits(_WIRE_209, 8, 8)
connect _WIRE_208.pw, _T_2815
node _T_2816 = bits(_WIRE_209, 9, 9)
connect _WIRE_208.hr, _T_2816
node _T_2817 = bits(_WIRE_209, 10, 10)
connect _WIRE_208.hx, _T_2817
node _T_2818 = bits(_WIRE_209, 11, 11)
connect _WIRE_208.hw, _T_2818
node _T_2819 = bits(_WIRE_209, 12, 12)
connect _WIRE_208.sr, _T_2819
node _T_2820 = bits(_WIRE_209, 13, 13)
connect _WIRE_208.sx, _T_2820
node _T_2821 = bits(_WIRE_209, 14, 14)
connect _WIRE_208.sw, _T_2821
node _T_2822 = bits(_WIRE_209, 15, 15)
connect _WIRE_208.gf, _T_2822
node _T_2823 = bits(_WIRE_209, 16, 16)
connect _WIRE_208.pf, _T_2823
node _T_2824 = bits(_WIRE_209, 17, 17)
connect _WIRE_208.ae_stage2, _T_2824
node _T_2825 = bits(_WIRE_209, 18, 18)
connect _WIRE_208.ae_final, _T_2825
node _T_2826 = bits(_WIRE_209, 19, 19)
connect _WIRE_208.ae_ptw, _T_2826
node _T_2827 = bits(_WIRE_209, 20, 20)
connect _WIRE_208.g, _T_2827
node _T_2828 = bits(_WIRE_209, 21, 21)
connect _WIRE_208.u, _T_2828
node _T_2829 = bits(_WIRE_209, 41, 22)
connect _WIRE_208.ppn, _T_2829
wire _WIRE_210 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_211 : UInt<42>
connect _WIRE_211, sectored_entries[0][6].data[1]
node _T_2830 = bits(_WIRE_211, 0, 0)
connect _WIRE_210.fragmented_superpage, _T_2830
node _T_2831 = bits(_WIRE_211, 1, 1)
connect _WIRE_210.c, _T_2831
node _T_2832 = bits(_WIRE_211, 2, 2)
connect _WIRE_210.eff, _T_2832
node _T_2833 = bits(_WIRE_211, 3, 3)
connect _WIRE_210.paa, _T_2833
node _T_2834 = bits(_WIRE_211, 4, 4)
connect _WIRE_210.pal, _T_2834
node _T_2835 = bits(_WIRE_211, 5, 5)
connect _WIRE_210.ppp, _T_2835
node _T_2836 = bits(_WIRE_211, 6, 6)
connect _WIRE_210.pr, _T_2836
node _T_2837 = bits(_WIRE_211, 7, 7)
connect _WIRE_210.px, _T_2837
node _T_2838 = bits(_WIRE_211, 8, 8)
connect _WIRE_210.pw, _T_2838
node _T_2839 = bits(_WIRE_211, 9, 9)
connect _WIRE_210.hr, _T_2839
node _T_2840 = bits(_WIRE_211, 10, 10)
connect _WIRE_210.hx, _T_2840
node _T_2841 = bits(_WIRE_211, 11, 11)
connect _WIRE_210.hw, _T_2841
node _T_2842 = bits(_WIRE_211, 12, 12)
connect _WIRE_210.sr, _T_2842
node _T_2843 = bits(_WIRE_211, 13, 13)
connect _WIRE_210.sx, _T_2843
node _T_2844 = bits(_WIRE_211, 14, 14)
connect _WIRE_210.sw, _T_2844
node _T_2845 = bits(_WIRE_211, 15, 15)
connect _WIRE_210.gf, _T_2845
node _T_2846 = bits(_WIRE_211, 16, 16)
connect _WIRE_210.pf, _T_2846
node _T_2847 = bits(_WIRE_211, 17, 17)
connect _WIRE_210.ae_stage2, _T_2847
node _T_2848 = bits(_WIRE_211, 18, 18)
connect _WIRE_210.ae_final, _T_2848
node _T_2849 = bits(_WIRE_211, 19, 19)
connect _WIRE_210.ae_ptw, _T_2849
node _T_2850 = bits(_WIRE_211, 20, 20)
connect _WIRE_210.g, _T_2850
node _T_2851 = bits(_WIRE_211, 21, 21)
connect _WIRE_210.u, _T_2851
node _T_2852 = bits(_WIRE_211, 41, 22)
connect _WIRE_210.ppn, _T_2852
wire _WIRE_212 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_213 : UInt<42>
connect _WIRE_213, sectored_entries[0][6].data[2]
node _T_2853 = bits(_WIRE_213, 0, 0)
connect _WIRE_212.fragmented_superpage, _T_2853
node _T_2854 = bits(_WIRE_213, 1, 1)
connect _WIRE_212.c, _T_2854
node _T_2855 = bits(_WIRE_213, 2, 2)
connect _WIRE_212.eff, _T_2855
node _T_2856 = bits(_WIRE_213, 3, 3)
connect _WIRE_212.paa, _T_2856
node _T_2857 = bits(_WIRE_213, 4, 4)
connect _WIRE_212.pal, _T_2857
node _T_2858 = bits(_WIRE_213, 5, 5)
connect _WIRE_212.ppp, _T_2858
node _T_2859 = bits(_WIRE_213, 6, 6)
connect _WIRE_212.pr, _T_2859
node _T_2860 = bits(_WIRE_213, 7, 7)
connect _WIRE_212.px, _T_2860
node _T_2861 = bits(_WIRE_213, 8, 8)
connect _WIRE_212.pw, _T_2861
node _T_2862 = bits(_WIRE_213, 9, 9)
connect _WIRE_212.hr, _T_2862
node _T_2863 = bits(_WIRE_213, 10, 10)
connect _WIRE_212.hx, _T_2863
node _T_2864 = bits(_WIRE_213, 11, 11)
connect _WIRE_212.hw, _T_2864
node _T_2865 = bits(_WIRE_213, 12, 12)
connect _WIRE_212.sr, _T_2865
node _T_2866 = bits(_WIRE_213, 13, 13)
connect _WIRE_212.sx, _T_2866
node _T_2867 = bits(_WIRE_213, 14, 14)
connect _WIRE_212.sw, _T_2867
node _T_2868 = bits(_WIRE_213, 15, 15)
connect _WIRE_212.gf, _T_2868
node _T_2869 = bits(_WIRE_213, 16, 16)
connect _WIRE_212.pf, _T_2869
node _T_2870 = bits(_WIRE_213, 17, 17)
connect _WIRE_212.ae_stage2, _T_2870
node _T_2871 = bits(_WIRE_213, 18, 18)
connect _WIRE_212.ae_final, _T_2871
node _T_2872 = bits(_WIRE_213, 19, 19)
connect _WIRE_212.ae_ptw, _T_2872
node _T_2873 = bits(_WIRE_213, 20, 20)
connect _WIRE_212.g, _T_2873
node _T_2874 = bits(_WIRE_213, 21, 21)
connect _WIRE_212.u, _T_2874
node _T_2875 = bits(_WIRE_213, 41, 22)
connect _WIRE_212.ppn, _T_2875
wire _WIRE_214 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_215 : UInt<42>
connect _WIRE_215, sectored_entries[0][6].data[3]
node _T_2876 = bits(_WIRE_215, 0, 0)
connect _WIRE_214.fragmented_superpage, _T_2876
node _T_2877 = bits(_WIRE_215, 1, 1)
connect _WIRE_214.c, _T_2877
node _T_2878 = bits(_WIRE_215, 2, 2)
connect _WIRE_214.eff, _T_2878
node _T_2879 = bits(_WIRE_215, 3, 3)
connect _WIRE_214.paa, _T_2879
node _T_2880 = bits(_WIRE_215, 4, 4)
connect _WIRE_214.pal, _T_2880
node _T_2881 = bits(_WIRE_215, 5, 5)
connect _WIRE_214.ppp, _T_2881
node _T_2882 = bits(_WIRE_215, 6, 6)
connect _WIRE_214.pr, _T_2882
node _T_2883 = bits(_WIRE_215, 7, 7)
connect _WIRE_214.px, _T_2883
node _T_2884 = bits(_WIRE_215, 8, 8)
connect _WIRE_214.pw, _T_2884
node _T_2885 = bits(_WIRE_215, 9, 9)
connect _WIRE_214.hr, _T_2885
node _T_2886 = bits(_WIRE_215, 10, 10)
connect _WIRE_214.hx, _T_2886
node _T_2887 = bits(_WIRE_215, 11, 11)
connect _WIRE_214.hw, _T_2887
node _T_2888 = bits(_WIRE_215, 12, 12)
connect _WIRE_214.sr, _T_2888
node _T_2889 = bits(_WIRE_215, 13, 13)
connect _WIRE_214.sx, _T_2889
node _T_2890 = bits(_WIRE_215, 14, 14)
connect _WIRE_214.sw, _T_2890
node _T_2891 = bits(_WIRE_215, 15, 15)
connect _WIRE_214.gf, _T_2891
node _T_2892 = bits(_WIRE_215, 16, 16)
connect _WIRE_214.pf, _T_2892
node _T_2893 = bits(_WIRE_215, 17, 17)
connect _WIRE_214.ae_stage2, _T_2893
node _T_2894 = bits(_WIRE_215, 18, 18)
connect _WIRE_214.ae_final, _T_2894
node _T_2895 = bits(_WIRE_215, 19, 19)
connect _WIRE_214.ae_ptw, _T_2895
node _T_2896 = bits(_WIRE_215, 20, 20)
connect _WIRE_214.g, _T_2896
node _T_2897 = bits(_WIRE_215, 21, 21)
connect _WIRE_214.u, _T_2897
node _T_2898 = bits(_WIRE_215, 41, 22)
connect _WIRE_214.ppn, _T_2898
node _T_2899 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2900 = eq(_WIRE_208.g, UInt<1>(0h0))
node _T_2901 = and(_T_2899, _T_2900)
when _T_2901 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
node _T_2902 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2903 = eq(_WIRE_210.g, UInt<1>(0h0))
node _T_2904 = and(_T_2902, _T_2903)
when _T_2904 :
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
node _T_2905 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2906 = eq(_WIRE_212.g, UInt<1>(0h0))
node _T_2907 = and(_T_2905, _T_2906)
when _T_2907 :
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
node _T_2908 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2909 = eq(_WIRE_214.g, UInt<1>(0h0))
node _T_2910 = and(_T_2908, _T_2909)
when _T_2910 :
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
else :
node _T_2911 = or(hv_6, hg_6)
wire _WIRE_216 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_217 : UInt<42>
connect _WIRE_217, sectored_entries[0][6].data[0]
node _T_2912 = bits(_WIRE_217, 0, 0)
connect _WIRE_216.fragmented_superpage, _T_2912
node _T_2913 = bits(_WIRE_217, 1, 1)
connect _WIRE_216.c, _T_2913
node _T_2914 = bits(_WIRE_217, 2, 2)
connect _WIRE_216.eff, _T_2914
node _T_2915 = bits(_WIRE_217, 3, 3)
connect _WIRE_216.paa, _T_2915
node _T_2916 = bits(_WIRE_217, 4, 4)
connect _WIRE_216.pal, _T_2916
node _T_2917 = bits(_WIRE_217, 5, 5)
connect _WIRE_216.ppp, _T_2917
node _T_2918 = bits(_WIRE_217, 6, 6)
connect _WIRE_216.pr, _T_2918
node _T_2919 = bits(_WIRE_217, 7, 7)
connect _WIRE_216.px, _T_2919
node _T_2920 = bits(_WIRE_217, 8, 8)
connect _WIRE_216.pw, _T_2920
node _T_2921 = bits(_WIRE_217, 9, 9)
connect _WIRE_216.hr, _T_2921
node _T_2922 = bits(_WIRE_217, 10, 10)
connect _WIRE_216.hx, _T_2922
node _T_2923 = bits(_WIRE_217, 11, 11)
connect _WIRE_216.hw, _T_2923
node _T_2924 = bits(_WIRE_217, 12, 12)
connect _WIRE_216.sr, _T_2924
node _T_2925 = bits(_WIRE_217, 13, 13)
connect _WIRE_216.sx, _T_2925
node _T_2926 = bits(_WIRE_217, 14, 14)
connect _WIRE_216.sw, _T_2926
node _T_2927 = bits(_WIRE_217, 15, 15)
connect _WIRE_216.gf, _T_2927
node _T_2928 = bits(_WIRE_217, 16, 16)
connect _WIRE_216.pf, _T_2928
node _T_2929 = bits(_WIRE_217, 17, 17)
connect _WIRE_216.ae_stage2, _T_2929
node _T_2930 = bits(_WIRE_217, 18, 18)
connect _WIRE_216.ae_final, _T_2930
node _T_2931 = bits(_WIRE_217, 19, 19)
connect _WIRE_216.ae_ptw, _T_2931
node _T_2932 = bits(_WIRE_217, 20, 20)
connect _WIRE_216.g, _T_2932
node _T_2933 = bits(_WIRE_217, 21, 21)
connect _WIRE_216.u, _T_2933
node _T_2934 = bits(_WIRE_217, 41, 22)
connect _WIRE_216.ppn, _T_2934
wire _WIRE_218 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_219 : UInt<42>
connect _WIRE_219, sectored_entries[0][6].data[1]
node _T_2935 = bits(_WIRE_219, 0, 0)
connect _WIRE_218.fragmented_superpage, _T_2935
node _T_2936 = bits(_WIRE_219, 1, 1)
connect _WIRE_218.c, _T_2936
node _T_2937 = bits(_WIRE_219, 2, 2)
connect _WIRE_218.eff, _T_2937
node _T_2938 = bits(_WIRE_219, 3, 3)
connect _WIRE_218.paa, _T_2938
node _T_2939 = bits(_WIRE_219, 4, 4)
connect _WIRE_218.pal, _T_2939
node _T_2940 = bits(_WIRE_219, 5, 5)
connect _WIRE_218.ppp, _T_2940
node _T_2941 = bits(_WIRE_219, 6, 6)
connect _WIRE_218.pr, _T_2941
node _T_2942 = bits(_WIRE_219, 7, 7)
connect _WIRE_218.px, _T_2942
node _T_2943 = bits(_WIRE_219, 8, 8)
connect _WIRE_218.pw, _T_2943
node _T_2944 = bits(_WIRE_219, 9, 9)
connect _WIRE_218.hr, _T_2944
node _T_2945 = bits(_WIRE_219, 10, 10)
connect _WIRE_218.hx, _T_2945
node _T_2946 = bits(_WIRE_219, 11, 11)
connect _WIRE_218.hw, _T_2946
node _T_2947 = bits(_WIRE_219, 12, 12)
connect _WIRE_218.sr, _T_2947
node _T_2948 = bits(_WIRE_219, 13, 13)
connect _WIRE_218.sx, _T_2948
node _T_2949 = bits(_WIRE_219, 14, 14)
connect _WIRE_218.sw, _T_2949
node _T_2950 = bits(_WIRE_219, 15, 15)
connect _WIRE_218.gf, _T_2950
node _T_2951 = bits(_WIRE_219, 16, 16)
connect _WIRE_218.pf, _T_2951
node _T_2952 = bits(_WIRE_219, 17, 17)
connect _WIRE_218.ae_stage2, _T_2952
node _T_2953 = bits(_WIRE_219, 18, 18)
connect _WIRE_218.ae_final, _T_2953
node _T_2954 = bits(_WIRE_219, 19, 19)
connect _WIRE_218.ae_ptw, _T_2954
node _T_2955 = bits(_WIRE_219, 20, 20)
connect _WIRE_218.g, _T_2955
node _T_2956 = bits(_WIRE_219, 21, 21)
connect _WIRE_218.u, _T_2956
node _T_2957 = bits(_WIRE_219, 41, 22)
connect _WIRE_218.ppn, _T_2957
wire _WIRE_220 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_221 : UInt<42>
connect _WIRE_221, sectored_entries[0][6].data[2]
node _T_2958 = bits(_WIRE_221, 0, 0)
connect _WIRE_220.fragmented_superpage, _T_2958
node _T_2959 = bits(_WIRE_221, 1, 1)
connect _WIRE_220.c, _T_2959
node _T_2960 = bits(_WIRE_221, 2, 2)
connect _WIRE_220.eff, _T_2960
node _T_2961 = bits(_WIRE_221, 3, 3)
connect _WIRE_220.paa, _T_2961
node _T_2962 = bits(_WIRE_221, 4, 4)
connect _WIRE_220.pal, _T_2962
node _T_2963 = bits(_WIRE_221, 5, 5)
connect _WIRE_220.ppp, _T_2963
node _T_2964 = bits(_WIRE_221, 6, 6)
connect _WIRE_220.pr, _T_2964
node _T_2965 = bits(_WIRE_221, 7, 7)
connect _WIRE_220.px, _T_2965
node _T_2966 = bits(_WIRE_221, 8, 8)
connect _WIRE_220.pw, _T_2966
node _T_2967 = bits(_WIRE_221, 9, 9)
connect _WIRE_220.hr, _T_2967
node _T_2968 = bits(_WIRE_221, 10, 10)
connect _WIRE_220.hx, _T_2968
node _T_2969 = bits(_WIRE_221, 11, 11)
connect _WIRE_220.hw, _T_2969
node _T_2970 = bits(_WIRE_221, 12, 12)
connect _WIRE_220.sr, _T_2970
node _T_2971 = bits(_WIRE_221, 13, 13)
connect _WIRE_220.sx, _T_2971
node _T_2972 = bits(_WIRE_221, 14, 14)
connect _WIRE_220.sw, _T_2972
node _T_2973 = bits(_WIRE_221, 15, 15)
connect _WIRE_220.gf, _T_2973
node _T_2974 = bits(_WIRE_221, 16, 16)
connect _WIRE_220.pf, _T_2974
node _T_2975 = bits(_WIRE_221, 17, 17)
connect _WIRE_220.ae_stage2, _T_2975
node _T_2976 = bits(_WIRE_221, 18, 18)
connect _WIRE_220.ae_final, _T_2976
node _T_2977 = bits(_WIRE_221, 19, 19)
connect _WIRE_220.ae_ptw, _T_2977
node _T_2978 = bits(_WIRE_221, 20, 20)
connect _WIRE_220.g, _T_2978
node _T_2979 = bits(_WIRE_221, 21, 21)
connect _WIRE_220.u, _T_2979
node _T_2980 = bits(_WIRE_221, 41, 22)
connect _WIRE_220.ppn, _T_2980
wire _WIRE_222 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_223 : UInt<42>
connect _WIRE_223, sectored_entries[0][6].data[3]
node _T_2981 = bits(_WIRE_223, 0, 0)
connect _WIRE_222.fragmented_superpage, _T_2981
node _T_2982 = bits(_WIRE_223, 1, 1)
connect _WIRE_222.c, _T_2982
node _T_2983 = bits(_WIRE_223, 2, 2)
connect _WIRE_222.eff, _T_2983
node _T_2984 = bits(_WIRE_223, 3, 3)
connect _WIRE_222.paa, _T_2984
node _T_2985 = bits(_WIRE_223, 4, 4)
connect _WIRE_222.pal, _T_2985
node _T_2986 = bits(_WIRE_223, 5, 5)
connect _WIRE_222.ppp, _T_2986
node _T_2987 = bits(_WIRE_223, 6, 6)
connect _WIRE_222.pr, _T_2987
node _T_2988 = bits(_WIRE_223, 7, 7)
connect _WIRE_222.px, _T_2988
node _T_2989 = bits(_WIRE_223, 8, 8)
connect _WIRE_222.pw, _T_2989
node _T_2990 = bits(_WIRE_223, 9, 9)
connect _WIRE_222.hr, _T_2990
node _T_2991 = bits(_WIRE_223, 10, 10)
connect _WIRE_222.hx, _T_2991
node _T_2992 = bits(_WIRE_223, 11, 11)
connect _WIRE_222.hw, _T_2992
node _T_2993 = bits(_WIRE_223, 12, 12)
connect _WIRE_222.sr, _T_2993
node _T_2994 = bits(_WIRE_223, 13, 13)
connect _WIRE_222.sx, _T_2994
node _T_2995 = bits(_WIRE_223, 14, 14)
connect _WIRE_222.sw, _T_2995
node _T_2996 = bits(_WIRE_223, 15, 15)
connect _WIRE_222.gf, _T_2996
node _T_2997 = bits(_WIRE_223, 16, 16)
connect _WIRE_222.pf, _T_2997
node _T_2998 = bits(_WIRE_223, 17, 17)
connect _WIRE_222.ae_stage2, _T_2998
node _T_2999 = bits(_WIRE_223, 18, 18)
connect _WIRE_222.ae_final, _T_2999
node _T_3000 = bits(_WIRE_223, 19, 19)
connect _WIRE_222.ae_ptw, _T_3000
node _T_3001 = bits(_WIRE_223, 20, 20)
connect _WIRE_222.g, _T_3001
node _T_3002 = bits(_WIRE_223, 21, 21)
connect _WIRE_222.u, _T_3002
node _T_3003 = bits(_WIRE_223, 41, 22)
connect _WIRE_222.ppn, _T_3003
node _T_3004 = eq(sectored_entries[0][6].tag_v, _T_2911)
when _T_3004 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
node _T_3005 = eq(sectored_entries[0][6].tag_v, _T_2911)
when _T_3005 :
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
node _T_3006 = eq(sectored_entries[0][6].tag_v, _T_2911)
when _T_3006 :
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
node _T_3007 = eq(sectored_entries[0][6].tag_v, _T_2911)
when _T_3007 :
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
node hv_7 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_7 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3008 = eq(hg_7, UInt<1>(0h0))
node _T_3009 = and(_T_3008, io.sfence.bits.rs1)
when _T_3009 :
node _T_3010 = xor(sectored_entries[0][7].tag_vpn, vpn)
node _T_3011 = shr(_T_3010, 2)
node _T_3012 = eq(_T_3011, UInt<1>(0h0))
node _T_3013 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3014 = and(_T_3012, _T_3013)
when _T_3014 :
wire _WIRE_224 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_225 : UInt<42>
connect _WIRE_225, sectored_entries[0][7].data[0]
node _T_3015 = bits(_WIRE_225, 0, 0)
connect _WIRE_224.fragmented_superpage, _T_3015
node _T_3016 = bits(_WIRE_225, 1, 1)
connect _WIRE_224.c, _T_3016
node _T_3017 = bits(_WIRE_225, 2, 2)
connect _WIRE_224.eff, _T_3017
node _T_3018 = bits(_WIRE_225, 3, 3)
connect _WIRE_224.paa, _T_3018
node _T_3019 = bits(_WIRE_225, 4, 4)
connect _WIRE_224.pal, _T_3019
node _T_3020 = bits(_WIRE_225, 5, 5)
connect _WIRE_224.ppp, _T_3020
node _T_3021 = bits(_WIRE_225, 6, 6)
connect _WIRE_224.pr, _T_3021
node _T_3022 = bits(_WIRE_225, 7, 7)
connect _WIRE_224.px, _T_3022
node _T_3023 = bits(_WIRE_225, 8, 8)
connect _WIRE_224.pw, _T_3023
node _T_3024 = bits(_WIRE_225, 9, 9)
connect _WIRE_224.hr, _T_3024
node _T_3025 = bits(_WIRE_225, 10, 10)
connect _WIRE_224.hx, _T_3025
node _T_3026 = bits(_WIRE_225, 11, 11)
connect _WIRE_224.hw, _T_3026
node _T_3027 = bits(_WIRE_225, 12, 12)
connect _WIRE_224.sr, _T_3027
node _T_3028 = bits(_WIRE_225, 13, 13)
connect _WIRE_224.sx, _T_3028
node _T_3029 = bits(_WIRE_225, 14, 14)
connect _WIRE_224.sw, _T_3029
node _T_3030 = bits(_WIRE_225, 15, 15)
connect _WIRE_224.gf, _T_3030
node _T_3031 = bits(_WIRE_225, 16, 16)
connect _WIRE_224.pf, _T_3031
node _T_3032 = bits(_WIRE_225, 17, 17)
connect _WIRE_224.ae_stage2, _T_3032
node _T_3033 = bits(_WIRE_225, 18, 18)
connect _WIRE_224.ae_final, _T_3033
node _T_3034 = bits(_WIRE_225, 19, 19)
connect _WIRE_224.ae_ptw, _T_3034
node _T_3035 = bits(_WIRE_225, 20, 20)
connect _WIRE_224.g, _T_3035
node _T_3036 = bits(_WIRE_225, 21, 21)
connect _WIRE_224.u, _T_3036
node _T_3037 = bits(_WIRE_225, 41, 22)
connect _WIRE_224.ppn, _T_3037
wire _WIRE_226 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_227 : UInt<42>
connect _WIRE_227, sectored_entries[0][7].data[1]
node _T_3038 = bits(_WIRE_227, 0, 0)
connect _WIRE_226.fragmented_superpage, _T_3038
node _T_3039 = bits(_WIRE_227, 1, 1)
connect _WIRE_226.c, _T_3039
node _T_3040 = bits(_WIRE_227, 2, 2)
connect _WIRE_226.eff, _T_3040
node _T_3041 = bits(_WIRE_227, 3, 3)
connect _WIRE_226.paa, _T_3041
node _T_3042 = bits(_WIRE_227, 4, 4)
connect _WIRE_226.pal, _T_3042
node _T_3043 = bits(_WIRE_227, 5, 5)
connect _WIRE_226.ppp, _T_3043
node _T_3044 = bits(_WIRE_227, 6, 6)
connect _WIRE_226.pr, _T_3044
node _T_3045 = bits(_WIRE_227, 7, 7)
connect _WIRE_226.px, _T_3045
node _T_3046 = bits(_WIRE_227, 8, 8)
connect _WIRE_226.pw, _T_3046
node _T_3047 = bits(_WIRE_227, 9, 9)
connect _WIRE_226.hr, _T_3047
node _T_3048 = bits(_WIRE_227, 10, 10)
connect _WIRE_226.hx, _T_3048
node _T_3049 = bits(_WIRE_227, 11, 11)
connect _WIRE_226.hw, _T_3049
node _T_3050 = bits(_WIRE_227, 12, 12)
connect _WIRE_226.sr, _T_3050
node _T_3051 = bits(_WIRE_227, 13, 13)
connect _WIRE_226.sx, _T_3051
node _T_3052 = bits(_WIRE_227, 14, 14)
connect _WIRE_226.sw, _T_3052
node _T_3053 = bits(_WIRE_227, 15, 15)
connect _WIRE_226.gf, _T_3053
node _T_3054 = bits(_WIRE_227, 16, 16)
connect _WIRE_226.pf, _T_3054
node _T_3055 = bits(_WIRE_227, 17, 17)
connect _WIRE_226.ae_stage2, _T_3055
node _T_3056 = bits(_WIRE_227, 18, 18)
connect _WIRE_226.ae_final, _T_3056
node _T_3057 = bits(_WIRE_227, 19, 19)
connect _WIRE_226.ae_ptw, _T_3057
node _T_3058 = bits(_WIRE_227, 20, 20)
connect _WIRE_226.g, _T_3058
node _T_3059 = bits(_WIRE_227, 21, 21)
connect _WIRE_226.u, _T_3059
node _T_3060 = bits(_WIRE_227, 41, 22)
connect _WIRE_226.ppn, _T_3060
wire _WIRE_228 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_229 : UInt<42>
connect _WIRE_229, sectored_entries[0][7].data[2]
node _T_3061 = bits(_WIRE_229, 0, 0)
connect _WIRE_228.fragmented_superpage, _T_3061
node _T_3062 = bits(_WIRE_229, 1, 1)
connect _WIRE_228.c, _T_3062
node _T_3063 = bits(_WIRE_229, 2, 2)
connect _WIRE_228.eff, _T_3063
node _T_3064 = bits(_WIRE_229, 3, 3)
connect _WIRE_228.paa, _T_3064
node _T_3065 = bits(_WIRE_229, 4, 4)
connect _WIRE_228.pal, _T_3065
node _T_3066 = bits(_WIRE_229, 5, 5)
connect _WIRE_228.ppp, _T_3066
node _T_3067 = bits(_WIRE_229, 6, 6)
connect _WIRE_228.pr, _T_3067
node _T_3068 = bits(_WIRE_229, 7, 7)
connect _WIRE_228.px, _T_3068
node _T_3069 = bits(_WIRE_229, 8, 8)
connect _WIRE_228.pw, _T_3069
node _T_3070 = bits(_WIRE_229, 9, 9)
connect _WIRE_228.hr, _T_3070
node _T_3071 = bits(_WIRE_229, 10, 10)
connect _WIRE_228.hx, _T_3071
node _T_3072 = bits(_WIRE_229, 11, 11)
connect _WIRE_228.hw, _T_3072
node _T_3073 = bits(_WIRE_229, 12, 12)
connect _WIRE_228.sr, _T_3073
node _T_3074 = bits(_WIRE_229, 13, 13)
connect _WIRE_228.sx, _T_3074
node _T_3075 = bits(_WIRE_229, 14, 14)
connect _WIRE_228.sw, _T_3075
node _T_3076 = bits(_WIRE_229, 15, 15)
connect _WIRE_228.gf, _T_3076
node _T_3077 = bits(_WIRE_229, 16, 16)
connect _WIRE_228.pf, _T_3077
node _T_3078 = bits(_WIRE_229, 17, 17)
connect _WIRE_228.ae_stage2, _T_3078
node _T_3079 = bits(_WIRE_229, 18, 18)
connect _WIRE_228.ae_final, _T_3079
node _T_3080 = bits(_WIRE_229, 19, 19)
connect _WIRE_228.ae_ptw, _T_3080
node _T_3081 = bits(_WIRE_229, 20, 20)
connect _WIRE_228.g, _T_3081
node _T_3082 = bits(_WIRE_229, 21, 21)
connect _WIRE_228.u, _T_3082
node _T_3083 = bits(_WIRE_229, 41, 22)
connect _WIRE_228.ppn, _T_3083
wire _WIRE_230 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_231 : UInt<42>
connect _WIRE_231, sectored_entries[0][7].data[3]
node _T_3084 = bits(_WIRE_231, 0, 0)
connect _WIRE_230.fragmented_superpage, _T_3084
node _T_3085 = bits(_WIRE_231, 1, 1)
connect _WIRE_230.c, _T_3085
node _T_3086 = bits(_WIRE_231, 2, 2)
connect _WIRE_230.eff, _T_3086
node _T_3087 = bits(_WIRE_231, 3, 3)
connect _WIRE_230.paa, _T_3087
node _T_3088 = bits(_WIRE_231, 4, 4)
connect _WIRE_230.pal, _T_3088
node _T_3089 = bits(_WIRE_231, 5, 5)
connect _WIRE_230.ppp, _T_3089
node _T_3090 = bits(_WIRE_231, 6, 6)
connect _WIRE_230.pr, _T_3090
node _T_3091 = bits(_WIRE_231, 7, 7)
connect _WIRE_230.px, _T_3091
node _T_3092 = bits(_WIRE_231, 8, 8)
connect _WIRE_230.pw, _T_3092
node _T_3093 = bits(_WIRE_231, 9, 9)
connect _WIRE_230.hr, _T_3093
node _T_3094 = bits(_WIRE_231, 10, 10)
connect _WIRE_230.hx, _T_3094
node _T_3095 = bits(_WIRE_231, 11, 11)
connect _WIRE_230.hw, _T_3095
node _T_3096 = bits(_WIRE_231, 12, 12)
connect _WIRE_230.sr, _T_3096
node _T_3097 = bits(_WIRE_231, 13, 13)
connect _WIRE_230.sx, _T_3097
node _T_3098 = bits(_WIRE_231, 14, 14)
connect _WIRE_230.sw, _T_3098
node _T_3099 = bits(_WIRE_231, 15, 15)
connect _WIRE_230.gf, _T_3099
node _T_3100 = bits(_WIRE_231, 16, 16)
connect _WIRE_230.pf, _T_3100
node _T_3101 = bits(_WIRE_231, 17, 17)
connect _WIRE_230.ae_stage2, _T_3101
node _T_3102 = bits(_WIRE_231, 18, 18)
connect _WIRE_230.ae_final, _T_3102
node _T_3103 = bits(_WIRE_231, 19, 19)
connect _WIRE_230.ae_ptw, _T_3103
node _T_3104 = bits(_WIRE_231, 20, 20)
connect _WIRE_230.g, _T_3104
node _T_3105 = bits(_WIRE_231, 21, 21)
connect _WIRE_230.u, _T_3105
node _T_3106 = bits(_WIRE_231, 41, 22)
connect _WIRE_230.ppn, _T_3106
node _T_3107 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3108 = bits(vpn, 1, 0)
node _T_3109 = eq(UInt<1>(0h0), _T_3108)
node _T_3110 = and(_T_3107, _T_3109)
when _T_3110 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
node _T_3111 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3112 = bits(vpn, 1, 0)
node _T_3113 = eq(UInt<1>(0h1), _T_3112)
node _T_3114 = and(_T_3111, _T_3113)
when _T_3114 :
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
node _T_3115 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3116 = bits(vpn, 1, 0)
node _T_3117 = eq(UInt<2>(0h2), _T_3116)
node _T_3118 = and(_T_3115, _T_3117)
when _T_3118 :
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
node _T_3119 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3120 = bits(vpn, 1, 0)
node _T_3121 = eq(UInt<2>(0h3), _T_3120)
node _T_3122 = and(_T_3119, _T_3121)
when _T_3122 :
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
node _T_3123 = xor(sectored_entries[0][7].tag_vpn, vpn)
node _T_3124 = shr(_T_3123, 18)
node _T_3125 = eq(_T_3124, UInt<1>(0h0))
when _T_3125 :
wire _WIRE_232 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_233 : UInt<42>
connect _WIRE_233, sectored_entries[0][7].data[0]
node _T_3126 = bits(_WIRE_233, 0, 0)
connect _WIRE_232.fragmented_superpage, _T_3126
node _T_3127 = bits(_WIRE_233, 1, 1)
connect _WIRE_232.c, _T_3127
node _T_3128 = bits(_WIRE_233, 2, 2)
connect _WIRE_232.eff, _T_3128
node _T_3129 = bits(_WIRE_233, 3, 3)
connect _WIRE_232.paa, _T_3129
node _T_3130 = bits(_WIRE_233, 4, 4)
connect _WIRE_232.pal, _T_3130
node _T_3131 = bits(_WIRE_233, 5, 5)
connect _WIRE_232.ppp, _T_3131
node _T_3132 = bits(_WIRE_233, 6, 6)
connect _WIRE_232.pr, _T_3132
node _T_3133 = bits(_WIRE_233, 7, 7)
connect _WIRE_232.px, _T_3133
node _T_3134 = bits(_WIRE_233, 8, 8)
connect _WIRE_232.pw, _T_3134
node _T_3135 = bits(_WIRE_233, 9, 9)
connect _WIRE_232.hr, _T_3135
node _T_3136 = bits(_WIRE_233, 10, 10)
connect _WIRE_232.hx, _T_3136
node _T_3137 = bits(_WIRE_233, 11, 11)
connect _WIRE_232.hw, _T_3137
node _T_3138 = bits(_WIRE_233, 12, 12)
connect _WIRE_232.sr, _T_3138
node _T_3139 = bits(_WIRE_233, 13, 13)
connect _WIRE_232.sx, _T_3139
node _T_3140 = bits(_WIRE_233, 14, 14)
connect _WIRE_232.sw, _T_3140
node _T_3141 = bits(_WIRE_233, 15, 15)
connect _WIRE_232.gf, _T_3141
node _T_3142 = bits(_WIRE_233, 16, 16)
connect _WIRE_232.pf, _T_3142
node _T_3143 = bits(_WIRE_233, 17, 17)
connect _WIRE_232.ae_stage2, _T_3143
node _T_3144 = bits(_WIRE_233, 18, 18)
connect _WIRE_232.ae_final, _T_3144
node _T_3145 = bits(_WIRE_233, 19, 19)
connect _WIRE_232.ae_ptw, _T_3145
node _T_3146 = bits(_WIRE_233, 20, 20)
connect _WIRE_232.g, _T_3146
node _T_3147 = bits(_WIRE_233, 21, 21)
connect _WIRE_232.u, _T_3147
node _T_3148 = bits(_WIRE_233, 41, 22)
connect _WIRE_232.ppn, _T_3148
wire _WIRE_234 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_235 : UInt<42>
connect _WIRE_235, sectored_entries[0][7].data[1]
node _T_3149 = bits(_WIRE_235, 0, 0)
connect _WIRE_234.fragmented_superpage, _T_3149
node _T_3150 = bits(_WIRE_235, 1, 1)
connect _WIRE_234.c, _T_3150
node _T_3151 = bits(_WIRE_235, 2, 2)
connect _WIRE_234.eff, _T_3151
node _T_3152 = bits(_WIRE_235, 3, 3)
connect _WIRE_234.paa, _T_3152
node _T_3153 = bits(_WIRE_235, 4, 4)
connect _WIRE_234.pal, _T_3153
node _T_3154 = bits(_WIRE_235, 5, 5)
connect _WIRE_234.ppp, _T_3154
node _T_3155 = bits(_WIRE_235, 6, 6)
connect _WIRE_234.pr, _T_3155
node _T_3156 = bits(_WIRE_235, 7, 7)
connect _WIRE_234.px, _T_3156
node _T_3157 = bits(_WIRE_235, 8, 8)
connect _WIRE_234.pw, _T_3157
node _T_3158 = bits(_WIRE_235, 9, 9)
connect _WIRE_234.hr, _T_3158
node _T_3159 = bits(_WIRE_235, 10, 10)
connect _WIRE_234.hx, _T_3159
node _T_3160 = bits(_WIRE_235, 11, 11)
connect _WIRE_234.hw, _T_3160
node _T_3161 = bits(_WIRE_235, 12, 12)
connect _WIRE_234.sr, _T_3161
node _T_3162 = bits(_WIRE_235, 13, 13)
connect _WIRE_234.sx, _T_3162
node _T_3163 = bits(_WIRE_235, 14, 14)
connect _WIRE_234.sw, _T_3163
node _T_3164 = bits(_WIRE_235, 15, 15)
connect _WIRE_234.gf, _T_3164
node _T_3165 = bits(_WIRE_235, 16, 16)
connect _WIRE_234.pf, _T_3165
node _T_3166 = bits(_WIRE_235, 17, 17)
connect _WIRE_234.ae_stage2, _T_3166
node _T_3167 = bits(_WIRE_235, 18, 18)
connect _WIRE_234.ae_final, _T_3167
node _T_3168 = bits(_WIRE_235, 19, 19)
connect _WIRE_234.ae_ptw, _T_3168
node _T_3169 = bits(_WIRE_235, 20, 20)
connect _WIRE_234.g, _T_3169
node _T_3170 = bits(_WIRE_235, 21, 21)
connect _WIRE_234.u, _T_3170
node _T_3171 = bits(_WIRE_235, 41, 22)
connect _WIRE_234.ppn, _T_3171
wire _WIRE_236 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_237 : UInt<42>
connect _WIRE_237, sectored_entries[0][7].data[2]
node _T_3172 = bits(_WIRE_237, 0, 0)
connect _WIRE_236.fragmented_superpage, _T_3172
node _T_3173 = bits(_WIRE_237, 1, 1)
connect _WIRE_236.c, _T_3173
node _T_3174 = bits(_WIRE_237, 2, 2)
connect _WIRE_236.eff, _T_3174
node _T_3175 = bits(_WIRE_237, 3, 3)
connect _WIRE_236.paa, _T_3175
node _T_3176 = bits(_WIRE_237, 4, 4)
connect _WIRE_236.pal, _T_3176
node _T_3177 = bits(_WIRE_237, 5, 5)
connect _WIRE_236.ppp, _T_3177
node _T_3178 = bits(_WIRE_237, 6, 6)
connect _WIRE_236.pr, _T_3178
node _T_3179 = bits(_WIRE_237, 7, 7)
connect _WIRE_236.px, _T_3179
node _T_3180 = bits(_WIRE_237, 8, 8)
connect _WIRE_236.pw, _T_3180
node _T_3181 = bits(_WIRE_237, 9, 9)
connect _WIRE_236.hr, _T_3181
node _T_3182 = bits(_WIRE_237, 10, 10)
connect _WIRE_236.hx, _T_3182
node _T_3183 = bits(_WIRE_237, 11, 11)
connect _WIRE_236.hw, _T_3183
node _T_3184 = bits(_WIRE_237, 12, 12)
connect _WIRE_236.sr, _T_3184
node _T_3185 = bits(_WIRE_237, 13, 13)
connect _WIRE_236.sx, _T_3185
node _T_3186 = bits(_WIRE_237, 14, 14)
connect _WIRE_236.sw, _T_3186
node _T_3187 = bits(_WIRE_237, 15, 15)
connect _WIRE_236.gf, _T_3187
node _T_3188 = bits(_WIRE_237, 16, 16)
connect _WIRE_236.pf, _T_3188
node _T_3189 = bits(_WIRE_237, 17, 17)
connect _WIRE_236.ae_stage2, _T_3189
node _T_3190 = bits(_WIRE_237, 18, 18)
connect _WIRE_236.ae_final, _T_3190
node _T_3191 = bits(_WIRE_237, 19, 19)
connect _WIRE_236.ae_ptw, _T_3191
node _T_3192 = bits(_WIRE_237, 20, 20)
connect _WIRE_236.g, _T_3192
node _T_3193 = bits(_WIRE_237, 21, 21)
connect _WIRE_236.u, _T_3193
node _T_3194 = bits(_WIRE_237, 41, 22)
connect _WIRE_236.ppn, _T_3194
wire _WIRE_238 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_239 : UInt<42>
connect _WIRE_239, sectored_entries[0][7].data[3]
node _T_3195 = bits(_WIRE_239, 0, 0)
connect _WIRE_238.fragmented_superpage, _T_3195
node _T_3196 = bits(_WIRE_239, 1, 1)
connect _WIRE_238.c, _T_3196
node _T_3197 = bits(_WIRE_239, 2, 2)
connect _WIRE_238.eff, _T_3197
node _T_3198 = bits(_WIRE_239, 3, 3)
connect _WIRE_238.paa, _T_3198
node _T_3199 = bits(_WIRE_239, 4, 4)
connect _WIRE_238.pal, _T_3199
node _T_3200 = bits(_WIRE_239, 5, 5)
connect _WIRE_238.ppp, _T_3200
node _T_3201 = bits(_WIRE_239, 6, 6)
connect _WIRE_238.pr, _T_3201
node _T_3202 = bits(_WIRE_239, 7, 7)
connect _WIRE_238.px, _T_3202
node _T_3203 = bits(_WIRE_239, 8, 8)
connect _WIRE_238.pw, _T_3203
node _T_3204 = bits(_WIRE_239, 9, 9)
connect _WIRE_238.hr, _T_3204
node _T_3205 = bits(_WIRE_239, 10, 10)
connect _WIRE_238.hx, _T_3205
node _T_3206 = bits(_WIRE_239, 11, 11)
connect _WIRE_238.hw, _T_3206
node _T_3207 = bits(_WIRE_239, 12, 12)
connect _WIRE_238.sr, _T_3207
node _T_3208 = bits(_WIRE_239, 13, 13)
connect _WIRE_238.sx, _T_3208
node _T_3209 = bits(_WIRE_239, 14, 14)
connect _WIRE_238.sw, _T_3209
node _T_3210 = bits(_WIRE_239, 15, 15)
connect _WIRE_238.gf, _T_3210
node _T_3211 = bits(_WIRE_239, 16, 16)
connect _WIRE_238.pf, _T_3211
node _T_3212 = bits(_WIRE_239, 17, 17)
connect _WIRE_238.ae_stage2, _T_3212
node _T_3213 = bits(_WIRE_239, 18, 18)
connect _WIRE_238.ae_final, _T_3213
node _T_3214 = bits(_WIRE_239, 19, 19)
connect _WIRE_238.ae_ptw, _T_3214
node _T_3215 = bits(_WIRE_239, 20, 20)
connect _WIRE_238.g, _T_3215
node _T_3216 = bits(_WIRE_239, 21, 21)
connect _WIRE_238.u, _T_3216
node _T_3217 = bits(_WIRE_239, 41, 22)
connect _WIRE_238.ppn, _T_3217
node _T_3218 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3219 = and(_T_3218, _WIRE_232.fragmented_superpage)
when _T_3219 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
node _T_3220 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3221 = and(_T_3220, _WIRE_234.fragmented_superpage)
when _T_3221 :
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
node _T_3222 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3223 = and(_T_3222, _WIRE_236.fragmented_superpage)
when _T_3223 :
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
node _T_3224 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3225 = and(_T_3224, _WIRE_238.fragmented_superpage)
when _T_3225 :
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
else :
node _T_3226 = eq(hg_7, UInt<1>(0h0))
node _T_3227 = and(_T_3226, io.sfence.bits.rs2)
when _T_3227 :
wire _WIRE_240 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_241 : UInt<42>
connect _WIRE_241, sectored_entries[0][7].data[0]
node _T_3228 = bits(_WIRE_241, 0, 0)
connect _WIRE_240.fragmented_superpage, _T_3228
node _T_3229 = bits(_WIRE_241, 1, 1)
connect _WIRE_240.c, _T_3229
node _T_3230 = bits(_WIRE_241, 2, 2)
connect _WIRE_240.eff, _T_3230
node _T_3231 = bits(_WIRE_241, 3, 3)
connect _WIRE_240.paa, _T_3231
node _T_3232 = bits(_WIRE_241, 4, 4)
connect _WIRE_240.pal, _T_3232
node _T_3233 = bits(_WIRE_241, 5, 5)
connect _WIRE_240.ppp, _T_3233
node _T_3234 = bits(_WIRE_241, 6, 6)
connect _WIRE_240.pr, _T_3234
node _T_3235 = bits(_WIRE_241, 7, 7)
connect _WIRE_240.px, _T_3235
node _T_3236 = bits(_WIRE_241, 8, 8)
connect _WIRE_240.pw, _T_3236
node _T_3237 = bits(_WIRE_241, 9, 9)
connect _WIRE_240.hr, _T_3237
node _T_3238 = bits(_WIRE_241, 10, 10)
connect _WIRE_240.hx, _T_3238
node _T_3239 = bits(_WIRE_241, 11, 11)
connect _WIRE_240.hw, _T_3239
node _T_3240 = bits(_WIRE_241, 12, 12)
connect _WIRE_240.sr, _T_3240
node _T_3241 = bits(_WIRE_241, 13, 13)
connect _WIRE_240.sx, _T_3241
node _T_3242 = bits(_WIRE_241, 14, 14)
connect _WIRE_240.sw, _T_3242
node _T_3243 = bits(_WIRE_241, 15, 15)
connect _WIRE_240.gf, _T_3243
node _T_3244 = bits(_WIRE_241, 16, 16)
connect _WIRE_240.pf, _T_3244
node _T_3245 = bits(_WIRE_241, 17, 17)
connect _WIRE_240.ae_stage2, _T_3245
node _T_3246 = bits(_WIRE_241, 18, 18)
connect _WIRE_240.ae_final, _T_3246
node _T_3247 = bits(_WIRE_241, 19, 19)
connect _WIRE_240.ae_ptw, _T_3247
node _T_3248 = bits(_WIRE_241, 20, 20)
connect _WIRE_240.g, _T_3248
node _T_3249 = bits(_WIRE_241, 21, 21)
connect _WIRE_240.u, _T_3249
node _T_3250 = bits(_WIRE_241, 41, 22)
connect _WIRE_240.ppn, _T_3250
wire _WIRE_242 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_243 : UInt<42>
connect _WIRE_243, sectored_entries[0][7].data[1]
node _T_3251 = bits(_WIRE_243, 0, 0)
connect _WIRE_242.fragmented_superpage, _T_3251
node _T_3252 = bits(_WIRE_243, 1, 1)
connect _WIRE_242.c, _T_3252
node _T_3253 = bits(_WIRE_243, 2, 2)
connect _WIRE_242.eff, _T_3253
node _T_3254 = bits(_WIRE_243, 3, 3)
connect _WIRE_242.paa, _T_3254
node _T_3255 = bits(_WIRE_243, 4, 4)
connect _WIRE_242.pal, _T_3255
node _T_3256 = bits(_WIRE_243, 5, 5)
connect _WIRE_242.ppp, _T_3256
node _T_3257 = bits(_WIRE_243, 6, 6)
connect _WIRE_242.pr, _T_3257
node _T_3258 = bits(_WIRE_243, 7, 7)
connect _WIRE_242.px, _T_3258
node _T_3259 = bits(_WIRE_243, 8, 8)
connect _WIRE_242.pw, _T_3259
node _T_3260 = bits(_WIRE_243, 9, 9)
connect _WIRE_242.hr, _T_3260
node _T_3261 = bits(_WIRE_243, 10, 10)
connect _WIRE_242.hx, _T_3261
node _T_3262 = bits(_WIRE_243, 11, 11)
connect _WIRE_242.hw, _T_3262
node _T_3263 = bits(_WIRE_243, 12, 12)
connect _WIRE_242.sr, _T_3263
node _T_3264 = bits(_WIRE_243, 13, 13)
connect _WIRE_242.sx, _T_3264
node _T_3265 = bits(_WIRE_243, 14, 14)
connect _WIRE_242.sw, _T_3265
node _T_3266 = bits(_WIRE_243, 15, 15)
connect _WIRE_242.gf, _T_3266
node _T_3267 = bits(_WIRE_243, 16, 16)
connect _WIRE_242.pf, _T_3267
node _T_3268 = bits(_WIRE_243, 17, 17)
connect _WIRE_242.ae_stage2, _T_3268
node _T_3269 = bits(_WIRE_243, 18, 18)
connect _WIRE_242.ae_final, _T_3269
node _T_3270 = bits(_WIRE_243, 19, 19)
connect _WIRE_242.ae_ptw, _T_3270
node _T_3271 = bits(_WIRE_243, 20, 20)
connect _WIRE_242.g, _T_3271
node _T_3272 = bits(_WIRE_243, 21, 21)
connect _WIRE_242.u, _T_3272
node _T_3273 = bits(_WIRE_243, 41, 22)
connect _WIRE_242.ppn, _T_3273
wire _WIRE_244 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_245 : UInt<42>
connect _WIRE_245, sectored_entries[0][7].data[2]
node _T_3274 = bits(_WIRE_245, 0, 0)
connect _WIRE_244.fragmented_superpage, _T_3274
node _T_3275 = bits(_WIRE_245, 1, 1)
connect _WIRE_244.c, _T_3275
node _T_3276 = bits(_WIRE_245, 2, 2)
connect _WIRE_244.eff, _T_3276
node _T_3277 = bits(_WIRE_245, 3, 3)
connect _WIRE_244.paa, _T_3277
node _T_3278 = bits(_WIRE_245, 4, 4)
connect _WIRE_244.pal, _T_3278
node _T_3279 = bits(_WIRE_245, 5, 5)
connect _WIRE_244.ppp, _T_3279
node _T_3280 = bits(_WIRE_245, 6, 6)
connect _WIRE_244.pr, _T_3280
node _T_3281 = bits(_WIRE_245, 7, 7)
connect _WIRE_244.px, _T_3281
node _T_3282 = bits(_WIRE_245, 8, 8)
connect _WIRE_244.pw, _T_3282
node _T_3283 = bits(_WIRE_245, 9, 9)
connect _WIRE_244.hr, _T_3283
node _T_3284 = bits(_WIRE_245, 10, 10)
connect _WIRE_244.hx, _T_3284
node _T_3285 = bits(_WIRE_245, 11, 11)
connect _WIRE_244.hw, _T_3285
node _T_3286 = bits(_WIRE_245, 12, 12)
connect _WIRE_244.sr, _T_3286
node _T_3287 = bits(_WIRE_245, 13, 13)
connect _WIRE_244.sx, _T_3287
node _T_3288 = bits(_WIRE_245, 14, 14)
connect _WIRE_244.sw, _T_3288
node _T_3289 = bits(_WIRE_245, 15, 15)
connect _WIRE_244.gf, _T_3289
node _T_3290 = bits(_WIRE_245, 16, 16)
connect _WIRE_244.pf, _T_3290
node _T_3291 = bits(_WIRE_245, 17, 17)
connect _WIRE_244.ae_stage2, _T_3291
node _T_3292 = bits(_WIRE_245, 18, 18)
connect _WIRE_244.ae_final, _T_3292
node _T_3293 = bits(_WIRE_245, 19, 19)
connect _WIRE_244.ae_ptw, _T_3293
node _T_3294 = bits(_WIRE_245, 20, 20)
connect _WIRE_244.g, _T_3294
node _T_3295 = bits(_WIRE_245, 21, 21)
connect _WIRE_244.u, _T_3295
node _T_3296 = bits(_WIRE_245, 41, 22)
connect _WIRE_244.ppn, _T_3296
wire _WIRE_246 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_247 : UInt<42>
connect _WIRE_247, sectored_entries[0][7].data[3]
node _T_3297 = bits(_WIRE_247, 0, 0)
connect _WIRE_246.fragmented_superpage, _T_3297
node _T_3298 = bits(_WIRE_247, 1, 1)
connect _WIRE_246.c, _T_3298
node _T_3299 = bits(_WIRE_247, 2, 2)
connect _WIRE_246.eff, _T_3299
node _T_3300 = bits(_WIRE_247, 3, 3)
connect _WIRE_246.paa, _T_3300
node _T_3301 = bits(_WIRE_247, 4, 4)
connect _WIRE_246.pal, _T_3301
node _T_3302 = bits(_WIRE_247, 5, 5)
connect _WIRE_246.ppp, _T_3302
node _T_3303 = bits(_WIRE_247, 6, 6)
connect _WIRE_246.pr, _T_3303
node _T_3304 = bits(_WIRE_247, 7, 7)
connect _WIRE_246.px, _T_3304
node _T_3305 = bits(_WIRE_247, 8, 8)
connect _WIRE_246.pw, _T_3305
node _T_3306 = bits(_WIRE_247, 9, 9)
connect _WIRE_246.hr, _T_3306
node _T_3307 = bits(_WIRE_247, 10, 10)
connect _WIRE_246.hx, _T_3307
node _T_3308 = bits(_WIRE_247, 11, 11)
connect _WIRE_246.hw, _T_3308
node _T_3309 = bits(_WIRE_247, 12, 12)
connect _WIRE_246.sr, _T_3309
node _T_3310 = bits(_WIRE_247, 13, 13)
connect _WIRE_246.sx, _T_3310
node _T_3311 = bits(_WIRE_247, 14, 14)
connect _WIRE_246.sw, _T_3311
node _T_3312 = bits(_WIRE_247, 15, 15)
connect _WIRE_246.gf, _T_3312
node _T_3313 = bits(_WIRE_247, 16, 16)
connect _WIRE_246.pf, _T_3313
node _T_3314 = bits(_WIRE_247, 17, 17)
connect _WIRE_246.ae_stage2, _T_3314
node _T_3315 = bits(_WIRE_247, 18, 18)
connect _WIRE_246.ae_final, _T_3315
node _T_3316 = bits(_WIRE_247, 19, 19)
connect _WIRE_246.ae_ptw, _T_3316
node _T_3317 = bits(_WIRE_247, 20, 20)
connect _WIRE_246.g, _T_3317
node _T_3318 = bits(_WIRE_247, 21, 21)
connect _WIRE_246.u, _T_3318
node _T_3319 = bits(_WIRE_247, 41, 22)
connect _WIRE_246.ppn, _T_3319
node _T_3320 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3321 = eq(_WIRE_240.g, UInt<1>(0h0))
node _T_3322 = and(_T_3320, _T_3321)
when _T_3322 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
node _T_3323 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3324 = eq(_WIRE_242.g, UInt<1>(0h0))
node _T_3325 = and(_T_3323, _T_3324)
when _T_3325 :
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
node _T_3326 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3327 = eq(_WIRE_244.g, UInt<1>(0h0))
node _T_3328 = and(_T_3326, _T_3327)
when _T_3328 :
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
node _T_3329 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3330 = eq(_WIRE_246.g, UInt<1>(0h0))
node _T_3331 = and(_T_3329, _T_3330)
when _T_3331 :
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
else :
node _T_3332 = or(hv_7, hg_7)
wire _WIRE_248 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_249 : UInt<42>
connect _WIRE_249, sectored_entries[0][7].data[0]
node _T_3333 = bits(_WIRE_249, 0, 0)
connect _WIRE_248.fragmented_superpage, _T_3333
node _T_3334 = bits(_WIRE_249, 1, 1)
connect _WIRE_248.c, _T_3334
node _T_3335 = bits(_WIRE_249, 2, 2)
connect _WIRE_248.eff, _T_3335
node _T_3336 = bits(_WIRE_249, 3, 3)
connect _WIRE_248.paa, _T_3336
node _T_3337 = bits(_WIRE_249, 4, 4)
connect _WIRE_248.pal, _T_3337
node _T_3338 = bits(_WIRE_249, 5, 5)
connect _WIRE_248.ppp, _T_3338
node _T_3339 = bits(_WIRE_249, 6, 6)
connect _WIRE_248.pr, _T_3339
node _T_3340 = bits(_WIRE_249, 7, 7)
connect _WIRE_248.px, _T_3340
node _T_3341 = bits(_WIRE_249, 8, 8)
connect _WIRE_248.pw, _T_3341
node _T_3342 = bits(_WIRE_249, 9, 9)
connect _WIRE_248.hr, _T_3342
node _T_3343 = bits(_WIRE_249, 10, 10)
connect _WIRE_248.hx, _T_3343
node _T_3344 = bits(_WIRE_249, 11, 11)
connect _WIRE_248.hw, _T_3344
node _T_3345 = bits(_WIRE_249, 12, 12)
connect _WIRE_248.sr, _T_3345
node _T_3346 = bits(_WIRE_249, 13, 13)
connect _WIRE_248.sx, _T_3346
node _T_3347 = bits(_WIRE_249, 14, 14)
connect _WIRE_248.sw, _T_3347
node _T_3348 = bits(_WIRE_249, 15, 15)
connect _WIRE_248.gf, _T_3348
node _T_3349 = bits(_WIRE_249, 16, 16)
connect _WIRE_248.pf, _T_3349
node _T_3350 = bits(_WIRE_249, 17, 17)
connect _WIRE_248.ae_stage2, _T_3350
node _T_3351 = bits(_WIRE_249, 18, 18)
connect _WIRE_248.ae_final, _T_3351
node _T_3352 = bits(_WIRE_249, 19, 19)
connect _WIRE_248.ae_ptw, _T_3352
node _T_3353 = bits(_WIRE_249, 20, 20)
connect _WIRE_248.g, _T_3353
node _T_3354 = bits(_WIRE_249, 21, 21)
connect _WIRE_248.u, _T_3354
node _T_3355 = bits(_WIRE_249, 41, 22)
connect _WIRE_248.ppn, _T_3355
wire _WIRE_250 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_251 : UInt<42>
connect _WIRE_251, sectored_entries[0][7].data[1]
node _T_3356 = bits(_WIRE_251, 0, 0)
connect _WIRE_250.fragmented_superpage, _T_3356
node _T_3357 = bits(_WIRE_251, 1, 1)
connect _WIRE_250.c, _T_3357
node _T_3358 = bits(_WIRE_251, 2, 2)
connect _WIRE_250.eff, _T_3358
node _T_3359 = bits(_WIRE_251, 3, 3)
connect _WIRE_250.paa, _T_3359
node _T_3360 = bits(_WIRE_251, 4, 4)
connect _WIRE_250.pal, _T_3360
node _T_3361 = bits(_WIRE_251, 5, 5)
connect _WIRE_250.ppp, _T_3361
node _T_3362 = bits(_WIRE_251, 6, 6)
connect _WIRE_250.pr, _T_3362
node _T_3363 = bits(_WIRE_251, 7, 7)
connect _WIRE_250.px, _T_3363
node _T_3364 = bits(_WIRE_251, 8, 8)
connect _WIRE_250.pw, _T_3364
node _T_3365 = bits(_WIRE_251, 9, 9)
connect _WIRE_250.hr, _T_3365
node _T_3366 = bits(_WIRE_251, 10, 10)
connect _WIRE_250.hx, _T_3366
node _T_3367 = bits(_WIRE_251, 11, 11)
connect _WIRE_250.hw, _T_3367
node _T_3368 = bits(_WIRE_251, 12, 12)
connect _WIRE_250.sr, _T_3368
node _T_3369 = bits(_WIRE_251, 13, 13)
connect _WIRE_250.sx, _T_3369
node _T_3370 = bits(_WIRE_251, 14, 14)
connect _WIRE_250.sw, _T_3370
node _T_3371 = bits(_WIRE_251, 15, 15)
connect _WIRE_250.gf, _T_3371
node _T_3372 = bits(_WIRE_251, 16, 16)
connect _WIRE_250.pf, _T_3372
node _T_3373 = bits(_WIRE_251, 17, 17)
connect _WIRE_250.ae_stage2, _T_3373
node _T_3374 = bits(_WIRE_251, 18, 18)
connect _WIRE_250.ae_final, _T_3374
node _T_3375 = bits(_WIRE_251, 19, 19)
connect _WIRE_250.ae_ptw, _T_3375
node _T_3376 = bits(_WIRE_251, 20, 20)
connect _WIRE_250.g, _T_3376
node _T_3377 = bits(_WIRE_251, 21, 21)
connect _WIRE_250.u, _T_3377
node _T_3378 = bits(_WIRE_251, 41, 22)
connect _WIRE_250.ppn, _T_3378
wire _WIRE_252 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_253 : UInt<42>
connect _WIRE_253, sectored_entries[0][7].data[2]
node _T_3379 = bits(_WIRE_253, 0, 0)
connect _WIRE_252.fragmented_superpage, _T_3379
node _T_3380 = bits(_WIRE_253, 1, 1)
connect _WIRE_252.c, _T_3380
node _T_3381 = bits(_WIRE_253, 2, 2)
connect _WIRE_252.eff, _T_3381
node _T_3382 = bits(_WIRE_253, 3, 3)
connect _WIRE_252.paa, _T_3382
node _T_3383 = bits(_WIRE_253, 4, 4)
connect _WIRE_252.pal, _T_3383
node _T_3384 = bits(_WIRE_253, 5, 5)
connect _WIRE_252.ppp, _T_3384
node _T_3385 = bits(_WIRE_253, 6, 6)
connect _WIRE_252.pr, _T_3385
node _T_3386 = bits(_WIRE_253, 7, 7)
connect _WIRE_252.px, _T_3386
node _T_3387 = bits(_WIRE_253, 8, 8)
connect _WIRE_252.pw, _T_3387
node _T_3388 = bits(_WIRE_253, 9, 9)
connect _WIRE_252.hr, _T_3388
node _T_3389 = bits(_WIRE_253, 10, 10)
connect _WIRE_252.hx, _T_3389
node _T_3390 = bits(_WIRE_253, 11, 11)
connect _WIRE_252.hw, _T_3390
node _T_3391 = bits(_WIRE_253, 12, 12)
connect _WIRE_252.sr, _T_3391
node _T_3392 = bits(_WIRE_253, 13, 13)
connect _WIRE_252.sx, _T_3392
node _T_3393 = bits(_WIRE_253, 14, 14)
connect _WIRE_252.sw, _T_3393
node _T_3394 = bits(_WIRE_253, 15, 15)
connect _WIRE_252.gf, _T_3394
node _T_3395 = bits(_WIRE_253, 16, 16)
connect _WIRE_252.pf, _T_3395
node _T_3396 = bits(_WIRE_253, 17, 17)
connect _WIRE_252.ae_stage2, _T_3396
node _T_3397 = bits(_WIRE_253, 18, 18)
connect _WIRE_252.ae_final, _T_3397
node _T_3398 = bits(_WIRE_253, 19, 19)
connect _WIRE_252.ae_ptw, _T_3398
node _T_3399 = bits(_WIRE_253, 20, 20)
connect _WIRE_252.g, _T_3399
node _T_3400 = bits(_WIRE_253, 21, 21)
connect _WIRE_252.u, _T_3400
node _T_3401 = bits(_WIRE_253, 41, 22)
connect _WIRE_252.ppn, _T_3401
wire _WIRE_254 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_255 : UInt<42>
connect _WIRE_255, sectored_entries[0][7].data[3]
node _T_3402 = bits(_WIRE_255, 0, 0)
connect _WIRE_254.fragmented_superpage, _T_3402
node _T_3403 = bits(_WIRE_255, 1, 1)
connect _WIRE_254.c, _T_3403
node _T_3404 = bits(_WIRE_255, 2, 2)
connect _WIRE_254.eff, _T_3404
node _T_3405 = bits(_WIRE_255, 3, 3)
connect _WIRE_254.paa, _T_3405
node _T_3406 = bits(_WIRE_255, 4, 4)
connect _WIRE_254.pal, _T_3406
node _T_3407 = bits(_WIRE_255, 5, 5)
connect _WIRE_254.ppp, _T_3407
node _T_3408 = bits(_WIRE_255, 6, 6)
connect _WIRE_254.pr, _T_3408
node _T_3409 = bits(_WIRE_255, 7, 7)
connect _WIRE_254.px, _T_3409
node _T_3410 = bits(_WIRE_255, 8, 8)
connect _WIRE_254.pw, _T_3410
node _T_3411 = bits(_WIRE_255, 9, 9)
connect _WIRE_254.hr, _T_3411
node _T_3412 = bits(_WIRE_255, 10, 10)
connect _WIRE_254.hx, _T_3412
node _T_3413 = bits(_WIRE_255, 11, 11)
connect _WIRE_254.hw, _T_3413
node _T_3414 = bits(_WIRE_255, 12, 12)
connect _WIRE_254.sr, _T_3414
node _T_3415 = bits(_WIRE_255, 13, 13)
connect _WIRE_254.sx, _T_3415
node _T_3416 = bits(_WIRE_255, 14, 14)
connect _WIRE_254.sw, _T_3416
node _T_3417 = bits(_WIRE_255, 15, 15)
connect _WIRE_254.gf, _T_3417
node _T_3418 = bits(_WIRE_255, 16, 16)
connect _WIRE_254.pf, _T_3418
node _T_3419 = bits(_WIRE_255, 17, 17)
connect _WIRE_254.ae_stage2, _T_3419
node _T_3420 = bits(_WIRE_255, 18, 18)
connect _WIRE_254.ae_final, _T_3420
node _T_3421 = bits(_WIRE_255, 19, 19)
connect _WIRE_254.ae_ptw, _T_3421
node _T_3422 = bits(_WIRE_255, 20, 20)
connect _WIRE_254.g, _T_3422
node _T_3423 = bits(_WIRE_255, 21, 21)
connect _WIRE_254.u, _T_3423
node _T_3424 = bits(_WIRE_255, 41, 22)
connect _WIRE_254.ppn, _T_3424
node _T_3425 = eq(sectored_entries[0][7].tag_v, _T_3332)
when _T_3425 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
node _T_3426 = eq(sectored_entries[0][7].tag_v, _T_3332)
when _T_3426 :
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
node _T_3427 = eq(sectored_entries[0][7].tag_v, _T_3332)
when _T_3427 :
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
node _T_3428 = eq(sectored_entries[0][7].tag_v, _T_3332)
when _T_3428 :
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
node hv_8 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_8 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3429 = eq(hg_8, UInt<1>(0h0))
node _T_3430 = and(_T_3429, io.sfence.bits.rs1)
when _T_3430 :
node _tagMatch_T = eq(superpage_entries[0].tag_v, hv_8)
node tagMatch = and(superpage_entries[0].valid[0], _tagMatch_T)
node _ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0))
node ignore = or(_ignore_T, UInt<1>(0h0))
node _T_3431 = xor(superpage_entries[0].tag_vpn, vpn)
node _T_3432 = bits(_T_3431, 26, 18)
node _T_3433 = eq(_T_3432, UInt<1>(0h0))
node _T_3434 = or(ignore, _T_3433)
node _T_3435 = and(tagMatch, _T_3434)
node _ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1))
node ignore_1 = or(_ignore_T_1, UInt<1>(0h0))
node _T_3436 = xor(superpage_entries[0].tag_vpn, vpn)
node _T_3437 = bits(_T_3436, 17, 9)
node _T_3438 = eq(_T_3437, UInt<1>(0h0))
node _T_3439 = or(ignore_1, _T_3438)
node _T_3440 = and(_T_3435, _T_3439)
node _ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2))
node ignore_2 = or(_ignore_T_2, UInt<1>(0h1))
node _T_3441 = xor(superpage_entries[0].tag_vpn, vpn)
node _T_3442 = bits(_T_3441, 8, 0)
node _T_3443 = eq(_T_3442, UInt<1>(0h0))
node _T_3444 = or(ignore_2, _T_3443)
node _T_3445 = and(_T_3440, _T_3444)
when _T_3445 :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
node _T_3446 = xor(superpage_entries[0].tag_vpn, vpn)
node _T_3447 = shr(_T_3446, 18)
node _T_3448 = eq(_T_3447, UInt<1>(0h0))
when _T_3448 :
wire _WIRE_256 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_257 : UInt<42>
connect _WIRE_257, superpage_entries[0].data[0]
node _T_3449 = bits(_WIRE_257, 0, 0)
connect _WIRE_256.fragmented_superpage, _T_3449
node _T_3450 = bits(_WIRE_257, 1, 1)
connect _WIRE_256.c, _T_3450
node _T_3451 = bits(_WIRE_257, 2, 2)
connect _WIRE_256.eff, _T_3451
node _T_3452 = bits(_WIRE_257, 3, 3)
connect _WIRE_256.paa, _T_3452
node _T_3453 = bits(_WIRE_257, 4, 4)
connect _WIRE_256.pal, _T_3453
node _T_3454 = bits(_WIRE_257, 5, 5)
connect _WIRE_256.ppp, _T_3454
node _T_3455 = bits(_WIRE_257, 6, 6)
connect _WIRE_256.pr, _T_3455
node _T_3456 = bits(_WIRE_257, 7, 7)
connect _WIRE_256.px, _T_3456
node _T_3457 = bits(_WIRE_257, 8, 8)
connect _WIRE_256.pw, _T_3457
node _T_3458 = bits(_WIRE_257, 9, 9)
connect _WIRE_256.hr, _T_3458
node _T_3459 = bits(_WIRE_257, 10, 10)
connect _WIRE_256.hx, _T_3459
node _T_3460 = bits(_WIRE_257, 11, 11)
connect _WIRE_256.hw, _T_3460
node _T_3461 = bits(_WIRE_257, 12, 12)
connect _WIRE_256.sr, _T_3461
node _T_3462 = bits(_WIRE_257, 13, 13)
connect _WIRE_256.sx, _T_3462
node _T_3463 = bits(_WIRE_257, 14, 14)
connect _WIRE_256.sw, _T_3463
node _T_3464 = bits(_WIRE_257, 15, 15)
connect _WIRE_256.gf, _T_3464
node _T_3465 = bits(_WIRE_257, 16, 16)
connect _WIRE_256.pf, _T_3465
node _T_3466 = bits(_WIRE_257, 17, 17)
connect _WIRE_256.ae_stage2, _T_3466
node _T_3467 = bits(_WIRE_257, 18, 18)
connect _WIRE_256.ae_final, _T_3467
node _T_3468 = bits(_WIRE_257, 19, 19)
connect _WIRE_256.ae_ptw, _T_3468
node _T_3469 = bits(_WIRE_257, 20, 20)
connect _WIRE_256.g, _T_3469
node _T_3470 = bits(_WIRE_257, 21, 21)
connect _WIRE_256.u, _T_3470
node _T_3471 = bits(_WIRE_257, 41, 22)
connect _WIRE_256.ppn, _T_3471
node _T_3472 = eq(superpage_entries[0].tag_v, hv_8)
node _T_3473 = and(_T_3472, _WIRE_256.fragmented_superpage)
when _T_3473 :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
else :
node _T_3474 = eq(hg_8, UInt<1>(0h0))
node _T_3475 = and(_T_3474, io.sfence.bits.rs2)
when _T_3475 :
wire _WIRE_258 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_259 : UInt<42>
connect _WIRE_259, superpage_entries[0].data[0]
node _T_3476 = bits(_WIRE_259, 0, 0)
connect _WIRE_258.fragmented_superpage, _T_3476
node _T_3477 = bits(_WIRE_259, 1, 1)
connect _WIRE_258.c, _T_3477
node _T_3478 = bits(_WIRE_259, 2, 2)
connect _WIRE_258.eff, _T_3478
node _T_3479 = bits(_WIRE_259, 3, 3)
connect _WIRE_258.paa, _T_3479
node _T_3480 = bits(_WIRE_259, 4, 4)
connect _WIRE_258.pal, _T_3480
node _T_3481 = bits(_WIRE_259, 5, 5)
connect _WIRE_258.ppp, _T_3481
node _T_3482 = bits(_WIRE_259, 6, 6)
connect _WIRE_258.pr, _T_3482
node _T_3483 = bits(_WIRE_259, 7, 7)
connect _WIRE_258.px, _T_3483
node _T_3484 = bits(_WIRE_259, 8, 8)
connect _WIRE_258.pw, _T_3484
node _T_3485 = bits(_WIRE_259, 9, 9)
connect _WIRE_258.hr, _T_3485
node _T_3486 = bits(_WIRE_259, 10, 10)
connect _WIRE_258.hx, _T_3486
node _T_3487 = bits(_WIRE_259, 11, 11)
connect _WIRE_258.hw, _T_3487
node _T_3488 = bits(_WIRE_259, 12, 12)
connect _WIRE_258.sr, _T_3488
node _T_3489 = bits(_WIRE_259, 13, 13)
connect _WIRE_258.sx, _T_3489
node _T_3490 = bits(_WIRE_259, 14, 14)
connect _WIRE_258.sw, _T_3490
node _T_3491 = bits(_WIRE_259, 15, 15)
connect _WIRE_258.gf, _T_3491
node _T_3492 = bits(_WIRE_259, 16, 16)
connect _WIRE_258.pf, _T_3492
node _T_3493 = bits(_WIRE_259, 17, 17)
connect _WIRE_258.ae_stage2, _T_3493
node _T_3494 = bits(_WIRE_259, 18, 18)
connect _WIRE_258.ae_final, _T_3494
node _T_3495 = bits(_WIRE_259, 19, 19)
connect _WIRE_258.ae_ptw, _T_3495
node _T_3496 = bits(_WIRE_259, 20, 20)
connect _WIRE_258.g, _T_3496
node _T_3497 = bits(_WIRE_259, 21, 21)
connect _WIRE_258.u, _T_3497
node _T_3498 = bits(_WIRE_259, 41, 22)
connect _WIRE_258.ppn, _T_3498
node _T_3499 = eq(superpage_entries[0].tag_v, hv_8)
node _T_3500 = eq(_WIRE_258.g, UInt<1>(0h0))
node _T_3501 = and(_T_3499, _T_3500)
when _T_3501 :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
else :
node _T_3502 = or(hv_8, hg_8)
wire _WIRE_260 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_261 : UInt<42>
connect _WIRE_261, superpage_entries[0].data[0]
node _T_3503 = bits(_WIRE_261, 0, 0)
connect _WIRE_260.fragmented_superpage, _T_3503
node _T_3504 = bits(_WIRE_261, 1, 1)
connect _WIRE_260.c, _T_3504
node _T_3505 = bits(_WIRE_261, 2, 2)
connect _WIRE_260.eff, _T_3505
node _T_3506 = bits(_WIRE_261, 3, 3)
connect _WIRE_260.paa, _T_3506
node _T_3507 = bits(_WIRE_261, 4, 4)
connect _WIRE_260.pal, _T_3507
node _T_3508 = bits(_WIRE_261, 5, 5)
connect _WIRE_260.ppp, _T_3508
node _T_3509 = bits(_WIRE_261, 6, 6)
connect _WIRE_260.pr, _T_3509
node _T_3510 = bits(_WIRE_261, 7, 7)
connect _WIRE_260.px, _T_3510
node _T_3511 = bits(_WIRE_261, 8, 8)
connect _WIRE_260.pw, _T_3511
node _T_3512 = bits(_WIRE_261, 9, 9)
connect _WIRE_260.hr, _T_3512
node _T_3513 = bits(_WIRE_261, 10, 10)
connect _WIRE_260.hx, _T_3513
node _T_3514 = bits(_WIRE_261, 11, 11)
connect _WIRE_260.hw, _T_3514
node _T_3515 = bits(_WIRE_261, 12, 12)
connect _WIRE_260.sr, _T_3515
node _T_3516 = bits(_WIRE_261, 13, 13)
connect _WIRE_260.sx, _T_3516
node _T_3517 = bits(_WIRE_261, 14, 14)
connect _WIRE_260.sw, _T_3517
node _T_3518 = bits(_WIRE_261, 15, 15)
connect _WIRE_260.gf, _T_3518
node _T_3519 = bits(_WIRE_261, 16, 16)
connect _WIRE_260.pf, _T_3519
node _T_3520 = bits(_WIRE_261, 17, 17)
connect _WIRE_260.ae_stage2, _T_3520
node _T_3521 = bits(_WIRE_261, 18, 18)
connect _WIRE_260.ae_final, _T_3521
node _T_3522 = bits(_WIRE_261, 19, 19)
connect _WIRE_260.ae_ptw, _T_3522
node _T_3523 = bits(_WIRE_261, 20, 20)
connect _WIRE_260.g, _T_3523
node _T_3524 = bits(_WIRE_261, 21, 21)
connect _WIRE_260.u, _T_3524
node _T_3525 = bits(_WIRE_261, 41, 22)
connect _WIRE_260.ppn, _T_3525
node _T_3526 = eq(superpage_entries[0].tag_v, _T_3502)
when _T_3526 :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
node hv_9 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_9 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3527 = eq(hg_9, UInt<1>(0h0))
node _T_3528 = and(_T_3527, io.sfence.bits.rs1)
when _T_3528 :
node _tagMatch_T_1 = eq(superpage_entries[1].tag_v, hv_9)
node tagMatch_1 = and(superpage_entries[1].valid[0], _tagMatch_T_1)
node _ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0))
node ignore_3 = or(_ignore_T_3, UInt<1>(0h0))
node _T_3529 = xor(superpage_entries[1].tag_vpn, vpn)
node _T_3530 = bits(_T_3529, 26, 18)
node _T_3531 = eq(_T_3530, UInt<1>(0h0))
node _T_3532 = or(ignore_3, _T_3531)
node _T_3533 = and(tagMatch_1, _T_3532)
node _ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1))
node ignore_4 = or(_ignore_T_4, UInt<1>(0h0))
node _T_3534 = xor(superpage_entries[1].tag_vpn, vpn)
node _T_3535 = bits(_T_3534, 17, 9)
node _T_3536 = eq(_T_3535, UInt<1>(0h0))
node _T_3537 = or(ignore_4, _T_3536)
node _T_3538 = and(_T_3533, _T_3537)
node _ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2))
node ignore_5 = or(_ignore_T_5, UInt<1>(0h1))
node _T_3539 = xor(superpage_entries[1].tag_vpn, vpn)
node _T_3540 = bits(_T_3539, 8, 0)
node _T_3541 = eq(_T_3540, UInt<1>(0h0))
node _T_3542 = or(ignore_5, _T_3541)
node _T_3543 = and(_T_3538, _T_3542)
when _T_3543 :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
node _T_3544 = xor(superpage_entries[1].tag_vpn, vpn)
node _T_3545 = shr(_T_3544, 18)
node _T_3546 = eq(_T_3545, UInt<1>(0h0))
when _T_3546 :
wire _WIRE_262 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_263 : UInt<42>
connect _WIRE_263, superpage_entries[1].data[0]
node _T_3547 = bits(_WIRE_263, 0, 0)
connect _WIRE_262.fragmented_superpage, _T_3547
node _T_3548 = bits(_WIRE_263, 1, 1)
connect _WIRE_262.c, _T_3548
node _T_3549 = bits(_WIRE_263, 2, 2)
connect _WIRE_262.eff, _T_3549
node _T_3550 = bits(_WIRE_263, 3, 3)
connect _WIRE_262.paa, _T_3550
node _T_3551 = bits(_WIRE_263, 4, 4)
connect _WIRE_262.pal, _T_3551
node _T_3552 = bits(_WIRE_263, 5, 5)
connect _WIRE_262.ppp, _T_3552
node _T_3553 = bits(_WIRE_263, 6, 6)
connect _WIRE_262.pr, _T_3553
node _T_3554 = bits(_WIRE_263, 7, 7)
connect _WIRE_262.px, _T_3554
node _T_3555 = bits(_WIRE_263, 8, 8)
connect _WIRE_262.pw, _T_3555
node _T_3556 = bits(_WIRE_263, 9, 9)
connect _WIRE_262.hr, _T_3556
node _T_3557 = bits(_WIRE_263, 10, 10)
connect _WIRE_262.hx, _T_3557
node _T_3558 = bits(_WIRE_263, 11, 11)
connect _WIRE_262.hw, _T_3558
node _T_3559 = bits(_WIRE_263, 12, 12)
connect _WIRE_262.sr, _T_3559
node _T_3560 = bits(_WIRE_263, 13, 13)
connect _WIRE_262.sx, _T_3560
node _T_3561 = bits(_WIRE_263, 14, 14)
connect _WIRE_262.sw, _T_3561
node _T_3562 = bits(_WIRE_263, 15, 15)
connect _WIRE_262.gf, _T_3562
node _T_3563 = bits(_WIRE_263, 16, 16)
connect _WIRE_262.pf, _T_3563
node _T_3564 = bits(_WIRE_263, 17, 17)
connect _WIRE_262.ae_stage2, _T_3564
node _T_3565 = bits(_WIRE_263, 18, 18)
connect _WIRE_262.ae_final, _T_3565
node _T_3566 = bits(_WIRE_263, 19, 19)
connect _WIRE_262.ae_ptw, _T_3566
node _T_3567 = bits(_WIRE_263, 20, 20)
connect _WIRE_262.g, _T_3567
node _T_3568 = bits(_WIRE_263, 21, 21)
connect _WIRE_262.u, _T_3568
node _T_3569 = bits(_WIRE_263, 41, 22)
connect _WIRE_262.ppn, _T_3569
node _T_3570 = eq(superpage_entries[1].tag_v, hv_9)
node _T_3571 = and(_T_3570, _WIRE_262.fragmented_superpage)
when _T_3571 :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
else :
node _T_3572 = eq(hg_9, UInt<1>(0h0))
node _T_3573 = and(_T_3572, io.sfence.bits.rs2)
when _T_3573 :
wire _WIRE_264 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_265 : UInt<42>
connect _WIRE_265, superpage_entries[1].data[0]
node _T_3574 = bits(_WIRE_265, 0, 0)
connect _WIRE_264.fragmented_superpage, _T_3574
node _T_3575 = bits(_WIRE_265, 1, 1)
connect _WIRE_264.c, _T_3575
node _T_3576 = bits(_WIRE_265, 2, 2)
connect _WIRE_264.eff, _T_3576
node _T_3577 = bits(_WIRE_265, 3, 3)
connect _WIRE_264.paa, _T_3577
node _T_3578 = bits(_WIRE_265, 4, 4)
connect _WIRE_264.pal, _T_3578
node _T_3579 = bits(_WIRE_265, 5, 5)
connect _WIRE_264.ppp, _T_3579
node _T_3580 = bits(_WIRE_265, 6, 6)
connect _WIRE_264.pr, _T_3580
node _T_3581 = bits(_WIRE_265, 7, 7)
connect _WIRE_264.px, _T_3581
node _T_3582 = bits(_WIRE_265, 8, 8)
connect _WIRE_264.pw, _T_3582
node _T_3583 = bits(_WIRE_265, 9, 9)
connect _WIRE_264.hr, _T_3583
node _T_3584 = bits(_WIRE_265, 10, 10)
connect _WIRE_264.hx, _T_3584
node _T_3585 = bits(_WIRE_265, 11, 11)
connect _WIRE_264.hw, _T_3585
node _T_3586 = bits(_WIRE_265, 12, 12)
connect _WIRE_264.sr, _T_3586
node _T_3587 = bits(_WIRE_265, 13, 13)
connect _WIRE_264.sx, _T_3587
node _T_3588 = bits(_WIRE_265, 14, 14)
connect _WIRE_264.sw, _T_3588
node _T_3589 = bits(_WIRE_265, 15, 15)
connect _WIRE_264.gf, _T_3589
node _T_3590 = bits(_WIRE_265, 16, 16)
connect _WIRE_264.pf, _T_3590
node _T_3591 = bits(_WIRE_265, 17, 17)
connect _WIRE_264.ae_stage2, _T_3591
node _T_3592 = bits(_WIRE_265, 18, 18)
connect _WIRE_264.ae_final, _T_3592
node _T_3593 = bits(_WIRE_265, 19, 19)
connect _WIRE_264.ae_ptw, _T_3593
node _T_3594 = bits(_WIRE_265, 20, 20)
connect _WIRE_264.g, _T_3594
node _T_3595 = bits(_WIRE_265, 21, 21)
connect _WIRE_264.u, _T_3595
node _T_3596 = bits(_WIRE_265, 41, 22)
connect _WIRE_264.ppn, _T_3596
node _T_3597 = eq(superpage_entries[1].tag_v, hv_9)
node _T_3598 = eq(_WIRE_264.g, UInt<1>(0h0))
node _T_3599 = and(_T_3597, _T_3598)
when _T_3599 :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
else :
node _T_3600 = or(hv_9, hg_9)
wire _WIRE_266 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_267 : UInt<42>
connect _WIRE_267, superpage_entries[1].data[0]
node _T_3601 = bits(_WIRE_267, 0, 0)
connect _WIRE_266.fragmented_superpage, _T_3601
node _T_3602 = bits(_WIRE_267, 1, 1)
connect _WIRE_266.c, _T_3602
node _T_3603 = bits(_WIRE_267, 2, 2)
connect _WIRE_266.eff, _T_3603
node _T_3604 = bits(_WIRE_267, 3, 3)
connect _WIRE_266.paa, _T_3604
node _T_3605 = bits(_WIRE_267, 4, 4)
connect _WIRE_266.pal, _T_3605
node _T_3606 = bits(_WIRE_267, 5, 5)
connect _WIRE_266.ppp, _T_3606
node _T_3607 = bits(_WIRE_267, 6, 6)
connect _WIRE_266.pr, _T_3607
node _T_3608 = bits(_WIRE_267, 7, 7)
connect _WIRE_266.px, _T_3608
node _T_3609 = bits(_WIRE_267, 8, 8)
connect _WIRE_266.pw, _T_3609
node _T_3610 = bits(_WIRE_267, 9, 9)
connect _WIRE_266.hr, _T_3610
node _T_3611 = bits(_WIRE_267, 10, 10)
connect _WIRE_266.hx, _T_3611
node _T_3612 = bits(_WIRE_267, 11, 11)
connect _WIRE_266.hw, _T_3612
node _T_3613 = bits(_WIRE_267, 12, 12)
connect _WIRE_266.sr, _T_3613
node _T_3614 = bits(_WIRE_267, 13, 13)
connect _WIRE_266.sx, _T_3614
node _T_3615 = bits(_WIRE_267, 14, 14)
connect _WIRE_266.sw, _T_3615
node _T_3616 = bits(_WIRE_267, 15, 15)
connect _WIRE_266.gf, _T_3616
node _T_3617 = bits(_WIRE_267, 16, 16)
connect _WIRE_266.pf, _T_3617
node _T_3618 = bits(_WIRE_267, 17, 17)
connect _WIRE_266.ae_stage2, _T_3618
node _T_3619 = bits(_WIRE_267, 18, 18)
connect _WIRE_266.ae_final, _T_3619
node _T_3620 = bits(_WIRE_267, 19, 19)
connect _WIRE_266.ae_ptw, _T_3620
node _T_3621 = bits(_WIRE_267, 20, 20)
connect _WIRE_266.g, _T_3621
node _T_3622 = bits(_WIRE_267, 21, 21)
connect _WIRE_266.u, _T_3622
node _T_3623 = bits(_WIRE_267, 41, 22)
connect _WIRE_266.ppn, _T_3623
node _T_3624 = eq(superpage_entries[1].tag_v, _T_3600)
when _T_3624 :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
node hv_10 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_10 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3625 = eq(hg_10, UInt<1>(0h0))
node _T_3626 = and(_T_3625, io.sfence.bits.rs1)
when _T_3626 :
node _tagMatch_T_2 = eq(superpage_entries[2].tag_v, hv_10)
node tagMatch_2 = and(superpage_entries[2].valid[0], _tagMatch_T_2)
node _ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0))
node ignore_6 = or(_ignore_T_6, UInt<1>(0h0))
node _T_3627 = xor(superpage_entries[2].tag_vpn, vpn)
node _T_3628 = bits(_T_3627, 26, 18)
node _T_3629 = eq(_T_3628, UInt<1>(0h0))
node _T_3630 = or(ignore_6, _T_3629)
node _T_3631 = and(tagMatch_2, _T_3630)
node _ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1))
node ignore_7 = or(_ignore_T_7, UInt<1>(0h0))
node _T_3632 = xor(superpage_entries[2].tag_vpn, vpn)
node _T_3633 = bits(_T_3632, 17, 9)
node _T_3634 = eq(_T_3633, UInt<1>(0h0))
node _T_3635 = or(ignore_7, _T_3634)
node _T_3636 = and(_T_3631, _T_3635)
node _ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2))
node ignore_8 = or(_ignore_T_8, UInt<1>(0h1))
node _T_3637 = xor(superpage_entries[2].tag_vpn, vpn)
node _T_3638 = bits(_T_3637, 8, 0)
node _T_3639 = eq(_T_3638, UInt<1>(0h0))
node _T_3640 = or(ignore_8, _T_3639)
node _T_3641 = and(_T_3636, _T_3640)
when _T_3641 :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
node _T_3642 = xor(superpage_entries[2].tag_vpn, vpn)
node _T_3643 = shr(_T_3642, 18)
node _T_3644 = eq(_T_3643, UInt<1>(0h0))
when _T_3644 :
wire _WIRE_268 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_269 : UInt<42>
connect _WIRE_269, superpage_entries[2].data[0]
node _T_3645 = bits(_WIRE_269, 0, 0)
connect _WIRE_268.fragmented_superpage, _T_3645
node _T_3646 = bits(_WIRE_269, 1, 1)
connect _WIRE_268.c, _T_3646
node _T_3647 = bits(_WIRE_269, 2, 2)
connect _WIRE_268.eff, _T_3647
node _T_3648 = bits(_WIRE_269, 3, 3)
connect _WIRE_268.paa, _T_3648
node _T_3649 = bits(_WIRE_269, 4, 4)
connect _WIRE_268.pal, _T_3649
node _T_3650 = bits(_WIRE_269, 5, 5)
connect _WIRE_268.ppp, _T_3650
node _T_3651 = bits(_WIRE_269, 6, 6)
connect _WIRE_268.pr, _T_3651
node _T_3652 = bits(_WIRE_269, 7, 7)
connect _WIRE_268.px, _T_3652
node _T_3653 = bits(_WIRE_269, 8, 8)
connect _WIRE_268.pw, _T_3653
node _T_3654 = bits(_WIRE_269, 9, 9)
connect _WIRE_268.hr, _T_3654
node _T_3655 = bits(_WIRE_269, 10, 10)
connect _WIRE_268.hx, _T_3655
node _T_3656 = bits(_WIRE_269, 11, 11)
connect _WIRE_268.hw, _T_3656
node _T_3657 = bits(_WIRE_269, 12, 12)
connect _WIRE_268.sr, _T_3657
node _T_3658 = bits(_WIRE_269, 13, 13)
connect _WIRE_268.sx, _T_3658
node _T_3659 = bits(_WIRE_269, 14, 14)
connect _WIRE_268.sw, _T_3659
node _T_3660 = bits(_WIRE_269, 15, 15)
connect _WIRE_268.gf, _T_3660
node _T_3661 = bits(_WIRE_269, 16, 16)
connect _WIRE_268.pf, _T_3661
node _T_3662 = bits(_WIRE_269, 17, 17)
connect _WIRE_268.ae_stage2, _T_3662
node _T_3663 = bits(_WIRE_269, 18, 18)
connect _WIRE_268.ae_final, _T_3663
node _T_3664 = bits(_WIRE_269, 19, 19)
connect _WIRE_268.ae_ptw, _T_3664
node _T_3665 = bits(_WIRE_269, 20, 20)
connect _WIRE_268.g, _T_3665
node _T_3666 = bits(_WIRE_269, 21, 21)
connect _WIRE_268.u, _T_3666
node _T_3667 = bits(_WIRE_269, 41, 22)
connect _WIRE_268.ppn, _T_3667
node _T_3668 = eq(superpage_entries[2].tag_v, hv_10)
node _T_3669 = and(_T_3668, _WIRE_268.fragmented_superpage)
when _T_3669 :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
else :
node _T_3670 = eq(hg_10, UInt<1>(0h0))
node _T_3671 = and(_T_3670, io.sfence.bits.rs2)
when _T_3671 :
wire _WIRE_270 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_271 : UInt<42>
connect _WIRE_271, superpage_entries[2].data[0]
node _T_3672 = bits(_WIRE_271, 0, 0)
connect _WIRE_270.fragmented_superpage, _T_3672
node _T_3673 = bits(_WIRE_271, 1, 1)
connect _WIRE_270.c, _T_3673
node _T_3674 = bits(_WIRE_271, 2, 2)
connect _WIRE_270.eff, _T_3674
node _T_3675 = bits(_WIRE_271, 3, 3)
connect _WIRE_270.paa, _T_3675
node _T_3676 = bits(_WIRE_271, 4, 4)
connect _WIRE_270.pal, _T_3676
node _T_3677 = bits(_WIRE_271, 5, 5)
connect _WIRE_270.ppp, _T_3677
node _T_3678 = bits(_WIRE_271, 6, 6)
connect _WIRE_270.pr, _T_3678
node _T_3679 = bits(_WIRE_271, 7, 7)
connect _WIRE_270.px, _T_3679
node _T_3680 = bits(_WIRE_271, 8, 8)
connect _WIRE_270.pw, _T_3680
node _T_3681 = bits(_WIRE_271, 9, 9)
connect _WIRE_270.hr, _T_3681
node _T_3682 = bits(_WIRE_271, 10, 10)
connect _WIRE_270.hx, _T_3682
node _T_3683 = bits(_WIRE_271, 11, 11)
connect _WIRE_270.hw, _T_3683
node _T_3684 = bits(_WIRE_271, 12, 12)
connect _WIRE_270.sr, _T_3684
node _T_3685 = bits(_WIRE_271, 13, 13)
connect _WIRE_270.sx, _T_3685
node _T_3686 = bits(_WIRE_271, 14, 14)
connect _WIRE_270.sw, _T_3686
node _T_3687 = bits(_WIRE_271, 15, 15)
connect _WIRE_270.gf, _T_3687
node _T_3688 = bits(_WIRE_271, 16, 16)
connect _WIRE_270.pf, _T_3688
node _T_3689 = bits(_WIRE_271, 17, 17)
connect _WIRE_270.ae_stage2, _T_3689
node _T_3690 = bits(_WIRE_271, 18, 18)
connect _WIRE_270.ae_final, _T_3690
node _T_3691 = bits(_WIRE_271, 19, 19)
connect _WIRE_270.ae_ptw, _T_3691
node _T_3692 = bits(_WIRE_271, 20, 20)
connect _WIRE_270.g, _T_3692
node _T_3693 = bits(_WIRE_271, 21, 21)
connect _WIRE_270.u, _T_3693
node _T_3694 = bits(_WIRE_271, 41, 22)
connect _WIRE_270.ppn, _T_3694
node _T_3695 = eq(superpage_entries[2].tag_v, hv_10)
node _T_3696 = eq(_WIRE_270.g, UInt<1>(0h0))
node _T_3697 = and(_T_3695, _T_3696)
when _T_3697 :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
else :
node _T_3698 = or(hv_10, hg_10)
wire _WIRE_272 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_273 : UInt<42>
connect _WIRE_273, superpage_entries[2].data[0]
node _T_3699 = bits(_WIRE_273, 0, 0)
connect _WIRE_272.fragmented_superpage, _T_3699
node _T_3700 = bits(_WIRE_273, 1, 1)
connect _WIRE_272.c, _T_3700
node _T_3701 = bits(_WIRE_273, 2, 2)
connect _WIRE_272.eff, _T_3701
node _T_3702 = bits(_WIRE_273, 3, 3)
connect _WIRE_272.paa, _T_3702
node _T_3703 = bits(_WIRE_273, 4, 4)
connect _WIRE_272.pal, _T_3703
node _T_3704 = bits(_WIRE_273, 5, 5)
connect _WIRE_272.ppp, _T_3704
node _T_3705 = bits(_WIRE_273, 6, 6)
connect _WIRE_272.pr, _T_3705
node _T_3706 = bits(_WIRE_273, 7, 7)
connect _WIRE_272.px, _T_3706
node _T_3707 = bits(_WIRE_273, 8, 8)
connect _WIRE_272.pw, _T_3707
node _T_3708 = bits(_WIRE_273, 9, 9)
connect _WIRE_272.hr, _T_3708
node _T_3709 = bits(_WIRE_273, 10, 10)
connect _WIRE_272.hx, _T_3709
node _T_3710 = bits(_WIRE_273, 11, 11)
connect _WIRE_272.hw, _T_3710
node _T_3711 = bits(_WIRE_273, 12, 12)
connect _WIRE_272.sr, _T_3711
node _T_3712 = bits(_WIRE_273, 13, 13)
connect _WIRE_272.sx, _T_3712
node _T_3713 = bits(_WIRE_273, 14, 14)
connect _WIRE_272.sw, _T_3713
node _T_3714 = bits(_WIRE_273, 15, 15)
connect _WIRE_272.gf, _T_3714
node _T_3715 = bits(_WIRE_273, 16, 16)
connect _WIRE_272.pf, _T_3715
node _T_3716 = bits(_WIRE_273, 17, 17)
connect _WIRE_272.ae_stage2, _T_3716
node _T_3717 = bits(_WIRE_273, 18, 18)
connect _WIRE_272.ae_final, _T_3717
node _T_3718 = bits(_WIRE_273, 19, 19)
connect _WIRE_272.ae_ptw, _T_3718
node _T_3719 = bits(_WIRE_273, 20, 20)
connect _WIRE_272.g, _T_3719
node _T_3720 = bits(_WIRE_273, 21, 21)
connect _WIRE_272.u, _T_3720
node _T_3721 = bits(_WIRE_273, 41, 22)
connect _WIRE_272.ppn, _T_3721
node _T_3722 = eq(superpage_entries[2].tag_v, _T_3698)
when _T_3722 :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
node hv_11 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_11 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3723 = eq(hg_11, UInt<1>(0h0))
node _T_3724 = and(_T_3723, io.sfence.bits.rs1)
when _T_3724 :
node _tagMatch_T_3 = eq(superpage_entries[3].tag_v, hv_11)
node tagMatch_3 = and(superpage_entries[3].valid[0], _tagMatch_T_3)
node _ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0))
node ignore_9 = or(_ignore_T_9, UInt<1>(0h0))
node _T_3725 = xor(superpage_entries[3].tag_vpn, vpn)
node _T_3726 = bits(_T_3725, 26, 18)
node _T_3727 = eq(_T_3726, UInt<1>(0h0))
node _T_3728 = or(ignore_9, _T_3727)
node _T_3729 = and(tagMatch_3, _T_3728)
node _ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1))
node ignore_10 = or(_ignore_T_10, UInt<1>(0h0))
node _T_3730 = xor(superpage_entries[3].tag_vpn, vpn)
node _T_3731 = bits(_T_3730, 17, 9)
node _T_3732 = eq(_T_3731, UInt<1>(0h0))
node _T_3733 = or(ignore_10, _T_3732)
node _T_3734 = and(_T_3729, _T_3733)
node _ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2))
node ignore_11 = or(_ignore_T_11, UInt<1>(0h1))
node _T_3735 = xor(superpage_entries[3].tag_vpn, vpn)
node _T_3736 = bits(_T_3735, 8, 0)
node _T_3737 = eq(_T_3736, UInt<1>(0h0))
node _T_3738 = or(ignore_11, _T_3737)
node _T_3739 = and(_T_3734, _T_3738)
when _T_3739 :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
node _T_3740 = xor(superpage_entries[3].tag_vpn, vpn)
node _T_3741 = shr(_T_3740, 18)
node _T_3742 = eq(_T_3741, UInt<1>(0h0))
when _T_3742 :
wire _WIRE_274 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_275 : UInt<42>
connect _WIRE_275, superpage_entries[3].data[0]
node _T_3743 = bits(_WIRE_275, 0, 0)
connect _WIRE_274.fragmented_superpage, _T_3743
node _T_3744 = bits(_WIRE_275, 1, 1)
connect _WIRE_274.c, _T_3744
node _T_3745 = bits(_WIRE_275, 2, 2)
connect _WIRE_274.eff, _T_3745
node _T_3746 = bits(_WIRE_275, 3, 3)
connect _WIRE_274.paa, _T_3746
node _T_3747 = bits(_WIRE_275, 4, 4)
connect _WIRE_274.pal, _T_3747
node _T_3748 = bits(_WIRE_275, 5, 5)
connect _WIRE_274.ppp, _T_3748
node _T_3749 = bits(_WIRE_275, 6, 6)
connect _WIRE_274.pr, _T_3749
node _T_3750 = bits(_WIRE_275, 7, 7)
connect _WIRE_274.px, _T_3750
node _T_3751 = bits(_WIRE_275, 8, 8)
connect _WIRE_274.pw, _T_3751
node _T_3752 = bits(_WIRE_275, 9, 9)
connect _WIRE_274.hr, _T_3752
node _T_3753 = bits(_WIRE_275, 10, 10)
connect _WIRE_274.hx, _T_3753
node _T_3754 = bits(_WIRE_275, 11, 11)
connect _WIRE_274.hw, _T_3754
node _T_3755 = bits(_WIRE_275, 12, 12)
connect _WIRE_274.sr, _T_3755
node _T_3756 = bits(_WIRE_275, 13, 13)
connect _WIRE_274.sx, _T_3756
node _T_3757 = bits(_WIRE_275, 14, 14)
connect _WIRE_274.sw, _T_3757
node _T_3758 = bits(_WIRE_275, 15, 15)
connect _WIRE_274.gf, _T_3758
node _T_3759 = bits(_WIRE_275, 16, 16)
connect _WIRE_274.pf, _T_3759
node _T_3760 = bits(_WIRE_275, 17, 17)
connect _WIRE_274.ae_stage2, _T_3760
node _T_3761 = bits(_WIRE_275, 18, 18)
connect _WIRE_274.ae_final, _T_3761
node _T_3762 = bits(_WIRE_275, 19, 19)
connect _WIRE_274.ae_ptw, _T_3762
node _T_3763 = bits(_WIRE_275, 20, 20)
connect _WIRE_274.g, _T_3763
node _T_3764 = bits(_WIRE_275, 21, 21)
connect _WIRE_274.u, _T_3764
node _T_3765 = bits(_WIRE_275, 41, 22)
connect _WIRE_274.ppn, _T_3765
node _T_3766 = eq(superpage_entries[3].tag_v, hv_11)
node _T_3767 = and(_T_3766, _WIRE_274.fragmented_superpage)
when _T_3767 :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
else :
node _T_3768 = eq(hg_11, UInt<1>(0h0))
node _T_3769 = and(_T_3768, io.sfence.bits.rs2)
when _T_3769 :
wire _WIRE_276 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_277 : UInt<42>
connect _WIRE_277, superpage_entries[3].data[0]
node _T_3770 = bits(_WIRE_277, 0, 0)
connect _WIRE_276.fragmented_superpage, _T_3770
node _T_3771 = bits(_WIRE_277, 1, 1)
connect _WIRE_276.c, _T_3771
node _T_3772 = bits(_WIRE_277, 2, 2)
connect _WIRE_276.eff, _T_3772
node _T_3773 = bits(_WIRE_277, 3, 3)
connect _WIRE_276.paa, _T_3773
node _T_3774 = bits(_WIRE_277, 4, 4)
connect _WIRE_276.pal, _T_3774
node _T_3775 = bits(_WIRE_277, 5, 5)
connect _WIRE_276.ppp, _T_3775
node _T_3776 = bits(_WIRE_277, 6, 6)
connect _WIRE_276.pr, _T_3776
node _T_3777 = bits(_WIRE_277, 7, 7)
connect _WIRE_276.px, _T_3777
node _T_3778 = bits(_WIRE_277, 8, 8)
connect _WIRE_276.pw, _T_3778
node _T_3779 = bits(_WIRE_277, 9, 9)
connect _WIRE_276.hr, _T_3779
node _T_3780 = bits(_WIRE_277, 10, 10)
connect _WIRE_276.hx, _T_3780
node _T_3781 = bits(_WIRE_277, 11, 11)
connect _WIRE_276.hw, _T_3781
node _T_3782 = bits(_WIRE_277, 12, 12)
connect _WIRE_276.sr, _T_3782
node _T_3783 = bits(_WIRE_277, 13, 13)
connect _WIRE_276.sx, _T_3783
node _T_3784 = bits(_WIRE_277, 14, 14)
connect _WIRE_276.sw, _T_3784
node _T_3785 = bits(_WIRE_277, 15, 15)
connect _WIRE_276.gf, _T_3785
node _T_3786 = bits(_WIRE_277, 16, 16)
connect _WIRE_276.pf, _T_3786
node _T_3787 = bits(_WIRE_277, 17, 17)
connect _WIRE_276.ae_stage2, _T_3787
node _T_3788 = bits(_WIRE_277, 18, 18)
connect _WIRE_276.ae_final, _T_3788
node _T_3789 = bits(_WIRE_277, 19, 19)
connect _WIRE_276.ae_ptw, _T_3789
node _T_3790 = bits(_WIRE_277, 20, 20)
connect _WIRE_276.g, _T_3790
node _T_3791 = bits(_WIRE_277, 21, 21)
connect _WIRE_276.u, _T_3791
node _T_3792 = bits(_WIRE_277, 41, 22)
connect _WIRE_276.ppn, _T_3792
node _T_3793 = eq(superpage_entries[3].tag_v, hv_11)
node _T_3794 = eq(_WIRE_276.g, UInt<1>(0h0))
node _T_3795 = and(_T_3793, _T_3794)
when _T_3795 :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
else :
node _T_3796 = or(hv_11, hg_11)
wire _WIRE_278 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_279 : UInt<42>
connect _WIRE_279, superpage_entries[3].data[0]
node _T_3797 = bits(_WIRE_279, 0, 0)
connect _WIRE_278.fragmented_superpage, _T_3797
node _T_3798 = bits(_WIRE_279, 1, 1)
connect _WIRE_278.c, _T_3798
node _T_3799 = bits(_WIRE_279, 2, 2)
connect _WIRE_278.eff, _T_3799
node _T_3800 = bits(_WIRE_279, 3, 3)
connect _WIRE_278.paa, _T_3800
node _T_3801 = bits(_WIRE_279, 4, 4)
connect _WIRE_278.pal, _T_3801
node _T_3802 = bits(_WIRE_279, 5, 5)
connect _WIRE_278.ppp, _T_3802
node _T_3803 = bits(_WIRE_279, 6, 6)
connect _WIRE_278.pr, _T_3803
node _T_3804 = bits(_WIRE_279, 7, 7)
connect _WIRE_278.px, _T_3804
node _T_3805 = bits(_WIRE_279, 8, 8)
connect _WIRE_278.pw, _T_3805
node _T_3806 = bits(_WIRE_279, 9, 9)
connect _WIRE_278.hr, _T_3806
node _T_3807 = bits(_WIRE_279, 10, 10)
connect _WIRE_278.hx, _T_3807
node _T_3808 = bits(_WIRE_279, 11, 11)
connect _WIRE_278.hw, _T_3808
node _T_3809 = bits(_WIRE_279, 12, 12)
connect _WIRE_278.sr, _T_3809
node _T_3810 = bits(_WIRE_279, 13, 13)
connect _WIRE_278.sx, _T_3810
node _T_3811 = bits(_WIRE_279, 14, 14)
connect _WIRE_278.sw, _T_3811
node _T_3812 = bits(_WIRE_279, 15, 15)
connect _WIRE_278.gf, _T_3812
node _T_3813 = bits(_WIRE_279, 16, 16)
connect _WIRE_278.pf, _T_3813
node _T_3814 = bits(_WIRE_279, 17, 17)
connect _WIRE_278.ae_stage2, _T_3814
node _T_3815 = bits(_WIRE_279, 18, 18)
connect _WIRE_278.ae_final, _T_3815
node _T_3816 = bits(_WIRE_279, 19, 19)
connect _WIRE_278.ae_ptw, _T_3816
node _T_3817 = bits(_WIRE_279, 20, 20)
connect _WIRE_278.g, _T_3817
node _T_3818 = bits(_WIRE_279, 21, 21)
connect _WIRE_278.u, _T_3818
node _T_3819 = bits(_WIRE_279, 41, 22)
connect _WIRE_278.ppn, _T_3819
node _T_3820 = eq(superpage_entries[3].tag_v, _T_3796)
when _T_3820 :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
node hv_12 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_12 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3821 = eq(hg_12, UInt<1>(0h0))
node _T_3822 = and(_T_3821, io.sfence.bits.rs1)
when _T_3822 :
node _tagMatch_T_4 = eq(special_entry.tag_v, hv_12)
node tagMatch_4 = and(special_entry.valid[0], _tagMatch_T_4)
node _ignore_T_12 = lt(special_entry.level, UInt<1>(0h0))
node ignore_12 = or(_ignore_T_12, UInt<1>(0h0))
node _T_3823 = xor(special_entry.tag_vpn, vpn)
node _T_3824 = bits(_T_3823, 26, 18)
node _T_3825 = eq(_T_3824, UInt<1>(0h0))
node _T_3826 = or(ignore_12, _T_3825)
node _T_3827 = and(tagMatch_4, _T_3826)
node _ignore_T_13 = lt(special_entry.level, UInt<1>(0h1))
node ignore_13 = or(_ignore_T_13, UInt<1>(0h0))
node _T_3828 = xor(special_entry.tag_vpn, vpn)
node _T_3829 = bits(_T_3828, 17, 9)
node _T_3830 = eq(_T_3829, UInt<1>(0h0))
node _T_3831 = or(ignore_13, _T_3830)
node _T_3832 = and(_T_3827, _T_3831)
node _ignore_T_14 = lt(special_entry.level, UInt<2>(0h2))
node ignore_14 = or(_ignore_T_14, UInt<1>(0h0))
node _T_3833 = xor(special_entry.tag_vpn, vpn)
node _T_3834 = bits(_T_3833, 8, 0)
node _T_3835 = eq(_T_3834, UInt<1>(0h0))
node _T_3836 = or(ignore_14, _T_3835)
node _T_3837 = and(_T_3832, _T_3836)
when _T_3837 :
connect special_entry.valid[0], UInt<1>(0h0)
node _T_3838 = xor(special_entry.tag_vpn, vpn)
node _T_3839 = shr(_T_3838, 18)
node _T_3840 = eq(_T_3839, UInt<1>(0h0))
when _T_3840 :
wire _WIRE_280 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_281 : UInt<42>
connect _WIRE_281, special_entry.data[0]
node _T_3841 = bits(_WIRE_281, 0, 0)
connect _WIRE_280.fragmented_superpage, _T_3841
node _T_3842 = bits(_WIRE_281, 1, 1)
connect _WIRE_280.c, _T_3842
node _T_3843 = bits(_WIRE_281, 2, 2)
connect _WIRE_280.eff, _T_3843
node _T_3844 = bits(_WIRE_281, 3, 3)
connect _WIRE_280.paa, _T_3844
node _T_3845 = bits(_WIRE_281, 4, 4)
connect _WIRE_280.pal, _T_3845
node _T_3846 = bits(_WIRE_281, 5, 5)
connect _WIRE_280.ppp, _T_3846
node _T_3847 = bits(_WIRE_281, 6, 6)
connect _WIRE_280.pr, _T_3847
node _T_3848 = bits(_WIRE_281, 7, 7)
connect _WIRE_280.px, _T_3848
node _T_3849 = bits(_WIRE_281, 8, 8)
connect _WIRE_280.pw, _T_3849
node _T_3850 = bits(_WIRE_281, 9, 9)
connect _WIRE_280.hr, _T_3850
node _T_3851 = bits(_WIRE_281, 10, 10)
connect _WIRE_280.hx, _T_3851
node _T_3852 = bits(_WIRE_281, 11, 11)
connect _WIRE_280.hw, _T_3852
node _T_3853 = bits(_WIRE_281, 12, 12)
connect _WIRE_280.sr, _T_3853
node _T_3854 = bits(_WIRE_281, 13, 13)
connect _WIRE_280.sx, _T_3854
node _T_3855 = bits(_WIRE_281, 14, 14)
connect _WIRE_280.sw, _T_3855
node _T_3856 = bits(_WIRE_281, 15, 15)
connect _WIRE_280.gf, _T_3856
node _T_3857 = bits(_WIRE_281, 16, 16)
connect _WIRE_280.pf, _T_3857
node _T_3858 = bits(_WIRE_281, 17, 17)
connect _WIRE_280.ae_stage2, _T_3858
node _T_3859 = bits(_WIRE_281, 18, 18)
connect _WIRE_280.ae_final, _T_3859
node _T_3860 = bits(_WIRE_281, 19, 19)
connect _WIRE_280.ae_ptw, _T_3860
node _T_3861 = bits(_WIRE_281, 20, 20)
connect _WIRE_280.g, _T_3861
node _T_3862 = bits(_WIRE_281, 21, 21)
connect _WIRE_280.u, _T_3862
node _T_3863 = bits(_WIRE_281, 41, 22)
connect _WIRE_280.ppn, _T_3863
node _T_3864 = eq(special_entry.tag_v, hv_12)
node _T_3865 = and(_T_3864, _WIRE_280.fragmented_superpage)
when _T_3865 :
connect special_entry.valid[0], UInt<1>(0h0)
else :
node _T_3866 = eq(hg_12, UInt<1>(0h0))
node _T_3867 = and(_T_3866, io.sfence.bits.rs2)
when _T_3867 :
wire _WIRE_282 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_283 : UInt<42>
connect _WIRE_283, special_entry.data[0]
node _T_3868 = bits(_WIRE_283, 0, 0)
connect _WIRE_282.fragmented_superpage, _T_3868
node _T_3869 = bits(_WIRE_283, 1, 1)
connect _WIRE_282.c, _T_3869
node _T_3870 = bits(_WIRE_283, 2, 2)
connect _WIRE_282.eff, _T_3870
node _T_3871 = bits(_WIRE_283, 3, 3)
connect _WIRE_282.paa, _T_3871
node _T_3872 = bits(_WIRE_283, 4, 4)
connect _WIRE_282.pal, _T_3872
node _T_3873 = bits(_WIRE_283, 5, 5)
connect _WIRE_282.ppp, _T_3873
node _T_3874 = bits(_WIRE_283, 6, 6)
connect _WIRE_282.pr, _T_3874
node _T_3875 = bits(_WIRE_283, 7, 7)
connect _WIRE_282.px, _T_3875
node _T_3876 = bits(_WIRE_283, 8, 8)
connect _WIRE_282.pw, _T_3876
node _T_3877 = bits(_WIRE_283, 9, 9)
connect _WIRE_282.hr, _T_3877
node _T_3878 = bits(_WIRE_283, 10, 10)
connect _WIRE_282.hx, _T_3878
node _T_3879 = bits(_WIRE_283, 11, 11)
connect _WIRE_282.hw, _T_3879
node _T_3880 = bits(_WIRE_283, 12, 12)
connect _WIRE_282.sr, _T_3880
node _T_3881 = bits(_WIRE_283, 13, 13)
connect _WIRE_282.sx, _T_3881
node _T_3882 = bits(_WIRE_283, 14, 14)
connect _WIRE_282.sw, _T_3882
node _T_3883 = bits(_WIRE_283, 15, 15)
connect _WIRE_282.gf, _T_3883
node _T_3884 = bits(_WIRE_283, 16, 16)
connect _WIRE_282.pf, _T_3884
node _T_3885 = bits(_WIRE_283, 17, 17)
connect _WIRE_282.ae_stage2, _T_3885
node _T_3886 = bits(_WIRE_283, 18, 18)
connect _WIRE_282.ae_final, _T_3886
node _T_3887 = bits(_WIRE_283, 19, 19)
connect _WIRE_282.ae_ptw, _T_3887
node _T_3888 = bits(_WIRE_283, 20, 20)
connect _WIRE_282.g, _T_3888
node _T_3889 = bits(_WIRE_283, 21, 21)
connect _WIRE_282.u, _T_3889
node _T_3890 = bits(_WIRE_283, 41, 22)
connect _WIRE_282.ppn, _T_3890
node _T_3891 = eq(special_entry.tag_v, hv_12)
node _T_3892 = eq(_WIRE_282.g, UInt<1>(0h0))
node _T_3893 = and(_T_3891, _T_3892)
when _T_3893 :
connect special_entry.valid[0], UInt<1>(0h0)
else :
node _T_3894 = or(hv_12, hg_12)
wire _WIRE_284 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_285 : UInt<42>
connect _WIRE_285, special_entry.data[0]
node _T_3895 = bits(_WIRE_285, 0, 0)
connect _WIRE_284.fragmented_superpage, _T_3895
node _T_3896 = bits(_WIRE_285, 1, 1)
connect _WIRE_284.c, _T_3896
node _T_3897 = bits(_WIRE_285, 2, 2)
connect _WIRE_284.eff, _T_3897
node _T_3898 = bits(_WIRE_285, 3, 3)
connect _WIRE_284.paa, _T_3898
node _T_3899 = bits(_WIRE_285, 4, 4)
connect _WIRE_284.pal, _T_3899
node _T_3900 = bits(_WIRE_285, 5, 5)
connect _WIRE_284.ppp, _T_3900
node _T_3901 = bits(_WIRE_285, 6, 6)
connect _WIRE_284.pr, _T_3901
node _T_3902 = bits(_WIRE_285, 7, 7)
connect _WIRE_284.px, _T_3902
node _T_3903 = bits(_WIRE_285, 8, 8)
connect _WIRE_284.pw, _T_3903
node _T_3904 = bits(_WIRE_285, 9, 9)
connect _WIRE_284.hr, _T_3904
node _T_3905 = bits(_WIRE_285, 10, 10)
connect _WIRE_284.hx, _T_3905
node _T_3906 = bits(_WIRE_285, 11, 11)
connect _WIRE_284.hw, _T_3906
node _T_3907 = bits(_WIRE_285, 12, 12)
connect _WIRE_284.sr, _T_3907
node _T_3908 = bits(_WIRE_285, 13, 13)
connect _WIRE_284.sx, _T_3908
node _T_3909 = bits(_WIRE_285, 14, 14)
connect _WIRE_284.sw, _T_3909
node _T_3910 = bits(_WIRE_285, 15, 15)
connect _WIRE_284.gf, _T_3910
node _T_3911 = bits(_WIRE_285, 16, 16)
connect _WIRE_284.pf, _T_3911
node _T_3912 = bits(_WIRE_285, 17, 17)
connect _WIRE_284.ae_stage2, _T_3912
node _T_3913 = bits(_WIRE_285, 18, 18)
connect _WIRE_284.ae_final, _T_3913
node _T_3914 = bits(_WIRE_285, 19, 19)
connect _WIRE_284.ae_ptw, _T_3914
node _T_3915 = bits(_WIRE_285, 20, 20)
connect _WIRE_284.g, _T_3915
node _T_3916 = bits(_WIRE_285, 21, 21)
connect _WIRE_284.u, _T_3916
node _T_3917 = bits(_WIRE_285, 41, 22)
connect _WIRE_284.ppn, _T_3917
node _T_3918 = eq(special_entry.tag_v, _T_3894)
when _T_3918 :
connect special_entry.valid[0], UInt<1>(0h0)
node _T_3919 = and(io.req.ready, io.req.valid)
node _T_3920 = and(_T_3919, vsatp_mode_mismatch)
when _T_3920 :
wire _WIRE_286 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_287 : UInt<42>
connect _WIRE_287, sectored_entries[0][0].data[0]
node _T_3921 = bits(_WIRE_287, 0, 0)
connect _WIRE_286.fragmented_superpage, _T_3921
node _T_3922 = bits(_WIRE_287, 1, 1)
connect _WIRE_286.c, _T_3922
node _T_3923 = bits(_WIRE_287, 2, 2)
connect _WIRE_286.eff, _T_3923
node _T_3924 = bits(_WIRE_287, 3, 3)
connect _WIRE_286.paa, _T_3924
node _T_3925 = bits(_WIRE_287, 4, 4)
connect _WIRE_286.pal, _T_3925
node _T_3926 = bits(_WIRE_287, 5, 5)
connect _WIRE_286.ppp, _T_3926
node _T_3927 = bits(_WIRE_287, 6, 6)
connect _WIRE_286.pr, _T_3927
node _T_3928 = bits(_WIRE_287, 7, 7)
connect _WIRE_286.px, _T_3928
node _T_3929 = bits(_WIRE_287, 8, 8)
connect _WIRE_286.pw, _T_3929
node _T_3930 = bits(_WIRE_287, 9, 9)
connect _WIRE_286.hr, _T_3930
node _T_3931 = bits(_WIRE_287, 10, 10)
connect _WIRE_286.hx, _T_3931
node _T_3932 = bits(_WIRE_287, 11, 11)
connect _WIRE_286.hw, _T_3932
node _T_3933 = bits(_WIRE_287, 12, 12)
connect _WIRE_286.sr, _T_3933
node _T_3934 = bits(_WIRE_287, 13, 13)
connect _WIRE_286.sx, _T_3934
node _T_3935 = bits(_WIRE_287, 14, 14)
connect _WIRE_286.sw, _T_3935
node _T_3936 = bits(_WIRE_287, 15, 15)
connect _WIRE_286.gf, _T_3936
node _T_3937 = bits(_WIRE_287, 16, 16)
connect _WIRE_286.pf, _T_3937
node _T_3938 = bits(_WIRE_287, 17, 17)
connect _WIRE_286.ae_stage2, _T_3938
node _T_3939 = bits(_WIRE_287, 18, 18)
connect _WIRE_286.ae_final, _T_3939
node _T_3940 = bits(_WIRE_287, 19, 19)
connect _WIRE_286.ae_ptw, _T_3940
node _T_3941 = bits(_WIRE_287, 20, 20)
connect _WIRE_286.g, _T_3941
node _T_3942 = bits(_WIRE_287, 21, 21)
connect _WIRE_286.u, _T_3942
node _T_3943 = bits(_WIRE_287, 41, 22)
connect _WIRE_286.ppn, _T_3943
wire _WIRE_288 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_289 : UInt<42>
connect _WIRE_289, sectored_entries[0][0].data[1]
node _T_3944 = bits(_WIRE_289, 0, 0)
connect _WIRE_288.fragmented_superpage, _T_3944
node _T_3945 = bits(_WIRE_289, 1, 1)
connect _WIRE_288.c, _T_3945
node _T_3946 = bits(_WIRE_289, 2, 2)
connect _WIRE_288.eff, _T_3946
node _T_3947 = bits(_WIRE_289, 3, 3)
connect _WIRE_288.paa, _T_3947
node _T_3948 = bits(_WIRE_289, 4, 4)
connect _WIRE_288.pal, _T_3948
node _T_3949 = bits(_WIRE_289, 5, 5)
connect _WIRE_288.ppp, _T_3949
node _T_3950 = bits(_WIRE_289, 6, 6)
connect _WIRE_288.pr, _T_3950
node _T_3951 = bits(_WIRE_289, 7, 7)
connect _WIRE_288.px, _T_3951
node _T_3952 = bits(_WIRE_289, 8, 8)
connect _WIRE_288.pw, _T_3952
node _T_3953 = bits(_WIRE_289, 9, 9)
connect _WIRE_288.hr, _T_3953
node _T_3954 = bits(_WIRE_289, 10, 10)
connect _WIRE_288.hx, _T_3954
node _T_3955 = bits(_WIRE_289, 11, 11)
connect _WIRE_288.hw, _T_3955
node _T_3956 = bits(_WIRE_289, 12, 12)
connect _WIRE_288.sr, _T_3956
node _T_3957 = bits(_WIRE_289, 13, 13)
connect _WIRE_288.sx, _T_3957
node _T_3958 = bits(_WIRE_289, 14, 14)
connect _WIRE_288.sw, _T_3958
node _T_3959 = bits(_WIRE_289, 15, 15)
connect _WIRE_288.gf, _T_3959
node _T_3960 = bits(_WIRE_289, 16, 16)
connect _WIRE_288.pf, _T_3960
node _T_3961 = bits(_WIRE_289, 17, 17)
connect _WIRE_288.ae_stage2, _T_3961
node _T_3962 = bits(_WIRE_289, 18, 18)
connect _WIRE_288.ae_final, _T_3962
node _T_3963 = bits(_WIRE_289, 19, 19)
connect _WIRE_288.ae_ptw, _T_3963
node _T_3964 = bits(_WIRE_289, 20, 20)
connect _WIRE_288.g, _T_3964
node _T_3965 = bits(_WIRE_289, 21, 21)
connect _WIRE_288.u, _T_3965
node _T_3966 = bits(_WIRE_289, 41, 22)
connect _WIRE_288.ppn, _T_3966
wire _WIRE_290 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_291 : UInt<42>
connect _WIRE_291, sectored_entries[0][0].data[2]
node _T_3967 = bits(_WIRE_291, 0, 0)
connect _WIRE_290.fragmented_superpage, _T_3967
node _T_3968 = bits(_WIRE_291, 1, 1)
connect _WIRE_290.c, _T_3968
node _T_3969 = bits(_WIRE_291, 2, 2)
connect _WIRE_290.eff, _T_3969
node _T_3970 = bits(_WIRE_291, 3, 3)
connect _WIRE_290.paa, _T_3970
node _T_3971 = bits(_WIRE_291, 4, 4)
connect _WIRE_290.pal, _T_3971
node _T_3972 = bits(_WIRE_291, 5, 5)
connect _WIRE_290.ppp, _T_3972
node _T_3973 = bits(_WIRE_291, 6, 6)
connect _WIRE_290.pr, _T_3973
node _T_3974 = bits(_WIRE_291, 7, 7)
connect _WIRE_290.px, _T_3974
node _T_3975 = bits(_WIRE_291, 8, 8)
connect _WIRE_290.pw, _T_3975
node _T_3976 = bits(_WIRE_291, 9, 9)
connect _WIRE_290.hr, _T_3976
node _T_3977 = bits(_WIRE_291, 10, 10)
connect _WIRE_290.hx, _T_3977
node _T_3978 = bits(_WIRE_291, 11, 11)
connect _WIRE_290.hw, _T_3978
node _T_3979 = bits(_WIRE_291, 12, 12)
connect _WIRE_290.sr, _T_3979
node _T_3980 = bits(_WIRE_291, 13, 13)
connect _WIRE_290.sx, _T_3980
node _T_3981 = bits(_WIRE_291, 14, 14)
connect _WIRE_290.sw, _T_3981
node _T_3982 = bits(_WIRE_291, 15, 15)
connect _WIRE_290.gf, _T_3982
node _T_3983 = bits(_WIRE_291, 16, 16)
connect _WIRE_290.pf, _T_3983
node _T_3984 = bits(_WIRE_291, 17, 17)
connect _WIRE_290.ae_stage2, _T_3984
node _T_3985 = bits(_WIRE_291, 18, 18)
connect _WIRE_290.ae_final, _T_3985
node _T_3986 = bits(_WIRE_291, 19, 19)
connect _WIRE_290.ae_ptw, _T_3986
node _T_3987 = bits(_WIRE_291, 20, 20)
connect _WIRE_290.g, _T_3987
node _T_3988 = bits(_WIRE_291, 21, 21)
connect _WIRE_290.u, _T_3988
node _T_3989 = bits(_WIRE_291, 41, 22)
connect _WIRE_290.ppn, _T_3989
wire _WIRE_292 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_293 : UInt<42>
connect _WIRE_293, sectored_entries[0][0].data[3]
node _T_3990 = bits(_WIRE_293, 0, 0)
connect _WIRE_292.fragmented_superpage, _T_3990
node _T_3991 = bits(_WIRE_293, 1, 1)
connect _WIRE_292.c, _T_3991
node _T_3992 = bits(_WIRE_293, 2, 2)
connect _WIRE_292.eff, _T_3992
node _T_3993 = bits(_WIRE_293, 3, 3)
connect _WIRE_292.paa, _T_3993
node _T_3994 = bits(_WIRE_293, 4, 4)
connect _WIRE_292.pal, _T_3994
node _T_3995 = bits(_WIRE_293, 5, 5)
connect _WIRE_292.ppp, _T_3995
node _T_3996 = bits(_WIRE_293, 6, 6)
connect _WIRE_292.pr, _T_3996
node _T_3997 = bits(_WIRE_293, 7, 7)
connect _WIRE_292.px, _T_3997
node _T_3998 = bits(_WIRE_293, 8, 8)
connect _WIRE_292.pw, _T_3998
node _T_3999 = bits(_WIRE_293, 9, 9)
connect _WIRE_292.hr, _T_3999
node _T_4000 = bits(_WIRE_293, 10, 10)
connect _WIRE_292.hx, _T_4000
node _T_4001 = bits(_WIRE_293, 11, 11)
connect _WIRE_292.hw, _T_4001
node _T_4002 = bits(_WIRE_293, 12, 12)
connect _WIRE_292.sr, _T_4002
node _T_4003 = bits(_WIRE_293, 13, 13)
connect _WIRE_292.sx, _T_4003
node _T_4004 = bits(_WIRE_293, 14, 14)
connect _WIRE_292.sw, _T_4004
node _T_4005 = bits(_WIRE_293, 15, 15)
connect _WIRE_292.gf, _T_4005
node _T_4006 = bits(_WIRE_293, 16, 16)
connect _WIRE_292.pf, _T_4006
node _T_4007 = bits(_WIRE_293, 17, 17)
connect _WIRE_292.ae_stage2, _T_4007
node _T_4008 = bits(_WIRE_293, 18, 18)
connect _WIRE_292.ae_final, _T_4008
node _T_4009 = bits(_WIRE_293, 19, 19)
connect _WIRE_292.ae_ptw, _T_4009
node _T_4010 = bits(_WIRE_293, 20, 20)
connect _WIRE_292.g, _T_4010
node _T_4011 = bits(_WIRE_293, 21, 21)
connect _WIRE_292.u, _T_4011
node _T_4012 = bits(_WIRE_293, 41, 22)
connect _WIRE_292.ppn, _T_4012
node _T_4013 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1))
when _T_4013 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
node _T_4014 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1))
when _T_4014 :
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
node _T_4015 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1))
when _T_4015 :
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
node _T_4016 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1))
when _T_4016 :
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
wire _WIRE_294 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_295 : UInt<42>
connect _WIRE_295, sectored_entries[0][1].data[0]
node _T_4017 = bits(_WIRE_295, 0, 0)
connect _WIRE_294.fragmented_superpage, _T_4017
node _T_4018 = bits(_WIRE_295, 1, 1)
connect _WIRE_294.c, _T_4018
node _T_4019 = bits(_WIRE_295, 2, 2)
connect _WIRE_294.eff, _T_4019
node _T_4020 = bits(_WIRE_295, 3, 3)
connect _WIRE_294.paa, _T_4020
node _T_4021 = bits(_WIRE_295, 4, 4)
connect _WIRE_294.pal, _T_4021
node _T_4022 = bits(_WIRE_295, 5, 5)
connect _WIRE_294.ppp, _T_4022
node _T_4023 = bits(_WIRE_295, 6, 6)
connect _WIRE_294.pr, _T_4023
node _T_4024 = bits(_WIRE_295, 7, 7)
connect _WIRE_294.px, _T_4024
node _T_4025 = bits(_WIRE_295, 8, 8)
connect _WIRE_294.pw, _T_4025
node _T_4026 = bits(_WIRE_295, 9, 9)
connect _WIRE_294.hr, _T_4026
node _T_4027 = bits(_WIRE_295, 10, 10)
connect _WIRE_294.hx, _T_4027
node _T_4028 = bits(_WIRE_295, 11, 11)
connect _WIRE_294.hw, _T_4028
node _T_4029 = bits(_WIRE_295, 12, 12)
connect _WIRE_294.sr, _T_4029
node _T_4030 = bits(_WIRE_295, 13, 13)
connect _WIRE_294.sx, _T_4030
node _T_4031 = bits(_WIRE_295, 14, 14)
connect _WIRE_294.sw, _T_4031
node _T_4032 = bits(_WIRE_295, 15, 15)
connect _WIRE_294.gf, _T_4032
node _T_4033 = bits(_WIRE_295, 16, 16)
connect _WIRE_294.pf, _T_4033
node _T_4034 = bits(_WIRE_295, 17, 17)
connect _WIRE_294.ae_stage2, _T_4034
node _T_4035 = bits(_WIRE_295, 18, 18)
connect _WIRE_294.ae_final, _T_4035
node _T_4036 = bits(_WIRE_295, 19, 19)
connect _WIRE_294.ae_ptw, _T_4036
node _T_4037 = bits(_WIRE_295, 20, 20)
connect _WIRE_294.g, _T_4037
node _T_4038 = bits(_WIRE_295, 21, 21)
connect _WIRE_294.u, _T_4038
node _T_4039 = bits(_WIRE_295, 41, 22)
connect _WIRE_294.ppn, _T_4039
wire _WIRE_296 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_297 : UInt<42>
connect _WIRE_297, sectored_entries[0][1].data[1]
node _T_4040 = bits(_WIRE_297, 0, 0)
connect _WIRE_296.fragmented_superpage, _T_4040
node _T_4041 = bits(_WIRE_297, 1, 1)
connect _WIRE_296.c, _T_4041
node _T_4042 = bits(_WIRE_297, 2, 2)
connect _WIRE_296.eff, _T_4042
node _T_4043 = bits(_WIRE_297, 3, 3)
connect _WIRE_296.paa, _T_4043
node _T_4044 = bits(_WIRE_297, 4, 4)
connect _WIRE_296.pal, _T_4044
node _T_4045 = bits(_WIRE_297, 5, 5)
connect _WIRE_296.ppp, _T_4045
node _T_4046 = bits(_WIRE_297, 6, 6)
connect _WIRE_296.pr, _T_4046
node _T_4047 = bits(_WIRE_297, 7, 7)
connect _WIRE_296.px, _T_4047
node _T_4048 = bits(_WIRE_297, 8, 8)
connect _WIRE_296.pw, _T_4048
node _T_4049 = bits(_WIRE_297, 9, 9)
connect _WIRE_296.hr, _T_4049
node _T_4050 = bits(_WIRE_297, 10, 10)
connect _WIRE_296.hx, _T_4050
node _T_4051 = bits(_WIRE_297, 11, 11)
connect _WIRE_296.hw, _T_4051
node _T_4052 = bits(_WIRE_297, 12, 12)
connect _WIRE_296.sr, _T_4052
node _T_4053 = bits(_WIRE_297, 13, 13)
connect _WIRE_296.sx, _T_4053
node _T_4054 = bits(_WIRE_297, 14, 14)
connect _WIRE_296.sw, _T_4054
node _T_4055 = bits(_WIRE_297, 15, 15)
connect _WIRE_296.gf, _T_4055
node _T_4056 = bits(_WIRE_297, 16, 16)
connect _WIRE_296.pf, _T_4056
node _T_4057 = bits(_WIRE_297, 17, 17)
connect _WIRE_296.ae_stage2, _T_4057
node _T_4058 = bits(_WIRE_297, 18, 18)
connect _WIRE_296.ae_final, _T_4058
node _T_4059 = bits(_WIRE_297, 19, 19)
connect _WIRE_296.ae_ptw, _T_4059
node _T_4060 = bits(_WIRE_297, 20, 20)
connect _WIRE_296.g, _T_4060
node _T_4061 = bits(_WIRE_297, 21, 21)
connect _WIRE_296.u, _T_4061
node _T_4062 = bits(_WIRE_297, 41, 22)
connect _WIRE_296.ppn, _T_4062
wire _WIRE_298 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_299 : UInt<42>
connect _WIRE_299, sectored_entries[0][1].data[2]
node _T_4063 = bits(_WIRE_299, 0, 0)
connect _WIRE_298.fragmented_superpage, _T_4063
node _T_4064 = bits(_WIRE_299, 1, 1)
connect _WIRE_298.c, _T_4064
node _T_4065 = bits(_WIRE_299, 2, 2)
connect _WIRE_298.eff, _T_4065
node _T_4066 = bits(_WIRE_299, 3, 3)
connect _WIRE_298.paa, _T_4066
node _T_4067 = bits(_WIRE_299, 4, 4)
connect _WIRE_298.pal, _T_4067
node _T_4068 = bits(_WIRE_299, 5, 5)
connect _WIRE_298.ppp, _T_4068
node _T_4069 = bits(_WIRE_299, 6, 6)
connect _WIRE_298.pr, _T_4069
node _T_4070 = bits(_WIRE_299, 7, 7)
connect _WIRE_298.px, _T_4070
node _T_4071 = bits(_WIRE_299, 8, 8)
connect _WIRE_298.pw, _T_4071
node _T_4072 = bits(_WIRE_299, 9, 9)
connect _WIRE_298.hr, _T_4072
node _T_4073 = bits(_WIRE_299, 10, 10)
connect _WIRE_298.hx, _T_4073
node _T_4074 = bits(_WIRE_299, 11, 11)
connect _WIRE_298.hw, _T_4074
node _T_4075 = bits(_WIRE_299, 12, 12)
connect _WIRE_298.sr, _T_4075
node _T_4076 = bits(_WIRE_299, 13, 13)
connect _WIRE_298.sx, _T_4076
node _T_4077 = bits(_WIRE_299, 14, 14)
connect _WIRE_298.sw, _T_4077
node _T_4078 = bits(_WIRE_299, 15, 15)
connect _WIRE_298.gf, _T_4078
node _T_4079 = bits(_WIRE_299, 16, 16)
connect _WIRE_298.pf, _T_4079
node _T_4080 = bits(_WIRE_299, 17, 17)
connect _WIRE_298.ae_stage2, _T_4080
node _T_4081 = bits(_WIRE_299, 18, 18)
connect _WIRE_298.ae_final, _T_4081
node _T_4082 = bits(_WIRE_299, 19, 19)
connect _WIRE_298.ae_ptw, _T_4082
node _T_4083 = bits(_WIRE_299, 20, 20)
connect _WIRE_298.g, _T_4083
node _T_4084 = bits(_WIRE_299, 21, 21)
connect _WIRE_298.u, _T_4084
node _T_4085 = bits(_WIRE_299, 41, 22)
connect _WIRE_298.ppn, _T_4085
wire _WIRE_300 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_301 : UInt<42>
connect _WIRE_301, sectored_entries[0][1].data[3]
node _T_4086 = bits(_WIRE_301, 0, 0)
connect _WIRE_300.fragmented_superpage, _T_4086
node _T_4087 = bits(_WIRE_301, 1, 1)
connect _WIRE_300.c, _T_4087
node _T_4088 = bits(_WIRE_301, 2, 2)
connect _WIRE_300.eff, _T_4088
node _T_4089 = bits(_WIRE_301, 3, 3)
connect _WIRE_300.paa, _T_4089
node _T_4090 = bits(_WIRE_301, 4, 4)
connect _WIRE_300.pal, _T_4090
node _T_4091 = bits(_WIRE_301, 5, 5)
connect _WIRE_300.ppp, _T_4091
node _T_4092 = bits(_WIRE_301, 6, 6)
connect _WIRE_300.pr, _T_4092
node _T_4093 = bits(_WIRE_301, 7, 7)
connect _WIRE_300.px, _T_4093
node _T_4094 = bits(_WIRE_301, 8, 8)
connect _WIRE_300.pw, _T_4094
node _T_4095 = bits(_WIRE_301, 9, 9)
connect _WIRE_300.hr, _T_4095
node _T_4096 = bits(_WIRE_301, 10, 10)
connect _WIRE_300.hx, _T_4096
node _T_4097 = bits(_WIRE_301, 11, 11)
connect _WIRE_300.hw, _T_4097
node _T_4098 = bits(_WIRE_301, 12, 12)
connect _WIRE_300.sr, _T_4098
node _T_4099 = bits(_WIRE_301, 13, 13)
connect _WIRE_300.sx, _T_4099
node _T_4100 = bits(_WIRE_301, 14, 14)
connect _WIRE_300.sw, _T_4100
node _T_4101 = bits(_WIRE_301, 15, 15)
connect _WIRE_300.gf, _T_4101
node _T_4102 = bits(_WIRE_301, 16, 16)
connect _WIRE_300.pf, _T_4102
node _T_4103 = bits(_WIRE_301, 17, 17)
connect _WIRE_300.ae_stage2, _T_4103
node _T_4104 = bits(_WIRE_301, 18, 18)
connect _WIRE_300.ae_final, _T_4104
node _T_4105 = bits(_WIRE_301, 19, 19)
connect _WIRE_300.ae_ptw, _T_4105
node _T_4106 = bits(_WIRE_301, 20, 20)
connect _WIRE_300.g, _T_4106
node _T_4107 = bits(_WIRE_301, 21, 21)
connect _WIRE_300.u, _T_4107
node _T_4108 = bits(_WIRE_301, 41, 22)
connect _WIRE_300.ppn, _T_4108
node _T_4109 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1))
when _T_4109 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
node _T_4110 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1))
when _T_4110 :
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
node _T_4111 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1))
when _T_4111 :
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
node _T_4112 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1))
when _T_4112 :
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
wire _WIRE_302 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_303 : UInt<42>
connect _WIRE_303, sectored_entries[0][2].data[0]
node _T_4113 = bits(_WIRE_303, 0, 0)
connect _WIRE_302.fragmented_superpage, _T_4113
node _T_4114 = bits(_WIRE_303, 1, 1)
connect _WIRE_302.c, _T_4114
node _T_4115 = bits(_WIRE_303, 2, 2)
connect _WIRE_302.eff, _T_4115
node _T_4116 = bits(_WIRE_303, 3, 3)
connect _WIRE_302.paa, _T_4116
node _T_4117 = bits(_WIRE_303, 4, 4)
connect _WIRE_302.pal, _T_4117
node _T_4118 = bits(_WIRE_303, 5, 5)
connect _WIRE_302.ppp, _T_4118
node _T_4119 = bits(_WIRE_303, 6, 6)
connect _WIRE_302.pr, _T_4119
node _T_4120 = bits(_WIRE_303, 7, 7)
connect _WIRE_302.px, _T_4120
node _T_4121 = bits(_WIRE_303, 8, 8)
connect _WIRE_302.pw, _T_4121
node _T_4122 = bits(_WIRE_303, 9, 9)
connect _WIRE_302.hr, _T_4122
node _T_4123 = bits(_WIRE_303, 10, 10)
connect _WIRE_302.hx, _T_4123
node _T_4124 = bits(_WIRE_303, 11, 11)
connect _WIRE_302.hw, _T_4124
node _T_4125 = bits(_WIRE_303, 12, 12)
connect _WIRE_302.sr, _T_4125
node _T_4126 = bits(_WIRE_303, 13, 13)
connect _WIRE_302.sx, _T_4126
node _T_4127 = bits(_WIRE_303, 14, 14)
connect _WIRE_302.sw, _T_4127
node _T_4128 = bits(_WIRE_303, 15, 15)
connect _WIRE_302.gf, _T_4128
node _T_4129 = bits(_WIRE_303, 16, 16)
connect _WIRE_302.pf, _T_4129
node _T_4130 = bits(_WIRE_303, 17, 17)
connect _WIRE_302.ae_stage2, _T_4130
node _T_4131 = bits(_WIRE_303, 18, 18)
connect _WIRE_302.ae_final, _T_4131
node _T_4132 = bits(_WIRE_303, 19, 19)
connect _WIRE_302.ae_ptw, _T_4132
node _T_4133 = bits(_WIRE_303, 20, 20)
connect _WIRE_302.g, _T_4133
node _T_4134 = bits(_WIRE_303, 21, 21)
connect _WIRE_302.u, _T_4134
node _T_4135 = bits(_WIRE_303, 41, 22)
connect _WIRE_302.ppn, _T_4135
wire _WIRE_304 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_305 : UInt<42>
connect _WIRE_305, sectored_entries[0][2].data[1]
node _T_4136 = bits(_WIRE_305, 0, 0)
connect _WIRE_304.fragmented_superpage, _T_4136
node _T_4137 = bits(_WIRE_305, 1, 1)
connect _WIRE_304.c, _T_4137
node _T_4138 = bits(_WIRE_305, 2, 2)
connect _WIRE_304.eff, _T_4138
node _T_4139 = bits(_WIRE_305, 3, 3)
connect _WIRE_304.paa, _T_4139
node _T_4140 = bits(_WIRE_305, 4, 4)
connect _WIRE_304.pal, _T_4140
node _T_4141 = bits(_WIRE_305, 5, 5)
connect _WIRE_304.ppp, _T_4141
node _T_4142 = bits(_WIRE_305, 6, 6)
connect _WIRE_304.pr, _T_4142
node _T_4143 = bits(_WIRE_305, 7, 7)
connect _WIRE_304.px, _T_4143
node _T_4144 = bits(_WIRE_305, 8, 8)
connect _WIRE_304.pw, _T_4144
node _T_4145 = bits(_WIRE_305, 9, 9)
connect _WIRE_304.hr, _T_4145
node _T_4146 = bits(_WIRE_305, 10, 10)
connect _WIRE_304.hx, _T_4146
node _T_4147 = bits(_WIRE_305, 11, 11)
connect _WIRE_304.hw, _T_4147
node _T_4148 = bits(_WIRE_305, 12, 12)
connect _WIRE_304.sr, _T_4148
node _T_4149 = bits(_WIRE_305, 13, 13)
connect _WIRE_304.sx, _T_4149
node _T_4150 = bits(_WIRE_305, 14, 14)
connect _WIRE_304.sw, _T_4150
node _T_4151 = bits(_WIRE_305, 15, 15)
connect _WIRE_304.gf, _T_4151
node _T_4152 = bits(_WIRE_305, 16, 16)
connect _WIRE_304.pf, _T_4152
node _T_4153 = bits(_WIRE_305, 17, 17)
connect _WIRE_304.ae_stage2, _T_4153
node _T_4154 = bits(_WIRE_305, 18, 18)
connect _WIRE_304.ae_final, _T_4154
node _T_4155 = bits(_WIRE_305, 19, 19)
connect _WIRE_304.ae_ptw, _T_4155
node _T_4156 = bits(_WIRE_305, 20, 20)
connect _WIRE_304.g, _T_4156
node _T_4157 = bits(_WIRE_305, 21, 21)
connect _WIRE_304.u, _T_4157
node _T_4158 = bits(_WIRE_305, 41, 22)
connect _WIRE_304.ppn, _T_4158
wire _WIRE_306 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_307 : UInt<42>
connect _WIRE_307, sectored_entries[0][2].data[2]
node _T_4159 = bits(_WIRE_307, 0, 0)
connect _WIRE_306.fragmented_superpage, _T_4159
node _T_4160 = bits(_WIRE_307, 1, 1)
connect _WIRE_306.c, _T_4160
node _T_4161 = bits(_WIRE_307, 2, 2)
connect _WIRE_306.eff, _T_4161
node _T_4162 = bits(_WIRE_307, 3, 3)
connect _WIRE_306.paa, _T_4162
node _T_4163 = bits(_WIRE_307, 4, 4)
connect _WIRE_306.pal, _T_4163
node _T_4164 = bits(_WIRE_307, 5, 5)
connect _WIRE_306.ppp, _T_4164
node _T_4165 = bits(_WIRE_307, 6, 6)
connect _WIRE_306.pr, _T_4165
node _T_4166 = bits(_WIRE_307, 7, 7)
connect _WIRE_306.px, _T_4166
node _T_4167 = bits(_WIRE_307, 8, 8)
connect _WIRE_306.pw, _T_4167
node _T_4168 = bits(_WIRE_307, 9, 9)
connect _WIRE_306.hr, _T_4168
node _T_4169 = bits(_WIRE_307, 10, 10)
connect _WIRE_306.hx, _T_4169
node _T_4170 = bits(_WIRE_307, 11, 11)
connect _WIRE_306.hw, _T_4170
node _T_4171 = bits(_WIRE_307, 12, 12)
connect _WIRE_306.sr, _T_4171
node _T_4172 = bits(_WIRE_307, 13, 13)
connect _WIRE_306.sx, _T_4172
node _T_4173 = bits(_WIRE_307, 14, 14)
connect _WIRE_306.sw, _T_4173
node _T_4174 = bits(_WIRE_307, 15, 15)
connect _WIRE_306.gf, _T_4174
node _T_4175 = bits(_WIRE_307, 16, 16)
connect _WIRE_306.pf, _T_4175
node _T_4176 = bits(_WIRE_307, 17, 17)
connect _WIRE_306.ae_stage2, _T_4176
node _T_4177 = bits(_WIRE_307, 18, 18)
connect _WIRE_306.ae_final, _T_4177
node _T_4178 = bits(_WIRE_307, 19, 19)
connect _WIRE_306.ae_ptw, _T_4178
node _T_4179 = bits(_WIRE_307, 20, 20)
connect _WIRE_306.g, _T_4179
node _T_4180 = bits(_WIRE_307, 21, 21)
connect _WIRE_306.u, _T_4180
node _T_4181 = bits(_WIRE_307, 41, 22)
connect _WIRE_306.ppn, _T_4181
wire _WIRE_308 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_309 : UInt<42>
connect _WIRE_309, sectored_entries[0][2].data[3]
node _T_4182 = bits(_WIRE_309, 0, 0)
connect _WIRE_308.fragmented_superpage, _T_4182
node _T_4183 = bits(_WIRE_309, 1, 1)
connect _WIRE_308.c, _T_4183
node _T_4184 = bits(_WIRE_309, 2, 2)
connect _WIRE_308.eff, _T_4184
node _T_4185 = bits(_WIRE_309, 3, 3)
connect _WIRE_308.paa, _T_4185
node _T_4186 = bits(_WIRE_309, 4, 4)
connect _WIRE_308.pal, _T_4186
node _T_4187 = bits(_WIRE_309, 5, 5)
connect _WIRE_308.ppp, _T_4187
node _T_4188 = bits(_WIRE_309, 6, 6)
connect _WIRE_308.pr, _T_4188
node _T_4189 = bits(_WIRE_309, 7, 7)
connect _WIRE_308.px, _T_4189
node _T_4190 = bits(_WIRE_309, 8, 8)
connect _WIRE_308.pw, _T_4190
node _T_4191 = bits(_WIRE_309, 9, 9)
connect _WIRE_308.hr, _T_4191
node _T_4192 = bits(_WIRE_309, 10, 10)
connect _WIRE_308.hx, _T_4192
node _T_4193 = bits(_WIRE_309, 11, 11)
connect _WIRE_308.hw, _T_4193
node _T_4194 = bits(_WIRE_309, 12, 12)
connect _WIRE_308.sr, _T_4194
node _T_4195 = bits(_WIRE_309, 13, 13)
connect _WIRE_308.sx, _T_4195
node _T_4196 = bits(_WIRE_309, 14, 14)
connect _WIRE_308.sw, _T_4196
node _T_4197 = bits(_WIRE_309, 15, 15)
connect _WIRE_308.gf, _T_4197
node _T_4198 = bits(_WIRE_309, 16, 16)
connect _WIRE_308.pf, _T_4198
node _T_4199 = bits(_WIRE_309, 17, 17)
connect _WIRE_308.ae_stage2, _T_4199
node _T_4200 = bits(_WIRE_309, 18, 18)
connect _WIRE_308.ae_final, _T_4200
node _T_4201 = bits(_WIRE_309, 19, 19)
connect _WIRE_308.ae_ptw, _T_4201
node _T_4202 = bits(_WIRE_309, 20, 20)
connect _WIRE_308.g, _T_4202
node _T_4203 = bits(_WIRE_309, 21, 21)
connect _WIRE_308.u, _T_4203
node _T_4204 = bits(_WIRE_309, 41, 22)
connect _WIRE_308.ppn, _T_4204
node _T_4205 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1))
when _T_4205 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
node _T_4206 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1))
when _T_4206 :
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
node _T_4207 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1))
when _T_4207 :
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
node _T_4208 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1))
when _T_4208 :
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
wire _WIRE_310 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_311 : UInt<42>
connect _WIRE_311, sectored_entries[0][3].data[0]
node _T_4209 = bits(_WIRE_311, 0, 0)
connect _WIRE_310.fragmented_superpage, _T_4209
node _T_4210 = bits(_WIRE_311, 1, 1)
connect _WIRE_310.c, _T_4210
node _T_4211 = bits(_WIRE_311, 2, 2)
connect _WIRE_310.eff, _T_4211
node _T_4212 = bits(_WIRE_311, 3, 3)
connect _WIRE_310.paa, _T_4212
node _T_4213 = bits(_WIRE_311, 4, 4)
connect _WIRE_310.pal, _T_4213
node _T_4214 = bits(_WIRE_311, 5, 5)
connect _WIRE_310.ppp, _T_4214
node _T_4215 = bits(_WIRE_311, 6, 6)
connect _WIRE_310.pr, _T_4215
node _T_4216 = bits(_WIRE_311, 7, 7)
connect _WIRE_310.px, _T_4216
node _T_4217 = bits(_WIRE_311, 8, 8)
connect _WIRE_310.pw, _T_4217
node _T_4218 = bits(_WIRE_311, 9, 9)
connect _WIRE_310.hr, _T_4218
node _T_4219 = bits(_WIRE_311, 10, 10)
connect _WIRE_310.hx, _T_4219
node _T_4220 = bits(_WIRE_311, 11, 11)
connect _WIRE_310.hw, _T_4220
node _T_4221 = bits(_WIRE_311, 12, 12)
connect _WIRE_310.sr, _T_4221
node _T_4222 = bits(_WIRE_311, 13, 13)
connect _WIRE_310.sx, _T_4222
node _T_4223 = bits(_WIRE_311, 14, 14)
connect _WIRE_310.sw, _T_4223
node _T_4224 = bits(_WIRE_311, 15, 15)
connect _WIRE_310.gf, _T_4224
node _T_4225 = bits(_WIRE_311, 16, 16)
connect _WIRE_310.pf, _T_4225
node _T_4226 = bits(_WIRE_311, 17, 17)
connect _WIRE_310.ae_stage2, _T_4226
node _T_4227 = bits(_WIRE_311, 18, 18)
connect _WIRE_310.ae_final, _T_4227
node _T_4228 = bits(_WIRE_311, 19, 19)
connect _WIRE_310.ae_ptw, _T_4228
node _T_4229 = bits(_WIRE_311, 20, 20)
connect _WIRE_310.g, _T_4229
node _T_4230 = bits(_WIRE_311, 21, 21)
connect _WIRE_310.u, _T_4230
node _T_4231 = bits(_WIRE_311, 41, 22)
connect _WIRE_310.ppn, _T_4231
wire _WIRE_312 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_313 : UInt<42>
connect _WIRE_313, sectored_entries[0][3].data[1]
node _T_4232 = bits(_WIRE_313, 0, 0)
connect _WIRE_312.fragmented_superpage, _T_4232
node _T_4233 = bits(_WIRE_313, 1, 1)
connect _WIRE_312.c, _T_4233
node _T_4234 = bits(_WIRE_313, 2, 2)
connect _WIRE_312.eff, _T_4234
node _T_4235 = bits(_WIRE_313, 3, 3)
connect _WIRE_312.paa, _T_4235
node _T_4236 = bits(_WIRE_313, 4, 4)
connect _WIRE_312.pal, _T_4236
node _T_4237 = bits(_WIRE_313, 5, 5)
connect _WIRE_312.ppp, _T_4237
node _T_4238 = bits(_WIRE_313, 6, 6)
connect _WIRE_312.pr, _T_4238
node _T_4239 = bits(_WIRE_313, 7, 7)
connect _WIRE_312.px, _T_4239
node _T_4240 = bits(_WIRE_313, 8, 8)
connect _WIRE_312.pw, _T_4240
node _T_4241 = bits(_WIRE_313, 9, 9)
connect _WIRE_312.hr, _T_4241
node _T_4242 = bits(_WIRE_313, 10, 10)
connect _WIRE_312.hx, _T_4242
node _T_4243 = bits(_WIRE_313, 11, 11)
connect _WIRE_312.hw, _T_4243
node _T_4244 = bits(_WIRE_313, 12, 12)
connect _WIRE_312.sr, _T_4244
node _T_4245 = bits(_WIRE_313, 13, 13)
connect _WIRE_312.sx, _T_4245
node _T_4246 = bits(_WIRE_313, 14, 14)
connect _WIRE_312.sw, _T_4246
node _T_4247 = bits(_WIRE_313, 15, 15)
connect _WIRE_312.gf, _T_4247
node _T_4248 = bits(_WIRE_313, 16, 16)
connect _WIRE_312.pf, _T_4248
node _T_4249 = bits(_WIRE_313, 17, 17)
connect _WIRE_312.ae_stage2, _T_4249
node _T_4250 = bits(_WIRE_313, 18, 18)
connect _WIRE_312.ae_final, _T_4250
node _T_4251 = bits(_WIRE_313, 19, 19)
connect _WIRE_312.ae_ptw, _T_4251
node _T_4252 = bits(_WIRE_313, 20, 20)
connect _WIRE_312.g, _T_4252
node _T_4253 = bits(_WIRE_313, 21, 21)
connect _WIRE_312.u, _T_4253
node _T_4254 = bits(_WIRE_313, 41, 22)
connect _WIRE_312.ppn, _T_4254
wire _WIRE_314 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_315 : UInt<42>
connect _WIRE_315, sectored_entries[0][3].data[2]
node _T_4255 = bits(_WIRE_315, 0, 0)
connect _WIRE_314.fragmented_superpage, _T_4255
node _T_4256 = bits(_WIRE_315, 1, 1)
connect _WIRE_314.c, _T_4256
node _T_4257 = bits(_WIRE_315, 2, 2)
connect _WIRE_314.eff, _T_4257
node _T_4258 = bits(_WIRE_315, 3, 3)
connect _WIRE_314.paa, _T_4258
node _T_4259 = bits(_WIRE_315, 4, 4)
connect _WIRE_314.pal, _T_4259
node _T_4260 = bits(_WIRE_315, 5, 5)
connect _WIRE_314.ppp, _T_4260
node _T_4261 = bits(_WIRE_315, 6, 6)
connect _WIRE_314.pr, _T_4261
node _T_4262 = bits(_WIRE_315, 7, 7)
connect _WIRE_314.px, _T_4262
node _T_4263 = bits(_WIRE_315, 8, 8)
connect _WIRE_314.pw, _T_4263
node _T_4264 = bits(_WIRE_315, 9, 9)
connect _WIRE_314.hr, _T_4264
node _T_4265 = bits(_WIRE_315, 10, 10)
connect _WIRE_314.hx, _T_4265
node _T_4266 = bits(_WIRE_315, 11, 11)
connect _WIRE_314.hw, _T_4266
node _T_4267 = bits(_WIRE_315, 12, 12)
connect _WIRE_314.sr, _T_4267
node _T_4268 = bits(_WIRE_315, 13, 13)
connect _WIRE_314.sx, _T_4268
node _T_4269 = bits(_WIRE_315, 14, 14)
connect _WIRE_314.sw, _T_4269
node _T_4270 = bits(_WIRE_315, 15, 15)
connect _WIRE_314.gf, _T_4270
node _T_4271 = bits(_WIRE_315, 16, 16)
connect _WIRE_314.pf, _T_4271
node _T_4272 = bits(_WIRE_315, 17, 17)
connect _WIRE_314.ae_stage2, _T_4272
node _T_4273 = bits(_WIRE_315, 18, 18)
connect _WIRE_314.ae_final, _T_4273
node _T_4274 = bits(_WIRE_315, 19, 19)
connect _WIRE_314.ae_ptw, _T_4274
node _T_4275 = bits(_WIRE_315, 20, 20)
connect _WIRE_314.g, _T_4275
node _T_4276 = bits(_WIRE_315, 21, 21)
connect _WIRE_314.u, _T_4276
node _T_4277 = bits(_WIRE_315, 41, 22)
connect _WIRE_314.ppn, _T_4277
wire _WIRE_316 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_317 : UInt<42>
connect _WIRE_317, sectored_entries[0][3].data[3]
node _T_4278 = bits(_WIRE_317, 0, 0)
connect _WIRE_316.fragmented_superpage, _T_4278
node _T_4279 = bits(_WIRE_317, 1, 1)
connect _WIRE_316.c, _T_4279
node _T_4280 = bits(_WIRE_317, 2, 2)
connect _WIRE_316.eff, _T_4280
node _T_4281 = bits(_WIRE_317, 3, 3)
connect _WIRE_316.paa, _T_4281
node _T_4282 = bits(_WIRE_317, 4, 4)
connect _WIRE_316.pal, _T_4282
node _T_4283 = bits(_WIRE_317, 5, 5)
connect _WIRE_316.ppp, _T_4283
node _T_4284 = bits(_WIRE_317, 6, 6)
connect _WIRE_316.pr, _T_4284
node _T_4285 = bits(_WIRE_317, 7, 7)
connect _WIRE_316.px, _T_4285
node _T_4286 = bits(_WIRE_317, 8, 8)
connect _WIRE_316.pw, _T_4286
node _T_4287 = bits(_WIRE_317, 9, 9)
connect _WIRE_316.hr, _T_4287
node _T_4288 = bits(_WIRE_317, 10, 10)
connect _WIRE_316.hx, _T_4288
node _T_4289 = bits(_WIRE_317, 11, 11)
connect _WIRE_316.hw, _T_4289
node _T_4290 = bits(_WIRE_317, 12, 12)
connect _WIRE_316.sr, _T_4290
node _T_4291 = bits(_WIRE_317, 13, 13)
connect _WIRE_316.sx, _T_4291
node _T_4292 = bits(_WIRE_317, 14, 14)
connect _WIRE_316.sw, _T_4292
node _T_4293 = bits(_WIRE_317, 15, 15)
connect _WIRE_316.gf, _T_4293
node _T_4294 = bits(_WIRE_317, 16, 16)
connect _WIRE_316.pf, _T_4294
node _T_4295 = bits(_WIRE_317, 17, 17)
connect _WIRE_316.ae_stage2, _T_4295
node _T_4296 = bits(_WIRE_317, 18, 18)
connect _WIRE_316.ae_final, _T_4296
node _T_4297 = bits(_WIRE_317, 19, 19)
connect _WIRE_316.ae_ptw, _T_4297
node _T_4298 = bits(_WIRE_317, 20, 20)
connect _WIRE_316.g, _T_4298
node _T_4299 = bits(_WIRE_317, 21, 21)
connect _WIRE_316.u, _T_4299
node _T_4300 = bits(_WIRE_317, 41, 22)
connect _WIRE_316.ppn, _T_4300
node _T_4301 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1))
when _T_4301 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
node _T_4302 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1))
when _T_4302 :
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
node _T_4303 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1))
when _T_4303 :
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
node _T_4304 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1))
when _T_4304 :
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
wire _WIRE_318 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_319 : UInt<42>
connect _WIRE_319, sectored_entries[0][4].data[0]
node _T_4305 = bits(_WIRE_319, 0, 0)
connect _WIRE_318.fragmented_superpage, _T_4305
node _T_4306 = bits(_WIRE_319, 1, 1)
connect _WIRE_318.c, _T_4306
node _T_4307 = bits(_WIRE_319, 2, 2)
connect _WIRE_318.eff, _T_4307
node _T_4308 = bits(_WIRE_319, 3, 3)
connect _WIRE_318.paa, _T_4308
node _T_4309 = bits(_WIRE_319, 4, 4)
connect _WIRE_318.pal, _T_4309
node _T_4310 = bits(_WIRE_319, 5, 5)
connect _WIRE_318.ppp, _T_4310
node _T_4311 = bits(_WIRE_319, 6, 6)
connect _WIRE_318.pr, _T_4311
node _T_4312 = bits(_WIRE_319, 7, 7)
connect _WIRE_318.px, _T_4312
node _T_4313 = bits(_WIRE_319, 8, 8)
connect _WIRE_318.pw, _T_4313
node _T_4314 = bits(_WIRE_319, 9, 9)
connect _WIRE_318.hr, _T_4314
node _T_4315 = bits(_WIRE_319, 10, 10)
connect _WIRE_318.hx, _T_4315
node _T_4316 = bits(_WIRE_319, 11, 11)
connect _WIRE_318.hw, _T_4316
node _T_4317 = bits(_WIRE_319, 12, 12)
connect _WIRE_318.sr, _T_4317
node _T_4318 = bits(_WIRE_319, 13, 13)
connect _WIRE_318.sx, _T_4318
node _T_4319 = bits(_WIRE_319, 14, 14)
connect _WIRE_318.sw, _T_4319
node _T_4320 = bits(_WIRE_319, 15, 15)
connect _WIRE_318.gf, _T_4320
node _T_4321 = bits(_WIRE_319, 16, 16)
connect _WIRE_318.pf, _T_4321
node _T_4322 = bits(_WIRE_319, 17, 17)
connect _WIRE_318.ae_stage2, _T_4322
node _T_4323 = bits(_WIRE_319, 18, 18)
connect _WIRE_318.ae_final, _T_4323
node _T_4324 = bits(_WIRE_319, 19, 19)
connect _WIRE_318.ae_ptw, _T_4324
node _T_4325 = bits(_WIRE_319, 20, 20)
connect _WIRE_318.g, _T_4325
node _T_4326 = bits(_WIRE_319, 21, 21)
connect _WIRE_318.u, _T_4326
node _T_4327 = bits(_WIRE_319, 41, 22)
connect _WIRE_318.ppn, _T_4327
wire _WIRE_320 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_321 : UInt<42>
connect _WIRE_321, sectored_entries[0][4].data[1]
node _T_4328 = bits(_WIRE_321, 0, 0)
connect _WIRE_320.fragmented_superpage, _T_4328
node _T_4329 = bits(_WIRE_321, 1, 1)
connect _WIRE_320.c, _T_4329
node _T_4330 = bits(_WIRE_321, 2, 2)
connect _WIRE_320.eff, _T_4330
node _T_4331 = bits(_WIRE_321, 3, 3)
connect _WIRE_320.paa, _T_4331
node _T_4332 = bits(_WIRE_321, 4, 4)
connect _WIRE_320.pal, _T_4332
node _T_4333 = bits(_WIRE_321, 5, 5)
connect _WIRE_320.ppp, _T_4333
node _T_4334 = bits(_WIRE_321, 6, 6)
connect _WIRE_320.pr, _T_4334
node _T_4335 = bits(_WIRE_321, 7, 7)
connect _WIRE_320.px, _T_4335
node _T_4336 = bits(_WIRE_321, 8, 8)
connect _WIRE_320.pw, _T_4336
node _T_4337 = bits(_WIRE_321, 9, 9)
connect _WIRE_320.hr, _T_4337
node _T_4338 = bits(_WIRE_321, 10, 10)
connect _WIRE_320.hx, _T_4338
node _T_4339 = bits(_WIRE_321, 11, 11)
connect _WIRE_320.hw, _T_4339
node _T_4340 = bits(_WIRE_321, 12, 12)
connect _WIRE_320.sr, _T_4340
node _T_4341 = bits(_WIRE_321, 13, 13)
connect _WIRE_320.sx, _T_4341
node _T_4342 = bits(_WIRE_321, 14, 14)
connect _WIRE_320.sw, _T_4342
node _T_4343 = bits(_WIRE_321, 15, 15)
connect _WIRE_320.gf, _T_4343
node _T_4344 = bits(_WIRE_321, 16, 16)
connect _WIRE_320.pf, _T_4344
node _T_4345 = bits(_WIRE_321, 17, 17)
connect _WIRE_320.ae_stage2, _T_4345
node _T_4346 = bits(_WIRE_321, 18, 18)
connect _WIRE_320.ae_final, _T_4346
node _T_4347 = bits(_WIRE_321, 19, 19)
connect _WIRE_320.ae_ptw, _T_4347
node _T_4348 = bits(_WIRE_321, 20, 20)
connect _WIRE_320.g, _T_4348
node _T_4349 = bits(_WIRE_321, 21, 21)
connect _WIRE_320.u, _T_4349
node _T_4350 = bits(_WIRE_321, 41, 22)
connect _WIRE_320.ppn, _T_4350
wire _WIRE_322 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_323 : UInt<42>
connect _WIRE_323, sectored_entries[0][4].data[2]
node _T_4351 = bits(_WIRE_323, 0, 0)
connect _WIRE_322.fragmented_superpage, _T_4351
node _T_4352 = bits(_WIRE_323, 1, 1)
connect _WIRE_322.c, _T_4352
node _T_4353 = bits(_WIRE_323, 2, 2)
connect _WIRE_322.eff, _T_4353
node _T_4354 = bits(_WIRE_323, 3, 3)
connect _WIRE_322.paa, _T_4354
node _T_4355 = bits(_WIRE_323, 4, 4)
connect _WIRE_322.pal, _T_4355
node _T_4356 = bits(_WIRE_323, 5, 5)
connect _WIRE_322.ppp, _T_4356
node _T_4357 = bits(_WIRE_323, 6, 6)
connect _WIRE_322.pr, _T_4357
node _T_4358 = bits(_WIRE_323, 7, 7)
connect _WIRE_322.px, _T_4358
node _T_4359 = bits(_WIRE_323, 8, 8)
connect _WIRE_322.pw, _T_4359
node _T_4360 = bits(_WIRE_323, 9, 9)
connect _WIRE_322.hr, _T_4360
node _T_4361 = bits(_WIRE_323, 10, 10)
connect _WIRE_322.hx, _T_4361
node _T_4362 = bits(_WIRE_323, 11, 11)
connect _WIRE_322.hw, _T_4362
node _T_4363 = bits(_WIRE_323, 12, 12)
connect _WIRE_322.sr, _T_4363
node _T_4364 = bits(_WIRE_323, 13, 13)
connect _WIRE_322.sx, _T_4364
node _T_4365 = bits(_WIRE_323, 14, 14)
connect _WIRE_322.sw, _T_4365
node _T_4366 = bits(_WIRE_323, 15, 15)
connect _WIRE_322.gf, _T_4366
node _T_4367 = bits(_WIRE_323, 16, 16)
connect _WIRE_322.pf, _T_4367
node _T_4368 = bits(_WIRE_323, 17, 17)
connect _WIRE_322.ae_stage2, _T_4368
node _T_4369 = bits(_WIRE_323, 18, 18)
connect _WIRE_322.ae_final, _T_4369
node _T_4370 = bits(_WIRE_323, 19, 19)
connect _WIRE_322.ae_ptw, _T_4370
node _T_4371 = bits(_WIRE_323, 20, 20)
connect _WIRE_322.g, _T_4371
node _T_4372 = bits(_WIRE_323, 21, 21)
connect _WIRE_322.u, _T_4372
node _T_4373 = bits(_WIRE_323, 41, 22)
connect _WIRE_322.ppn, _T_4373
wire _WIRE_324 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_325 : UInt<42>
connect _WIRE_325, sectored_entries[0][4].data[3]
node _T_4374 = bits(_WIRE_325, 0, 0)
connect _WIRE_324.fragmented_superpage, _T_4374
node _T_4375 = bits(_WIRE_325, 1, 1)
connect _WIRE_324.c, _T_4375
node _T_4376 = bits(_WIRE_325, 2, 2)
connect _WIRE_324.eff, _T_4376
node _T_4377 = bits(_WIRE_325, 3, 3)
connect _WIRE_324.paa, _T_4377
node _T_4378 = bits(_WIRE_325, 4, 4)
connect _WIRE_324.pal, _T_4378
node _T_4379 = bits(_WIRE_325, 5, 5)
connect _WIRE_324.ppp, _T_4379
node _T_4380 = bits(_WIRE_325, 6, 6)
connect _WIRE_324.pr, _T_4380
node _T_4381 = bits(_WIRE_325, 7, 7)
connect _WIRE_324.px, _T_4381
node _T_4382 = bits(_WIRE_325, 8, 8)
connect _WIRE_324.pw, _T_4382
node _T_4383 = bits(_WIRE_325, 9, 9)
connect _WIRE_324.hr, _T_4383
node _T_4384 = bits(_WIRE_325, 10, 10)
connect _WIRE_324.hx, _T_4384
node _T_4385 = bits(_WIRE_325, 11, 11)
connect _WIRE_324.hw, _T_4385
node _T_4386 = bits(_WIRE_325, 12, 12)
connect _WIRE_324.sr, _T_4386
node _T_4387 = bits(_WIRE_325, 13, 13)
connect _WIRE_324.sx, _T_4387
node _T_4388 = bits(_WIRE_325, 14, 14)
connect _WIRE_324.sw, _T_4388
node _T_4389 = bits(_WIRE_325, 15, 15)
connect _WIRE_324.gf, _T_4389
node _T_4390 = bits(_WIRE_325, 16, 16)
connect _WIRE_324.pf, _T_4390
node _T_4391 = bits(_WIRE_325, 17, 17)
connect _WIRE_324.ae_stage2, _T_4391
node _T_4392 = bits(_WIRE_325, 18, 18)
connect _WIRE_324.ae_final, _T_4392
node _T_4393 = bits(_WIRE_325, 19, 19)
connect _WIRE_324.ae_ptw, _T_4393
node _T_4394 = bits(_WIRE_325, 20, 20)
connect _WIRE_324.g, _T_4394
node _T_4395 = bits(_WIRE_325, 21, 21)
connect _WIRE_324.u, _T_4395
node _T_4396 = bits(_WIRE_325, 41, 22)
connect _WIRE_324.ppn, _T_4396
node _T_4397 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1))
when _T_4397 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
node _T_4398 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1))
when _T_4398 :
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
node _T_4399 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1))
when _T_4399 :
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
node _T_4400 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1))
when _T_4400 :
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
wire _WIRE_326 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_327 : UInt<42>
connect _WIRE_327, sectored_entries[0][5].data[0]
node _T_4401 = bits(_WIRE_327, 0, 0)
connect _WIRE_326.fragmented_superpage, _T_4401
node _T_4402 = bits(_WIRE_327, 1, 1)
connect _WIRE_326.c, _T_4402
node _T_4403 = bits(_WIRE_327, 2, 2)
connect _WIRE_326.eff, _T_4403
node _T_4404 = bits(_WIRE_327, 3, 3)
connect _WIRE_326.paa, _T_4404
node _T_4405 = bits(_WIRE_327, 4, 4)
connect _WIRE_326.pal, _T_4405
node _T_4406 = bits(_WIRE_327, 5, 5)
connect _WIRE_326.ppp, _T_4406
node _T_4407 = bits(_WIRE_327, 6, 6)
connect _WIRE_326.pr, _T_4407
node _T_4408 = bits(_WIRE_327, 7, 7)
connect _WIRE_326.px, _T_4408
node _T_4409 = bits(_WIRE_327, 8, 8)
connect _WIRE_326.pw, _T_4409
node _T_4410 = bits(_WIRE_327, 9, 9)
connect _WIRE_326.hr, _T_4410
node _T_4411 = bits(_WIRE_327, 10, 10)
connect _WIRE_326.hx, _T_4411
node _T_4412 = bits(_WIRE_327, 11, 11)
connect _WIRE_326.hw, _T_4412
node _T_4413 = bits(_WIRE_327, 12, 12)
connect _WIRE_326.sr, _T_4413
node _T_4414 = bits(_WIRE_327, 13, 13)
connect _WIRE_326.sx, _T_4414
node _T_4415 = bits(_WIRE_327, 14, 14)
connect _WIRE_326.sw, _T_4415
node _T_4416 = bits(_WIRE_327, 15, 15)
connect _WIRE_326.gf, _T_4416
node _T_4417 = bits(_WIRE_327, 16, 16)
connect _WIRE_326.pf, _T_4417
node _T_4418 = bits(_WIRE_327, 17, 17)
connect _WIRE_326.ae_stage2, _T_4418
node _T_4419 = bits(_WIRE_327, 18, 18)
connect _WIRE_326.ae_final, _T_4419
node _T_4420 = bits(_WIRE_327, 19, 19)
connect _WIRE_326.ae_ptw, _T_4420
node _T_4421 = bits(_WIRE_327, 20, 20)
connect _WIRE_326.g, _T_4421
node _T_4422 = bits(_WIRE_327, 21, 21)
connect _WIRE_326.u, _T_4422
node _T_4423 = bits(_WIRE_327, 41, 22)
connect _WIRE_326.ppn, _T_4423
wire _WIRE_328 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_329 : UInt<42>
connect _WIRE_329, sectored_entries[0][5].data[1]
node _T_4424 = bits(_WIRE_329, 0, 0)
connect _WIRE_328.fragmented_superpage, _T_4424
node _T_4425 = bits(_WIRE_329, 1, 1)
connect _WIRE_328.c, _T_4425
node _T_4426 = bits(_WIRE_329, 2, 2)
connect _WIRE_328.eff, _T_4426
node _T_4427 = bits(_WIRE_329, 3, 3)
connect _WIRE_328.paa, _T_4427
node _T_4428 = bits(_WIRE_329, 4, 4)
connect _WIRE_328.pal, _T_4428
node _T_4429 = bits(_WIRE_329, 5, 5)
connect _WIRE_328.ppp, _T_4429
node _T_4430 = bits(_WIRE_329, 6, 6)
connect _WIRE_328.pr, _T_4430
node _T_4431 = bits(_WIRE_329, 7, 7)
connect _WIRE_328.px, _T_4431
node _T_4432 = bits(_WIRE_329, 8, 8)
connect _WIRE_328.pw, _T_4432
node _T_4433 = bits(_WIRE_329, 9, 9)
connect _WIRE_328.hr, _T_4433
node _T_4434 = bits(_WIRE_329, 10, 10)
connect _WIRE_328.hx, _T_4434
node _T_4435 = bits(_WIRE_329, 11, 11)
connect _WIRE_328.hw, _T_4435
node _T_4436 = bits(_WIRE_329, 12, 12)
connect _WIRE_328.sr, _T_4436
node _T_4437 = bits(_WIRE_329, 13, 13)
connect _WIRE_328.sx, _T_4437
node _T_4438 = bits(_WIRE_329, 14, 14)
connect _WIRE_328.sw, _T_4438
node _T_4439 = bits(_WIRE_329, 15, 15)
connect _WIRE_328.gf, _T_4439
node _T_4440 = bits(_WIRE_329, 16, 16)
connect _WIRE_328.pf, _T_4440
node _T_4441 = bits(_WIRE_329, 17, 17)
connect _WIRE_328.ae_stage2, _T_4441
node _T_4442 = bits(_WIRE_329, 18, 18)
connect _WIRE_328.ae_final, _T_4442
node _T_4443 = bits(_WIRE_329, 19, 19)
connect _WIRE_328.ae_ptw, _T_4443
node _T_4444 = bits(_WIRE_329, 20, 20)
connect _WIRE_328.g, _T_4444
node _T_4445 = bits(_WIRE_329, 21, 21)
connect _WIRE_328.u, _T_4445
node _T_4446 = bits(_WIRE_329, 41, 22)
connect _WIRE_328.ppn, _T_4446
wire _WIRE_330 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_331 : UInt<42>
connect _WIRE_331, sectored_entries[0][5].data[2]
node _T_4447 = bits(_WIRE_331, 0, 0)
connect _WIRE_330.fragmented_superpage, _T_4447
node _T_4448 = bits(_WIRE_331, 1, 1)
connect _WIRE_330.c, _T_4448
node _T_4449 = bits(_WIRE_331, 2, 2)
connect _WIRE_330.eff, _T_4449
node _T_4450 = bits(_WIRE_331, 3, 3)
connect _WIRE_330.paa, _T_4450
node _T_4451 = bits(_WIRE_331, 4, 4)
connect _WIRE_330.pal, _T_4451
node _T_4452 = bits(_WIRE_331, 5, 5)
connect _WIRE_330.ppp, _T_4452
node _T_4453 = bits(_WIRE_331, 6, 6)
connect _WIRE_330.pr, _T_4453
node _T_4454 = bits(_WIRE_331, 7, 7)
connect _WIRE_330.px, _T_4454
node _T_4455 = bits(_WIRE_331, 8, 8)
connect _WIRE_330.pw, _T_4455
node _T_4456 = bits(_WIRE_331, 9, 9)
connect _WIRE_330.hr, _T_4456
node _T_4457 = bits(_WIRE_331, 10, 10)
connect _WIRE_330.hx, _T_4457
node _T_4458 = bits(_WIRE_331, 11, 11)
connect _WIRE_330.hw, _T_4458
node _T_4459 = bits(_WIRE_331, 12, 12)
connect _WIRE_330.sr, _T_4459
node _T_4460 = bits(_WIRE_331, 13, 13)
connect _WIRE_330.sx, _T_4460
node _T_4461 = bits(_WIRE_331, 14, 14)
connect _WIRE_330.sw, _T_4461
node _T_4462 = bits(_WIRE_331, 15, 15)
connect _WIRE_330.gf, _T_4462
node _T_4463 = bits(_WIRE_331, 16, 16)
connect _WIRE_330.pf, _T_4463
node _T_4464 = bits(_WIRE_331, 17, 17)
connect _WIRE_330.ae_stage2, _T_4464
node _T_4465 = bits(_WIRE_331, 18, 18)
connect _WIRE_330.ae_final, _T_4465
node _T_4466 = bits(_WIRE_331, 19, 19)
connect _WIRE_330.ae_ptw, _T_4466
node _T_4467 = bits(_WIRE_331, 20, 20)
connect _WIRE_330.g, _T_4467
node _T_4468 = bits(_WIRE_331, 21, 21)
connect _WIRE_330.u, _T_4468
node _T_4469 = bits(_WIRE_331, 41, 22)
connect _WIRE_330.ppn, _T_4469
wire _WIRE_332 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_333 : UInt<42>
connect _WIRE_333, sectored_entries[0][5].data[3]
node _T_4470 = bits(_WIRE_333, 0, 0)
connect _WIRE_332.fragmented_superpage, _T_4470
node _T_4471 = bits(_WIRE_333, 1, 1)
connect _WIRE_332.c, _T_4471
node _T_4472 = bits(_WIRE_333, 2, 2)
connect _WIRE_332.eff, _T_4472
node _T_4473 = bits(_WIRE_333, 3, 3)
connect _WIRE_332.paa, _T_4473
node _T_4474 = bits(_WIRE_333, 4, 4)
connect _WIRE_332.pal, _T_4474
node _T_4475 = bits(_WIRE_333, 5, 5)
connect _WIRE_332.ppp, _T_4475
node _T_4476 = bits(_WIRE_333, 6, 6)
connect _WIRE_332.pr, _T_4476
node _T_4477 = bits(_WIRE_333, 7, 7)
connect _WIRE_332.px, _T_4477
node _T_4478 = bits(_WIRE_333, 8, 8)
connect _WIRE_332.pw, _T_4478
node _T_4479 = bits(_WIRE_333, 9, 9)
connect _WIRE_332.hr, _T_4479
node _T_4480 = bits(_WIRE_333, 10, 10)
connect _WIRE_332.hx, _T_4480
node _T_4481 = bits(_WIRE_333, 11, 11)
connect _WIRE_332.hw, _T_4481
node _T_4482 = bits(_WIRE_333, 12, 12)
connect _WIRE_332.sr, _T_4482
node _T_4483 = bits(_WIRE_333, 13, 13)
connect _WIRE_332.sx, _T_4483
node _T_4484 = bits(_WIRE_333, 14, 14)
connect _WIRE_332.sw, _T_4484
node _T_4485 = bits(_WIRE_333, 15, 15)
connect _WIRE_332.gf, _T_4485
node _T_4486 = bits(_WIRE_333, 16, 16)
connect _WIRE_332.pf, _T_4486
node _T_4487 = bits(_WIRE_333, 17, 17)
connect _WIRE_332.ae_stage2, _T_4487
node _T_4488 = bits(_WIRE_333, 18, 18)
connect _WIRE_332.ae_final, _T_4488
node _T_4489 = bits(_WIRE_333, 19, 19)
connect _WIRE_332.ae_ptw, _T_4489
node _T_4490 = bits(_WIRE_333, 20, 20)
connect _WIRE_332.g, _T_4490
node _T_4491 = bits(_WIRE_333, 21, 21)
connect _WIRE_332.u, _T_4491
node _T_4492 = bits(_WIRE_333, 41, 22)
connect _WIRE_332.ppn, _T_4492
node _T_4493 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1))
when _T_4493 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
node _T_4494 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1))
when _T_4494 :
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
node _T_4495 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1))
when _T_4495 :
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
node _T_4496 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1))
when _T_4496 :
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
wire _WIRE_334 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_335 : UInt<42>
connect _WIRE_335, sectored_entries[0][6].data[0]
node _T_4497 = bits(_WIRE_335, 0, 0)
connect _WIRE_334.fragmented_superpage, _T_4497
node _T_4498 = bits(_WIRE_335, 1, 1)
connect _WIRE_334.c, _T_4498
node _T_4499 = bits(_WIRE_335, 2, 2)
connect _WIRE_334.eff, _T_4499
node _T_4500 = bits(_WIRE_335, 3, 3)
connect _WIRE_334.paa, _T_4500
node _T_4501 = bits(_WIRE_335, 4, 4)
connect _WIRE_334.pal, _T_4501
node _T_4502 = bits(_WIRE_335, 5, 5)
connect _WIRE_334.ppp, _T_4502
node _T_4503 = bits(_WIRE_335, 6, 6)
connect _WIRE_334.pr, _T_4503
node _T_4504 = bits(_WIRE_335, 7, 7)
connect _WIRE_334.px, _T_4504
node _T_4505 = bits(_WIRE_335, 8, 8)
connect _WIRE_334.pw, _T_4505
node _T_4506 = bits(_WIRE_335, 9, 9)
connect _WIRE_334.hr, _T_4506
node _T_4507 = bits(_WIRE_335, 10, 10)
connect _WIRE_334.hx, _T_4507
node _T_4508 = bits(_WIRE_335, 11, 11)
connect _WIRE_334.hw, _T_4508
node _T_4509 = bits(_WIRE_335, 12, 12)
connect _WIRE_334.sr, _T_4509
node _T_4510 = bits(_WIRE_335, 13, 13)
connect _WIRE_334.sx, _T_4510
node _T_4511 = bits(_WIRE_335, 14, 14)
connect _WIRE_334.sw, _T_4511
node _T_4512 = bits(_WIRE_335, 15, 15)
connect _WIRE_334.gf, _T_4512
node _T_4513 = bits(_WIRE_335, 16, 16)
connect _WIRE_334.pf, _T_4513
node _T_4514 = bits(_WIRE_335, 17, 17)
connect _WIRE_334.ae_stage2, _T_4514
node _T_4515 = bits(_WIRE_335, 18, 18)
connect _WIRE_334.ae_final, _T_4515
node _T_4516 = bits(_WIRE_335, 19, 19)
connect _WIRE_334.ae_ptw, _T_4516
node _T_4517 = bits(_WIRE_335, 20, 20)
connect _WIRE_334.g, _T_4517
node _T_4518 = bits(_WIRE_335, 21, 21)
connect _WIRE_334.u, _T_4518
node _T_4519 = bits(_WIRE_335, 41, 22)
connect _WIRE_334.ppn, _T_4519
wire _WIRE_336 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_337 : UInt<42>
connect _WIRE_337, sectored_entries[0][6].data[1]
node _T_4520 = bits(_WIRE_337, 0, 0)
connect _WIRE_336.fragmented_superpage, _T_4520
node _T_4521 = bits(_WIRE_337, 1, 1)
connect _WIRE_336.c, _T_4521
node _T_4522 = bits(_WIRE_337, 2, 2)
connect _WIRE_336.eff, _T_4522
node _T_4523 = bits(_WIRE_337, 3, 3)
connect _WIRE_336.paa, _T_4523
node _T_4524 = bits(_WIRE_337, 4, 4)
connect _WIRE_336.pal, _T_4524
node _T_4525 = bits(_WIRE_337, 5, 5)
connect _WIRE_336.ppp, _T_4525
node _T_4526 = bits(_WIRE_337, 6, 6)
connect _WIRE_336.pr, _T_4526
node _T_4527 = bits(_WIRE_337, 7, 7)
connect _WIRE_336.px, _T_4527
node _T_4528 = bits(_WIRE_337, 8, 8)
connect _WIRE_336.pw, _T_4528
node _T_4529 = bits(_WIRE_337, 9, 9)
connect _WIRE_336.hr, _T_4529
node _T_4530 = bits(_WIRE_337, 10, 10)
connect _WIRE_336.hx, _T_4530
node _T_4531 = bits(_WIRE_337, 11, 11)
connect _WIRE_336.hw, _T_4531
node _T_4532 = bits(_WIRE_337, 12, 12)
connect _WIRE_336.sr, _T_4532
node _T_4533 = bits(_WIRE_337, 13, 13)
connect _WIRE_336.sx, _T_4533
node _T_4534 = bits(_WIRE_337, 14, 14)
connect _WIRE_336.sw, _T_4534
node _T_4535 = bits(_WIRE_337, 15, 15)
connect _WIRE_336.gf, _T_4535
node _T_4536 = bits(_WIRE_337, 16, 16)
connect _WIRE_336.pf, _T_4536
node _T_4537 = bits(_WIRE_337, 17, 17)
connect _WIRE_336.ae_stage2, _T_4537
node _T_4538 = bits(_WIRE_337, 18, 18)
connect _WIRE_336.ae_final, _T_4538
node _T_4539 = bits(_WIRE_337, 19, 19)
connect _WIRE_336.ae_ptw, _T_4539
node _T_4540 = bits(_WIRE_337, 20, 20)
connect _WIRE_336.g, _T_4540
node _T_4541 = bits(_WIRE_337, 21, 21)
connect _WIRE_336.u, _T_4541
node _T_4542 = bits(_WIRE_337, 41, 22)
connect _WIRE_336.ppn, _T_4542
wire _WIRE_338 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_339 : UInt<42>
connect _WIRE_339, sectored_entries[0][6].data[2]
node _T_4543 = bits(_WIRE_339, 0, 0)
connect _WIRE_338.fragmented_superpage, _T_4543
node _T_4544 = bits(_WIRE_339, 1, 1)
connect _WIRE_338.c, _T_4544
node _T_4545 = bits(_WIRE_339, 2, 2)
connect _WIRE_338.eff, _T_4545
node _T_4546 = bits(_WIRE_339, 3, 3)
connect _WIRE_338.paa, _T_4546
node _T_4547 = bits(_WIRE_339, 4, 4)
connect _WIRE_338.pal, _T_4547
node _T_4548 = bits(_WIRE_339, 5, 5)
connect _WIRE_338.ppp, _T_4548
node _T_4549 = bits(_WIRE_339, 6, 6)
connect _WIRE_338.pr, _T_4549
node _T_4550 = bits(_WIRE_339, 7, 7)
connect _WIRE_338.px, _T_4550
node _T_4551 = bits(_WIRE_339, 8, 8)
connect _WIRE_338.pw, _T_4551
node _T_4552 = bits(_WIRE_339, 9, 9)
connect _WIRE_338.hr, _T_4552
node _T_4553 = bits(_WIRE_339, 10, 10)
connect _WIRE_338.hx, _T_4553
node _T_4554 = bits(_WIRE_339, 11, 11)
connect _WIRE_338.hw, _T_4554
node _T_4555 = bits(_WIRE_339, 12, 12)
connect _WIRE_338.sr, _T_4555
node _T_4556 = bits(_WIRE_339, 13, 13)
connect _WIRE_338.sx, _T_4556
node _T_4557 = bits(_WIRE_339, 14, 14)
connect _WIRE_338.sw, _T_4557
node _T_4558 = bits(_WIRE_339, 15, 15)
connect _WIRE_338.gf, _T_4558
node _T_4559 = bits(_WIRE_339, 16, 16)
connect _WIRE_338.pf, _T_4559
node _T_4560 = bits(_WIRE_339, 17, 17)
connect _WIRE_338.ae_stage2, _T_4560
node _T_4561 = bits(_WIRE_339, 18, 18)
connect _WIRE_338.ae_final, _T_4561
node _T_4562 = bits(_WIRE_339, 19, 19)
connect _WIRE_338.ae_ptw, _T_4562
node _T_4563 = bits(_WIRE_339, 20, 20)
connect _WIRE_338.g, _T_4563
node _T_4564 = bits(_WIRE_339, 21, 21)
connect _WIRE_338.u, _T_4564
node _T_4565 = bits(_WIRE_339, 41, 22)
connect _WIRE_338.ppn, _T_4565
wire _WIRE_340 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_341 : UInt<42>
connect _WIRE_341, sectored_entries[0][6].data[3]
node _T_4566 = bits(_WIRE_341, 0, 0)
connect _WIRE_340.fragmented_superpage, _T_4566
node _T_4567 = bits(_WIRE_341, 1, 1)
connect _WIRE_340.c, _T_4567
node _T_4568 = bits(_WIRE_341, 2, 2)
connect _WIRE_340.eff, _T_4568
node _T_4569 = bits(_WIRE_341, 3, 3)
connect _WIRE_340.paa, _T_4569
node _T_4570 = bits(_WIRE_341, 4, 4)
connect _WIRE_340.pal, _T_4570
node _T_4571 = bits(_WIRE_341, 5, 5)
connect _WIRE_340.ppp, _T_4571
node _T_4572 = bits(_WIRE_341, 6, 6)
connect _WIRE_340.pr, _T_4572
node _T_4573 = bits(_WIRE_341, 7, 7)
connect _WIRE_340.px, _T_4573
node _T_4574 = bits(_WIRE_341, 8, 8)
connect _WIRE_340.pw, _T_4574
node _T_4575 = bits(_WIRE_341, 9, 9)
connect _WIRE_340.hr, _T_4575
node _T_4576 = bits(_WIRE_341, 10, 10)
connect _WIRE_340.hx, _T_4576
node _T_4577 = bits(_WIRE_341, 11, 11)
connect _WIRE_340.hw, _T_4577
node _T_4578 = bits(_WIRE_341, 12, 12)
connect _WIRE_340.sr, _T_4578
node _T_4579 = bits(_WIRE_341, 13, 13)
connect _WIRE_340.sx, _T_4579
node _T_4580 = bits(_WIRE_341, 14, 14)
connect _WIRE_340.sw, _T_4580
node _T_4581 = bits(_WIRE_341, 15, 15)
connect _WIRE_340.gf, _T_4581
node _T_4582 = bits(_WIRE_341, 16, 16)
connect _WIRE_340.pf, _T_4582
node _T_4583 = bits(_WIRE_341, 17, 17)
connect _WIRE_340.ae_stage2, _T_4583
node _T_4584 = bits(_WIRE_341, 18, 18)
connect _WIRE_340.ae_final, _T_4584
node _T_4585 = bits(_WIRE_341, 19, 19)
connect _WIRE_340.ae_ptw, _T_4585
node _T_4586 = bits(_WIRE_341, 20, 20)
connect _WIRE_340.g, _T_4586
node _T_4587 = bits(_WIRE_341, 21, 21)
connect _WIRE_340.u, _T_4587
node _T_4588 = bits(_WIRE_341, 41, 22)
connect _WIRE_340.ppn, _T_4588
node _T_4589 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1))
when _T_4589 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
node _T_4590 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1))
when _T_4590 :
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
node _T_4591 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1))
when _T_4591 :
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
node _T_4592 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1))
when _T_4592 :
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
wire _WIRE_342 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_343 : UInt<42>
connect _WIRE_343, sectored_entries[0][7].data[0]
node _T_4593 = bits(_WIRE_343, 0, 0)
connect _WIRE_342.fragmented_superpage, _T_4593
node _T_4594 = bits(_WIRE_343, 1, 1)
connect _WIRE_342.c, _T_4594
node _T_4595 = bits(_WIRE_343, 2, 2)
connect _WIRE_342.eff, _T_4595
node _T_4596 = bits(_WIRE_343, 3, 3)
connect _WIRE_342.paa, _T_4596
node _T_4597 = bits(_WIRE_343, 4, 4)
connect _WIRE_342.pal, _T_4597
node _T_4598 = bits(_WIRE_343, 5, 5)
connect _WIRE_342.ppp, _T_4598
node _T_4599 = bits(_WIRE_343, 6, 6)
connect _WIRE_342.pr, _T_4599
node _T_4600 = bits(_WIRE_343, 7, 7)
connect _WIRE_342.px, _T_4600
node _T_4601 = bits(_WIRE_343, 8, 8)
connect _WIRE_342.pw, _T_4601
node _T_4602 = bits(_WIRE_343, 9, 9)
connect _WIRE_342.hr, _T_4602
node _T_4603 = bits(_WIRE_343, 10, 10)
connect _WIRE_342.hx, _T_4603
node _T_4604 = bits(_WIRE_343, 11, 11)
connect _WIRE_342.hw, _T_4604
node _T_4605 = bits(_WIRE_343, 12, 12)
connect _WIRE_342.sr, _T_4605
node _T_4606 = bits(_WIRE_343, 13, 13)
connect _WIRE_342.sx, _T_4606
node _T_4607 = bits(_WIRE_343, 14, 14)
connect _WIRE_342.sw, _T_4607
node _T_4608 = bits(_WIRE_343, 15, 15)
connect _WIRE_342.gf, _T_4608
node _T_4609 = bits(_WIRE_343, 16, 16)
connect _WIRE_342.pf, _T_4609
node _T_4610 = bits(_WIRE_343, 17, 17)
connect _WIRE_342.ae_stage2, _T_4610
node _T_4611 = bits(_WIRE_343, 18, 18)
connect _WIRE_342.ae_final, _T_4611
node _T_4612 = bits(_WIRE_343, 19, 19)
connect _WIRE_342.ae_ptw, _T_4612
node _T_4613 = bits(_WIRE_343, 20, 20)
connect _WIRE_342.g, _T_4613
node _T_4614 = bits(_WIRE_343, 21, 21)
connect _WIRE_342.u, _T_4614
node _T_4615 = bits(_WIRE_343, 41, 22)
connect _WIRE_342.ppn, _T_4615
wire _WIRE_344 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_345 : UInt<42>
connect _WIRE_345, sectored_entries[0][7].data[1]
node _T_4616 = bits(_WIRE_345, 0, 0)
connect _WIRE_344.fragmented_superpage, _T_4616
node _T_4617 = bits(_WIRE_345, 1, 1)
connect _WIRE_344.c, _T_4617
node _T_4618 = bits(_WIRE_345, 2, 2)
connect _WIRE_344.eff, _T_4618
node _T_4619 = bits(_WIRE_345, 3, 3)
connect _WIRE_344.paa, _T_4619
node _T_4620 = bits(_WIRE_345, 4, 4)
connect _WIRE_344.pal, _T_4620
node _T_4621 = bits(_WIRE_345, 5, 5)
connect _WIRE_344.ppp, _T_4621
node _T_4622 = bits(_WIRE_345, 6, 6)
connect _WIRE_344.pr, _T_4622
node _T_4623 = bits(_WIRE_345, 7, 7)
connect _WIRE_344.px, _T_4623
node _T_4624 = bits(_WIRE_345, 8, 8)
connect _WIRE_344.pw, _T_4624
node _T_4625 = bits(_WIRE_345, 9, 9)
connect _WIRE_344.hr, _T_4625
node _T_4626 = bits(_WIRE_345, 10, 10)
connect _WIRE_344.hx, _T_4626
node _T_4627 = bits(_WIRE_345, 11, 11)
connect _WIRE_344.hw, _T_4627
node _T_4628 = bits(_WIRE_345, 12, 12)
connect _WIRE_344.sr, _T_4628
node _T_4629 = bits(_WIRE_345, 13, 13)
connect _WIRE_344.sx, _T_4629
node _T_4630 = bits(_WIRE_345, 14, 14)
connect _WIRE_344.sw, _T_4630
node _T_4631 = bits(_WIRE_345, 15, 15)
connect _WIRE_344.gf, _T_4631
node _T_4632 = bits(_WIRE_345, 16, 16)
connect _WIRE_344.pf, _T_4632
node _T_4633 = bits(_WIRE_345, 17, 17)
connect _WIRE_344.ae_stage2, _T_4633
node _T_4634 = bits(_WIRE_345, 18, 18)
connect _WIRE_344.ae_final, _T_4634
node _T_4635 = bits(_WIRE_345, 19, 19)
connect _WIRE_344.ae_ptw, _T_4635
node _T_4636 = bits(_WIRE_345, 20, 20)
connect _WIRE_344.g, _T_4636
node _T_4637 = bits(_WIRE_345, 21, 21)
connect _WIRE_344.u, _T_4637
node _T_4638 = bits(_WIRE_345, 41, 22)
connect _WIRE_344.ppn, _T_4638
wire _WIRE_346 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_347 : UInt<42>
connect _WIRE_347, sectored_entries[0][7].data[2]
node _T_4639 = bits(_WIRE_347, 0, 0)
connect _WIRE_346.fragmented_superpage, _T_4639
node _T_4640 = bits(_WIRE_347, 1, 1)
connect _WIRE_346.c, _T_4640
node _T_4641 = bits(_WIRE_347, 2, 2)
connect _WIRE_346.eff, _T_4641
node _T_4642 = bits(_WIRE_347, 3, 3)
connect _WIRE_346.paa, _T_4642
node _T_4643 = bits(_WIRE_347, 4, 4)
connect _WIRE_346.pal, _T_4643
node _T_4644 = bits(_WIRE_347, 5, 5)
connect _WIRE_346.ppp, _T_4644
node _T_4645 = bits(_WIRE_347, 6, 6)
connect _WIRE_346.pr, _T_4645
node _T_4646 = bits(_WIRE_347, 7, 7)
connect _WIRE_346.px, _T_4646
node _T_4647 = bits(_WIRE_347, 8, 8)
connect _WIRE_346.pw, _T_4647
node _T_4648 = bits(_WIRE_347, 9, 9)
connect _WIRE_346.hr, _T_4648
node _T_4649 = bits(_WIRE_347, 10, 10)
connect _WIRE_346.hx, _T_4649
node _T_4650 = bits(_WIRE_347, 11, 11)
connect _WIRE_346.hw, _T_4650
node _T_4651 = bits(_WIRE_347, 12, 12)
connect _WIRE_346.sr, _T_4651
node _T_4652 = bits(_WIRE_347, 13, 13)
connect _WIRE_346.sx, _T_4652
node _T_4653 = bits(_WIRE_347, 14, 14)
connect _WIRE_346.sw, _T_4653
node _T_4654 = bits(_WIRE_347, 15, 15)
connect _WIRE_346.gf, _T_4654
node _T_4655 = bits(_WIRE_347, 16, 16)
connect _WIRE_346.pf, _T_4655
node _T_4656 = bits(_WIRE_347, 17, 17)
connect _WIRE_346.ae_stage2, _T_4656
node _T_4657 = bits(_WIRE_347, 18, 18)
connect _WIRE_346.ae_final, _T_4657
node _T_4658 = bits(_WIRE_347, 19, 19)
connect _WIRE_346.ae_ptw, _T_4658
node _T_4659 = bits(_WIRE_347, 20, 20)
connect _WIRE_346.g, _T_4659
node _T_4660 = bits(_WIRE_347, 21, 21)
connect _WIRE_346.u, _T_4660
node _T_4661 = bits(_WIRE_347, 41, 22)
connect _WIRE_346.ppn, _T_4661
wire _WIRE_348 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_349 : UInt<42>
connect _WIRE_349, sectored_entries[0][7].data[3]
node _T_4662 = bits(_WIRE_349, 0, 0)
connect _WIRE_348.fragmented_superpage, _T_4662
node _T_4663 = bits(_WIRE_349, 1, 1)
connect _WIRE_348.c, _T_4663
node _T_4664 = bits(_WIRE_349, 2, 2)
connect _WIRE_348.eff, _T_4664
node _T_4665 = bits(_WIRE_349, 3, 3)
connect _WIRE_348.paa, _T_4665
node _T_4666 = bits(_WIRE_349, 4, 4)
connect _WIRE_348.pal, _T_4666
node _T_4667 = bits(_WIRE_349, 5, 5)
connect _WIRE_348.ppp, _T_4667
node _T_4668 = bits(_WIRE_349, 6, 6)
connect _WIRE_348.pr, _T_4668
node _T_4669 = bits(_WIRE_349, 7, 7)
connect _WIRE_348.px, _T_4669
node _T_4670 = bits(_WIRE_349, 8, 8)
connect _WIRE_348.pw, _T_4670
node _T_4671 = bits(_WIRE_349, 9, 9)
connect _WIRE_348.hr, _T_4671
node _T_4672 = bits(_WIRE_349, 10, 10)
connect _WIRE_348.hx, _T_4672
node _T_4673 = bits(_WIRE_349, 11, 11)
connect _WIRE_348.hw, _T_4673
node _T_4674 = bits(_WIRE_349, 12, 12)
connect _WIRE_348.sr, _T_4674
node _T_4675 = bits(_WIRE_349, 13, 13)
connect _WIRE_348.sx, _T_4675
node _T_4676 = bits(_WIRE_349, 14, 14)
connect _WIRE_348.sw, _T_4676
node _T_4677 = bits(_WIRE_349, 15, 15)
connect _WIRE_348.gf, _T_4677
node _T_4678 = bits(_WIRE_349, 16, 16)
connect _WIRE_348.pf, _T_4678
node _T_4679 = bits(_WIRE_349, 17, 17)
connect _WIRE_348.ae_stage2, _T_4679
node _T_4680 = bits(_WIRE_349, 18, 18)
connect _WIRE_348.ae_final, _T_4680
node _T_4681 = bits(_WIRE_349, 19, 19)
connect _WIRE_348.ae_ptw, _T_4681
node _T_4682 = bits(_WIRE_349, 20, 20)
connect _WIRE_348.g, _T_4682
node _T_4683 = bits(_WIRE_349, 21, 21)
connect _WIRE_348.u, _T_4683
node _T_4684 = bits(_WIRE_349, 41, 22)
connect _WIRE_348.ppn, _T_4684
node _T_4685 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1))
when _T_4685 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
node _T_4686 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1))
when _T_4686 :
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
node _T_4687 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1))
when _T_4687 :
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
node _T_4688 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1))
when _T_4688 :
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
wire _WIRE_350 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_351 : UInt<42>
connect _WIRE_351, superpage_entries[0].data[0]
node _T_4689 = bits(_WIRE_351, 0, 0)
connect _WIRE_350.fragmented_superpage, _T_4689
node _T_4690 = bits(_WIRE_351, 1, 1)
connect _WIRE_350.c, _T_4690
node _T_4691 = bits(_WIRE_351, 2, 2)
connect _WIRE_350.eff, _T_4691
node _T_4692 = bits(_WIRE_351, 3, 3)
connect _WIRE_350.paa, _T_4692
node _T_4693 = bits(_WIRE_351, 4, 4)
connect _WIRE_350.pal, _T_4693
node _T_4694 = bits(_WIRE_351, 5, 5)
connect _WIRE_350.ppp, _T_4694
node _T_4695 = bits(_WIRE_351, 6, 6)
connect _WIRE_350.pr, _T_4695
node _T_4696 = bits(_WIRE_351, 7, 7)
connect _WIRE_350.px, _T_4696
node _T_4697 = bits(_WIRE_351, 8, 8)
connect _WIRE_350.pw, _T_4697
node _T_4698 = bits(_WIRE_351, 9, 9)
connect _WIRE_350.hr, _T_4698
node _T_4699 = bits(_WIRE_351, 10, 10)
connect _WIRE_350.hx, _T_4699
node _T_4700 = bits(_WIRE_351, 11, 11)
connect _WIRE_350.hw, _T_4700
node _T_4701 = bits(_WIRE_351, 12, 12)
connect _WIRE_350.sr, _T_4701
node _T_4702 = bits(_WIRE_351, 13, 13)
connect _WIRE_350.sx, _T_4702
node _T_4703 = bits(_WIRE_351, 14, 14)
connect _WIRE_350.sw, _T_4703
node _T_4704 = bits(_WIRE_351, 15, 15)
connect _WIRE_350.gf, _T_4704
node _T_4705 = bits(_WIRE_351, 16, 16)
connect _WIRE_350.pf, _T_4705
node _T_4706 = bits(_WIRE_351, 17, 17)
connect _WIRE_350.ae_stage2, _T_4706
node _T_4707 = bits(_WIRE_351, 18, 18)
connect _WIRE_350.ae_final, _T_4707
node _T_4708 = bits(_WIRE_351, 19, 19)
connect _WIRE_350.ae_ptw, _T_4708
node _T_4709 = bits(_WIRE_351, 20, 20)
connect _WIRE_350.g, _T_4709
node _T_4710 = bits(_WIRE_351, 21, 21)
connect _WIRE_350.u, _T_4710
node _T_4711 = bits(_WIRE_351, 41, 22)
connect _WIRE_350.ppn, _T_4711
node _T_4712 = eq(superpage_entries[0].tag_v, UInt<1>(0h1))
when _T_4712 :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
wire _WIRE_352 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_353 : UInt<42>
connect _WIRE_353, superpage_entries[1].data[0]
node _T_4713 = bits(_WIRE_353, 0, 0)
connect _WIRE_352.fragmented_superpage, _T_4713
node _T_4714 = bits(_WIRE_353, 1, 1)
connect _WIRE_352.c, _T_4714
node _T_4715 = bits(_WIRE_353, 2, 2)
connect _WIRE_352.eff, _T_4715
node _T_4716 = bits(_WIRE_353, 3, 3)
connect _WIRE_352.paa, _T_4716
node _T_4717 = bits(_WIRE_353, 4, 4)
connect _WIRE_352.pal, _T_4717
node _T_4718 = bits(_WIRE_353, 5, 5)
connect _WIRE_352.ppp, _T_4718
node _T_4719 = bits(_WIRE_353, 6, 6)
connect _WIRE_352.pr, _T_4719
node _T_4720 = bits(_WIRE_353, 7, 7)
connect _WIRE_352.px, _T_4720
node _T_4721 = bits(_WIRE_353, 8, 8)
connect _WIRE_352.pw, _T_4721
node _T_4722 = bits(_WIRE_353, 9, 9)
connect _WIRE_352.hr, _T_4722
node _T_4723 = bits(_WIRE_353, 10, 10)
connect _WIRE_352.hx, _T_4723
node _T_4724 = bits(_WIRE_353, 11, 11)
connect _WIRE_352.hw, _T_4724
node _T_4725 = bits(_WIRE_353, 12, 12)
connect _WIRE_352.sr, _T_4725
node _T_4726 = bits(_WIRE_353, 13, 13)
connect _WIRE_352.sx, _T_4726
node _T_4727 = bits(_WIRE_353, 14, 14)
connect _WIRE_352.sw, _T_4727
node _T_4728 = bits(_WIRE_353, 15, 15)
connect _WIRE_352.gf, _T_4728
node _T_4729 = bits(_WIRE_353, 16, 16)
connect _WIRE_352.pf, _T_4729
node _T_4730 = bits(_WIRE_353, 17, 17)
connect _WIRE_352.ae_stage2, _T_4730
node _T_4731 = bits(_WIRE_353, 18, 18)
connect _WIRE_352.ae_final, _T_4731
node _T_4732 = bits(_WIRE_353, 19, 19)
connect _WIRE_352.ae_ptw, _T_4732
node _T_4733 = bits(_WIRE_353, 20, 20)
connect _WIRE_352.g, _T_4733
node _T_4734 = bits(_WIRE_353, 21, 21)
connect _WIRE_352.u, _T_4734
node _T_4735 = bits(_WIRE_353, 41, 22)
connect _WIRE_352.ppn, _T_4735
node _T_4736 = eq(superpage_entries[1].tag_v, UInt<1>(0h1))
when _T_4736 :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
wire _WIRE_354 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_355 : UInt<42>
connect _WIRE_355, superpage_entries[2].data[0]
node _T_4737 = bits(_WIRE_355, 0, 0)
connect _WIRE_354.fragmented_superpage, _T_4737
node _T_4738 = bits(_WIRE_355, 1, 1)
connect _WIRE_354.c, _T_4738
node _T_4739 = bits(_WIRE_355, 2, 2)
connect _WIRE_354.eff, _T_4739
node _T_4740 = bits(_WIRE_355, 3, 3)
connect _WIRE_354.paa, _T_4740
node _T_4741 = bits(_WIRE_355, 4, 4)
connect _WIRE_354.pal, _T_4741
node _T_4742 = bits(_WIRE_355, 5, 5)
connect _WIRE_354.ppp, _T_4742
node _T_4743 = bits(_WIRE_355, 6, 6)
connect _WIRE_354.pr, _T_4743
node _T_4744 = bits(_WIRE_355, 7, 7)
connect _WIRE_354.px, _T_4744
node _T_4745 = bits(_WIRE_355, 8, 8)
connect _WIRE_354.pw, _T_4745
node _T_4746 = bits(_WIRE_355, 9, 9)
connect _WIRE_354.hr, _T_4746
node _T_4747 = bits(_WIRE_355, 10, 10)
connect _WIRE_354.hx, _T_4747
node _T_4748 = bits(_WIRE_355, 11, 11)
connect _WIRE_354.hw, _T_4748
node _T_4749 = bits(_WIRE_355, 12, 12)
connect _WIRE_354.sr, _T_4749
node _T_4750 = bits(_WIRE_355, 13, 13)
connect _WIRE_354.sx, _T_4750
node _T_4751 = bits(_WIRE_355, 14, 14)
connect _WIRE_354.sw, _T_4751
node _T_4752 = bits(_WIRE_355, 15, 15)
connect _WIRE_354.gf, _T_4752
node _T_4753 = bits(_WIRE_355, 16, 16)
connect _WIRE_354.pf, _T_4753
node _T_4754 = bits(_WIRE_355, 17, 17)
connect _WIRE_354.ae_stage2, _T_4754
node _T_4755 = bits(_WIRE_355, 18, 18)
connect _WIRE_354.ae_final, _T_4755
node _T_4756 = bits(_WIRE_355, 19, 19)
connect _WIRE_354.ae_ptw, _T_4756
node _T_4757 = bits(_WIRE_355, 20, 20)
connect _WIRE_354.g, _T_4757
node _T_4758 = bits(_WIRE_355, 21, 21)
connect _WIRE_354.u, _T_4758
node _T_4759 = bits(_WIRE_355, 41, 22)
connect _WIRE_354.ppn, _T_4759
node _T_4760 = eq(superpage_entries[2].tag_v, UInt<1>(0h1))
when _T_4760 :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
wire _WIRE_356 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_357 : UInt<42>
connect _WIRE_357, superpage_entries[3].data[0]
node _T_4761 = bits(_WIRE_357, 0, 0)
connect _WIRE_356.fragmented_superpage, _T_4761
node _T_4762 = bits(_WIRE_357, 1, 1)
connect _WIRE_356.c, _T_4762
node _T_4763 = bits(_WIRE_357, 2, 2)
connect _WIRE_356.eff, _T_4763
node _T_4764 = bits(_WIRE_357, 3, 3)
connect _WIRE_356.paa, _T_4764
node _T_4765 = bits(_WIRE_357, 4, 4)
connect _WIRE_356.pal, _T_4765
node _T_4766 = bits(_WIRE_357, 5, 5)
connect _WIRE_356.ppp, _T_4766
node _T_4767 = bits(_WIRE_357, 6, 6)
connect _WIRE_356.pr, _T_4767
node _T_4768 = bits(_WIRE_357, 7, 7)
connect _WIRE_356.px, _T_4768
node _T_4769 = bits(_WIRE_357, 8, 8)
connect _WIRE_356.pw, _T_4769
node _T_4770 = bits(_WIRE_357, 9, 9)
connect _WIRE_356.hr, _T_4770
node _T_4771 = bits(_WIRE_357, 10, 10)
connect _WIRE_356.hx, _T_4771
node _T_4772 = bits(_WIRE_357, 11, 11)
connect _WIRE_356.hw, _T_4772
node _T_4773 = bits(_WIRE_357, 12, 12)
connect _WIRE_356.sr, _T_4773
node _T_4774 = bits(_WIRE_357, 13, 13)
connect _WIRE_356.sx, _T_4774
node _T_4775 = bits(_WIRE_357, 14, 14)
connect _WIRE_356.sw, _T_4775
node _T_4776 = bits(_WIRE_357, 15, 15)
connect _WIRE_356.gf, _T_4776
node _T_4777 = bits(_WIRE_357, 16, 16)
connect _WIRE_356.pf, _T_4777
node _T_4778 = bits(_WIRE_357, 17, 17)
connect _WIRE_356.ae_stage2, _T_4778
node _T_4779 = bits(_WIRE_357, 18, 18)
connect _WIRE_356.ae_final, _T_4779
node _T_4780 = bits(_WIRE_357, 19, 19)
connect _WIRE_356.ae_ptw, _T_4780
node _T_4781 = bits(_WIRE_357, 20, 20)
connect _WIRE_356.g, _T_4781
node _T_4782 = bits(_WIRE_357, 21, 21)
connect _WIRE_356.u, _T_4782
node _T_4783 = bits(_WIRE_357, 41, 22)
connect _WIRE_356.ppn, _T_4783
node _T_4784 = eq(superpage_entries[3].tag_v, UInt<1>(0h1))
when _T_4784 :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
wire _WIRE_358 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_359 : UInt<42>
connect _WIRE_359, special_entry.data[0]
node _T_4785 = bits(_WIRE_359, 0, 0)
connect _WIRE_358.fragmented_superpage, _T_4785
node _T_4786 = bits(_WIRE_359, 1, 1)
connect _WIRE_358.c, _T_4786
node _T_4787 = bits(_WIRE_359, 2, 2)
connect _WIRE_358.eff, _T_4787
node _T_4788 = bits(_WIRE_359, 3, 3)
connect _WIRE_358.paa, _T_4788
node _T_4789 = bits(_WIRE_359, 4, 4)
connect _WIRE_358.pal, _T_4789
node _T_4790 = bits(_WIRE_359, 5, 5)
connect _WIRE_358.ppp, _T_4790
node _T_4791 = bits(_WIRE_359, 6, 6)
connect _WIRE_358.pr, _T_4791
node _T_4792 = bits(_WIRE_359, 7, 7)
connect _WIRE_358.px, _T_4792
node _T_4793 = bits(_WIRE_359, 8, 8)
connect _WIRE_358.pw, _T_4793
node _T_4794 = bits(_WIRE_359, 9, 9)
connect _WIRE_358.hr, _T_4794
node _T_4795 = bits(_WIRE_359, 10, 10)
connect _WIRE_358.hx, _T_4795
node _T_4796 = bits(_WIRE_359, 11, 11)
connect _WIRE_358.hw, _T_4796
node _T_4797 = bits(_WIRE_359, 12, 12)
connect _WIRE_358.sr, _T_4797
node _T_4798 = bits(_WIRE_359, 13, 13)
connect _WIRE_358.sx, _T_4798
node _T_4799 = bits(_WIRE_359, 14, 14)
connect _WIRE_358.sw, _T_4799
node _T_4800 = bits(_WIRE_359, 15, 15)
connect _WIRE_358.gf, _T_4800
node _T_4801 = bits(_WIRE_359, 16, 16)
connect _WIRE_358.pf, _T_4801
node _T_4802 = bits(_WIRE_359, 17, 17)
connect _WIRE_358.ae_stage2, _T_4802
node _T_4803 = bits(_WIRE_359, 18, 18)
connect _WIRE_358.ae_final, _T_4803
node _T_4804 = bits(_WIRE_359, 19, 19)
connect _WIRE_358.ae_ptw, _T_4804
node _T_4805 = bits(_WIRE_359, 20, 20)
connect _WIRE_358.g, _T_4805
node _T_4806 = bits(_WIRE_359, 21, 21)
connect _WIRE_358.u, _T_4806
node _T_4807 = bits(_WIRE_359, 41, 22)
connect _WIRE_358.ppn, _T_4807
node _T_4808 = eq(special_entry.tag_v, UInt<1>(0h1))
when _T_4808 :
connect special_entry.valid[0], UInt<1>(0h0)
connect v_entries_use_stage1, vstage1_en
node _T_4809 = asUInt(reset)
node _T_4810 = or(multipleHits, _T_4809)
when _T_4810 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
connect superpage_entries[0].valid[0], UInt<1>(0h0)
connect superpage_entries[1].valid[0], UInt<1>(0h0)
connect superpage_entries[2].valid[0], UInt<1>(0h0)
connect superpage_entries[3].valid[0], UInt<1>(0h0)
connect special_entry.valid[0], UInt<1>(0h0)
node _T_4811 = and(io.ptw.req.ready, io.ptw.req.valid)
node _T_4812 = eq(io.ptw.req.ready, UInt<1>(0h0))
node _T_4813 = and(io.ptw.req.valid, _T_4812)
node _T_4814 = eq(state, UInt<2>(0h3))
node _T_4815 = eq(io.sfence.bits.rs1, UInt<1>(0h0))
node _T_4816 = and(io.sfence.valid, _T_4815)
node _T_4817 = eq(io.sfence.bits.rs2, UInt<1>(0h0))
node _T_4818 = and(_T_4816, _T_4817)
node _T_4819 = eq(io.sfence.bits.rs1, UInt<1>(0h0))
node _T_4820 = and(io.sfence.valid, _T_4819)
node _T_4821 = and(_T_4820, io.sfence.bits.rs2)
node _T_4822 = and(io.sfence.valid, io.sfence.bits.rs1)
node _T_4823 = eq(io.sfence.bits.rs2, UInt<1>(0h0))
node _T_4824 = and(_T_4822, _T_4823)
node _T_4825 = and(io.sfence.valid, io.sfence.bits.rs1)
node _T_4826 = and(_T_4825, io.sfence.bits.rs2) | module DTLB_12( // @[TLB.scala:318:7]
input clock, // @[TLB.scala:318:7]
input reset, // @[TLB.scala:318:7]
output io_req_ready, // @[TLB.scala:320:14]
input io_req_valid, // @[TLB.scala:320:14]
input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14]
input io_req_bits_passthrough, // @[TLB.scala:320:14]
input [1:0] io_req_bits_size, // @[TLB.scala:320:14]
input [4:0] io_req_bits_cmd, // @[TLB.scala:320:14]
input [1:0] io_req_bits_prv, // @[TLB.scala:320:14]
input io_req_bits_v, // @[TLB.scala:320:14]
output io_resp_miss, // @[TLB.scala:320:14]
output [31:0] io_resp_paddr, // @[TLB.scala:320:14]
output [39:0] io_resp_gpa, // @[TLB.scala:320:14]
output io_resp_pf_ld, // @[TLB.scala:320:14]
output io_resp_pf_st, // @[TLB.scala:320:14]
output io_resp_pf_inst, // @[TLB.scala:320:14]
output io_resp_ae_ld, // @[TLB.scala:320:14]
output io_resp_ae_st, // @[TLB.scala:320:14]
output io_resp_ae_inst, // @[TLB.scala:320:14]
output io_resp_ma_ld, // @[TLB.scala:320:14]
output io_resp_ma_st, // @[TLB.scala:320:14]
output io_resp_cacheable, // @[TLB.scala:320:14]
output io_resp_must_alloc, // @[TLB.scala:320:14]
output io_resp_prefetchable, // @[TLB.scala:320:14]
output [1:0] io_resp_size, // @[TLB.scala:320:14]
output [4:0] io_resp_cmd, // @[TLB.scala:320:14]
input io_sfence_valid, // @[TLB.scala:320:14]
input io_sfence_bits_rs1, // @[TLB.scala:320:14]
input io_sfence_bits_rs2, // @[TLB.scala:320:14]
input [38:0] io_sfence_bits_addr, // @[TLB.scala:320:14]
input io_sfence_bits_asid, // @[TLB.scala:320:14]
input io_sfence_bits_hv, // @[TLB.scala:320:14]
input io_sfence_bits_hg, // @[TLB.scala:320:14]
input io_ptw_req_ready, // @[TLB.scala:320:14]
output io_ptw_req_valid, // @[TLB.scala:320:14]
output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14]
output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14]
input io_ptw_resp_valid, // @[TLB.scala:320:14]
input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14]
input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pf, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gf, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hr, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hw, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hx, // @[TLB.scala:320:14]
input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14]
input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14]
input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14]
input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14]
input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14]
input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14]
input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14]
input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14]
input io_ptw_status_debug, // @[TLB.scala:320:14]
input io_ptw_status_cease, // @[TLB.scala:320:14]
input io_ptw_status_wfi, // @[TLB.scala:320:14]
input [31:0] io_ptw_status_isa, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14]
input io_ptw_status_dv, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14]
input io_ptw_status_v, // @[TLB.scala:320:14]
input io_ptw_status_sd, // @[TLB.scala:320:14]
input io_ptw_status_mpv, // @[TLB.scala:320:14]
input io_ptw_status_gva, // @[TLB.scala:320:14]
input io_ptw_status_tsr, // @[TLB.scala:320:14]
input io_ptw_status_tw, // @[TLB.scala:320:14]
input io_ptw_status_tvm, // @[TLB.scala:320:14]
input io_ptw_status_mxr, // @[TLB.scala:320:14]
input io_ptw_status_sum, // @[TLB.scala:320:14]
input io_ptw_status_mprv, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14]
input io_ptw_status_spp, // @[TLB.scala:320:14]
input io_ptw_status_mpie, // @[TLB.scala:320:14]
input io_ptw_status_spie, // @[TLB.scala:320:14]
input io_ptw_status_mie, // @[TLB.scala:320:14]
input io_ptw_status_sie, // @[TLB.scala:320:14]
input io_ptw_hstatus_spvp, // @[TLB.scala:320:14]
input io_ptw_hstatus_spv, // @[TLB.scala:320:14]
input io_ptw_hstatus_gva, // @[TLB.scala:320:14]
input io_ptw_gstatus_debug, // @[TLB.scala:320:14]
input io_ptw_gstatus_cease, // @[TLB.scala:320:14]
input io_ptw_gstatus_wfi, // @[TLB.scala:320:14]
input [31:0] io_ptw_gstatus_isa, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_dprv, // @[TLB.scala:320:14]
input io_ptw_gstatus_dv, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_prv, // @[TLB.scala:320:14]
input io_ptw_gstatus_v, // @[TLB.scala:320:14]
input io_ptw_gstatus_sd, // @[TLB.scala:320:14]
input [22:0] io_ptw_gstatus_zero2, // @[TLB.scala:320:14]
input io_ptw_gstatus_mpv, // @[TLB.scala:320:14]
input io_ptw_gstatus_gva, // @[TLB.scala:320:14]
input io_ptw_gstatus_mbe, // @[TLB.scala:320:14]
input io_ptw_gstatus_sbe, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_sxl, // @[TLB.scala:320:14]
input [7:0] io_ptw_gstatus_zero1, // @[TLB.scala:320:14]
input io_ptw_gstatus_tsr, // @[TLB.scala:320:14]
input io_ptw_gstatus_tw, // @[TLB.scala:320:14]
input io_ptw_gstatus_tvm, // @[TLB.scala:320:14]
input io_ptw_gstatus_mxr, // @[TLB.scala:320:14]
input io_ptw_gstatus_sum, // @[TLB.scala:320:14]
input io_ptw_gstatus_mprv, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_fs, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_mpp, // @[TLB.scala:320:14]
input [1:0] io_ptw_gstatus_vs, // @[TLB.scala:320:14]
input io_ptw_gstatus_spp, // @[TLB.scala:320:14]
input io_ptw_gstatus_mpie, // @[TLB.scala:320:14]
input io_ptw_gstatus_ube, // @[TLB.scala:320:14]
input io_ptw_gstatus_spie, // @[TLB.scala:320:14]
input io_ptw_gstatus_upie, // @[TLB.scala:320:14]
input io_ptw_gstatus_mie, // @[TLB.scala:320:14]
input io_ptw_gstatus_hie, // @[TLB.scala:320:14]
input io_ptw_gstatus_sie, // @[TLB.scala:320:14]
input io_ptw_gstatus_uie, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_7_mask, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_0_ren, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_0_wen, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_0_value, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_1_ren, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_1_wen, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_1_value, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_2_ren, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_2_wen, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_2_value, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_3_ren, // @[TLB.scala:320:14]
input io_ptw_customCSRs_csrs_3_wen, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[TLB.scala:320:14]
input [63:0] io_ptw_customCSRs_csrs_3_value // @[TLB.scala:320:14]
);
wire [19:0] _entries_barrier_12_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_hr; // @[package.scala:267:25]
wire [19:0] _entries_barrier_11_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_10_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_9_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_8_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_7_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_6_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_io_y_c; // @[package.scala:267:25]
wire _pma_io_resp_r; // @[TLB.scala:422:19]
wire _pma_io_resp_w; // @[TLB.scala:422:19]
wire _pma_io_resp_pp; // @[TLB.scala:422:19]
wire _pma_io_resp_al; // @[TLB.scala:422:19]
wire _pma_io_resp_aa; // @[TLB.scala:422:19]
wire _pma_io_resp_x; // @[TLB.scala:422:19]
wire _pma_io_resp_eff; // @[TLB.scala:422:19]
wire _pmp_io_r; // @[TLB.scala:416:19]
wire _pmp_io_w; // @[TLB.scala:416:19]
wire _pmp_io_x; // @[TLB.scala:416:19]
wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25]
wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7]
wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7]
wire io_req_bits_passthrough_0 = io_req_bits_passthrough; // @[TLB.scala:318:7]
wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[TLB.scala:318:7]
wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[TLB.scala:318:7]
wire [1:0] io_req_bits_prv_0 = io_req_bits_prv; // @[TLB.scala:318:7]
wire io_req_bits_v_0 = io_req_bits_v; // @[TLB.scala:318:7]
wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7]
wire io_sfence_bits_rs1_0 = io_sfence_bits_rs1; // @[TLB.scala:318:7]
wire io_sfence_bits_rs2_0 = io_sfence_bits_rs2; // @[TLB.scala:318:7]
wire [38:0] io_sfence_bits_addr_0 = io_sfence_bits_addr; // @[TLB.scala:318:7]
wire io_sfence_bits_asid_0 = io_sfence_bits_asid; // @[TLB.scala:318:7]
wire io_sfence_bits_hv_0 = io_sfence_bits_hv; // @[TLB.scala:318:7]
wire io_sfence_bits_hg_0 = io_sfence_bits_hg; // @[TLB.scala:318:7]
wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7]
wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7]
wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7]
wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7]
wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7]
wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7]
wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7]
wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7]
wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7]
wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7]
wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7]
wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7]
wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7]
wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7]
wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7]
wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7]
wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7]
wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7]
wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7]
wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7]
wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7]
wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7]
wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7]
wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7]
wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7]
wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7]
wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7]
wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7]
wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7]
wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[TLB.scala:318:7]
wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[TLB.scala:318:7]
wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[TLB.scala:318:7]
wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[TLB.scala:318:7]
wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[TLB.scala:318:7]
wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[TLB.scala:318:7]
wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[TLB.scala:318:7]
wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[TLB.scala:318:7]
wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sd_0 = io_ptw_gstatus_sd; // @[TLB.scala:318:7]
wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[TLB.scala:318:7]
wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[TLB.scala:318:7]
wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[TLB.scala:318:7]
wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[TLB.scala:318:7]
wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[TLB.scala:318:7]
wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[TLB.scala:318:7]
wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7]
wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_mbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_sbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_sd_rv32 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_ube = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_upie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_hie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_uie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[TLB.scala:318:7]
wire io_kill = 1'h0; // @[TLB.scala:318:7]
wire priv_v = 1'h0; // @[TLB.scala:369:34]
wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38]
wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68]
wire vstage1_en = 1'h0; // @[TLB.scala:376:48]
wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38]
wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68]
wire stage2_en = 1'h0; // @[TLB.scala:378:48]
wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52]
wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37]
wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78]
wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28]
wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34]
wire _superpage_hits_ignore_T_3 = 1'h0; // @[TLB.scala:182:28]
wire superpage_hits_ignore_3 = 1'h0; // @[TLB.scala:182:34]
wire _superpage_hits_ignore_T_6 = 1'h0; // @[TLB.scala:182:28]
wire superpage_hits_ignore_6 = 1'h0; // @[TLB.scala:182:34]
wire _superpage_hits_ignore_T_9 = 1'h0; // @[TLB.scala:182:28]
wire superpage_hits_ignore_9 = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T_6 = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore_6 = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T_9 = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore_9 = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T_12 = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore_12 = 1'h0; // @[TLB.scala:182:34]
wire refill_v = 1'h0; // @[TLB.scala:448:33]
wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24]
wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24]
wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84]
wire _waddr_T = 1'h0; // @[TLB.scala:477:45]
wire _mxr_T = 1'h0; // @[TLB.scala:518:36]
wire cmd_readx = 1'h0; // @[TLB.scala:575:37]
wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32]
wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32]
wire _multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37]
wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29]
wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66]
wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42]
wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29]
wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73]
wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49]
wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56]
wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30]
wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36]
wire hv = 1'h0; // @[TLB.scala:721:36]
wire hg = 1'h0; // @[TLB.scala:722:36]
wire hv_1 = 1'h0; // @[TLB.scala:721:36]
wire hg_1 = 1'h0; // @[TLB.scala:722:36]
wire hv_2 = 1'h0; // @[TLB.scala:721:36]
wire hg_2 = 1'h0; // @[TLB.scala:722:36]
wire hv_3 = 1'h0; // @[TLB.scala:721:36]
wire hg_3 = 1'h0; // @[TLB.scala:722:36]
wire hv_4 = 1'h0; // @[TLB.scala:721:36]
wire hg_4 = 1'h0; // @[TLB.scala:722:36]
wire hv_5 = 1'h0; // @[TLB.scala:721:36]
wire hg_5 = 1'h0; // @[TLB.scala:722:36]
wire hv_6 = 1'h0; // @[TLB.scala:721:36]
wire hg_6 = 1'h0; // @[TLB.scala:722:36]
wire hv_7 = 1'h0; // @[TLB.scala:721:36]
wire hg_7 = 1'h0; // @[TLB.scala:722:36]
wire hv_8 = 1'h0; // @[TLB.scala:721:36]
wire hg_8 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T = 1'h0; // @[TLB.scala:182:28]
wire ignore = 1'h0; // @[TLB.scala:182:34]
wire hv_9 = 1'h0; // @[TLB.scala:721:36]
wire hg_9 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28]
wire ignore_3 = 1'h0; // @[TLB.scala:182:34]
wire hv_10 = 1'h0; // @[TLB.scala:721:36]
wire hg_10 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T_6 = 1'h0; // @[TLB.scala:182:28]
wire ignore_6 = 1'h0; // @[TLB.scala:182:34]
wire hv_11 = 1'h0; // @[TLB.scala:721:36]
wire hg_11 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T_9 = 1'h0; // @[TLB.scala:182:28]
wire ignore_9 = 1'h0; // @[TLB.scala:182:34]
wire hv_12 = 1'h0; // @[TLB.scala:721:36]
wire hg_12 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T_12 = 1'h0; // @[TLB.scala:182:28]
wire ignore_12 = 1'h0; // @[TLB.scala:182:34]
wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[TLB.scala:318:7]
wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7]
wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7]
wire [15:0] satp_asid = 16'h0; // @[TLB.scala:373:17]
wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7]
wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7]
wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7]
wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7]
wire [22:0] io_ptw_status_zero2 = 23'h0; // @[TLB.scala:318:7]
wire [7:0] io_ptw_status_zero1 = 8'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_xs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_vs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7]
wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7]
wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7]
wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_valid = 1'h1; // @[TLB.scala:318:7]
wire _homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22]
wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40]
wire superpage_hits_ignore_5 = 1'h1; // @[TLB.scala:182:34]
wire _superpage_hits_T_27 = 1'h1; // @[TLB.scala:183:40]
wire superpage_hits_ignore_8 = 1'h1; // @[TLB.scala:182:34]
wire _superpage_hits_T_41 = 1'h1; // @[TLB.scala:183:40]
wire superpage_hits_ignore_11 = 1'h1; // @[TLB.scala:182:34]
wire _superpage_hits_T_55 = 1'h1; // @[TLB.scala:183:40]
wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire _hitsVec_T_61 = 1'h1; // @[TLB.scala:183:40]
wire hitsVec_ignore_5 = 1'h1; // @[TLB.scala:182:34]
wire _hitsVec_T_76 = 1'h1; // @[TLB.scala:183:40]
wire hitsVec_ignore_8 = 1'h1; // @[TLB.scala:182:34]
wire _hitsVec_T_91 = 1'h1; // @[TLB.scala:183:40]
wire hitsVec_ignore_11 = 1'h1; // @[TLB.scala:182:34]
wire _hitsVec_T_106 = 1'h1; // @[TLB.scala:183:40]
wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34]
wire ppn_ignore_3 = 1'h1; // @[TLB.scala:197:34]
wire ppn_ignore_5 = 1'h1; // @[TLB.scala:197:34]
wire ppn_ignore_7 = 1'h1; // @[TLB.scala:197:34]
wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42]
wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26]
wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107]
wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32]
wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20]
wire _io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28]
wire ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire ignore_5 = 1'h1; // @[TLB.scala:182:34]
wire ignore_8 = 1'h1; // @[TLB.scala:182:34]
wire ignore_11 = 1'h1; // @[TLB.scala:182:34]
wire [1:0] io_ptw_status_sxl = 2'h2; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_uxl = 2'h2; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[TLB.scala:318:7]
wire [13:0] _gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46]
wire [13:0] gf_ld_array = 14'h0; // @[TLB.scala:600:24]
wire [13:0] _gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53]
wire [13:0] gf_st_array = 14'h0; // @[TLB.scala:601:24]
wire [13:0] _gf_inst_array_T = 14'h0; // @[TLB.scala:602:36]
wire [13:0] gf_inst_array = 14'h0; // @[TLB.scala:602:26]
wire [13:0] gpa_hits_need_gpa_mask = 14'h0; // @[TLB.scala:605:73]
wire [13:0] _io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58]
wire [13:0] _io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65]
wire [13:0] _io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48]
wire [6:0] _state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25]
wire [12:0] stage2_bypass = 13'h1FFF; // @[TLB.scala:523:27]
wire [12:0] _hr_array_T_4 = 13'h1FFF; // @[TLB.scala:524:111]
wire [12:0] _hw_array_T_1 = 13'h1FFF; // @[TLB.scala:525:55]
wire [12:0] _hx_array_T_1 = 13'h1FFF; // @[TLB.scala:526:55]
wire [12:0] _gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:606:88]
wire [12:0] gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:606:82]
wire [12:0] _gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:607:16]
wire [12:0] gpa_hits = 13'h1FFF; // @[TLB.scala:607:14]
wire [12:0] _stage1_bypass_T = 13'h0; // @[TLB.scala:517:27]
wire [12:0] stage1_bypass = 13'h0; // @[TLB.scala:517:61]
wire [12:0] _gpa_hits_T = 13'h0; // @[TLB.scala:607:30]
wire [13:0] hr_array = 14'h3FFF; // @[TLB.scala:524:21]
wire [13:0] hw_array = 14'h3FFF; // @[TLB.scala:525:21]
wire [13:0] hx_array = 14'h3FFF; // @[TLB.scala:526:21]
wire [13:0] _must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19]
wire [13:0] _gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50]
wire _io_req_ready_T; // @[TLB.scala:631:25]
wire [1:0] io_resp_size_0 = io_req_bits_size_0; // @[TLB.scala:318:7]
wire [4:0] io_resp_cmd_0 = io_req_bits_cmd_0; // @[TLB.scala:318:7]
wire _io_resp_miss_T_2; // @[TLB.scala:651:64]
wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23]
wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8]
wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41]
wire _io_resp_pf_st_T_3; // @[TLB.scala:634:48]
wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29]
wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41]
wire _io_resp_ae_st_T_1; // @[TLB.scala:642:41]
wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41]
wire _io_resp_ma_ld_T; // @[TLB.scala:645:31]
wire _io_resp_ma_st_T; // @[TLB.scala:646:31]
wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41]
wire _io_resp_must_alloc_T_1; // @[TLB.scala:649:51]
wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59]
wire _io_ptw_req_valid_T; // @[TLB.scala:662:29]
wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29]
wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24]
wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13]
wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17]
wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17]
wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31]
wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16]
wire io_req_ready_0; // @[TLB.scala:318:7]
wire io_resp_pf_ld_0; // @[TLB.scala:318:7]
wire io_resp_pf_st_0; // @[TLB.scala:318:7]
wire io_resp_pf_inst_0; // @[TLB.scala:318:7]
wire io_resp_ae_ld_0; // @[TLB.scala:318:7]
wire io_resp_ae_st_0; // @[TLB.scala:318:7]
wire io_resp_ae_inst_0; // @[TLB.scala:318:7]
wire io_resp_ma_ld_0; // @[TLB.scala:318:7]
wire io_resp_ma_st_0; // @[TLB.scala:318:7]
wire io_resp_miss_0; // @[TLB.scala:318:7]
wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7]
wire [39:0] io_resp_gpa_0; // @[TLB.scala:318:7]
wire io_resp_cacheable_0; // @[TLB.scala:318:7]
wire io_resp_must_alloc_0; // @[TLB.scala:318:7]
wire io_resp_prefetchable_0; // @[TLB.scala:318:7]
wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7]
wire io_ptw_req_valid_0; // @[TLB.scala:318:7]
wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30]
wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] _ppn_T_13 = vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] _ppn_T_21 = vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] _ppn_T_29 = vpn; // @[TLB.scala:198:28, :335:30]
reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_0_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_0_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_0_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_0_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_0_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_0_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_1_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_1_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_1_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_1_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_1_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_1_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_1_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_2_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_2_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_2_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_2_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_2_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_2_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_2_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_3_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_3_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_3_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_3_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_3_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_3_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_3_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_4_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_4_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_4_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_4_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_4_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_4_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_4_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_4_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_4_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_4_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_4_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_5_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_5_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_5_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_5_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_5_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_5_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_5_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_5_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_5_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_5_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_5_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_6_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_6_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_6_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_6_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_6_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_6_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_6_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_6_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_6_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_6_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_6_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_7_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_7_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_7_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_7_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_7_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_7_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_7_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_7_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_7_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_7_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_7_valid_3; // @[TLB.scala:339:29]
reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30]
reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30]
reg superpage_entries_0_tag_v; // @[TLB.scala:341:30]
reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30]
wire [41:0] _entries_WIRE_17 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30]
reg superpage_entries_0_valid_0; // @[TLB.scala:341:30]
reg [1:0] superpage_entries_1_level; // @[TLB.scala:341:30]
reg [26:0] superpage_entries_1_tag_vpn; // @[TLB.scala:341:30]
reg superpage_entries_1_tag_v; // @[TLB.scala:341:30]
reg [41:0] superpage_entries_1_data_0; // @[TLB.scala:341:30]
wire [41:0] _entries_WIRE_19 = superpage_entries_1_data_0; // @[TLB.scala:170:77, :341:30]
reg superpage_entries_1_valid_0; // @[TLB.scala:341:30]
reg [1:0] superpage_entries_2_level; // @[TLB.scala:341:30]
reg [26:0] superpage_entries_2_tag_vpn; // @[TLB.scala:341:30]
reg superpage_entries_2_tag_v; // @[TLB.scala:341:30]
reg [41:0] superpage_entries_2_data_0; // @[TLB.scala:341:30]
wire [41:0] _entries_WIRE_21 = superpage_entries_2_data_0; // @[TLB.scala:170:77, :341:30]
reg superpage_entries_2_valid_0; // @[TLB.scala:341:30]
reg [1:0] superpage_entries_3_level; // @[TLB.scala:341:30]
reg [26:0] superpage_entries_3_tag_vpn; // @[TLB.scala:341:30]
reg superpage_entries_3_tag_v; // @[TLB.scala:341:30]
reg [41:0] superpage_entries_3_data_0; // @[TLB.scala:341:30]
wire [41:0] _entries_WIRE_23 = superpage_entries_3_data_0; // @[TLB.scala:170:77, :341:30]
reg superpage_entries_3_valid_0; // @[TLB.scala:341:30]
reg [1:0] special_entry_level; // @[TLB.scala:346:56]
reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56]
reg special_entry_tag_v; // @[TLB.scala:346:56]
reg [41:0] special_entry_data_0; // @[TLB.scala:346:56]
wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56]
wire [41:0] _entries_WIRE_25 = special_entry_data_0; // @[TLB.scala:170:77, :346:56]
reg special_entry_valid_0; // @[TLB.scala:346:56]
reg [1:0] state; // @[TLB.scala:352:22]
reg [26:0] r_refill_tag; // @[TLB.scala:354:25]
assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25]
reg [1:0] r_superpage_repl_addr; // @[TLB.scala:355:34]
wire [1:0] waddr = r_superpage_repl_addr; // @[TLB.scala:355:34, :477:22]
reg [2:0] r_sectored_repl_addr; // @[TLB.scala:356:33]
reg r_sectored_hit_valid; // @[TLB.scala:357:27]
reg [2:0] r_sectored_hit_bits; // @[TLB.scala:357:27]
reg r_superpage_hit_valid; // @[TLB.scala:358:28]
reg [1:0] r_superpage_hit_bits; // @[TLB.scala:358:28]
reg r_need_gpa; // @[TLB.scala:361:23]
assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23]
reg r_gpa_valid; // @[TLB.scala:362:24]
reg [38:0] r_gpa; // @[TLB.scala:363:18]
reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22]
reg r_gpa_is_pte; // @[TLB.scala:365:25]
wire priv_s = io_req_bits_prv_0[0]; // @[TLB.scala:318:7, :370:20]
wire priv_uses_vm = ~(io_req_bits_prv_0[1]); // @[TLB.scala:318:7, :372:27]
wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41]
wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}]
wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31]
wire _vm_enabled_T_1 = _vm_enabled_T & priv_uses_vm; // @[TLB.scala:372:27, :399:{31,45}]
wire _vm_enabled_T_2 = ~io_req_bits_passthrough_0; // @[TLB.scala:318:7, :399:64]
wire vm_enabled = _vm_enabled_T_1 & _vm_enabled_T_2; // @[TLB.scala:399:{45,61,64}]
wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32]
wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29]
wire _vsatp_mode_mismatch_T_2 = ~io_req_bits_passthrough_0; // @[TLB.scala:318:7, :399:64, :403:81]
wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44]
wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24]
wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29]
wire _T_51 = state == 2'h1; // @[package.scala:16:47]
wire _invalidate_refill_T; // @[package.scala:16:47]
assign _invalidate_refill_T = _T_51; // @[package.scala:16:47]
assign _io_ptw_req_valid_T = _T_51; // @[package.scala:16:47]
wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47]
wire _invalidate_refill_T_2 = _invalidate_refill_T | _invalidate_refill_T_1; // @[package.scala:16:47, :81:59]
wire invalidate_refill = _invalidate_refill_T_2 | io_sfence_valid_0; // @[package.scala:81:59]
wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77]
wire _mpu_ppn_T_22; // @[TLB.scala:170:77]
wire _mpu_ppn_T_21; // @[TLB.scala:170:77]
wire _mpu_ppn_T_20; // @[TLB.scala:170:77]
wire _mpu_ppn_T_19; // @[TLB.scala:170:77]
wire _mpu_ppn_T_18; // @[TLB.scala:170:77]
wire _mpu_ppn_T_17; // @[TLB.scala:170:77]
wire _mpu_ppn_T_16; // @[TLB.scala:170:77]
wire _mpu_ppn_T_15; // @[TLB.scala:170:77]
wire _mpu_ppn_T_14; // @[TLB.scala:170:77]
wire _mpu_ppn_T_13; // @[TLB.scala:170:77]
wire _mpu_ppn_T_12; // @[TLB.scala:170:77]
wire _mpu_ppn_T_11; // @[TLB.scala:170:77]
wire _mpu_ppn_T_10; // @[TLB.scala:170:77]
wire _mpu_ppn_T_9; // @[TLB.scala:170:77]
wire _mpu_ppn_T_8; // @[TLB.scala:170:77]
wire _mpu_ppn_T_7; // @[TLB.scala:170:77]
wire _mpu_ppn_T_6; // @[TLB.scala:170:77]
wire _mpu_ppn_T_5; // @[TLB.scala:170:77]
wire _mpu_ppn_T_4; // @[TLB.scala:170:77]
wire _mpu_ppn_T_3; // @[TLB.scala:170:77]
wire _mpu_ppn_T_2; // @[TLB.scala:170:77]
wire _mpu_ppn_T_1; // @[TLB.scala:170:77]
assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77]
assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77]
assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77]
assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77]
assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77]
assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77]
assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77]
assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77]
assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77]
assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77]
assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77]
assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77]
assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77]
assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77]
assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77]
assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77]
assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77]
assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77]
assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77]
assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77]
assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77]
assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77]
assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77]
wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77]
wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25]
wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56]
wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28]
assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28]
wire _hitsVec_ignore_T_13; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28]
wire _ppn_ignore_T_8; // @[TLB.scala:197:28]
assign _ppn_ignore_T_8 = _GEN; // @[TLB.scala:197:28]
wire _ignore_T_13; // @[TLB.scala:182:28]
assign _ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28]
wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}]
wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}]
wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56]
wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}]
wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}]
wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146]
wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}]
wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20]
wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52]
wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46]
wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82]
wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}]
wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_67 = mpu_physaddr; // @[TLB.scala:414:25]
wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25]
wire _mpu_priv_T = do_refill | io_req_bits_passthrough_0; // @[TLB.scala:318:7, :408:29, :415:52]
wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}]
wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, io_req_bits_prv_0}; // @[TLB.scala:318:7, :415:103]
wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}]
wire cacheable; // @[TLB.scala:425:41]
wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24]
wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46]
wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_50 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65]
wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31]
assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31]
assign _homogeneous_T_72 = _GEN_0; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46]
wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31]
assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_60; // @[Parameters.scala:137:31]
assign _homogeneous_T_60 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_77; // @[Parameters.scala:137:31]
assign _homogeneous_T_77 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31]
assign _homogeneous_T_109 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_116; // @[Parameters.scala:137:31]
assign _homogeneous_T_116 = _GEN_1; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46]
wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46]
wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46]
wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46]
wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_30; // @[Parameters.scala:137:31]
assign _homogeneous_T_30 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_82; // @[Parameters.scala:137:31]
assign _homogeneous_T_82 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_97; // @[Parameters.scala:137:31]
assign _homogeneous_T_97 = _GEN_2; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46]
wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46]
wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_40 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46]
wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15]
wire [39:0] _homogeneous_T_45; // @[Parameters.scala:137:31]
assign _homogeneous_T_45 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_87; // @[Parameters.scala:137:31]
assign _homogeneous_T_87 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_102; // @[Parameters.scala:137:31]
assign _homogeneous_T_102 = _GEN_3; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46]
wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_51 = _homogeneous_T_50 | _homogeneous_T_9; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_52 = _homogeneous_T_51 | _homogeneous_T_14; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_53 = _homogeneous_T_52 | _homogeneous_T_19; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_54 = _homogeneous_T_53 | _homogeneous_T_24; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_55 = _homogeneous_T_54 | _homogeneous_T_29; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_56 = _homogeneous_T_55 | _homogeneous_T_34; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_57 = _homogeneous_T_56 | _homogeneous_T_39; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_58 = _homogeneous_T_57 | _homogeneous_T_44; // @[TLBPermissions.scala:101:65]
wire homogeneous = _homogeneous_T_58 | _homogeneous_T_49; // @[TLBPermissions.scala:101:65]
wire [40:0] _homogeneous_T_61 = {1'h0, _homogeneous_T_60}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_62 = _homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_63 = _homogeneous_T_62; // @[Parameters.scala:137:46]
wire _homogeneous_T_64 = _homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_65 = _homogeneous_T_64; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_66 = ~_homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}]
wire [40:0] _homogeneous_T_68 = {1'h0, _homogeneous_T_67}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_69 = _homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_70 = _homogeneous_T_69; // @[Parameters.scala:137:46]
wire _homogeneous_T_71 = _homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_92 = _homogeneous_T_71; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46]
wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _homogeneous_T_78 = {1'h0, _homogeneous_T_77}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_79 = _homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_80 = _homogeneous_T_79; // @[Parameters.scala:137:46]
wire _homogeneous_T_81 = _homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _homogeneous_T_83 = {1'h0, _homogeneous_T_82}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_84 = _homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_85 = _homogeneous_T_84; // @[Parameters.scala:137:46]
wire _homogeneous_T_86 = _homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _homogeneous_T_88 = {1'h0, _homogeneous_T_87}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_89 = _homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_90 = _homogeneous_T_89; // @[Parameters.scala:137:46]
wire _homogeneous_T_91 = _homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_93 = _homogeneous_T_92 | _homogeneous_T_76; // @[TLBPermissions.scala:85:66]
wire _homogeneous_T_94 = _homogeneous_T_93 | _homogeneous_T_81; // @[TLBPermissions.scala:85:66]
wire _homogeneous_T_95 = _homogeneous_T_94 | _homogeneous_T_86; // @[TLBPermissions.scala:85:66]
wire _homogeneous_T_96 = _homogeneous_T_95 | _homogeneous_T_91; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_98 = {1'h0, _homogeneous_T_97}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_99 = _homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_100 = _homogeneous_T_99; // @[Parameters.scala:137:46]
wire _homogeneous_T_101 = _homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_107 = _homogeneous_T_101; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_103 = {1'h0, _homogeneous_T_102}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_104 = _homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_105 = _homogeneous_T_104; // @[Parameters.scala:137:46]
wire _homogeneous_T_106 = _homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_108 = _homogeneous_T_107 | _homogeneous_T_106; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46]
wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_114 = _homogeneous_T_113; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_115 = ~_homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}]
wire [40:0] _homogeneous_T_117 = {1'h0, _homogeneous_T_116}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_118 = _homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_119 = _homogeneous_T_118; // @[Parameters.scala:137:46]
wire _homogeneous_T_120 = _homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_121 = _homogeneous_T_120; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_122 = ~_homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}]
wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39]
wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46]
wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}]
wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33]
wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}]
wire prot_r = _prot_r_T_1 & _pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}]
wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24]
wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33]
wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}]
wire prot_w = _prot_w_T_1 & _pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}]
wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24]
wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33]
wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}]
wire prot_x = _prot_x_T_1 & _pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}]
wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24]
wire _GEN_4 = sectored_entries_0_0_valid_0 | sectored_entries_0_0_valid_1; // @[package.scala:81:59]
wire _sector_hits_T; // @[package.scala:81:59]
assign _sector_hits_T = _GEN_4; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T = _GEN_4; // @[package.scala:81:59]
wire _sector_hits_T_1 = _sector_hits_T | sectored_entries_0_0_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_2 = _sector_hits_T_1 | sectored_entries_0_0_valid_3; // @[package.scala:81:59]
wire [26:0] _T_176 = sectored_entries_0_0_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_3; // @[TLB.scala:174:61]
assign _sector_hits_T_3 = _T_176; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T; // @[TLB.scala:174:61]
assign _hitsVec_T = _T_176; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_4 = _sector_hits_T_3[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_5 = _sector_hits_T_4 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_6 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_7 = _sector_hits_T_5 & _sector_hits_T_6; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_0 = _sector_hits_T_2 & _sector_hits_T_7; // @[package.scala:81:59]
wire _GEN_5 = sectored_entries_0_1_valid_0 | sectored_entries_0_1_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_8; // @[package.scala:81:59]
assign _sector_hits_T_8 = _GEN_5; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_3; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_3 = _GEN_5; // @[package.scala:81:59]
wire _sector_hits_T_9 = _sector_hits_T_8 | sectored_entries_0_1_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_10 = _sector_hits_T_9 | sectored_entries_0_1_valid_3; // @[package.scala:81:59]
wire [26:0] _T_597 = sectored_entries_0_1_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_11; // @[TLB.scala:174:61]
assign _sector_hits_T_11 = _T_597; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_6; // @[TLB.scala:174:61]
assign _hitsVec_T_6 = _T_597; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_12 = _sector_hits_T_11[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_13 = _sector_hits_T_12 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_14 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_15 = _sector_hits_T_13 & _sector_hits_T_14; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_1 = _sector_hits_T_10 & _sector_hits_T_15; // @[package.scala:81:59]
wire _GEN_6 = sectored_entries_0_2_valid_0 | sectored_entries_0_2_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_16; // @[package.scala:81:59]
assign _sector_hits_T_16 = _GEN_6; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_6; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_6 = _GEN_6; // @[package.scala:81:59]
wire _sector_hits_T_17 = _sector_hits_T_16 | sectored_entries_0_2_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_18 = _sector_hits_T_17 | sectored_entries_0_2_valid_3; // @[package.scala:81:59]
wire [26:0] _T_1018 = sectored_entries_0_2_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_19; // @[TLB.scala:174:61]
assign _sector_hits_T_19 = _T_1018; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_12; // @[TLB.scala:174:61]
assign _hitsVec_T_12 = _T_1018; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_20 = _sector_hits_T_19[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_21 = _sector_hits_T_20 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_22 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_23 = _sector_hits_T_21 & _sector_hits_T_22; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_2 = _sector_hits_T_18 & _sector_hits_T_23; // @[package.scala:81:59]
wire _GEN_7 = sectored_entries_0_3_valid_0 | sectored_entries_0_3_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_24; // @[package.scala:81:59]
assign _sector_hits_T_24 = _GEN_7; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_9; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_9 = _GEN_7; // @[package.scala:81:59]
wire _sector_hits_T_25 = _sector_hits_T_24 | sectored_entries_0_3_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_26 = _sector_hits_T_25 | sectored_entries_0_3_valid_3; // @[package.scala:81:59]
wire [26:0] _T_1439 = sectored_entries_0_3_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_27; // @[TLB.scala:174:61]
assign _sector_hits_T_27 = _T_1439; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_18; // @[TLB.scala:174:61]
assign _hitsVec_T_18 = _T_1439; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_28 = _sector_hits_T_27[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_29 = _sector_hits_T_28 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_30 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_31 = _sector_hits_T_29 & _sector_hits_T_30; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_3 = _sector_hits_T_26 & _sector_hits_T_31; // @[package.scala:81:59]
wire _GEN_8 = sectored_entries_0_4_valid_0 | sectored_entries_0_4_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_32; // @[package.scala:81:59]
assign _sector_hits_T_32 = _GEN_8; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_12; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_12 = _GEN_8; // @[package.scala:81:59]
wire _sector_hits_T_33 = _sector_hits_T_32 | sectored_entries_0_4_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_34 = _sector_hits_T_33 | sectored_entries_0_4_valid_3; // @[package.scala:81:59]
wire [26:0] _T_1860 = sectored_entries_0_4_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_35; // @[TLB.scala:174:61]
assign _sector_hits_T_35 = _T_1860; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_24; // @[TLB.scala:174:61]
assign _hitsVec_T_24 = _T_1860; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_36 = _sector_hits_T_35[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_37 = _sector_hits_T_36 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_38 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_39 = _sector_hits_T_37 & _sector_hits_T_38; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_4 = _sector_hits_T_34 & _sector_hits_T_39; // @[package.scala:81:59]
wire _GEN_9 = sectored_entries_0_5_valid_0 | sectored_entries_0_5_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_40; // @[package.scala:81:59]
assign _sector_hits_T_40 = _GEN_9; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_15; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_15 = _GEN_9; // @[package.scala:81:59]
wire _sector_hits_T_41 = _sector_hits_T_40 | sectored_entries_0_5_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_42 = _sector_hits_T_41 | sectored_entries_0_5_valid_3; // @[package.scala:81:59]
wire [26:0] _T_2281 = sectored_entries_0_5_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_43; // @[TLB.scala:174:61]
assign _sector_hits_T_43 = _T_2281; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_30; // @[TLB.scala:174:61]
assign _hitsVec_T_30 = _T_2281; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_44 = _sector_hits_T_43[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_45 = _sector_hits_T_44 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_46 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_47 = _sector_hits_T_45 & _sector_hits_T_46; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_5 = _sector_hits_T_42 & _sector_hits_T_47; // @[package.scala:81:59]
wire _GEN_10 = sectored_entries_0_6_valid_0 | sectored_entries_0_6_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_48; // @[package.scala:81:59]
assign _sector_hits_T_48 = _GEN_10; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_18; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_18 = _GEN_10; // @[package.scala:81:59]
wire _sector_hits_T_49 = _sector_hits_T_48 | sectored_entries_0_6_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_50 = _sector_hits_T_49 | sectored_entries_0_6_valid_3; // @[package.scala:81:59]
wire [26:0] _T_2702 = sectored_entries_0_6_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_51; // @[TLB.scala:174:61]
assign _sector_hits_T_51 = _T_2702; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_36; // @[TLB.scala:174:61]
assign _hitsVec_T_36 = _T_2702; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_52 = _sector_hits_T_51[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_53 = _sector_hits_T_52 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_54 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_55 = _sector_hits_T_53 & _sector_hits_T_54; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_6 = _sector_hits_T_50 & _sector_hits_T_55; // @[package.scala:81:59]
wire _GEN_11 = sectored_entries_0_7_valid_0 | sectored_entries_0_7_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_56; // @[package.scala:81:59]
assign _sector_hits_T_56 = _GEN_11; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_21; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_21 = _GEN_11; // @[package.scala:81:59]
wire _sector_hits_T_57 = _sector_hits_T_56 | sectored_entries_0_7_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_58 = _sector_hits_T_57 | sectored_entries_0_7_valid_3; // @[package.scala:81:59]
wire [26:0] _T_3123 = sectored_entries_0_7_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_59; // @[TLB.scala:174:61]
assign _sector_hits_T_59 = _T_3123; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_42; // @[TLB.scala:174:61]
assign _hitsVec_T_42 = _T_3123; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_60 = _sector_hits_T_59[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_61 = _sector_hits_T_60 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_62 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_63 = _sector_hits_T_61 & _sector_hits_T_62; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_7 = _sector_hits_T_58 & _sector_hits_T_63; // @[package.scala:81:59]
wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30]
wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30]
wire [26:0] _T_3446 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30]
wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52]
assign _superpage_hits_T = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52]
assign _superpage_hits_T_5 = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52]
assign _superpage_hits_T_10 = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_48; // @[TLB.scala:183:52]
assign _hitsVec_T_48 = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_53; // @[TLB.scala:183:52]
assign _hitsVec_T_53 = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_58; // @[TLB.scala:183:52]
assign _hitsVec_T_58 = _T_3446; // @[TLB.scala:183:52]
wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}]
wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}]
wire _GEN_12 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30]
wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28]
assign _superpage_hits_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28]
wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28]
wire _ppn_ignore_T; // @[TLB.scala:197:28]
assign _ppn_ignore_T = _GEN_12; // @[TLB.scala:182:28, :197:28]
wire _ignore_T_1; // @[TLB.scala:182:28]
assign _ignore_T_1 = _GEN_12; // @[TLB.scala:182:28]
wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}]
wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_8 = superpage_hits_ignore_1 | _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}]
wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}]
wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29]
wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30]
wire superpage_hits_tagMatch_1 = superpage_entries_1_valid_0 & _superpage_hits_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30]
wire [26:0] _T_3544 = superpage_entries_1_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30]
wire [26:0] _superpage_hits_T_14; // @[TLB.scala:183:52]
assign _superpage_hits_T_14 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_19; // @[TLB.scala:183:52]
assign _superpage_hits_T_19 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_24; // @[TLB.scala:183:52]
assign _superpage_hits_T_24 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_63; // @[TLB.scala:183:52]
assign _hitsVec_T_63 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_68; // @[TLB.scala:183:52]
assign _hitsVec_T_68 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_73; // @[TLB.scala:183:52]
assign _hitsVec_T_73 = _T_3544; // @[TLB.scala:183:52]
wire [8:0] _superpage_hits_T_15 = _superpage_hits_T_14[26:18]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_16 = _superpage_hits_T_15 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_17 = _superpage_hits_T_16; // @[TLB.scala:183:{40,79}]
wire _superpage_hits_T_18 = superpage_hits_tagMatch_1 & _superpage_hits_T_17; // @[TLB.scala:178:33, :183:{29,40}]
wire _GEN_13 = superpage_entries_1_level == 2'h0; // @[TLB.scala:182:28, :341:30]
wire _superpage_hits_ignore_T_4; // @[TLB.scala:182:28]
assign _superpage_hits_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28]
wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28]
wire _ppn_ignore_T_2; // @[TLB.scala:197:28]
assign _ppn_ignore_T_2 = _GEN_13; // @[TLB.scala:182:28, :197:28]
wire _ignore_T_4; // @[TLB.scala:182:28]
assign _ignore_T_4 = _GEN_13; // @[TLB.scala:182:28]
wire superpage_hits_ignore_4 = _superpage_hits_ignore_T_4; // @[TLB.scala:182:{28,34}]
wire [8:0] _superpage_hits_T_20 = _superpage_hits_T_19[17:9]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_21 = _superpage_hits_T_20 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_22 = superpage_hits_ignore_4 | _superpage_hits_T_21; // @[TLB.scala:182:34, :183:{40,79}]
wire _superpage_hits_T_23 = _superpage_hits_T_18 & _superpage_hits_T_22; // @[TLB.scala:183:{29,40}]
wire superpage_hits_1 = _superpage_hits_T_23; // @[TLB.scala:183:29]
wire _superpage_hits_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _superpage_hits_T_25 = _superpage_hits_T_24[8:0]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_26 = _superpage_hits_T_25 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30]
wire superpage_hits_tagMatch_2 = superpage_entries_2_valid_0 & _superpage_hits_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30]
wire [26:0] _T_3642 = superpage_entries_2_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30]
wire [26:0] _superpage_hits_T_28; // @[TLB.scala:183:52]
assign _superpage_hits_T_28 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_33; // @[TLB.scala:183:52]
assign _superpage_hits_T_33 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_38; // @[TLB.scala:183:52]
assign _superpage_hits_T_38 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_78; // @[TLB.scala:183:52]
assign _hitsVec_T_78 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_83; // @[TLB.scala:183:52]
assign _hitsVec_T_83 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_88; // @[TLB.scala:183:52]
assign _hitsVec_T_88 = _T_3642; // @[TLB.scala:183:52]
wire [8:0] _superpage_hits_T_29 = _superpage_hits_T_28[26:18]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_30 = _superpage_hits_T_29 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_31 = _superpage_hits_T_30; // @[TLB.scala:183:{40,79}]
wire _superpage_hits_T_32 = superpage_hits_tagMatch_2 & _superpage_hits_T_31; // @[TLB.scala:178:33, :183:{29,40}]
wire _GEN_14 = superpage_entries_2_level == 2'h0; // @[TLB.scala:182:28, :341:30]
wire _superpage_hits_ignore_T_7; // @[TLB.scala:182:28]
assign _superpage_hits_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28]
wire _hitsVec_ignore_T_7; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28]
wire _ppn_ignore_T_4; // @[TLB.scala:197:28]
assign _ppn_ignore_T_4 = _GEN_14; // @[TLB.scala:182:28, :197:28]
wire _ignore_T_7; // @[TLB.scala:182:28]
assign _ignore_T_7 = _GEN_14; // @[TLB.scala:182:28]
wire superpage_hits_ignore_7 = _superpage_hits_ignore_T_7; // @[TLB.scala:182:{28,34}]
wire [8:0] _superpage_hits_T_34 = _superpage_hits_T_33[17:9]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_35 = _superpage_hits_T_34 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_36 = superpage_hits_ignore_7 | _superpage_hits_T_35; // @[TLB.scala:182:34, :183:{40,79}]
wire _superpage_hits_T_37 = _superpage_hits_T_32 & _superpage_hits_T_36; // @[TLB.scala:183:{29,40}]
wire superpage_hits_2 = _superpage_hits_T_37; // @[TLB.scala:183:29]
wire _superpage_hits_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _superpage_hits_T_39 = _superpage_hits_T_38[8:0]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_40 = _superpage_hits_T_39 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30]
wire superpage_hits_tagMatch_3 = superpage_entries_3_valid_0 & _superpage_hits_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30]
wire [26:0] _T_3740 = superpage_entries_3_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30]
wire [26:0] _superpage_hits_T_42; // @[TLB.scala:183:52]
assign _superpage_hits_T_42 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_47; // @[TLB.scala:183:52]
assign _superpage_hits_T_47 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_52; // @[TLB.scala:183:52]
assign _superpage_hits_T_52 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_93; // @[TLB.scala:183:52]
assign _hitsVec_T_93 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_98; // @[TLB.scala:183:52]
assign _hitsVec_T_98 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_103; // @[TLB.scala:183:52]
assign _hitsVec_T_103 = _T_3740; // @[TLB.scala:183:52]
wire [8:0] _superpage_hits_T_43 = _superpage_hits_T_42[26:18]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_44 = _superpage_hits_T_43 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_45 = _superpage_hits_T_44; // @[TLB.scala:183:{40,79}]
wire _superpage_hits_T_46 = superpage_hits_tagMatch_3 & _superpage_hits_T_45; // @[TLB.scala:178:33, :183:{29,40}]
wire _GEN_15 = superpage_entries_3_level == 2'h0; // @[TLB.scala:182:28, :341:30]
wire _superpage_hits_ignore_T_10; // @[TLB.scala:182:28]
assign _superpage_hits_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28]
wire _hitsVec_ignore_T_10; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28]
wire _ppn_ignore_T_6; // @[TLB.scala:197:28]
assign _ppn_ignore_T_6 = _GEN_15; // @[TLB.scala:182:28, :197:28]
wire _ignore_T_10; // @[TLB.scala:182:28]
assign _ignore_T_10 = _GEN_15; // @[TLB.scala:182:28]
wire superpage_hits_ignore_10 = _superpage_hits_ignore_T_10; // @[TLB.scala:182:{28,34}]
wire [8:0] _superpage_hits_T_48 = _superpage_hits_T_47[17:9]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_49 = _superpage_hits_T_48 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_50 = superpage_hits_ignore_10 | _superpage_hits_T_49; // @[TLB.scala:182:34, :183:{40,79}]
wire _superpage_hits_T_51 = _superpage_hits_T_46 & _superpage_hits_T_50; // @[TLB.scala:183:{29,40}]
wire superpage_hits_3 = _superpage_hits_T_51; // @[TLB.scala:183:29]
wire _superpage_hits_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _superpage_hits_T_53 = _superpage_hits_T_52[8:0]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_54 = _superpage_hits_T_53 == 9'h0; // @[TLB.scala:183:{58,79}]
wire [1:0] hitsVec_idx = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_1 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_2 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_3 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_4 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_5 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_6 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_7 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_24 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_48 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_72 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_96 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_120 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_144 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_168 = vpn[1:0]; // @[package.scala:163:13]
wire [24:0] _hitsVec_T_1 = _hitsVec_T[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_2 = _hitsVec_T_1 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_3 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_16 = {{sectored_entries_0_0_valid_3}, {sectored_entries_0_0_valid_2}, {sectored_entries_0_0_valid_1}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_5 = _GEN_16[hitsVec_idx] & _hitsVec_T_4; // @[package.scala:163:13]
wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_7 = _hitsVec_T_6[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_8 = _hitsVec_T_7 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_9 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_17 = {{sectored_entries_0_1_valid_3}, {sectored_entries_0_1_valid_2}, {sectored_entries_0_1_valid_1}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_11 = _GEN_17[hitsVec_idx_1] & _hitsVec_T_10; // @[package.scala:163:13]
wire hitsVec_1 = vm_enabled & _hitsVec_T_11; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_13 = _hitsVec_T_12[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_14 = _hitsVec_T_13 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_15 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_18 = {{sectored_entries_0_2_valid_3}, {sectored_entries_0_2_valid_2}, {sectored_entries_0_2_valid_1}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_17 = _GEN_18[hitsVec_idx_2] & _hitsVec_T_16; // @[package.scala:163:13]
wire hitsVec_2 = vm_enabled & _hitsVec_T_17; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_19 = _hitsVec_T_18[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_20 = _hitsVec_T_19 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_21 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_19 = {{sectored_entries_0_3_valid_3}, {sectored_entries_0_3_valid_2}, {sectored_entries_0_3_valid_1}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_23 = _GEN_19[hitsVec_idx_3] & _hitsVec_T_22; // @[package.scala:163:13]
wire hitsVec_3 = vm_enabled & _hitsVec_T_23; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_25 = _hitsVec_T_24[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_26 = _hitsVec_T_25 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_27 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_28 = _hitsVec_T_26 & _hitsVec_T_27; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_20 = {{sectored_entries_0_4_valid_3}, {sectored_entries_0_4_valid_2}, {sectored_entries_0_4_valid_1}, {sectored_entries_0_4_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_29 = _GEN_20[hitsVec_idx_4] & _hitsVec_T_28; // @[package.scala:163:13]
wire hitsVec_4 = vm_enabled & _hitsVec_T_29; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_31 = _hitsVec_T_30[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_32 = _hitsVec_T_31 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_33 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_34 = _hitsVec_T_32 & _hitsVec_T_33; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_21 = {{sectored_entries_0_5_valid_3}, {sectored_entries_0_5_valid_2}, {sectored_entries_0_5_valid_1}, {sectored_entries_0_5_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_35 = _GEN_21[hitsVec_idx_5] & _hitsVec_T_34; // @[package.scala:163:13]
wire hitsVec_5 = vm_enabled & _hitsVec_T_35; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_37 = _hitsVec_T_36[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_38 = _hitsVec_T_37 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_39 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_40 = _hitsVec_T_38 & _hitsVec_T_39; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_22 = {{sectored_entries_0_6_valid_3}, {sectored_entries_0_6_valid_2}, {sectored_entries_0_6_valid_1}, {sectored_entries_0_6_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_41 = _GEN_22[hitsVec_idx_6] & _hitsVec_T_40; // @[package.scala:163:13]
wire hitsVec_6 = vm_enabled & _hitsVec_T_41; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_43 = _hitsVec_T_42[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_44 = _hitsVec_T_43 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_45 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_46 = _hitsVec_T_44 & _hitsVec_T_45; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_23 = {{sectored_entries_0_7_valid_3}, {sectored_entries_0_7_valid_2}, {sectored_entries_0_7_valid_1}, {sectored_entries_0_7_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_47 = _GEN_23[hitsVec_idx_7] & _hitsVec_T_46; // @[package.scala:163:13]
wire hitsVec_7 = vm_enabled & _hitsVec_T_47; // @[TLB.scala:188:18, :399:61, :440:44]
wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30]
wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30]
wire [8:0] _hitsVec_T_49 = _hitsVec_T_48[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_50 = _hitsVec_T_49 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_51 = _hitsVec_T_50; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_52 = hitsVec_tagMatch & _hitsVec_T_51; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_54 = _hitsVec_T_53[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_55 = _hitsVec_T_54 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_56 = hitsVec_ignore_1 | _hitsVec_T_55; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_57 = _hitsVec_T_52 & _hitsVec_T_56; // @[TLB.scala:183:{29,40}]
wire _hitsVec_T_62 = _hitsVec_T_57; // @[TLB.scala:183:29]
wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _hitsVec_T_59 = _hitsVec_T_58[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_60 = _hitsVec_T_59 == 9'h0; // @[TLB.scala:183:{58,79}]
wire hitsVec_8 = vm_enabled & _hitsVec_T_62; // @[TLB.scala:183:29, :399:61, :440:44]
wire _hitsVec_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30]
wire hitsVec_tagMatch_1 = superpage_entries_1_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30]
wire [8:0] _hitsVec_T_64 = _hitsVec_T_63[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_65 = _hitsVec_T_64 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_66 = _hitsVec_T_65; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_67 = hitsVec_tagMatch_1 & _hitsVec_T_66; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_69 = _hitsVec_T_68[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_70 = _hitsVec_T_69 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_71 = hitsVec_ignore_4 | _hitsVec_T_70; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_72 = _hitsVec_T_67 & _hitsVec_T_71; // @[TLB.scala:183:{29,40}]
wire _hitsVec_T_77 = _hitsVec_T_72; // @[TLB.scala:183:29]
wire _hitsVec_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _hitsVec_T_74 = _hitsVec_T_73[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_75 = _hitsVec_T_74 == 9'h0; // @[TLB.scala:183:{58,79}]
wire hitsVec_9 = vm_enabled & _hitsVec_T_77; // @[TLB.scala:183:29, :399:61, :440:44]
wire _hitsVec_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30]
wire hitsVec_tagMatch_2 = superpage_entries_2_valid_0 & _hitsVec_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30]
wire [8:0] _hitsVec_T_79 = _hitsVec_T_78[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_80 = _hitsVec_T_79 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_81 = _hitsVec_T_80; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_82 = hitsVec_tagMatch_2 & _hitsVec_T_81; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_7 = _hitsVec_ignore_T_7; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_84 = _hitsVec_T_83[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_85 = _hitsVec_T_84 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_86 = hitsVec_ignore_7 | _hitsVec_T_85; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_87 = _hitsVec_T_82 & _hitsVec_T_86; // @[TLB.scala:183:{29,40}]
wire _hitsVec_T_92 = _hitsVec_T_87; // @[TLB.scala:183:29]
wire _hitsVec_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _hitsVec_T_89 = _hitsVec_T_88[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_90 = _hitsVec_T_89 == 9'h0; // @[TLB.scala:183:{58,79}]
wire hitsVec_10 = vm_enabled & _hitsVec_T_92; // @[TLB.scala:183:29, :399:61, :440:44]
wire _hitsVec_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30]
wire hitsVec_tagMatch_3 = superpage_entries_3_valid_0 & _hitsVec_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30]
wire [8:0] _hitsVec_T_94 = _hitsVec_T_93[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_95 = _hitsVec_T_94 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_96 = _hitsVec_T_95; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_97 = hitsVec_tagMatch_3 & _hitsVec_T_96; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_10 = _hitsVec_ignore_T_10; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_99 = _hitsVec_T_98[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_100 = _hitsVec_T_99 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_101 = hitsVec_ignore_10 | _hitsVec_T_100; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_102 = _hitsVec_T_97 & _hitsVec_T_101; // @[TLB.scala:183:{29,40}]
wire _hitsVec_T_107 = _hitsVec_T_102; // @[TLB.scala:183:29]
wire _hitsVec_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _hitsVec_T_104 = _hitsVec_T_103[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_105 = _hitsVec_T_104 == 9'h0; // @[TLB.scala:183:{58,79}]
wire hitsVec_11 = vm_enabled & _hitsVec_T_107; // @[TLB.scala:183:29, :399:61, :440:44]
wire _hitsVec_tagMatch_T_4 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56]
wire hitsVec_tagMatch_4 = special_entry_valid_0 & _hitsVec_tagMatch_T_4; // @[TLB.scala:178:{33,43}, :346:56]
wire [26:0] _T_3838 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56]
wire [26:0] _hitsVec_T_108; // @[TLB.scala:183:52]
assign _hitsVec_T_108 = _T_3838; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_113; // @[TLB.scala:183:52]
assign _hitsVec_T_113 = _T_3838; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_118; // @[TLB.scala:183:52]
assign _hitsVec_T_118 = _T_3838; // @[TLB.scala:183:52]
wire [8:0] _hitsVec_T_109 = _hitsVec_T_108[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_110 = _hitsVec_T_109 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_111 = _hitsVec_T_110; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_112 = hitsVec_tagMatch_4 & _hitsVec_T_111; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_13 = _hitsVec_ignore_T_13; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_114 = _hitsVec_T_113[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_115 = _hitsVec_T_114 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_116 = hitsVec_ignore_13 | _hitsVec_T_115; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_117 = _hitsVec_T_112 & _hitsVec_T_116; // @[TLB.scala:183:{29,40}]
wire _hitsVec_ignore_T_14 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56]
wire hitsVec_ignore_14 = _hitsVec_ignore_T_14; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_119 = _hitsVec_T_118[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_120 = _hitsVec_T_119 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_121 = hitsVec_ignore_14 | _hitsVec_T_120; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_122 = _hitsVec_T_117 & _hitsVec_T_121; // @[TLB.scala:183:{29,40}]
wire hitsVec_12 = vm_enabled & _hitsVec_T_122; // @[TLB.scala:183:29, :399:61, :440:44]
wire [1:0] real_hits_lo_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27]
wire [2:0] real_hits_lo_lo = {real_hits_lo_lo_hi, hitsVec_0}; // @[package.scala:45:27]
wire [1:0] real_hits_lo_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27]
wire [2:0] real_hits_lo_hi = {real_hits_lo_hi_hi, hitsVec_3}; // @[package.scala:45:27]
wire [5:0] real_hits_lo = {real_hits_lo_hi, real_hits_lo_lo}; // @[package.scala:45:27]
wire [1:0] real_hits_hi_lo_hi = {hitsVec_8, hitsVec_7}; // @[package.scala:45:27]
wire [2:0] real_hits_hi_lo = {real_hits_hi_lo_hi, hitsVec_6}; // @[package.scala:45:27]
wire [1:0] real_hits_hi_hi_lo = {hitsVec_10, hitsVec_9}; // @[package.scala:45:27]
wire [1:0] real_hits_hi_hi_hi = {hitsVec_12, hitsVec_11}; // @[package.scala:45:27]
wire [3:0] real_hits_hi_hi = {real_hits_hi_hi_hi, real_hits_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] real_hits_hi = {real_hits_hi_hi, real_hits_hi_lo}; // @[package.scala:45:27]
wire [12:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27]
wire [12:0] _tlb_hit_T = real_hits; // @[package.scala:45:27]
wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18]
wire [13:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27]
wire _newEntry_g_T; // @[TLB.scala:453:25]
wire _newEntry_sw_T_6; // @[PTW.scala:151:40]
wire _newEntry_sx_T_5; // @[PTW.scala:153:35]
wire _newEntry_sr_T_5; // @[PTW.scala:149:35]
wire newEntry_g; // @[TLB.scala:449:24]
wire newEntry_sw; // @[TLB.scala:449:24]
wire newEntry_sx; // @[TLB.scala:449:24]
wire newEntry_sr; // @[TLB.scala:449:24]
wire newEntry_ppp; // @[TLB.scala:449:24]
wire newEntry_pal; // @[TLB.scala:449:24]
wire newEntry_paa; // @[TLB.scala:449:24]
wire newEntry_eff; // @[TLB.scala:449:24]
assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25]
assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25]
wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53]
wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7]
wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sr_T_1; // @[TLB.scala:318:7]
wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7]
wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7]
assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24]
wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7]
wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sw_T_1; // @[TLB.scala:318:7]
wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7]
wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7]
assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24]
wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7]
wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sx_T_1; // @[TLB.scala:318:7]
wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7]
wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7]
assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24]
wire [1:0] _GEN_24 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] _GEN_25 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [1:0] _GEN_26 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [1:0] _GEN_27 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [1:0] _GEN_28 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [1:0] _GEN_29 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [1:0] _GEN_30 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [20:0] _GEN_31 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24]
wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_0_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_1_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_2_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_3_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_4_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_5_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_6_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_7_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24]
wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire _superpage_entries_1_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire _superpage_entries_2_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire _superpage_entries_3_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_lo_lo_hi = {superpage_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_1_data_0_lo_lo = {superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_lo_hi_lo = {superpage_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_1_data_0_lo_hi_hi = {superpage_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_1_data_0_lo_hi = {superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_1_data_0_lo = {superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_hi_lo_lo = {superpage_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_1_data_0_hi_lo_hi = {superpage_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_1_data_0_hi_lo = {superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_hi_hi_lo = {superpage_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] superpage_entries_1_data_0_hi_hi_hi = {superpage_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_1_data_0_hi_hi = {superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_1_data_0_hi = {superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_1_data_0_T = {superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_lo_lo_hi = {superpage_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_2_data_0_lo_lo = {superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_lo_hi_lo = {superpage_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_2_data_0_lo_hi_hi = {superpage_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_2_data_0_lo_hi = {superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_2_data_0_lo = {superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_hi_lo_lo = {superpage_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_2_data_0_hi_lo_hi = {superpage_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_2_data_0_hi_lo = {superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_hi_hi_lo = {superpage_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] superpage_entries_2_data_0_hi_hi_hi = {superpage_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_2_data_0_hi_hi = {superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_2_data_0_hi = {superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_2_data_0_T = {superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_lo_lo_hi = {superpage_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_3_data_0_lo_lo = {superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_lo_hi_lo = {superpage_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_3_data_0_lo_hi_hi = {superpage_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_3_data_0_lo_hi = {superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_3_data_0_lo = {superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_hi_lo_lo = {superpage_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_3_data_0_hi_lo_hi = {superpage_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_3_data_0_hi_lo = {superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_hi_hi_lo = {superpage_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] superpage_entries_3_data_0_hi_hi_hi = {superpage_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_3_data_0_hi_hi = {superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_3_data_0_hi = {superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_3_data_0_T = {superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] waddr_1 = r_sectored_hit_valid ? r_sectored_hit_bits : r_sectored_repl_addr; // @[TLB.scala:356:33, :357:27, :485:22]
wire [1:0] idx = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_1 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_2 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_3 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_4 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_5 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_6 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_7 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [2:0] sectored_entries_0_0_data_lo_lo_hi = {sectored_entries_0_0_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_0_data_lo_lo = {sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_0_data_lo_hi_lo = {sectored_entries_0_0_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_0_data_lo_hi_hi = {sectored_entries_0_0_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_0_data_lo_hi = {sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_0_data_lo = {sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_0_data_hi_lo_lo = {sectored_entries_0_0_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_0_data_hi_lo_hi = {sectored_entries_0_0_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_0_data_hi_lo = {sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_0_data_hi_hi_lo = {sectored_entries_0_0_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_0_data_hi_hi_hi = {sectored_entries_0_0_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_0_data_hi_hi = {sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_0_data_hi = {sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_0_data_T = {sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_lo_lo_hi = {sectored_entries_0_1_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_1_data_lo_lo = {sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_lo_hi_lo = {sectored_entries_0_1_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_1_data_lo_hi_hi = {sectored_entries_0_1_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_1_data_lo_hi = {sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_1_data_lo = {sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_hi_lo_lo = {sectored_entries_0_1_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_1_data_hi_lo_hi = {sectored_entries_0_1_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_1_data_hi_lo = {sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_hi_hi_lo = {sectored_entries_0_1_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_1_data_hi_hi_hi = {sectored_entries_0_1_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_1_data_hi_hi = {sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_1_data_hi = {sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_1_data_T = {sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_lo_lo_hi = {sectored_entries_0_2_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_2_data_lo_lo = {sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_lo_hi_lo = {sectored_entries_0_2_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_2_data_lo_hi_hi = {sectored_entries_0_2_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_2_data_lo_hi = {sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_2_data_lo = {sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_hi_lo_lo = {sectored_entries_0_2_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_2_data_hi_lo_hi = {sectored_entries_0_2_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_2_data_hi_lo = {sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_hi_hi_lo = {sectored_entries_0_2_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_2_data_hi_hi_hi = {sectored_entries_0_2_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_2_data_hi_hi = {sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_2_data_hi = {sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_2_data_T = {sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_lo_lo_hi = {sectored_entries_0_3_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_3_data_lo_lo = {sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_lo_hi_lo = {sectored_entries_0_3_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_3_data_lo_hi_hi = {sectored_entries_0_3_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_3_data_lo_hi = {sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_3_data_lo = {sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_hi_lo_lo = {sectored_entries_0_3_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_3_data_hi_lo_hi = {sectored_entries_0_3_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_3_data_hi_lo = {sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_hi_hi_lo = {sectored_entries_0_3_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_3_data_hi_hi_hi = {sectored_entries_0_3_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_3_data_hi_hi = {sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_3_data_hi = {sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_3_data_T = {sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_lo_lo_hi = {sectored_entries_0_4_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_4_data_lo_lo = {sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_lo_hi_lo = {sectored_entries_0_4_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_4_data_lo_hi_hi = {sectored_entries_0_4_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_4_data_lo_hi = {sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_4_data_lo = {sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_hi_lo_lo = {sectored_entries_0_4_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_4_data_hi_lo_hi = {sectored_entries_0_4_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_4_data_hi_lo = {sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_hi_hi_lo = {sectored_entries_0_4_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_4_data_hi_hi_hi = {sectored_entries_0_4_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_4_data_hi_hi = {sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_4_data_hi = {sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_4_data_T = {sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_lo_lo_hi = {sectored_entries_0_5_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_5_data_lo_lo = {sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_lo_hi_lo = {sectored_entries_0_5_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_5_data_lo_hi_hi = {sectored_entries_0_5_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_5_data_lo_hi = {sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_5_data_lo = {sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_hi_lo_lo = {sectored_entries_0_5_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_5_data_hi_lo_hi = {sectored_entries_0_5_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_5_data_hi_lo = {sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_hi_hi_lo = {sectored_entries_0_5_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_5_data_hi_hi_hi = {sectored_entries_0_5_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_5_data_hi_hi = {sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_5_data_hi = {sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_5_data_T = {sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_lo_lo_hi = {sectored_entries_0_6_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_6_data_lo_lo = {sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_lo_hi_lo = {sectored_entries_0_6_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_6_data_lo_hi_hi = {sectored_entries_0_6_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_6_data_lo_hi = {sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_6_data_lo = {sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_hi_lo_lo = {sectored_entries_0_6_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_6_data_hi_lo_hi = {sectored_entries_0_6_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_6_data_hi_lo = {sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_hi_hi_lo = {sectored_entries_0_6_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_6_data_hi_hi_hi = {sectored_entries_0_6_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_6_data_hi_hi = {sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_6_data_hi = {sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_6_data_T = {sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_lo_lo_hi = {sectored_entries_0_7_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_7_data_lo_lo = {sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_lo_hi_lo = {sectored_entries_0_7_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_7_data_lo_hi_hi = {sectored_entries_0_7_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_7_data_lo_hi = {sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_7_data_lo = {sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_hi_lo_lo = {sectored_entries_0_7_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_7_data_hi_lo_hi = {sectored_entries_0_7_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_7_data_hi_lo = {sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_hi_hi_lo = {sectored_entries_0_7_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_7_data_hi_hi_hi = {sectored_entries_0_7_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_7_data_hi_hi = {sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_7_data_hi = {sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_7_data_T = {sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24]
wire [19:0] _entries_T_23; // @[TLB.scala:170:77]
wire _entries_T_22; // @[TLB.scala:170:77]
wire _entries_T_21; // @[TLB.scala:170:77]
wire _entries_T_20; // @[TLB.scala:170:77]
wire _entries_T_19; // @[TLB.scala:170:77]
wire _entries_T_18; // @[TLB.scala:170:77]
wire _entries_T_17; // @[TLB.scala:170:77]
wire _entries_T_16; // @[TLB.scala:170:77]
wire _entries_T_15; // @[TLB.scala:170:77]
wire _entries_T_14; // @[TLB.scala:170:77]
wire _entries_T_13; // @[TLB.scala:170:77]
wire _entries_T_12; // @[TLB.scala:170:77]
wire _entries_T_11; // @[TLB.scala:170:77]
wire _entries_T_10; // @[TLB.scala:170:77]
wire _entries_T_9; // @[TLB.scala:170:77]
wire _entries_T_8; // @[TLB.scala:170:77]
wire _entries_T_7; // @[TLB.scala:170:77]
wire _entries_T_6; // @[TLB.scala:170:77]
wire _entries_T_5; // @[TLB.scala:170:77]
wire _entries_T_4; // @[TLB.scala:170:77]
wire _entries_T_3; // @[TLB.scala:170:77]
wire _entries_T_2; // @[TLB.scala:170:77]
wire _entries_T_1; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_32 = {{sectored_entries_0_0_data_3}, {sectored_entries_0_0_data_2}, {sectored_entries_0_0_data_1}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_1 = _GEN_32[_entries_T]; // @[package.scala:163:13]
assign _entries_T_1 = _entries_WIRE_1[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_fragmented_superpage = _entries_T_1; // @[TLB.scala:170:77]
assign _entries_T_2 = _entries_WIRE_1[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_c = _entries_T_2; // @[TLB.scala:170:77]
assign _entries_T_3 = _entries_WIRE_1[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_eff = _entries_T_3; // @[TLB.scala:170:77]
assign _entries_T_4 = _entries_WIRE_1[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_paa = _entries_T_4; // @[TLB.scala:170:77]
assign _entries_T_5 = _entries_WIRE_1[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_pal = _entries_T_5; // @[TLB.scala:170:77]
assign _entries_T_6 = _entries_WIRE_1[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_ppp = _entries_T_6; // @[TLB.scala:170:77]
assign _entries_T_7 = _entries_WIRE_1[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_pr = _entries_T_7; // @[TLB.scala:170:77]
assign _entries_T_8 = _entries_WIRE_1[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_px = _entries_T_8; // @[TLB.scala:170:77]
assign _entries_T_9 = _entries_WIRE_1[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_pw = _entries_T_9; // @[TLB.scala:170:77]
assign _entries_T_10 = _entries_WIRE_1[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_hr = _entries_T_10; // @[TLB.scala:170:77]
assign _entries_T_11 = _entries_WIRE_1[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_hx = _entries_T_11; // @[TLB.scala:170:77]
assign _entries_T_12 = _entries_WIRE_1[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_hw = _entries_T_12; // @[TLB.scala:170:77]
assign _entries_T_13 = _entries_WIRE_1[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_sr = _entries_T_13; // @[TLB.scala:170:77]
assign _entries_T_14 = _entries_WIRE_1[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_sx = _entries_T_14; // @[TLB.scala:170:77]
assign _entries_T_15 = _entries_WIRE_1[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_sw = _entries_T_15; // @[TLB.scala:170:77]
assign _entries_T_16 = _entries_WIRE_1[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_gf = _entries_T_16; // @[TLB.scala:170:77]
assign _entries_T_17 = _entries_WIRE_1[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_pf = _entries_T_17; // @[TLB.scala:170:77]
assign _entries_T_18 = _entries_WIRE_1[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_stage2 = _entries_T_18; // @[TLB.scala:170:77]
assign _entries_T_19 = _entries_WIRE_1[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_final = _entries_T_19; // @[TLB.scala:170:77]
assign _entries_T_20 = _entries_WIRE_1[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_ptw = _entries_T_20; // @[TLB.scala:170:77]
assign _entries_T_21 = _entries_WIRE_1[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_g = _entries_T_21; // @[TLB.scala:170:77]
assign _entries_T_22 = _entries_WIRE_1[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_u = _entries_T_22; // @[TLB.scala:170:77]
assign _entries_T_23 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_ppn = _entries_T_23; // @[TLB.scala:170:77]
wire [19:0] _entries_T_47; // @[TLB.scala:170:77]
wire _entries_T_46; // @[TLB.scala:170:77]
wire _entries_T_45; // @[TLB.scala:170:77]
wire _entries_T_44; // @[TLB.scala:170:77]
wire _entries_T_43; // @[TLB.scala:170:77]
wire _entries_T_42; // @[TLB.scala:170:77]
wire _entries_T_41; // @[TLB.scala:170:77]
wire _entries_T_40; // @[TLB.scala:170:77]
wire _entries_T_39; // @[TLB.scala:170:77]
wire _entries_T_38; // @[TLB.scala:170:77]
wire _entries_T_37; // @[TLB.scala:170:77]
wire _entries_T_36; // @[TLB.scala:170:77]
wire _entries_T_35; // @[TLB.scala:170:77]
wire _entries_T_34; // @[TLB.scala:170:77]
wire _entries_T_33; // @[TLB.scala:170:77]
wire _entries_T_32; // @[TLB.scala:170:77]
wire _entries_T_31; // @[TLB.scala:170:77]
wire _entries_T_30; // @[TLB.scala:170:77]
wire _entries_T_29; // @[TLB.scala:170:77]
wire _entries_T_28; // @[TLB.scala:170:77]
wire _entries_T_27; // @[TLB.scala:170:77]
wire _entries_T_26; // @[TLB.scala:170:77]
wire _entries_T_25; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_33 = {{sectored_entries_0_1_data_3}, {sectored_entries_0_1_data_2}, {sectored_entries_0_1_data_1}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_3 = _GEN_33[_entries_T_24]; // @[package.scala:163:13]
assign _entries_T_25 = _entries_WIRE_3[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_fragmented_superpage = _entries_T_25; // @[TLB.scala:170:77]
assign _entries_T_26 = _entries_WIRE_3[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_c = _entries_T_26; // @[TLB.scala:170:77]
assign _entries_T_27 = _entries_WIRE_3[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_eff = _entries_T_27; // @[TLB.scala:170:77]
assign _entries_T_28 = _entries_WIRE_3[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_paa = _entries_T_28; // @[TLB.scala:170:77]
assign _entries_T_29 = _entries_WIRE_3[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pal = _entries_T_29; // @[TLB.scala:170:77]
assign _entries_T_30 = _entries_WIRE_3[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ppp = _entries_T_30; // @[TLB.scala:170:77]
assign _entries_T_31 = _entries_WIRE_3[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pr = _entries_T_31; // @[TLB.scala:170:77]
assign _entries_T_32 = _entries_WIRE_3[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_px = _entries_T_32; // @[TLB.scala:170:77]
assign _entries_T_33 = _entries_WIRE_3[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pw = _entries_T_33; // @[TLB.scala:170:77]
assign _entries_T_34 = _entries_WIRE_3[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hr = _entries_T_34; // @[TLB.scala:170:77]
assign _entries_T_35 = _entries_WIRE_3[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hx = _entries_T_35; // @[TLB.scala:170:77]
assign _entries_T_36 = _entries_WIRE_3[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hw = _entries_T_36; // @[TLB.scala:170:77]
assign _entries_T_37 = _entries_WIRE_3[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sr = _entries_T_37; // @[TLB.scala:170:77]
assign _entries_T_38 = _entries_WIRE_3[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sx = _entries_T_38; // @[TLB.scala:170:77]
assign _entries_T_39 = _entries_WIRE_3[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sw = _entries_T_39; // @[TLB.scala:170:77]
assign _entries_T_40 = _entries_WIRE_3[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_gf = _entries_T_40; // @[TLB.scala:170:77]
assign _entries_T_41 = _entries_WIRE_3[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pf = _entries_T_41; // @[TLB.scala:170:77]
assign _entries_T_42 = _entries_WIRE_3[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_stage2 = _entries_T_42; // @[TLB.scala:170:77]
assign _entries_T_43 = _entries_WIRE_3[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_final = _entries_T_43; // @[TLB.scala:170:77]
assign _entries_T_44 = _entries_WIRE_3[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_ptw = _entries_T_44; // @[TLB.scala:170:77]
assign _entries_T_45 = _entries_WIRE_3[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_g = _entries_T_45; // @[TLB.scala:170:77]
assign _entries_T_46 = _entries_WIRE_3[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_u = _entries_T_46; // @[TLB.scala:170:77]
assign _entries_T_47 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_2_ppn = _entries_T_47; // @[TLB.scala:170:77]
wire [19:0] _entries_T_71; // @[TLB.scala:170:77]
wire _entries_T_70; // @[TLB.scala:170:77]
wire _entries_T_69; // @[TLB.scala:170:77]
wire _entries_T_68; // @[TLB.scala:170:77]
wire _entries_T_67; // @[TLB.scala:170:77]
wire _entries_T_66; // @[TLB.scala:170:77]
wire _entries_T_65; // @[TLB.scala:170:77]
wire _entries_T_64; // @[TLB.scala:170:77]
wire _entries_T_63; // @[TLB.scala:170:77]
wire _entries_T_62; // @[TLB.scala:170:77]
wire _entries_T_61; // @[TLB.scala:170:77]
wire _entries_T_60; // @[TLB.scala:170:77]
wire _entries_T_59; // @[TLB.scala:170:77]
wire _entries_T_58; // @[TLB.scala:170:77]
wire _entries_T_57; // @[TLB.scala:170:77]
wire _entries_T_56; // @[TLB.scala:170:77]
wire _entries_T_55; // @[TLB.scala:170:77]
wire _entries_T_54; // @[TLB.scala:170:77]
wire _entries_T_53; // @[TLB.scala:170:77]
wire _entries_T_52; // @[TLB.scala:170:77]
wire _entries_T_51; // @[TLB.scala:170:77]
wire _entries_T_50; // @[TLB.scala:170:77]
wire _entries_T_49; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_34 = {{sectored_entries_0_2_data_3}, {sectored_entries_0_2_data_2}, {sectored_entries_0_2_data_1}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_5 = _GEN_34[_entries_T_48]; // @[package.scala:163:13]
assign _entries_T_49 = _entries_WIRE_5[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_fragmented_superpage = _entries_T_49; // @[TLB.scala:170:77]
assign _entries_T_50 = _entries_WIRE_5[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_c = _entries_T_50; // @[TLB.scala:170:77]
assign _entries_T_51 = _entries_WIRE_5[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_eff = _entries_T_51; // @[TLB.scala:170:77]
assign _entries_T_52 = _entries_WIRE_5[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_paa = _entries_T_52; // @[TLB.scala:170:77]
assign _entries_T_53 = _entries_WIRE_5[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pal = _entries_T_53; // @[TLB.scala:170:77]
assign _entries_T_54 = _entries_WIRE_5[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ppp = _entries_T_54; // @[TLB.scala:170:77]
assign _entries_T_55 = _entries_WIRE_5[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pr = _entries_T_55; // @[TLB.scala:170:77]
assign _entries_T_56 = _entries_WIRE_5[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_px = _entries_T_56; // @[TLB.scala:170:77]
assign _entries_T_57 = _entries_WIRE_5[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pw = _entries_T_57; // @[TLB.scala:170:77]
assign _entries_T_58 = _entries_WIRE_5[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hr = _entries_T_58; // @[TLB.scala:170:77]
assign _entries_T_59 = _entries_WIRE_5[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hx = _entries_T_59; // @[TLB.scala:170:77]
assign _entries_T_60 = _entries_WIRE_5[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hw = _entries_T_60; // @[TLB.scala:170:77]
assign _entries_T_61 = _entries_WIRE_5[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sr = _entries_T_61; // @[TLB.scala:170:77]
assign _entries_T_62 = _entries_WIRE_5[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sx = _entries_T_62; // @[TLB.scala:170:77]
assign _entries_T_63 = _entries_WIRE_5[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sw = _entries_T_63; // @[TLB.scala:170:77]
assign _entries_T_64 = _entries_WIRE_5[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_gf = _entries_T_64; // @[TLB.scala:170:77]
assign _entries_T_65 = _entries_WIRE_5[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pf = _entries_T_65; // @[TLB.scala:170:77]
assign _entries_T_66 = _entries_WIRE_5[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_stage2 = _entries_T_66; // @[TLB.scala:170:77]
assign _entries_T_67 = _entries_WIRE_5[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_final = _entries_T_67; // @[TLB.scala:170:77]
assign _entries_T_68 = _entries_WIRE_5[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_ptw = _entries_T_68; // @[TLB.scala:170:77]
assign _entries_T_69 = _entries_WIRE_5[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_g = _entries_T_69; // @[TLB.scala:170:77]
assign _entries_T_70 = _entries_WIRE_5[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_u = _entries_T_70; // @[TLB.scala:170:77]
assign _entries_T_71 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_4_ppn = _entries_T_71; // @[TLB.scala:170:77]
wire [19:0] _entries_T_95; // @[TLB.scala:170:77]
wire _entries_T_94; // @[TLB.scala:170:77]
wire _entries_T_93; // @[TLB.scala:170:77]
wire _entries_T_92; // @[TLB.scala:170:77]
wire _entries_T_91; // @[TLB.scala:170:77]
wire _entries_T_90; // @[TLB.scala:170:77]
wire _entries_T_89; // @[TLB.scala:170:77]
wire _entries_T_88; // @[TLB.scala:170:77]
wire _entries_T_87; // @[TLB.scala:170:77]
wire _entries_T_86; // @[TLB.scala:170:77]
wire _entries_T_85; // @[TLB.scala:170:77]
wire _entries_T_84; // @[TLB.scala:170:77]
wire _entries_T_83; // @[TLB.scala:170:77]
wire _entries_T_82; // @[TLB.scala:170:77]
wire _entries_T_81; // @[TLB.scala:170:77]
wire _entries_T_80; // @[TLB.scala:170:77]
wire _entries_T_79; // @[TLB.scala:170:77]
wire _entries_T_78; // @[TLB.scala:170:77]
wire _entries_T_77; // @[TLB.scala:170:77]
wire _entries_T_76; // @[TLB.scala:170:77]
wire _entries_T_75; // @[TLB.scala:170:77]
wire _entries_T_74; // @[TLB.scala:170:77]
wire _entries_T_73; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_35 = {{sectored_entries_0_3_data_3}, {sectored_entries_0_3_data_2}, {sectored_entries_0_3_data_1}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_7 = _GEN_35[_entries_T_72]; // @[package.scala:163:13]
assign _entries_T_73 = _entries_WIRE_7[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_fragmented_superpage = _entries_T_73; // @[TLB.scala:170:77]
assign _entries_T_74 = _entries_WIRE_7[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_c = _entries_T_74; // @[TLB.scala:170:77]
assign _entries_T_75 = _entries_WIRE_7[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_eff = _entries_T_75; // @[TLB.scala:170:77]
assign _entries_T_76 = _entries_WIRE_7[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_paa = _entries_T_76; // @[TLB.scala:170:77]
assign _entries_T_77 = _entries_WIRE_7[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pal = _entries_T_77; // @[TLB.scala:170:77]
assign _entries_T_78 = _entries_WIRE_7[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ppp = _entries_T_78; // @[TLB.scala:170:77]
assign _entries_T_79 = _entries_WIRE_7[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pr = _entries_T_79; // @[TLB.scala:170:77]
assign _entries_T_80 = _entries_WIRE_7[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_px = _entries_T_80; // @[TLB.scala:170:77]
assign _entries_T_81 = _entries_WIRE_7[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pw = _entries_T_81; // @[TLB.scala:170:77]
assign _entries_T_82 = _entries_WIRE_7[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hr = _entries_T_82; // @[TLB.scala:170:77]
assign _entries_T_83 = _entries_WIRE_7[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hx = _entries_T_83; // @[TLB.scala:170:77]
assign _entries_T_84 = _entries_WIRE_7[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hw = _entries_T_84; // @[TLB.scala:170:77]
assign _entries_T_85 = _entries_WIRE_7[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sr = _entries_T_85; // @[TLB.scala:170:77]
assign _entries_T_86 = _entries_WIRE_7[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sx = _entries_T_86; // @[TLB.scala:170:77]
assign _entries_T_87 = _entries_WIRE_7[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sw = _entries_T_87; // @[TLB.scala:170:77]
assign _entries_T_88 = _entries_WIRE_7[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_gf = _entries_T_88; // @[TLB.scala:170:77]
assign _entries_T_89 = _entries_WIRE_7[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pf = _entries_T_89; // @[TLB.scala:170:77]
assign _entries_T_90 = _entries_WIRE_7[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_stage2 = _entries_T_90; // @[TLB.scala:170:77]
assign _entries_T_91 = _entries_WIRE_7[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_final = _entries_T_91; // @[TLB.scala:170:77]
assign _entries_T_92 = _entries_WIRE_7[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_ptw = _entries_T_92; // @[TLB.scala:170:77]
assign _entries_T_93 = _entries_WIRE_7[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_g = _entries_T_93; // @[TLB.scala:170:77]
assign _entries_T_94 = _entries_WIRE_7[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_u = _entries_T_94; // @[TLB.scala:170:77]
assign _entries_T_95 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_6_ppn = _entries_T_95; // @[TLB.scala:170:77]
wire [19:0] _entries_T_119; // @[TLB.scala:170:77]
wire _entries_T_118; // @[TLB.scala:170:77]
wire _entries_T_117; // @[TLB.scala:170:77]
wire _entries_T_116; // @[TLB.scala:170:77]
wire _entries_T_115; // @[TLB.scala:170:77]
wire _entries_T_114; // @[TLB.scala:170:77]
wire _entries_T_113; // @[TLB.scala:170:77]
wire _entries_T_112; // @[TLB.scala:170:77]
wire _entries_T_111; // @[TLB.scala:170:77]
wire _entries_T_110; // @[TLB.scala:170:77]
wire _entries_T_109; // @[TLB.scala:170:77]
wire _entries_T_108; // @[TLB.scala:170:77]
wire _entries_T_107; // @[TLB.scala:170:77]
wire _entries_T_106; // @[TLB.scala:170:77]
wire _entries_T_105; // @[TLB.scala:170:77]
wire _entries_T_104; // @[TLB.scala:170:77]
wire _entries_T_103; // @[TLB.scala:170:77]
wire _entries_T_102; // @[TLB.scala:170:77]
wire _entries_T_101; // @[TLB.scala:170:77]
wire _entries_T_100; // @[TLB.scala:170:77]
wire _entries_T_99; // @[TLB.scala:170:77]
wire _entries_T_98; // @[TLB.scala:170:77]
wire _entries_T_97; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_36 = {{sectored_entries_0_4_data_3}, {sectored_entries_0_4_data_2}, {sectored_entries_0_4_data_1}, {sectored_entries_0_4_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_9 = _GEN_36[_entries_T_96]; // @[package.scala:163:13]
assign _entries_T_97 = _entries_WIRE_9[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_fragmented_superpage = _entries_T_97; // @[TLB.scala:170:77]
assign _entries_T_98 = _entries_WIRE_9[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_c = _entries_T_98; // @[TLB.scala:170:77]
assign _entries_T_99 = _entries_WIRE_9[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_eff = _entries_T_99; // @[TLB.scala:170:77]
assign _entries_T_100 = _entries_WIRE_9[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_paa = _entries_T_100; // @[TLB.scala:170:77]
assign _entries_T_101 = _entries_WIRE_9[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pal = _entries_T_101; // @[TLB.scala:170:77]
assign _entries_T_102 = _entries_WIRE_9[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ppp = _entries_T_102; // @[TLB.scala:170:77]
assign _entries_T_103 = _entries_WIRE_9[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pr = _entries_T_103; // @[TLB.scala:170:77]
assign _entries_T_104 = _entries_WIRE_9[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_px = _entries_T_104; // @[TLB.scala:170:77]
assign _entries_T_105 = _entries_WIRE_9[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pw = _entries_T_105; // @[TLB.scala:170:77]
assign _entries_T_106 = _entries_WIRE_9[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hr = _entries_T_106; // @[TLB.scala:170:77]
assign _entries_T_107 = _entries_WIRE_9[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hx = _entries_T_107; // @[TLB.scala:170:77]
assign _entries_T_108 = _entries_WIRE_9[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hw = _entries_T_108; // @[TLB.scala:170:77]
assign _entries_T_109 = _entries_WIRE_9[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sr = _entries_T_109; // @[TLB.scala:170:77]
assign _entries_T_110 = _entries_WIRE_9[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sx = _entries_T_110; // @[TLB.scala:170:77]
assign _entries_T_111 = _entries_WIRE_9[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sw = _entries_T_111; // @[TLB.scala:170:77]
assign _entries_T_112 = _entries_WIRE_9[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_gf = _entries_T_112; // @[TLB.scala:170:77]
assign _entries_T_113 = _entries_WIRE_9[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pf = _entries_T_113; // @[TLB.scala:170:77]
assign _entries_T_114 = _entries_WIRE_9[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_stage2 = _entries_T_114; // @[TLB.scala:170:77]
assign _entries_T_115 = _entries_WIRE_9[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_final = _entries_T_115; // @[TLB.scala:170:77]
assign _entries_T_116 = _entries_WIRE_9[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_ptw = _entries_T_116; // @[TLB.scala:170:77]
assign _entries_T_117 = _entries_WIRE_9[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_g = _entries_T_117; // @[TLB.scala:170:77]
assign _entries_T_118 = _entries_WIRE_9[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_u = _entries_T_118; // @[TLB.scala:170:77]
assign _entries_T_119 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_8_ppn = _entries_T_119; // @[TLB.scala:170:77]
wire [19:0] _entries_T_143; // @[TLB.scala:170:77]
wire _entries_T_142; // @[TLB.scala:170:77]
wire _entries_T_141; // @[TLB.scala:170:77]
wire _entries_T_140; // @[TLB.scala:170:77]
wire _entries_T_139; // @[TLB.scala:170:77]
wire _entries_T_138; // @[TLB.scala:170:77]
wire _entries_T_137; // @[TLB.scala:170:77]
wire _entries_T_136; // @[TLB.scala:170:77]
wire _entries_T_135; // @[TLB.scala:170:77]
wire _entries_T_134; // @[TLB.scala:170:77]
wire _entries_T_133; // @[TLB.scala:170:77]
wire _entries_T_132; // @[TLB.scala:170:77]
wire _entries_T_131; // @[TLB.scala:170:77]
wire _entries_T_130; // @[TLB.scala:170:77]
wire _entries_T_129; // @[TLB.scala:170:77]
wire _entries_T_128; // @[TLB.scala:170:77]
wire _entries_T_127; // @[TLB.scala:170:77]
wire _entries_T_126; // @[TLB.scala:170:77]
wire _entries_T_125; // @[TLB.scala:170:77]
wire _entries_T_124; // @[TLB.scala:170:77]
wire _entries_T_123; // @[TLB.scala:170:77]
wire _entries_T_122; // @[TLB.scala:170:77]
wire _entries_T_121; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_37 = {{sectored_entries_0_5_data_3}, {sectored_entries_0_5_data_2}, {sectored_entries_0_5_data_1}, {sectored_entries_0_5_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_11 = _GEN_37[_entries_T_120]; // @[package.scala:163:13]
assign _entries_T_121 = _entries_WIRE_11[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_fragmented_superpage = _entries_T_121; // @[TLB.scala:170:77]
assign _entries_T_122 = _entries_WIRE_11[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_c = _entries_T_122; // @[TLB.scala:170:77]
assign _entries_T_123 = _entries_WIRE_11[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_eff = _entries_T_123; // @[TLB.scala:170:77]
assign _entries_T_124 = _entries_WIRE_11[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_paa = _entries_T_124; // @[TLB.scala:170:77]
assign _entries_T_125 = _entries_WIRE_11[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pal = _entries_T_125; // @[TLB.scala:170:77]
assign _entries_T_126 = _entries_WIRE_11[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ppp = _entries_T_126; // @[TLB.scala:170:77]
assign _entries_T_127 = _entries_WIRE_11[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pr = _entries_T_127; // @[TLB.scala:170:77]
assign _entries_T_128 = _entries_WIRE_11[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_px = _entries_T_128; // @[TLB.scala:170:77]
assign _entries_T_129 = _entries_WIRE_11[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pw = _entries_T_129; // @[TLB.scala:170:77]
assign _entries_T_130 = _entries_WIRE_11[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hr = _entries_T_130; // @[TLB.scala:170:77]
assign _entries_T_131 = _entries_WIRE_11[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hx = _entries_T_131; // @[TLB.scala:170:77]
assign _entries_T_132 = _entries_WIRE_11[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hw = _entries_T_132; // @[TLB.scala:170:77]
assign _entries_T_133 = _entries_WIRE_11[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sr = _entries_T_133; // @[TLB.scala:170:77]
assign _entries_T_134 = _entries_WIRE_11[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sx = _entries_T_134; // @[TLB.scala:170:77]
assign _entries_T_135 = _entries_WIRE_11[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sw = _entries_T_135; // @[TLB.scala:170:77]
assign _entries_T_136 = _entries_WIRE_11[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_gf = _entries_T_136; // @[TLB.scala:170:77]
assign _entries_T_137 = _entries_WIRE_11[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pf = _entries_T_137; // @[TLB.scala:170:77]
assign _entries_T_138 = _entries_WIRE_11[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_stage2 = _entries_T_138; // @[TLB.scala:170:77]
assign _entries_T_139 = _entries_WIRE_11[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_final = _entries_T_139; // @[TLB.scala:170:77]
assign _entries_T_140 = _entries_WIRE_11[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_ptw = _entries_T_140; // @[TLB.scala:170:77]
assign _entries_T_141 = _entries_WIRE_11[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_g = _entries_T_141; // @[TLB.scala:170:77]
assign _entries_T_142 = _entries_WIRE_11[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_u = _entries_T_142; // @[TLB.scala:170:77]
assign _entries_T_143 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_10_ppn = _entries_T_143; // @[TLB.scala:170:77]
wire [19:0] _entries_T_167; // @[TLB.scala:170:77]
wire _entries_T_166; // @[TLB.scala:170:77]
wire _entries_T_165; // @[TLB.scala:170:77]
wire _entries_T_164; // @[TLB.scala:170:77]
wire _entries_T_163; // @[TLB.scala:170:77]
wire _entries_T_162; // @[TLB.scala:170:77]
wire _entries_T_161; // @[TLB.scala:170:77]
wire _entries_T_160; // @[TLB.scala:170:77]
wire _entries_T_159; // @[TLB.scala:170:77]
wire _entries_T_158; // @[TLB.scala:170:77]
wire _entries_T_157; // @[TLB.scala:170:77]
wire _entries_T_156; // @[TLB.scala:170:77]
wire _entries_T_155; // @[TLB.scala:170:77]
wire _entries_T_154; // @[TLB.scala:170:77]
wire _entries_T_153; // @[TLB.scala:170:77]
wire _entries_T_152; // @[TLB.scala:170:77]
wire _entries_T_151; // @[TLB.scala:170:77]
wire _entries_T_150; // @[TLB.scala:170:77]
wire _entries_T_149; // @[TLB.scala:170:77]
wire _entries_T_148; // @[TLB.scala:170:77]
wire _entries_T_147; // @[TLB.scala:170:77]
wire _entries_T_146; // @[TLB.scala:170:77]
wire _entries_T_145; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_38 = {{sectored_entries_0_6_data_3}, {sectored_entries_0_6_data_2}, {sectored_entries_0_6_data_1}, {sectored_entries_0_6_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_13 = _GEN_38[_entries_T_144]; // @[package.scala:163:13]
assign _entries_T_145 = _entries_WIRE_13[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_fragmented_superpage = _entries_T_145; // @[TLB.scala:170:77]
assign _entries_T_146 = _entries_WIRE_13[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_c = _entries_T_146; // @[TLB.scala:170:77]
assign _entries_T_147 = _entries_WIRE_13[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_eff = _entries_T_147; // @[TLB.scala:170:77]
assign _entries_T_148 = _entries_WIRE_13[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_paa = _entries_T_148; // @[TLB.scala:170:77]
assign _entries_T_149 = _entries_WIRE_13[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pal = _entries_T_149; // @[TLB.scala:170:77]
assign _entries_T_150 = _entries_WIRE_13[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ppp = _entries_T_150; // @[TLB.scala:170:77]
assign _entries_T_151 = _entries_WIRE_13[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pr = _entries_T_151; // @[TLB.scala:170:77]
assign _entries_T_152 = _entries_WIRE_13[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_px = _entries_T_152; // @[TLB.scala:170:77]
assign _entries_T_153 = _entries_WIRE_13[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pw = _entries_T_153; // @[TLB.scala:170:77]
assign _entries_T_154 = _entries_WIRE_13[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_hr = _entries_T_154; // @[TLB.scala:170:77]
assign _entries_T_155 = _entries_WIRE_13[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_hx = _entries_T_155; // @[TLB.scala:170:77]
assign _entries_T_156 = _entries_WIRE_13[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_hw = _entries_T_156; // @[TLB.scala:170:77]
assign _entries_T_157 = _entries_WIRE_13[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_sr = _entries_T_157; // @[TLB.scala:170:77]
assign _entries_T_158 = _entries_WIRE_13[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_sx = _entries_T_158; // @[TLB.scala:170:77]
assign _entries_T_159 = _entries_WIRE_13[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_sw = _entries_T_159; // @[TLB.scala:170:77]
assign _entries_T_160 = _entries_WIRE_13[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_gf = _entries_T_160; // @[TLB.scala:170:77]
assign _entries_T_161 = _entries_WIRE_13[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pf = _entries_T_161; // @[TLB.scala:170:77]
assign _entries_T_162 = _entries_WIRE_13[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ae_stage2 = _entries_T_162; // @[TLB.scala:170:77]
assign _entries_T_163 = _entries_WIRE_13[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ae_final = _entries_T_163; // @[TLB.scala:170:77]
assign _entries_T_164 = _entries_WIRE_13[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ae_ptw = _entries_T_164; // @[TLB.scala:170:77]
assign _entries_T_165 = _entries_WIRE_13[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_g = _entries_T_165; // @[TLB.scala:170:77]
assign _entries_T_166 = _entries_WIRE_13[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_u = _entries_T_166; // @[TLB.scala:170:77]
assign _entries_T_167 = _entries_WIRE_13[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_12_ppn = _entries_T_167; // @[TLB.scala:170:77]
wire [19:0] _entries_T_191; // @[TLB.scala:170:77]
wire _entries_T_190; // @[TLB.scala:170:77]
wire _entries_T_189; // @[TLB.scala:170:77]
wire _entries_T_188; // @[TLB.scala:170:77]
wire _entries_T_187; // @[TLB.scala:170:77]
wire _entries_T_186; // @[TLB.scala:170:77]
wire _entries_T_185; // @[TLB.scala:170:77]
wire _entries_T_184; // @[TLB.scala:170:77]
wire _entries_T_183; // @[TLB.scala:170:77]
wire _entries_T_182; // @[TLB.scala:170:77]
wire _entries_T_181; // @[TLB.scala:170:77]
wire _entries_T_180; // @[TLB.scala:170:77]
wire _entries_T_179; // @[TLB.scala:170:77]
wire _entries_T_178; // @[TLB.scala:170:77]
wire _entries_T_177; // @[TLB.scala:170:77]
wire _entries_T_176; // @[TLB.scala:170:77]
wire _entries_T_175; // @[TLB.scala:170:77]
wire _entries_T_174; // @[TLB.scala:170:77]
wire _entries_T_173; // @[TLB.scala:170:77]
wire _entries_T_172; // @[TLB.scala:170:77]
wire _entries_T_171; // @[TLB.scala:170:77]
wire _entries_T_170; // @[TLB.scala:170:77]
wire _entries_T_169; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_39 = {{sectored_entries_0_7_data_3}, {sectored_entries_0_7_data_2}, {sectored_entries_0_7_data_1}, {sectored_entries_0_7_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_15 = _GEN_39[_entries_T_168]; // @[package.scala:163:13]
assign _entries_T_169 = _entries_WIRE_15[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_fragmented_superpage = _entries_T_169; // @[TLB.scala:170:77]
assign _entries_T_170 = _entries_WIRE_15[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_c = _entries_T_170; // @[TLB.scala:170:77]
assign _entries_T_171 = _entries_WIRE_15[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_eff = _entries_T_171; // @[TLB.scala:170:77]
assign _entries_T_172 = _entries_WIRE_15[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_paa = _entries_T_172; // @[TLB.scala:170:77]
assign _entries_T_173 = _entries_WIRE_15[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pal = _entries_T_173; // @[TLB.scala:170:77]
assign _entries_T_174 = _entries_WIRE_15[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ppp = _entries_T_174; // @[TLB.scala:170:77]
assign _entries_T_175 = _entries_WIRE_15[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pr = _entries_T_175; // @[TLB.scala:170:77]
assign _entries_T_176 = _entries_WIRE_15[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_px = _entries_T_176; // @[TLB.scala:170:77]
assign _entries_T_177 = _entries_WIRE_15[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pw = _entries_T_177; // @[TLB.scala:170:77]
assign _entries_T_178 = _entries_WIRE_15[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_hr = _entries_T_178; // @[TLB.scala:170:77]
assign _entries_T_179 = _entries_WIRE_15[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_hx = _entries_T_179; // @[TLB.scala:170:77]
assign _entries_T_180 = _entries_WIRE_15[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_hw = _entries_T_180; // @[TLB.scala:170:77]
assign _entries_T_181 = _entries_WIRE_15[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_sr = _entries_T_181; // @[TLB.scala:170:77]
assign _entries_T_182 = _entries_WIRE_15[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_sx = _entries_T_182; // @[TLB.scala:170:77]
assign _entries_T_183 = _entries_WIRE_15[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_sw = _entries_T_183; // @[TLB.scala:170:77]
assign _entries_T_184 = _entries_WIRE_15[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_gf = _entries_T_184; // @[TLB.scala:170:77]
assign _entries_T_185 = _entries_WIRE_15[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pf = _entries_T_185; // @[TLB.scala:170:77]
assign _entries_T_186 = _entries_WIRE_15[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ae_stage2 = _entries_T_186; // @[TLB.scala:170:77]
assign _entries_T_187 = _entries_WIRE_15[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ae_final = _entries_T_187; // @[TLB.scala:170:77]
assign _entries_T_188 = _entries_WIRE_15[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ae_ptw = _entries_T_188; // @[TLB.scala:170:77]
assign _entries_T_189 = _entries_WIRE_15[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_g = _entries_T_189; // @[TLB.scala:170:77]
assign _entries_T_190 = _entries_WIRE_15[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_u = _entries_T_190; // @[TLB.scala:170:77]
assign _entries_T_191 = _entries_WIRE_15[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_14_ppn = _entries_T_191; // @[TLB.scala:170:77]
wire [19:0] _entries_T_214; // @[TLB.scala:170:77]
wire _entries_T_213; // @[TLB.scala:170:77]
wire _entries_T_212; // @[TLB.scala:170:77]
wire _entries_T_211; // @[TLB.scala:170:77]
wire _entries_T_210; // @[TLB.scala:170:77]
wire _entries_T_209; // @[TLB.scala:170:77]
wire _entries_T_208; // @[TLB.scala:170:77]
wire _entries_T_207; // @[TLB.scala:170:77]
wire _entries_T_206; // @[TLB.scala:170:77]
wire _entries_T_205; // @[TLB.scala:170:77]
wire _entries_T_204; // @[TLB.scala:170:77]
wire _entries_T_203; // @[TLB.scala:170:77]
wire _entries_T_202; // @[TLB.scala:170:77]
wire _entries_T_201; // @[TLB.scala:170:77]
wire _entries_T_200; // @[TLB.scala:170:77]
wire _entries_T_199; // @[TLB.scala:170:77]
wire _entries_T_198; // @[TLB.scala:170:77]
wire _entries_T_197; // @[TLB.scala:170:77]
wire _entries_T_196; // @[TLB.scala:170:77]
wire _entries_T_195; // @[TLB.scala:170:77]
wire _entries_T_194; // @[TLB.scala:170:77]
wire _entries_T_193; // @[TLB.scala:170:77]
wire _entries_T_192; // @[TLB.scala:170:77]
assign _entries_T_192 = _entries_WIRE_17[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_fragmented_superpage = _entries_T_192; // @[TLB.scala:170:77]
assign _entries_T_193 = _entries_WIRE_17[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_c = _entries_T_193; // @[TLB.scala:170:77]
assign _entries_T_194 = _entries_WIRE_17[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_eff = _entries_T_194; // @[TLB.scala:170:77]
assign _entries_T_195 = _entries_WIRE_17[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_paa = _entries_T_195; // @[TLB.scala:170:77]
assign _entries_T_196 = _entries_WIRE_17[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pal = _entries_T_196; // @[TLB.scala:170:77]
assign _entries_T_197 = _entries_WIRE_17[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ppp = _entries_T_197; // @[TLB.scala:170:77]
assign _entries_T_198 = _entries_WIRE_17[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pr = _entries_T_198; // @[TLB.scala:170:77]
assign _entries_T_199 = _entries_WIRE_17[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_px = _entries_T_199; // @[TLB.scala:170:77]
assign _entries_T_200 = _entries_WIRE_17[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pw = _entries_T_200; // @[TLB.scala:170:77]
assign _entries_T_201 = _entries_WIRE_17[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_hr = _entries_T_201; // @[TLB.scala:170:77]
assign _entries_T_202 = _entries_WIRE_17[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_hx = _entries_T_202; // @[TLB.scala:170:77]
assign _entries_T_203 = _entries_WIRE_17[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_hw = _entries_T_203; // @[TLB.scala:170:77]
assign _entries_T_204 = _entries_WIRE_17[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_sr = _entries_T_204; // @[TLB.scala:170:77]
assign _entries_T_205 = _entries_WIRE_17[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_sx = _entries_T_205; // @[TLB.scala:170:77]
assign _entries_T_206 = _entries_WIRE_17[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_sw = _entries_T_206; // @[TLB.scala:170:77]
assign _entries_T_207 = _entries_WIRE_17[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_gf = _entries_T_207; // @[TLB.scala:170:77]
assign _entries_T_208 = _entries_WIRE_17[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pf = _entries_T_208; // @[TLB.scala:170:77]
assign _entries_T_209 = _entries_WIRE_17[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ae_stage2 = _entries_T_209; // @[TLB.scala:170:77]
assign _entries_T_210 = _entries_WIRE_17[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ae_final = _entries_T_210; // @[TLB.scala:170:77]
assign _entries_T_211 = _entries_WIRE_17[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ae_ptw = _entries_T_211; // @[TLB.scala:170:77]
assign _entries_T_212 = _entries_WIRE_17[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_g = _entries_T_212; // @[TLB.scala:170:77]
assign _entries_T_213 = _entries_WIRE_17[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_u = _entries_T_213; // @[TLB.scala:170:77]
assign _entries_T_214 = _entries_WIRE_17[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_16_ppn = _entries_T_214; // @[TLB.scala:170:77]
wire [19:0] _entries_T_237; // @[TLB.scala:170:77]
wire _entries_T_236; // @[TLB.scala:170:77]
wire _entries_T_235; // @[TLB.scala:170:77]
wire _entries_T_234; // @[TLB.scala:170:77]
wire _entries_T_233; // @[TLB.scala:170:77]
wire _entries_T_232; // @[TLB.scala:170:77]
wire _entries_T_231; // @[TLB.scala:170:77]
wire _entries_T_230; // @[TLB.scala:170:77]
wire _entries_T_229; // @[TLB.scala:170:77]
wire _entries_T_228; // @[TLB.scala:170:77]
wire _entries_T_227; // @[TLB.scala:170:77]
wire _entries_T_226; // @[TLB.scala:170:77]
wire _entries_T_225; // @[TLB.scala:170:77]
wire _entries_T_224; // @[TLB.scala:170:77]
wire _entries_T_223; // @[TLB.scala:170:77]
wire _entries_T_222; // @[TLB.scala:170:77]
wire _entries_T_221; // @[TLB.scala:170:77]
wire _entries_T_220; // @[TLB.scala:170:77]
wire _entries_T_219; // @[TLB.scala:170:77]
wire _entries_T_218; // @[TLB.scala:170:77]
wire _entries_T_217; // @[TLB.scala:170:77]
wire _entries_T_216; // @[TLB.scala:170:77]
wire _entries_T_215; // @[TLB.scala:170:77]
assign _entries_T_215 = _entries_WIRE_19[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_fragmented_superpage = _entries_T_215; // @[TLB.scala:170:77]
assign _entries_T_216 = _entries_WIRE_19[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_c = _entries_T_216; // @[TLB.scala:170:77]
assign _entries_T_217 = _entries_WIRE_19[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_eff = _entries_T_217; // @[TLB.scala:170:77]
assign _entries_T_218 = _entries_WIRE_19[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_paa = _entries_T_218; // @[TLB.scala:170:77]
assign _entries_T_219 = _entries_WIRE_19[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pal = _entries_T_219; // @[TLB.scala:170:77]
assign _entries_T_220 = _entries_WIRE_19[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ppp = _entries_T_220; // @[TLB.scala:170:77]
assign _entries_T_221 = _entries_WIRE_19[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pr = _entries_T_221; // @[TLB.scala:170:77]
assign _entries_T_222 = _entries_WIRE_19[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_px = _entries_T_222; // @[TLB.scala:170:77]
assign _entries_T_223 = _entries_WIRE_19[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pw = _entries_T_223; // @[TLB.scala:170:77]
assign _entries_T_224 = _entries_WIRE_19[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_hr = _entries_T_224; // @[TLB.scala:170:77]
assign _entries_T_225 = _entries_WIRE_19[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_hx = _entries_T_225; // @[TLB.scala:170:77]
assign _entries_T_226 = _entries_WIRE_19[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_hw = _entries_T_226; // @[TLB.scala:170:77]
assign _entries_T_227 = _entries_WIRE_19[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_sr = _entries_T_227; // @[TLB.scala:170:77]
assign _entries_T_228 = _entries_WIRE_19[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_sx = _entries_T_228; // @[TLB.scala:170:77]
assign _entries_T_229 = _entries_WIRE_19[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_sw = _entries_T_229; // @[TLB.scala:170:77]
assign _entries_T_230 = _entries_WIRE_19[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_gf = _entries_T_230; // @[TLB.scala:170:77]
assign _entries_T_231 = _entries_WIRE_19[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pf = _entries_T_231; // @[TLB.scala:170:77]
assign _entries_T_232 = _entries_WIRE_19[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ae_stage2 = _entries_T_232; // @[TLB.scala:170:77]
assign _entries_T_233 = _entries_WIRE_19[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ae_final = _entries_T_233; // @[TLB.scala:170:77]
assign _entries_T_234 = _entries_WIRE_19[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ae_ptw = _entries_T_234; // @[TLB.scala:170:77]
assign _entries_T_235 = _entries_WIRE_19[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_g = _entries_T_235; // @[TLB.scala:170:77]
assign _entries_T_236 = _entries_WIRE_19[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_u = _entries_T_236; // @[TLB.scala:170:77]
assign _entries_T_237 = _entries_WIRE_19[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_18_ppn = _entries_T_237; // @[TLB.scala:170:77]
wire [19:0] _entries_T_260; // @[TLB.scala:170:77]
wire _entries_T_259; // @[TLB.scala:170:77]
wire _entries_T_258; // @[TLB.scala:170:77]
wire _entries_T_257; // @[TLB.scala:170:77]
wire _entries_T_256; // @[TLB.scala:170:77]
wire _entries_T_255; // @[TLB.scala:170:77]
wire _entries_T_254; // @[TLB.scala:170:77]
wire _entries_T_253; // @[TLB.scala:170:77]
wire _entries_T_252; // @[TLB.scala:170:77]
wire _entries_T_251; // @[TLB.scala:170:77]
wire _entries_T_250; // @[TLB.scala:170:77]
wire _entries_T_249; // @[TLB.scala:170:77]
wire _entries_T_248; // @[TLB.scala:170:77]
wire _entries_T_247; // @[TLB.scala:170:77]
wire _entries_T_246; // @[TLB.scala:170:77]
wire _entries_T_245; // @[TLB.scala:170:77]
wire _entries_T_244; // @[TLB.scala:170:77]
wire _entries_T_243; // @[TLB.scala:170:77]
wire _entries_T_242; // @[TLB.scala:170:77]
wire _entries_T_241; // @[TLB.scala:170:77]
wire _entries_T_240; // @[TLB.scala:170:77]
wire _entries_T_239; // @[TLB.scala:170:77]
wire _entries_T_238; // @[TLB.scala:170:77]
assign _entries_T_238 = _entries_WIRE_21[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_fragmented_superpage = _entries_T_238; // @[TLB.scala:170:77]
assign _entries_T_239 = _entries_WIRE_21[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_c = _entries_T_239; // @[TLB.scala:170:77]
assign _entries_T_240 = _entries_WIRE_21[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_eff = _entries_T_240; // @[TLB.scala:170:77]
assign _entries_T_241 = _entries_WIRE_21[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_paa = _entries_T_241; // @[TLB.scala:170:77]
assign _entries_T_242 = _entries_WIRE_21[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pal = _entries_T_242; // @[TLB.scala:170:77]
assign _entries_T_243 = _entries_WIRE_21[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ppp = _entries_T_243; // @[TLB.scala:170:77]
assign _entries_T_244 = _entries_WIRE_21[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pr = _entries_T_244; // @[TLB.scala:170:77]
assign _entries_T_245 = _entries_WIRE_21[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_px = _entries_T_245; // @[TLB.scala:170:77]
assign _entries_T_246 = _entries_WIRE_21[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pw = _entries_T_246; // @[TLB.scala:170:77]
assign _entries_T_247 = _entries_WIRE_21[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_hr = _entries_T_247; // @[TLB.scala:170:77]
assign _entries_T_248 = _entries_WIRE_21[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_hx = _entries_T_248; // @[TLB.scala:170:77]
assign _entries_T_249 = _entries_WIRE_21[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_hw = _entries_T_249; // @[TLB.scala:170:77]
assign _entries_T_250 = _entries_WIRE_21[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_sr = _entries_T_250; // @[TLB.scala:170:77]
assign _entries_T_251 = _entries_WIRE_21[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_sx = _entries_T_251; // @[TLB.scala:170:77]
assign _entries_T_252 = _entries_WIRE_21[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_sw = _entries_T_252; // @[TLB.scala:170:77]
assign _entries_T_253 = _entries_WIRE_21[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_gf = _entries_T_253; // @[TLB.scala:170:77]
assign _entries_T_254 = _entries_WIRE_21[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pf = _entries_T_254; // @[TLB.scala:170:77]
assign _entries_T_255 = _entries_WIRE_21[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ae_stage2 = _entries_T_255; // @[TLB.scala:170:77]
assign _entries_T_256 = _entries_WIRE_21[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ae_final = _entries_T_256; // @[TLB.scala:170:77]
assign _entries_T_257 = _entries_WIRE_21[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ae_ptw = _entries_T_257; // @[TLB.scala:170:77]
assign _entries_T_258 = _entries_WIRE_21[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_g = _entries_T_258; // @[TLB.scala:170:77]
assign _entries_T_259 = _entries_WIRE_21[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_u = _entries_T_259; // @[TLB.scala:170:77]
assign _entries_T_260 = _entries_WIRE_21[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_20_ppn = _entries_T_260; // @[TLB.scala:170:77]
wire [19:0] _entries_T_283; // @[TLB.scala:170:77]
wire _entries_T_282; // @[TLB.scala:170:77]
wire _entries_T_281; // @[TLB.scala:170:77]
wire _entries_T_280; // @[TLB.scala:170:77]
wire _entries_T_279; // @[TLB.scala:170:77]
wire _entries_T_278; // @[TLB.scala:170:77]
wire _entries_T_277; // @[TLB.scala:170:77]
wire _entries_T_276; // @[TLB.scala:170:77]
wire _entries_T_275; // @[TLB.scala:170:77]
wire _entries_T_274; // @[TLB.scala:170:77]
wire _entries_T_273; // @[TLB.scala:170:77]
wire _entries_T_272; // @[TLB.scala:170:77]
wire _entries_T_271; // @[TLB.scala:170:77]
wire _entries_T_270; // @[TLB.scala:170:77]
wire _entries_T_269; // @[TLB.scala:170:77]
wire _entries_T_268; // @[TLB.scala:170:77]
wire _entries_T_267; // @[TLB.scala:170:77]
wire _entries_T_266; // @[TLB.scala:170:77]
wire _entries_T_265; // @[TLB.scala:170:77]
wire _entries_T_264; // @[TLB.scala:170:77]
wire _entries_T_263; // @[TLB.scala:170:77]
wire _entries_T_262; // @[TLB.scala:170:77]
wire _entries_T_261; // @[TLB.scala:170:77]
assign _entries_T_261 = _entries_WIRE_23[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_fragmented_superpage = _entries_T_261; // @[TLB.scala:170:77]
assign _entries_T_262 = _entries_WIRE_23[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_c = _entries_T_262; // @[TLB.scala:170:77]
assign _entries_T_263 = _entries_WIRE_23[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_eff = _entries_T_263; // @[TLB.scala:170:77]
assign _entries_T_264 = _entries_WIRE_23[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_paa = _entries_T_264; // @[TLB.scala:170:77]
assign _entries_T_265 = _entries_WIRE_23[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pal = _entries_T_265; // @[TLB.scala:170:77]
assign _entries_T_266 = _entries_WIRE_23[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ppp = _entries_T_266; // @[TLB.scala:170:77]
assign _entries_T_267 = _entries_WIRE_23[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pr = _entries_T_267; // @[TLB.scala:170:77]
assign _entries_T_268 = _entries_WIRE_23[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_px = _entries_T_268; // @[TLB.scala:170:77]
assign _entries_T_269 = _entries_WIRE_23[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pw = _entries_T_269; // @[TLB.scala:170:77]
assign _entries_T_270 = _entries_WIRE_23[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_hr = _entries_T_270; // @[TLB.scala:170:77]
assign _entries_T_271 = _entries_WIRE_23[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_hx = _entries_T_271; // @[TLB.scala:170:77]
assign _entries_T_272 = _entries_WIRE_23[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_hw = _entries_T_272; // @[TLB.scala:170:77]
assign _entries_T_273 = _entries_WIRE_23[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_sr = _entries_T_273; // @[TLB.scala:170:77]
assign _entries_T_274 = _entries_WIRE_23[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_sx = _entries_T_274; // @[TLB.scala:170:77]
assign _entries_T_275 = _entries_WIRE_23[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_sw = _entries_T_275; // @[TLB.scala:170:77]
assign _entries_T_276 = _entries_WIRE_23[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_gf = _entries_T_276; // @[TLB.scala:170:77]
assign _entries_T_277 = _entries_WIRE_23[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pf = _entries_T_277; // @[TLB.scala:170:77]
assign _entries_T_278 = _entries_WIRE_23[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ae_stage2 = _entries_T_278; // @[TLB.scala:170:77]
assign _entries_T_279 = _entries_WIRE_23[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ae_final = _entries_T_279; // @[TLB.scala:170:77]
assign _entries_T_280 = _entries_WIRE_23[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ae_ptw = _entries_T_280; // @[TLB.scala:170:77]
assign _entries_T_281 = _entries_WIRE_23[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_g = _entries_T_281; // @[TLB.scala:170:77]
assign _entries_T_282 = _entries_WIRE_23[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_u = _entries_T_282; // @[TLB.scala:170:77]
assign _entries_T_283 = _entries_WIRE_23[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_22_ppn = _entries_T_283; // @[TLB.scala:170:77]
wire [19:0] _entries_T_306; // @[TLB.scala:170:77]
wire _entries_T_305; // @[TLB.scala:170:77]
wire _entries_T_304; // @[TLB.scala:170:77]
wire _entries_T_303; // @[TLB.scala:170:77]
wire _entries_T_302; // @[TLB.scala:170:77]
wire _entries_T_301; // @[TLB.scala:170:77]
wire _entries_T_300; // @[TLB.scala:170:77]
wire _entries_T_299; // @[TLB.scala:170:77]
wire _entries_T_298; // @[TLB.scala:170:77]
wire _entries_T_297; // @[TLB.scala:170:77]
wire _entries_T_296; // @[TLB.scala:170:77]
wire _entries_T_295; // @[TLB.scala:170:77]
wire _entries_T_294; // @[TLB.scala:170:77]
wire _entries_T_293; // @[TLB.scala:170:77]
wire _entries_T_292; // @[TLB.scala:170:77]
wire _entries_T_291; // @[TLB.scala:170:77]
wire _entries_T_290; // @[TLB.scala:170:77]
wire _entries_T_289; // @[TLB.scala:170:77]
wire _entries_T_288; // @[TLB.scala:170:77]
wire _entries_T_287; // @[TLB.scala:170:77]
wire _entries_T_286; // @[TLB.scala:170:77]
wire _entries_T_285; // @[TLB.scala:170:77]
wire _entries_T_284; // @[TLB.scala:170:77]
assign _entries_T_284 = _entries_WIRE_25[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_fragmented_superpage = _entries_T_284; // @[TLB.scala:170:77]
assign _entries_T_285 = _entries_WIRE_25[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_c = _entries_T_285; // @[TLB.scala:170:77]
assign _entries_T_286 = _entries_WIRE_25[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_eff = _entries_T_286; // @[TLB.scala:170:77]
assign _entries_T_287 = _entries_WIRE_25[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_paa = _entries_T_287; // @[TLB.scala:170:77]
assign _entries_T_288 = _entries_WIRE_25[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pal = _entries_T_288; // @[TLB.scala:170:77]
assign _entries_T_289 = _entries_WIRE_25[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ppp = _entries_T_289; // @[TLB.scala:170:77]
assign _entries_T_290 = _entries_WIRE_25[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pr = _entries_T_290; // @[TLB.scala:170:77]
assign _entries_T_291 = _entries_WIRE_25[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_px = _entries_T_291; // @[TLB.scala:170:77]
assign _entries_T_292 = _entries_WIRE_25[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pw = _entries_T_292; // @[TLB.scala:170:77]
assign _entries_T_293 = _entries_WIRE_25[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_hr = _entries_T_293; // @[TLB.scala:170:77]
assign _entries_T_294 = _entries_WIRE_25[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_hx = _entries_T_294; // @[TLB.scala:170:77]
assign _entries_T_295 = _entries_WIRE_25[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_hw = _entries_T_295; // @[TLB.scala:170:77]
assign _entries_T_296 = _entries_WIRE_25[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_sr = _entries_T_296; // @[TLB.scala:170:77]
assign _entries_T_297 = _entries_WIRE_25[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_sx = _entries_T_297; // @[TLB.scala:170:77]
assign _entries_T_298 = _entries_WIRE_25[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_sw = _entries_T_298; // @[TLB.scala:170:77]
assign _entries_T_299 = _entries_WIRE_25[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_gf = _entries_T_299; // @[TLB.scala:170:77]
assign _entries_T_300 = _entries_WIRE_25[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pf = _entries_T_300; // @[TLB.scala:170:77]
assign _entries_T_301 = _entries_WIRE_25[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ae_stage2 = _entries_T_301; // @[TLB.scala:170:77]
assign _entries_T_302 = _entries_WIRE_25[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ae_final = _entries_T_302; // @[TLB.scala:170:77]
assign _entries_T_303 = _entries_WIRE_25[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ae_ptw = _entries_T_303; // @[TLB.scala:170:77]
assign _entries_T_304 = _entries_WIRE_25[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_g = _entries_T_304; // @[TLB.scala:170:77]
assign _entries_T_305 = _entries_WIRE_25[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_u = _entries_T_305; // @[TLB.scala:170:77]
assign _entries_T_306 = _entries_WIRE_25[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_24_ppn = _entries_T_306; // @[TLB.scala:170:77]
wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30]
wire [1:0] ppn_res = _entries_barrier_8_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] | _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30]
wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] | _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}]
wire [1:0] ppn_res_1 = _entries_barrier_9_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] | _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_3 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :197:28, :341:30]
wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] | _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}]
wire [1:0] ppn_res_2 = _entries_barrier_10_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore_4 = _ppn_ignore_T_4; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_17 = ppn_ignore_4 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_18 = {_ppn_T_17[26:20], _ppn_T_17[19:0] | _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_19 = _ppn_T_18[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_20 = {ppn_res_2, _ppn_T_19}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_5 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :197:28, :341:30]
wire [26:0] _ppn_T_22 = {_ppn_T_21[26:20], _ppn_T_21[19:0] | _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_23 = _ppn_T_22[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_24 = {_ppn_T_20, _ppn_T_23}; // @[TLB.scala:198:{18,58}]
wire [1:0] ppn_res_3 = _entries_barrier_11_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore_6 = _ppn_ignore_T_6; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_25 = ppn_ignore_6 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_26 = {_ppn_T_25[26:20], _ppn_T_25[19:0] | _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_27 = _ppn_T_26[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_28 = {ppn_res_3, _ppn_T_27}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_7 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :197:28, :341:30]
wire [26:0] _ppn_T_30 = {_ppn_T_29[26:20], _ppn_T_29[19:0] | _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_31 = _ppn_T_30[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_32 = {_ppn_T_28, _ppn_T_31}; // @[TLB.scala:198:{18,58}]
wire [1:0] ppn_res_4 = _entries_barrier_12_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore_8 = _ppn_ignore_T_8; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_33 = ppn_ignore_8 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_34 = {_ppn_T_33[26:20], _ppn_T_33[19:0] | _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_35 = _ppn_T_34[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_36 = {ppn_res_4, _ppn_T_35}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_9 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56]
wire ppn_ignore_9 = _ppn_ignore_T_9; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_37 = ppn_ignore_9 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_38 = {_ppn_T_37[26:20], _ppn_T_37[19:0] | _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_39 = _ppn_T_38[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_40 = {_ppn_T_36, _ppn_T_39}; // @[TLB.scala:198:{18,58}]
wire [19:0] _ppn_T_41 = vpn[19:0]; // @[TLB.scala:335:30, :502:125]
wire [19:0] _ppn_T_42 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_43 = hitsVec_1 ? _entries_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_44 = hitsVec_2 ? _entries_barrier_2_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_45 = hitsVec_3 ? _entries_barrier_3_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_46 = hitsVec_4 ? _entries_barrier_4_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_47 = hitsVec_5 ? _entries_barrier_5_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_48 = hitsVec_6 ? _entries_barrier_6_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_49 = hitsVec_7 ? _entries_barrier_7_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_50 = hitsVec_8 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_51 = hitsVec_9 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_52 = hitsVec_10 ? _ppn_T_24 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_53 = hitsVec_11 ? _ppn_T_32 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_54 = hitsVec_12 ? _ppn_T_40 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_55 = _ppn_T ? _ppn_T_41 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_56 = _ppn_T_42 | _ppn_T_43; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_57 = _ppn_T_56 | _ppn_T_44; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_58 = _ppn_T_57 | _ppn_T_45; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_59 = _ppn_T_58 | _ppn_T_46; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_60 = _ppn_T_59 | _ppn_T_47; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_61 = _ppn_T_60 | _ppn_T_48; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_62 = _ppn_T_61 | _ppn_T_49; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_63 = _ppn_T_62 | _ppn_T_50; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_64 = _ppn_T_63 | _ppn_T_51; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_65 = _ppn_T_64 | _ppn_T_52; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_66 = _ppn_T_65 | _ppn_T_53; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_67 = _ppn_T_66 | _ppn_T_54; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_68 = _ppn_T_67 | _ppn_T_55; // @[Mux.scala:30:73]
wire [19:0] ppn = _ppn_T_68; // @[Mux.scala:30:73]
wire [1:0] ptw_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_ae_array_lo_lo = {ptw_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_ae_array_lo_hi = {ptw_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [5:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, ptw_ae_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ptw_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_ptw, _entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_ae_array_hi_lo = {ptw_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_ptw, _entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_ptw, _entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [3:0] ptw_ae_array_hi_hi = {ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, ptw_ae_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27]
wire [13:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27]
wire [1:0] final_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] final_ae_array_lo_lo = {final_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] final_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] final_ae_array_lo_hi = {final_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [5:0] final_ae_array_lo = {final_ae_array_lo_hi, final_ae_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] final_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_final, _entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] final_ae_array_hi_lo = {final_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] final_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_final, _entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] final_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_final, _entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [3:0] final_ae_array_hi_hi = {final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] final_ae_array_hi = {final_ae_array_hi_hi, final_ae_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27]
wire [13:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27]
wire [1:0] ptw_pf_array_lo_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_pf_array_lo_lo = {ptw_pf_array_lo_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_pf_array_lo_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_pf_array_lo_hi = {ptw_pf_array_lo_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [5:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, ptw_pf_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ptw_pf_array_hi_lo_hi = {_entries_barrier_8_io_y_pf, _entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_pf_array_hi_lo = {ptw_pf_array_hi_lo_hi, _entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_pf_array_hi_hi_lo = {_entries_barrier_10_io_y_pf, _entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_pf_array_hi_hi_hi = {_entries_barrier_12_io_y_pf, _entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [3:0] ptw_pf_array_hi_hi = {ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, ptw_pf_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27]
wire [13:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27]
wire [1:0] ptw_gf_array_lo_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_gf_array_lo_lo = {ptw_gf_array_lo_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_gf_array_lo_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_gf_array_lo_hi = {ptw_gf_array_lo_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [5:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, ptw_gf_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ptw_gf_array_hi_lo_hi = {_entries_barrier_8_io_y_gf, _entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_gf_array_hi_lo = {ptw_gf_array_hi_lo_hi, _entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_gf_array_hi_hi_lo = {_entries_barrier_10_io_y_gf, _entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_gf_array_hi_hi_hi = {_entries_barrier_12_io_y_gf, _entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [3:0] ptw_gf_array_hi_hi = {ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, ptw_gf_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27]
wire [13:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27]
wire [13:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82]
wire [13:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63]
wire [13:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46]
wire _priv_rw_ok_T = ~priv_s; // @[TLB.scala:370:20, :513:24]
wire _priv_rw_ok_T_1 = _priv_rw_ok_T | sum; // @[TLB.scala:510:16, :513:{24,32}]
wire [1:0] _GEN_40 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_lo_lo_hi; // @[package.scala:45:27]
assign priv_rw_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_lo_hi; // @[package.scala:45:27]
assign priv_x_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27]
assign priv_x_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_lo = {priv_rw_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_41 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_lo_hi_hi; // @[package.scala:45:27]
assign priv_rw_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_hi_hi; // @[package.scala:45:27]
assign priv_x_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27]
assign priv_x_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_hi = {priv_rw_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, priv_rw_ok_lo_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_42 = {_entries_barrier_8_io_y_u, _entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_hi_lo_hi; // @[package.scala:45:27]
assign priv_rw_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_lo_hi; // @[package.scala:45:27]
assign priv_x_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27]
assign priv_x_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_hi_lo = {priv_rw_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_43 = {_entries_barrier_10_io_y_u, _entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_hi_hi_lo; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_lo; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27]
wire [1:0] _GEN_44 = {_entries_barrier_12_io_y_u, _entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_hi_hi_hi; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_hi; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27]
wire [3:0] priv_rw_ok_hi_hi = {priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, priv_rw_ok_hi_lo}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_1 ? _priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_lo_1 = {priv_rw_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_rw_ok_lo_hi_1 = {priv_rw_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1}; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_hi_lo_1 = {priv_rw_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] priv_rw_ok_hi_hi_1 = {priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_6 = priv_s ? _priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}]
wire [12:0] priv_rw_ok = _priv_rw_ok_T_3 | _priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}]
wire [2:0] priv_x_ok_lo_lo = {priv_x_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_x_ok_lo_hi = {priv_x_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_x_ok_lo = {priv_x_ok_lo_hi, priv_x_ok_lo_lo}; // @[package.scala:45:27]
wire [2:0] priv_x_ok_hi_lo = {priv_x_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] priv_x_ok_hi_hi = {priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] priv_x_ok_hi = {priv_x_ok_hi_hi, priv_x_ok_hi_lo}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27]
wire [2:0] priv_x_ok_lo_lo_1 = {priv_x_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_x_ok_lo_hi_1 = {priv_x_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1}; // @[package.scala:45:27]
wire [2:0] priv_x_ok_hi_lo_1 = {priv_x_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] priv_x_ok_hi_hi_1 = {priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27]
wire [12:0] priv_x_ok = priv_s ? _priv_x_ok_T_1 : _priv_x_ok_T_2; // @[package.scala:45:27]
wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83]
wire [12:0] _stage1_bypass_T_2 = {13{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}]
wire [1:0] stage1_bypass_lo_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] stage1_bypass_lo_lo = {stage1_bypass_lo_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] stage1_bypass_lo_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] stage1_bypass_lo_hi = {stage1_bypass_lo_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [5:0] stage1_bypass_lo = {stage1_bypass_lo_hi, stage1_bypass_lo_lo}; // @[package.scala:45:27]
wire [1:0] stage1_bypass_hi_lo_hi = {_entries_barrier_8_io_y_ae_stage2, _entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] stage1_bypass_hi_lo = {stage1_bypass_hi_lo_hi, _entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] stage1_bypass_hi_hi_lo = {_entries_barrier_10_io_y_ae_stage2, _entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] stage1_bypass_hi_hi_hi = {_entries_barrier_12_io_y_ae_stage2, _entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [3:0] stage1_bypass_hi_hi = {stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] stage1_bypass_hi = {stage1_bypass_hi_hi, stage1_bypass_hi_lo}; // @[package.scala:45:27]
wire [12:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27]
wire [12:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 | _stage1_bypass_T_3; // @[package.scala:45:27]
wire [1:0] r_array_lo_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] r_array_lo_lo = {r_array_lo_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_lo_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] r_array_lo_hi = {r_array_lo_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [5:0] r_array_lo = {r_array_lo_hi, r_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] r_array_hi_lo_hi = {_entries_barrier_8_io_y_sr, _entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] r_array_hi_lo = {r_array_hi_lo_hi, _entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_lo = {_entries_barrier_10_io_y_sr, _entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_hi = {_entries_barrier_12_io_y_sr, _entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [3:0] r_array_hi_hi = {r_array_hi_hi_hi, r_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] r_array_hi = {r_array_hi_hi, r_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_45 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_lo_lo_hi_1; // @[package.scala:45:27]
assign r_array_lo_lo_hi_1 = _GEN_45; // @[package.scala:45:27]
wire [1:0] x_array_lo_lo_hi; // @[package.scala:45:27]
assign x_array_lo_lo_hi = _GEN_45; // @[package.scala:45:27]
wire [2:0] r_array_lo_lo_1 = {r_array_lo_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_46 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_lo_hi_hi_1; // @[package.scala:45:27]
assign r_array_lo_hi_hi_1 = _GEN_46; // @[package.scala:45:27]
wire [1:0] x_array_lo_hi_hi; // @[package.scala:45:27]
assign x_array_lo_hi_hi = _GEN_46; // @[package.scala:45:27]
wire [2:0] r_array_lo_hi_1 = {r_array_lo_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [5:0] r_array_lo_1 = {r_array_lo_hi_1, r_array_lo_lo_1}; // @[package.scala:45:27]
wire [1:0] _GEN_47 = {_entries_barrier_8_io_y_sx, _entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_lo_hi_1; // @[package.scala:45:27]
assign r_array_hi_lo_hi_1 = _GEN_47; // @[package.scala:45:27]
wire [1:0] x_array_hi_lo_hi; // @[package.scala:45:27]
assign x_array_hi_lo_hi = _GEN_47; // @[package.scala:45:27]
wire [2:0] r_array_hi_lo_1 = {r_array_hi_lo_hi_1, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_48 = {_entries_barrier_10_io_y_sx, _entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_lo_1; // @[package.scala:45:27]
assign r_array_hi_hi_lo_1 = _GEN_48; // @[package.scala:45:27]
wire [1:0] x_array_hi_hi_lo; // @[package.scala:45:27]
assign x_array_hi_hi_lo = _GEN_48; // @[package.scala:45:27]
wire [1:0] _GEN_49 = {_entries_barrier_12_io_y_sx, _entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_hi_1; // @[package.scala:45:27]
assign r_array_hi_hi_hi_1 = _GEN_49; // @[package.scala:45:27]
wire [1:0] x_array_hi_hi_hi; // @[package.scala:45:27]
assign x_array_hi_hi_hi = _GEN_49; // @[package.scala:45:27]
wire [3:0] r_array_hi_hi_1 = {r_array_hi_hi_hi_1, r_array_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] r_array_hi_1 = {r_array_hi_hi_1, r_array_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27]
wire [12:0] _r_array_T_2 = mxr ? _r_array_T_1 : 13'h0; // @[package.scala:45:27]
wire [12:0] _r_array_T_3 = _r_array_T | _r_array_T_2; // @[package.scala:45:27]
wire [12:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}]
wire [12:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}]
wire [13:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}]
wire [13:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41]
wire [1:0] w_array_lo_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] w_array_lo_lo = {w_array_lo_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] w_array_lo_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] w_array_lo_hi = {w_array_lo_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [5:0] w_array_lo = {w_array_lo_hi, w_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] w_array_hi_lo_hi = {_entries_barrier_8_io_y_sw, _entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] w_array_hi_lo = {w_array_hi_lo_hi, _entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] w_array_hi_hi_lo = {_entries_barrier_10_io_y_sw, _entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] w_array_hi_hi_hi = {_entries_barrier_12_io_y_sw, _entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [3:0] w_array_hi_hi = {w_array_hi_hi_hi, w_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] w_array_hi = {w_array_hi_hi, w_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27]
wire [12:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27]
wire [12:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}]
wire [13:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}]
wire [2:0] x_array_lo_lo = {x_array_lo_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [2:0] x_array_lo_hi = {x_array_lo_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [5:0] x_array_lo = {x_array_lo_hi, x_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] x_array_hi_lo = {x_array_hi_lo_hi, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [3:0] x_array_hi_hi = {x_array_hi_hi_hi, x_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] x_array_hi = {x_array_hi_hi, x_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27]
wire [12:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27]
wire [12:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}]
wire [13:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}]
wire [1:0] hr_array_lo_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] hr_array_lo_lo = {hr_array_lo_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_lo_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] hr_array_lo_hi = {hr_array_lo_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [5:0] hr_array_lo = {hr_array_lo_hi, hr_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] hr_array_hi_lo_hi = {_entries_barrier_8_io_y_hr, _entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] hr_array_hi_lo = {hr_array_hi_lo_hi, _entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_lo = {_entries_barrier_10_io_y_hr, _entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_hi = {_entries_barrier_12_io_y_hr, _entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [3:0] hr_array_hi_hi = {hr_array_hi_hi_hi, hr_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] hr_array_hi = {hr_array_hi_hi, hr_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_50 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_lo_lo_hi_1; // @[package.scala:45:27]
assign hr_array_lo_lo_hi_1 = _GEN_50; // @[package.scala:45:27]
wire [1:0] hx_array_lo_lo_hi; // @[package.scala:45:27]
assign hx_array_lo_lo_hi = _GEN_50; // @[package.scala:45:27]
wire [2:0] hr_array_lo_lo_1 = {hr_array_lo_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_51 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_lo_hi_hi_1; // @[package.scala:45:27]
assign hr_array_lo_hi_hi_1 = _GEN_51; // @[package.scala:45:27]
wire [1:0] hx_array_lo_hi_hi; // @[package.scala:45:27]
assign hx_array_lo_hi_hi = _GEN_51; // @[package.scala:45:27]
wire [2:0] hr_array_lo_hi_1 = {hr_array_lo_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [5:0] hr_array_lo_1 = {hr_array_lo_hi_1, hr_array_lo_lo_1}; // @[package.scala:45:27]
wire [1:0] _GEN_52 = {_entries_barrier_8_io_y_hx, _entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_lo_hi_1; // @[package.scala:45:27]
assign hr_array_hi_lo_hi_1 = _GEN_52; // @[package.scala:45:27]
wire [1:0] hx_array_hi_lo_hi; // @[package.scala:45:27]
assign hx_array_hi_lo_hi = _GEN_52; // @[package.scala:45:27]
wire [2:0] hr_array_hi_lo_1 = {hr_array_hi_lo_hi_1, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_53 = {_entries_barrier_10_io_y_hx, _entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_lo_1; // @[package.scala:45:27]
assign hr_array_hi_hi_lo_1 = _GEN_53; // @[package.scala:45:27]
wire [1:0] hx_array_hi_hi_lo; // @[package.scala:45:27]
assign hx_array_hi_hi_lo = _GEN_53; // @[package.scala:45:27]
wire [1:0] _GEN_54 = {_entries_barrier_12_io_y_hx, _entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_hi_1; // @[package.scala:45:27]
assign hr_array_hi_hi_hi_1 = _GEN_54; // @[package.scala:45:27]
wire [1:0] hx_array_hi_hi_hi; // @[package.scala:45:27]
assign hx_array_hi_hi_hi = _GEN_54; // @[package.scala:45:27]
wire [3:0] hr_array_hi_hi_1 = {hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] hr_array_hi_1 = {hr_array_hi_hi_1, hr_array_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27]
wire [12:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 13'h0; // @[package.scala:45:27]
wire [12:0] _hr_array_T_3 = _hr_array_T | _hr_array_T_2; // @[package.scala:45:27]
wire [1:0] hw_array_lo_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] hw_array_lo_lo = {hw_array_lo_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] hw_array_lo_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] hw_array_lo_hi = {hw_array_lo_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [5:0] hw_array_lo = {hw_array_lo_hi, hw_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] hw_array_hi_lo_hi = {_entries_barrier_8_io_y_hw, _entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] hw_array_hi_lo = {hw_array_hi_lo_hi, _entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] hw_array_hi_hi_lo = {_entries_barrier_10_io_y_hw, _entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] hw_array_hi_hi_hi = {_entries_barrier_12_io_y_hw, _entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [3:0] hw_array_hi_hi = {hw_array_hi_hi_hi, hw_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] hw_array_hi = {hw_array_hi_hi, hw_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27]
wire [2:0] hx_array_lo_lo = {hx_array_lo_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [2:0] hx_array_lo_hi = {hx_array_lo_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [5:0] hx_array_lo = {hx_array_lo_hi, hx_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] hx_array_hi_lo = {hx_array_hi_lo_hi, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [3:0] hx_array_hi_hi = {hx_array_hi_hi_hi, hx_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] hx_array_hi = {hx_array_hi_hi, hx_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27]
wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26]
wire [1:0] pr_array_lo_lo_hi = {_entries_barrier_2_io_y_pr, _entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_lo_lo = {pr_array_lo_lo_hi, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [1:0] pr_array_lo_hi_hi = {_entries_barrier_5_io_y_pr, _entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_lo_hi = {pr_array_lo_hi_hi, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [5:0] pr_array_lo = {pr_array_lo_hi, pr_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pr_array_hi_lo_hi = {_entries_barrier_8_io_y_pr, _entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_hi_lo = {pr_array_hi_lo_hi, _entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [1:0] pr_array_hi_hi_hi = {_entries_barrier_11_io_y_pr, _entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_hi_hi = {pr_array_hi_hi_hi, _entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [5:0] pr_array_hi = {pr_array_hi_hi, pr_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27]
wire [13:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27]
wire [13:0] _GEN_55 = ptw_ae_array | final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104]
wire [13:0] _pr_array_T_3; // @[TLB.scala:529:104]
assign _pr_array_T_3 = _GEN_55; // @[TLB.scala:529:104]
wire [13:0] _pw_array_T_3; // @[TLB.scala:531:104]
assign _pw_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :531:104]
wire [13:0] _px_array_T_3; // @[TLB.scala:533:104]
assign _px_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :533:104]
wire [13:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}]
wire [13:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}]
wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26]
wire [1:0] pw_array_lo_lo_hi = {_entries_barrier_2_io_y_pw, _entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_lo_lo = {pw_array_lo_lo_hi, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [1:0] pw_array_lo_hi_hi = {_entries_barrier_5_io_y_pw, _entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_lo_hi = {pw_array_lo_hi_hi, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [5:0] pw_array_lo = {pw_array_lo_hi, pw_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pw_array_hi_lo_hi = {_entries_barrier_8_io_y_pw, _entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_hi_lo = {pw_array_hi_lo_hi, _entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [1:0] pw_array_hi_hi_hi = {_entries_barrier_11_io_y_pw, _entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_hi_hi = {pw_array_hi_hi_hi, _entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [5:0] pw_array_hi = {pw_array_hi_hi, pw_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27]
wire [13:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27]
wire [13:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}]
wire [13:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}]
wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26]
wire [1:0] px_array_lo_lo_hi = {_entries_barrier_2_io_y_px, _entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_lo_lo = {px_array_lo_lo_hi, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25]
wire [1:0] px_array_lo_hi_hi = {_entries_barrier_5_io_y_px, _entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_lo_hi = {px_array_lo_hi_hi, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25]
wire [5:0] px_array_lo = {px_array_lo_hi, px_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] px_array_hi_lo_hi = {_entries_barrier_8_io_y_px, _entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_hi_lo = {px_array_hi_lo_hi, _entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25]
wire [1:0] px_array_hi_hi_hi = {_entries_barrier_11_io_y_px, _entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_hi_hi = {px_array_hi_hi_hi, _entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25]
wire [5:0] px_array_hi = {px_array_hi_hi, px_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27]
wire [13:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27]
wire [13:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}]
wire [13:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}]
wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27]
wire [1:0] eff_array_lo_lo_hi = {_entries_barrier_2_io_y_eff, _entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_lo_lo = {eff_array_lo_lo_hi, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [1:0] eff_array_lo_hi_hi = {_entries_barrier_5_io_y_eff, _entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_lo_hi = {eff_array_lo_hi_hi, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [5:0] eff_array_lo = {eff_array_lo_hi, eff_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] eff_array_hi_lo_hi = {_entries_barrier_8_io_y_eff, _entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_hi_lo = {eff_array_hi_lo_hi, _entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [1:0] eff_array_hi_hi_hi = {_entries_barrier_11_io_y_eff, _entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_hi_hi = {eff_array_hi_hi_hi, _entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [5:0] eff_array_hi = {eff_array_hi_hi, eff_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27]
wire [13:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27]
wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25]
wire [1:0] _GEN_56 = {_entries_barrier_2_io_y_c, _entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_lo_lo_hi; // @[package.scala:45:27]
assign c_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27]
wire [1:0] prefetchable_array_lo_lo_hi; // @[package.scala:45:27]
assign prefetchable_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27]
wire [2:0] c_array_lo_lo = {c_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_57 = {_entries_barrier_5_io_y_c, _entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_lo_hi_hi; // @[package.scala:45:27]
assign c_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27]
wire [1:0] prefetchable_array_lo_hi_hi; // @[package.scala:45:27]
assign prefetchable_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27]
wire [2:0] c_array_lo_hi = {c_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] c_array_lo = {c_array_lo_hi, c_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_58 = {_entries_barrier_8_io_y_c, _entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_hi_lo_hi; // @[package.scala:45:27]
assign c_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27]
wire [1:0] prefetchable_array_hi_lo_hi; // @[package.scala:45:27]
assign prefetchable_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27]
wire [2:0] c_array_hi_lo = {c_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_59 = {_entries_barrier_11_io_y_c, _entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_hi_hi_hi; // @[package.scala:45:27]
assign c_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27]
wire [1:0] prefetchable_array_hi_hi_hi; // @[package.scala:45:27]
assign prefetchable_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27]
wire [2:0] c_array_hi_hi = {c_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] c_array_hi = {c_array_hi_hi, c_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27]
wire [13:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27]
wire [13:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24]
wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27]
wire [1:0] ppp_array_lo_lo_hi = {_entries_barrier_2_io_y_ppp, _entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_lo_lo = {ppp_array_lo_lo_hi, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [1:0] ppp_array_lo_hi_hi = {_entries_barrier_5_io_y_ppp, _entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_lo_hi = {ppp_array_lo_hi_hi, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [5:0] ppp_array_lo = {ppp_array_lo_hi, ppp_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ppp_array_hi_lo_hi = {_entries_barrier_8_io_y_ppp, _entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_hi_lo = {ppp_array_hi_lo_hi, _entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [1:0] ppp_array_hi_hi_hi = {_entries_barrier_11_io_y_ppp, _entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_hi_hi = {ppp_array_hi_hi_hi, _entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [5:0] ppp_array_hi = {ppp_array_hi_hi, ppp_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27]
wire [13:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27]
wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27]
wire [1:0] paa_array_lo_lo_hi = {_entries_barrier_2_io_y_paa, _entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_lo_lo = {paa_array_lo_lo_hi, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [1:0] paa_array_lo_hi_hi = {_entries_barrier_5_io_y_paa, _entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_lo_hi = {paa_array_lo_hi_hi, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [5:0] paa_array_lo = {paa_array_lo_hi, paa_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] paa_array_hi_lo_hi = {_entries_barrier_8_io_y_paa, _entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_hi_lo = {paa_array_hi_lo_hi, _entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [1:0] paa_array_hi_hi_hi = {_entries_barrier_11_io_y_paa, _entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_hi_hi = {paa_array_hi_hi_hi, _entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [5:0] paa_array_hi = {paa_array_hi_hi, paa_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27]
wire [13:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27]
wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27]
wire [1:0] pal_array_lo_lo_hi = {_entries_barrier_2_io_y_pal, _entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_lo_lo = {pal_array_lo_lo_hi, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [1:0] pal_array_lo_hi_hi = {_entries_barrier_5_io_y_pal, _entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_lo_hi = {pal_array_lo_hi_hi, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [5:0] pal_array_lo = {pal_array_lo_hi, pal_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pal_array_hi_lo_hi = {_entries_barrier_8_io_y_pal, _entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_hi_lo = {pal_array_hi_lo_hi, _entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [1:0] pal_array_hi_hi_hi = {_entries_barrier_11_io_y_pal, _entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_hi_hi = {pal_array_hi_hi_hi, _entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [5:0] pal_array_hi = {pal_array_hi_hi, pal_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27]
wire [13:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27]
wire [13:0] ppp_array_if_cached = ppp_array | c_array; // @[TLB.scala:537:20, :539:22, :544:39]
wire [13:0] paa_array_if_cached = paa_array | c_array; // @[TLB.scala:537:20, :541:22, :545:39]
wire [13:0] pal_array_if_cached = pal_array | c_array; // @[TLB.scala:537:20, :543:22, :546:39]
wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65]
wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}]
wire [2:0] prefetchable_array_lo_lo = {prefetchable_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25]
wire [2:0] prefetchable_array_lo_hi = {prefetchable_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] prefetchable_array_lo = {prefetchable_array_lo_hi, prefetchable_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] prefetchable_array_hi_lo = {prefetchable_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25]
wire [2:0] prefetchable_array_hi_hi = {prefetchable_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] prefetchable_array_hi = {prefetchable_array_hi_hi, prefetchable_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27]
wire [13:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27]
wire [3:0] _misaligned_T = 4'h1 << io_req_bits_size_0; // @[OneHot.scala:58:35]
wire [4:0] _misaligned_T_1 = {1'h0, _misaligned_T} - 5'h1; // @[OneHot.scala:58:35]
wire [3:0] _misaligned_T_2 = _misaligned_T_1[3:0]; // @[TLB.scala:550:69]
wire [39:0] _misaligned_T_3 = {36'h0, io_req_bits_vaddr_0[3:0] & _misaligned_T_2}; // @[TLB.scala:318:7, :550:{39,69}]
wire misaligned = |_misaligned_T_3; // @[TLB.scala:550:{39,77}]
wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21]
wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43]
wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:559:43, :560:51]
wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86]
wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}]
wire _bad_va_T_5 = _bad_va_T_2 | _bad_va_T_4; // @[TLB.scala:560:{51,59,71}]
wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}]
wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}]
wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}]
wire _GEN_60 = io_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47]
wire _cmd_lrsc_T; // @[package.scala:16:47]
assign _cmd_lrsc_T = _GEN_60; // @[package.scala:16:47]
wire _cmd_read_T_2; // @[package.scala:16:47]
assign _cmd_read_T_2 = _GEN_60; // @[package.scala:16:47]
wire _GEN_61 = io_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47]
wire _cmd_lrsc_T_1; // @[package.scala:16:47]
assign _cmd_lrsc_T_1 = _GEN_61; // @[package.scala:16:47]
wire _cmd_read_T_3; // @[package.scala:16:47]
assign _cmd_read_T_3 = _GEN_61; // @[package.scala:16:47]
wire _cmd_write_T_3; // @[Consts.scala:90:66]
assign _cmd_write_T_3 = _GEN_61; // @[package.scala:16:47]
wire _cmd_lrsc_T_2 = _cmd_lrsc_T | _cmd_lrsc_T_1; // @[package.scala:16:47, :81:59]
wire cmd_lrsc = _cmd_lrsc_T_2; // @[package.scala:81:59]
wire _GEN_62 = io_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47]
wire _cmd_amo_logical_T; // @[package.scala:16:47]
assign _cmd_amo_logical_T = _GEN_62; // @[package.scala:16:47]
wire _cmd_read_T_7; // @[package.scala:16:47]
assign _cmd_read_T_7 = _GEN_62; // @[package.scala:16:47]
wire _cmd_write_T_5; // @[package.scala:16:47]
assign _cmd_write_T_5 = _GEN_62; // @[package.scala:16:47]
wire _GEN_63 = io_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47]
wire _cmd_amo_logical_T_1; // @[package.scala:16:47]
assign _cmd_amo_logical_T_1 = _GEN_63; // @[package.scala:16:47]
wire _cmd_read_T_8; // @[package.scala:16:47]
assign _cmd_read_T_8 = _GEN_63; // @[package.scala:16:47]
wire _cmd_write_T_6; // @[package.scala:16:47]
assign _cmd_write_T_6 = _GEN_63; // @[package.scala:16:47]
wire _GEN_64 = io_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47]
wire _cmd_amo_logical_T_2; // @[package.scala:16:47]
assign _cmd_amo_logical_T_2 = _GEN_64; // @[package.scala:16:47]
wire _cmd_read_T_9; // @[package.scala:16:47]
assign _cmd_read_T_9 = _GEN_64; // @[package.scala:16:47]
wire _cmd_write_T_7; // @[package.scala:16:47]
assign _cmd_write_T_7 = _GEN_64; // @[package.scala:16:47]
wire _GEN_65 = io_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47]
wire _cmd_amo_logical_T_3; // @[package.scala:16:47]
assign _cmd_amo_logical_T_3 = _GEN_65; // @[package.scala:16:47]
wire _cmd_read_T_10; // @[package.scala:16:47]
assign _cmd_read_T_10 = _GEN_65; // @[package.scala:16:47]
wire _cmd_write_T_8; // @[package.scala:16:47]
assign _cmd_write_T_8 = _GEN_65; // @[package.scala:16:47]
wire _cmd_amo_logical_T_4 = _cmd_amo_logical_T | _cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59]
wire _cmd_amo_logical_T_5 = _cmd_amo_logical_T_4 | _cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59]
wire _cmd_amo_logical_T_6 = _cmd_amo_logical_T_5 | _cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59]
wire cmd_amo_logical = _cmd_amo_logical_T_6; // @[package.scala:81:59]
wire _GEN_66 = io_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T = _GEN_66; // @[package.scala:16:47]
wire _cmd_read_T_14; // @[package.scala:16:47]
assign _cmd_read_T_14 = _GEN_66; // @[package.scala:16:47]
wire _cmd_write_T_12; // @[package.scala:16:47]
assign _cmd_write_T_12 = _GEN_66; // @[package.scala:16:47]
wire _GEN_67 = io_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_1; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_1 = _GEN_67; // @[package.scala:16:47]
wire _cmd_read_T_15; // @[package.scala:16:47]
assign _cmd_read_T_15 = _GEN_67; // @[package.scala:16:47]
wire _cmd_write_T_13; // @[package.scala:16:47]
assign _cmd_write_T_13 = _GEN_67; // @[package.scala:16:47]
wire _GEN_68 = io_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_2; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_2 = _GEN_68; // @[package.scala:16:47]
wire _cmd_read_T_16; // @[package.scala:16:47]
assign _cmd_read_T_16 = _GEN_68; // @[package.scala:16:47]
wire _cmd_write_T_14; // @[package.scala:16:47]
assign _cmd_write_T_14 = _GEN_68; // @[package.scala:16:47]
wire _GEN_69 = io_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_3; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_3 = _GEN_69; // @[package.scala:16:47]
wire _cmd_read_T_17; // @[package.scala:16:47]
assign _cmd_read_T_17 = _GEN_69; // @[package.scala:16:47]
wire _cmd_write_T_15; // @[package.scala:16:47]
assign _cmd_write_T_15 = _GEN_69; // @[package.scala:16:47]
wire _GEN_70 = io_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_4; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_4 = _GEN_70; // @[package.scala:16:47]
wire _cmd_read_T_18; // @[package.scala:16:47]
assign _cmd_read_T_18 = _GEN_70; // @[package.scala:16:47]
wire _cmd_write_T_16; // @[package.scala:16:47]
assign _cmd_write_T_16 = _GEN_70; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_5 = _cmd_amo_arithmetic_T | _cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59]
wire _cmd_amo_arithmetic_T_6 = _cmd_amo_arithmetic_T_5 | _cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59]
wire _cmd_amo_arithmetic_T_7 = _cmd_amo_arithmetic_T_6 | _cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59]
wire _cmd_amo_arithmetic_T_8 = _cmd_amo_arithmetic_T_7 | _cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59]
wire cmd_amo_arithmetic = _cmd_amo_arithmetic_T_8; // @[package.scala:81:59]
wire _GEN_71 = io_req_bits_cmd_0 == 5'h11; // @[TLB.scala:318:7, :573:41]
wire cmd_put_partial; // @[TLB.scala:573:41]
assign cmd_put_partial = _GEN_71; // @[TLB.scala:573:41]
wire _cmd_write_T_1; // @[Consts.scala:90:49]
assign _cmd_write_T_1 = _GEN_71; // @[TLB.scala:573:41]
wire _cmd_read_T = io_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47]
wire _GEN_72 = io_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47]
wire _cmd_read_T_1; // @[package.scala:16:47]
assign _cmd_read_T_1 = _GEN_72; // @[package.scala:16:47]
wire _cmd_readx_T; // @[TLB.scala:575:56]
assign _cmd_readx_T = _GEN_72; // @[package.scala:16:47]
wire _cmd_read_T_4 = _cmd_read_T | _cmd_read_T_1; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_5 = _cmd_read_T_4 | _cmd_read_T_2; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_6 = _cmd_read_T_5 | _cmd_read_T_3; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_11 = _cmd_read_T_7 | _cmd_read_T_8; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_12 = _cmd_read_T_11 | _cmd_read_T_9; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_13 = _cmd_read_T_12 | _cmd_read_T_10; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_19 = _cmd_read_T_14 | _cmd_read_T_15; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_20 = _cmd_read_T_19 | _cmd_read_T_16; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_21 = _cmd_read_T_20 | _cmd_read_T_17; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_22 = _cmd_read_T_21 | _cmd_read_T_18; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_23 = _cmd_read_T_13 | _cmd_read_T_22; // @[package.scala:81:59]
wire cmd_read = _cmd_read_T_6 | _cmd_read_T_23; // @[package.scala:81:59]
wire _cmd_write_T = io_req_bits_cmd_0 == 5'h1; // @[TLB.scala:318:7]
wire _cmd_write_T_2 = _cmd_write_T | _cmd_write_T_1; // @[Consts.scala:90:{32,42,49}]
wire _cmd_write_T_4 = _cmd_write_T_2 | _cmd_write_T_3; // @[Consts.scala:90:{42,59,66}]
wire _cmd_write_T_9 = _cmd_write_T_5 | _cmd_write_T_6; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_10 = _cmd_write_T_9 | _cmd_write_T_7; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_11 = _cmd_write_T_10 | _cmd_write_T_8; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_17 = _cmd_write_T_12 | _cmd_write_T_13; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_18 = _cmd_write_T_17 | _cmd_write_T_14; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_19 = _cmd_write_T_18 | _cmd_write_T_15; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_20 = _cmd_write_T_19 | _cmd_write_T_16; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_21 = _cmd_write_T_11 | _cmd_write_T_20; // @[package.scala:81:59]
wire cmd_write = _cmd_write_T_4 | _cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _cmd_write_perms_T = io_req_bits_cmd_0 == 5'h5; // @[package.scala:16:47]
wire _cmd_write_perms_T_1 = io_req_bits_cmd_0 == 5'h17; // @[package.scala:16:47]
wire _cmd_write_perms_T_2 = _cmd_write_perms_T | _cmd_write_perms_T_1; // @[package.scala:16:47, :81:59]
wire cmd_write_perms = cmd_write | _cmd_write_perms_T_2; // @[package.scala:81:59]
wire [13:0] _ae_array_T = misaligned ? eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8]
wire [13:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19]
wire [13:0] _ae_array_T_2 = cmd_lrsc ? _ae_array_T_1 : 14'h0; // @[TLB.scala:570:33, :583:{8,19}]
wire [13:0] ae_array = _ae_array_T | _ae_array_T_2; // @[TLB.scala:582:{8,37}, :583:8]
wire [13:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46]
wire [13:0] _ae_ld_array_T_1 = ae_array | _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}]
wire [13:0] ae_ld_array = cmd_read ? _ae_ld_array_T_1 : 14'h0; // @[TLB.scala:586:{24,44}]
wire [13:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37]
wire [13:0] _ae_st_array_T_1 = ae_array | _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}]
wire [13:0] _ae_st_array_T_2 = cmd_write_perms ? _ae_st_array_T_1 : 14'h0; // @[TLB.scala:577:35, :588:{8,35}]
wire [13:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26]
wire [13:0] _ae_st_array_T_4 = cmd_put_partial ? _ae_st_array_T_3 : 14'h0; // @[TLB.scala:573:41, :589:{8,26}]
wire [13:0] _ae_st_array_T_5 = _ae_st_array_T_2 | _ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8]
wire [13:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26]
wire [13:0] _ae_st_array_T_7 = cmd_amo_logical ? _ae_st_array_T_6 : 14'h0; // @[TLB.scala:571:40, :590:{8,26}]
wire [13:0] _ae_st_array_T_8 = _ae_st_array_T_5 | _ae_st_array_T_7; // @[TLB.scala:588:53, :589:53, :590:8]
wire [13:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29]
wire [13:0] _ae_st_array_T_10 = cmd_amo_arithmetic ? _ae_st_array_T_9 : 14'h0; // @[TLB.scala:572:43, :591:{8,29}]
wire [13:0] ae_st_array = _ae_st_array_T_8 | _ae_st_array_T_10; // @[TLB.scala:589:53, :590:53, :591:8]
wire [13:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26]
wire [13:0] _must_alloc_array_T_1 = cmd_put_partial ? _must_alloc_array_T : 14'h0; // @[TLB.scala:573:41, :593:{8,26}]
wire [13:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26]
wire [13:0] _must_alloc_array_T_3 = cmd_amo_logical ? _must_alloc_array_T_2 : 14'h0; // @[TLB.scala:571:40, :594:{8,26}]
wire [13:0] _must_alloc_array_T_4 = _must_alloc_array_T_1 | _must_alloc_array_T_3; // @[TLB.scala:593:{8,43}, :594:8]
wire [13:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29]
wire [13:0] _must_alloc_array_T_6 = cmd_amo_arithmetic ? _must_alloc_array_T_5 : 14'h0; // @[TLB.scala:572:43, :595:{8,29}]
wire [13:0] _must_alloc_array_T_7 = _must_alloc_array_T_4 | _must_alloc_array_T_6; // @[TLB.scala:593:43, :594:43, :595:8]
wire [13:0] _must_alloc_array_T_9 = {14{cmd_lrsc}}; // @[TLB.scala:570:33, :596:8]
wire [13:0] must_alloc_array = _must_alloc_array_T_7 | _must_alloc_array_T_9; // @[TLB.scala:594:43, :595:46, :596:8]
wire [13:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}]
wire [13:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73]
wire [13:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}]
wire [13:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 | ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}]
wire [13:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106]
wire [13:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}]
wire [13:0] pf_ld_array = cmd_read ? _pf_ld_array_T_6 : 14'h0; // @[TLB.scala:597:{24,104}]
wire [13:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44]
wire [13:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55]
wire [13:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}]
wire [13:0] _pf_st_array_T_3 = _pf_st_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}]
wire [13:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88]
wire [13:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}]
wire [13:0] pf_st_array = cmd_write_perms ? _pf_st_array_T_5 : 14'h0; // @[TLB.scala:577:35, :598:{24,86}]
wire [13:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25]
wire [13:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36]
wire [13:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}]
wire [13:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}]
wire [13:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69]
wire [13:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}]
wire [13:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100]
wire [13:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}]
wire [13:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81]
wire [13:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}]
wire [13:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64]
wire [13:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}]
wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73]
wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}]
wire [11:0] _gpa_hits_hit_mask_T_2 = {12{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}]
wire tlb_hit_if_not_gpa_miss = |real_hits; // @[package.scala:45:27]
wire tlb_hit = |_tlb_hit_T; // @[TLB.scala:611:{28,40}]
wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56]
wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}]
wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67]
wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}]
reg [6:0] state_vec_0; // @[Replacement.scala:305:17]
reg [2:0] state_reg_1; // @[Replacement.scala:168:70]
wire [1:0] _GEN_73 = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45]
wire [1:0] lo_lo; // @[OneHot.scala:21:45]
assign lo_lo = _GEN_73; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_lo_lo; // @[OneHot.scala:21:45]
assign r_sectored_hit_bits_lo_lo = _GEN_73; // @[OneHot.scala:21:45]
wire [1:0] _GEN_74 = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45]
wire [1:0] lo_hi; // @[OneHot.scala:21:45]
assign lo_hi = _GEN_74; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_lo_hi; // @[OneHot.scala:21:45]
assign r_sectored_hit_bits_lo_hi = _GEN_74; // @[OneHot.scala:21:45]
wire [3:0] lo = {lo_hi, lo_lo}; // @[OneHot.scala:21:45]
wire [3:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18]
wire [1:0] _GEN_75 = {sector_hits_5, sector_hits_4}; // @[OneHot.scala:21:45]
wire [1:0] hi_lo; // @[OneHot.scala:21:45]
assign hi_lo = _GEN_75; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_hi_lo; // @[OneHot.scala:21:45]
assign r_sectored_hit_bits_hi_lo = _GEN_75; // @[OneHot.scala:21:45]
wire [1:0] _GEN_76 = {sector_hits_7, sector_hits_6}; // @[OneHot.scala:21:45]
wire [1:0] hi_hi; // @[OneHot.scala:21:45]
assign hi_hi = _GEN_76; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_hi_hi; // @[OneHot.scala:21:45]
assign r_sectored_hit_bits_hi_hi = _GEN_76; // @[OneHot.scala:21:45]
wire [3:0] hi = {hi_hi, hi_lo}; // @[OneHot.scala:21:45]
wire [3:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18]
wire [3:0] _T_33 = hi_1 | lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] hi_2 = _T_33[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] lo_2 = _T_33[1:0]; // @[OneHot.scala:31:18, :32:28]
wire [2:0] state_vec_0_touch_way_sized = {|hi_1, |hi_2, hi_2[1] | lo_2[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire _state_vec_0_set_left_older_T = state_vec_0_touch_way_sized[2]; // @[package.scala:163:13]
wire state_vec_0_set_left_older = ~_state_vec_0_set_left_older_T; // @[Replacement.scala:196:{33,43}]
wire [2:0] state_vec_0_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13]
wire [2:0] r_sectored_repl_addr_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13]
wire [2:0] state_vec_0_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :305:17]
wire [2:0] r_sectored_repl_addr_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :245:38, :305:17]
wire [1:0] _state_vec_0_T = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13]
wire [1:0] _state_vec_0_T_11 = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13]
wire _state_vec_0_set_left_older_T_1 = _state_vec_0_T[1]; // @[package.scala:163:13]
wire state_vec_0_set_left_older_1 = ~_state_vec_0_set_left_older_T_1; // @[Replacement.scala:196:{33,43}]
wire state_vec_0_left_subtree_state_1 = state_vec_0_left_subtree_state[1]; // @[package.scala:163:13]
wire state_vec_0_right_subtree_state_1 = state_vec_0_left_subtree_state[0]; // @[package.scala:163:13]
wire _state_vec_0_T_1 = _state_vec_0_T[0]; // @[package.scala:163:13]
wire _state_vec_0_T_5 = _state_vec_0_T[0]; // @[package.scala:163:13]
wire _state_vec_0_T_2 = _state_vec_0_T_1; // @[package.scala:163:13]
wire _state_vec_0_T_3 = ~_state_vec_0_T_2; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_4 = state_vec_0_set_left_older_1 ? state_vec_0_left_subtree_state_1 : _state_vec_0_T_3; // @[package.scala:163:13]
wire _state_vec_0_T_6 = _state_vec_0_T_5; // @[Replacement.scala:207:62, :218:17]
wire _state_vec_0_T_7 = ~_state_vec_0_T_6; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_8 = state_vec_0_set_left_older_1 ? _state_vec_0_T_7 : state_vec_0_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_vec_0_hi = {state_vec_0_set_left_older_1, _state_vec_0_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_vec_0_T_9 = {state_vec_0_hi, _state_vec_0_T_8}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_vec_0_T_10 = state_vec_0_set_left_older ? state_vec_0_left_subtree_state : _state_vec_0_T_9; // @[package.scala:163:13]
wire _state_vec_0_set_left_older_T_2 = _state_vec_0_T_11[1]; // @[Replacement.scala:196:43, :207:62]
wire state_vec_0_set_left_older_2 = ~_state_vec_0_set_left_older_T_2; // @[Replacement.scala:196:{33,43}]
wire state_vec_0_left_subtree_state_2 = state_vec_0_right_subtree_state[1]; // @[package.scala:163:13]
wire state_vec_0_right_subtree_state_2 = state_vec_0_right_subtree_state[0]; // @[Replacement.scala:198:38]
wire _state_vec_0_T_12 = _state_vec_0_T_11[0]; // @[package.scala:163:13]
wire _state_vec_0_T_16 = _state_vec_0_T_11[0]; // @[package.scala:163:13]
wire _state_vec_0_T_13 = _state_vec_0_T_12; // @[package.scala:163:13]
wire _state_vec_0_T_14 = ~_state_vec_0_T_13; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_15 = state_vec_0_set_left_older_2 ? state_vec_0_left_subtree_state_2 : _state_vec_0_T_14; // @[package.scala:163:13]
wire _state_vec_0_T_17 = _state_vec_0_T_16; // @[Replacement.scala:207:62, :218:17]
wire _state_vec_0_T_18 = ~_state_vec_0_T_17; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_19 = state_vec_0_set_left_older_2 ? _state_vec_0_T_18 : state_vec_0_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_vec_0_hi_1 = {state_vec_0_set_left_older_2, _state_vec_0_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_vec_0_T_20 = {state_vec_0_hi_1, _state_vec_0_T_19}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_vec_0_T_21 = state_vec_0_set_left_older ? _state_vec_0_T_20 : state_vec_0_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16]
wire [3:0] state_vec_0_hi_2 = {state_vec_0_set_left_older, _state_vec_0_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [6:0] _state_vec_0_T_22 = {state_vec_0_hi_2, _state_vec_0_T_21}; // @[Replacement.scala:202:12, :206:16]
wire [1:0] _GEN_77 = {superpage_hits_1, superpage_hits_0}; // @[OneHot.scala:21:45]
wire [1:0] lo_3; // @[OneHot.scala:21:45]
assign lo_3 = _GEN_77; // @[OneHot.scala:21:45]
wire [1:0] r_superpage_hit_bits_lo; // @[OneHot.scala:21:45]
assign r_superpage_hit_bits_lo = _GEN_77; // @[OneHot.scala:21:45]
wire [1:0] lo_4 = lo_3; // @[OneHot.scala:21:45, :31:18]
wire [1:0] _GEN_78 = {superpage_hits_3, superpage_hits_2}; // @[OneHot.scala:21:45]
wire [1:0] hi_3; // @[OneHot.scala:21:45]
assign hi_3 = _GEN_78; // @[OneHot.scala:21:45]
wire [1:0] r_superpage_hit_bits_hi; // @[OneHot.scala:21:45]
assign r_superpage_hit_bits_hi = _GEN_78; // @[OneHot.scala:21:45]
wire [1:0] hi_4 = hi_3; // @[OneHot.scala:21:45, :30:18]
wire [1:0] state_reg_touch_way_sized = {|hi_4, hi_4[1] | lo_4[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire _state_reg_set_left_older_T = state_reg_touch_way_sized[1]; // @[package.scala:163:13]
wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13]
wire r_superpage_repl_addr_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38]
wire r_superpage_repl_addr_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38, :245:38]
wire _state_reg_T = state_reg_touch_way_sized[0]; // @[package.scala:163:13]
wire _state_reg_T_4 = state_reg_touch_way_sized[0]; // @[package.scala:163:13]
wire _state_reg_T_1 = _state_reg_T; // @[package.scala:163:13]
wire _state_reg_T_2 = ~_state_reg_T_1; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_3 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_2; // @[package.scala:163:13]
wire _state_reg_T_5 = _state_reg_T_4; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_6 = ~_state_reg_T_5; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_7 = state_reg_set_left_older ? _state_reg_T_6 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi = {state_reg_set_left_older, _state_reg_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_8 = {state_reg_hi, _state_reg_T_7}; // @[Replacement.scala:202:12, :206:16]
wire [5:0] _multipleHits_T = real_hits[5:0]; // @[package.scala:45:27]
wire [2:0] _multipleHits_T_1 = _multipleHits_T[2:0]; // @[Misc.scala:181:37]
wire _multipleHits_T_2 = _multipleHits_T_1[0]; // @[Misc.scala:181:37]
wire multipleHits_leftOne = _multipleHits_T_2; // @[Misc.scala:178:18, :181:37]
wire [1:0] _multipleHits_T_3 = _multipleHits_T_1[2:1]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_4 = _multipleHits_T_3[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_1 = _multipleHits_T_4; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_5 = _multipleHits_T_3[1]; // @[Misc.scala:182:39]
wire multipleHits_rightOne = _multipleHits_T_5; // @[Misc.scala:178:18, :182:39]
wire multipleHits_rightOne_1 = multipleHits_leftOne_1 | multipleHits_rightOne; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_7 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61]
wire multipleHits_rightTwo = _multipleHits_T_7; // @[Misc.scala:183:{49,61}]
wire _multipleHits_T_8 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}]
wire multipleHits_leftOne_2 = multipleHits_leftOne | multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_9 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}]
wire multipleHits_leftTwo = _multipleHits_T_8 | _multipleHits_T_9; // @[Misc.scala:183:{37,49,61}]
wire [2:0] _multipleHits_T_10 = _multipleHits_T[5:3]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_11 = _multipleHits_T_10[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_3 = _multipleHits_T_11; // @[Misc.scala:178:18, :181:37]
wire [1:0] _multipleHits_T_12 = _multipleHits_T_10[2:1]; // @[Misc.scala:182:39]
wire _multipleHits_T_13 = _multipleHits_T_12[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_4 = _multipleHits_T_13; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_14 = _multipleHits_T_12[1]; // @[Misc.scala:182:39]
wire multipleHits_rightOne_2 = _multipleHits_T_14; // @[Misc.scala:178:18, :182:39]
wire multipleHits_rightOne_3 = multipleHits_leftOne_4 | multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_16 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61]
wire multipleHits_rightTwo_1 = _multipleHits_T_16; // @[Misc.scala:183:{49,61}]
wire _multipleHits_T_17 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}]
wire multipleHits_rightOne_4 = multipleHits_leftOne_3 | multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_18 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}]
wire multipleHits_rightTwo_2 = _multipleHits_T_17 | _multipleHits_T_18; // @[Misc.scala:183:{37,49,61}]
wire multipleHits_leftOne_5 = multipleHits_leftOne_2 | multipleHits_rightOne_4; // @[Misc.scala:183:16]
wire _multipleHits_T_19 = multipleHits_leftTwo | multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}]
wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}]
wire multipleHits_leftTwo_1 = _multipleHits_T_19 | _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}]
wire [6:0] _multipleHits_T_21 = real_hits[12:6]; // @[package.scala:45:27]
wire [2:0] _multipleHits_T_22 = _multipleHits_T_21[2:0]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_23 = _multipleHits_T_22[0]; // @[Misc.scala:181:37]
wire multipleHits_leftOne_6 = _multipleHits_T_23; // @[Misc.scala:178:18, :181:37]
wire [1:0] _multipleHits_T_24 = _multipleHits_T_22[2:1]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_25 = _multipleHits_T_24[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_7 = _multipleHits_T_25; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_26 = _multipleHits_T_24[1]; // @[Misc.scala:182:39]
wire multipleHits_rightOne_5 = _multipleHits_T_26; // @[Misc.scala:178:18, :182:39]
wire multipleHits_rightOne_6 = multipleHits_leftOne_7 | multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_28 = multipleHits_leftOne_7 & multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:61]
wire multipleHits_rightTwo_3 = _multipleHits_T_28; // @[Misc.scala:183:{49,61}]
wire _multipleHits_T_29 = multipleHits_rightTwo_3; // @[Misc.scala:183:{37,49}]
wire multipleHits_leftOne_8 = multipleHits_leftOne_6 | multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_30 = multipleHits_leftOne_6 & multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:{16,61}]
wire multipleHits_leftTwo_2 = _multipleHits_T_29 | _multipleHits_T_30; // @[Misc.scala:183:{37,49,61}]
wire [3:0] _multipleHits_T_31 = _multipleHits_T_21[6:3]; // @[Misc.scala:182:39]
wire [1:0] _multipleHits_T_32 = _multipleHits_T_31[1:0]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_33 = _multipleHits_T_32[0]; // @[Misc.scala:181:37]
wire multipleHits_leftOne_9 = _multipleHits_T_33; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_34 = _multipleHits_T_32[1]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_rightOne_7 = _multipleHits_T_34; // @[Misc.scala:178:18, :182:39]
wire multipleHits_leftOne_10 = multipleHits_leftOne_9 | multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_36 = multipleHits_leftOne_9 & multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:61]
wire multipleHits_leftTwo_3 = _multipleHits_T_36; // @[Misc.scala:183:{49,61}]
wire [1:0] _multipleHits_T_37 = _multipleHits_T_31[3:2]; // @[Misc.scala:182:39]
wire _multipleHits_T_38 = _multipleHits_T_37[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_11 = _multipleHits_T_38; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_39 = _multipleHits_T_37[1]; // @[Misc.scala:182:39]
wire multipleHits_rightOne_8 = _multipleHits_T_39; // @[Misc.scala:178:18, :182:39]
wire multipleHits_rightOne_9 = multipleHits_leftOne_11 | multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_41 = multipleHits_leftOne_11 & multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:61]
wire multipleHits_rightTwo_4 = _multipleHits_T_41; // @[Misc.scala:183:{49,61}]
wire multipleHits_rightOne_10 = multipleHits_leftOne_10 | multipleHits_rightOne_9; // @[Misc.scala:183:16]
wire _multipleHits_T_42 = multipleHits_leftTwo_3 | multipleHits_rightTwo_4; // @[Misc.scala:183:{37,49}]
wire _multipleHits_T_43 = multipleHits_leftOne_10 & multipleHits_rightOne_9; // @[Misc.scala:183:{16,61}]
wire multipleHits_rightTwo_5 = _multipleHits_T_42 | _multipleHits_T_43; // @[Misc.scala:183:{37,49,61}]
wire multipleHits_rightOne_11 = multipleHits_leftOne_8 | multipleHits_rightOne_10; // @[Misc.scala:183:16]
wire _multipleHits_T_44 = multipleHits_leftTwo_2 | multipleHits_rightTwo_5; // @[Misc.scala:183:{37,49}]
wire _multipleHits_T_45 = multipleHits_leftOne_8 & multipleHits_rightOne_10; // @[Misc.scala:183:{16,61}]
wire multipleHits_rightTwo_6 = _multipleHits_T_44 | _multipleHits_T_45; // @[Misc.scala:183:{37,49,61}]
wire _multipleHits_T_46 = multipleHits_leftOne_5 | multipleHits_rightOne_11; // @[Misc.scala:183:16]
wire _multipleHits_T_47 = multipleHits_leftTwo_1 | multipleHits_rightTwo_6; // @[Misc.scala:183:{37,49}]
wire _multipleHits_T_48 = multipleHits_leftOne_5 & multipleHits_rightOne_11; // @[Misc.scala:183:{16,61}]
wire multipleHits = _multipleHits_T_47 | _multipleHits_T_48; // @[Misc.scala:183:{37,49,61}]
assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25]
assign io_req_ready_0 = _io_req_ready_T; // @[TLB.scala:318:7, :631:25]
wire _io_resp_pf_ld_T = bad_va & cmd_read; // @[TLB.scala:568:34, :633:28]
wire [13:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57]
wire _io_resp_pf_ld_T_2 = |_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}]
assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T | _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}]
assign io_resp_pf_ld_0 = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41]
wire _io_resp_pf_st_T = bad_va & cmd_write_perms; // @[TLB.scala:568:34, :577:35, :634:28]
wire [13:0] _io_resp_pf_st_T_1 = pf_st_array & hits; // @[TLB.scala:442:17, :598:24, :634:64]
wire _io_resp_pf_st_T_2 = |_io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}]
assign _io_resp_pf_st_T_3 = _io_resp_pf_st_T | _io_resp_pf_st_T_2; // @[TLB.scala:634:{28,48,72}]
assign io_resp_pf_st_0 = _io_resp_pf_st_T_3; // @[TLB.scala:318:7, :634:48]
wire [13:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47]
wire _io_resp_pf_inst_T_1 = |_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}]
assign _io_resp_pf_inst_T_2 = bad_va | _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}]
assign io_resp_pf_inst_0 = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29]
wire [13:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33]
assign _io_resp_ae_ld_T_1 = |_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}]
assign io_resp_ae_ld_0 = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41]
wire [13:0] _io_resp_ae_st_T = ae_st_array & hits; // @[TLB.scala:442:17, :590:53, :642:33]
assign _io_resp_ae_st_T_1 = |_io_resp_ae_st_T; // @[TLB.scala:642:{33,41}]
assign io_resp_ae_st_0 = _io_resp_ae_st_T_1; // @[TLB.scala:318:7, :642:41]
wire [13:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23]
wire [13:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}]
assign _io_resp_ae_inst_T_2 = |_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}]
assign io_resp_ae_inst_0 = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41]
assign _io_resp_ma_ld_T = misaligned & cmd_read; // @[TLB.scala:550:77, :645:31]
assign io_resp_ma_ld_0 = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31]
assign _io_resp_ma_st_T = misaligned & cmd_write; // @[TLB.scala:550:77, :646:31]
assign io_resp_ma_st_0 = _io_resp_ma_st_T; // @[TLB.scala:318:7, :646:31]
wire [13:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33]
assign _io_resp_cacheable_T_1 = |_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}]
assign io_resp_cacheable_0 = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41]
wire [13:0] _io_resp_must_alloc_T = must_alloc_array & hits; // @[TLB.scala:442:17, :595:46, :649:43]
assign _io_resp_must_alloc_T_1 = |_io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}]
assign io_resp_must_alloc_0 = _io_resp_must_alloc_T_1; // @[TLB.scala:318:7, :649:51]
wire [13:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47]
wire _io_resp_prefetchable_T_1 = |_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}]
assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}]
assign io_resp_prefetchable_0 = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59]
wire _io_resp_miss_T_1 = _io_resp_miss_T | tlb_miss; // @[TLB.scala:613:64, :651:{29,52}]
assign _io_resp_miss_T_2 = _io_resp_miss_T_1 | multipleHits; // @[Misc.scala:183:49]
assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64]
assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73]
assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23]
wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36]
wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}]
wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58]
wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47]
wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}]
assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8]
assign io_resp_gpa_0 = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8]
assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29]
wire r_superpage_repl_addr_left_subtree_older = state_reg_1[2]; // @[Replacement.scala:168:70, :243:38]
wire _r_superpage_repl_addr_T = r_superpage_repl_addr_left_subtree_state; // @[package.scala:163:13]
wire _r_superpage_repl_addr_T_1 = r_superpage_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12]
wire _r_superpage_repl_addr_T_2 = r_superpage_repl_addr_left_subtree_older ? _r_superpage_repl_addr_T : _r_superpage_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_superpage_repl_addr_T_3 = {r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [1:0] r_superpage_repl_addr_valids_lo = {superpage_entries_1_valid_0, superpage_entries_0_valid_0}; // @[package.scala:45:27]
wire [1:0] r_superpage_repl_addr_valids_hi = {superpage_entries_3_valid_0, superpage_entries_2_valid_0}; // @[package.scala:45:27]
wire [3:0] r_superpage_repl_addr_valids = {r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo}; // @[package.scala:45:27]
wire _r_superpage_repl_addr_T_4 = &r_superpage_repl_addr_valids; // @[package.scala:45:27]
wire [3:0] _r_superpage_repl_addr_T_5 = ~r_superpage_repl_addr_valids; // @[package.scala:45:27]
wire _r_superpage_repl_addr_T_6 = _r_superpage_repl_addr_T_5[0]; // @[OneHot.scala:48:45]
wire _r_superpage_repl_addr_T_7 = _r_superpage_repl_addr_T_5[1]; // @[OneHot.scala:48:45]
wire _r_superpage_repl_addr_T_8 = _r_superpage_repl_addr_T_5[2]; // @[OneHot.scala:48:45]
wire _r_superpage_repl_addr_T_9 = _r_superpage_repl_addr_T_5[3]; // @[OneHot.scala:48:45]
wire [1:0] _r_superpage_repl_addr_T_10 = {1'h1, ~_r_superpage_repl_addr_T_8}; // @[OneHot.scala:48:45]
wire [1:0] _r_superpage_repl_addr_T_11 = _r_superpage_repl_addr_T_7 ? 2'h1 : _r_superpage_repl_addr_T_10; // @[OneHot.scala:48:45]
wire [1:0] _r_superpage_repl_addr_T_12 = _r_superpage_repl_addr_T_6 ? 2'h0 : _r_superpage_repl_addr_T_11; // @[OneHot.scala:48:45]
wire [1:0] _r_superpage_repl_addr_T_13 = _r_superpage_repl_addr_T_4 ? _r_superpage_repl_addr_T_3 : _r_superpage_repl_addr_T_12; // @[Mux.scala:50:70]
wire r_sectored_repl_addr_left_subtree_older = state_vec_0[6]; // @[Replacement.scala:243:38, :305:17]
wire r_sectored_repl_addr_left_subtree_older_1 = r_sectored_repl_addr_left_subtree_state[2]; // @[package.scala:163:13]
wire r_sectored_repl_addr_left_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[1]; // @[package.scala:163:13]
wire _r_sectored_repl_addr_T = r_sectored_repl_addr_left_subtree_state_1; // @[package.scala:163:13]
wire r_sectored_repl_addr_right_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[0]; // @[package.scala:163:13]
wire _r_sectored_repl_addr_T_1 = r_sectored_repl_addr_right_subtree_state_1; // @[Replacement.scala:245:38, :262:12]
wire _r_sectored_repl_addr_T_2 = r_sectored_repl_addr_left_subtree_older_1 ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_sectored_repl_addr_T_3 = {r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire r_sectored_repl_addr_left_subtree_older_2 = r_sectored_repl_addr_right_subtree_state[2]; // @[Replacement.scala:243:38, :245:38]
wire r_sectored_repl_addr_left_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[1]; // @[package.scala:163:13]
wire _r_sectored_repl_addr_T_4 = r_sectored_repl_addr_left_subtree_state_2; // @[package.scala:163:13]
wire r_sectored_repl_addr_right_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[0]; // @[Replacement.scala:245:38]
wire _r_sectored_repl_addr_T_5 = r_sectored_repl_addr_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12]
wire _r_sectored_repl_addr_T_6 = r_sectored_repl_addr_left_subtree_older_2 ? _r_sectored_repl_addr_T_4 : _r_sectored_repl_addr_T_5; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_sectored_repl_addr_T_7 = {r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [1:0] _r_sectored_repl_addr_T_8 = r_sectored_repl_addr_left_subtree_older ? _r_sectored_repl_addr_T_3 : _r_sectored_repl_addr_T_7; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [2:0] _r_sectored_repl_addr_T_9 = {r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire _r_sectored_repl_addr_valids_T_1 = _r_sectored_repl_addr_valids_T | sectored_entries_0_0_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_2 = _r_sectored_repl_addr_valids_T_1 | sectored_entries_0_0_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_4 = _r_sectored_repl_addr_valids_T_3 | sectored_entries_0_1_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_5 = _r_sectored_repl_addr_valids_T_4 | sectored_entries_0_1_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_7 = _r_sectored_repl_addr_valids_T_6 | sectored_entries_0_2_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_8 = _r_sectored_repl_addr_valids_T_7 | sectored_entries_0_2_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_10 = _r_sectored_repl_addr_valids_T_9 | sectored_entries_0_3_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_11 = _r_sectored_repl_addr_valids_T_10 | sectored_entries_0_3_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_13 = _r_sectored_repl_addr_valids_T_12 | sectored_entries_0_4_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_14 = _r_sectored_repl_addr_valids_T_13 | sectored_entries_0_4_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_16 = _r_sectored_repl_addr_valids_T_15 | sectored_entries_0_5_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_17 = _r_sectored_repl_addr_valids_T_16 | sectored_entries_0_5_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_19 = _r_sectored_repl_addr_valids_T_18 | sectored_entries_0_6_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_20 = _r_sectored_repl_addr_valids_T_19 | sectored_entries_0_6_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_22 = _r_sectored_repl_addr_valids_T_21 | sectored_entries_0_7_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_23 = _r_sectored_repl_addr_valids_T_22 | sectored_entries_0_7_valid_3; // @[package.scala:81:59]
wire [1:0] r_sectored_repl_addr_valids_lo_lo = {_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2}; // @[package.scala:45:27, :81:59]
wire [1:0] r_sectored_repl_addr_valids_lo_hi = {_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8}; // @[package.scala:45:27, :81:59]
wire [3:0] r_sectored_repl_addr_valids_lo = {r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo}; // @[package.scala:45:27]
wire [1:0] r_sectored_repl_addr_valids_hi_lo = {_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14}; // @[package.scala:45:27, :81:59]
wire [1:0] r_sectored_repl_addr_valids_hi_hi = {_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20}; // @[package.scala:45:27, :81:59]
wire [3:0] r_sectored_repl_addr_valids_hi = {r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo}; // @[package.scala:45:27]
wire [7:0] r_sectored_repl_addr_valids = {r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo}; // @[package.scala:45:27]
wire _r_sectored_repl_addr_T_10 = &r_sectored_repl_addr_valids; // @[package.scala:45:27]
wire [7:0] _r_sectored_repl_addr_T_11 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27]
wire _r_sectored_repl_addr_T_12 = _r_sectored_repl_addr_T_11[0]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_13 = _r_sectored_repl_addr_T_11[1]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_14 = _r_sectored_repl_addr_T_11[2]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_15 = _r_sectored_repl_addr_T_11[3]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_16 = _r_sectored_repl_addr_T_11[4]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_17 = _r_sectored_repl_addr_T_11[5]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_18 = _r_sectored_repl_addr_T_11[6]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_19 = _r_sectored_repl_addr_T_11[7]; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_20 = {2'h3, ~_r_sectored_repl_addr_T_18}; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_21 = _r_sectored_repl_addr_T_17 ? 3'h5 : _r_sectored_repl_addr_T_20; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_22 = _r_sectored_repl_addr_T_16 ? 3'h4 : _r_sectored_repl_addr_T_21; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_23 = _r_sectored_repl_addr_T_15 ? 3'h3 : _r_sectored_repl_addr_T_22; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_24 = _r_sectored_repl_addr_T_14 ? 3'h2 : _r_sectored_repl_addr_T_23; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_25 = _r_sectored_repl_addr_T_13 ? 3'h1 : _r_sectored_repl_addr_T_24; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_26 = _r_sectored_repl_addr_T_12 ? 3'h0 : _r_sectored_repl_addr_T_25; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_27 = _r_sectored_repl_addr_T_10 ? _r_sectored_repl_addr_T_9 : _r_sectored_repl_addr_T_26; // @[Mux.scala:50:70]
wire _r_sectored_hit_valid_T = sector_hits_0 | sector_hits_1; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_1 = _r_sectored_hit_valid_T | sector_hits_2; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_2 = _r_sectored_hit_valid_T_1 | sector_hits_3; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_3 = _r_sectored_hit_valid_T_2 | sector_hits_4; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_4 = _r_sectored_hit_valid_T_3 | sector_hits_5; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_5 = _r_sectored_hit_valid_T_4 | sector_hits_6; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_6 = _r_sectored_hit_valid_T_5 | sector_hits_7; // @[package.scala:81:59]
wire [3:0] r_sectored_hit_bits_lo = {r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo}; // @[OneHot.scala:21:45]
wire [3:0] r_sectored_hit_bits_hi = {r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo}; // @[OneHot.scala:21:45]
wire [7:0] _r_sectored_hit_bits_T = {r_sectored_hit_bits_hi, r_sectored_hit_bits_lo}; // @[OneHot.scala:21:45]
wire [3:0] r_sectored_hit_bits_hi_1 = _r_sectored_hit_bits_T[7:4]; // @[OneHot.scala:21:45, :30:18]
wire [3:0] r_sectored_hit_bits_lo_1 = _r_sectored_hit_bits_T[3:0]; // @[OneHot.scala:21:45, :31:18]
wire _r_sectored_hit_bits_T_1 = |r_sectored_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _r_sectored_hit_bits_T_2 = r_sectored_hit_bits_hi_1 | r_sectored_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] r_sectored_hit_bits_hi_2 = _r_sectored_hit_bits_T_2[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] r_sectored_hit_bits_lo_2 = _r_sectored_hit_bits_T_2[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _r_sectored_hit_bits_T_3 = |r_sectored_hit_bits_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _r_sectored_hit_bits_T_4 = r_sectored_hit_bits_hi_2 | r_sectored_hit_bits_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _r_sectored_hit_bits_T_5 = _r_sectored_hit_bits_T_4[1]; // @[OneHot.scala:32:28]
wire [1:0] _r_sectored_hit_bits_T_6 = {_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _r_sectored_hit_bits_T_7 = {_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6}; // @[OneHot.scala:32:{10,14}]
wire _r_superpage_hit_valid_T = superpage_hits_0 | superpage_hits_1; // @[package.scala:81:59]
wire _r_superpage_hit_valid_T_1 = _r_superpage_hit_valid_T | superpage_hits_2; // @[package.scala:81:59]
wire _r_superpage_hit_valid_T_2 = _r_superpage_hit_valid_T_1 | superpage_hits_3; // @[package.scala:81:59]
wire [3:0] _r_superpage_hit_bits_T = {r_superpage_hit_bits_hi, r_superpage_hit_bits_lo}; // @[OneHot.scala:21:45]
wire [1:0] r_superpage_hit_bits_hi_1 = _r_superpage_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18]
wire [1:0] r_superpage_hit_bits_lo_1 = _r_superpage_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18]
wire _r_superpage_hit_bits_T_1 = |r_superpage_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _r_superpage_hit_bits_T_2 = r_superpage_hit_bits_hi_1 | r_superpage_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _r_superpage_hit_bits_T_3 = _r_superpage_hit_bits_T_2[1]; // @[OneHot.scala:32:28]
wire [1:0] _r_superpage_hit_bits_T_4 = {_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}]
wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45] |
Generate the Verilog code corresponding to this FIRRTL code module Pipeline_1 :
input clock : Clock
input reset : Reset
output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { out : { bits : UInt<32>}[4], row : UInt<16>, last : UInt<1>, tag : { data : UInt<128>, addr : UInt<14>, mask : UInt<1>[16], is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<16>, len : UInt<16>, last : UInt<1>, bytes_read : UInt<8>, cmd_id : UInt<8>}}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { out : { bits : UInt<32>}[4], row : UInt<16>, last : UInt<1>, tag : { data : UInt<128>, addr : UInt<14>, mask : UInt<1>[16], is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<16>, len : UInt<16>, last : UInt<1>, bytes_read : UInt<8>, cmd_id : UInt<8>}}}, busy : UInt<1>}
reg stages : { out : { bits : UInt<32>}[4], row : UInt<16>, last : UInt<1>, tag : { data : UInt<128>, addr : UInt<14>, mask : UInt<1>[16], is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<16>, len : UInt<16>, last : UInt<1>, bytes_read : UInt<8>, cmd_id : UInt<8>}}[4], clock
wire _valids_WIRE : UInt<1>[4]
connect _valids_WIRE[0], UInt<1>(0h0)
connect _valids_WIRE[1], UInt<1>(0h0)
connect _valids_WIRE[2], UInt<1>(0h0)
connect _valids_WIRE[3], UInt<1>(0h0)
regreset valids : UInt<1>[4], clock, reset, _valids_WIRE
wire stalling : UInt<1>[4]
connect stalling[0], UInt<1>(0h0)
connect stalling[1], UInt<1>(0h0)
connect stalling[2], UInt<1>(0h0)
connect stalling[3], UInt<1>(0h0)
node _io_busy_T = or(valids[0], valids[1])
node _io_busy_T_1 = or(_io_busy_T, valids[2])
node _io_busy_T_2 = or(_io_busy_T_1, valids[3])
node _io_busy_T_3 = or(io.in.valid, _io_busy_T_2)
connect io.busy, _io_busy_T_3
node _io_in_ready_T = eq(stalling[0], UInt<1>(0h0))
connect io.in.ready, _io_in_ready_T
node _stalling_3_T = eq(io.out.ready, UInt<1>(0h0))
node _stalling_3_T_1 = and(valids[3], _stalling_3_T)
connect stalling[3], _stalling_3_T_1
node _stalling_0_T = and(valids[0], stalling[1])
connect stalling[0], _stalling_0_T
node _stalling_1_T = and(valids[1], stalling[2])
connect stalling[1], _stalling_1_T
node _stalling_2_T = and(valids[2], stalling[3])
connect stalling[2], _stalling_2_T
connect io.out.valid, valids[3]
when io.out.ready :
connect valids[3], UInt<1>(0h0)
node _T = eq(stalling[1], UInt<1>(0h0))
when _T :
connect valids[0], UInt<1>(0h0)
node _T_1 = eq(stalling[2], UInt<1>(0h0))
when _T_1 :
connect valids[1], UInt<1>(0h0)
node _T_2 = eq(stalling[3], UInt<1>(0h0))
when _T_2 :
connect valids[2], UInt<1>(0h0)
node _T_3 = and(io.in.ready, io.in.valid)
when _T_3 :
connect valids[0], UInt<1>(0h1)
when valids[0] :
connect valids[1], UInt<1>(0h1)
when valids[1] :
connect valids[2], UInt<1>(0h1)
when valids[2] :
connect valids[3], UInt<1>(0h1)
node _T_4 = and(io.in.ready, io.in.valid)
when _T_4 :
connect stages[0], io.in.bits
connect io.out.bits, stages[3]
node _T_5 = eq(stalling[1], UInt<1>(0h0))
when _T_5 :
connect stages[1], stages[0]
node _T_6 = eq(stalling[2], UInt<1>(0h0))
when _T_6 :
connect stages[2], stages[1]
node _T_7 = eq(stalling[3], UInt<1>(0h0))
when _T_7 :
connect stages[3], stages[2] | module Pipeline_1( // @[Pipeline.scala:6:7]
input clock, // @[Pipeline.scala:6:7]
input reset, // @[Pipeline.scala:6:7]
output io_in_ready, // @[Pipeline.scala:7:14]
input io_in_valid, // @[Pipeline.scala:7:14]
input [31:0] io_in_bits_out_0_bits, // @[Pipeline.scala:7:14]
input [31:0] io_in_bits_out_1_bits, // @[Pipeline.scala:7:14]
input [31:0] io_in_bits_out_2_bits, // @[Pipeline.scala:7:14]
input [31:0] io_in_bits_out_3_bits, // @[Pipeline.scala:7:14]
input [15:0] io_in_bits_row, // @[Pipeline.scala:7:14]
input io_in_bits_last, // @[Pipeline.scala:7:14]
input [127:0] io_in_bits_tag_data, // @[Pipeline.scala:7:14]
input [13:0] io_in_bits_tag_addr, // @[Pipeline.scala:7:14]
input io_in_bits_tag_mask_0, // @[Pipeline.scala:7:14]
input io_in_bits_tag_mask_1, // @[Pipeline.scala:7:14]
input io_in_bits_tag_mask_2, // @[Pipeline.scala:7:14]
input io_in_bits_tag_mask_3, // @[Pipeline.scala:7:14]
input io_in_bits_tag_mask_4, // @[Pipeline.scala:7:14]
input io_in_bits_tag_mask_5, // @[Pipeline.scala:7:14]
input io_in_bits_tag_mask_6, // @[Pipeline.scala:7:14]
input io_in_bits_tag_mask_7, // @[Pipeline.scala:7:14]
input io_in_bits_tag_mask_8, // @[Pipeline.scala:7:14]
input io_in_bits_tag_mask_9, // @[Pipeline.scala:7:14]
input io_in_bits_tag_mask_10, // @[Pipeline.scala:7:14]
input io_in_bits_tag_mask_11, // @[Pipeline.scala:7:14]
input io_in_bits_tag_mask_12, // @[Pipeline.scala:7:14]
input io_in_bits_tag_mask_13, // @[Pipeline.scala:7:14]
input io_in_bits_tag_mask_14, // @[Pipeline.scala:7:14]
input io_in_bits_tag_mask_15, // @[Pipeline.scala:7:14]
input io_in_bits_tag_is_acc, // @[Pipeline.scala:7:14]
input io_in_bits_tag_accumulate, // @[Pipeline.scala:7:14]
input io_in_bits_tag_has_acc_bitwidth, // @[Pipeline.scala:7:14]
input [31:0] io_in_bits_tag_scale, // @[Pipeline.scala:7:14]
input [15:0] io_in_bits_tag_repeats, // @[Pipeline.scala:7:14]
input [15:0] io_in_bits_tag_pixel_repeats, // @[Pipeline.scala:7:14]
input [15:0] io_in_bits_tag_len, // @[Pipeline.scala:7:14]
input io_in_bits_tag_last, // @[Pipeline.scala:7:14]
input [7:0] io_in_bits_tag_bytes_read, // @[Pipeline.scala:7:14]
input [7:0] io_in_bits_tag_cmd_id, // @[Pipeline.scala:7:14]
input io_out_ready, // @[Pipeline.scala:7:14]
output io_out_valid, // @[Pipeline.scala:7:14]
output [31:0] io_out_bits_out_0_bits, // @[Pipeline.scala:7:14]
output [31:0] io_out_bits_out_1_bits, // @[Pipeline.scala:7:14]
output [31:0] io_out_bits_out_2_bits, // @[Pipeline.scala:7:14]
output [31:0] io_out_bits_out_3_bits, // @[Pipeline.scala:7:14]
output [15:0] io_out_bits_row, // @[Pipeline.scala:7:14]
output io_out_bits_last, // @[Pipeline.scala:7:14]
output [127:0] io_out_bits_tag_data, // @[Pipeline.scala:7:14]
output [13:0] io_out_bits_tag_addr, // @[Pipeline.scala:7:14]
output io_out_bits_tag_mask_0, // @[Pipeline.scala:7:14]
output io_out_bits_tag_mask_1, // @[Pipeline.scala:7:14]
output io_out_bits_tag_mask_2, // @[Pipeline.scala:7:14]
output io_out_bits_tag_mask_3, // @[Pipeline.scala:7:14]
output io_out_bits_tag_mask_4, // @[Pipeline.scala:7:14]
output io_out_bits_tag_mask_5, // @[Pipeline.scala:7:14]
output io_out_bits_tag_mask_6, // @[Pipeline.scala:7:14]
output io_out_bits_tag_mask_7, // @[Pipeline.scala:7:14]
output io_out_bits_tag_mask_8, // @[Pipeline.scala:7:14]
output io_out_bits_tag_mask_9, // @[Pipeline.scala:7:14]
output io_out_bits_tag_mask_10, // @[Pipeline.scala:7:14]
output io_out_bits_tag_mask_11, // @[Pipeline.scala:7:14]
output io_out_bits_tag_mask_12, // @[Pipeline.scala:7:14]
output io_out_bits_tag_mask_13, // @[Pipeline.scala:7:14]
output io_out_bits_tag_mask_14, // @[Pipeline.scala:7:14]
output io_out_bits_tag_mask_15, // @[Pipeline.scala:7:14]
output io_out_bits_tag_is_acc, // @[Pipeline.scala:7:14]
output io_out_bits_tag_accumulate, // @[Pipeline.scala:7:14]
output io_out_bits_tag_has_acc_bitwidth, // @[Pipeline.scala:7:14]
output [31:0] io_out_bits_tag_scale, // @[Pipeline.scala:7:14]
output [15:0] io_out_bits_tag_repeats, // @[Pipeline.scala:7:14]
output [15:0] io_out_bits_tag_pixel_repeats, // @[Pipeline.scala:7:14]
output [15:0] io_out_bits_tag_len, // @[Pipeline.scala:7:14]
output io_out_bits_tag_last, // @[Pipeline.scala:7:14]
output [7:0] io_out_bits_tag_bytes_read, // @[Pipeline.scala:7:14]
output [7:0] io_out_bits_tag_cmd_id // @[Pipeline.scala:7:14]
);
wire io_in_valid_0 = io_in_valid; // @[Pipeline.scala:6:7]
wire [31:0] io_in_bits_out_0_bits_0 = io_in_bits_out_0_bits; // @[Pipeline.scala:6:7]
wire [31:0] io_in_bits_out_1_bits_0 = io_in_bits_out_1_bits; // @[Pipeline.scala:6:7]
wire [31:0] io_in_bits_out_2_bits_0 = io_in_bits_out_2_bits; // @[Pipeline.scala:6:7]
wire [31:0] io_in_bits_out_3_bits_0 = io_in_bits_out_3_bits; // @[Pipeline.scala:6:7]
wire [15:0] io_in_bits_row_0 = io_in_bits_row; // @[Pipeline.scala:6:7]
wire io_in_bits_last_0 = io_in_bits_last; // @[Pipeline.scala:6:7]
wire [127:0] io_in_bits_tag_data_0 = io_in_bits_tag_data; // @[Pipeline.scala:6:7]
wire [13:0] io_in_bits_tag_addr_0 = io_in_bits_tag_addr; // @[Pipeline.scala:6:7]
wire io_in_bits_tag_mask_0_0 = io_in_bits_tag_mask_0; // @[Pipeline.scala:6:7]
wire io_in_bits_tag_mask_1_0 = io_in_bits_tag_mask_1; // @[Pipeline.scala:6:7]
wire io_in_bits_tag_mask_2_0 = io_in_bits_tag_mask_2; // @[Pipeline.scala:6:7]
wire io_in_bits_tag_mask_3_0 = io_in_bits_tag_mask_3; // @[Pipeline.scala:6:7]
wire io_in_bits_tag_mask_4_0 = io_in_bits_tag_mask_4; // @[Pipeline.scala:6:7]
wire io_in_bits_tag_mask_5_0 = io_in_bits_tag_mask_5; // @[Pipeline.scala:6:7]
wire io_in_bits_tag_mask_6_0 = io_in_bits_tag_mask_6; // @[Pipeline.scala:6:7]
wire io_in_bits_tag_mask_7_0 = io_in_bits_tag_mask_7; // @[Pipeline.scala:6:7]
wire io_in_bits_tag_mask_8_0 = io_in_bits_tag_mask_8; // @[Pipeline.scala:6:7]
wire io_in_bits_tag_mask_9_0 = io_in_bits_tag_mask_9; // @[Pipeline.scala:6:7]
wire io_in_bits_tag_mask_10_0 = io_in_bits_tag_mask_10; // @[Pipeline.scala:6:7]
wire io_in_bits_tag_mask_11_0 = io_in_bits_tag_mask_11; // @[Pipeline.scala:6:7]
wire io_in_bits_tag_mask_12_0 = io_in_bits_tag_mask_12; // @[Pipeline.scala:6:7]
wire io_in_bits_tag_mask_13_0 = io_in_bits_tag_mask_13; // @[Pipeline.scala:6:7]
wire io_in_bits_tag_mask_14_0 = io_in_bits_tag_mask_14; // @[Pipeline.scala:6:7]
wire io_in_bits_tag_mask_15_0 = io_in_bits_tag_mask_15; // @[Pipeline.scala:6:7]
wire io_in_bits_tag_is_acc_0 = io_in_bits_tag_is_acc; // @[Pipeline.scala:6:7]
wire io_in_bits_tag_accumulate_0 = io_in_bits_tag_accumulate; // @[Pipeline.scala:6:7]
wire io_in_bits_tag_has_acc_bitwidth_0 = io_in_bits_tag_has_acc_bitwidth; // @[Pipeline.scala:6:7]
wire [31:0] io_in_bits_tag_scale_0 = io_in_bits_tag_scale; // @[Pipeline.scala:6:7]
wire [15:0] io_in_bits_tag_repeats_0 = io_in_bits_tag_repeats; // @[Pipeline.scala:6:7]
wire [15:0] io_in_bits_tag_pixel_repeats_0 = io_in_bits_tag_pixel_repeats; // @[Pipeline.scala:6:7]
wire [15:0] io_in_bits_tag_len_0 = io_in_bits_tag_len; // @[Pipeline.scala:6:7]
wire io_in_bits_tag_last_0 = io_in_bits_tag_last; // @[Pipeline.scala:6:7]
wire [7:0] io_in_bits_tag_bytes_read_0 = io_in_bits_tag_bytes_read; // @[Pipeline.scala:6:7]
wire [7:0] io_in_bits_tag_cmd_id_0 = io_in_bits_tag_cmd_id; // @[Pipeline.scala:6:7]
wire io_out_ready_0 = io_out_ready; // @[Pipeline.scala:6:7]
wire _valids_WIRE_0 = 1'h0; // @[Pipeline.scala:22:33]
wire _valids_WIRE_1 = 1'h0; // @[Pipeline.scala:22:33]
wire _valids_WIRE_2 = 1'h0; // @[Pipeline.scala:22:33]
wire _valids_WIRE_3 = 1'h0; // @[Pipeline.scala:22:33]
wire _io_in_ready_T; // @[Pipeline.scala:27:20]
wire _io_busy_T_3; // @[Pipeline.scala:24:28]
wire io_in_ready_0; // @[Pipeline.scala:6:7]
wire [31:0] io_out_bits_out_0_bits_0; // @[Pipeline.scala:6:7]
wire [31:0] io_out_bits_out_1_bits_0; // @[Pipeline.scala:6:7]
wire [31:0] io_out_bits_out_2_bits_0; // @[Pipeline.scala:6:7]
wire [31:0] io_out_bits_out_3_bits_0; // @[Pipeline.scala:6:7]
wire io_out_bits_tag_mask_0_0; // @[Pipeline.scala:6:7]
wire io_out_bits_tag_mask_1_0; // @[Pipeline.scala:6:7]
wire io_out_bits_tag_mask_2_0; // @[Pipeline.scala:6:7]
wire io_out_bits_tag_mask_3_0; // @[Pipeline.scala:6:7]
wire io_out_bits_tag_mask_4_0; // @[Pipeline.scala:6:7]
wire io_out_bits_tag_mask_5_0; // @[Pipeline.scala:6:7]
wire io_out_bits_tag_mask_6_0; // @[Pipeline.scala:6:7]
wire io_out_bits_tag_mask_7_0; // @[Pipeline.scala:6:7]
wire io_out_bits_tag_mask_8_0; // @[Pipeline.scala:6:7]
wire io_out_bits_tag_mask_9_0; // @[Pipeline.scala:6:7]
wire io_out_bits_tag_mask_10_0; // @[Pipeline.scala:6:7]
wire io_out_bits_tag_mask_11_0; // @[Pipeline.scala:6:7]
wire io_out_bits_tag_mask_12_0; // @[Pipeline.scala:6:7]
wire io_out_bits_tag_mask_13_0; // @[Pipeline.scala:6:7]
wire io_out_bits_tag_mask_14_0; // @[Pipeline.scala:6:7]
wire io_out_bits_tag_mask_15_0; // @[Pipeline.scala:6:7]
wire [127:0] io_out_bits_tag_data_0; // @[Pipeline.scala:6:7]
wire [13:0] io_out_bits_tag_addr_0; // @[Pipeline.scala:6:7]
wire io_out_bits_tag_is_acc_0; // @[Pipeline.scala:6:7]
wire io_out_bits_tag_accumulate_0; // @[Pipeline.scala:6:7]
wire io_out_bits_tag_has_acc_bitwidth_0; // @[Pipeline.scala:6:7]
wire [31:0] io_out_bits_tag_scale_0; // @[Pipeline.scala:6:7]
wire [15:0] io_out_bits_tag_repeats_0; // @[Pipeline.scala:6:7]
wire [15:0] io_out_bits_tag_pixel_repeats_0; // @[Pipeline.scala:6:7]
wire [15:0] io_out_bits_tag_len_0; // @[Pipeline.scala:6:7]
wire io_out_bits_tag_last_0; // @[Pipeline.scala:6:7]
wire [7:0] io_out_bits_tag_bytes_read_0; // @[Pipeline.scala:6:7]
wire [7:0] io_out_bits_tag_cmd_id_0; // @[Pipeline.scala:6:7]
wire [15:0] io_out_bits_row_0; // @[Pipeline.scala:6:7]
wire io_out_bits_last_0; // @[Pipeline.scala:6:7]
wire io_out_valid_0; // @[Pipeline.scala:6:7]
wire io_busy; // @[Pipeline.scala:6:7]
reg [31:0] stages_0_out_0_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_0_out_1_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_0_out_2_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_0_out_3_bits; // @[Pipeline.scala:21:21]
reg [15:0] stages_0_row; // @[Pipeline.scala:21:21]
reg stages_0_last; // @[Pipeline.scala:21:21]
reg [127:0] stages_0_tag_data; // @[Pipeline.scala:21:21]
reg [13:0] stages_0_tag_addr; // @[Pipeline.scala:21:21]
reg stages_0_tag_mask_0; // @[Pipeline.scala:21:21]
reg stages_0_tag_mask_1; // @[Pipeline.scala:21:21]
reg stages_0_tag_mask_2; // @[Pipeline.scala:21:21]
reg stages_0_tag_mask_3; // @[Pipeline.scala:21:21]
reg stages_0_tag_mask_4; // @[Pipeline.scala:21:21]
reg stages_0_tag_mask_5; // @[Pipeline.scala:21:21]
reg stages_0_tag_mask_6; // @[Pipeline.scala:21:21]
reg stages_0_tag_mask_7; // @[Pipeline.scala:21:21]
reg stages_0_tag_mask_8; // @[Pipeline.scala:21:21]
reg stages_0_tag_mask_9; // @[Pipeline.scala:21:21]
reg stages_0_tag_mask_10; // @[Pipeline.scala:21:21]
reg stages_0_tag_mask_11; // @[Pipeline.scala:21:21]
reg stages_0_tag_mask_12; // @[Pipeline.scala:21:21]
reg stages_0_tag_mask_13; // @[Pipeline.scala:21:21]
reg stages_0_tag_mask_14; // @[Pipeline.scala:21:21]
reg stages_0_tag_mask_15; // @[Pipeline.scala:21:21]
reg stages_0_tag_is_acc; // @[Pipeline.scala:21:21]
reg stages_0_tag_accumulate; // @[Pipeline.scala:21:21]
reg stages_0_tag_has_acc_bitwidth; // @[Pipeline.scala:21:21]
reg [31:0] stages_0_tag_scale; // @[Pipeline.scala:21:21]
reg [15:0] stages_0_tag_repeats; // @[Pipeline.scala:21:21]
reg [15:0] stages_0_tag_pixel_repeats; // @[Pipeline.scala:21:21]
reg [15:0] stages_0_tag_len; // @[Pipeline.scala:21:21]
reg stages_0_tag_last; // @[Pipeline.scala:21:21]
reg [7:0] stages_0_tag_bytes_read; // @[Pipeline.scala:21:21]
reg [7:0] stages_0_tag_cmd_id; // @[Pipeline.scala:21:21]
reg [31:0] stages_1_out_0_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_1_out_1_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_1_out_2_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_1_out_3_bits; // @[Pipeline.scala:21:21]
reg [15:0] stages_1_row; // @[Pipeline.scala:21:21]
reg stages_1_last; // @[Pipeline.scala:21:21]
reg [127:0] stages_1_tag_data; // @[Pipeline.scala:21:21]
reg [13:0] stages_1_tag_addr; // @[Pipeline.scala:21:21]
reg stages_1_tag_mask_0; // @[Pipeline.scala:21:21]
reg stages_1_tag_mask_1; // @[Pipeline.scala:21:21]
reg stages_1_tag_mask_2; // @[Pipeline.scala:21:21]
reg stages_1_tag_mask_3; // @[Pipeline.scala:21:21]
reg stages_1_tag_mask_4; // @[Pipeline.scala:21:21]
reg stages_1_tag_mask_5; // @[Pipeline.scala:21:21]
reg stages_1_tag_mask_6; // @[Pipeline.scala:21:21]
reg stages_1_tag_mask_7; // @[Pipeline.scala:21:21]
reg stages_1_tag_mask_8; // @[Pipeline.scala:21:21]
reg stages_1_tag_mask_9; // @[Pipeline.scala:21:21]
reg stages_1_tag_mask_10; // @[Pipeline.scala:21:21]
reg stages_1_tag_mask_11; // @[Pipeline.scala:21:21]
reg stages_1_tag_mask_12; // @[Pipeline.scala:21:21]
reg stages_1_tag_mask_13; // @[Pipeline.scala:21:21]
reg stages_1_tag_mask_14; // @[Pipeline.scala:21:21]
reg stages_1_tag_mask_15; // @[Pipeline.scala:21:21]
reg stages_1_tag_is_acc; // @[Pipeline.scala:21:21]
reg stages_1_tag_accumulate; // @[Pipeline.scala:21:21]
reg stages_1_tag_has_acc_bitwidth; // @[Pipeline.scala:21:21]
reg [31:0] stages_1_tag_scale; // @[Pipeline.scala:21:21]
reg [15:0] stages_1_tag_repeats; // @[Pipeline.scala:21:21]
reg [15:0] stages_1_tag_pixel_repeats; // @[Pipeline.scala:21:21]
reg [15:0] stages_1_tag_len; // @[Pipeline.scala:21:21]
reg stages_1_tag_last; // @[Pipeline.scala:21:21]
reg [7:0] stages_1_tag_bytes_read; // @[Pipeline.scala:21:21]
reg [7:0] stages_1_tag_cmd_id; // @[Pipeline.scala:21:21]
reg [31:0] stages_2_out_0_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_2_out_1_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_2_out_2_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_2_out_3_bits; // @[Pipeline.scala:21:21]
reg [15:0] stages_2_row; // @[Pipeline.scala:21:21]
reg stages_2_last; // @[Pipeline.scala:21:21]
reg [127:0] stages_2_tag_data; // @[Pipeline.scala:21:21]
reg [13:0] stages_2_tag_addr; // @[Pipeline.scala:21:21]
reg stages_2_tag_mask_0; // @[Pipeline.scala:21:21]
reg stages_2_tag_mask_1; // @[Pipeline.scala:21:21]
reg stages_2_tag_mask_2; // @[Pipeline.scala:21:21]
reg stages_2_tag_mask_3; // @[Pipeline.scala:21:21]
reg stages_2_tag_mask_4; // @[Pipeline.scala:21:21]
reg stages_2_tag_mask_5; // @[Pipeline.scala:21:21]
reg stages_2_tag_mask_6; // @[Pipeline.scala:21:21]
reg stages_2_tag_mask_7; // @[Pipeline.scala:21:21]
reg stages_2_tag_mask_8; // @[Pipeline.scala:21:21]
reg stages_2_tag_mask_9; // @[Pipeline.scala:21:21]
reg stages_2_tag_mask_10; // @[Pipeline.scala:21:21]
reg stages_2_tag_mask_11; // @[Pipeline.scala:21:21]
reg stages_2_tag_mask_12; // @[Pipeline.scala:21:21]
reg stages_2_tag_mask_13; // @[Pipeline.scala:21:21]
reg stages_2_tag_mask_14; // @[Pipeline.scala:21:21]
reg stages_2_tag_mask_15; // @[Pipeline.scala:21:21]
reg stages_2_tag_is_acc; // @[Pipeline.scala:21:21]
reg stages_2_tag_accumulate; // @[Pipeline.scala:21:21]
reg stages_2_tag_has_acc_bitwidth; // @[Pipeline.scala:21:21]
reg [31:0] stages_2_tag_scale; // @[Pipeline.scala:21:21]
reg [15:0] stages_2_tag_repeats; // @[Pipeline.scala:21:21]
reg [15:0] stages_2_tag_pixel_repeats; // @[Pipeline.scala:21:21]
reg [15:0] stages_2_tag_len; // @[Pipeline.scala:21:21]
reg stages_2_tag_last; // @[Pipeline.scala:21:21]
reg [7:0] stages_2_tag_bytes_read; // @[Pipeline.scala:21:21]
reg [7:0] stages_2_tag_cmd_id; // @[Pipeline.scala:21:21]
reg [31:0] stages_3_out_0_bits; // @[Pipeline.scala:21:21]
assign io_out_bits_out_0_bits_0 = stages_3_out_0_bits; // @[Pipeline.scala:6:7, :21:21]
reg [31:0] stages_3_out_1_bits; // @[Pipeline.scala:21:21]
assign io_out_bits_out_1_bits_0 = stages_3_out_1_bits; // @[Pipeline.scala:6:7, :21:21]
reg [31:0] stages_3_out_2_bits; // @[Pipeline.scala:21:21]
assign io_out_bits_out_2_bits_0 = stages_3_out_2_bits; // @[Pipeline.scala:6:7, :21:21]
reg [31:0] stages_3_out_3_bits; // @[Pipeline.scala:21:21]
assign io_out_bits_out_3_bits_0 = stages_3_out_3_bits; // @[Pipeline.scala:6:7, :21:21]
reg [15:0] stages_3_row; // @[Pipeline.scala:21:21]
assign io_out_bits_row_0 = stages_3_row; // @[Pipeline.scala:6:7, :21:21]
reg stages_3_last; // @[Pipeline.scala:21:21]
assign io_out_bits_last_0 = stages_3_last; // @[Pipeline.scala:6:7, :21:21]
reg [127:0] stages_3_tag_data; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_data_0 = stages_3_tag_data; // @[Pipeline.scala:6:7, :21:21]
reg [13:0] stages_3_tag_addr; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_addr_0 = stages_3_tag_addr; // @[Pipeline.scala:6:7, :21:21]
reg stages_3_tag_mask_0; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_mask_0_0 = stages_3_tag_mask_0; // @[Pipeline.scala:6:7, :21:21]
reg stages_3_tag_mask_1; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_mask_1_0 = stages_3_tag_mask_1; // @[Pipeline.scala:6:7, :21:21]
reg stages_3_tag_mask_2; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_mask_2_0 = stages_3_tag_mask_2; // @[Pipeline.scala:6:7, :21:21]
reg stages_3_tag_mask_3; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_mask_3_0 = stages_3_tag_mask_3; // @[Pipeline.scala:6:7, :21:21]
reg stages_3_tag_mask_4; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_mask_4_0 = stages_3_tag_mask_4; // @[Pipeline.scala:6:7, :21:21]
reg stages_3_tag_mask_5; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_mask_5_0 = stages_3_tag_mask_5; // @[Pipeline.scala:6:7, :21:21]
reg stages_3_tag_mask_6; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_mask_6_0 = stages_3_tag_mask_6; // @[Pipeline.scala:6:7, :21:21]
reg stages_3_tag_mask_7; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_mask_7_0 = stages_3_tag_mask_7; // @[Pipeline.scala:6:7, :21:21]
reg stages_3_tag_mask_8; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_mask_8_0 = stages_3_tag_mask_8; // @[Pipeline.scala:6:7, :21:21]
reg stages_3_tag_mask_9; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_mask_9_0 = stages_3_tag_mask_9; // @[Pipeline.scala:6:7, :21:21]
reg stages_3_tag_mask_10; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_mask_10_0 = stages_3_tag_mask_10; // @[Pipeline.scala:6:7, :21:21]
reg stages_3_tag_mask_11; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_mask_11_0 = stages_3_tag_mask_11; // @[Pipeline.scala:6:7, :21:21]
reg stages_3_tag_mask_12; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_mask_12_0 = stages_3_tag_mask_12; // @[Pipeline.scala:6:7, :21:21]
reg stages_3_tag_mask_13; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_mask_13_0 = stages_3_tag_mask_13; // @[Pipeline.scala:6:7, :21:21]
reg stages_3_tag_mask_14; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_mask_14_0 = stages_3_tag_mask_14; // @[Pipeline.scala:6:7, :21:21]
reg stages_3_tag_mask_15; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_mask_15_0 = stages_3_tag_mask_15; // @[Pipeline.scala:6:7, :21:21]
reg stages_3_tag_is_acc; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_is_acc_0 = stages_3_tag_is_acc; // @[Pipeline.scala:6:7, :21:21]
reg stages_3_tag_accumulate; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_accumulate_0 = stages_3_tag_accumulate; // @[Pipeline.scala:6:7, :21:21]
reg stages_3_tag_has_acc_bitwidth; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_has_acc_bitwidth_0 = stages_3_tag_has_acc_bitwidth; // @[Pipeline.scala:6:7, :21:21]
reg [31:0] stages_3_tag_scale; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_scale_0 = stages_3_tag_scale; // @[Pipeline.scala:6:7, :21:21]
reg [15:0] stages_3_tag_repeats; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_repeats_0 = stages_3_tag_repeats; // @[Pipeline.scala:6:7, :21:21]
reg [15:0] stages_3_tag_pixel_repeats; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_pixel_repeats_0 = stages_3_tag_pixel_repeats; // @[Pipeline.scala:6:7, :21:21]
reg [15:0] stages_3_tag_len; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_len_0 = stages_3_tag_len; // @[Pipeline.scala:6:7, :21:21]
reg stages_3_tag_last; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_last_0 = stages_3_tag_last; // @[Pipeline.scala:6:7, :21:21]
reg [7:0] stages_3_tag_bytes_read; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_bytes_read_0 = stages_3_tag_bytes_read; // @[Pipeline.scala:6:7, :21:21]
reg [7:0] stages_3_tag_cmd_id; // @[Pipeline.scala:21:21]
assign io_out_bits_tag_cmd_id_0 = stages_3_tag_cmd_id; // @[Pipeline.scala:6:7, :21:21]
reg valids_0; // @[Pipeline.scala:22:25]
reg valids_1; // @[Pipeline.scala:22:25]
reg valids_2; // @[Pipeline.scala:22:25]
reg valids_3; // @[Pipeline.scala:22:25]
assign io_out_valid_0 = valids_3; // @[Pipeline.scala:6:7, :22:25]
wire _stalling_0_T; // @[Pipeline.scala:30:16]
wire _stalling_1_T; // @[Pipeline.scala:30:16]
wire _stalling_2_T; // @[Pipeline.scala:30:16]
wire _stalling_3_T_1; // @[Pipeline.scala:28:34]
wire stalling_0; // @[Pipeline.scala:23:27]
wire stalling_1; // @[Pipeline.scala:23:27]
wire stalling_2; // @[Pipeline.scala:23:27]
wire stalling_3; // @[Pipeline.scala:23:27]
wire _io_busy_T = valids_0 | valids_1; // @[Pipeline.scala:22:25, :24:46]
wire _io_busy_T_1 = _io_busy_T | valids_2; // @[Pipeline.scala:22:25, :24:46]
wire _io_busy_T_2 = _io_busy_T_1 | valids_3; // @[Pipeline.scala:22:25, :24:46]
assign _io_busy_T_3 = io_in_valid_0 | _io_busy_T_2; // @[Pipeline.scala:6:7, :24:{28,46}]
assign io_busy = _io_busy_T_3; // @[Pipeline.scala:6:7, :24:28]
assign _io_in_ready_T = ~stalling_0; // @[Pipeline.scala:23:27, :27:20]
assign io_in_ready_0 = _io_in_ready_T; // @[Pipeline.scala:6:7, :27:20]
wire _stalling_3_T = ~io_out_ready_0; // @[Pipeline.scala:6:7, :28:37]
assign _stalling_3_T_1 = valids_3 & _stalling_3_T; // @[Pipeline.scala:22:25, :28:{34,37}]
assign stalling_3 = _stalling_3_T_1; // @[Pipeline.scala:23:27, :28:34]
assign _stalling_0_T = valids_0 & stalling_1; // @[Pipeline.scala:22:25, :23:27, :30:16]
assign stalling_0 = _stalling_0_T; // @[Pipeline.scala:23:27, :30:16]
assign _stalling_1_T = valids_1 & stalling_2; // @[Pipeline.scala:22:25, :23:27, :30:16]
assign stalling_1 = _stalling_1_T; // @[Pipeline.scala:23:27, :30:16]
assign _stalling_2_T = valids_2 & stalling_3; // @[Pipeline.scala:22:25, :23:27, :30:16]
assign stalling_2 = _stalling_2_T; // @[Pipeline.scala:23:27, :30:16]
wire _T_4 = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Pipeline.scala:6:7]
if (_T_4) begin // @[Decoupled.scala:51:35]
stages_0_out_0_bits <= io_in_bits_out_0_bits_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_out_1_bits <= io_in_bits_out_1_bits_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_out_2_bits <= io_in_bits_out_2_bits_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_out_3_bits <= io_in_bits_out_3_bits_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_row <= io_in_bits_row_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_last <= io_in_bits_last_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_data <= io_in_bits_tag_data_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_addr <= io_in_bits_tag_addr_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_mask_0 <= io_in_bits_tag_mask_0_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_mask_1 <= io_in_bits_tag_mask_1_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_mask_2 <= io_in_bits_tag_mask_2_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_mask_3 <= io_in_bits_tag_mask_3_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_mask_4 <= io_in_bits_tag_mask_4_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_mask_5 <= io_in_bits_tag_mask_5_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_mask_6 <= io_in_bits_tag_mask_6_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_mask_7 <= io_in_bits_tag_mask_7_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_mask_8 <= io_in_bits_tag_mask_8_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_mask_9 <= io_in_bits_tag_mask_9_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_mask_10 <= io_in_bits_tag_mask_10_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_mask_11 <= io_in_bits_tag_mask_11_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_mask_12 <= io_in_bits_tag_mask_12_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_mask_13 <= io_in_bits_tag_mask_13_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_mask_14 <= io_in_bits_tag_mask_14_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_mask_15 <= io_in_bits_tag_mask_15_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_is_acc <= io_in_bits_tag_is_acc_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_accumulate <= io_in_bits_tag_accumulate_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_has_acc_bitwidth <= io_in_bits_tag_has_acc_bitwidth_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_scale <= io_in_bits_tag_scale_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_repeats <= io_in_bits_tag_repeats_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_pixel_repeats <= io_in_bits_tag_pixel_repeats_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_len <= io_in_bits_tag_len_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_last <= io_in_bits_tag_last_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_bytes_read <= io_in_bits_tag_bytes_read_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_tag_cmd_id <= io_in_bits_tag_cmd_id_0; // @[Pipeline.scala:6:7, :21:21]
end
if (stalling_1) begin // @[Pipeline.scala:23:27]
end
else begin // @[Pipeline.scala:23:27]
stages_1_out_0_bits <= stages_0_out_0_bits; // @[Pipeline.scala:21:21]
stages_1_out_1_bits <= stages_0_out_1_bits; // @[Pipeline.scala:21:21]
stages_1_out_2_bits <= stages_0_out_2_bits; // @[Pipeline.scala:21:21]
stages_1_out_3_bits <= stages_0_out_3_bits; // @[Pipeline.scala:21:21]
stages_1_row <= stages_0_row; // @[Pipeline.scala:21:21]
stages_1_last <= stages_0_last; // @[Pipeline.scala:21:21]
stages_1_tag_data <= stages_0_tag_data; // @[Pipeline.scala:21:21]
stages_1_tag_addr <= stages_0_tag_addr; // @[Pipeline.scala:21:21]
stages_1_tag_mask_0 <= stages_0_tag_mask_0; // @[Pipeline.scala:21:21]
stages_1_tag_mask_1 <= stages_0_tag_mask_1; // @[Pipeline.scala:21:21]
stages_1_tag_mask_2 <= stages_0_tag_mask_2; // @[Pipeline.scala:21:21]
stages_1_tag_mask_3 <= stages_0_tag_mask_3; // @[Pipeline.scala:21:21]
stages_1_tag_mask_4 <= stages_0_tag_mask_4; // @[Pipeline.scala:21:21]
stages_1_tag_mask_5 <= stages_0_tag_mask_5; // @[Pipeline.scala:21:21]
stages_1_tag_mask_6 <= stages_0_tag_mask_6; // @[Pipeline.scala:21:21]
stages_1_tag_mask_7 <= stages_0_tag_mask_7; // @[Pipeline.scala:21:21]
stages_1_tag_mask_8 <= stages_0_tag_mask_8; // @[Pipeline.scala:21:21]
stages_1_tag_mask_9 <= stages_0_tag_mask_9; // @[Pipeline.scala:21:21]
stages_1_tag_mask_10 <= stages_0_tag_mask_10; // @[Pipeline.scala:21:21]
stages_1_tag_mask_11 <= stages_0_tag_mask_11; // @[Pipeline.scala:21:21]
stages_1_tag_mask_12 <= stages_0_tag_mask_12; // @[Pipeline.scala:21:21]
stages_1_tag_mask_13 <= stages_0_tag_mask_13; // @[Pipeline.scala:21:21]
stages_1_tag_mask_14 <= stages_0_tag_mask_14; // @[Pipeline.scala:21:21]
stages_1_tag_mask_15 <= stages_0_tag_mask_15; // @[Pipeline.scala:21:21]
stages_1_tag_is_acc <= stages_0_tag_is_acc; // @[Pipeline.scala:21:21]
stages_1_tag_accumulate <= stages_0_tag_accumulate; // @[Pipeline.scala:21:21]
stages_1_tag_has_acc_bitwidth <= stages_0_tag_has_acc_bitwidth; // @[Pipeline.scala:21:21]
stages_1_tag_scale <= stages_0_tag_scale; // @[Pipeline.scala:21:21]
stages_1_tag_repeats <= stages_0_tag_repeats; // @[Pipeline.scala:21:21]
stages_1_tag_pixel_repeats <= stages_0_tag_pixel_repeats; // @[Pipeline.scala:21:21]
stages_1_tag_len <= stages_0_tag_len; // @[Pipeline.scala:21:21]
stages_1_tag_last <= stages_0_tag_last; // @[Pipeline.scala:21:21]
stages_1_tag_bytes_read <= stages_0_tag_bytes_read; // @[Pipeline.scala:21:21]
stages_1_tag_cmd_id <= stages_0_tag_cmd_id; // @[Pipeline.scala:21:21]
end
if (stalling_2) begin // @[Pipeline.scala:23:27]
end
else begin // @[Pipeline.scala:23:27]
stages_2_out_0_bits <= stages_1_out_0_bits; // @[Pipeline.scala:21:21]
stages_2_out_1_bits <= stages_1_out_1_bits; // @[Pipeline.scala:21:21]
stages_2_out_2_bits <= stages_1_out_2_bits; // @[Pipeline.scala:21:21]
stages_2_out_3_bits <= stages_1_out_3_bits; // @[Pipeline.scala:21:21]
stages_2_row <= stages_1_row; // @[Pipeline.scala:21:21]
stages_2_last <= stages_1_last; // @[Pipeline.scala:21:21]
stages_2_tag_data <= stages_1_tag_data; // @[Pipeline.scala:21:21]
stages_2_tag_addr <= stages_1_tag_addr; // @[Pipeline.scala:21:21]
stages_2_tag_mask_0 <= stages_1_tag_mask_0; // @[Pipeline.scala:21:21]
stages_2_tag_mask_1 <= stages_1_tag_mask_1; // @[Pipeline.scala:21:21]
stages_2_tag_mask_2 <= stages_1_tag_mask_2; // @[Pipeline.scala:21:21]
stages_2_tag_mask_3 <= stages_1_tag_mask_3; // @[Pipeline.scala:21:21]
stages_2_tag_mask_4 <= stages_1_tag_mask_4; // @[Pipeline.scala:21:21]
stages_2_tag_mask_5 <= stages_1_tag_mask_5; // @[Pipeline.scala:21:21]
stages_2_tag_mask_6 <= stages_1_tag_mask_6; // @[Pipeline.scala:21:21]
stages_2_tag_mask_7 <= stages_1_tag_mask_7; // @[Pipeline.scala:21:21]
stages_2_tag_mask_8 <= stages_1_tag_mask_8; // @[Pipeline.scala:21:21]
stages_2_tag_mask_9 <= stages_1_tag_mask_9; // @[Pipeline.scala:21:21]
stages_2_tag_mask_10 <= stages_1_tag_mask_10; // @[Pipeline.scala:21:21]
stages_2_tag_mask_11 <= stages_1_tag_mask_11; // @[Pipeline.scala:21:21]
stages_2_tag_mask_12 <= stages_1_tag_mask_12; // @[Pipeline.scala:21:21]
stages_2_tag_mask_13 <= stages_1_tag_mask_13; // @[Pipeline.scala:21:21]
stages_2_tag_mask_14 <= stages_1_tag_mask_14; // @[Pipeline.scala:21:21]
stages_2_tag_mask_15 <= stages_1_tag_mask_15; // @[Pipeline.scala:21:21]
stages_2_tag_is_acc <= stages_1_tag_is_acc; // @[Pipeline.scala:21:21]
stages_2_tag_accumulate <= stages_1_tag_accumulate; // @[Pipeline.scala:21:21]
stages_2_tag_has_acc_bitwidth <= stages_1_tag_has_acc_bitwidth; // @[Pipeline.scala:21:21]
stages_2_tag_scale <= stages_1_tag_scale; // @[Pipeline.scala:21:21]
stages_2_tag_repeats <= stages_1_tag_repeats; // @[Pipeline.scala:21:21]
stages_2_tag_pixel_repeats <= stages_1_tag_pixel_repeats; // @[Pipeline.scala:21:21]
stages_2_tag_len <= stages_1_tag_len; // @[Pipeline.scala:21:21]
stages_2_tag_last <= stages_1_tag_last; // @[Pipeline.scala:21:21]
stages_2_tag_bytes_read <= stages_1_tag_bytes_read; // @[Pipeline.scala:21:21]
stages_2_tag_cmd_id <= stages_1_tag_cmd_id; // @[Pipeline.scala:21:21]
end
if (stalling_3) begin // @[Pipeline.scala:23:27]
end
else begin // @[Pipeline.scala:23:27]
stages_3_out_0_bits <= stages_2_out_0_bits; // @[Pipeline.scala:21:21]
stages_3_out_1_bits <= stages_2_out_1_bits; // @[Pipeline.scala:21:21]
stages_3_out_2_bits <= stages_2_out_2_bits; // @[Pipeline.scala:21:21]
stages_3_out_3_bits <= stages_2_out_3_bits; // @[Pipeline.scala:21:21]
stages_3_row <= stages_2_row; // @[Pipeline.scala:21:21]
stages_3_last <= stages_2_last; // @[Pipeline.scala:21:21]
stages_3_tag_data <= stages_2_tag_data; // @[Pipeline.scala:21:21]
stages_3_tag_addr <= stages_2_tag_addr; // @[Pipeline.scala:21:21]
stages_3_tag_mask_0 <= stages_2_tag_mask_0; // @[Pipeline.scala:21:21]
stages_3_tag_mask_1 <= stages_2_tag_mask_1; // @[Pipeline.scala:21:21]
stages_3_tag_mask_2 <= stages_2_tag_mask_2; // @[Pipeline.scala:21:21]
stages_3_tag_mask_3 <= stages_2_tag_mask_3; // @[Pipeline.scala:21:21]
stages_3_tag_mask_4 <= stages_2_tag_mask_4; // @[Pipeline.scala:21:21]
stages_3_tag_mask_5 <= stages_2_tag_mask_5; // @[Pipeline.scala:21:21]
stages_3_tag_mask_6 <= stages_2_tag_mask_6; // @[Pipeline.scala:21:21]
stages_3_tag_mask_7 <= stages_2_tag_mask_7; // @[Pipeline.scala:21:21]
stages_3_tag_mask_8 <= stages_2_tag_mask_8; // @[Pipeline.scala:21:21]
stages_3_tag_mask_9 <= stages_2_tag_mask_9; // @[Pipeline.scala:21:21]
stages_3_tag_mask_10 <= stages_2_tag_mask_10; // @[Pipeline.scala:21:21]
stages_3_tag_mask_11 <= stages_2_tag_mask_11; // @[Pipeline.scala:21:21]
stages_3_tag_mask_12 <= stages_2_tag_mask_12; // @[Pipeline.scala:21:21]
stages_3_tag_mask_13 <= stages_2_tag_mask_13; // @[Pipeline.scala:21:21]
stages_3_tag_mask_14 <= stages_2_tag_mask_14; // @[Pipeline.scala:21:21]
stages_3_tag_mask_15 <= stages_2_tag_mask_15; // @[Pipeline.scala:21:21]
stages_3_tag_is_acc <= stages_2_tag_is_acc; // @[Pipeline.scala:21:21]
stages_3_tag_accumulate <= stages_2_tag_accumulate; // @[Pipeline.scala:21:21]
stages_3_tag_has_acc_bitwidth <= stages_2_tag_has_acc_bitwidth; // @[Pipeline.scala:21:21]
stages_3_tag_scale <= stages_2_tag_scale; // @[Pipeline.scala:21:21]
stages_3_tag_repeats <= stages_2_tag_repeats; // @[Pipeline.scala:21:21]
stages_3_tag_pixel_repeats <= stages_2_tag_pixel_repeats; // @[Pipeline.scala:21:21]
stages_3_tag_len <= stages_2_tag_len; // @[Pipeline.scala:21:21]
stages_3_tag_last <= stages_2_tag_last; // @[Pipeline.scala:21:21]
stages_3_tag_bytes_read <= stages_2_tag_bytes_read; // @[Pipeline.scala:21:21]
stages_3_tag_cmd_id <= stages_2_tag_cmd_id; // @[Pipeline.scala:21:21]
end
if (reset) begin // @[Pipeline.scala:6:7]
valids_0 <= 1'h0; // @[Pipeline.scala:22:25]
valids_1 <= 1'h0; // @[Pipeline.scala:22:25]
valids_2 <= 1'h0; // @[Pipeline.scala:22:25]
valids_3 <= 1'h0; // @[Pipeline.scala:22:25]
end
else begin // @[Pipeline.scala:6:7]
valids_0 <= _T_4 | stalling_1 & valids_0; // @[Decoupled.scala:51:35]
valids_1 <= valids_0 | stalling_2 & valids_1; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12]
valids_2 <= valids_1 | stalling_3 & valids_2; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12]
valids_3 <= valids_2 | ~io_out_ready_0 & valids_3; // @[Pipeline.scala:6:7, :22:25, :36:24, :37:19, :49:16, :50:12]
end
always @(posedge)
assign io_in_ready = io_in_ready_0; // @[Pipeline.scala:6:7]
assign io_out_valid = io_out_valid_0; // @[Pipeline.scala:6:7]
assign io_out_bits_out_0_bits = io_out_bits_out_0_bits_0; // @[Pipeline.scala:6:7]
assign io_out_bits_out_1_bits = io_out_bits_out_1_bits_0; // @[Pipeline.scala:6:7]
assign io_out_bits_out_2_bits = io_out_bits_out_2_bits_0; // @[Pipeline.scala:6:7]
assign io_out_bits_out_3_bits = io_out_bits_out_3_bits_0; // @[Pipeline.scala:6:7]
assign io_out_bits_row = io_out_bits_row_0; // @[Pipeline.scala:6:7]
assign io_out_bits_last = io_out_bits_last_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_data = io_out_bits_tag_data_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_addr = io_out_bits_tag_addr_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_mask_0 = io_out_bits_tag_mask_0_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_mask_1 = io_out_bits_tag_mask_1_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_mask_2 = io_out_bits_tag_mask_2_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_mask_3 = io_out_bits_tag_mask_3_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_mask_4 = io_out_bits_tag_mask_4_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_mask_5 = io_out_bits_tag_mask_5_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_mask_6 = io_out_bits_tag_mask_6_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_mask_7 = io_out_bits_tag_mask_7_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_mask_8 = io_out_bits_tag_mask_8_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_mask_9 = io_out_bits_tag_mask_9_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_mask_10 = io_out_bits_tag_mask_10_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_mask_11 = io_out_bits_tag_mask_11_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_mask_12 = io_out_bits_tag_mask_12_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_mask_13 = io_out_bits_tag_mask_13_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_mask_14 = io_out_bits_tag_mask_14_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_mask_15 = io_out_bits_tag_mask_15_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_is_acc = io_out_bits_tag_is_acc_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_accumulate = io_out_bits_tag_accumulate_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_has_acc_bitwidth = io_out_bits_tag_has_acc_bitwidth_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_scale = io_out_bits_tag_scale_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_repeats = io_out_bits_tag_repeats_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_pixel_repeats = io_out_bits_tag_pixel_repeats_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_len = io_out_bits_tag_len_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_last = io_out_bits_tag_last_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_bytes_read = io_out_bits_tag_bytes_read_0; // @[Pipeline.scala:6:7]
assign io_out_bits_tag_cmd_id = io_out_bits_tag_cmd_id_0; // @[Pipeline.scala:6:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_32 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 2, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 3)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<2>(0h2))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<3>(0h7))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 2, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 3)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<2>(0h3))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<3>(0h7))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<1>(0h0))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<1>(0h1))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 2)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<2>(0h2))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_31 = shr(io.in.a.bits.source, 2)
node _source_ok_T_32 = eq(_source_ok_T_31, UInt<2>(0h3))
node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE : UInt<1>[10]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_36
connect _source_ok_WIRE[7], _source_ok_T_37
connect _source_ok_WIRE[8], _source_ok_T_38
connect _source_ok_WIRE[9], _source_ok_T_39
node _source_ok_T_40 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[2])
node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[3])
node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[4])
node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[5])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[6])
node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[7])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[8])
node source_ok = or(_source_ok_T_47, _source_ok_WIRE[9])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits = bits(_uncommonBits_T, 2, 0)
node _T_12 = shr(io.in.a.bits.source, 3)
node _T_13 = eq(_T_12, UInt<2>(0h2))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<3>(0h7))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 2, 0)
node _T_25 = shr(io.in.a.bits.source, 3)
node _T_26 = eq(_T_25, UInt<2>(0h3))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<3>(0h7))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<1>(0h0))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<1>(0h1))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_64 = shr(io.in.a.bits.source, 2)
node _T_65 = eq(_T_64, UInt<2>(0h2))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_77 = shr(io.in.a.bits.source, 2)
node _T_78 = eq(_T_77, UInt<2>(0h3))
node _T_79 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_80 = and(_T_78, _T_79)
node _T_81 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(_T_82, UInt<1>(0h0))
node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = or(_T_83, _T_88)
node _T_90 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_91 = eq(_T_90, UInt<1>(0h0))
node _T_92 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_93 = cvt(_T_92)
node _T_94 = and(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = asSInt(_T_94)
node _T_96 = eq(_T_95, asSInt(UInt<1>(0h0)))
node _T_97 = or(_T_91, _T_96)
node _T_98 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = or(_T_99, _T_104)
node _T_106 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_107 = eq(_T_106, UInt<1>(0h0))
node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_109 = cvt(_T_108)
node _T_110 = and(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = asSInt(_T_110)
node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0)))
node _T_113 = or(_T_107, _T_112)
node _T_114 = and(_T_11, _T_24)
node _T_115 = and(_T_114, _T_37)
node _T_116 = and(_T_115, _T_50)
node _T_117 = and(_T_116, _T_63)
node _T_118 = and(_T_117, _T_76)
node _T_119 = and(_T_118, _T_89)
node _T_120 = and(_T_119, _T_97)
node _T_121 = and(_T_120, _T_105)
node _T_122 = and(_T_121, _T_113)
node _T_123 = asUInt(reset)
node _T_124 = eq(_T_123, UInt<1>(0h0))
when _T_124 :
node _T_125 = eq(_T_122, UInt<1>(0h0))
when _T_125 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_122, UInt<1>(0h1), "") : assert_1
node _T_126 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_126 :
node _T_127 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_128 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_129 = and(_T_127, _T_128)
node _T_130 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0)
node _T_131 = shr(io.in.a.bits.source, 3)
node _T_132 = eq(_T_131, UInt<2>(0h2))
node _T_133 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_134 = and(_T_132, _T_133)
node _T_135 = leq(uncommonBits_6, UInt<3>(0h7))
node _T_136 = and(_T_134, _T_135)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 2, 0)
node _T_137 = shr(io.in.a.bits.source, 3)
node _T_138 = eq(_T_137, UInt<2>(0h3))
node _T_139 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_140 = and(_T_138, _T_139)
node _T_141 = leq(uncommonBits_7, UInt<3>(0h7))
node _T_142 = and(_T_140, _T_141)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_143 = shr(io.in.a.bits.source, 2)
node _T_144 = eq(_T_143, UInt<1>(0h0))
node _T_145 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_146 = and(_T_144, _T_145)
node _T_147 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_148 = and(_T_146, _T_147)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_149 = shr(io.in.a.bits.source, 2)
node _T_150 = eq(_T_149, UInt<1>(0h1))
node _T_151 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_152 = and(_T_150, _T_151)
node _T_153 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_154 = and(_T_152, _T_153)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_155 = shr(io.in.a.bits.source, 2)
node _T_156 = eq(_T_155, UInt<2>(0h2))
node _T_157 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_158 = and(_T_156, _T_157)
node _T_159 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_160 = and(_T_158, _T_159)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_161 = shr(io.in.a.bits.source, 2)
node _T_162 = eq(_T_161, UInt<2>(0h3))
node _T_163 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_164 = and(_T_162, _T_163)
node _T_165 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_166 = and(_T_164, _T_165)
node _T_167 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_168 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_169 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_170 = or(_T_130, _T_136)
node _T_171 = or(_T_170, _T_142)
node _T_172 = or(_T_171, _T_148)
node _T_173 = or(_T_172, _T_154)
node _T_174 = or(_T_173, _T_160)
node _T_175 = or(_T_174, _T_166)
node _T_176 = or(_T_175, _T_167)
node _T_177 = or(_T_176, _T_168)
node _T_178 = or(_T_177, _T_169)
node _T_179 = and(_T_129, _T_178)
node _T_180 = or(UInt<1>(0h0), _T_179)
node _T_181 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_182 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_183 = cvt(_T_182)
node _T_184 = and(_T_183, asSInt(UInt<17>(0h10000)))
node _T_185 = asSInt(_T_184)
node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0)))
node _T_187 = and(_T_181, _T_186)
node _T_188 = or(UInt<1>(0h0), _T_187)
node _T_189 = and(_T_180, _T_188)
node _T_190 = asUInt(reset)
node _T_191 = eq(_T_190, UInt<1>(0h0))
when _T_191 :
node _T_192 = eq(_T_189, UInt<1>(0h0))
when _T_192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_189, UInt<1>(0h1), "") : assert_2
node _T_193 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_194 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_195 = and(_T_193, _T_194)
node _T_196 = or(UInt<1>(0h0), _T_195)
node _T_197 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_198 = cvt(_T_197)
node _T_199 = and(_T_198, asSInt(UInt<17>(0h10000)))
node _T_200 = asSInt(_T_199)
node _T_201 = eq(_T_200, asSInt(UInt<1>(0h0)))
node _T_202 = and(_T_196, _T_201)
node _T_203 = or(UInt<1>(0h0), _T_202)
node _T_204 = and(UInt<1>(0h0), _T_203)
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(_T_204, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_204, UInt<1>(0h1), "") : assert_3
node _T_208 = asUInt(reset)
node _T_209 = eq(_T_208, UInt<1>(0h0))
when _T_209 :
node _T_210 = eq(source_ok, UInt<1>(0h0))
when _T_210 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_211 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_211, UInt<1>(0h1), "") : assert_5
node _T_215 = asUInt(reset)
node _T_216 = eq(_T_215, UInt<1>(0h0))
when _T_216 :
node _T_217 = eq(is_aligned, UInt<1>(0h0))
when _T_217 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_218 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_218, UInt<1>(0h1), "") : assert_7
node _T_222 = not(io.in.a.bits.mask)
node _T_223 = eq(_T_222, UInt<1>(0h0))
node _T_224 = asUInt(reset)
node _T_225 = eq(_T_224, UInt<1>(0h0))
when _T_225 :
node _T_226 = eq(_T_223, UInt<1>(0h0))
when _T_226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_223, UInt<1>(0h1), "") : assert_8
node _T_227 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_228 = asUInt(reset)
node _T_229 = eq(_T_228, UInt<1>(0h0))
when _T_229 :
node _T_230 = eq(_T_227, UInt<1>(0h0))
when _T_230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_227, UInt<1>(0h1), "") : assert_9
node _T_231 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_231 :
node _T_232 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_233 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_234 = and(_T_232, _T_233)
node _T_235 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0)
node _T_236 = shr(io.in.a.bits.source, 3)
node _T_237 = eq(_T_236, UInt<2>(0h2))
node _T_238 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_239 = and(_T_237, _T_238)
node _T_240 = leq(uncommonBits_12, UInt<3>(0h7))
node _T_241 = and(_T_239, _T_240)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0)
node _T_242 = shr(io.in.a.bits.source, 3)
node _T_243 = eq(_T_242, UInt<2>(0h3))
node _T_244 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_245 = and(_T_243, _T_244)
node _T_246 = leq(uncommonBits_13, UInt<3>(0h7))
node _T_247 = and(_T_245, _T_246)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_248 = shr(io.in.a.bits.source, 2)
node _T_249 = eq(_T_248, UInt<1>(0h0))
node _T_250 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_251 = and(_T_249, _T_250)
node _T_252 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_253 = and(_T_251, _T_252)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_254 = shr(io.in.a.bits.source, 2)
node _T_255 = eq(_T_254, UInt<1>(0h1))
node _T_256 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_257 = and(_T_255, _T_256)
node _T_258 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_259 = and(_T_257, _T_258)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_260 = shr(io.in.a.bits.source, 2)
node _T_261 = eq(_T_260, UInt<2>(0h2))
node _T_262 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_263 = and(_T_261, _T_262)
node _T_264 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_265 = and(_T_263, _T_264)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_266 = shr(io.in.a.bits.source, 2)
node _T_267 = eq(_T_266, UInt<2>(0h3))
node _T_268 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_269 = and(_T_267, _T_268)
node _T_270 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_271 = and(_T_269, _T_270)
node _T_272 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_273 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_274 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_275 = or(_T_235, _T_241)
node _T_276 = or(_T_275, _T_247)
node _T_277 = or(_T_276, _T_253)
node _T_278 = or(_T_277, _T_259)
node _T_279 = or(_T_278, _T_265)
node _T_280 = or(_T_279, _T_271)
node _T_281 = or(_T_280, _T_272)
node _T_282 = or(_T_281, _T_273)
node _T_283 = or(_T_282, _T_274)
node _T_284 = and(_T_234, _T_283)
node _T_285 = or(UInt<1>(0h0), _T_284)
node _T_286 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_287 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_288 = cvt(_T_287)
node _T_289 = and(_T_288, asSInt(UInt<17>(0h10000)))
node _T_290 = asSInt(_T_289)
node _T_291 = eq(_T_290, asSInt(UInt<1>(0h0)))
node _T_292 = and(_T_286, _T_291)
node _T_293 = or(UInt<1>(0h0), _T_292)
node _T_294 = and(_T_285, _T_293)
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_294, UInt<1>(0h1), "") : assert_10
node _T_298 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_299 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_300 = and(_T_298, _T_299)
node _T_301 = or(UInt<1>(0h0), _T_300)
node _T_302 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_303 = cvt(_T_302)
node _T_304 = and(_T_303, asSInt(UInt<17>(0h10000)))
node _T_305 = asSInt(_T_304)
node _T_306 = eq(_T_305, asSInt(UInt<1>(0h0)))
node _T_307 = and(_T_301, _T_306)
node _T_308 = or(UInt<1>(0h0), _T_307)
node _T_309 = and(UInt<1>(0h0), _T_308)
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_309, UInt<1>(0h1), "") : assert_11
node _T_313 = asUInt(reset)
node _T_314 = eq(_T_313, UInt<1>(0h0))
when _T_314 :
node _T_315 = eq(source_ok, UInt<1>(0h0))
when _T_315 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_316 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_317 = asUInt(reset)
node _T_318 = eq(_T_317, UInt<1>(0h0))
when _T_318 :
node _T_319 = eq(_T_316, UInt<1>(0h0))
when _T_319 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_316, UInt<1>(0h1), "") : assert_13
node _T_320 = asUInt(reset)
node _T_321 = eq(_T_320, UInt<1>(0h0))
when _T_321 :
node _T_322 = eq(is_aligned, UInt<1>(0h0))
when _T_322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_323 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_324 = asUInt(reset)
node _T_325 = eq(_T_324, UInt<1>(0h0))
when _T_325 :
node _T_326 = eq(_T_323, UInt<1>(0h0))
when _T_326 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_323, UInt<1>(0h1), "") : assert_15
node _T_327 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_328 = asUInt(reset)
node _T_329 = eq(_T_328, UInt<1>(0h0))
when _T_329 :
node _T_330 = eq(_T_327, UInt<1>(0h0))
when _T_330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_327, UInt<1>(0h1), "") : assert_16
node _T_331 = not(io.in.a.bits.mask)
node _T_332 = eq(_T_331, UInt<1>(0h0))
node _T_333 = asUInt(reset)
node _T_334 = eq(_T_333, UInt<1>(0h0))
when _T_334 :
node _T_335 = eq(_T_332, UInt<1>(0h0))
when _T_335 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_332, UInt<1>(0h1), "") : assert_17
node _T_336 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_337 = asUInt(reset)
node _T_338 = eq(_T_337, UInt<1>(0h0))
when _T_338 :
node _T_339 = eq(_T_336, UInt<1>(0h0))
when _T_339 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_336, UInt<1>(0h1), "") : assert_18
node _T_340 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_340 :
node _T_341 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_342 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_343 = and(_T_341, _T_342)
node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 2, 0)
node _T_345 = shr(io.in.a.bits.source, 3)
node _T_346 = eq(_T_345, UInt<2>(0h2))
node _T_347 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_348 = and(_T_346, _T_347)
node _T_349 = leq(uncommonBits_18, UInt<3>(0h7))
node _T_350 = and(_T_348, _T_349)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0)
node _T_351 = shr(io.in.a.bits.source, 3)
node _T_352 = eq(_T_351, UInt<2>(0h3))
node _T_353 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_354 = and(_T_352, _T_353)
node _T_355 = leq(uncommonBits_19, UInt<3>(0h7))
node _T_356 = and(_T_354, _T_355)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_357 = shr(io.in.a.bits.source, 2)
node _T_358 = eq(_T_357, UInt<1>(0h0))
node _T_359 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_360 = and(_T_358, _T_359)
node _T_361 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_362 = and(_T_360, _T_361)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_363 = shr(io.in.a.bits.source, 2)
node _T_364 = eq(_T_363, UInt<1>(0h1))
node _T_365 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_366 = and(_T_364, _T_365)
node _T_367 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_368 = and(_T_366, _T_367)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_369 = shr(io.in.a.bits.source, 2)
node _T_370 = eq(_T_369, UInt<2>(0h2))
node _T_371 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_372 = and(_T_370, _T_371)
node _T_373 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_374 = and(_T_372, _T_373)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_375 = shr(io.in.a.bits.source, 2)
node _T_376 = eq(_T_375, UInt<2>(0h3))
node _T_377 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_378 = and(_T_376, _T_377)
node _T_379 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_380 = and(_T_378, _T_379)
node _T_381 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_382 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_383 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_384 = or(_T_344, _T_350)
node _T_385 = or(_T_384, _T_356)
node _T_386 = or(_T_385, _T_362)
node _T_387 = or(_T_386, _T_368)
node _T_388 = or(_T_387, _T_374)
node _T_389 = or(_T_388, _T_380)
node _T_390 = or(_T_389, _T_381)
node _T_391 = or(_T_390, _T_382)
node _T_392 = or(_T_391, _T_383)
node _T_393 = and(_T_343, _T_392)
node _T_394 = or(UInt<1>(0h0), _T_393)
node _T_395 = asUInt(reset)
node _T_396 = eq(_T_395, UInt<1>(0h0))
when _T_396 :
node _T_397 = eq(_T_394, UInt<1>(0h0))
when _T_397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_394, UInt<1>(0h1), "") : assert_19
node _T_398 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_399 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_400 = and(_T_398, _T_399)
node _T_401 = or(UInt<1>(0h0), _T_400)
node _T_402 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_403 = cvt(_T_402)
node _T_404 = and(_T_403, asSInt(UInt<17>(0h10000)))
node _T_405 = asSInt(_T_404)
node _T_406 = eq(_T_405, asSInt(UInt<1>(0h0)))
node _T_407 = and(_T_401, _T_406)
node _T_408 = or(UInt<1>(0h0), _T_407)
node _T_409 = asUInt(reset)
node _T_410 = eq(_T_409, UInt<1>(0h0))
when _T_410 :
node _T_411 = eq(_T_408, UInt<1>(0h0))
when _T_411 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_408, UInt<1>(0h1), "") : assert_20
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(source_ok, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_415 = asUInt(reset)
node _T_416 = eq(_T_415, UInt<1>(0h0))
when _T_416 :
node _T_417 = eq(is_aligned, UInt<1>(0h0))
when _T_417 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_418 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_418, UInt<1>(0h1), "") : assert_23
node _T_422 = eq(io.in.a.bits.mask, mask)
node _T_423 = asUInt(reset)
node _T_424 = eq(_T_423, UInt<1>(0h0))
when _T_424 :
node _T_425 = eq(_T_422, UInt<1>(0h0))
when _T_425 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_422, UInt<1>(0h1), "") : assert_24
node _T_426 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(_T_426, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_426, UInt<1>(0h1), "") : assert_25
node _T_430 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_430 :
node _T_431 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_432 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_433 = and(_T_431, _T_432)
node _T_434 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0)
node _T_435 = shr(io.in.a.bits.source, 3)
node _T_436 = eq(_T_435, UInt<2>(0h2))
node _T_437 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_438 = and(_T_436, _T_437)
node _T_439 = leq(uncommonBits_24, UInt<3>(0h7))
node _T_440 = and(_T_438, _T_439)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 2, 0)
node _T_441 = shr(io.in.a.bits.source, 3)
node _T_442 = eq(_T_441, UInt<2>(0h3))
node _T_443 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_444 = and(_T_442, _T_443)
node _T_445 = leq(uncommonBits_25, UInt<3>(0h7))
node _T_446 = and(_T_444, _T_445)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_447 = shr(io.in.a.bits.source, 2)
node _T_448 = eq(_T_447, UInt<1>(0h0))
node _T_449 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_450 = and(_T_448, _T_449)
node _T_451 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_452 = and(_T_450, _T_451)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_453 = shr(io.in.a.bits.source, 2)
node _T_454 = eq(_T_453, UInt<1>(0h1))
node _T_455 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_456 = and(_T_454, _T_455)
node _T_457 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_458 = and(_T_456, _T_457)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_459 = shr(io.in.a.bits.source, 2)
node _T_460 = eq(_T_459, UInt<2>(0h2))
node _T_461 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_462 = and(_T_460, _T_461)
node _T_463 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_464 = and(_T_462, _T_463)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_465 = shr(io.in.a.bits.source, 2)
node _T_466 = eq(_T_465, UInt<2>(0h3))
node _T_467 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_468 = and(_T_466, _T_467)
node _T_469 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_470 = and(_T_468, _T_469)
node _T_471 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_472 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_473 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_474 = or(_T_434, _T_440)
node _T_475 = or(_T_474, _T_446)
node _T_476 = or(_T_475, _T_452)
node _T_477 = or(_T_476, _T_458)
node _T_478 = or(_T_477, _T_464)
node _T_479 = or(_T_478, _T_470)
node _T_480 = or(_T_479, _T_471)
node _T_481 = or(_T_480, _T_472)
node _T_482 = or(_T_481, _T_473)
node _T_483 = and(_T_433, _T_482)
node _T_484 = or(UInt<1>(0h0), _T_483)
node _T_485 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_486 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_487 = cvt(_T_486)
node _T_488 = and(_T_487, asSInt(UInt<17>(0h10000)))
node _T_489 = asSInt(_T_488)
node _T_490 = eq(_T_489, asSInt(UInt<1>(0h0)))
node _T_491 = and(_T_485, _T_490)
node _T_492 = or(UInt<1>(0h0), _T_491)
node _T_493 = and(_T_484, _T_492)
node _T_494 = asUInt(reset)
node _T_495 = eq(_T_494, UInt<1>(0h0))
when _T_495 :
node _T_496 = eq(_T_493, UInt<1>(0h0))
when _T_496 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_493, UInt<1>(0h1), "") : assert_26
node _T_497 = asUInt(reset)
node _T_498 = eq(_T_497, UInt<1>(0h0))
when _T_498 :
node _T_499 = eq(source_ok, UInt<1>(0h0))
when _T_499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(is_aligned, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_503 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_504 = asUInt(reset)
node _T_505 = eq(_T_504, UInt<1>(0h0))
when _T_505 :
node _T_506 = eq(_T_503, UInt<1>(0h0))
when _T_506 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_503, UInt<1>(0h1), "") : assert_29
node _T_507 = eq(io.in.a.bits.mask, mask)
node _T_508 = asUInt(reset)
node _T_509 = eq(_T_508, UInt<1>(0h0))
when _T_509 :
node _T_510 = eq(_T_507, UInt<1>(0h0))
when _T_510 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_507, UInt<1>(0h1), "") : assert_30
node _T_511 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_511 :
node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_513 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_514 = and(_T_512, _T_513)
node _T_515 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 2, 0)
node _T_516 = shr(io.in.a.bits.source, 3)
node _T_517 = eq(_T_516, UInt<2>(0h2))
node _T_518 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_519 = and(_T_517, _T_518)
node _T_520 = leq(uncommonBits_30, UInt<3>(0h7))
node _T_521 = and(_T_519, _T_520)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 2, 0)
node _T_522 = shr(io.in.a.bits.source, 3)
node _T_523 = eq(_T_522, UInt<2>(0h3))
node _T_524 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_525 = and(_T_523, _T_524)
node _T_526 = leq(uncommonBits_31, UInt<3>(0h7))
node _T_527 = and(_T_525, _T_526)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_528 = shr(io.in.a.bits.source, 2)
node _T_529 = eq(_T_528, UInt<1>(0h0))
node _T_530 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_531 = and(_T_529, _T_530)
node _T_532 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_533 = and(_T_531, _T_532)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_534 = shr(io.in.a.bits.source, 2)
node _T_535 = eq(_T_534, UInt<1>(0h1))
node _T_536 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_537 = and(_T_535, _T_536)
node _T_538 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_539 = and(_T_537, _T_538)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_540 = shr(io.in.a.bits.source, 2)
node _T_541 = eq(_T_540, UInt<2>(0h2))
node _T_542 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_543 = and(_T_541, _T_542)
node _T_544 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_545 = and(_T_543, _T_544)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_546 = shr(io.in.a.bits.source, 2)
node _T_547 = eq(_T_546, UInt<2>(0h3))
node _T_548 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_549 = and(_T_547, _T_548)
node _T_550 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_551 = and(_T_549, _T_550)
node _T_552 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_553 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_554 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_555 = or(_T_515, _T_521)
node _T_556 = or(_T_555, _T_527)
node _T_557 = or(_T_556, _T_533)
node _T_558 = or(_T_557, _T_539)
node _T_559 = or(_T_558, _T_545)
node _T_560 = or(_T_559, _T_551)
node _T_561 = or(_T_560, _T_552)
node _T_562 = or(_T_561, _T_553)
node _T_563 = or(_T_562, _T_554)
node _T_564 = and(_T_514, _T_563)
node _T_565 = or(UInt<1>(0h0), _T_564)
node _T_566 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_567 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_568 = cvt(_T_567)
node _T_569 = and(_T_568, asSInt(UInt<17>(0h10000)))
node _T_570 = asSInt(_T_569)
node _T_571 = eq(_T_570, asSInt(UInt<1>(0h0)))
node _T_572 = and(_T_566, _T_571)
node _T_573 = or(UInt<1>(0h0), _T_572)
node _T_574 = and(_T_565, _T_573)
node _T_575 = asUInt(reset)
node _T_576 = eq(_T_575, UInt<1>(0h0))
when _T_576 :
node _T_577 = eq(_T_574, UInt<1>(0h0))
when _T_577 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_574, UInt<1>(0h1), "") : assert_31
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(source_ok, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(is_aligned, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_584 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_584, UInt<1>(0h1), "") : assert_34
node _T_588 = not(mask)
node _T_589 = and(io.in.a.bits.mask, _T_588)
node _T_590 = eq(_T_589, UInt<1>(0h0))
node _T_591 = asUInt(reset)
node _T_592 = eq(_T_591, UInt<1>(0h0))
when _T_592 :
node _T_593 = eq(_T_590, UInt<1>(0h0))
when _T_593 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_590, UInt<1>(0h1), "") : assert_35
node _T_594 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_594 :
node _T_595 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_596 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_597 = and(_T_595, _T_596)
node _T_598 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 2, 0)
node _T_599 = shr(io.in.a.bits.source, 3)
node _T_600 = eq(_T_599, UInt<2>(0h2))
node _T_601 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_602 = and(_T_600, _T_601)
node _T_603 = leq(uncommonBits_36, UInt<3>(0h7))
node _T_604 = and(_T_602, _T_603)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 2, 0)
node _T_605 = shr(io.in.a.bits.source, 3)
node _T_606 = eq(_T_605, UInt<2>(0h3))
node _T_607 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_608 = and(_T_606, _T_607)
node _T_609 = leq(uncommonBits_37, UInt<3>(0h7))
node _T_610 = and(_T_608, _T_609)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_611 = shr(io.in.a.bits.source, 2)
node _T_612 = eq(_T_611, UInt<1>(0h0))
node _T_613 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_614 = and(_T_612, _T_613)
node _T_615 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_616 = and(_T_614, _T_615)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_617 = shr(io.in.a.bits.source, 2)
node _T_618 = eq(_T_617, UInt<1>(0h1))
node _T_619 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_620 = and(_T_618, _T_619)
node _T_621 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_622 = and(_T_620, _T_621)
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_623 = shr(io.in.a.bits.source, 2)
node _T_624 = eq(_T_623, UInt<2>(0h2))
node _T_625 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_626 = and(_T_624, _T_625)
node _T_627 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_628 = and(_T_626, _T_627)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_629 = shr(io.in.a.bits.source, 2)
node _T_630 = eq(_T_629, UInt<2>(0h3))
node _T_631 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_632 = and(_T_630, _T_631)
node _T_633 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_634 = and(_T_632, _T_633)
node _T_635 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_636 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_637 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_638 = or(_T_598, _T_604)
node _T_639 = or(_T_638, _T_610)
node _T_640 = or(_T_639, _T_616)
node _T_641 = or(_T_640, _T_622)
node _T_642 = or(_T_641, _T_628)
node _T_643 = or(_T_642, _T_634)
node _T_644 = or(_T_643, _T_635)
node _T_645 = or(_T_644, _T_636)
node _T_646 = or(_T_645, _T_637)
node _T_647 = and(_T_597, _T_646)
node _T_648 = or(UInt<1>(0h0), _T_647)
node _T_649 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_650 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_651 = cvt(_T_650)
node _T_652 = and(_T_651, asSInt(UInt<17>(0h10000)))
node _T_653 = asSInt(_T_652)
node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0)))
node _T_655 = and(_T_649, _T_654)
node _T_656 = or(UInt<1>(0h0), _T_655)
node _T_657 = and(_T_648, _T_656)
node _T_658 = asUInt(reset)
node _T_659 = eq(_T_658, UInt<1>(0h0))
when _T_659 :
node _T_660 = eq(_T_657, UInt<1>(0h0))
when _T_660 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_657, UInt<1>(0h1), "") : assert_36
node _T_661 = asUInt(reset)
node _T_662 = eq(_T_661, UInt<1>(0h0))
when _T_662 :
node _T_663 = eq(source_ok, UInt<1>(0h0))
when _T_663 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_664 = asUInt(reset)
node _T_665 = eq(_T_664, UInt<1>(0h0))
when _T_665 :
node _T_666 = eq(is_aligned, UInt<1>(0h0))
when _T_666 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_667 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_668 = asUInt(reset)
node _T_669 = eq(_T_668, UInt<1>(0h0))
when _T_669 :
node _T_670 = eq(_T_667, UInt<1>(0h0))
when _T_670 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_667, UInt<1>(0h1), "") : assert_39
node _T_671 = eq(io.in.a.bits.mask, mask)
node _T_672 = asUInt(reset)
node _T_673 = eq(_T_672, UInt<1>(0h0))
when _T_673 :
node _T_674 = eq(_T_671, UInt<1>(0h0))
when _T_674 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_671, UInt<1>(0h1), "") : assert_40
node _T_675 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_675 :
node _T_676 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_677 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_678 = and(_T_676, _T_677)
node _T_679 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 2, 0)
node _T_680 = shr(io.in.a.bits.source, 3)
node _T_681 = eq(_T_680, UInt<2>(0h2))
node _T_682 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_683 = and(_T_681, _T_682)
node _T_684 = leq(uncommonBits_42, UInt<3>(0h7))
node _T_685 = and(_T_683, _T_684)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 2, 0)
node _T_686 = shr(io.in.a.bits.source, 3)
node _T_687 = eq(_T_686, UInt<2>(0h3))
node _T_688 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_689 = and(_T_687, _T_688)
node _T_690 = leq(uncommonBits_43, UInt<3>(0h7))
node _T_691 = and(_T_689, _T_690)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_692 = shr(io.in.a.bits.source, 2)
node _T_693 = eq(_T_692, UInt<1>(0h0))
node _T_694 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_695 = and(_T_693, _T_694)
node _T_696 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_697 = and(_T_695, _T_696)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_698 = shr(io.in.a.bits.source, 2)
node _T_699 = eq(_T_698, UInt<1>(0h1))
node _T_700 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_701 = and(_T_699, _T_700)
node _T_702 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_703 = and(_T_701, _T_702)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0)
node _T_704 = shr(io.in.a.bits.source, 2)
node _T_705 = eq(_T_704, UInt<2>(0h2))
node _T_706 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_707 = and(_T_705, _T_706)
node _T_708 = leq(uncommonBits_46, UInt<2>(0h3))
node _T_709 = and(_T_707, _T_708)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0)
node _T_710 = shr(io.in.a.bits.source, 2)
node _T_711 = eq(_T_710, UInt<2>(0h3))
node _T_712 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_713 = and(_T_711, _T_712)
node _T_714 = leq(uncommonBits_47, UInt<2>(0h3))
node _T_715 = and(_T_713, _T_714)
node _T_716 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_717 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_718 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_719 = or(_T_679, _T_685)
node _T_720 = or(_T_719, _T_691)
node _T_721 = or(_T_720, _T_697)
node _T_722 = or(_T_721, _T_703)
node _T_723 = or(_T_722, _T_709)
node _T_724 = or(_T_723, _T_715)
node _T_725 = or(_T_724, _T_716)
node _T_726 = or(_T_725, _T_717)
node _T_727 = or(_T_726, _T_718)
node _T_728 = and(_T_678, _T_727)
node _T_729 = or(UInt<1>(0h0), _T_728)
node _T_730 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_731 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_732 = cvt(_T_731)
node _T_733 = and(_T_732, asSInt(UInt<17>(0h10000)))
node _T_734 = asSInt(_T_733)
node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0)))
node _T_736 = and(_T_730, _T_735)
node _T_737 = or(UInt<1>(0h0), _T_736)
node _T_738 = and(_T_729, _T_737)
node _T_739 = asUInt(reset)
node _T_740 = eq(_T_739, UInt<1>(0h0))
when _T_740 :
node _T_741 = eq(_T_738, UInt<1>(0h0))
when _T_741 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_738, UInt<1>(0h1), "") : assert_41
node _T_742 = asUInt(reset)
node _T_743 = eq(_T_742, UInt<1>(0h0))
when _T_743 :
node _T_744 = eq(source_ok, UInt<1>(0h0))
when _T_744 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_745 = asUInt(reset)
node _T_746 = eq(_T_745, UInt<1>(0h0))
when _T_746 :
node _T_747 = eq(is_aligned, UInt<1>(0h0))
when _T_747 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_748 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_749 = asUInt(reset)
node _T_750 = eq(_T_749, UInt<1>(0h0))
when _T_750 :
node _T_751 = eq(_T_748, UInt<1>(0h0))
when _T_751 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_748, UInt<1>(0h1), "") : assert_44
node _T_752 = eq(io.in.a.bits.mask, mask)
node _T_753 = asUInt(reset)
node _T_754 = eq(_T_753, UInt<1>(0h0))
when _T_754 :
node _T_755 = eq(_T_752, UInt<1>(0h0))
when _T_755 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_752, UInt<1>(0h1), "") : assert_45
node _T_756 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_756 :
node _T_757 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_758 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_759 = and(_T_757, _T_758)
node _T_760 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 2, 0)
node _T_761 = shr(io.in.a.bits.source, 3)
node _T_762 = eq(_T_761, UInt<2>(0h2))
node _T_763 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_764 = and(_T_762, _T_763)
node _T_765 = leq(uncommonBits_48, UInt<3>(0h7))
node _T_766 = and(_T_764, _T_765)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0)
node _T_767 = shr(io.in.a.bits.source, 3)
node _T_768 = eq(_T_767, UInt<2>(0h3))
node _T_769 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_770 = and(_T_768, _T_769)
node _T_771 = leq(uncommonBits_49, UInt<3>(0h7))
node _T_772 = and(_T_770, _T_771)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_773 = shr(io.in.a.bits.source, 2)
node _T_774 = eq(_T_773, UInt<1>(0h0))
node _T_775 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_776 = and(_T_774, _T_775)
node _T_777 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_778 = and(_T_776, _T_777)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_779 = shr(io.in.a.bits.source, 2)
node _T_780 = eq(_T_779, UInt<1>(0h1))
node _T_781 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_782 = and(_T_780, _T_781)
node _T_783 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_784 = and(_T_782, _T_783)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0)
node _T_785 = shr(io.in.a.bits.source, 2)
node _T_786 = eq(_T_785, UInt<2>(0h2))
node _T_787 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_788 = and(_T_786, _T_787)
node _T_789 = leq(uncommonBits_52, UInt<2>(0h3))
node _T_790 = and(_T_788, _T_789)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0)
node _T_791 = shr(io.in.a.bits.source, 2)
node _T_792 = eq(_T_791, UInt<2>(0h3))
node _T_793 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_794 = and(_T_792, _T_793)
node _T_795 = leq(uncommonBits_53, UInt<2>(0h3))
node _T_796 = and(_T_794, _T_795)
node _T_797 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_798 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_799 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_800 = or(_T_760, _T_766)
node _T_801 = or(_T_800, _T_772)
node _T_802 = or(_T_801, _T_778)
node _T_803 = or(_T_802, _T_784)
node _T_804 = or(_T_803, _T_790)
node _T_805 = or(_T_804, _T_796)
node _T_806 = or(_T_805, _T_797)
node _T_807 = or(_T_806, _T_798)
node _T_808 = or(_T_807, _T_799)
node _T_809 = and(_T_759, _T_808)
node _T_810 = or(UInt<1>(0h0), _T_809)
node _T_811 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_812 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_813 = cvt(_T_812)
node _T_814 = and(_T_813, asSInt(UInt<17>(0h10000)))
node _T_815 = asSInt(_T_814)
node _T_816 = eq(_T_815, asSInt(UInt<1>(0h0)))
node _T_817 = and(_T_811, _T_816)
node _T_818 = or(UInt<1>(0h0), _T_817)
node _T_819 = and(_T_810, _T_818)
node _T_820 = asUInt(reset)
node _T_821 = eq(_T_820, UInt<1>(0h0))
when _T_821 :
node _T_822 = eq(_T_819, UInt<1>(0h0))
when _T_822 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_819, UInt<1>(0h1), "") : assert_46
node _T_823 = asUInt(reset)
node _T_824 = eq(_T_823, UInt<1>(0h0))
when _T_824 :
node _T_825 = eq(source_ok, UInt<1>(0h0))
when _T_825 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_826 = asUInt(reset)
node _T_827 = eq(_T_826, UInt<1>(0h0))
when _T_827 :
node _T_828 = eq(is_aligned, UInt<1>(0h0))
when _T_828 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_829 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_830 = asUInt(reset)
node _T_831 = eq(_T_830, UInt<1>(0h0))
when _T_831 :
node _T_832 = eq(_T_829, UInt<1>(0h0))
when _T_832 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_829, UInt<1>(0h1), "") : assert_49
node _T_833 = eq(io.in.a.bits.mask, mask)
node _T_834 = asUInt(reset)
node _T_835 = eq(_T_834, UInt<1>(0h0))
when _T_835 :
node _T_836 = eq(_T_833, UInt<1>(0h0))
when _T_836 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_833, UInt<1>(0h1), "") : assert_50
node _T_837 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_838 = asUInt(reset)
node _T_839 = eq(_T_838, UInt<1>(0h0))
when _T_839 :
node _T_840 = eq(_T_837, UInt<1>(0h0))
when _T_840 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_837, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_841 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_842 = asUInt(reset)
node _T_843 = eq(_T_842, UInt<1>(0h0))
when _T_843 :
node _T_844 = eq(_T_841, UInt<1>(0h0))
when _T_844 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_841, UInt<1>(0h1), "") : assert_52
node _source_ok_T_48 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 2, 0)
node _source_ok_T_49 = shr(io.in.d.bits.source, 3)
node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2))
node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51)
node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<3>(0h7))
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 2, 0)
node _source_ok_T_55 = shr(io.in.d.bits.source, 3)
node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3))
node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57)
node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<3>(0h7))
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_61 = shr(io.in.d.bits.source, 2)
node _source_ok_T_62 = eq(_source_ok_T_61, UInt<1>(0h0))
node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63)
node _source_ok_T_65 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_67 = shr(io.in.d.bits.source, 2)
node _source_ok_T_68 = eq(_source_ok_T_67, UInt<1>(0h1))
node _source_ok_T_69 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69)
node _source_ok_T_71 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71)
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0)
node _source_ok_T_73 = shr(io.in.d.bits.source, 2)
node _source_ok_T_74 = eq(_source_ok_T_73, UInt<2>(0h2))
node _source_ok_T_75 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75)
node _source_ok_T_77 = leq(source_ok_uncommonBits_10, UInt<2>(0h3))
node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77)
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0)
node _source_ok_T_79 = shr(io.in.d.bits.source, 2)
node _source_ok_T_80 = eq(_source_ok_T_79, UInt<2>(0h3))
node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81)
node _source_ok_T_83 = leq(source_ok_uncommonBits_11, UInt<2>(0h3))
node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83)
node _source_ok_T_85 = eq(io.in.d.bits.source, UInt<7>(0h41))
node _source_ok_T_86 = eq(io.in.d.bits.source, UInt<7>(0h40))
node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE_1 : UInt<1>[10]
connect _source_ok_WIRE_1[0], _source_ok_T_48
connect _source_ok_WIRE_1[1], _source_ok_T_54
connect _source_ok_WIRE_1[2], _source_ok_T_60
connect _source_ok_WIRE_1[3], _source_ok_T_66
connect _source_ok_WIRE_1[4], _source_ok_T_72
connect _source_ok_WIRE_1[5], _source_ok_T_78
connect _source_ok_WIRE_1[6], _source_ok_T_84
connect _source_ok_WIRE_1[7], _source_ok_T_85
connect _source_ok_WIRE_1[8], _source_ok_T_86
connect _source_ok_WIRE_1[9], _source_ok_T_87
node _source_ok_T_88 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE_1[2])
node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE_1[3])
node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE_1[4])
node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE_1[5])
node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[6])
node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[7])
node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[8])
node source_ok_1 = or(_source_ok_T_95, _source_ok_WIRE_1[9])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_845 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_845 :
node _T_846 = asUInt(reset)
node _T_847 = eq(_T_846, UInt<1>(0h0))
when _T_847 :
node _T_848 = eq(source_ok_1, UInt<1>(0h0))
when _T_848 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_849 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_850 = asUInt(reset)
node _T_851 = eq(_T_850, UInt<1>(0h0))
when _T_851 :
node _T_852 = eq(_T_849, UInt<1>(0h0))
when _T_852 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_849, UInt<1>(0h1), "") : assert_54
node _T_853 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_854 = asUInt(reset)
node _T_855 = eq(_T_854, UInt<1>(0h0))
when _T_855 :
node _T_856 = eq(_T_853, UInt<1>(0h0))
when _T_856 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_853, UInt<1>(0h1), "") : assert_55
node _T_857 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_858 = asUInt(reset)
node _T_859 = eq(_T_858, UInt<1>(0h0))
when _T_859 :
node _T_860 = eq(_T_857, UInt<1>(0h0))
when _T_860 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_857, UInt<1>(0h1), "") : assert_56
node _T_861 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_862 = asUInt(reset)
node _T_863 = eq(_T_862, UInt<1>(0h0))
when _T_863 :
node _T_864 = eq(_T_861, UInt<1>(0h0))
when _T_864 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_861, UInt<1>(0h1), "") : assert_57
node _T_865 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_865 :
node _T_866 = asUInt(reset)
node _T_867 = eq(_T_866, UInt<1>(0h0))
when _T_867 :
node _T_868 = eq(source_ok_1, UInt<1>(0h0))
when _T_868 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_869 = asUInt(reset)
node _T_870 = eq(_T_869, UInt<1>(0h0))
when _T_870 :
node _T_871 = eq(sink_ok, UInt<1>(0h0))
when _T_871 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_872 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_873 = asUInt(reset)
node _T_874 = eq(_T_873, UInt<1>(0h0))
when _T_874 :
node _T_875 = eq(_T_872, UInt<1>(0h0))
when _T_875 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_872, UInt<1>(0h1), "") : assert_60
node _T_876 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_877 = asUInt(reset)
node _T_878 = eq(_T_877, UInt<1>(0h0))
when _T_878 :
node _T_879 = eq(_T_876, UInt<1>(0h0))
when _T_879 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_876, UInt<1>(0h1), "") : assert_61
node _T_880 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_881 = asUInt(reset)
node _T_882 = eq(_T_881, UInt<1>(0h0))
when _T_882 :
node _T_883 = eq(_T_880, UInt<1>(0h0))
when _T_883 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_880, UInt<1>(0h1), "") : assert_62
node _T_884 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_885 = asUInt(reset)
node _T_886 = eq(_T_885, UInt<1>(0h0))
when _T_886 :
node _T_887 = eq(_T_884, UInt<1>(0h0))
when _T_887 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_884, UInt<1>(0h1), "") : assert_63
node _T_888 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_889 = or(UInt<1>(0h0), _T_888)
node _T_890 = asUInt(reset)
node _T_891 = eq(_T_890, UInt<1>(0h0))
when _T_891 :
node _T_892 = eq(_T_889, UInt<1>(0h0))
when _T_892 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_889, UInt<1>(0h1), "") : assert_64
node _T_893 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_893 :
node _T_894 = asUInt(reset)
node _T_895 = eq(_T_894, UInt<1>(0h0))
when _T_895 :
node _T_896 = eq(source_ok_1, UInt<1>(0h0))
when _T_896 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_897 = asUInt(reset)
node _T_898 = eq(_T_897, UInt<1>(0h0))
when _T_898 :
node _T_899 = eq(sink_ok, UInt<1>(0h0))
when _T_899 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_900 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_901 = asUInt(reset)
node _T_902 = eq(_T_901, UInt<1>(0h0))
when _T_902 :
node _T_903 = eq(_T_900, UInt<1>(0h0))
when _T_903 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_900, UInt<1>(0h1), "") : assert_67
node _T_904 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_905 = asUInt(reset)
node _T_906 = eq(_T_905, UInt<1>(0h0))
when _T_906 :
node _T_907 = eq(_T_904, UInt<1>(0h0))
when _T_907 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_904, UInt<1>(0h1), "") : assert_68
node _T_908 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_909 = asUInt(reset)
node _T_910 = eq(_T_909, UInt<1>(0h0))
when _T_910 :
node _T_911 = eq(_T_908, UInt<1>(0h0))
when _T_911 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_908, UInt<1>(0h1), "") : assert_69
node _T_912 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_913 = or(_T_912, io.in.d.bits.corrupt)
node _T_914 = asUInt(reset)
node _T_915 = eq(_T_914, UInt<1>(0h0))
when _T_915 :
node _T_916 = eq(_T_913, UInt<1>(0h0))
when _T_916 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_913, UInt<1>(0h1), "") : assert_70
node _T_917 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_918 = or(UInt<1>(0h0), _T_917)
node _T_919 = asUInt(reset)
node _T_920 = eq(_T_919, UInt<1>(0h0))
when _T_920 :
node _T_921 = eq(_T_918, UInt<1>(0h0))
when _T_921 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_918, UInt<1>(0h1), "") : assert_71
node _T_922 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_922 :
node _T_923 = asUInt(reset)
node _T_924 = eq(_T_923, UInt<1>(0h0))
when _T_924 :
node _T_925 = eq(source_ok_1, UInt<1>(0h0))
when _T_925 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_926 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_927 = asUInt(reset)
node _T_928 = eq(_T_927, UInt<1>(0h0))
when _T_928 :
node _T_929 = eq(_T_926, UInt<1>(0h0))
when _T_929 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_926, UInt<1>(0h1), "") : assert_73
node _T_930 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_931 = asUInt(reset)
node _T_932 = eq(_T_931, UInt<1>(0h0))
when _T_932 :
node _T_933 = eq(_T_930, UInt<1>(0h0))
when _T_933 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_930, UInt<1>(0h1), "") : assert_74
node _T_934 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_935 = or(UInt<1>(0h0), _T_934)
node _T_936 = asUInt(reset)
node _T_937 = eq(_T_936, UInt<1>(0h0))
when _T_937 :
node _T_938 = eq(_T_935, UInt<1>(0h0))
when _T_938 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_935, UInt<1>(0h1), "") : assert_75
node _T_939 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_939 :
node _T_940 = asUInt(reset)
node _T_941 = eq(_T_940, UInt<1>(0h0))
when _T_941 :
node _T_942 = eq(source_ok_1, UInt<1>(0h0))
when _T_942 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_943 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_944 = asUInt(reset)
node _T_945 = eq(_T_944, UInt<1>(0h0))
when _T_945 :
node _T_946 = eq(_T_943, UInt<1>(0h0))
when _T_946 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_943, UInt<1>(0h1), "") : assert_77
node _T_947 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_948 = or(_T_947, io.in.d.bits.corrupt)
node _T_949 = asUInt(reset)
node _T_950 = eq(_T_949, UInt<1>(0h0))
when _T_950 :
node _T_951 = eq(_T_948, UInt<1>(0h0))
when _T_951 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_948, UInt<1>(0h1), "") : assert_78
node _T_952 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_953 = or(UInt<1>(0h0), _T_952)
node _T_954 = asUInt(reset)
node _T_955 = eq(_T_954, UInt<1>(0h0))
when _T_955 :
node _T_956 = eq(_T_953, UInt<1>(0h0))
when _T_956 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_953, UInt<1>(0h1), "") : assert_79
node _T_957 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_957 :
node _T_958 = asUInt(reset)
node _T_959 = eq(_T_958, UInt<1>(0h0))
when _T_959 :
node _T_960 = eq(source_ok_1, UInt<1>(0h0))
when _T_960 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_961 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_962 = asUInt(reset)
node _T_963 = eq(_T_962, UInt<1>(0h0))
when _T_963 :
node _T_964 = eq(_T_961, UInt<1>(0h0))
when _T_964 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_961, UInt<1>(0h1), "") : assert_81
node _T_965 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_966 = asUInt(reset)
node _T_967 = eq(_T_966, UInt<1>(0h0))
when _T_967 :
node _T_968 = eq(_T_965, UInt<1>(0h0))
when _T_968 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_965, UInt<1>(0h1), "") : assert_82
node _T_969 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_970 = or(UInt<1>(0h0), _T_969)
node _T_971 = asUInt(reset)
node _T_972 = eq(_T_971, UInt<1>(0h0))
when _T_972 :
node _T_973 = eq(_T_970, UInt<1>(0h0))
when _T_973 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_970, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<17>(0h0)
connect _WIRE.bits.source, UInt<8>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_974 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_975 = asUInt(reset)
node _T_976 = eq(_T_975, UInt<1>(0h0))
when _T_976 :
node _T_977 = eq(_T_974, UInt<1>(0h0))
when _T_977 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_974, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<17>(0h0)
connect _WIRE_2.bits.source, UInt<8>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_978 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_979 = asUInt(reset)
node _T_980 = eq(_T_979, UInt<1>(0h0))
when _T_980 :
node _T_981 = eq(_T_978, UInt<1>(0h0))
when _T_981 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_978, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_982 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_983 = asUInt(reset)
node _T_984 = eq(_T_983, UInt<1>(0h0))
when _T_984 :
node _T_985 = eq(_T_982, UInt<1>(0h0))
when _T_985 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_982, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(UInt<1>(0h0), a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_986 = eq(a_first, UInt<1>(0h0))
node _T_987 = and(io.in.a.valid, _T_986)
when _T_987 :
node _T_988 = eq(io.in.a.bits.opcode, opcode)
node _T_989 = asUInt(reset)
node _T_990 = eq(_T_989, UInt<1>(0h0))
when _T_990 :
node _T_991 = eq(_T_988, UInt<1>(0h0))
when _T_991 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_988, UInt<1>(0h1), "") : assert_87
node _T_992 = eq(io.in.a.bits.param, param)
node _T_993 = asUInt(reset)
node _T_994 = eq(_T_993, UInt<1>(0h0))
when _T_994 :
node _T_995 = eq(_T_992, UInt<1>(0h0))
when _T_995 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_992, UInt<1>(0h1), "") : assert_88
node _T_996 = eq(io.in.a.bits.size, size)
node _T_997 = asUInt(reset)
node _T_998 = eq(_T_997, UInt<1>(0h0))
when _T_998 :
node _T_999 = eq(_T_996, UInt<1>(0h0))
when _T_999 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_996, UInt<1>(0h1), "") : assert_89
node _T_1000 = eq(io.in.a.bits.source, source)
node _T_1001 = asUInt(reset)
node _T_1002 = eq(_T_1001, UInt<1>(0h0))
when _T_1002 :
node _T_1003 = eq(_T_1000, UInt<1>(0h0))
when _T_1003 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1000, UInt<1>(0h1), "") : assert_90
node _T_1004 = eq(io.in.a.bits.address, address)
node _T_1005 = asUInt(reset)
node _T_1006 = eq(_T_1005, UInt<1>(0h0))
when _T_1006 :
node _T_1007 = eq(_T_1004, UInt<1>(0h0))
when _T_1007 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1004, UInt<1>(0h1), "") : assert_91
node _T_1008 = and(io.in.a.ready, io.in.a.valid)
node _T_1009 = and(_T_1008, a_first)
when _T_1009 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(UInt<1>(0h1), d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1010 = eq(d_first, UInt<1>(0h0))
node _T_1011 = and(io.in.d.valid, _T_1010)
when _T_1011 :
node _T_1012 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1013 = asUInt(reset)
node _T_1014 = eq(_T_1013, UInt<1>(0h0))
when _T_1014 :
node _T_1015 = eq(_T_1012, UInt<1>(0h0))
when _T_1015 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1012, UInt<1>(0h1), "") : assert_92
node _T_1016 = eq(io.in.d.bits.param, param_1)
node _T_1017 = asUInt(reset)
node _T_1018 = eq(_T_1017, UInt<1>(0h0))
when _T_1018 :
node _T_1019 = eq(_T_1016, UInt<1>(0h0))
when _T_1019 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1016, UInt<1>(0h1), "") : assert_93
node _T_1020 = eq(io.in.d.bits.size, size_1)
node _T_1021 = asUInt(reset)
node _T_1022 = eq(_T_1021, UInt<1>(0h0))
when _T_1022 :
node _T_1023 = eq(_T_1020, UInt<1>(0h0))
when _T_1023 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1020, UInt<1>(0h1), "") : assert_94
node _T_1024 = eq(io.in.d.bits.source, source_1)
node _T_1025 = asUInt(reset)
node _T_1026 = eq(_T_1025, UInt<1>(0h0))
when _T_1026 :
node _T_1027 = eq(_T_1024, UInt<1>(0h0))
when _T_1027 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1024, UInt<1>(0h1), "") : assert_95
node _T_1028 = eq(io.in.d.bits.sink, sink)
node _T_1029 = asUInt(reset)
node _T_1030 = eq(_T_1029, UInt<1>(0h0))
when _T_1030 :
node _T_1031 = eq(_T_1028, UInt<1>(0h0))
when _T_1031 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1028, UInt<1>(0h1), "") : assert_96
node _T_1032 = eq(io.in.d.bits.denied, denied)
node _T_1033 = asUInt(reset)
node _T_1034 = eq(_T_1033, UInt<1>(0h0))
when _T_1034 :
node _T_1035 = eq(_T_1032, UInt<1>(0h0))
when _T_1035 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1032, UInt<1>(0h1), "") : assert_97
node _T_1036 = and(io.in.d.ready, io.in.d.valid)
node _T_1037 = and(_T_1036, d_first)
when _T_1037 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(UInt<1>(0h0), a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(UInt<1>(0h1), d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<129>
connect a_set, UInt<129>(0h0)
wire a_set_wo_ready : UInt<129>
connect a_set_wo_ready, UInt<129>(0h0)
wire a_opcodes_set : UInt<516>
connect a_opcodes_set, UInt<516>(0h0)
wire a_sizes_set : UInt<516>
connect a_sizes_set, UInt<516>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1038 = and(io.in.a.valid, a_first_1)
node _T_1039 = and(_T_1038, UInt<1>(0h1))
when _T_1039 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1040 = and(io.in.a.ready, io.in.a.valid)
node _T_1041 = and(_T_1040, a_first_1)
node _T_1042 = and(_T_1041, UInt<1>(0h1))
when _T_1042 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1043 = dshr(inflight, io.in.a.bits.source)
node _T_1044 = bits(_T_1043, 0, 0)
node _T_1045 = eq(_T_1044, UInt<1>(0h0))
node _T_1046 = asUInt(reset)
node _T_1047 = eq(_T_1046, UInt<1>(0h0))
when _T_1047 :
node _T_1048 = eq(_T_1045, UInt<1>(0h0))
when _T_1048 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1045, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<129>
connect d_clr, UInt<129>(0h0)
wire d_clr_wo_ready : UInt<129>
connect d_clr_wo_ready, UInt<129>(0h0)
wire d_opcodes_clr : UInt<516>
connect d_opcodes_clr, UInt<516>(0h0)
wire d_sizes_clr : UInt<516>
connect d_sizes_clr, UInt<516>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1049 = and(io.in.d.valid, d_first_1)
node _T_1050 = and(_T_1049, UInt<1>(0h1))
node _T_1051 = eq(d_release_ack, UInt<1>(0h0))
node _T_1052 = and(_T_1050, _T_1051)
when _T_1052 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1053 = and(io.in.d.ready, io.in.d.valid)
node _T_1054 = and(_T_1053, d_first_1)
node _T_1055 = and(_T_1054, UInt<1>(0h1))
node _T_1056 = eq(d_release_ack, UInt<1>(0h0))
node _T_1057 = and(_T_1055, _T_1056)
when _T_1057 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1058 = and(io.in.d.valid, d_first_1)
node _T_1059 = and(_T_1058, UInt<1>(0h1))
node _T_1060 = eq(d_release_ack, UInt<1>(0h0))
node _T_1061 = and(_T_1059, _T_1060)
when _T_1061 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1062 = dshr(inflight, io.in.d.bits.source)
node _T_1063 = bits(_T_1062, 0, 0)
node _T_1064 = or(_T_1063, same_cycle_resp)
node _T_1065 = asUInt(reset)
node _T_1066 = eq(_T_1065, UInt<1>(0h0))
when _T_1066 :
node _T_1067 = eq(_T_1064, UInt<1>(0h0))
when _T_1067 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1064, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1068 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1069 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1070 = or(_T_1068, _T_1069)
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_100
node _T_1074 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1075 = asUInt(reset)
node _T_1076 = eq(_T_1075, UInt<1>(0h0))
when _T_1076 :
node _T_1077 = eq(_T_1074, UInt<1>(0h0))
when _T_1077 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1074, UInt<1>(0h1), "") : assert_101
else :
node _T_1078 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1079 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1080 = or(_T_1078, _T_1079)
node _T_1081 = asUInt(reset)
node _T_1082 = eq(_T_1081, UInt<1>(0h0))
when _T_1082 :
node _T_1083 = eq(_T_1080, UInt<1>(0h0))
when _T_1083 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1080, UInt<1>(0h1), "") : assert_102
node _T_1084 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(_T_1084, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1084, UInt<1>(0h1), "") : assert_103
node _T_1088 = and(io.in.d.valid, d_first_1)
node _T_1089 = and(_T_1088, a_first_1)
node _T_1090 = and(_T_1089, io.in.a.valid)
node _T_1091 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1092 = and(_T_1090, _T_1091)
node _T_1093 = eq(d_release_ack, UInt<1>(0h0))
node _T_1094 = and(_T_1092, _T_1093)
when _T_1094 :
node _T_1095 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1096 = or(_T_1095, io.in.a.ready)
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(_T_1096, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1096, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_64
node _T_1100 = orr(inflight)
node _T_1101 = eq(_T_1100, UInt<1>(0h0))
node _T_1102 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1103 = or(_T_1101, _T_1102)
node _T_1104 = lt(watchdog, plusarg_reader.out)
node _T_1105 = or(_T_1103, _T_1104)
node _T_1106 = asUInt(reset)
node _T_1107 = eq(_T_1106, UInt<1>(0h0))
when _T_1107 :
node _T_1108 = eq(_T_1105, UInt<1>(0h0))
when _T_1108 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1105, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1109 = and(io.in.a.ready, io.in.a.valid)
node _T_1110 = and(io.in.d.ready, io.in.d.valid)
node _T_1111 = or(_T_1109, _T_1110)
when _T_1111 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<17>(0h0)
connect _c_first_WIRE.bits.source, UInt<8>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<17>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(UInt<1>(0h1), d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<129>
connect c_set, UInt<129>(0h0)
wire c_set_wo_ready : UInt<129>
connect c_set_wo_ready, UInt<129>(0h0)
wire c_opcodes_set : UInt<516>
connect c_opcodes_set, UInt<516>(0h0)
wire c_sizes_set : UInt<516>
connect c_sizes_set, UInt<516>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<17>(0h0)
connect _WIRE_6.bits.source, UInt<8>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1112 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<17>(0h0)
connect _WIRE_8.bits.source, UInt<8>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1113 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1114 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1115 = and(_T_1113, _T_1114)
node _T_1116 = and(_T_1112, _T_1115)
when _T_1116 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<17>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<17>(0h0)
connect _WIRE_10.bits.source, UInt<8>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1117 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1118 = and(_T_1117, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<17>(0h0)
connect _WIRE_12.bits.source, UInt<8>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1119 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1120 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1121 = and(_T_1119, _T_1120)
node _T_1122 = and(_T_1118, _T_1121)
when _T_1122 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<17>(0h0)
connect _c_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<17>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<17>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<17>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<17>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<17>(0h0)
connect _WIRE_14.bits.source, UInt<8>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1123 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1124 = bits(_T_1123, 0, 0)
node _T_1125 = eq(_T_1124, UInt<1>(0h0))
node _T_1126 = asUInt(reset)
node _T_1127 = eq(_T_1126, UInt<1>(0h0))
when _T_1127 :
node _T_1128 = eq(_T_1125, UInt<1>(0h0))
when _T_1128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1125, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<17>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<17>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<129>
connect d_clr_1, UInt<129>(0h0)
wire d_clr_wo_ready_1 : UInt<129>
connect d_clr_wo_ready_1, UInt<129>(0h0)
wire d_opcodes_clr_1 : UInt<516>
connect d_opcodes_clr_1, UInt<516>(0h0)
wire d_sizes_clr_1 : UInt<516>
connect d_sizes_clr_1, UInt<516>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1129 = and(io.in.d.valid, d_first_2)
node _T_1130 = and(_T_1129, UInt<1>(0h1))
node _T_1131 = and(_T_1130, d_release_ack_1)
when _T_1131 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1132 = and(io.in.d.ready, io.in.d.valid)
node _T_1133 = and(_T_1132, d_first_2)
node _T_1134 = and(_T_1133, UInt<1>(0h1))
node _T_1135 = and(_T_1134, d_release_ack_1)
when _T_1135 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1136 = and(io.in.d.valid, d_first_2)
node _T_1137 = and(_T_1136, UInt<1>(0h1))
node _T_1138 = and(_T_1137, d_release_ack_1)
when _T_1138 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<17>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<17>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<17>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1139 = dshr(inflight_1, io.in.d.bits.source)
node _T_1140 = bits(_T_1139, 0, 0)
node _T_1141 = or(_T_1140, same_cycle_resp_1)
node _T_1142 = asUInt(reset)
node _T_1143 = eq(_T_1142, UInt<1>(0h0))
when _T_1143 :
node _T_1144 = eq(_T_1141, UInt<1>(0h0))
when _T_1144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1141, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<17>(0h0)
connect _WIRE_16.bits.source, UInt<8>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1145 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1146 = asUInt(reset)
node _T_1147 = eq(_T_1146, UInt<1>(0h0))
when _T_1147 :
node _T_1148 = eq(_T_1145, UInt<1>(0h0))
when _T_1148 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1145, UInt<1>(0h1), "") : assert_108
else :
node _T_1149 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1150 = asUInt(reset)
node _T_1151 = eq(_T_1150, UInt<1>(0h0))
when _T_1151 :
node _T_1152 = eq(_T_1149, UInt<1>(0h0))
when _T_1152 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1149, UInt<1>(0h1), "") : assert_109
node _T_1153 = and(io.in.d.valid, d_first_2)
node _T_1154 = and(_T_1153, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<17>(0h0)
connect _WIRE_18.bits.source, UInt<8>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1155 = and(_T_1154, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<17>(0h0)
connect _WIRE_20.bits.source, UInt<8>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1156 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1157 = and(_T_1155, _T_1156)
node _T_1158 = and(_T_1157, d_release_ack_1)
node _T_1159 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1160 = and(_T_1158, _T_1159)
when _T_1160 :
node _T_1161 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<17>(0h0)
connect _WIRE_22.bits.source, UInt<8>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1162 = or(_T_1161, _WIRE_23.ready)
node _T_1163 = asUInt(reset)
node _T_1164 = eq(_T_1163, UInt<1>(0h0))
when _T_1164 :
node _T_1165 = eq(_T_1162, UInt<1>(0h0))
when _T_1165 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1162, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_65
node _T_1166 = orr(inflight_1)
node _T_1167 = eq(_T_1166, UInt<1>(0h0))
node _T_1168 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1169 = or(_T_1167, _T_1168)
node _T_1170 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1171 = or(_T_1169, _T_1170)
node _T_1172 = asUInt(reset)
node _T_1173 = eq(_T_1172, UInt<1>(0h0))
when _T_1173 :
node _T_1174 = eq(_T_1171, UInt<1>(0h0))
when _T_1174 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1171, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<17>(0h0)
connect _WIRE_24.bits.source, UInt<8>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1175 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1176 = and(io.in.d.ready, io.in.d.valid)
node _T_1177 = or(_T_1175, _T_1176)
when _T_1177 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_32( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [16:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire d_release_ack = 1'h0; // @[Monitor.scala:673:46]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire d_release_ack_1 = 1'h0; // @[Monitor.scala:783:46]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] a_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] a_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] a_first_beats1_1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] a_first_count_1 = 3'h0; // @[Edges.scala:234:25]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire d_first_beats1_opdata = 1'h1; // @[Edges.scala:106:36]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire d_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:106:36]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire d_first_beats1_opdata_2 = 1'h1; // @[Edges.scala:106:36]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode = 3'h1; // @[Monitor.scala:36:7]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [515:0] _inflight_opcodes_T_4 = 516'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:815:62]
wire [515:0] _inflight_sizes_T_4 = 516'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:816:58]
wire [128:0] _inflight_T_4 = 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:814:46]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_first_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_first_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_first_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_first_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_set_wo_ready_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_set_wo_ready_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_opcodes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_opcodes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_sizes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_sizes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_opcodes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_opcodes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_sizes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_sizes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_probe_ack_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_probe_ack_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_probe_ack_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_probe_ack_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _same_cycle_resp_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _same_cycle_resp_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _same_cycle_resp_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _same_cycle_resp_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _same_cycle_resp_WIRE_4_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _same_cycle_resp_WIRE_5_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34]
wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34]
wire [515:0] d_opcodes_clr_1 = 516'h0; // @[Monitor.scala:776:34]
wire [515:0] d_sizes_clr_1 = 516'h0; // @[Monitor.scala:777:34]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34]
wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34]
wire [128:0] d_clr_1 = 129'h0; // @[Monitor.scala:774:34]
wire [128:0] d_clr_wo_ready_1 = 129'h0; // @[Monitor.scala:775:34]
wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54]
wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52]
wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79]
wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35]
wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_25 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_31 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_14 = _source_ok_T_13 == 6'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 6'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_26 = _source_ok_T_25 == 6'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 6'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_47 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [16:0] _is_aligned_T = {11'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [2:0] uncommonBits = _uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_1 = _uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_7 = _uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_30 = _uncommonBits_T_30[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_31 = _uncommonBits_T_31[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_36 = _uncommonBits_T_36[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_37 = _uncommonBits_T_37[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_42 = _uncommonBits_T_42[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_43 = _uncommonBits_T_43[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_48 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_48; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_54; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_60; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_61 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_67 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_73 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_79 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_62 = _source_ok_T_61 == 6'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_66; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_68 = _source_ok_T_67 == 6'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_72; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_74 = _source_ok_T_73 == 6'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_78; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_80 = _source_ok_T_79 == 6'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_84; // @[Parameters.scala:1138:31]
wire _source_ok_T_85 = io_in_d_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_85; // @[Parameters.scala:1138:31]
wire _source_ok_T_86 = io_in_d_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_86; // @[Parameters.scala:1138:31]
wire _source_ok_T_87 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_87; // @[Parameters.scala:1138:31]
wire _source_ok_T_88 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_89 = _source_ok_T_88 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_90 = _source_ok_T_89 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_91 = _source_ok_T_90 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_95 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1109 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1109; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1109; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] _a_first_counter_T = a_first ? 3'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [16:0] address; // @[Monitor.scala:391:22]
wire _T_1177 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1177; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1177; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1177; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1 = d_first_beats1_decode; // @[Edges.scala:220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg [128:0] inflight; // @[Monitor.scala:614:27]
reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [515:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? 3'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_decode_1; // @[Edges.scala:220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [128:0] a_set; // @[Monitor.scala:626:34]
wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [515:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [255:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1042 = _T_1109 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1042 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1042 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1042 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1042 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1042 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [128:0] d_clr; // @[Monitor.scala:664:34]
wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _T_1088 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [255:0] _GEN_4 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1088 ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1055 = _T_1177 & d_first_1; // @[Decoupled.scala:51:35]
assign d_clr = _T_1055 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1055 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,89}, :680:{21,76}]
wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1055 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [515:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [128:0] inflight_1; // @[Monitor.scala:726:35]
wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_decode_2; // @[Edges.scala:220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113]
wire [128:0] _inflight_T_5 = _inflight_T_3; // @[Monitor.scala:814:{35,44}]
wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3; // @[Monitor.scala:815:{43,60}]
wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3; // @[Monitor.scala:816:{41,56}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncQueue_5 :
output io : { flip enq_clock : Clock, flip enq_reset : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, flip deq_clock : Clock, flip deq_reset : UInt<1>, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}}
inst source of AsyncQueueSource_Phit_5
connect source.clock, io.enq_clock
connect source.reset, io.enq_reset
inst sink of AsyncQueueSink_Phit_5
connect sink.clock, io.deq_clock
connect sink.reset, io.deq_reset
connect source.io.enq, io.enq
connect io.deq.bits, sink.io.deq.bits
connect io.deq.valid, sink.io.deq.valid
connect sink.io.deq.ready, io.deq.ready
connect sink.io.async, source.io.async | module AsyncQueue_5( // @[AsyncQueue.scala:226:7]
input io_enq_clock, // @[AsyncQueue.scala:227:14]
input io_enq_reset, // @[AsyncQueue.scala:227:14]
output io_enq_ready, // @[AsyncQueue.scala:227:14]
input io_enq_valid, // @[AsyncQueue.scala:227:14]
input [31:0] io_enq_bits_phit, // @[AsyncQueue.scala:227:14]
input io_deq_clock, // @[AsyncQueue.scala:227:14]
input io_deq_reset, // @[AsyncQueue.scala:227:14]
input io_deq_ready, // @[AsyncQueue.scala:227:14]
output io_deq_valid, // @[AsyncQueue.scala:227:14]
output [31:0] io_deq_bits_phit // @[AsyncQueue.scala:227:14]
);
wire [3:0] _sink_io_async_ridx; // @[AsyncQueue.scala:229:70]
wire _sink_io_async_safe_ridx_valid; // @[AsyncQueue.scala:229:70]
wire _sink_io_async_safe_sink_reset_n; // @[AsyncQueue.scala:229:70]
wire [31:0] _source_io_async_mem_0_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_1_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_2_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_3_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_4_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_5_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_6_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_7_phit; // @[AsyncQueue.scala:228:70]
wire [3:0] _source_io_async_widx; // @[AsyncQueue.scala:228:70]
wire _source_io_async_safe_widx_valid; // @[AsyncQueue.scala:228:70]
wire _source_io_async_safe_source_reset_n; // @[AsyncQueue.scala:228:70]
wire io_enq_clock_0 = io_enq_clock; // @[AsyncQueue.scala:226:7]
wire io_enq_reset_0 = io_enq_reset; // @[AsyncQueue.scala:226:7]
wire io_enq_valid_0 = io_enq_valid; // @[AsyncQueue.scala:226:7]
wire [31:0] io_enq_bits_phit_0 = io_enq_bits_phit; // @[AsyncQueue.scala:226:7]
wire io_deq_clock_0 = io_deq_clock; // @[AsyncQueue.scala:226:7]
wire io_deq_reset_0 = io_deq_reset; // @[AsyncQueue.scala:226:7]
wire io_deq_ready_0 = io_deq_ready; // @[AsyncQueue.scala:226:7]
wire io_enq_ready_0; // @[AsyncQueue.scala:226:7]
wire [31:0] io_deq_bits_phit_0; // @[AsyncQueue.scala:226:7]
wire io_deq_valid_0; // @[AsyncQueue.scala:226:7]
AsyncQueueSource_Phit_5 source ( // @[AsyncQueue.scala:228:70]
.clock (io_enq_clock_0), // @[AsyncQueue.scala:226:7]
.reset (io_enq_reset_0), // @[AsyncQueue.scala:226:7]
.io_enq_ready (io_enq_ready_0),
.io_enq_valid (io_enq_valid_0), // @[AsyncQueue.scala:226:7]
.io_enq_bits_phit (io_enq_bits_phit_0), // @[AsyncQueue.scala:226:7]
.io_async_mem_0_phit (_source_io_async_mem_0_phit),
.io_async_mem_1_phit (_source_io_async_mem_1_phit),
.io_async_mem_2_phit (_source_io_async_mem_2_phit),
.io_async_mem_3_phit (_source_io_async_mem_3_phit),
.io_async_mem_4_phit (_source_io_async_mem_4_phit),
.io_async_mem_5_phit (_source_io_async_mem_5_phit),
.io_async_mem_6_phit (_source_io_async_mem_6_phit),
.io_async_mem_7_phit (_source_io_async_mem_7_phit),
.io_async_ridx (_sink_io_async_ridx), // @[AsyncQueue.scala:229:70]
.io_async_widx (_source_io_async_widx),
.io_async_safe_ridx_valid (_sink_io_async_safe_ridx_valid), // @[AsyncQueue.scala:229:70]
.io_async_safe_widx_valid (_source_io_async_safe_widx_valid),
.io_async_safe_source_reset_n (_source_io_async_safe_source_reset_n),
.io_async_safe_sink_reset_n (_sink_io_async_safe_sink_reset_n) // @[AsyncQueue.scala:229:70]
); // @[AsyncQueue.scala:228:70]
AsyncQueueSink_Phit_5 sink ( // @[AsyncQueue.scala:229:70]
.clock (io_deq_clock_0), // @[AsyncQueue.scala:226:7]
.reset (io_deq_reset_0), // @[AsyncQueue.scala:226:7]
.io_deq_ready (io_deq_ready_0), // @[AsyncQueue.scala:226:7]
.io_deq_valid (io_deq_valid_0),
.io_deq_bits_phit (io_deq_bits_phit_0),
.io_async_mem_0_phit (_source_io_async_mem_0_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_1_phit (_source_io_async_mem_1_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_2_phit (_source_io_async_mem_2_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_3_phit (_source_io_async_mem_3_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_4_phit (_source_io_async_mem_4_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_5_phit (_source_io_async_mem_5_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_6_phit (_source_io_async_mem_6_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_7_phit (_source_io_async_mem_7_phit), // @[AsyncQueue.scala:228:70]
.io_async_ridx (_sink_io_async_ridx),
.io_async_widx (_source_io_async_widx), // @[AsyncQueue.scala:228:70]
.io_async_safe_ridx_valid (_sink_io_async_safe_ridx_valid),
.io_async_safe_widx_valid (_source_io_async_safe_widx_valid), // @[AsyncQueue.scala:228:70]
.io_async_safe_source_reset_n (_source_io_async_safe_source_reset_n), // @[AsyncQueue.scala:228:70]
.io_async_safe_sink_reset_n (_sink_io_async_safe_sink_reset_n)
); // @[AsyncQueue.scala:229:70]
assign io_enq_ready = io_enq_ready_0; // @[AsyncQueue.scala:226:7]
assign io_deq_valid = io_deq_valid_0; // @[AsyncQueue.scala:226:7]
assign io_deq_bits_phit = io_deq_bits_phit_0; // @[AsyncQueue.scala:226:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_476 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_220
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_476( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_220 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ITLB_3 :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<3>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<3>, cmd : UInt<5>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[2]}}, flip kill : UInt<1>}
invalidate io.ptw.customCSRs.csrs[0].sdata
invalidate io.ptw.customCSRs.csrs[0].set
invalidate io.ptw.customCSRs.csrs[0].stall
invalidate io.ptw.customCSRs.csrs[0].value
invalidate io.ptw.customCSRs.csrs[0].wdata
invalidate io.ptw.customCSRs.csrs[0].wen
invalidate io.ptw.customCSRs.csrs[0].ren
invalidate io.ptw.customCSRs.csrs[1].sdata
invalidate io.ptw.customCSRs.csrs[1].set
invalidate io.ptw.customCSRs.csrs[1].stall
invalidate io.ptw.customCSRs.csrs[1].value
invalidate io.ptw.customCSRs.csrs[1].wdata
invalidate io.ptw.customCSRs.csrs[1].wen
invalidate io.ptw.customCSRs.csrs[1].ren
node vpn = bits(io.req.bits.vaddr, 38, 12)
reg sectored_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[4], valid : UInt<1>[4]}[8][1], clock
reg superpage_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[4], clock
reg special_entry : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}, clock
regreset state : UInt<2>, clock, reset, UInt<2>(0h0)
reg r_refill_tag : UInt<27>, clock
reg r_superpage_repl_addr : UInt<2>, clock
reg r_sectored_repl_addr : UInt<3>, clock
reg r_sectored_hit : { valid : UInt<1>, bits : UInt<3>}, clock
reg r_superpage_hit : { valid : UInt<1>, bits : UInt<2>}, clock
reg r_vstage1_en : UInt<1>, clock
reg r_stage2_en : UInt<1>, clock
reg r_need_gpa : UInt<1>, clock
reg r_gpa_valid : UInt<1>, clock
reg r_gpa : UInt<39>, clock
reg r_gpa_vpn : UInt<27>, clock
reg r_gpa_is_pte : UInt<1>, clock
node priv_v = and(UInt<1>(0h0), io.req.bits.v)
node priv_s = bits(io.req.bits.prv, 0, 0)
node priv_uses_vm = leq(io.req.bits.prv, UInt<1>(0h1))
node satp = mux(priv_v, io.ptw.vsatp, io.ptw.ptbr)
node _stage1_en_T = bits(satp.mode, 3, 3)
node stage1_en = and(UInt<1>(0h1), _stage1_en_T)
node _vstage1_en_T = and(UInt<1>(0h0), priv_v)
node _vstage1_en_T_1 = bits(io.ptw.vsatp.mode, 3, 3)
node vstage1_en = and(_vstage1_en_T, _vstage1_en_T_1)
node _stage2_en_T = and(UInt<1>(0h0), priv_v)
node _stage2_en_T_1 = bits(io.ptw.hgatp.mode, 3, 3)
node stage2_en = and(_stage2_en_T, _stage2_en_T_1)
node _vm_enabled_T = or(stage1_en, stage2_en)
node _vm_enabled_T_1 = and(_vm_enabled_T, priv_uses_vm)
node _vm_enabled_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0))
node vm_enabled = and(_vm_enabled_T_1, _vm_enabled_T_2)
regreset v_entries_use_stage1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _vsatp_mode_mismatch_T = neq(vstage1_en, v_entries_use_stage1)
node _vsatp_mode_mismatch_T_1 = and(priv_v, _vsatp_mode_mismatch_T)
node _vsatp_mode_mismatch_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0))
node vsatp_mode_mismatch = and(_vsatp_mode_mismatch_T_1, _vsatp_mode_mismatch_T_2)
node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0)
node do_refill = and(UInt<1>(0h1), io.ptw.resp.valid)
node _invalidate_refill_T = eq(state, UInt<2>(0h1))
node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3))
node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1)
node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid)
node _mpu_ppn_T = and(vm_enabled, UInt<1>(0h1))
wire _mpu_ppn_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _mpu_ppn_WIRE_1 : UInt<42>
connect _mpu_ppn_WIRE_1, special_entry.data[0]
node _mpu_ppn_T_1 = bits(_mpu_ppn_WIRE_1, 0, 0)
connect _mpu_ppn_WIRE.fragmented_superpage, _mpu_ppn_T_1
node _mpu_ppn_T_2 = bits(_mpu_ppn_WIRE_1, 1, 1)
connect _mpu_ppn_WIRE.c, _mpu_ppn_T_2
node _mpu_ppn_T_3 = bits(_mpu_ppn_WIRE_1, 2, 2)
connect _mpu_ppn_WIRE.eff, _mpu_ppn_T_3
node _mpu_ppn_T_4 = bits(_mpu_ppn_WIRE_1, 3, 3)
connect _mpu_ppn_WIRE.paa, _mpu_ppn_T_4
node _mpu_ppn_T_5 = bits(_mpu_ppn_WIRE_1, 4, 4)
connect _mpu_ppn_WIRE.pal, _mpu_ppn_T_5
node _mpu_ppn_T_6 = bits(_mpu_ppn_WIRE_1, 5, 5)
connect _mpu_ppn_WIRE.ppp, _mpu_ppn_T_6
node _mpu_ppn_T_7 = bits(_mpu_ppn_WIRE_1, 6, 6)
connect _mpu_ppn_WIRE.pr, _mpu_ppn_T_7
node _mpu_ppn_T_8 = bits(_mpu_ppn_WIRE_1, 7, 7)
connect _mpu_ppn_WIRE.px, _mpu_ppn_T_8
node _mpu_ppn_T_9 = bits(_mpu_ppn_WIRE_1, 8, 8)
connect _mpu_ppn_WIRE.pw, _mpu_ppn_T_9
node _mpu_ppn_T_10 = bits(_mpu_ppn_WIRE_1, 9, 9)
connect _mpu_ppn_WIRE.hr, _mpu_ppn_T_10
node _mpu_ppn_T_11 = bits(_mpu_ppn_WIRE_1, 10, 10)
connect _mpu_ppn_WIRE.hx, _mpu_ppn_T_11
node _mpu_ppn_T_12 = bits(_mpu_ppn_WIRE_1, 11, 11)
connect _mpu_ppn_WIRE.hw, _mpu_ppn_T_12
node _mpu_ppn_T_13 = bits(_mpu_ppn_WIRE_1, 12, 12)
connect _mpu_ppn_WIRE.sr, _mpu_ppn_T_13
node _mpu_ppn_T_14 = bits(_mpu_ppn_WIRE_1, 13, 13)
connect _mpu_ppn_WIRE.sx, _mpu_ppn_T_14
node _mpu_ppn_T_15 = bits(_mpu_ppn_WIRE_1, 14, 14)
connect _mpu_ppn_WIRE.sw, _mpu_ppn_T_15
node _mpu_ppn_T_16 = bits(_mpu_ppn_WIRE_1, 15, 15)
connect _mpu_ppn_WIRE.gf, _mpu_ppn_T_16
node _mpu_ppn_T_17 = bits(_mpu_ppn_WIRE_1, 16, 16)
connect _mpu_ppn_WIRE.pf, _mpu_ppn_T_17
node _mpu_ppn_T_18 = bits(_mpu_ppn_WIRE_1, 17, 17)
connect _mpu_ppn_WIRE.ae_stage2, _mpu_ppn_T_18
node _mpu_ppn_T_19 = bits(_mpu_ppn_WIRE_1, 18, 18)
connect _mpu_ppn_WIRE.ae_final, _mpu_ppn_T_19
node _mpu_ppn_T_20 = bits(_mpu_ppn_WIRE_1, 19, 19)
connect _mpu_ppn_WIRE.ae_ptw, _mpu_ppn_T_20
node _mpu_ppn_T_21 = bits(_mpu_ppn_WIRE_1, 20, 20)
connect _mpu_ppn_WIRE.g, _mpu_ppn_T_21
node _mpu_ppn_T_22 = bits(_mpu_ppn_WIRE_1, 21, 21)
connect _mpu_ppn_WIRE.u, _mpu_ppn_T_22
node _mpu_ppn_T_23 = bits(_mpu_ppn_WIRE_1, 41, 22)
connect _mpu_ppn_WIRE.ppn, _mpu_ppn_T_23
inst mpu_ppn_barrier of OptimizationBarrier_TLBEntryData_98
connect mpu_ppn_barrier.clock, clock
connect mpu_ppn_barrier.reset, reset
connect mpu_ppn_barrier.io.x.fragmented_superpage, _mpu_ppn_WIRE.fragmented_superpage
connect mpu_ppn_barrier.io.x.c, _mpu_ppn_WIRE.c
connect mpu_ppn_barrier.io.x.eff, _mpu_ppn_WIRE.eff
connect mpu_ppn_barrier.io.x.paa, _mpu_ppn_WIRE.paa
connect mpu_ppn_barrier.io.x.pal, _mpu_ppn_WIRE.pal
connect mpu_ppn_barrier.io.x.ppp, _mpu_ppn_WIRE.ppp
connect mpu_ppn_barrier.io.x.pr, _mpu_ppn_WIRE.pr
connect mpu_ppn_barrier.io.x.px, _mpu_ppn_WIRE.px
connect mpu_ppn_barrier.io.x.pw, _mpu_ppn_WIRE.pw
connect mpu_ppn_barrier.io.x.hr, _mpu_ppn_WIRE.hr
connect mpu_ppn_barrier.io.x.hx, _mpu_ppn_WIRE.hx
connect mpu_ppn_barrier.io.x.hw, _mpu_ppn_WIRE.hw
connect mpu_ppn_barrier.io.x.sr, _mpu_ppn_WIRE.sr
connect mpu_ppn_barrier.io.x.sx, _mpu_ppn_WIRE.sx
connect mpu_ppn_barrier.io.x.sw, _mpu_ppn_WIRE.sw
connect mpu_ppn_barrier.io.x.gf, _mpu_ppn_WIRE.gf
connect mpu_ppn_barrier.io.x.pf, _mpu_ppn_WIRE.pf
connect mpu_ppn_barrier.io.x.ae_stage2, _mpu_ppn_WIRE.ae_stage2
connect mpu_ppn_barrier.io.x.ae_final, _mpu_ppn_WIRE.ae_final
connect mpu_ppn_barrier.io.x.ae_ptw, _mpu_ppn_WIRE.ae_ptw
connect mpu_ppn_barrier.io.x.g, _mpu_ppn_WIRE.g
connect mpu_ppn_barrier.io.x.u, _mpu_ppn_WIRE.u
connect mpu_ppn_barrier.io.x.ppn, _mpu_ppn_WIRE.ppn
node mpu_ppn_res = shr(mpu_ppn_barrier.io.y.ppn, 18)
node _mpu_ppn_ignore_T = lt(special_entry.level, UInt<1>(0h1))
node mpu_ppn_ignore = or(_mpu_ppn_ignore_T, UInt<1>(0h0))
node _mpu_ppn_T_24 = mux(mpu_ppn_ignore, vpn, UInt<1>(0h0))
node _mpu_ppn_T_25 = or(_mpu_ppn_T_24, mpu_ppn_barrier.io.y.ppn)
node _mpu_ppn_T_26 = bits(_mpu_ppn_T_25, 17, 9)
node _mpu_ppn_T_27 = cat(mpu_ppn_res, _mpu_ppn_T_26)
node _mpu_ppn_ignore_T_1 = lt(special_entry.level, UInt<2>(0h2))
node mpu_ppn_ignore_1 = or(_mpu_ppn_ignore_T_1, UInt<1>(0h0))
node _mpu_ppn_T_28 = mux(mpu_ppn_ignore_1, vpn, UInt<1>(0h0))
node _mpu_ppn_T_29 = or(_mpu_ppn_T_28, mpu_ppn_barrier.io.y.ppn)
node _mpu_ppn_T_30 = bits(_mpu_ppn_T_29, 8, 0)
node _mpu_ppn_T_31 = cat(_mpu_ppn_T_27, _mpu_ppn_T_30)
node _mpu_ppn_T_32 = shr(io.req.bits.vaddr, 12)
node _mpu_ppn_T_33 = mux(_mpu_ppn_T, _mpu_ppn_T_31, _mpu_ppn_T_32)
node mpu_ppn = mux(do_refill, refill_ppn, _mpu_ppn_T_33)
node _mpu_physaddr_T = bits(io.req.bits.vaddr, 11, 0)
node mpu_physaddr = cat(mpu_ppn, _mpu_physaddr_T)
node _mpu_priv_T = or(do_refill, io.req.bits.passthrough)
node _mpu_priv_T_1 = and(UInt<1>(0h1), _mpu_priv_T)
node _mpu_priv_T_2 = cat(io.ptw.status.debug, io.req.bits.prv)
node mpu_priv = mux(_mpu_priv_T_1, UInt<1>(0h1), _mpu_priv_T_2)
inst pmp of PMPChecker_s4_1
connect pmp.clock, clock
connect pmp.reset, reset
connect pmp.io.addr, mpu_physaddr
connect pmp.io.size, io.req.bits.size
connect pmp.io.pmp[0].mask, io.ptw.pmp[0].mask
connect pmp.io.pmp[0].addr, io.ptw.pmp[0].addr
connect pmp.io.pmp[0].cfg.r, io.ptw.pmp[0].cfg.r
connect pmp.io.pmp[0].cfg.w, io.ptw.pmp[0].cfg.w
connect pmp.io.pmp[0].cfg.x, io.ptw.pmp[0].cfg.x
connect pmp.io.pmp[0].cfg.a, io.ptw.pmp[0].cfg.a
connect pmp.io.pmp[0].cfg.res, io.ptw.pmp[0].cfg.res
connect pmp.io.pmp[0].cfg.l, io.ptw.pmp[0].cfg.l
connect pmp.io.pmp[1].mask, io.ptw.pmp[1].mask
connect pmp.io.pmp[1].addr, io.ptw.pmp[1].addr
connect pmp.io.pmp[1].cfg.r, io.ptw.pmp[1].cfg.r
connect pmp.io.pmp[1].cfg.w, io.ptw.pmp[1].cfg.w
connect pmp.io.pmp[1].cfg.x, io.ptw.pmp[1].cfg.x
connect pmp.io.pmp[1].cfg.a, io.ptw.pmp[1].cfg.a
connect pmp.io.pmp[1].cfg.res, io.ptw.pmp[1].cfg.res
connect pmp.io.pmp[1].cfg.l, io.ptw.pmp[1].cfg.l
connect pmp.io.pmp[2].mask, io.ptw.pmp[2].mask
connect pmp.io.pmp[2].addr, io.ptw.pmp[2].addr
connect pmp.io.pmp[2].cfg.r, io.ptw.pmp[2].cfg.r
connect pmp.io.pmp[2].cfg.w, io.ptw.pmp[2].cfg.w
connect pmp.io.pmp[2].cfg.x, io.ptw.pmp[2].cfg.x
connect pmp.io.pmp[2].cfg.a, io.ptw.pmp[2].cfg.a
connect pmp.io.pmp[2].cfg.res, io.ptw.pmp[2].cfg.res
connect pmp.io.pmp[2].cfg.l, io.ptw.pmp[2].cfg.l
connect pmp.io.pmp[3].mask, io.ptw.pmp[3].mask
connect pmp.io.pmp[3].addr, io.ptw.pmp[3].addr
connect pmp.io.pmp[3].cfg.r, io.ptw.pmp[3].cfg.r
connect pmp.io.pmp[3].cfg.w, io.ptw.pmp[3].cfg.w
connect pmp.io.pmp[3].cfg.x, io.ptw.pmp[3].cfg.x
connect pmp.io.pmp[3].cfg.a, io.ptw.pmp[3].cfg.a
connect pmp.io.pmp[3].cfg.res, io.ptw.pmp[3].cfg.res
connect pmp.io.pmp[3].cfg.l, io.ptw.pmp[3].cfg.l
connect pmp.io.pmp[4].mask, io.ptw.pmp[4].mask
connect pmp.io.pmp[4].addr, io.ptw.pmp[4].addr
connect pmp.io.pmp[4].cfg.r, io.ptw.pmp[4].cfg.r
connect pmp.io.pmp[4].cfg.w, io.ptw.pmp[4].cfg.w
connect pmp.io.pmp[4].cfg.x, io.ptw.pmp[4].cfg.x
connect pmp.io.pmp[4].cfg.a, io.ptw.pmp[4].cfg.a
connect pmp.io.pmp[4].cfg.res, io.ptw.pmp[4].cfg.res
connect pmp.io.pmp[4].cfg.l, io.ptw.pmp[4].cfg.l
connect pmp.io.pmp[5].mask, io.ptw.pmp[5].mask
connect pmp.io.pmp[5].addr, io.ptw.pmp[5].addr
connect pmp.io.pmp[5].cfg.r, io.ptw.pmp[5].cfg.r
connect pmp.io.pmp[5].cfg.w, io.ptw.pmp[5].cfg.w
connect pmp.io.pmp[5].cfg.x, io.ptw.pmp[5].cfg.x
connect pmp.io.pmp[5].cfg.a, io.ptw.pmp[5].cfg.a
connect pmp.io.pmp[5].cfg.res, io.ptw.pmp[5].cfg.res
connect pmp.io.pmp[5].cfg.l, io.ptw.pmp[5].cfg.l
connect pmp.io.pmp[6].mask, io.ptw.pmp[6].mask
connect pmp.io.pmp[6].addr, io.ptw.pmp[6].addr
connect pmp.io.pmp[6].cfg.r, io.ptw.pmp[6].cfg.r
connect pmp.io.pmp[6].cfg.w, io.ptw.pmp[6].cfg.w
connect pmp.io.pmp[6].cfg.x, io.ptw.pmp[6].cfg.x
connect pmp.io.pmp[6].cfg.a, io.ptw.pmp[6].cfg.a
connect pmp.io.pmp[6].cfg.res, io.ptw.pmp[6].cfg.res
connect pmp.io.pmp[6].cfg.l, io.ptw.pmp[6].cfg.l
connect pmp.io.pmp[7].mask, io.ptw.pmp[7].mask
connect pmp.io.pmp[7].addr, io.ptw.pmp[7].addr
connect pmp.io.pmp[7].cfg.r, io.ptw.pmp[7].cfg.r
connect pmp.io.pmp[7].cfg.w, io.ptw.pmp[7].cfg.w
connect pmp.io.pmp[7].cfg.x, io.ptw.pmp[7].cfg.x
connect pmp.io.pmp[7].cfg.a, io.ptw.pmp[7].cfg.a
connect pmp.io.pmp[7].cfg.res, io.ptw.pmp[7].cfg.res
connect pmp.io.pmp[7].cfg.l, io.ptw.pmp[7].cfg.l
connect pmp.io.prv, mpu_priv
inst pma of PMAChecker_7
connect pma.clock, clock
connect pma.reset, reset
connect pma.io.paddr, mpu_physaddr
node cacheable = and(pma.io.resp.cacheable, UInt<1>(0h1))
node _homogeneous_T = xor(mpu_physaddr, UInt<1>(0h0))
node _homogeneous_T_1 = cvt(_homogeneous_T)
node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<14>(0h2000)))
node _homogeneous_T_3 = asSInt(_homogeneous_T_2)
node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0)))
node _homogeneous_T_5 = xor(mpu_physaddr, UInt<14>(0h3000))
node _homogeneous_T_6 = cvt(_homogeneous_T_5)
node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<13>(0h1000)))
node _homogeneous_T_8 = asSInt(_homogeneous_T_7)
node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0)))
node _homogeneous_T_10 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_11 = cvt(_homogeneous_T_10)
node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<17>(0h10000)))
node _homogeneous_T_13 = asSInt(_homogeneous_T_12)
node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0)))
node _homogeneous_T_15 = xor(mpu_physaddr, UInt<21>(0h100000))
node _homogeneous_T_16 = cvt(_homogeneous_T_15)
node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<18>(0h2f000)))
node _homogeneous_T_18 = asSInt(_homogeneous_T_17)
node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0)))
node _homogeneous_T_20 = xor(mpu_physaddr, UInt<26>(0h2000000))
node _homogeneous_T_21 = cvt(_homogeneous_T_20)
node _homogeneous_T_22 = and(_homogeneous_T_21, asSInt(UInt<17>(0h10000)))
node _homogeneous_T_23 = asSInt(_homogeneous_T_22)
node _homogeneous_T_24 = eq(_homogeneous_T_23, asSInt(UInt<1>(0h0)))
node _homogeneous_T_25 = xor(mpu_physaddr, UInt<26>(0h2010000))
node _homogeneous_T_26 = cvt(_homogeneous_T_25)
node _homogeneous_T_27 = and(_homogeneous_T_26, asSInt(UInt<13>(0h1000)))
node _homogeneous_T_28 = asSInt(_homogeneous_T_27)
node _homogeneous_T_29 = eq(_homogeneous_T_28, asSInt(UInt<1>(0h0)))
node _homogeneous_T_30 = xor(mpu_physaddr, UInt<28>(0h8000000))
node _homogeneous_T_31 = cvt(_homogeneous_T_30)
node _homogeneous_T_32 = and(_homogeneous_T_31, asSInt(UInt<17>(0h10000)))
node _homogeneous_T_33 = asSInt(_homogeneous_T_32)
node _homogeneous_T_34 = eq(_homogeneous_T_33, asSInt(UInt<1>(0h0)))
node _homogeneous_T_35 = xor(mpu_physaddr, UInt<28>(0hc000000))
node _homogeneous_T_36 = cvt(_homogeneous_T_35)
node _homogeneous_T_37 = and(_homogeneous_T_36, asSInt(UInt<27>(0h4000000)))
node _homogeneous_T_38 = asSInt(_homogeneous_T_37)
node _homogeneous_T_39 = eq(_homogeneous_T_38, asSInt(UInt<1>(0h0)))
node _homogeneous_T_40 = xor(mpu_physaddr, UInt<29>(0h10020000))
node _homogeneous_T_41 = cvt(_homogeneous_T_40)
node _homogeneous_T_42 = and(_homogeneous_T_41, asSInt(UInt<13>(0h1000)))
node _homogeneous_T_43 = asSInt(_homogeneous_T_42)
node _homogeneous_T_44 = eq(_homogeneous_T_43, asSInt(UInt<1>(0h0)))
node _homogeneous_T_45 = xor(mpu_physaddr, UInt<32>(0h80000000))
node _homogeneous_T_46 = cvt(_homogeneous_T_45)
node _homogeneous_T_47 = and(_homogeneous_T_46, asSInt(UInt<29>(0h10000000)))
node _homogeneous_T_48 = asSInt(_homogeneous_T_47)
node _homogeneous_T_49 = eq(_homogeneous_T_48, asSInt(UInt<1>(0h0)))
node _homogeneous_T_50 = or(UInt<1>(0h0), _homogeneous_T_4)
node _homogeneous_T_51 = or(_homogeneous_T_50, _homogeneous_T_9)
node _homogeneous_T_52 = or(_homogeneous_T_51, _homogeneous_T_14)
node _homogeneous_T_53 = or(_homogeneous_T_52, _homogeneous_T_19)
node _homogeneous_T_54 = or(_homogeneous_T_53, _homogeneous_T_24)
node _homogeneous_T_55 = or(_homogeneous_T_54, _homogeneous_T_29)
node _homogeneous_T_56 = or(_homogeneous_T_55, _homogeneous_T_34)
node _homogeneous_T_57 = or(_homogeneous_T_56, _homogeneous_T_39)
node _homogeneous_T_58 = or(_homogeneous_T_57, _homogeneous_T_44)
node homogeneous = or(_homogeneous_T_58, _homogeneous_T_49)
node _homogeneous_T_59 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _homogeneous_T_60 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_61 = cvt(_homogeneous_T_60)
node _homogeneous_T_62 = and(_homogeneous_T_61, asSInt(UInt<33>(0h8a110000)))
node _homogeneous_T_63 = asSInt(_homogeneous_T_62)
node _homogeneous_T_64 = eq(_homogeneous_T_63, asSInt(UInt<1>(0h0)))
node _homogeneous_T_65 = or(UInt<1>(0h0), _homogeneous_T_64)
node _homogeneous_T_66 = eq(_homogeneous_T_65, UInt<1>(0h0))
node _homogeneous_T_67 = xor(mpu_physaddr, UInt<1>(0h0))
node _homogeneous_T_68 = cvt(_homogeneous_T_67)
node _homogeneous_T_69 = and(_homogeneous_T_68, asSInt(UInt<33>(0h9e113000)))
node _homogeneous_T_70 = asSInt(_homogeneous_T_69)
node _homogeneous_T_71 = eq(_homogeneous_T_70, asSInt(UInt<1>(0h0)))
node _homogeneous_T_72 = xor(mpu_physaddr, UInt<14>(0h3000))
node _homogeneous_T_73 = cvt(_homogeneous_T_72)
node _homogeneous_T_74 = and(_homogeneous_T_73, asSInt(UInt<33>(0h9e113000)))
node _homogeneous_T_75 = asSInt(_homogeneous_T_74)
node _homogeneous_T_76 = eq(_homogeneous_T_75, asSInt(UInt<1>(0h0)))
node _homogeneous_T_77 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_78 = cvt(_homogeneous_T_77)
node _homogeneous_T_79 = and(_homogeneous_T_78, asSInt(UInt<33>(0h9e110000)))
node _homogeneous_T_80 = asSInt(_homogeneous_T_79)
node _homogeneous_T_81 = eq(_homogeneous_T_80, asSInt(UInt<1>(0h0)))
node _homogeneous_T_82 = xor(mpu_physaddr, UInt<28>(0h8000000))
node _homogeneous_T_83 = cvt(_homogeneous_T_82)
node _homogeneous_T_84 = and(_homogeneous_T_83, asSInt(UInt<33>(0h9e110000)))
node _homogeneous_T_85 = asSInt(_homogeneous_T_84)
node _homogeneous_T_86 = eq(_homogeneous_T_85, asSInt(UInt<1>(0h0)))
node _homogeneous_T_87 = xor(mpu_physaddr, UInt<32>(0h80000000))
node _homogeneous_T_88 = cvt(_homogeneous_T_87)
node _homogeneous_T_89 = and(_homogeneous_T_88, asSInt(UInt<33>(0h90000000)))
node _homogeneous_T_90 = asSInt(_homogeneous_T_89)
node _homogeneous_T_91 = eq(_homogeneous_T_90, asSInt(UInt<1>(0h0)))
node _homogeneous_T_92 = or(UInt<1>(0h0), _homogeneous_T_71)
node _homogeneous_T_93 = or(_homogeneous_T_92, _homogeneous_T_76)
node _homogeneous_T_94 = or(_homogeneous_T_93, _homogeneous_T_81)
node _homogeneous_T_95 = or(_homogeneous_T_94, _homogeneous_T_86)
node _homogeneous_T_96 = or(_homogeneous_T_95, _homogeneous_T_91)
node _homogeneous_T_97 = xor(mpu_physaddr, UInt<28>(0h8000000))
node _homogeneous_T_98 = cvt(_homogeneous_T_97)
node _homogeneous_T_99 = and(_homogeneous_T_98, asSInt(UInt<33>(0h8e000000)))
node _homogeneous_T_100 = asSInt(_homogeneous_T_99)
node _homogeneous_T_101 = eq(_homogeneous_T_100, asSInt(UInt<1>(0h0)))
node _homogeneous_T_102 = xor(mpu_physaddr, UInt<32>(0h80000000))
node _homogeneous_T_103 = cvt(_homogeneous_T_102)
node _homogeneous_T_104 = and(_homogeneous_T_103, asSInt(UInt<33>(0h80000000)))
node _homogeneous_T_105 = asSInt(_homogeneous_T_104)
node _homogeneous_T_106 = eq(_homogeneous_T_105, asSInt(UInt<1>(0h0)))
node _homogeneous_T_107 = or(UInt<1>(0h0), _homogeneous_T_101)
node _homogeneous_T_108 = or(_homogeneous_T_107, _homogeneous_T_106)
node _homogeneous_T_109 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_110 = cvt(_homogeneous_T_109)
node _homogeneous_T_111 = and(_homogeneous_T_110, asSInt(UInt<33>(0h8a110000)))
node _homogeneous_T_112 = asSInt(_homogeneous_T_111)
node _homogeneous_T_113 = eq(_homogeneous_T_112, asSInt(UInt<1>(0h0)))
node _homogeneous_T_114 = or(UInt<1>(0h0), _homogeneous_T_113)
node _homogeneous_T_115 = eq(_homogeneous_T_114, UInt<1>(0h0))
node _homogeneous_T_116 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_117 = cvt(_homogeneous_T_116)
node _homogeneous_T_118 = and(_homogeneous_T_117, asSInt(UInt<33>(0h8a110000)))
node _homogeneous_T_119 = asSInt(_homogeneous_T_118)
node _homogeneous_T_120 = eq(_homogeneous_T_119, asSInt(UInt<1>(0h0)))
node _homogeneous_T_121 = or(UInt<1>(0h0), _homogeneous_T_120)
node _homogeneous_T_122 = eq(_homogeneous_T_121, UInt<1>(0h0))
node _deny_access_to_debug_T = leq(mpu_priv, UInt<2>(0h3))
node _deny_access_to_debug_T_1 = xor(mpu_physaddr, UInt<1>(0h0))
node _deny_access_to_debug_T_2 = cvt(_deny_access_to_debug_T_1)
node _deny_access_to_debug_T_3 = and(_deny_access_to_debug_T_2, asSInt(UInt<13>(0h1000)))
node _deny_access_to_debug_T_4 = asSInt(_deny_access_to_debug_T_3)
node _deny_access_to_debug_T_5 = eq(_deny_access_to_debug_T_4, asSInt(UInt<1>(0h0)))
node deny_access_to_debug = and(_deny_access_to_debug_T, _deny_access_to_debug_T_5)
node _prot_r_T = eq(deny_access_to_debug, UInt<1>(0h0))
node _prot_r_T_1 = and(pma.io.resp.r, _prot_r_T)
node prot_r = and(_prot_r_T_1, pmp.io.r)
node _prot_w_T = eq(deny_access_to_debug, UInt<1>(0h0))
node _prot_w_T_1 = and(pma.io.resp.w, _prot_w_T)
node prot_w = and(_prot_w_T_1, pmp.io.w)
node _prot_x_T = eq(deny_access_to_debug, UInt<1>(0h0))
node _prot_x_T_1 = and(pma.io.resp.x, _prot_x_T)
node prot_x = and(_prot_x_T_1, pmp.io.x)
node _sector_hits_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1])
node _sector_hits_T_1 = or(_sector_hits_T, sectored_entries[0][0].valid[2])
node _sector_hits_T_2 = or(_sector_hits_T_1, sectored_entries[0][0].valid[3])
node _sector_hits_T_3 = xor(sectored_entries[0][0].tag_vpn, vpn)
node _sector_hits_T_4 = shr(_sector_hits_T_3, 2)
node _sector_hits_T_5 = eq(_sector_hits_T_4, UInt<1>(0h0))
node _sector_hits_T_6 = eq(sectored_entries[0][0].tag_v, priv_v)
node _sector_hits_T_7 = and(_sector_hits_T_5, _sector_hits_T_6)
node sector_hits_0 = and(_sector_hits_T_2, _sector_hits_T_7)
node _sector_hits_T_8 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1])
node _sector_hits_T_9 = or(_sector_hits_T_8, sectored_entries[0][1].valid[2])
node _sector_hits_T_10 = or(_sector_hits_T_9, sectored_entries[0][1].valid[3])
node _sector_hits_T_11 = xor(sectored_entries[0][1].tag_vpn, vpn)
node _sector_hits_T_12 = shr(_sector_hits_T_11, 2)
node _sector_hits_T_13 = eq(_sector_hits_T_12, UInt<1>(0h0))
node _sector_hits_T_14 = eq(sectored_entries[0][1].tag_v, priv_v)
node _sector_hits_T_15 = and(_sector_hits_T_13, _sector_hits_T_14)
node sector_hits_1 = and(_sector_hits_T_10, _sector_hits_T_15)
node _sector_hits_T_16 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1])
node _sector_hits_T_17 = or(_sector_hits_T_16, sectored_entries[0][2].valid[2])
node _sector_hits_T_18 = or(_sector_hits_T_17, sectored_entries[0][2].valid[3])
node _sector_hits_T_19 = xor(sectored_entries[0][2].tag_vpn, vpn)
node _sector_hits_T_20 = shr(_sector_hits_T_19, 2)
node _sector_hits_T_21 = eq(_sector_hits_T_20, UInt<1>(0h0))
node _sector_hits_T_22 = eq(sectored_entries[0][2].tag_v, priv_v)
node _sector_hits_T_23 = and(_sector_hits_T_21, _sector_hits_T_22)
node sector_hits_2 = and(_sector_hits_T_18, _sector_hits_T_23)
node _sector_hits_T_24 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1])
node _sector_hits_T_25 = or(_sector_hits_T_24, sectored_entries[0][3].valid[2])
node _sector_hits_T_26 = or(_sector_hits_T_25, sectored_entries[0][3].valid[3])
node _sector_hits_T_27 = xor(sectored_entries[0][3].tag_vpn, vpn)
node _sector_hits_T_28 = shr(_sector_hits_T_27, 2)
node _sector_hits_T_29 = eq(_sector_hits_T_28, UInt<1>(0h0))
node _sector_hits_T_30 = eq(sectored_entries[0][3].tag_v, priv_v)
node _sector_hits_T_31 = and(_sector_hits_T_29, _sector_hits_T_30)
node sector_hits_3 = and(_sector_hits_T_26, _sector_hits_T_31)
node _sector_hits_T_32 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1])
node _sector_hits_T_33 = or(_sector_hits_T_32, sectored_entries[0][4].valid[2])
node _sector_hits_T_34 = or(_sector_hits_T_33, sectored_entries[0][4].valid[3])
node _sector_hits_T_35 = xor(sectored_entries[0][4].tag_vpn, vpn)
node _sector_hits_T_36 = shr(_sector_hits_T_35, 2)
node _sector_hits_T_37 = eq(_sector_hits_T_36, UInt<1>(0h0))
node _sector_hits_T_38 = eq(sectored_entries[0][4].tag_v, priv_v)
node _sector_hits_T_39 = and(_sector_hits_T_37, _sector_hits_T_38)
node sector_hits_4 = and(_sector_hits_T_34, _sector_hits_T_39)
node _sector_hits_T_40 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1])
node _sector_hits_T_41 = or(_sector_hits_T_40, sectored_entries[0][5].valid[2])
node _sector_hits_T_42 = or(_sector_hits_T_41, sectored_entries[0][5].valid[3])
node _sector_hits_T_43 = xor(sectored_entries[0][5].tag_vpn, vpn)
node _sector_hits_T_44 = shr(_sector_hits_T_43, 2)
node _sector_hits_T_45 = eq(_sector_hits_T_44, UInt<1>(0h0))
node _sector_hits_T_46 = eq(sectored_entries[0][5].tag_v, priv_v)
node _sector_hits_T_47 = and(_sector_hits_T_45, _sector_hits_T_46)
node sector_hits_5 = and(_sector_hits_T_42, _sector_hits_T_47)
node _sector_hits_T_48 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1])
node _sector_hits_T_49 = or(_sector_hits_T_48, sectored_entries[0][6].valid[2])
node _sector_hits_T_50 = or(_sector_hits_T_49, sectored_entries[0][6].valid[3])
node _sector_hits_T_51 = xor(sectored_entries[0][6].tag_vpn, vpn)
node _sector_hits_T_52 = shr(_sector_hits_T_51, 2)
node _sector_hits_T_53 = eq(_sector_hits_T_52, UInt<1>(0h0))
node _sector_hits_T_54 = eq(sectored_entries[0][6].tag_v, priv_v)
node _sector_hits_T_55 = and(_sector_hits_T_53, _sector_hits_T_54)
node sector_hits_6 = and(_sector_hits_T_50, _sector_hits_T_55)
node _sector_hits_T_56 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1])
node _sector_hits_T_57 = or(_sector_hits_T_56, sectored_entries[0][7].valid[2])
node _sector_hits_T_58 = or(_sector_hits_T_57, sectored_entries[0][7].valid[3])
node _sector_hits_T_59 = xor(sectored_entries[0][7].tag_vpn, vpn)
node _sector_hits_T_60 = shr(_sector_hits_T_59, 2)
node _sector_hits_T_61 = eq(_sector_hits_T_60, UInt<1>(0h0))
node _sector_hits_T_62 = eq(sectored_entries[0][7].tag_v, priv_v)
node _sector_hits_T_63 = and(_sector_hits_T_61, _sector_hits_T_62)
node sector_hits_7 = and(_sector_hits_T_58, _sector_hits_T_63)
node _superpage_hits_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v)
node superpage_hits_tagMatch = and(superpage_entries[0].valid[0], _superpage_hits_tagMatch_T)
node _superpage_hits_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0))
node superpage_hits_ignore = or(_superpage_hits_ignore_T, UInt<1>(0h0))
node _superpage_hits_T = xor(superpage_entries[0].tag_vpn, vpn)
node _superpage_hits_T_1 = bits(_superpage_hits_T, 26, 18)
node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0))
node _superpage_hits_T_3 = or(superpage_hits_ignore, _superpage_hits_T_2)
node _superpage_hits_T_4 = and(superpage_hits_tagMatch, _superpage_hits_T_3)
node _superpage_hits_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1))
node superpage_hits_ignore_1 = or(_superpage_hits_ignore_T_1, UInt<1>(0h0))
node _superpage_hits_T_5 = xor(superpage_entries[0].tag_vpn, vpn)
node _superpage_hits_T_6 = bits(_superpage_hits_T_5, 17, 9)
node _superpage_hits_T_7 = eq(_superpage_hits_T_6, UInt<1>(0h0))
node _superpage_hits_T_8 = or(superpage_hits_ignore_1, _superpage_hits_T_7)
node _superpage_hits_T_9 = and(_superpage_hits_T_4, _superpage_hits_T_8)
node _superpage_hits_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2))
node superpage_hits_ignore_2 = or(_superpage_hits_ignore_T_2, UInt<1>(0h1))
node _superpage_hits_T_10 = xor(superpage_entries[0].tag_vpn, vpn)
node _superpage_hits_T_11 = bits(_superpage_hits_T_10, 8, 0)
node _superpage_hits_T_12 = eq(_superpage_hits_T_11, UInt<1>(0h0))
node _superpage_hits_T_13 = or(superpage_hits_ignore_2, _superpage_hits_T_12)
node superpage_hits_0 = and(_superpage_hits_T_9, _superpage_hits_T_13)
node _superpage_hits_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v)
node superpage_hits_tagMatch_1 = and(superpage_entries[1].valid[0], _superpage_hits_tagMatch_T_1)
node _superpage_hits_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0))
node superpage_hits_ignore_3 = or(_superpage_hits_ignore_T_3, UInt<1>(0h0))
node _superpage_hits_T_14 = xor(superpage_entries[1].tag_vpn, vpn)
node _superpage_hits_T_15 = bits(_superpage_hits_T_14, 26, 18)
node _superpage_hits_T_16 = eq(_superpage_hits_T_15, UInt<1>(0h0))
node _superpage_hits_T_17 = or(superpage_hits_ignore_3, _superpage_hits_T_16)
node _superpage_hits_T_18 = and(superpage_hits_tagMatch_1, _superpage_hits_T_17)
node _superpage_hits_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1))
node superpage_hits_ignore_4 = or(_superpage_hits_ignore_T_4, UInt<1>(0h0))
node _superpage_hits_T_19 = xor(superpage_entries[1].tag_vpn, vpn)
node _superpage_hits_T_20 = bits(_superpage_hits_T_19, 17, 9)
node _superpage_hits_T_21 = eq(_superpage_hits_T_20, UInt<1>(0h0))
node _superpage_hits_T_22 = or(superpage_hits_ignore_4, _superpage_hits_T_21)
node _superpage_hits_T_23 = and(_superpage_hits_T_18, _superpage_hits_T_22)
node _superpage_hits_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2))
node superpage_hits_ignore_5 = or(_superpage_hits_ignore_T_5, UInt<1>(0h1))
node _superpage_hits_T_24 = xor(superpage_entries[1].tag_vpn, vpn)
node _superpage_hits_T_25 = bits(_superpage_hits_T_24, 8, 0)
node _superpage_hits_T_26 = eq(_superpage_hits_T_25, UInt<1>(0h0))
node _superpage_hits_T_27 = or(superpage_hits_ignore_5, _superpage_hits_T_26)
node superpage_hits_1 = and(_superpage_hits_T_23, _superpage_hits_T_27)
node _superpage_hits_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v)
node superpage_hits_tagMatch_2 = and(superpage_entries[2].valid[0], _superpage_hits_tagMatch_T_2)
node _superpage_hits_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0))
node superpage_hits_ignore_6 = or(_superpage_hits_ignore_T_6, UInt<1>(0h0))
node _superpage_hits_T_28 = xor(superpage_entries[2].tag_vpn, vpn)
node _superpage_hits_T_29 = bits(_superpage_hits_T_28, 26, 18)
node _superpage_hits_T_30 = eq(_superpage_hits_T_29, UInt<1>(0h0))
node _superpage_hits_T_31 = or(superpage_hits_ignore_6, _superpage_hits_T_30)
node _superpage_hits_T_32 = and(superpage_hits_tagMatch_2, _superpage_hits_T_31)
node _superpage_hits_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1))
node superpage_hits_ignore_7 = or(_superpage_hits_ignore_T_7, UInt<1>(0h0))
node _superpage_hits_T_33 = xor(superpage_entries[2].tag_vpn, vpn)
node _superpage_hits_T_34 = bits(_superpage_hits_T_33, 17, 9)
node _superpage_hits_T_35 = eq(_superpage_hits_T_34, UInt<1>(0h0))
node _superpage_hits_T_36 = or(superpage_hits_ignore_7, _superpage_hits_T_35)
node _superpage_hits_T_37 = and(_superpage_hits_T_32, _superpage_hits_T_36)
node _superpage_hits_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2))
node superpage_hits_ignore_8 = or(_superpage_hits_ignore_T_8, UInt<1>(0h1))
node _superpage_hits_T_38 = xor(superpage_entries[2].tag_vpn, vpn)
node _superpage_hits_T_39 = bits(_superpage_hits_T_38, 8, 0)
node _superpage_hits_T_40 = eq(_superpage_hits_T_39, UInt<1>(0h0))
node _superpage_hits_T_41 = or(superpage_hits_ignore_8, _superpage_hits_T_40)
node superpage_hits_2 = and(_superpage_hits_T_37, _superpage_hits_T_41)
node _superpage_hits_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v)
node superpage_hits_tagMatch_3 = and(superpage_entries[3].valid[0], _superpage_hits_tagMatch_T_3)
node _superpage_hits_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0))
node superpage_hits_ignore_9 = or(_superpage_hits_ignore_T_9, UInt<1>(0h0))
node _superpage_hits_T_42 = xor(superpage_entries[3].tag_vpn, vpn)
node _superpage_hits_T_43 = bits(_superpage_hits_T_42, 26, 18)
node _superpage_hits_T_44 = eq(_superpage_hits_T_43, UInt<1>(0h0))
node _superpage_hits_T_45 = or(superpage_hits_ignore_9, _superpage_hits_T_44)
node _superpage_hits_T_46 = and(superpage_hits_tagMatch_3, _superpage_hits_T_45)
node _superpage_hits_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1))
node superpage_hits_ignore_10 = or(_superpage_hits_ignore_T_10, UInt<1>(0h0))
node _superpage_hits_T_47 = xor(superpage_entries[3].tag_vpn, vpn)
node _superpage_hits_T_48 = bits(_superpage_hits_T_47, 17, 9)
node _superpage_hits_T_49 = eq(_superpage_hits_T_48, UInt<1>(0h0))
node _superpage_hits_T_50 = or(superpage_hits_ignore_10, _superpage_hits_T_49)
node _superpage_hits_T_51 = and(_superpage_hits_T_46, _superpage_hits_T_50)
node _superpage_hits_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2))
node superpage_hits_ignore_11 = or(_superpage_hits_ignore_T_11, UInt<1>(0h1))
node _superpage_hits_T_52 = xor(superpage_entries[3].tag_vpn, vpn)
node _superpage_hits_T_53 = bits(_superpage_hits_T_52, 8, 0)
node _superpage_hits_T_54 = eq(_superpage_hits_T_53, UInt<1>(0h0))
node _superpage_hits_T_55 = or(superpage_hits_ignore_11, _superpage_hits_T_54)
node superpage_hits_3 = and(_superpage_hits_T_51, _superpage_hits_T_55)
node hitsVec_idx = bits(vpn, 1, 0)
node _hitsVec_T = xor(sectored_entries[0][0].tag_vpn, vpn)
node _hitsVec_T_1 = shr(_hitsVec_T, 2)
node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0))
node _hitsVec_T_3 = eq(sectored_entries[0][0].tag_v, priv_v)
node _hitsVec_T_4 = and(_hitsVec_T_2, _hitsVec_T_3)
node _hitsVec_T_5 = and(sectored_entries[0][0].valid[hitsVec_idx], _hitsVec_T_4)
node hitsVec_0 = and(vm_enabled, _hitsVec_T_5)
node hitsVec_idx_1 = bits(vpn, 1, 0)
node _hitsVec_T_6 = xor(sectored_entries[0][1].tag_vpn, vpn)
node _hitsVec_T_7 = shr(_hitsVec_T_6, 2)
node _hitsVec_T_8 = eq(_hitsVec_T_7, UInt<1>(0h0))
node _hitsVec_T_9 = eq(sectored_entries[0][1].tag_v, priv_v)
node _hitsVec_T_10 = and(_hitsVec_T_8, _hitsVec_T_9)
node _hitsVec_T_11 = and(sectored_entries[0][1].valid[hitsVec_idx_1], _hitsVec_T_10)
node hitsVec_1 = and(vm_enabled, _hitsVec_T_11)
node hitsVec_idx_2 = bits(vpn, 1, 0)
node _hitsVec_T_12 = xor(sectored_entries[0][2].tag_vpn, vpn)
node _hitsVec_T_13 = shr(_hitsVec_T_12, 2)
node _hitsVec_T_14 = eq(_hitsVec_T_13, UInt<1>(0h0))
node _hitsVec_T_15 = eq(sectored_entries[0][2].tag_v, priv_v)
node _hitsVec_T_16 = and(_hitsVec_T_14, _hitsVec_T_15)
node _hitsVec_T_17 = and(sectored_entries[0][2].valid[hitsVec_idx_2], _hitsVec_T_16)
node hitsVec_2 = and(vm_enabled, _hitsVec_T_17)
node hitsVec_idx_3 = bits(vpn, 1, 0)
node _hitsVec_T_18 = xor(sectored_entries[0][3].tag_vpn, vpn)
node _hitsVec_T_19 = shr(_hitsVec_T_18, 2)
node _hitsVec_T_20 = eq(_hitsVec_T_19, UInt<1>(0h0))
node _hitsVec_T_21 = eq(sectored_entries[0][3].tag_v, priv_v)
node _hitsVec_T_22 = and(_hitsVec_T_20, _hitsVec_T_21)
node _hitsVec_T_23 = and(sectored_entries[0][3].valid[hitsVec_idx_3], _hitsVec_T_22)
node hitsVec_3 = and(vm_enabled, _hitsVec_T_23)
node hitsVec_idx_4 = bits(vpn, 1, 0)
node _hitsVec_T_24 = xor(sectored_entries[0][4].tag_vpn, vpn)
node _hitsVec_T_25 = shr(_hitsVec_T_24, 2)
node _hitsVec_T_26 = eq(_hitsVec_T_25, UInt<1>(0h0))
node _hitsVec_T_27 = eq(sectored_entries[0][4].tag_v, priv_v)
node _hitsVec_T_28 = and(_hitsVec_T_26, _hitsVec_T_27)
node _hitsVec_T_29 = and(sectored_entries[0][4].valid[hitsVec_idx_4], _hitsVec_T_28)
node hitsVec_4 = and(vm_enabled, _hitsVec_T_29)
node hitsVec_idx_5 = bits(vpn, 1, 0)
node _hitsVec_T_30 = xor(sectored_entries[0][5].tag_vpn, vpn)
node _hitsVec_T_31 = shr(_hitsVec_T_30, 2)
node _hitsVec_T_32 = eq(_hitsVec_T_31, UInt<1>(0h0))
node _hitsVec_T_33 = eq(sectored_entries[0][5].tag_v, priv_v)
node _hitsVec_T_34 = and(_hitsVec_T_32, _hitsVec_T_33)
node _hitsVec_T_35 = and(sectored_entries[0][5].valid[hitsVec_idx_5], _hitsVec_T_34)
node hitsVec_5 = and(vm_enabled, _hitsVec_T_35)
node hitsVec_idx_6 = bits(vpn, 1, 0)
node _hitsVec_T_36 = xor(sectored_entries[0][6].tag_vpn, vpn)
node _hitsVec_T_37 = shr(_hitsVec_T_36, 2)
node _hitsVec_T_38 = eq(_hitsVec_T_37, UInt<1>(0h0))
node _hitsVec_T_39 = eq(sectored_entries[0][6].tag_v, priv_v)
node _hitsVec_T_40 = and(_hitsVec_T_38, _hitsVec_T_39)
node _hitsVec_T_41 = and(sectored_entries[0][6].valid[hitsVec_idx_6], _hitsVec_T_40)
node hitsVec_6 = and(vm_enabled, _hitsVec_T_41)
node hitsVec_idx_7 = bits(vpn, 1, 0)
node _hitsVec_T_42 = xor(sectored_entries[0][7].tag_vpn, vpn)
node _hitsVec_T_43 = shr(_hitsVec_T_42, 2)
node _hitsVec_T_44 = eq(_hitsVec_T_43, UInt<1>(0h0))
node _hitsVec_T_45 = eq(sectored_entries[0][7].tag_v, priv_v)
node _hitsVec_T_46 = and(_hitsVec_T_44, _hitsVec_T_45)
node _hitsVec_T_47 = and(sectored_entries[0][7].valid[hitsVec_idx_7], _hitsVec_T_46)
node hitsVec_7 = and(vm_enabled, _hitsVec_T_47)
node _hitsVec_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v)
node hitsVec_tagMatch = and(superpage_entries[0].valid[0], _hitsVec_tagMatch_T)
node _hitsVec_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0))
node hitsVec_ignore = or(_hitsVec_ignore_T, UInt<1>(0h0))
node _hitsVec_T_48 = xor(superpage_entries[0].tag_vpn, vpn)
node _hitsVec_T_49 = bits(_hitsVec_T_48, 26, 18)
node _hitsVec_T_50 = eq(_hitsVec_T_49, UInt<1>(0h0))
node _hitsVec_T_51 = or(hitsVec_ignore, _hitsVec_T_50)
node _hitsVec_T_52 = and(hitsVec_tagMatch, _hitsVec_T_51)
node _hitsVec_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1))
node hitsVec_ignore_1 = or(_hitsVec_ignore_T_1, UInt<1>(0h0))
node _hitsVec_T_53 = xor(superpage_entries[0].tag_vpn, vpn)
node _hitsVec_T_54 = bits(_hitsVec_T_53, 17, 9)
node _hitsVec_T_55 = eq(_hitsVec_T_54, UInt<1>(0h0))
node _hitsVec_T_56 = or(hitsVec_ignore_1, _hitsVec_T_55)
node _hitsVec_T_57 = and(_hitsVec_T_52, _hitsVec_T_56)
node _hitsVec_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2))
node hitsVec_ignore_2 = or(_hitsVec_ignore_T_2, UInt<1>(0h1))
node _hitsVec_T_58 = xor(superpage_entries[0].tag_vpn, vpn)
node _hitsVec_T_59 = bits(_hitsVec_T_58, 8, 0)
node _hitsVec_T_60 = eq(_hitsVec_T_59, UInt<1>(0h0))
node _hitsVec_T_61 = or(hitsVec_ignore_2, _hitsVec_T_60)
node _hitsVec_T_62 = and(_hitsVec_T_57, _hitsVec_T_61)
node hitsVec_8 = and(vm_enabled, _hitsVec_T_62)
node _hitsVec_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v)
node hitsVec_tagMatch_1 = and(superpage_entries[1].valid[0], _hitsVec_tagMatch_T_1)
node _hitsVec_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0))
node hitsVec_ignore_3 = or(_hitsVec_ignore_T_3, UInt<1>(0h0))
node _hitsVec_T_63 = xor(superpage_entries[1].tag_vpn, vpn)
node _hitsVec_T_64 = bits(_hitsVec_T_63, 26, 18)
node _hitsVec_T_65 = eq(_hitsVec_T_64, UInt<1>(0h0))
node _hitsVec_T_66 = or(hitsVec_ignore_3, _hitsVec_T_65)
node _hitsVec_T_67 = and(hitsVec_tagMatch_1, _hitsVec_T_66)
node _hitsVec_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1))
node hitsVec_ignore_4 = or(_hitsVec_ignore_T_4, UInt<1>(0h0))
node _hitsVec_T_68 = xor(superpage_entries[1].tag_vpn, vpn)
node _hitsVec_T_69 = bits(_hitsVec_T_68, 17, 9)
node _hitsVec_T_70 = eq(_hitsVec_T_69, UInt<1>(0h0))
node _hitsVec_T_71 = or(hitsVec_ignore_4, _hitsVec_T_70)
node _hitsVec_T_72 = and(_hitsVec_T_67, _hitsVec_T_71)
node _hitsVec_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2))
node hitsVec_ignore_5 = or(_hitsVec_ignore_T_5, UInt<1>(0h1))
node _hitsVec_T_73 = xor(superpage_entries[1].tag_vpn, vpn)
node _hitsVec_T_74 = bits(_hitsVec_T_73, 8, 0)
node _hitsVec_T_75 = eq(_hitsVec_T_74, UInt<1>(0h0))
node _hitsVec_T_76 = or(hitsVec_ignore_5, _hitsVec_T_75)
node _hitsVec_T_77 = and(_hitsVec_T_72, _hitsVec_T_76)
node hitsVec_9 = and(vm_enabled, _hitsVec_T_77)
node _hitsVec_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v)
node hitsVec_tagMatch_2 = and(superpage_entries[2].valid[0], _hitsVec_tagMatch_T_2)
node _hitsVec_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0))
node hitsVec_ignore_6 = or(_hitsVec_ignore_T_6, UInt<1>(0h0))
node _hitsVec_T_78 = xor(superpage_entries[2].tag_vpn, vpn)
node _hitsVec_T_79 = bits(_hitsVec_T_78, 26, 18)
node _hitsVec_T_80 = eq(_hitsVec_T_79, UInt<1>(0h0))
node _hitsVec_T_81 = or(hitsVec_ignore_6, _hitsVec_T_80)
node _hitsVec_T_82 = and(hitsVec_tagMatch_2, _hitsVec_T_81)
node _hitsVec_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1))
node hitsVec_ignore_7 = or(_hitsVec_ignore_T_7, UInt<1>(0h0))
node _hitsVec_T_83 = xor(superpage_entries[2].tag_vpn, vpn)
node _hitsVec_T_84 = bits(_hitsVec_T_83, 17, 9)
node _hitsVec_T_85 = eq(_hitsVec_T_84, UInt<1>(0h0))
node _hitsVec_T_86 = or(hitsVec_ignore_7, _hitsVec_T_85)
node _hitsVec_T_87 = and(_hitsVec_T_82, _hitsVec_T_86)
node _hitsVec_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2))
node hitsVec_ignore_8 = or(_hitsVec_ignore_T_8, UInt<1>(0h1))
node _hitsVec_T_88 = xor(superpage_entries[2].tag_vpn, vpn)
node _hitsVec_T_89 = bits(_hitsVec_T_88, 8, 0)
node _hitsVec_T_90 = eq(_hitsVec_T_89, UInt<1>(0h0))
node _hitsVec_T_91 = or(hitsVec_ignore_8, _hitsVec_T_90)
node _hitsVec_T_92 = and(_hitsVec_T_87, _hitsVec_T_91)
node hitsVec_10 = and(vm_enabled, _hitsVec_T_92)
node _hitsVec_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v)
node hitsVec_tagMatch_3 = and(superpage_entries[3].valid[0], _hitsVec_tagMatch_T_3)
node _hitsVec_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0))
node hitsVec_ignore_9 = or(_hitsVec_ignore_T_9, UInt<1>(0h0))
node _hitsVec_T_93 = xor(superpage_entries[3].tag_vpn, vpn)
node _hitsVec_T_94 = bits(_hitsVec_T_93, 26, 18)
node _hitsVec_T_95 = eq(_hitsVec_T_94, UInt<1>(0h0))
node _hitsVec_T_96 = or(hitsVec_ignore_9, _hitsVec_T_95)
node _hitsVec_T_97 = and(hitsVec_tagMatch_3, _hitsVec_T_96)
node _hitsVec_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1))
node hitsVec_ignore_10 = or(_hitsVec_ignore_T_10, UInt<1>(0h0))
node _hitsVec_T_98 = xor(superpage_entries[3].tag_vpn, vpn)
node _hitsVec_T_99 = bits(_hitsVec_T_98, 17, 9)
node _hitsVec_T_100 = eq(_hitsVec_T_99, UInt<1>(0h0))
node _hitsVec_T_101 = or(hitsVec_ignore_10, _hitsVec_T_100)
node _hitsVec_T_102 = and(_hitsVec_T_97, _hitsVec_T_101)
node _hitsVec_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2))
node hitsVec_ignore_11 = or(_hitsVec_ignore_T_11, UInt<1>(0h1))
node _hitsVec_T_103 = xor(superpage_entries[3].tag_vpn, vpn)
node _hitsVec_T_104 = bits(_hitsVec_T_103, 8, 0)
node _hitsVec_T_105 = eq(_hitsVec_T_104, UInt<1>(0h0))
node _hitsVec_T_106 = or(hitsVec_ignore_11, _hitsVec_T_105)
node _hitsVec_T_107 = and(_hitsVec_T_102, _hitsVec_T_106)
node hitsVec_11 = and(vm_enabled, _hitsVec_T_107)
node _hitsVec_tagMatch_T_4 = eq(special_entry.tag_v, priv_v)
node hitsVec_tagMatch_4 = and(special_entry.valid[0], _hitsVec_tagMatch_T_4)
node _hitsVec_ignore_T_12 = lt(special_entry.level, UInt<1>(0h0))
node hitsVec_ignore_12 = or(_hitsVec_ignore_T_12, UInt<1>(0h0))
node _hitsVec_T_108 = xor(special_entry.tag_vpn, vpn)
node _hitsVec_T_109 = bits(_hitsVec_T_108, 26, 18)
node _hitsVec_T_110 = eq(_hitsVec_T_109, UInt<1>(0h0))
node _hitsVec_T_111 = or(hitsVec_ignore_12, _hitsVec_T_110)
node _hitsVec_T_112 = and(hitsVec_tagMatch_4, _hitsVec_T_111)
node _hitsVec_ignore_T_13 = lt(special_entry.level, UInt<1>(0h1))
node hitsVec_ignore_13 = or(_hitsVec_ignore_T_13, UInt<1>(0h0))
node _hitsVec_T_113 = xor(special_entry.tag_vpn, vpn)
node _hitsVec_T_114 = bits(_hitsVec_T_113, 17, 9)
node _hitsVec_T_115 = eq(_hitsVec_T_114, UInt<1>(0h0))
node _hitsVec_T_116 = or(hitsVec_ignore_13, _hitsVec_T_115)
node _hitsVec_T_117 = and(_hitsVec_T_112, _hitsVec_T_116)
node _hitsVec_ignore_T_14 = lt(special_entry.level, UInt<2>(0h2))
node hitsVec_ignore_14 = or(_hitsVec_ignore_T_14, UInt<1>(0h0))
node _hitsVec_T_118 = xor(special_entry.tag_vpn, vpn)
node _hitsVec_T_119 = bits(_hitsVec_T_118, 8, 0)
node _hitsVec_T_120 = eq(_hitsVec_T_119, UInt<1>(0h0))
node _hitsVec_T_121 = or(hitsVec_ignore_14, _hitsVec_T_120)
node _hitsVec_T_122 = and(_hitsVec_T_117, _hitsVec_T_121)
node hitsVec_12 = and(vm_enabled, _hitsVec_T_122)
node real_hits_lo_lo_hi = cat(hitsVec_2, hitsVec_1)
node real_hits_lo_lo = cat(real_hits_lo_lo_hi, hitsVec_0)
node real_hits_lo_hi_hi = cat(hitsVec_5, hitsVec_4)
node real_hits_lo_hi = cat(real_hits_lo_hi_hi, hitsVec_3)
node real_hits_lo = cat(real_hits_lo_hi, real_hits_lo_lo)
node real_hits_hi_lo_hi = cat(hitsVec_8, hitsVec_7)
node real_hits_hi_lo = cat(real_hits_hi_lo_hi, hitsVec_6)
node real_hits_hi_hi_lo = cat(hitsVec_10, hitsVec_9)
node real_hits_hi_hi_hi = cat(hitsVec_12, hitsVec_11)
node real_hits_hi_hi = cat(real_hits_hi_hi_hi, real_hits_hi_hi_lo)
node real_hits_hi = cat(real_hits_hi_hi, real_hits_hi_lo)
node real_hits = cat(real_hits_hi, real_hits_lo)
node _hits_T = eq(vm_enabled, UInt<1>(0h0))
node hits = cat(_hits_T, real_hits)
when do_refill :
node refill_v = or(r_vstage1_en, r_stage2_en)
wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
connect newEntry.ppn, io.ptw.resp.bits.pte.ppn
connect newEntry.c, cacheable
connect newEntry.u, io.ptw.resp.bits.pte.u
node _newEntry_g_T = and(io.ptw.resp.bits.pte.g, io.ptw.resp.bits.pte.v)
connect newEntry.g, _newEntry_g_T
connect newEntry.ae_ptw, io.ptw.resp.bits.ae_ptw
connect newEntry.ae_final, io.ptw.resp.bits.ae_final
node _newEntry_ae_stage2_T = and(io.ptw.resp.bits.ae_final, io.ptw.resp.bits.gpa_is_pte)
node _newEntry_ae_stage2_T_1 = and(_newEntry_ae_stage2_T, r_stage2_en)
connect newEntry.ae_stage2, _newEntry_ae_stage2_T_1
connect newEntry.pf, io.ptw.resp.bits.pf
connect newEntry.gf, io.ptw.resp.bits.gf
connect newEntry.hr, io.ptw.resp.bits.hr
connect newEntry.hw, io.ptw.resp.bits.hw
connect newEntry.hx, io.ptw.resp.bits.hx
node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0))
node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T)
node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1)
node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2)
node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a)
node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r)
connect newEntry.sr, _newEntry_sr_T_5
node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0))
node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T)
node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1)
node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2)
node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a)
node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w)
node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d)
connect newEntry.sw, _newEntry_sw_T_6
node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0))
node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T)
node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1)
node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2)
node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a)
node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x)
connect newEntry.sx, _newEntry_sx_T_5
connect newEntry.pr, prot_r
connect newEntry.pw, prot_w
connect newEntry.px, prot_x
connect newEntry.ppp, pma.io.resp.pp
connect newEntry.pal, pma.io.resp.al
connect newEntry.paa, pma.io.resp.aa
connect newEntry.eff, pma.io.resp.eff
connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage
node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
when _T_1 :
connect special_entry.tag_vpn, r_refill_tag
connect special_entry.tag_v, refill_v
node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0)
connect special_entry.level, _special_entry_level_T
connect special_entry.valid[0], UInt<1>(0h1)
node special_entry_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node special_entry_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node special_entry_data_0_lo_lo_hi = cat(special_entry_data_0_lo_lo_hi_hi, newEntry.eff)
node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo)
node special_entry_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node special_entry_data_0_lo_hi_lo = cat(special_entry_data_0_lo_hi_lo_hi, newEntry.ppp)
node special_entry_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node special_entry_data_0_lo_hi_hi = cat(special_entry_data_0_lo_hi_hi_hi, newEntry.pw)
node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo)
node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo)
node special_entry_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node special_entry_data_0_hi_lo_lo = cat(special_entry_data_0_hi_lo_lo_hi, newEntry.hw)
node special_entry_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node special_entry_data_0_hi_lo_hi = cat(special_entry_data_0_hi_lo_hi_hi, newEntry.sw)
node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo)
node special_entry_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node special_entry_data_0_hi_hi_lo = cat(special_entry_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node special_entry_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node special_entry_data_0_hi_hi_hi = cat(special_entry_data_0_hi_hi_hi_hi, newEntry.g)
node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo)
node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo)
node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo)
connect special_entry.data[0], _special_entry_data_0_T
else :
node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2))
when _T_2 :
node _waddr_T = and(r_superpage_hit.valid, UInt<1>(0h0))
node waddr = mux(_waddr_T, r_superpage_hit.bits, r_superpage_repl_addr)
node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0))
when _T_3 :
connect superpage_entries[0].tag_vpn, r_refill_tag
connect superpage_entries[0].tag_v, refill_v
node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[0].level, _superpage_entries_0_level_T
connect superpage_entries[0].valid[0], UInt<1>(0h1)
node superpage_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node superpage_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node superpage_entries_0_data_0_lo_lo_hi = cat(superpage_entries_0_data_0_lo_lo_hi_hi, newEntry.eff)
node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo)
node superpage_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_0_data_0_lo_hi_lo = cat(superpage_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp)
node superpage_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node superpage_entries_0_data_0_lo_hi_hi = cat(superpage_entries_0_data_0_lo_hi_hi_hi, newEntry.pw)
node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo)
node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo)
node superpage_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node superpage_entries_0_data_0_hi_lo_lo = cat(superpage_entries_0_data_0_hi_lo_lo_hi, newEntry.hw)
node superpage_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node superpage_entries_0_data_0_hi_lo_hi = cat(superpage_entries_0_data_0_hi_lo_hi_hi, newEntry.sw)
node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo)
node superpage_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node superpage_entries_0_data_0_hi_hi_lo = cat(superpage_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node superpage_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_0_data_0_hi_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi_hi, newEntry.g)
node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo)
node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo)
node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo)
connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T
when invalidate_refill :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
node _T_4 = eq(r_superpage_repl_addr, UInt<1>(0h1))
when _T_4 :
connect superpage_entries[1].tag_vpn, r_refill_tag
connect superpage_entries[1].tag_v, refill_v
node _superpage_entries_1_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[1].level, _superpage_entries_1_level_T
connect superpage_entries[1].valid[0], UInt<1>(0h1)
node superpage_entries_1_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node superpage_entries_1_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node superpage_entries_1_data_0_lo_lo_hi = cat(superpage_entries_1_data_0_lo_lo_hi_hi, newEntry.eff)
node superpage_entries_1_data_0_lo_lo = cat(superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo)
node superpage_entries_1_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_1_data_0_lo_hi_lo = cat(superpage_entries_1_data_0_lo_hi_lo_hi, newEntry.ppp)
node superpage_entries_1_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node superpage_entries_1_data_0_lo_hi_hi = cat(superpage_entries_1_data_0_lo_hi_hi_hi, newEntry.pw)
node superpage_entries_1_data_0_lo_hi = cat(superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo)
node superpage_entries_1_data_0_lo = cat(superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo)
node superpage_entries_1_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node superpage_entries_1_data_0_hi_lo_lo = cat(superpage_entries_1_data_0_hi_lo_lo_hi, newEntry.hw)
node superpage_entries_1_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node superpage_entries_1_data_0_hi_lo_hi = cat(superpage_entries_1_data_0_hi_lo_hi_hi, newEntry.sw)
node superpage_entries_1_data_0_hi_lo = cat(superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo)
node superpage_entries_1_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node superpage_entries_1_data_0_hi_hi_lo = cat(superpage_entries_1_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node superpage_entries_1_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_1_data_0_hi_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi_hi, newEntry.g)
node superpage_entries_1_data_0_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo)
node superpage_entries_1_data_0_hi = cat(superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo)
node _superpage_entries_1_data_0_T = cat(superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo)
connect superpage_entries[1].data[0], _superpage_entries_1_data_0_T
when invalidate_refill :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
node _T_5 = eq(r_superpage_repl_addr, UInt<2>(0h2))
when _T_5 :
connect superpage_entries[2].tag_vpn, r_refill_tag
connect superpage_entries[2].tag_v, refill_v
node _superpage_entries_2_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[2].level, _superpage_entries_2_level_T
connect superpage_entries[2].valid[0], UInt<1>(0h1)
node superpage_entries_2_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node superpage_entries_2_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node superpage_entries_2_data_0_lo_lo_hi = cat(superpage_entries_2_data_0_lo_lo_hi_hi, newEntry.eff)
node superpage_entries_2_data_0_lo_lo = cat(superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo)
node superpage_entries_2_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_2_data_0_lo_hi_lo = cat(superpage_entries_2_data_0_lo_hi_lo_hi, newEntry.ppp)
node superpage_entries_2_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node superpage_entries_2_data_0_lo_hi_hi = cat(superpage_entries_2_data_0_lo_hi_hi_hi, newEntry.pw)
node superpage_entries_2_data_0_lo_hi = cat(superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo)
node superpage_entries_2_data_0_lo = cat(superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo)
node superpage_entries_2_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node superpage_entries_2_data_0_hi_lo_lo = cat(superpage_entries_2_data_0_hi_lo_lo_hi, newEntry.hw)
node superpage_entries_2_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node superpage_entries_2_data_0_hi_lo_hi = cat(superpage_entries_2_data_0_hi_lo_hi_hi, newEntry.sw)
node superpage_entries_2_data_0_hi_lo = cat(superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo)
node superpage_entries_2_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node superpage_entries_2_data_0_hi_hi_lo = cat(superpage_entries_2_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node superpage_entries_2_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_2_data_0_hi_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi_hi, newEntry.g)
node superpage_entries_2_data_0_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo)
node superpage_entries_2_data_0_hi = cat(superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo)
node _superpage_entries_2_data_0_T = cat(superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo)
connect superpage_entries[2].data[0], _superpage_entries_2_data_0_T
when invalidate_refill :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
node _T_6 = eq(r_superpage_repl_addr, UInt<2>(0h3))
when _T_6 :
connect superpage_entries[3].tag_vpn, r_refill_tag
connect superpage_entries[3].tag_v, refill_v
node _superpage_entries_3_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[3].level, _superpage_entries_3_level_T
connect superpage_entries[3].valid[0], UInt<1>(0h1)
node superpage_entries_3_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node superpage_entries_3_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node superpage_entries_3_data_0_lo_lo_hi = cat(superpage_entries_3_data_0_lo_lo_hi_hi, newEntry.eff)
node superpage_entries_3_data_0_lo_lo = cat(superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo)
node superpage_entries_3_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_3_data_0_lo_hi_lo = cat(superpage_entries_3_data_0_lo_hi_lo_hi, newEntry.ppp)
node superpage_entries_3_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node superpage_entries_3_data_0_lo_hi_hi = cat(superpage_entries_3_data_0_lo_hi_hi_hi, newEntry.pw)
node superpage_entries_3_data_0_lo_hi = cat(superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo)
node superpage_entries_3_data_0_lo = cat(superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo)
node superpage_entries_3_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node superpage_entries_3_data_0_hi_lo_lo = cat(superpage_entries_3_data_0_hi_lo_lo_hi, newEntry.hw)
node superpage_entries_3_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node superpage_entries_3_data_0_hi_lo_hi = cat(superpage_entries_3_data_0_hi_lo_hi_hi, newEntry.sw)
node superpage_entries_3_data_0_hi_lo = cat(superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo)
node superpage_entries_3_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node superpage_entries_3_data_0_hi_hi_lo = cat(superpage_entries_3_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node superpage_entries_3_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_3_data_0_hi_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi_hi, newEntry.g)
node superpage_entries_3_data_0_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo)
node superpage_entries_3_data_0_hi = cat(superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo)
node _superpage_entries_3_data_0_T = cat(superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo)
connect superpage_entries[3].data[0], _superpage_entries_3_data_0_T
when invalidate_refill :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
else :
node waddr_1 = mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr)
node _T_7 = eq(waddr_1, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_8 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
connect sectored_entries[0][0].tag_vpn, r_refill_tag
connect sectored_entries[0][0].tag_v, refill_v
connect sectored_entries[0][0].level, UInt<2>(0h0)
node idx = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][0].valid[idx], UInt<1>(0h1)
node sectored_entries_0_0_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_0_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_0_data_lo_lo_hi = cat(sectored_entries_0_0_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_0_data_lo_lo = cat(sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo)
node sectored_entries_0_0_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_0_data_lo_hi_lo = cat(sectored_entries_0_0_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_0_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_0_data_lo_hi_hi = cat(sectored_entries_0_0_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_0_data_lo_hi = cat(sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo)
node sectored_entries_0_0_data_lo = cat(sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo)
node sectored_entries_0_0_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_0_data_hi_lo_lo = cat(sectored_entries_0_0_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_0_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_0_data_hi_lo_hi = cat(sectored_entries_0_0_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_0_data_hi_lo = cat(sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo)
node sectored_entries_0_0_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_0_data_hi_hi_lo = cat(sectored_entries_0_0_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_0_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_0_data_hi_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_0_data_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo)
node sectored_entries_0_0_data_hi = cat(sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo)
node _sectored_entries_0_0_data_T = cat(sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo)
connect sectored_entries[0][0].data[idx], _sectored_entries_0_0_data_T
when invalidate_refill :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
node _T_9 = eq(waddr_1, UInt<1>(0h1))
when _T_9 :
node _T_10 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_10 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
connect sectored_entries[0][1].tag_vpn, r_refill_tag
connect sectored_entries[0][1].tag_v, refill_v
connect sectored_entries[0][1].level, UInt<2>(0h0)
node idx_1 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][1].valid[idx_1], UInt<1>(0h1)
node sectored_entries_0_1_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_1_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_1_data_lo_lo_hi = cat(sectored_entries_0_1_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_1_data_lo_lo = cat(sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo)
node sectored_entries_0_1_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_1_data_lo_hi_lo = cat(sectored_entries_0_1_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_1_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_1_data_lo_hi_hi = cat(sectored_entries_0_1_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_1_data_lo_hi = cat(sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo)
node sectored_entries_0_1_data_lo = cat(sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo)
node sectored_entries_0_1_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_1_data_hi_lo_lo = cat(sectored_entries_0_1_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_1_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_1_data_hi_lo_hi = cat(sectored_entries_0_1_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_1_data_hi_lo = cat(sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo)
node sectored_entries_0_1_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_1_data_hi_hi_lo = cat(sectored_entries_0_1_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_1_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_1_data_hi_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_1_data_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo)
node sectored_entries_0_1_data_hi = cat(sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo)
node _sectored_entries_0_1_data_T = cat(sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo)
connect sectored_entries[0][1].data[idx_1], _sectored_entries_0_1_data_T
when invalidate_refill :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
node _T_11 = eq(waddr_1, UInt<2>(0h2))
when _T_11 :
node _T_12 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_12 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
connect sectored_entries[0][2].tag_vpn, r_refill_tag
connect sectored_entries[0][2].tag_v, refill_v
connect sectored_entries[0][2].level, UInt<2>(0h0)
node idx_2 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][2].valid[idx_2], UInt<1>(0h1)
node sectored_entries_0_2_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_2_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_2_data_lo_lo_hi = cat(sectored_entries_0_2_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_2_data_lo_lo = cat(sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo)
node sectored_entries_0_2_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_2_data_lo_hi_lo = cat(sectored_entries_0_2_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_2_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_2_data_lo_hi_hi = cat(sectored_entries_0_2_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_2_data_lo_hi = cat(sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo)
node sectored_entries_0_2_data_lo = cat(sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo)
node sectored_entries_0_2_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_2_data_hi_lo_lo = cat(sectored_entries_0_2_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_2_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_2_data_hi_lo_hi = cat(sectored_entries_0_2_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_2_data_hi_lo = cat(sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo)
node sectored_entries_0_2_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_2_data_hi_hi_lo = cat(sectored_entries_0_2_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_2_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_2_data_hi_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_2_data_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo)
node sectored_entries_0_2_data_hi = cat(sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo)
node _sectored_entries_0_2_data_T = cat(sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo)
connect sectored_entries[0][2].data[idx_2], _sectored_entries_0_2_data_T
when invalidate_refill :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
node _T_13 = eq(waddr_1, UInt<2>(0h3))
when _T_13 :
node _T_14 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_14 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
connect sectored_entries[0][3].tag_vpn, r_refill_tag
connect sectored_entries[0][3].tag_v, refill_v
connect sectored_entries[0][3].level, UInt<2>(0h0)
node idx_3 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][3].valid[idx_3], UInt<1>(0h1)
node sectored_entries_0_3_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_3_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_3_data_lo_lo_hi = cat(sectored_entries_0_3_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_3_data_lo_lo = cat(sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo)
node sectored_entries_0_3_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_3_data_lo_hi_lo = cat(sectored_entries_0_3_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_3_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_3_data_lo_hi_hi = cat(sectored_entries_0_3_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_3_data_lo_hi = cat(sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo)
node sectored_entries_0_3_data_lo = cat(sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo)
node sectored_entries_0_3_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_3_data_hi_lo_lo = cat(sectored_entries_0_3_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_3_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_3_data_hi_lo_hi = cat(sectored_entries_0_3_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_3_data_hi_lo = cat(sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo)
node sectored_entries_0_3_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_3_data_hi_hi_lo = cat(sectored_entries_0_3_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_3_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_3_data_hi_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_3_data_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo)
node sectored_entries_0_3_data_hi = cat(sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo)
node _sectored_entries_0_3_data_T = cat(sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo)
connect sectored_entries[0][3].data[idx_3], _sectored_entries_0_3_data_T
when invalidate_refill :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
node _T_15 = eq(waddr_1, UInt<3>(0h4))
when _T_15 :
node _T_16 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_16 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
connect sectored_entries[0][4].tag_vpn, r_refill_tag
connect sectored_entries[0][4].tag_v, refill_v
connect sectored_entries[0][4].level, UInt<2>(0h0)
node idx_4 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][4].valid[idx_4], UInt<1>(0h1)
node sectored_entries_0_4_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_4_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_4_data_lo_lo_hi = cat(sectored_entries_0_4_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_4_data_lo_lo = cat(sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo)
node sectored_entries_0_4_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_4_data_lo_hi_lo = cat(sectored_entries_0_4_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_4_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_4_data_lo_hi_hi = cat(sectored_entries_0_4_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_4_data_lo_hi = cat(sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo)
node sectored_entries_0_4_data_lo = cat(sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo)
node sectored_entries_0_4_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_4_data_hi_lo_lo = cat(sectored_entries_0_4_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_4_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_4_data_hi_lo_hi = cat(sectored_entries_0_4_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_4_data_hi_lo = cat(sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo)
node sectored_entries_0_4_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_4_data_hi_hi_lo = cat(sectored_entries_0_4_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_4_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_4_data_hi_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_4_data_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo)
node sectored_entries_0_4_data_hi = cat(sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo)
node _sectored_entries_0_4_data_T = cat(sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo)
connect sectored_entries[0][4].data[idx_4], _sectored_entries_0_4_data_T
when invalidate_refill :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
node _T_17 = eq(waddr_1, UInt<3>(0h5))
when _T_17 :
node _T_18 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_18 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
connect sectored_entries[0][5].tag_vpn, r_refill_tag
connect sectored_entries[0][5].tag_v, refill_v
connect sectored_entries[0][5].level, UInt<2>(0h0)
node idx_5 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][5].valid[idx_5], UInt<1>(0h1)
node sectored_entries_0_5_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_5_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_5_data_lo_lo_hi = cat(sectored_entries_0_5_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_5_data_lo_lo = cat(sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo)
node sectored_entries_0_5_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_5_data_lo_hi_lo = cat(sectored_entries_0_5_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_5_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_5_data_lo_hi_hi = cat(sectored_entries_0_5_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_5_data_lo_hi = cat(sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo)
node sectored_entries_0_5_data_lo = cat(sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo)
node sectored_entries_0_5_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_5_data_hi_lo_lo = cat(sectored_entries_0_5_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_5_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_5_data_hi_lo_hi = cat(sectored_entries_0_5_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_5_data_hi_lo = cat(sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo)
node sectored_entries_0_5_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_5_data_hi_hi_lo = cat(sectored_entries_0_5_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_5_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_5_data_hi_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_5_data_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo)
node sectored_entries_0_5_data_hi = cat(sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo)
node _sectored_entries_0_5_data_T = cat(sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo)
connect sectored_entries[0][5].data[idx_5], _sectored_entries_0_5_data_T
when invalidate_refill :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
node _T_19 = eq(waddr_1, UInt<3>(0h6))
when _T_19 :
node _T_20 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_20 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
connect sectored_entries[0][6].tag_vpn, r_refill_tag
connect sectored_entries[0][6].tag_v, refill_v
connect sectored_entries[0][6].level, UInt<2>(0h0)
node idx_6 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][6].valid[idx_6], UInt<1>(0h1)
node sectored_entries_0_6_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_6_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_6_data_lo_lo_hi = cat(sectored_entries_0_6_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_6_data_lo_lo = cat(sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo)
node sectored_entries_0_6_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_6_data_lo_hi_lo = cat(sectored_entries_0_6_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_6_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_6_data_lo_hi_hi = cat(sectored_entries_0_6_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_6_data_lo_hi = cat(sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo)
node sectored_entries_0_6_data_lo = cat(sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo)
node sectored_entries_0_6_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_6_data_hi_lo_lo = cat(sectored_entries_0_6_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_6_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_6_data_hi_lo_hi = cat(sectored_entries_0_6_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_6_data_hi_lo = cat(sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo)
node sectored_entries_0_6_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_6_data_hi_hi_lo = cat(sectored_entries_0_6_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_6_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_6_data_hi_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_6_data_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo)
node sectored_entries_0_6_data_hi = cat(sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo)
node _sectored_entries_0_6_data_T = cat(sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo)
connect sectored_entries[0][6].data[idx_6], _sectored_entries_0_6_data_T
when invalidate_refill :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
node _T_21 = eq(waddr_1, UInt<3>(0h7))
when _T_21 :
node _T_22 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_22 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
connect sectored_entries[0][7].tag_vpn, r_refill_tag
connect sectored_entries[0][7].tag_v, refill_v
connect sectored_entries[0][7].level, UInt<2>(0h0)
node idx_7 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][7].valid[idx_7], UInt<1>(0h1)
node sectored_entries_0_7_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_7_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_7_data_lo_lo_hi = cat(sectored_entries_0_7_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_7_data_lo_lo = cat(sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo)
node sectored_entries_0_7_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_7_data_lo_hi_lo = cat(sectored_entries_0_7_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_7_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_7_data_lo_hi_hi = cat(sectored_entries_0_7_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_7_data_lo_hi = cat(sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo)
node sectored_entries_0_7_data_lo = cat(sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo)
node sectored_entries_0_7_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_7_data_hi_lo_lo = cat(sectored_entries_0_7_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_7_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_7_data_hi_lo_hi = cat(sectored_entries_0_7_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_7_data_hi_lo = cat(sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo)
node sectored_entries_0_7_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_7_data_hi_hi_lo = cat(sectored_entries_0_7_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_7_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_7_data_hi_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_7_data_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo)
node sectored_entries_0_7_data_hi = cat(sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo)
node _sectored_entries_0_7_data_T = cat(sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo)
connect sectored_entries[0][7].data[idx_7], _sectored_entries_0_7_data_T
when invalidate_refill :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
connect r_gpa_valid, io.ptw.resp.bits.gpa.valid
connect r_gpa, io.ptw.resp.bits.gpa.bits
connect r_gpa_is_pte, io.ptw.resp.bits.gpa_is_pte
node _entries_T = bits(vpn, 1, 0)
wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_1 : UInt<42>
connect _entries_WIRE_1, sectored_entries[0][0].data[_entries_T]
node _entries_T_1 = bits(_entries_WIRE_1, 0, 0)
connect _entries_WIRE.fragmented_superpage, _entries_T_1
node _entries_T_2 = bits(_entries_WIRE_1, 1, 1)
connect _entries_WIRE.c, _entries_T_2
node _entries_T_3 = bits(_entries_WIRE_1, 2, 2)
connect _entries_WIRE.eff, _entries_T_3
node _entries_T_4 = bits(_entries_WIRE_1, 3, 3)
connect _entries_WIRE.paa, _entries_T_4
node _entries_T_5 = bits(_entries_WIRE_1, 4, 4)
connect _entries_WIRE.pal, _entries_T_5
node _entries_T_6 = bits(_entries_WIRE_1, 5, 5)
connect _entries_WIRE.ppp, _entries_T_6
node _entries_T_7 = bits(_entries_WIRE_1, 6, 6)
connect _entries_WIRE.pr, _entries_T_7
node _entries_T_8 = bits(_entries_WIRE_1, 7, 7)
connect _entries_WIRE.px, _entries_T_8
node _entries_T_9 = bits(_entries_WIRE_1, 8, 8)
connect _entries_WIRE.pw, _entries_T_9
node _entries_T_10 = bits(_entries_WIRE_1, 9, 9)
connect _entries_WIRE.hr, _entries_T_10
node _entries_T_11 = bits(_entries_WIRE_1, 10, 10)
connect _entries_WIRE.hx, _entries_T_11
node _entries_T_12 = bits(_entries_WIRE_1, 11, 11)
connect _entries_WIRE.hw, _entries_T_12
node _entries_T_13 = bits(_entries_WIRE_1, 12, 12)
connect _entries_WIRE.sr, _entries_T_13
node _entries_T_14 = bits(_entries_WIRE_1, 13, 13)
connect _entries_WIRE.sx, _entries_T_14
node _entries_T_15 = bits(_entries_WIRE_1, 14, 14)
connect _entries_WIRE.sw, _entries_T_15
node _entries_T_16 = bits(_entries_WIRE_1, 15, 15)
connect _entries_WIRE.gf, _entries_T_16
node _entries_T_17 = bits(_entries_WIRE_1, 16, 16)
connect _entries_WIRE.pf, _entries_T_17
node _entries_T_18 = bits(_entries_WIRE_1, 17, 17)
connect _entries_WIRE.ae_stage2, _entries_T_18
node _entries_T_19 = bits(_entries_WIRE_1, 18, 18)
connect _entries_WIRE.ae_final, _entries_T_19
node _entries_T_20 = bits(_entries_WIRE_1, 19, 19)
connect _entries_WIRE.ae_ptw, _entries_T_20
node _entries_T_21 = bits(_entries_WIRE_1, 20, 20)
connect _entries_WIRE.g, _entries_T_21
node _entries_T_22 = bits(_entries_WIRE_1, 21, 21)
connect _entries_WIRE.u, _entries_T_22
node _entries_T_23 = bits(_entries_WIRE_1, 41, 22)
connect _entries_WIRE.ppn, _entries_T_23
inst entries_barrier of OptimizationBarrier_TLBEntryData_99
connect entries_barrier.clock, clock
connect entries_barrier.reset, reset
connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage
connect entries_barrier.io.x.c, _entries_WIRE.c
connect entries_barrier.io.x.eff, _entries_WIRE.eff
connect entries_barrier.io.x.paa, _entries_WIRE.paa
connect entries_barrier.io.x.pal, _entries_WIRE.pal
connect entries_barrier.io.x.ppp, _entries_WIRE.ppp
connect entries_barrier.io.x.pr, _entries_WIRE.pr
connect entries_barrier.io.x.px, _entries_WIRE.px
connect entries_barrier.io.x.pw, _entries_WIRE.pw
connect entries_barrier.io.x.hr, _entries_WIRE.hr
connect entries_barrier.io.x.hx, _entries_WIRE.hx
connect entries_barrier.io.x.hw, _entries_WIRE.hw
connect entries_barrier.io.x.sr, _entries_WIRE.sr
connect entries_barrier.io.x.sx, _entries_WIRE.sx
connect entries_barrier.io.x.sw, _entries_WIRE.sw
connect entries_barrier.io.x.gf, _entries_WIRE.gf
connect entries_barrier.io.x.pf, _entries_WIRE.pf
connect entries_barrier.io.x.ae_stage2, _entries_WIRE.ae_stage2
connect entries_barrier.io.x.ae_final, _entries_WIRE.ae_final
connect entries_barrier.io.x.ae_ptw, _entries_WIRE.ae_ptw
connect entries_barrier.io.x.g, _entries_WIRE.g
connect entries_barrier.io.x.u, _entries_WIRE.u
connect entries_barrier.io.x.ppn, _entries_WIRE.ppn
node _entries_T_24 = bits(vpn, 1, 0)
wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_3 : UInt<42>
connect _entries_WIRE_3, sectored_entries[0][1].data[_entries_T_24]
node _entries_T_25 = bits(_entries_WIRE_3, 0, 0)
connect _entries_WIRE_2.fragmented_superpage, _entries_T_25
node _entries_T_26 = bits(_entries_WIRE_3, 1, 1)
connect _entries_WIRE_2.c, _entries_T_26
node _entries_T_27 = bits(_entries_WIRE_3, 2, 2)
connect _entries_WIRE_2.eff, _entries_T_27
node _entries_T_28 = bits(_entries_WIRE_3, 3, 3)
connect _entries_WIRE_2.paa, _entries_T_28
node _entries_T_29 = bits(_entries_WIRE_3, 4, 4)
connect _entries_WIRE_2.pal, _entries_T_29
node _entries_T_30 = bits(_entries_WIRE_3, 5, 5)
connect _entries_WIRE_2.ppp, _entries_T_30
node _entries_T_31 = bits(_entries_WIRE_3, 6, 6)
connect _entries_WIRE_2.pr, _entries_T_31
node _entries_T_32 = bits(_entries_WIRE_3, 7, 7)
connect _entries_WIRE_2.px, _entries_T_32
node _entries_T_33 = bits(_entries_WIRE_3, 8, 8)
connect _entries_WIRE_2.pw, _entries_T_33
node _entries_T_34 = bits(_entries_WIRE_3, 9, 9)
connect _entries_WIRE_2.hr, _entries_T_34
node _entries_T_35 = bits(_entries_WIRE_3, 10, 10)
connect _entries_WIRE_2.hx, _entries_T_35
node _entries_T_36 = bits(_entries_WIRE_3, 11, 11)
connect _entries_WIRE_2.hw, _entries_T_36
node _entries_T_37 = bits(_entries_WIRE_3, 12, 12)
connect _entries_WIRE_2.sr, _entries_T_37
node _entries_T_38 = bits(_entries_WIRE_3, 13, 13)
connect _entries_WIRE_2.sx, _entries_T_38
node _entries_T_39 = bits(_entries_WIRE_3, 14, 14)
connect _entries_WIRE_2.sw, _entries_T_39
node _entries_T_40 = bits(_entries_WIRE_3, 15, 15)
connect _entries_WIRE_2.gf, _entries_T_40
node _entries_T_41 = bits(_entries_WIRE_3, 16, 16)
connect _entries_WIRE_2.pf, _entries_T_41
node _entries_T_42 = bits(_entries_WIRE_3, 17, 17)
connect _entries_WIRE_2.ae_stage2, _entries_T_42
node _entries_T_43 = bits(_entries_WIRE_3, 18, 18)
connect _entries_WIRE_2.ae_final, _entries_T_43
node _entries_T_44 = bits(_entries_WIRE_3, 19, 19)
connect _entries_WIRE_2.ae_ptw, _entries_T_44
node _entries_T_45 = bits(_entries_WIRE_3, 20, 20)
connect _entries_WIRE_2.g, _entries_T_45
node _entries_T_46 = bits(_entries_WIRE_3, 21, 21)
connect _entries_WIRE_2.u, _entries_T_46
node _entries_T_47 = bits(_entries_WIRE_3, 41, 22)
connect _entries_WIRE_2.ppn, _entries_T_47
inst entries_barrier_1 of OptimizationBarrier_TLBEntryData_100
connect entries_barrier_1.clock, clock
connect entries_barrier_1.reset, reset
connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage
connect entries_barrier_1.io.x.c, _entries_WIRE_2.c
connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff
connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa
connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal
connect entries_barrier_1.io.x.ppp, _entries_WIRE_2.ppp
connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr
connect entries_barrier_1.io.x.px, _entries_WIRE_2.px
connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw
connect entries_barrier_1.io.x.hr, _entries_WIRE_2.hr
connect entries_barrier_1.io.x.hx, _entries_WIRE_2.hx
connect entries_barrier_1.io.x.hw, _entries_WIRE_2.hw
connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr
connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx
connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw
connect entries_barrier_1.io.x.gf, _entries_WIRE_2.gf
connect entries_barrier_1.io.x.pf, _entries_WIRE_2.pf
connect entries_barrier_1.io.x.ae_stage2, _entries_WIRE_2.ae_stage2
connect entries_barrier_1.io.x.ae_final, _entries_WIRE_2.ae_final
connect entries_barrier_1.io.x.ae_ptw, _entries_WIRE_2.ae_ptw
connect entries_barrier_1.io.x.g, _entries_WIRE_2.g
connect entries_barrier_1.io.x.u, _entries_WIRE_2.u
connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn
node _entries_T_48 = bits(vpn, 1, 0)
wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_5 : UInt<42>
connect _entries_WIRE_5, sectored_entries[0][2].data[_entries_T_48]
node _entries_T_49 = bits(_entries_WIRE_5, 0, 0)
connect _entries_WIRE_4.fragmented_superpage, _entries_T_49
node _entries_T_50 = bits(_entries_WIRE_5, 1, 1)
connect _entries_WIRE_4.c, _entries_T_50
node _entries_T_51 = bits(_entries_WIRE_5, 2, 2)
connect _entries_WIRE_4.eff, _entries_T_51
node _entries_T_52 = bits(_entries_WIRE_5, 3, 3)
connect _entries_WIRE_4.paa, _entries_T_52
node _entries_T_53 = bits(_entries_WIRE_5, 4, 4)
connect _entries_WIRE_4.pal, _entries_T_53
node _entries_T_54 = bits(_entries_WIRE_5, 5, 5)
connect _entries_WIRE_4.ppp, _entries_T_54
node _entries_T_55 = bits(_entries_WIRE_5, 6, 6)
connect _entries_WIRE_4.pr, _entries_T_55
node _entries_T_56 = bits(_entries_WIRE_5, 7, 7)
connect _entries_WIRE_4.px, _entries_T_56
node _entries_T_57 = bits(_entries_WIRE_5, 8, 8)
connect _entries_WIRE_4.pw, _entries_T_57
node _entries_T_58 = bits(_entries_WIRE_5, 9, 9)
connect _entries_WIRE_4.hr, _entries_T_58
node _entries_T_59 = bits(_entries_WIRE_5, 10, 10)
connect _entries_WIRE_4.hx, _entries_T_59
node _entries_T_60 = bits(_entries_WIRE_5, 11, 11)
connect _entries_WIRE_4.hw, _entries_T_60
node _entries_T_61 = bits(_entries_WIRE_5, 12, 12)
connect _entries_WIRE_4.sr, _entries_T_61
node _entries_T_62 = bits(_entries_WIRE_5, 13, 13)
connect _entries_WIRE_4.sx, _entries_T_62
node _entries_T_63 = bits(_entries_WIRE_5, 14, 14)
connect _entries_WIRE_4.sw, _entries_T_63
node _entries_T_64 = bits(_entries_WIRE_5, 15, 15)
connect _entries_WIRE_4.gf, _entries_T_64
node _entries_T_65 = bits(_entries_WIRE_5, 16, 16)
connect _entries_WIRE_4.pf, _entries_T_65
node _entries_T_66 = bits(_entries_WIRE_5, 17, 17)
connect _entries_WIRE_4.ae_stage2, _entries_T_66
node _entries_T_67 = bits(_entries_WIRE_5, 18, 18)
connect _entries_WIRE_4.ae_final, _entries_T_67
node _entries_T_68 = bits(_entries_WIRE_5, 19, 19)
connect _entries_WIRE_4.ae_ptw, _entries_T_68
node _entries_T_69 = bits(_entries_WIRE_5, 20, 20)
connect _entries_WIRE_4.g, _entries_T_69
node _entries_T_70 = bits(_entries_WIRE_5, 21, 21)
connect _entries_WIRE_4.u, _entries_T_70
node _entries_T_71 = bits(_entries_WIRE_5, 41, 22)
connect _entries_WIRE_4.ppn, _entries_T_71
inst entries_barrier_2 of OptimizationBarrier_TLBEntryData_101
connect entries_barrier_2.clock, clock
connect entries_barrier_2.reset, reset
connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage
connect entries_barrier_2.io.x.c, _entries_WIRE_4.c
connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff
connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa
connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal
connect entries_barrier_2.io.x.ppp, _entries_WIRE_4.ppp
connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr
connect entries_barrier_2.io.x.px, _entries_WIRE_4.px
connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw
connect entries_barrier_2.io.x.hr, _entries_WIRE_4.hr
connect entries_barrier_2.io.x.hx, _entries_WIRE_4.hx
connect entries_barrier_2.io.x.hw, _entries_WIRE_4.hw
connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr
connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx
connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw
connect entries_barrier_2.io.x.gf, _entries_WIRE_4.gf
connect entries_barrier_2.io.x.pf, _entries_WIRE_4.pf
connect entries_barrier_2.io.x.ae_stage2, _entries_WIRE_4.ae_stage2
connect entries_barrier_2.io.x.ae_final, _entries_WIRE_4.ae_final
connect entries_barrier_2.io.x.ae_ptw, _entries_WIRE_4.ae_ptw
connect entries_barrier_2.io.x.g, _entries_WIRE_4.g
connect entries_barrier_2.io.x.u, _entries_WIRE_4.u
connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn
node _entries_T_72 = bits(vpn, 1, 0)
wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_7 : UInt<42>
connect _entries_WIRE_7, sectored_entries[0][3].data[_entries_T_72]
node _entries_T_73 = bits(_entries_WIRE_7, 0, 0)
connect _entries_WIRE_6.fragmented_superpage, _entries_T_73
node _entries_T_74 = bits(_entries_WIRE_7, 1, 1)
connect _entries_WIRE_6.c, _entries_T_74
node _entries_T_75 = bits(_entries_WIRE_7, 2, 2)
connect _entries_WIRE_6.eff, _entries_T_75
node _entries_T_76 = bits(_entries_WIRE_7, 3, 3)
connect _entries_WIRE_6.paa, _entries_T_76
node _entries_T_77 = bits(_entries_WIRE_7, 4, 4)
connect _entries_WIRE_6.pal, _entries_T_77
node _entries_T_78 = bits(_entries_WIRE_7, 5, 5)
connect _entries_WIRE_6.ppp, _entries_T_78
node _entries_T_79 = bits(_entries_WIRE_7, 6, 6)
connect _entries_WIRE_6.pr, _entries_T_79
node _entries_T_80 = bits(_entries_WIRE_7, 7, 7)
connect _entries_WIRE_6.px, _entries_T_80
node _entries_T_81 = bits(_entries_WIRE_7, 8, 8)
connect _entries_WIRE_6.pw, _entries_T_81
node _entries_T_82 = bits(_entries_WIRE_7, 9, 9)
connect _entries_WIRE_6.hr, _entries_T_82
node _entries_T_83 = bits(_entries_WIRE_7, 10, 10)
connect _entries_WIRE_6.hx, _entries_T_83
node _entries_T_84 = bits(_entries_WIRE_7, 11, 11)
connect _entries_WIRE_6.hw, _entries_T_84
node _entries_T_85 = bits(_entries_WIRE_7, 12, 12)
connect _entries_WIRE_6.sr, _entries_T_85
node _entries_T_86 = bits(_entries_WIRE_7, 13, 13)
connect _entries_WIRE_6.sx, _entries_T_86
node _entries_T_87 = bits(_entries_WIRE_7, 14, 14)
connect _entries_WIRE_6.sw, _entries_T_87
node _entries_T_88 = bits(_entries_WIRE_7, 15, 15)
connect _entries_WIRE_6.gf, _entries_T_88
node _entries_T_89 = bits(_entries_WIRE_7, 16, 16)
connect _entries_WIRE_6.pf, _entries_T_89
node _entries_T_90 = bits(_entries_WIRE_7, 17, 17)
connect _entries_WIRE_6.ae_stage2, _entries_T_90
node _entries_T_91 = bits(_entries_WIRE_7, 18, 18)
connect _entries_WIRE_6.ae_final, _entries_T_91
node _entries_T_92 = bits(_entries_WIRE_7, 19, 19)
connect _entries_WIRE_6.ae_ptw, _entries_T_92
node _entries_T_93 = bits(_entries_WIRE_7, 20, 20)
connect _entries_WIRE_6.g, _entries_T_93
node _entries_T_94 = bits(_entries_WIRE_7, 21, 21)
connect _entries_WIRE_6.u, _entries_T_94
node _entries_T_95 = bits(_entries_WIRE_7, 41, 22)
connect _entries_WIRE_6.ppn, _entries_T_95
inst entries_barrier_3 of OptimizationBarrier_TLBEntryData_102
connect entries_barrier_3.clock, clock
connect entries_barrier_3.reset, reset
connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage
connect entries_barrier_3.io.x.c, _entries_WIRE_6.c
connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff
connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa
connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal
connect entries_barrier_3.io.x.ppp, _entries_WIRE_6.ppp
connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr
connect entries_barrier_3.io.x.px, _entries_WIRE_6.px
connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw
connect entries_barrier_3.io.x.hr, _entries_WIRE_6.hr
connect entries_barrier_3.io.x.hx, _entries_WIRE_6.hx
connect entries_barrier_3.io.x.hw, _entries_WIRE_6.hw
connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr
connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx
connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw
connect entries_barrier_3.io.x.gf, _entries_WIRE_6.gf
connect entries_barrier_3.io.x.pf, _entries_WIRE_6.pf
connect entries_barrier_3.io.x.ae_stage2, _entries_WIRE_6.ae_stage2
connect entries_barrier_3.io.x.ae_final, _entries_WIRE_6.ae_final
connect entries_barrier_3.io.x.ae_ptw, _entries_WIRE_6.ae_ptw
connect entries_barrier_3.io.x.g, _entries_WIRE_6.g
connect entries_barrier_3.io.x.u, _entries_WIRE_6.u
connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn
node _entries_T_96 = bits(vpn, 1, 0)
wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_9 : UInt<42>
connect _entries_WIRE_9, sectored_entries[0][4].data[_entries_T_96]
node _entries_T_97 = bits(_entries_WIRE_9, 0, 0)
connect _entries_WIRE_8.fragmented_superpage, _entries_T_97
node _entries_T_98 = bits(_entries_WIRE_9, 1, 1)
connect _entries_WIRE_8.c, _entries_T_98
node _entries_T_99 = bits(_entries_WIRE_9, 2, 2)
connect _entries_WIRE_8.eff, _entries_T_99
node _entries_T_100 = bits(_entries_WIRE_9, 3, 3)
connect _entries_WIRE_8.paa, _entries_T_100
node _entries_T_101 = bits(_entries_WIRE_9, 4, 4)
connect _entries_WIRE_8.pal, _entries_T_101
node _entries_T_102 = bits(_entries_WIRE_9, 5, 5)
connect _entries_WIRE_8.ppp, _entries_T_102
node _entries_T_103 = bits(_entries_WIRE_9, 6, 6)
connect _entries_WIRE_8.pr, _entries_T_103
node _entries_T_104 = bits(_entries_WIRE_9, 7, 7)
connect _entries_WIRE_8.px, _entries_T_104
node _entries_T_105 = bits(_entries_WIRE_9, 8, 8)
connect _entries_WIRE_8.pw, _entries_T_105
node _entries_T_106 = bits(_entries_WIRE_9, 9, 9)
connect _entries_WIRE_8.hr, _entries_T_106
node _entries_T_107 = bits(_entries_WIRE_9, 10, 10)
connect _entries_WIRE_8.hx, _entries_T_107
node _entries_T_108 = bits(_entries_WIRE_9, 11, 11)
connect _entries_WIRE_8.hw, _entries_T_108
node _entries_T_109 = bits(_entries_WIRE_9, 12, 12)
connect _entries_WIRE_8.sr, _entries_T_109
node _entries_T_110 = bits(_entries_WIRE_9, 13, 13)
connect _entries_WIRE_8.sx, _entries_T_110
node _entries_T_111 = bits(_entries_WIRE_9, 14, 14)
connect _entries_WIRE_8.sw, _entries_T_111
node _entries_T_112 = bits(_entries_WIRE_9, 15, 15)
connect _entries_WIRE_8.gf, _entries_T_112
node _entries_T_113 = bits(_entries_WIRE_9, 16, 16)
connect _entries_WIRE_8.pf, _entries_T_113
node _entries_T_114 = bits(_entries_WIRE_9, 17, 17)
connect _entries_WIRE_8.ae_stage2, _entries_T_114
node _entries_T_115 = bits(_entries_WIRE_9, 18, 18)
connect _entries_WIRE_8.ae_final, _entries_T_115
node _entries_T_116 = bits(_entries_WIRE_9, 19, 19)
connect _entries_WIRE_8.ae_ptw, _entries_T_116
node _entries_T_117 = bits(_entries_WIRE_9, 20, 20)
connect _entries_WIRE_8.g, _entries_T_117
node _entries_T_118 = bits(_entries_WIRE_9, 21, 21)
connect _entries_WIRE_8.u, _entries_T_118
node _entries_T_119 = bits(_entries_WIRE_9, 41, 22)
connect _entries_WIRE_8.ppn, _entries_T_119
inst entries_barrier_4 of OptimizationBarrier_TLBEntryData_103
connect entries_barrier_4.clock, clock
connect entries_barrier_4.reset, reset
connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage
connect entries_barrier_4.io.x.c, _entries_WIRE_8.c
connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff
connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa
connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal
connect entries_barrier_4.io.x.ppp, _entries_WIRE_8.ppp
connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr
connect entries_barrier_4.io.x.px, _entries_WIRE_8.px
connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw
connect entries_barrier_4.io.x.hr, _entries_WIRE_8.hr
connect entries_barrier_4.io.x.hx, _entries_WIRE_8.hx
connect entries_barrier_4.io.x.hw, _entries_WIRE_8.hw
connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr
connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx
connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw
connect entries_barrier_4.io.x.gf, _entries_WIRE_8.gf
connect entries_barrier_4.io.x.pf, _entries_WIRE_8.pf
connect entries_barrier_4.io.x.ae_stage2, _entries_WIRE_8.ae_stage2
connect entries_barrier_4.io.x.ae_final, _entries_WIRE_8.ae_final
connect entries_barrier_4.io.x.ae_ptw, _entries_WIRE_8.ae_ptw
connect entries_barrier_4.io.x.g, _entries_WIRE_8.g
connect entries_barrier_4.io.x.u, _entries_WIRE_8.u
connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn
node _entries_T_120 = bits(vpn, 1, 0)
wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_11 : UInt<42>
connect _entries_WIRE_11, sectored_entries[0][5].data[_entries_T_120]
node _entries_T_121 = bits(_entries_WIRE_11, 0, 0)
connect _entries_WIRE_10.fragmented_superpage, _entries_T_121
node _entries_T_122 = bits(_entries_WIRE_11, 1, 1)
connect _entries_WIRE_10.c, _entries_T_122
node _entries_T_123 = bits(_entries_WIRE_11, 2, 2)
connect _entries_WIRE_10.eff, _entries_T_123
node _entries_T_124 = bits(_entries_WIRE_11, 3, 3)
connect _entries_WIRE_10.paa, _entries_T_124
node _entries_T_125 = bits(_entries_WIRE_11, 4, 4)
connect _entries_WIRE_10.pal, _entries_T_125
node _entries_T_126 = bits(_entries_WIRE_11, 5, 5)
connect _entries_WIRE_10.ppp, _entries_T_126
node _entries_T_127 = bits(_entries_WIRE_11, 6, 6)
connect _entries_WIRE_10.pr, _entries_T_127
node _entries_T_128 = bits(_entries_WIRE_11, 7, 7)
connect _entries_WIRE_10.px, _entries_T_128
node _entries_T_129 = bits(_entries_WIRE_11, 8, 8)
connect _entries_WIRE_10.pw, _entries_T_129
node _entries_T_130 = bits(_entries_WIRE_11, 9, 9)
connect _entries_WIRE_10.hr, _entries_T_130
node _entries_T_131 = bits(_entries_WIRE_11, 10, 10)
connect _entries_WIRE_10.hx, _entries_T_131
node _entries_T_132 = bits(_entries_WIRE_11, 11, 11)
connect _entries_WIRE_10.hw, _entries_T_132
node _entries_T_133 = bits(_entries_WIRE_11, 12, 12)
connect _entries_WIRE_10.sr, _entries_T_133
node _entries_T_134 = bits(_entries_WIRE_11, 13, 13)
connect _entries_WIRE_10.sx, _entries_T_134
node _entries_T_135 = bits(_entries_WIRE_11, 14, 14)
connect _entries_WIRE_10.sw, _entries_T_135
node _entries_T_136 = bits(_entries_WIRE_11, 15, 15)
connect _entries_WIRE_10.gf, _entries_T_136
node _entries_T_137 = bits(_entries_WIRE_11, 16, 16)
connect _entries_WIRE_10.pf, _entries_T_137
node _entries_T_138 = bits(_entries_WIRE_11, 17, 17)
connect _entries_WIRE_10.ae_stage2, _entries_T_138
node _entries_T_139 = bits(_entries_WIRE_11, 18, 18)
connect _entries_WIRE_10.ae_final, _entries_T_139
node _entries_T_140 = bits(_entries_WIRE_11, 19, 19)
connect _entries_WIRE_10.ae_ptw, _entries_T_140
node _entries_T_141 = bits(_entries_WIRE_11, 20, 20)
connect _entries_WIRE_10.g, _entries_T_141
node _entries_T_142 = bits(_entries_WIRE_11, 21, 21)
connect _entries_WIRE_10.u, _entries_T_142
node _entries_T_143 = bits(_entries_WIRE_11, 41, 22)
connect _entries_WIRE_10.ppn, _entries_T_143
inst entries_barrier_5 of OptimizationBarrier_TLBEntryData_104
connect entries_barrier_5.clock, clock
connect entries_barrier_5.reset, reset
connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage
connect entries_barrier_5.io.x.c, _entries_WIRE_10.c
connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff
connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa
connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal
connect entries_barrier_5.io.x.ppp, _entries_WIRE_10.ppp
connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr
connect entries_barrier_5.io.x.px, _entries_WIRE_10.px
connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw
connect entries_barrier_5.io.x.hr, _entries_WIRE_10.hr
connect entries_barrier_5.io.x.hx, _entries_WIRE_10.hx
connect entries_barrier_5.io.x.hw, _entries_WIRE_10.hw
connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr
connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx
connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw
connect entries_barrier_5.io.x.gf, _entries_WIRE_10.gf
connect entries_barrier_5.io.x.pf, _entries_WIRE_10.pf
connect entries_barrier_5.io.x.ae_stage2, _entries_WIRE_10.ae_stage2
connect entries_barrier_5.io.x.ae_final, _entries_WIRE_10.ae_final
connect entries_barrier_5.io.x.ae_ptw, _entries_WIRE_10.ae_ptw
connect entries_barrier_5.io.x.g, _entries_WIRE_10.g
connect entries_barrier_5.io.x.u, _entries_WIRE_10.u
connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn
node _entries_T_144 = bits(vpn, 1, 0)
wire _entries_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_13 : UInt<42>
connect _entries_WIRE_13, sectored_entries[0][6].data[_entries_T_144]
node _entries_T_145 = bits(_entries_WIRE_13, 0, 0)
connect _entries_WIRE_12.fragmented_superpage, _entries_T_145
node _entries_T_146 = bits(_entries_WIRE_13, 1, 1)
connect _entries_WIRE_12.c, _entries_T_146
node _entries_T_147 = bits(_entries_WIRE_13, 2, 2)
connect _entries_WIRE_12.eff, _entries_T_147
node _entries_T_148 = bits(_entries_WIRE_13, 3, 3)
connect _entries_WIRE_12.paa, _entries_T_148
node _entries_T_149 = bits(_entries_WIRE_13, 4, 4)
connect _entries_WIRE_12.pal, _entries_T_149
node _entries_T_150 = bits(_entries_WIRE_13, 5, 5)
connect _entries_WIRE_12.ppp, _entries_T_150
node _entries_T_151 = bits(_entries_WIRE_13, 6, 6)
connect _entries_WIRE_12.pr, _entries_T_151
node _entries_T_152 = bits(_entries_WIRE_13, 7, 7)
connect _entries_WIRE_12.px, _entries_T_152
node _entries_T_153 = bits(_entries_WIRE_13, 8, 8)
connect _entries_WIRE_12.pw, _entries_T_153
node _entries_T_154 = bits(_entries_WIRE_13, 9, 9)
connect _entries_WIRE_12.hr, _entries_T_154
node _entries_T_155 = bits(_entries_WIRE_13, 10, 10)
connect _entries_WIRE_12.hx, _entries_T_155
node _entries_T_156 = bits(_entries_WIRE_13, 11, 11)
connect _entries_WIRE_12.hw, _entries_T_156
node _entries_T_157 = bits(_entries_WIRE_13, 12, 12)
connect _entries_WIRE_12.sr, _entries_T_157
node _entries_T_158 = bits(_entries_WIRE_13, 13, 13)
connect _entries_WIRE_12.sx, _entries_T_158
node _entries_T_159 = bits(_entries_WIRE_13, 14, 14)
connect _entries_WIRE_12.sw, _entries_T_159
node _entries_T_160 = bits(_entries_WIRE_13, 15, 15)
connect _entries_WIRE_12.gf, _entries_T_160
node _entries_T_161 = bits(_entries_WIRE_13, 16, 16)
connect _entries_WIRE_12.pf, _entries_T_161
node _entries_T_162 = bits(_entries_WIRE_13, 17, 17)
connect _entries_WIRE_12.ae_stage2, _entries_T_162
node _entries_T_163 = bits(_entries_WIRE_13, 18, 18)
connect _entries_WIRE_12.ae_final, _entries_T_163
node _entries_T_164 = bits(_entries_WIRE_13, 19, 19)
connect _entries_WIRE_12.ae_ptw, _entries_T_164
node _entries_T_165 = bits(_entries_WIRE_13, 20, 20)
connect _entries_WIRE_12.g, _entries_T_165
node _entries_T_166 = bits(_entries_WIRE_13, 21, 21)
connect _entries_WIRE_12.u, _entries_T_166
node _entries_T_167 = bits(_entries_WIRE_13, 41, 22)
connect _entries_WIRE_12.ppn, _entries_T_167
inst entries_barrier_6 of OptimizationBarrier_TLBEntryData_105
connect entries_barrier_6.clock, clock
connect entries_barrier_6.reset, reset
connect entries_barrier_6.io.x.fragmented_superpage, _entries_WIRE_12.fragmented_superpage
connect entries_barrier_6.io.x.c, _entries_WIRE_12.c
connect entries_barrier_6.io.x.eff, _entries_WIRE_12.eff
connect entries_barrier_6.io.x.paa, _entries_WIRE_12.paa
connect entries_barrier_6.io.x.pal, _entries_WIRE_12.pal
connect entries_barrier_6.io.x.ppp, _entries_WIRE_12.ppp
connect entries_barrier_6.io.x.pr, _entries_WIRE_12.pr
connect entries_barrier_6.io.x.px, _entries_WIRE_12.px
connect entries_barrier_6.io.x.pw, _entries_WIRE_12.pw
connect entries_barrier_6.io.x.hr, _entries_WIRE_12.hr
connect entries_barrier_6.io.x.hx, _entries_WIRE_12.hx
connect entries_barrier_6.io.x.hw, _entries_WIRE_12.hw
connect entries_barrier_6.io.x.sr, _entries_WIRE_12.sr
connect entries_barrier_6.io.x.sx, _entries_WIRE_12.sx
connect entries_barrier_6.io.x.sw, _entries_WIRE_12.sw
connect entries_barrier_6.io.x.gf, _entries_WIRE_12.gf
connect entries_barrier_6.io.x.pf, _entries_WIRE_12.pf
connect entries_barrier_6.io.x.ae_stage2, _entries_WIRE_12.ae_stage2
connect entries_barrier_6.io.x.ae_final, _entries_WIRE_12.ae_final
connect entries_barrier_6.io.x.ae_ptw, _entries_WIRE_12.ae_ptw
connect entries_barrier_6.io.x.g, _entries_WIRE_12.g
connect entries_barrier_6.io.x.u, _entries_WIRE_12.u
connect entries_barrier_6.io.x.ppn, _entries_WIRE_12.ppn
node _entries_T_168 = bits(vpn, 1, 0)
wire _entries_WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_15 : UInt<42>
connect _entries_WIRE_15, sectored_entries[0][7].data[_entries_T_168]
node _entries_T_169 = bits(_entries_WIRE_15, 0, 0)
connect _entries_WIRE_14.fragmented_superpage, _entries_T_169
node _entries_T_170 = bits(_entries_WIRE_15, 1, 1)
connect _entries_WIRE_14.c, _entries_T_170
node _entries_T_171 = bits(_entries_WIRE_15, 2, 2)
connect _entries_WIRE_14.eff, _entries_T_171
node _entries_T_172 = bits(_entries_WIRE_15, 3, 3)
connect _entries_WIRE_14.paa, _entries_T_172
node _entries_T_173 = bits(_entries_WIRE_15, 4, 4)
connect _entries_WIRE_14.pal, _entries_T_173
node _entries_T_174 = bits(_entries_WIRE_15, 5, 5)
connect _entries_WIRE_14.ppp, _entries_T_174
node _entries_T_175 = bits(_entries_WIRE_15, 6, 6)
connect _entries_WIRE_14.pr, _entries_T_175
node _entries_T_176 = bits(_entries_WIRE_15, 7, 7)
connect _entries_WIRE_14.px, _entries_T_176
node _entries_T_177 = bits(_entries_WIRE_15, 8, 8)
connect _entries_WIRE_14.pw, _entries_T_177
node _entries_T_178 = bits(_entries_WIRE_15, 9, 9)
connect _entries_WIRE_14.hr, _entries_T_178
node _entries_T_179 = bits(_entries_WIRE_15, 10, 10)
connect _entries_WIRE_14.hx, _entries_T_179
node _entries_T_180 = bits(_entries_WIRE_15, 11, 11)
connect _entries_WIRE_14.hw, _entries_T_180
node _entries_T_181 = bits(_entries_WIRE_15, 12, 12)
connect _entries_WIRE_14.sr, _entries_T_181
node _entries_T_182 = bits(_entries_WIRE_15, 13, 13)
connect _entries_WIRE_14.sx, _entries_T_182
node _entries_T_183 = bits(_entries_WIRE_15, 14, 14)
connect _entries_WIRE_14.sw, _entries_T_183
node _entries_T_184 = bits(_entries_WIRE_15, 15, 15)
connect _entries_WIRE_14.gf, _entries_T_184
node _entries_T_185 = bits(_entries_WIRE_15, 16, 16)
connect _entries_WIRE_14.pf, _entries_T_185
node _entries_T_186 = bits(_entries_WIRE_15, 17, 17)
connect _entries_WIRE_14.ae_stage2, _entries_T_186
node _entries_T_187 = bits(_entries_WIRE_15, 18, 18)
connect _entries_WIRE_14.ae_final, _entries_T_187
node _entries_T_188 = bits(_entries_WIRE_15, 19, 19)
connect _entries_WIRE_14.ae_ptw, _entries_T_188
node _entries_T_189 = bits(_entries_WIRE_15, 20, 20)
connect _entries_WIRE_14.g, _entries_T_189
node _entries_T_190 = bits(_entries_WIRE_15, 21, 21)
connect _entries_WIRE_14.u, _entries_T_190
node _entries_T_191 = bits(_entries_WIRE_15, 41, 22)
connect _entries_WIRE_14.ppn, _entries_T_191
inst entries_barrier_7 of OptimizationBarrier_TLBEntryData_106
connect entries_barrier_7.clock, clock
connect entries_barrier_7.reset, reset
connect entries_barrier_7.io.x.fragmented_superpage, _entries_WIRE_14.fragmented_superpage
connect entries_barrier_7.io.x.c, _entries_WIRE_14.c
connect entries_barrier_7.io.x.eff, _entries_WIRE_14.eff
connect entries_barrier_7.io.x.paa, _entries_WIRE_14.paa
connect entries_barrier_7.io.x.pal, _entries_WIRE_14.pal
connect entries_barrier_7.io.x.ppp, _entries_WIRE_14.ppp
connect entries_barrier_7.io.x.pr, _entries_WIRE_14.pr
connect entries_barrier_7.io.x.px, _entries_WIRE_14.px
connect entries_barrier_7.io.x.pw, _entries_WIRE_14.pw
connect entries_barrier_7.io.x.hr, _entries_WIRE_14.hr
connect entries_barrier_7.io.x.hx, _entries_WIRE_14.hx
connect entries_barrier_7.io.x.hw, _entries_WIRE_14.hw
connect entries_barrier_7.io.x.sr, _entries_WIRE_14.sr
connect entries_barrier_7.io.x.sx, _entries_WIRE_14.sx
connect entries_barrier_7.io.x.sw, _entries_WIRE_14.sw
connect entries_barrier_7.io.x.gf, _entries_WIRE_14.gf
connect entries_barrier_7.io.x.pf, _entries_WIRE_14.pf
connect entries_barrier_7.io.x.ae_stage2, _entries_WIRE_14.ae_stage2
connect entries_barrier_7.io.x.ae_final, _entries_WIRE_14.ae_final
connect entries_barrier_7.io.x.ae_ptw, _entries_WIRE_14.ae_ptw
connect entries_barrier_7.io.x.g, _entries_WIRE_14.g
connect entries_barrier_7.io.x.u, _entries_WIRE_14.u
connect entries_barrier_7.io.x.ppn, _entries_WIRE_14.ppn
wire _entries_WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_17 : UInt<42>
connect _entries_WIRE_17, superpage_entries[0].data[0]
node _entries_T_192 = bits(_entries_WIRE_17, 0, 0)
connect _entries_WIRE_16.fragmented_superpage, _entries_T_192
node _entries_T_193 = bits(_entries_WIRE_17, 1, 1)
connect _entries_WIRE_16.c, _entries_T_193
node _entries_T_194 = bits(_entries_WIRE_17, 2, 2)
connect _entries_WIRE_16.eff, _entries_T_194
node _entries_T_195 = bits(_entries_WIRE_17, 3, 3)
connect _entries_WIRE_16.paa, _entries_T_195
node _entries_T_196 = bits(_entries_WIRE_17, 4, 4)
connect _entries_WIRE_16.pal, _entries_T_196
node _entries_T_197 = bits(_entries_WIRE_17, 5, 5)
connect _entries_WIRE_16.ppp, _entries_T_197
node _entries_T_198 = bits(_entries_WIRE_17, 6, 6)
connect _entries_WIRE_16.pr, _entries_T_198
node _entries_T_199 = bits(_entries_WIRE_17, 7, 7)
connect _entries_WIRE_16.px, _entries_T_199
node _entries_T_200 = bits(_entries_WIRE_17, 8, 8)
connect _entries_WIRE_16.pw, _entries_T_200
node _entries_T_201 = bits(_entries_WIRE_17, 9, 9)
connect _entries_WIRE_16.hr, _entries_T_201
node _entries_T_202 = bits(_entries_WIRE_17, 10, 10)
connect _entries_WIRE_16.hx, _entries_T_202
node _entries_T_203 = bits(_entries_WIRE_17, 11, 11)
connect _entries_WIRE_16.hw, _entries_T_203
node _entries_T_204 = bits(_entries_WIRE_17, 12, 12)
connect _entries_WIRE_16.sr, _entries_T_204
node _entries_T_205 = bits(_entries_WIRE_17, 13, 13)
connect _entries_WIRE_16.sx, _entries_T_205
node _entries_T_206 = bits(_entries_WIRE_17, 14, 14)
connect _entries_WIRE_16.sw, _entries_T_206
node _entries_T_207 = bits(_entries_WIRE_17, 15, 15)
connect _entries_WIRE_16.gf, _entries_T_207
node _entries_T_208 = bits(_entries_WIRE_17, 16, 16)
connect _entries_WIRE_16.pf, _entries_T_208
node _entries_T_209 = bits(_entries_WIRE_17, 17, 17)
connect _entries_WIRE_16.ae_stage2, _entries_T_209
node _entries_T_210 = bits(_entries_WIRE_17, 18, 18)
connect _entries_WIRE_16.ae_final, _entries_T_210
node _entries_T_211 = bits(_entries_WIRE_17, 19, 19)
connect _entries_WIRE_16.ae_ptw, _entries_T_211
node _entries_T_212 = bits(_entries_WIRE_17, 20, 20)
connect _entries_WIRE_16.g, _entries_T_212
node _entries_T_213 = bits(_entries_WIRE_17, 21, 21)
connect _entries_WIRE_16.u, _entries_T_213
node _entries_T_214 = bits(_entries_WIRE_17, 41, 22)
connect _entries_WIRE_16.ppn, _entries_T_214
inst entries_barrier_8 of OptimizationBarrier_TLBEntryData_107
connect entries_barrier_8.clock, clock
connect entries_barrier_8.reset, reset
connect entries_barrier_8.io.x.fragmented_superpage, _entries_WIRE_16.fragmented_superpage
connect entries_barrier_8.io.x.c, _entries_WIRE_16.c
connect entries_barrier_8.io.x.eff, _entries_WIRE_16.eff
connect entries_barrier_8.io.x.paa, _entries_WIRE_16.paa
connect entries_barrier_8.io.x.pal, _entries_WIRE_16.pal
connect entries_barrier_8.io.x.ppp, _entries_WIRE_16.ppp
connect entries_barrier_8.io.x.pr, _entries_WIRE_16.pr
connect entries_barrier_8.io.x.px, _entries_WIRE_16.px
connect entries_barrier_8.io.x.pw, _entries_WIRE_16.pw
connect entries_barrier_8.io.x.hr, _entries_WIRE_16.hr
connect entries_barrier_8.io.x.hx, _entries_WIRE_16.hx
connect entries_barrier_8.io.x.hw, _entries_WIRE_16.hw
connect entries_barrier_8.io.x.sr, _entries_WIRE_16.sr
connect entries_barrier_8.io.x.sx, _entries_WIRE_16.sx
connect entries_barrier_8.io.x.sw, _entries_WIRE_16.sw
connect entries_barrier_8.io.x.gf, _entries_WIRE_16.gf
connect entries_barrier_8.io.x.pf, _entries_WIRE_16.pf
connect entries_barrier_8.io.x.ae_stage2, _entries_WIRE_16.ae_stage2
connect entries_barrier_8.io.x.ae_final, _entries_WIRE_16.ae_final
connect entries_barrier_8.io.x.ae_ptw, _entries_WIRE_16.ae_ptw
connect entries_barrier_8.io.x.g, _entries_WIRE_16.g
connect entries_barrier_8.io.x.u, _entries_WIRE_16.u
connect entries_barrier_8.io.x.ppn, _entries_WIRE_16.ppn
wire _entries_WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_19 : UInt<42>
connect _entries_WIRE_19, superpage_entries[1].data[0]
node _entries_T_215 = bits(_entries_WIRE_19, 0, 0)
connect _entries_WIRE_18.fragmented_superpage, _entries_T_215
node _entries_T_216 = bits(_entries_WIRE_19, 1, 1)
connect _entries_WIRE_18.c, _entries_T_216
node _entries_T_217 = bits(_entries_WIRE_19, 2, 2)
connect _entries_WIRE_18.eff, _entries_T_217
node _entries_T_218 = bits(_entries_WIRE_19, 3, 3)
connect _entries_WIRE_18.paa, _entries_T_218
node _entries_T_219 = bits(_entries_WIRE_19, 4, 4)
connect _entries_WIRE_18.pal, _entries_T_219
node _entries_T_220 = bits(_entries_WIRE_19, 5, 5)
connect _entries_WIRE_18.ppp, _entries_T_220
node _entries_T_221 = bits(_entries_WIRE_19, 6, 6)
connect _entries_WIRE_18.pr, _entries_T_221
node _entries_T_222 = bits(_entries_WIRE_19, 7, 7)
connect _entries_WIRE_18.px, _entries_T_222
node _entries_T_223 = bits(_entries_WIRE_19, 8, 8)
connect _entries_WIRE_18.pw, _entries_T_223
node _entries_T_224 = bits(_entries_WIRE_19, 9, 9)
connect _entries_WIRE_18.hr, _entries_T_224
node _entries_T_225 = bits(_entries_WIRE_19, 10, 10)
connect _entries_WIRE_18.hx, _entries_T_225
node _entries_T_226 = bits(_entries_WIRE_19, 11, 11)
connect _entries_WIRE_18.hw, _entries_T_226
node _entries_T_227 = bits(_entries_WIRE_19, 12, 12)
connect _entries_WIRE_18.sr, _entries_T_227
node _entries_T_228 = bits(_entries_WIRE_19, 13, 13)
connect _entries_WIRE_18.sx, _entries_T_228
node _entries_T_229 = bits(_entries_WIRE_19, 14, 14)
connect _entries_WIRE_18.sw, _entries_T_229
node _entries_T_230 = bits(_entries_WIRE_19, 15, 15)
connect _entries_WIRE_18.gf, _entries_T_230
node _entries_T_231 = bits(_entries_WIRE_19, 16, 16)
connect _entries_WIRE_18.pf, _entries_T_231
node _entries_T_232 = bits(_entries_WIRE_19, 17, 17)
connect _entries_WIRE_18.ae_stage2, _entries_T_232
node _entries_T_233 = bits(_entries_WIRE_19, 18, 18)
connect _entries_WIRE_18.ae_final, _entries_T_233
node _entries_T_234 = bits(_entries_WIRE_19, 19, 19)
connect _entries_WIRE_18.ae_ptw, _entries_T_234
node _entries_T_235 = bits(_entries_WIRE_19, 20, 20)
connect _entries_WIRE_18.g, _entries_T_235
node _entries_T_236 = bits(_entries_WIRE_19, 21, 21)
connect _entries_WIRE_18.u, _entries_T_236
node _entries_T_237 = bits(_entries_WIRE_19, 41, 22)
connect _entries_WIRE_18.ppn, _entries_T_237
inst entries_barrier_9 of OptimizationBarrier_TLBEntryData_108
connect entries_barrier_9.clock, clock
connect entries_barrier_9.reset, reset
connect entries_barrier_9.io.x.fragmented_superpage, _entries_WIRE_18.fragmented_superpage
connect entries_barrier_9.io.x.c, _entries_WIRE_18.c
connect entries_barrier_9.io.x.eff, _entries_WIRE_18.eff
connect entries_barrier_9.io.x.paa, _entries_WIRE_18.paa
connect entries_barrier_9.io.x.pal, _entries_WIRE_18.pal
connect entries_barrier_9.io.x.ppp, _entries_WIRE_18.ppp
connect entries_barrier_9.io.x.pr, _entries_WIRE_18.pr
connect entries_barrier_9.io.x.px, _entries_WIRE_18.px
connect entries_barrier_9.io.x.pw, _entries_WIRE_18.pw
connect entries_barrier_9.io.x.hr, _entries_WIRE_18.hr
connect entries_barrier_9.io.x.hx, _entries_WIRE_18.hx
connect entries_barrier_9.io.x.hw, _entries_WIRE_18.hw
connect entries_barrier_9.io.x.sr, _entries_WIRE_18.sr
connect entries_barrier_9.io.x.sx, _entries_WIRE_18.sx
connect entries_barrier_9.io.x.sw, _entries_WIRE_18.sw
connect entries_barrier_9.io.x.gf, _entries_WIRE_18.gf
connect entries_barrier_9.io.x.pf, _entries_WIRE_18.pf
connect entries_barrier_9.io.x.ae_stage2, _entries_WIRE_18.ae_stage2
connect entries_barrier_9.io.x.ae_final, _entries_WIRE_18.ae_final
connect entries_barrier_9.io.x.ae_ptw, _entries_WIRE_18.ae_ptw
connect entries_barrier_9.io.x.g, _entries_WIRE_18.g
connect entries_barrier_9.io.x.u, _entries_WIRE_18.u
connect entries_barrier_9.io.x.ppn, _entries_WIRE_18.ppn
wire _entries_WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_21 : UInt<42>
connect _entries_WIRE_21, superpage_entries[2].data[0]
node _entries_T_238 = bits(_entries_WIRE_21, 0, 0)
connect _entries_WIRE_20.fragmented_superpage, _entries_T_238
node _entries_T_239 = bits(_entries_WIRE_21, 1, 1)
connect _entries_WIRE_20.c, _entries_T_239
node _entries_T_240 = bits(_entries_WIRE_21, 2, 2)
connect _entries_WIRE_20.eff, _entries_T_240
node _entries_T_241 = bits(_entries_WIRE_21, 3, 3)
connect _entries_WIRE_20.paa, _entries_T_241
node _entries_T_242 = bits(_entries_WIRE_21, 4, 4)
connect _entries_WIRE_20.pal, _entries_T_242
node _entries_T_243 = bits(_entries_WIRE_21, 5, 5)
connect _entries_WIRE_20.ppp, _entries_T_243
node _entries_T_244 = bits(_entries_WIRE_21, 6, 6)
connect _entries_WIRE_20.pr, _entries_T_244
node _entries_T_245 = bits(_entries_WIRE_21, 7, 7)
connect _entries_WIRE_20.px, _entries_T_245
node _entries_T_246 = bits(_entries_WIRE_21, 8, 8)
connect _entries_WIRE_20.pw, _entries_T_246
node _entries_T_247 = bits(_entries_WIRE_21, 9, 9)
connect _entries_WIRE_20.hr, _entries_T_247
node _entries_T_248 = bits(_entries_WIRE_21, 10, 10)
connect _entries_WIRE_20.hx, _entries_T_248
node _entries_T_249 = bits(_entries_WIRE_21, 11, 11)
connect _entries_WIRE_20.hw, _entries_T_249
node _entries_T_250 = bits(_entries_WIRE_21, 12, 12)
connect _entries_WIRE_20.sr, _entries_T_250
node _entries_T_251 = bits(_entries_WIRE_21, 13, 13)
connect _entries_WIRE_20.sx, _entries_T_251
node _entries_T_252 = bits(_entries_WIRE_21, 14, 14)
connect _entries_WIRE_20.sw, _entries_T_252
node _entries_T_253 = bits(_entries_WIRE_21, 15, 15)
connect _entries_WIRE_20.gf, _entries_T_253
node _entries_T_254 = bits(_entries_WIRE_21, 16, 16)
connect _entries_WIRE_20.pf, _entries_T_254
node _entries_T_255 = bits(_entries_WIRE_21, 17, 17)
connect _entries_WIRE_20.ae_stage2, _entries_T_255
node _entries_T_256 = bits(_entries_WIRE_21, 18, 18)
connect _entries_WIRE_20.ae_final, _entries_T_256
node _entries_T_257 = bits(_entries_WIRE_21, 19, 19)
connect _entries_WIRE_20.ae_ptw, _entries_T_257
node _entries_T_258 = bits(_entries_WIRE_21, 20, 20)
connect _entries_WIRE_20.g, _entries_T_258
node _entries_T_259 = bits(_entries_WIRE_21, 21, 21)
connect _entries_WIRE_20.u, _entries_T_259
node _entries_T_260 = bits(_entries_WIRE_21, 41, 22)
connect _entries_WIRE_20.ppn, _entries_T_260
inst entries_barrier_10 of OptimizationBarrier_TLBEntryData_109
connect entries_barrier_10.clock, clock
connect entries_barrier_10.reset, reset
connect entries_barrier_10.io.x.fragmented_superpage, _entries_WIRE_20.fragmented_superpage
connect entries_barrier_10.io.x.c, _entries_WIRE_20.c
connect entries_barrier_10.io.x.eff, _entries_WIRE_20.eff
connect entries_barrier_10.io.x.paa, _entries_WIRE_20.paa
connect entries_barrier_10.io.x.pal, _entries_WIRE_20.pal
connect entries_barrier_10.io.x.ppp, _entries_WIRE_20.ppp
connect entries_barrier_10.io.x.pr, _entries_WIRE_20.pr
connect entries_barrier_10.io.x.px, _entries_WIRE_20.px
connect entries_barrier_10.io.x.pw, _entries_WIRE_20.pw
connect entries_barrier_10.io.x.hr, _entries_WIRE_20.hr
connect entries_barrier_10.io.x.hx, _entries_WIRE_20.hx
connect entries_barrier_10.io.x.hw, _entries_WIRE_20.hw
connect entries_barrier_10.io.x.sr, _entries_WIRE_20.sr
connect entries_barrier_10.io.x.sx, _entries_WIRE_20.sx
connect entries_barrier_10.io.x.sw, _entries_WIRE_20.sw
connect entries_barrier_10.io.x.gf, _entries_WIRE_20.gf
connect entries_barrier_10.io.x.pf, _entries_WIRE_20.pf
connect entries_barrier_10.io.x.ae_stage2, _entries_WIRE_20.ae_stage2
connect entries_barrier_10.io.x.ae_final, _entries_WIRE_20.ae_final
connect entries_barrier_10.io.x.ae_ptw, _entries_WIRE_20.ae_ptw
connect entries_barrier_10.io.x.g, _entries_WIRE_20.g
connect entries_barrier_10.io.x.u, _entries_WIRE_20.u
connect entries_barrier_10.io.x.ppn, _entries_WIRE_20.ppn
wire _entries_WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_23 : UInt<42>
connect _entries_WIRE_23, superpage_entries[3].data[0]
node _entries_T_261 = bits(_entries_WIRE_23, 0, 0)
connect _entries_WIRE_22.fragmented_superpage, _entries_T_261
node _entries_T_262 = bits(_entries_WIRE_23, 1, 1)
connect _entries_WIRE_22.c, _entries_T_262
node _entries_T_263 = bits(_entries_WIRE_23, 2, 2)
connect _entries_WIRE_22.eff, _entries_T_263
node _entries_T_264 = bits(_entries_WIRE_23, 3, 3)
connect _entries_WIRE_22.paa, _entries_T_264
node _entries_T_265 = bits(_entries_WIRE_23, 4, 4)
connect _entries_WIRE_22.pal, _entries_T_265
node _entries_T_266 = bits(_entries_WIRE_23, 5, 5)
connect _entries_WIRE_22.ppp, _entries_T_266
node _entries_T_267 = bits(_entries_WIRE_23, 6, 6)
connect _entries_WIRE_22.pr, _entries_T_267
node _entries_T_268 = bits(_entries_WIRE_23, 7, 7)
connect _entries_WIRE_22.px, _entries_T_268
node _entries_T_269 = bits(_entries_WIRE_23, 8, 8)
connect _entries_WIRE_22.pw, _entries_T_269
node _entries_T_270 = bits(_entries_WIRE_23, 9, 9)
connect _entries_WIRE_22.hr, _entries_T_270
node _entries_T_271 = bits(_entries_WIRE_23, 10, 10)
connect _entries_WIRE_22.hx, _entries_T_271
node _entries_T_272 = bits(_entries_WIRE_23, 11, 11)
connect _entries_WIRE_22.hw, _entries_T_272
node _entries_T_273 = bits(_entries_WIRE_23, 12, 12)
connect _entries_WIRE_22.sr, _entries_T_273
node _entries_T_274 = bits(_entries_WIRE_23, 13, 13)
connect _entries_WIRE_22.sx, _entries_T_274
node _entries_T_275 = bits(_entries_WIRE_23, 14, 14)
connect _entries_WIRE_22.sw, _entries_T_275
node _entries_T_276 = bits(_entries_WIRE_23, 15, 15)
connect _entries_WIRE_22.gf, _entries_T_276
node _entries_T_277 = bits(_entries_WIRE_23, 16, 16)
connect _entries_WIRE_22.pf, _entries_T_277
node _entries_T_278 = bits(_entries_WIRE_23, 17, 17)
connect _entries_WIRE_22.ae_stage2, _entries_T_278
node _entries_T_279 = bits(_entries_WIRE_23, 18, 18)
connect _entries_WIRE_22.ae_final, _entries_T_279
node _entries_T_280 = bits(_entries_WIRE_23, 19, 19)
connect _entries_WIRE_22.ae_ptw, _entries_T_280
node _entries_T_281 = bits(_entries_WIRE_23, 20, 20)
connect _entries_WIRE_22.g, _entries_T_281
node _entries_T_282 = bits(_entries_WIRE_23, 21, 21)
connect _entries_WIRE_22.u, _entries_T_282
node _entries_T_283 = bits(_entries_WIRE_23, 41, 22)
connect _entries_WIRE_22.ppn, _entries_T_283
inst entries_barrier_11 of OptimizationBarrier_TLBEntryData_110
connect entries_barrier_11.clock, clock
connect entries_barrier_11.reset, reset
connect entries_barrier_11.io.x.fragmented_superpage, _entries_WIRE_22.fragmented_superpage
connect entries_barrier_11.io.x.c, _entries_WIRE_22.c
connect entries_barrier_11.io.x.eff, _entries_WIRE_22.eff
connect entries_barrier_11.io.x.paa, _entries_WIRE_22.paa
connect entries_barrier_11.io.x.pal, _entries_WIRE_22.pal
connect entries_barrier_11.io.x.ppp, _entries_WIRE_22.ppp
connect entries_barrier_11.io.x.pr, _entries_WIRE_22.pr
connect entries_barrier_11.io.x.px, _entries_WIRE_22.px
connect entries_barrier_11.io.x.pw, _entries_WIRE_22.pw
connect entries_barrier_11.io.x.hr, _entries_WIRE_22.hr
connect entries_barrier_11.io.x.hx, _entries_WIRE_22.hx
connect entries_barrier_11.io.x.hw, _entries_WIRE_22.hw
connect entries_barrier_11.io.x.sr, _entries_WIRE_22.sr
connect entries_barrier_11.io.x.sx, _entries_WIRE_22.sx
connect entries_barrier_11.io.x.sw, _entries_WIRE_22.sw
connect entries_barrier_11.io.x.gf, _entries_WIRE_22.gf
connect entries_barrier_11.io.x.pf, _entries_WIRE_22.pf
connect entries_barrier_11.io.x.ae_stage2, _entries_WIRE_22.ae_stage2
connect entries_barrier_11.io.x.ae_final, _entries_WIRE_22.ae_final
connect entries_barrier_11.io.x.ae_ptw, _entries_WIRE_22.ae_ptw
connect entries_barrier_11.io.x.g, _entries_WIRE_22.g
connect entries_barrier_11.io.x.u, _entries_WIRE_22.u
connect entries_barrier_11.io.x.ppn, _entries_WIRE_22.ppn
wire _entries_WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_25 : UInt<42>
connect _entries_WIRE_25, special_entry.data[0]
node _entries_T_284 = bits(_entries_WIRE_25, 0, 0)
connect _entries_WIRE_24.fragmented_superpage, _entries_T_284
node _entries_T_285 = bits(_entries_WIRE_25, 1, 1)
connect _entries_WIRE_24.c, _entries_T_285
node _entries_T_286 = bits(_entries_WIRE_25, 2, 2)
connect _entries_WIRE_24.eff, _entries_T_286
node _entries_T_287 = bits(_entries_WIRE_25, 3, 3)
connect _entries_WIRE_24.paa, _entries_T_287
node _entries_T_288 = bits(_entries_WIRE_25, 4, 4)
connect _entries_WIRE_24.pal, _entries_T_288
node _entries_T_289 = bits(_entries_WIRE_25, 5, 5)
connect _entries_WIRE_24.ppp, _entries_T_289
node _entries_T_290 = bits(_entries_WIRE_25, 6, 6)
connect _entries_WIRE_24.pr, _entries_T_290
node _entries_T_291 = bits(_entries_WIRE_25, 7, 7)
connect _entries_WIRE_24.px, _entries_T_291
node _entries_T_292 = bits(_entries_WIRE_25, 8, 8)
connect _entries_WIRE_24.pw, _entries_T_292
node _entries_T_293 = bits(_entries_WIRE_25, 9, 9)
connect _entries_WIRE_24.hr, _entries_T_293
node _entries_T_294 = bits(_entries_WIRE_25, 10, 10)
connect _entries_WIRE_24.hx, _entries_T_294
node _entries_T_295 = bits(_entries_WIRE_25, 11, 11)
connect _entries_WIRE_24.hw, _entries_T_295
node _entries_T_296 = bits(_entries_WIRE_25, 12, 12)
connect _entries_WIRE_24.sr, _entries_T_296
node _entries_T_297 = bits(_entries_WIRE_25, 13, 13)
connect _entries_WIRE_24.sx, _entries_T_297
node _entries_T_298 = bits(_entries_WIRE_25, 14, 14)
connect _entries_WIRE_24.sw, _entries_T_298
node _entries_T_299 = bits(_entries_WIRE_25, 15, 15)
connect _entries_WIRE_24.gf, _entries_T_299
node _entries_T_300 = bits(_entries_WIRE_25, 16, 16)
connect _entries_WIRE_24.pf, _entries_T_300
node _entries_T_301 = bits(_entries_WIRE_25, 17, 17)
connect _entries_WIRE_24.ae_stage2, _entries_T_301
node _entries_T_302 = bits(_entries_WIRE_25, 18, 18)
connect _entries_WIRE_24.ae_final, _entries_T_302
node _entries_T_303 = bits(_entries_WIRE_25, 19, 19)
connect _entries_WIRE_24.ae_ptw, _entries_T_303
node _entries_T_304 = bits(_entries_WIRE_25, 20, 20)
connect _entries_WIRE_24.g, _entries_T_304
node _entries_T_305 = bits(_entries_WIRE_25, 21, 21)
connect _entries_WIRE_24.u, _entries_T_305
node _entries_T_306 = bits(_entries_WIRE_25, 41, 22)
connect _entries_WIRE_24.ppn, _entries_T_306
inst entries_barrier_12 of OptimizationBarrier_TLBEntryData_111
connect entries_barrier_12.clock, clock
connect entries_barrier_12.reset, reset
connect entries_barrier_12.io.x.fragmented_superpage, _entries_WIRE_24.fragmented_superpage
connect entries_barrier_12.io.x.c, _entries_WIRE_24.c
connect entries_barrier_12.io.x.eff, _entries_WIRE_24.eff
connect entries_barrier_12.io.x.paa, _entries_WIRE_24.paa
connect entries_barrier_12.io.x.pal, _entries_WIRE_24.pal
connect entries_barrier_12.io.x.ppp, _entries_WIRE_24.ppp
connect entries_barrier_12.io.x.pr, _entries_WIRE_24.pr
connect entries_barrier_12.io.x.px, _entries_WIRE_24.px
connect entries_barrier_12.io.x.pw, _entries_WIRE_24.pw
connect entries_barrier_12.io.x.hr, _entries_WIRE_24.hr
connect entries_barrier_12.io.x.hx, _entries_WIRE_24.hx
connect entries_barrier_12.io.x.hw, _entries_WIRE_24.hw
connect entries_barrier_12.io.x.sr, _entries_WIRE_24.sr
connect entries_barrier_12.io.x.sx, _entries_WIRE_24.sx
connect entries_barrier_12.io.x.sw, _entries_WIRE_24.sw
connect entries_barrier_12.io.x.gf, _entries_WIRE_24.gf
connect entries_barrier_12.io.x.pf, _entries_WIRE_24.pf
connect entries_barrier_12.io.x.ae_stage2, _entries_WIRE_24.ae_stage2
connect entries_barrier_12.io.x.ae_final, _entries_WIRE_24.ae_final
connect entries_barrier_12.io.x.ae_ptw, _entries_WIRE_24.ae_ptw
connect entries_barrier_12.io.x.g, _entries_WIRE_24.g
connect entries_barrier_12.io.x.u, _entries_WIRE_24.u
connect entries_barrier_12.io.x.ppn, _entries_WIRE_24.ppn
node _ppn_T = eq(vm_enabled, UInt<1>(0h0))
node ppn_res = shr(entries_barrier_8.io.y.ppn, 18)
node _ppn_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h1))
node ppn_ignore = or(_ppn_ignore_T, UInt<1>(0h0))
node _ppn_T_1 = mux(ppn_ignore, vpn, UInt<1>(0h0))
node _ppn_T_2 = or(_ppn_T_1, entries_barrier_8.io.y.ppn)
node _ppn_T_3 = bits(_ppn_T_2, 17, 9)
node _ppn_T_4 = cat(ppn_res, _ppn_T_3)
node _ppn_ignore_T_1 = lt(superpage_entries[0].level, UInt<2>(0h2))
node ppn_ignore_1 = or(_ppn_ignore_T_1, UInt<1>(0h1))
node _ppn_T_5 = mux(ppn_ignore_1, vpn, UInt<1>(0h0))
node _ppn_T_6 = or(_ppn_T_5, entries_barrier_8.io.y.ppn)
node _ppn_T_7 = bits(_ppn_T_6, 8, 0)
node _ppn_T_8 = cat(_ppn_T_4, _ppn_T_7)
node ppn_res_1 = shr(entries_barrier_9.io.y.ppn, 18)
node _ppn_ignore_T_2 = lt(superpage_entries[1].level, UInt<1>(0h1))
node ppn_ignore_2 = or(_ppn_ignore_T_2, UInt<1>(0h0))
node _ppn_T_9 = mux(ppn_ignore_2, vpn, UInt<1>(0h0))
node _ppn_T_10 = or(_ppn_T_9, entries_barrier_9.io.y.ppn)
node _ppn_T_11 = bits(_ppn_T_10, 17, 9)
node _ppn_T_12 = cat(ppn_res_1, _ppn_T_11)
node _ppn_ignore_T_3 = lt(superpage_entries[1].level, UInt<2>(0h2))
node ppn_ignore_3 = or(_ppn_ignore_T_3, UInt<1>(0h1))
node _ppn_T_13 = mux(ppn_ignore_3, vpn, UInt<1>(0h0))
node _ppn_T_14 = or(_ppn_T_13, entries_barrier_9.io.y.ppn)
node _ppn_T_15 = bits(_ppn_T_14, 8, 0)
node _ppn_T_16 = cat(_ppn_T_12, _ppn_T_15)
node ppn_res_2 = shr(entries_barrier_10.io.y.ppn, 18)
node _ppn_ignore_T_4 = lt(superpage_entries[2].level, UInt<1>(0h1))
node ppn_ignore_4 = or(_ppn_ignore_T_4, UInt<1>(0h0))
node _ppn_T_17 = mux(ppn_ignore_4, vpn, UInt<1>(0h0))
node _ppn_T_18 = or(_ppn_T_17, entries_barrier_10.io.y.ppn)
node _ppn_T_19 = bits(_ppn_T_18, 17, 9)
node _ppn_T_20 = cat(ppn_res_2, _ppn_T_19)
node _ppn_ignore_T_5 = lt(superpage_entries[2].level, UInt<2>(0h2))
node ppn_ignore_5 = or(_ppn_ignore_T_5, UInt<1>(0h1))
node _ppn_T_21 = mux(ppn_ignore_5, vpn, UInt<1>(0h0))
node _ppn_T_22 = or(_ppn_T_21, entries_barrier_10.io.y.ppn)
node _ppn_T_23 = bits(_ppn_T_22, 8, 0)
node _ppn_T_24 = cat(_ppn_T_20, _ppn_T_23)
node ppn_res_3 = shr(entries_barrier_11.io.y.ppn, 18)
node _ppn_ignore_T_6 = lt(superpage_entries[3].level, UInt<1>(0h1))
node ppn_ignore_6 = or(_ppn_ignore_T_6, UInt<1>(0h0))
node _ppn_T_25 = mux(ppn_ignore_6, vpn, UInt<1>(0h0))
node _ppn_T_26 = or(_ppn_T_25, entries_barrier_11.io.y.ppn)
node _ppn_T_27 = bits(_ppn_T_26, 17, 9)
node _ppn_T_28 = cat(ppn_res_3, _ppn_T_27)
node _ppn_ignore_T_7 = lt(superpage_entries[3].level, UInt<2>(0h2))
node ppn_ignore_7 = or(_ppn_ignore_T_7, UInt<1>(0h1))
node _ppn_T_29 = mux(ppn_ignore_7, vpn, UInt<1>(0h0))
node _ppn_T_30 = or(_ppn_T_29, entries_barrier_11.io.y.ppn)
node _ppn_T_31 = bits(_ppn_T_30, 8, 0)
node _ppn_T_32 = cat(_ppn_T_28, _ppn_T_31)
node ppn_res_4 = shr(entries_barrier_12.io.y.ppn, 18)
node _ppn_ignore_T_8 = lt(special_entry.level, UInt<1>(0h1))
node ppn_ignore_8 = or(_ppn_ignore_T_8, UInt<1>(0h0))
node _ppn_T_33 = mux(ppn_ignore_8, vpn, UInt<1>(0h0))
node _ppn_T_34 = or(_ppn_T_33, entries_barrier_12.io.y.ppn)
node _ppn_T_35 = bits(_ppn_T_34, 17, 9)
node _ppn_T_36 = cat(ppn_res_4, _ppn_T_35)
node _ppn_ignore_T_9 = lt(special_entry.level, UInt<2>(0h2))
node ppn_ignore_9 = or(_ppn_ignore_T_9, UInt<1>(0h0))
node _ppn_T_37 = mux(ppn_ignore_9, vpn, UInt<1>(0h0))
node _ppn_T_38 = or(_ppn_T_37, entries_barrier_12.io.y.ppn)
node _ppn_T_39 = bits(_ppn_T_38, 8, 0)
node _ppn_T_40 = cat(_ppn_T_36, _ppn_T_39)
node _ppn_T_41 = bits(vpn, 19, 0)
node _ppn_T_42 = mux(hitsVec_0, entries_barrier.io.y.ppn, UInt<1>(0h0))
node _ppn_T_43 = mux(hitsVec_1, entries_barrier_1.io.y.ppn, UInt<1>(0h0))
node _ppn_T_44 = mux(hitsVec_2, entries_barrier_2.io.y.ppn, UInt<1>(0h0))
node _ppn_T_45 = mux(hitsVec_3, entries_barrier_3.io.y.ppn, UInt<1>(0h0))
node _ppn_T_46 = mux(hitsVec_4, entries_barrier_4.io.y.ppn, UInt<1>(0h0))
node _ppn_T_47 = mux(hitsVec_5, entries_barrier_5.io.y.ppn, UInt<1>(0h0))
node _ppn_T_48 = mux(hitsVec_6, entries_barrier_6.io.y.ppn, UInt<1>(0h0))
node _ppn_T_49 = mux(hitsVec_7, entries_barrier_7.io.y.ppn, UInt<1>(0h0))
node _ppn_T_50 = mux(hitsVec_8, _ppn_T_8, UInt<1>(0h0))
node _ppn_T_51 = mux(hitsVec_9, _ppn_T_16, UInt<1>(0h0))
node _ppn_T_52 = mux(hitsVec_10, _ppn_T_24, UInt<1>(0h0))
node _ppn_T_53 = mux(hitsVec_11, _ppn_T_32, UInt<1>(0h0))
node _ppn_T_54 = mux(hitsVec_12, _ppn_T_40, UInt<1>(0h0))
node _ppn_T_55 = mux(_ppn_T, _ppn_T_41, UInt<1>(0h0))
node _ppn_T_56 = or(_ppn_T_42, _ppn_T_43)
node _ppn_T_57 = or(_ppn_T_56, _ppn_T_44)
node _ppn_T_58 = or(_ppn_T_57, _ppn_T_45)
node _ppn_T_59 = or(_ppn_T_58, _ppn_T_46)
node _ppn_T_60 = or(_ppn_T_59, _ppn_T_47)
node _ppn_T_61 = or(_ppn_T_60, _ppn_T_48)
node _ppn_T_62 = or(_ppn_T_61, _ppn_T_49)
node _ppn_T_63 = or(_ppn_T_62, _ppn_T_50)
node _ppn_T_64 = or(_ppn_T_63, _ppn_T_51)
node _ppn_T_65 = or(_ppn_T_64, _ppn_T_52)
node _ppn_T_66 = or(_ppn_T_65, _ppn_T_53)
node _ppn_T_67 = or(_ppn_T_66, _ppn_T_54)
node _ppn_T_68 = or(_ppn_T_67, _ppn_T_55)
wire ppn : UInt<20>
connect ppn, _ppn_T_68
node ptw_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_ptw, entries_barrier_1.io.y.ae_ptw)
node ptw_ae_array_lo_lo = cat(ptw_ae_array_lo_lo_hi, entries_barrier.io.y.ae_ptw)
node ptw_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_ptw, entries_barrier_4.io.y.ae_ptw)
node ptw_ae_array_lo_hi = cat(ptw_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_ptw)
node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, ptw_ae_array_lo_lo)
node ptw_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_ptw, entries_barrier_7.io.y.ae_ptw)
node ptw_ae_array_hi_lo = cat(ptw_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_ptw)
node ptw_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_ptw, entries_barrier_9.io.y.ae_ptw)
node ptw_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_ptw, entries_barrier_11.io.y.ae_ptw)
node ptw_ae_array_hi_hi = cat(ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo)
node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, ptw_ae_array_hi_lo)
node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo)
node ptw_ae_array = cat(UInt<1>(0h0), _ptw_ae_array_T)
node final_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_final, entries_barrier_1.io.y.ae_final)
node final_ae_array_lo_lo = cat(final_ae_array_lo_lo_hi, entries_barrier.io.y.ae_final)
node final_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_final, entries_barrier_4.io.y.ae_final)
node final_ae_array_lo_hi = cat(final_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_final)
node final_ae_array_lo = cat(final_ae_array_lo_hi, final_ae_array_lo_lo)
node final_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_final, entries_barrier_7.io.y.ae_final)
node final_ae_array_hi_lo = cat(final_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_final)
node final_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_final, entries_barrier_9.io.y.ae_final)
node final_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_final, entries_barrier_11.io.y.ae_final)
node final_ae_array_hi_hi = cat(final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo)
node final_ae_array_hi = cat(final_ae_array_hi_hi, final_ae_array_hi_lo)
node _final_ae_array_T = cat(final_ae_array_hi, final_ae_array_lo)
node final_ae_array = cat(UInt<1>(0h0), _final_ae_array_T)
node ptw_pf_array_lo_lo_hi = cat(entries_barrier_2.io.y.pf, entries_barrier_1.io.y.pf)
node ptw_pf_array_lo_lo = cat(ptw_pf_array_lo_lo_hi, entries_barrier.io.y.pf)
node ptw_pf_array_lo_hi_hi = cat(entries_barrier_5.io.y.pf, entries_barrier_4.io.y.pf)
node ptw_pf_array_lo_hi = cat(ptw_pf_array_lo_hi_hi, entries_barrier_3.io.y.pf)
node ptw_pf_array_lo = cat(ptw_pf_array_lo_hi, ptw_pf_array_lo_lo)
node ptw_pf_array_hi_lo_hi = cat(entries_barrier_8.io.y.pf, entries_barrier_7.io.y.pf)
node ptw_pf_array_hi_lo = cat(ptw_pf_array_hi_lo_hi, entries_barrier_6.io.y.pf)
node ptw_pf_array_hi_hi_lo = cat(entries_barrier_10.io.y.pf, entries_barrier_9.io.y.pf)
node ptw_pf_array_hi_hi_hi = cat(entries_barrier_12.io.y.pf, entries_barrier_11.io.y.pf)
node ptw_pf_array_hi_hi = cat(ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo)
node ptw_pf_array_hi = cat(ptw_pf_array_hi_hi, ptw_pf_array_hi_lo)
node _ptw_pf_array_T = cat(ptw_pf_array_hi, ptw_pf_array_lo)
node ptw_pf_array = cat(UInt<1>(0h0), _ptw_pf_array_T)
node ptw_gf_array_lo_lo_hi = cat(entries_barrier_2.io.y.gf, entries_barrier_1.io.y.gf)
node ptw_gf_array_lo_lo = cat(ptw_gf_array_lo_lo_hi, entries_barrier.io.y.gf)
node ptw_gf_array_lo_hi_hi = cat(entries_barrier_5.io.y.gf, entries_barrier_4.io.y.gf)
node ptw_gf_array_lo_hi = cat(ptw_gf_array_lo_hi_hi, entries_barrier_3.io.y.gf)
node ptw_gf_array_lo = cat(ptw_gf_array_lo_hi, ptw_gf_array_lo_lo)
node ptw_gf_array_hi_lo_hi = cat(entries_barrier_8.io.y.gf, entries_barrier_7.io.y.gf)
node ptw_gf_array_hi_lo = cat(ptw_gf_array_hi_lo_hi, entries_barrier_6.io.y.gf)
node ptw_gf_array_hi_hi_lo = cat(entries_barrier_10.io.y.gf, entries_barrier_9.io.y.gf)
node ptw_gf_array_hi_hi_hi = cat(entries_barrier_12.io.y.gf, entries_barrier_11.io.y.gf)
node ptw_gf_array_hi_hi = cat(ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo)
node ptw_gf_array_hi = cat(ptw_gf_array_hi_hi, ptw_gf_array_hi_lo)
node _ptw_gf_array_T = cat(ptw_gf_array_hi, ptw_gf_array_lo)
node ptw_gf_array = cat(UInt<1>(0h0), _ptw_gf_array_T)
node sum = mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum)
node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0))
node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, sum)
node priv_rw_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u)
node priv_rw_ok_lo_lo = cat(priv_rw_ok_lo_lo_hi, entries_barrier.io.y.u)
node priv_rw_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u)
node priv_rw_ok_lo_hi = cat(priv_rw_ok_lo_hi_hi, entries_barrier_3.io.y.u)
node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, priv_rw_ok_lo_lo)
node priv_rw_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u)
node priv_rw_ok_hi_lo = cat(priv_rw_ok_hi_lo_hi, entries_barrier_6.io.y.u)
node priv_rw_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u)
node priv_rw_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u)
node priv_rw_ok_hi_hi = cat(priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo)
node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, priv_rw_ok_hi_lo)
node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo)
node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0))
node priv_rw_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u)
node priv_rw_ok_lo_lo_1 = cat(priv_rw_ok_lo_lo_hi_1, entries_barrier.io.y.u)
node priv_rw_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u)
node priv_rw_ok_lo_hi_1 = cat(priv_rw_ok_lo_hi_hi_1, entries_barrier_3.io.y.u)
node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1)
node priv_rw_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u)
node priv_rw_ok_hi_lo_1 = cat(priv_rw_ok_hi_lo_hi_1, entries_barrier_6.io.y.u)
node priv_rw_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u)
node priv_rw_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u)
node priv_rw_ok_hi_hi_1 = cat(priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1)
node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1)
node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1)
node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4)
node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0))
node priv_rw_ok = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6)
node priv_x_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u)
node priv_x_ok_lo_lo = cat(priv_x_ok_lo_lo_hi, entries_barrier.io.y.u)
node priv_x_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u)
node priv_x_ok_lo_hi = cat(priv_x_ok_lo_hi_hi, entries_barrier_3.io.y.u)
node priv_x_ok_lo = cat(priv_x_ok_lo_hi, priv_x_ok_lo_lo)
node priv_x_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u)
node priv_x_ok_hi_lo = cat(priv_x_ok_hi_lo_hi, entries_barrier_6.io.y.u)
node priv_x_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u)
node priv_x_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u)
node priv_x_ok_hi_hi = cat(priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo)
node priv_x_ok_hi = cat(priv_x_ok_hi_hi, priv_x_ok_hi_lo)
node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo)
node _priv_x_ok_T_1 = not(_priv_x_ok_T)
node priv_x_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u)
node priv_x_ok_lo_lo_1 = cat(priv_x_ok_lo_lo_hi_1, entries_barrier.io.y.u)
node priv_x_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u)
node priv_x_ok_lo_hi_1 = cat(priv_x_ok_lo_hi_hi_1, entries_barrier_3.io.y.u)
node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1)
node priv_x_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u)
node priv_x_ok_hi_lo_1 = cat(priv_x_ok_hi_lo_hi_1, entries_barrier_6.io.y.u)
node priv_x_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u)
node priv_x_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u)
node priv_x_ok_hi_hi_1 = cat(priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1)
node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1)
node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1)
node priv_x_ok = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2)
node _stage1_bypass_T = mux(UInt<1>(0h0), UInt<13>(0h1fff), UInt<13>(0h0))
node _stage1_bypass_T_1 = eq(stage1_en, UInt<1>(0h0))
node _stage1_bypass_T_2 = mux(_stage1_bypass_T_1, UInt<13>(0h1fff), UInt<13>(0h0))
node stage1_bypass_lo_lo_hi = cat(entries_barrier_2.io.y.ae_stage2, entries_barrier_1.io.y.ae_stage2)
node stage1_bypass_lo_lo = cat(stage1_bypass_lo_lo_hi, entries_barrier.io.y.ae_stage2)
node stage1_bypass_lo_hi_hi = cat(entries_barrier_5.io.y.ae_stage2, entries_barrier_4.io.y.ae_stage2)
node stage1_bypass_lo_hi = cat(stage1_bypass_lo_hi_hi, entries_barrier_3.io.y.ae_stage2)
node stage1_bypass_lo = cat(stage1_bypass_lo_hi, stage1_bypass_lo_lo)
node stage1_bypass_hi_lo_hi = cat(entries_barrier_8.io.y.ae_stage2, entries_barrier_7.io.y.ae_stage2)
node stage1_bypass_hi_lo = cat(stage1_bypass_hi_lo_hi, entries_barrier_6.io.y.ae_stage2)
node stage1_bypass_hi_hi_lo = cat(entries_barrier_10.io.y.ae_stage2, entries_barrier_9.io.y.ae_stage2)
node stage1_bypass_hi_hi_hi = cat(entries_barrier_12.io.y.ae_stage2, entries_barrier_11.io.y.ae_stage2)
node stage1_bypass_hi_hi = cat(stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo)
node stage1_bypass_hi = cat(stage1_bypass_hi_hi, stage1_bypass_hi_lo)
node _stage1_bypass_T_3 = cat(stage1_bypass_hi, stage1_bypass_lo)
node _stage1_bypass_T_4 = or(_stage1_bypass_T_2, _stage1_bypass_T_3)
node stage1_bypass = and(_stage1_bypass_T, _stage1_bypass_T_4)
node _mxr_T = mux(priv_v, io.ptw.gstatus.mxr, UInt<1>(0h0))
node mxr = or(io.ptw.status.mxr, _mxr_T)
node r_array_lo_lo_hi = cat(entries_barrier_2.io.y.sr, entries_barrier_1.io.y.sr)
node r_array_lo_lo = cat(r_array_lo_lo_hi, entries_barrier.io.y.sr)
node r_array_lo_hi_hi = cat(entries_barrier_5.io.y.sr, entries_barrier_4.io.y.sr)
node r_array_lo_hi = cat(r_array_lo_hi_hi, entries_barrier_3.io.y.sr)
node r_array_lo = cat(r_array_lo_hi, r_array_lo_lo)
node r_array_hi_lo_hi = cat(entries_barrier_8.io.y.sr, entries_barrier_7.io.y.sr)
node r_array_hi_lo = cat(r_array_hi_lo_hi, entries_barrier_6.io.y.sr)
node r_array_hi_hi_lo = cat(entries_barrier_10.io.y.sr, entries_barrier_9.io.y.sr)
node r_array_hi_hi_hi = cat(entries_barrier_12.io.y.sr, entries_barrier_11.io.y.sr)
node r_array_hi_hi = cat(r_array_hi_hi_hi, r_array_hi_hi_lo)
node r_array_hi = cat(r_array_hi_hi, r_array_hi_lo)
node _r_array_T = cat(r_array_hi, r_array_lo)
node r_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx)
node r_array_lo_lo_1 = cat(r_array_lo_lo_hi_1, entries_barrier.io.y.sx)
node r_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx)
node r_array_lo_hi_1 = cat(r_array_lo_hi_hi_1, entries_barrier_3.io.y.sx)
node r_array_lo_1 = cat(r_array_lo_hi_1, r_array_lo_lo_1)
node r_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx)
node r_array_hi_lo_1 = cat(r_array_hi_lo_hi_1, entries_barrier_6.io.y.sx)
node r_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx)
node r_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx)
node r_array_hi_hi_1 = cat(r_array_hi_hi_hi_1, r_array_hi_hi_lo_1)
node r_array_hi_1 = cat(r_array_hi_hi_1, r_array_hi_lo_1)
node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1)
node _r_array_T_2 = mux(mxr, _r_array_T_1, UInt<1>(0h0))
node _r_array_T_3 = or(_r_array_T, _r_array_T_2)
node _r_array_T_4 = and(priv_rw_ok, _r_array_T_3)
node _r_array_T_5 = or(_r_array_T_4, stage1_bypass)
node r_array = cat(UInt<1>(0h1), _r_array_T_5)
node w_array_lo_lo_hi = cat(entries_barrier_2.io.y.sw, entries_barrier_1.io.y.sw)
node w_array_lo_lo = cat(w_array_lo_lo_hi, entries_barrier.io.y.sw)
node w_array_lo_hi_hi = cat(entries_barrier_5.io.y.sw, entries_barrier_4.io.y.sw)
node w_array_lo_hi = cat(w_array_lo_hi_hi, entries_barrier_3.io.y.sw)
node w_array_lo = cat(w_array_lo_hi, w_array_lo_lo)
node w_array_hi_lo_hi = cat(entries_barrier_8.io.y.sw, entries_barrier_7.io.y.sw)
node w_array_hi_lo = cat(w_array_hi_lo_hi, entries_barrier_6.io.y.sw)
node w_array_hi_hi_lo = cat(entries_barrier_10.io.y.sw, entries_barrier_9.io.y.sw)
node w_array_hi_hi_hi = cat(entries_barrier_12.io.y.sw, entries_barrier_11.io.y.sw)
node w_array_hi_hi = cat(w_array_hi_hi_hi, w_array_hi_hi_lo)
node w_array_hi = cat(w_array_hi_hi, w_array_hi_lo)
node _w_array_T = cat(w_array_hi, w_array_lo)
node _w_array_T_1 = and(priv_rw_ok, _w_array_T)
node _w_array_T_2 = or(_w_array_T_1, stage1_bypass)
node w_array = cat(UInt<1>(0h1), _w_array_T_2)
node x_array_lo_lo_hi = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx)
node x_array_lo_lo = cat(x_array_lo_lo_hi, entries_barrier.io.y.sx)
node x_array_lo_hi_hi = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx)
node x_array_lo_hi = cat(x_array_lo_hi_hi, entries_barrier_3.io.y.sx)
node x_array_lo = cat(x_array_lo_hi, x_array_lo_lo)
node x_array_hi_lo_hi = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx)
node x_array_hi_lo = cat(x_array_hi_lo_hi, entries_barrier_6.io.y.sx)
node x_array_hi_hi_lo = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx)
node x_array_hi_hi_hi = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx)
node x_array_hi_hi = cat(x_array_hi_hi_hi, x_array_hi_hi_lo)
node x_array_hi = cat(x_array_hi_hi, x_array_hi_lo)
node _x_array_T = cat(x_array_hi, x_array_lo)
node _x_array_T_1 = and(priv_x_ok, _x_array_T)
node _x_array_T_2 = or(_x_array_T_1, stage1_bypass)
node x_array = cat(UInt<1>(0h1), _x_array_T_2)
node _stage2_bypass_T = eq(stage2_en, UInt<1>(0h0))
node stage2_bypass = mux(_stage2_bypass_T, UInt<13>(0h1fff), UInt<13>(0h0))
node hr_array_lo_lo_hi = cat(entries_barrier_2.io.y.hr, entries_barrier_1.io.y.hr)
node hr_array_lo_lo = cat(hr_array_lo_lo_hi, entries_barrier.io.y.hr)
node hr_array_lo_hi_hi = cat(entries_barrier_5.io.y.hr, entries_barrier_4.io.y.hr)
node hr_array_lo_hi = cat(hr_array_lo_hi_hi, entries_barrier_3.io.y.hr)
node hr_array_lo = cat(hr_array_lo_hi, hr_array_lo_lo)
node hr_array_hi_lo_hi = cat(entries_barrier_8.io.y.hr, entries_barrier_7.io.y.hr)
node hr_array_hi_lo = cat(hr_array_hi_lo_hi, entries_barrier_6.io.y.hr)
node hr_array_hi_hi_lo = cat(entries_barrier_10.io.y.hr, entries_barrier_9.io.y.hr)
node hr_array_hi_hi_hi = cat(entries_barrier_12.io.y.hr, entries_barrier_11.io.y.hr)
node hr_array_hi_hi = cat(hr_array_hi_hi_hi, hr_array_hi_hi_lo)
node hr_array_hi = cat(hr_array_hi_hi, hr_array_hi_lo)
node _hr_array_T = cat(hr_array_hi, hr_array_lo)
node hr_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx)
node hr_array_lo_lo_1 = cat(hr_array_lo_lo_hi_1, entries_barrier.io.y.hx)
node hr_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx)
node hr_array_lo_hi_1 = cat(hr_array_lo_hi_hi_1, entries_barrier_3.io.y.hx)
node hr_array_lo_1 = cat(hr_array_lo_hi_1, hr_array_lo_lo_1)
node hr_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx)
node hr_array_hi_lo_1 = cat(hr_array_hi_lo_hi_1, entries_barrier_6.io.y.hx)
node hr_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx)
node hr_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx)
node hr_array_hi_hi_1 = cat(hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1)
node hr_array_hi_1 = cat(hr_array_hi_hi_1, hr_array_hi_lo_1)
node _hr_array_T_1 = cat(hr_array_hi_1, hr_array_lo_1)
node _hr_array_T_2 = mux(io.ptw.status.mxr, _hr_array_T_1, UInt<1>(0h0))
node _hr_array_T_3 = or(_hr_array_T, _hr_array_T_2)
node _hr_array_T_4 = or(_hr_array_T_3, stage2_bypass)
node hr_array = cat(UInt<1>(0h1), _hr_array_T_4)
node hw_array_lo_lo_hi = cat(entries_barrier_2.io.y.hw, entries_barrier_1.io.y.hw)
node hw_array_lo_lo = cat(hw_array_lo_lo_hi, entries_barrier.io.y.hw)
node hw_array_lo_hi_hi = cat(entries_barrier_5.io.y.hw, entries_barrier_4.io.y.hw)
node hw_array_lo_hi = cat(hw_array_lo_hi_hi, entries_barrier_3.io.y.hw)
node hw_array_lo = cat(hw_array_lo_hi, hw_array_lo_lo)
node hw_array_hi_lo_hi = cat(entries_barrier_8.io.y.hw, entries_barrier_7.io.y.hw)
node hw_array_hi_lo = cat(hw_array_hi_lo_hi, entries_barrier_6.io.y.hw)
node hw_array_hi_hi_lo = cat(entries_barrier_10.io.y.hw, entries_barrier_9.io.y.hw)
node hw_array_hi_hi_hi = cat(entries_barrier_12.io.y.hw, entries_barrier_11.io.y.hw)
node hw_array_hi_hi = cat(hw_array_hi_hi_hi, hw_array_hi_hi_lo)
node hw_array_hi = cat(hw_array_hi_hi, hw_array_hi_lo)
node _hw_array_T = cat(hw_array_hi, hw_array_lo)
node _hw_array_T_1 = or(_hw_array_T, stage2_bypass)
node hw_array = cat(UInt<1>(0h1), _hw_array_T_1)
node hx_array_lo_lo_hi = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx)
node hx_array_lo_lo = cat(hx_array_lo_lo_hi, entries_barrier.io.y.hx)
node hx_array_lo_hi_hi = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx)
node hx_array_lo_hi = cat(hx_array_lo_hi_hi, entries_barrier_3.io.y.hx)
node hx_array_lo = cat(hx_array_lo_hi, hx_array_lo_lo)
node hx_array_hi_lo_hi = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx)
node hx_array_hi_lo = cat(hx_array_hi_lo_hi, entries_barrier_6.io.y.hx)
node hx_array_hi_hi_lo = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx)
node hx_array_hi_hi_hi = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx)
node hx_array_hi_hi = cat(hx_array_hi_hi_hi, hx_array_hi_hi_lo)
node hx_array_hi = cat(hx_array_hi_hi, hx_array_hi_lo)
node _hx_array_T = cat(hx_array_hi, hx_array_lo)
node _hx_array_T_1 = or(_hx_array_T, stage2_bypass)
node hx_array = cat(UInt<1>(0h1), _hx_array_T_1)
node _pr_array_T = mux(prot_r, UInt<2>(0h3), UInt<2>(0h0))
node pr_array_lo_lo_hi = cat(entries_barrier_2.io.y.pr, entries_barrier_1.io.y.pr)
node pr_array_lo_lo = cat(pr_array_lo_lo_hi, entries_barrier.io.y.pr)
node pr_array_lo_hi_hi = cat(entries_barrier_5.io.y.pr, entries_barrier_4.io.y.pr)
node pr_array_lo_hi = cat(pr_array_lo_hi_hi, entries_barrier_3.io.y.pr)
node pr_array_lo = cat(pr_array_lo_hi, pr_array_lo_lo)
node pr_array_hi_lo_hi = cat(entries_barrier_8.io.y.pr, entries_barrier_7.io.y.pr)
node pr_array_hi_lo = cat(pr_array_hi_lo_hi, entries_barrier_6.io.y.pr)
node pr_array_hi_hi_hi = cat(entries_barrier_11.io.y.pr, entries_barrier_10.io.y.pr)
node pr_array_hi_hi = cat(pr_array_hi_hi_hi, entries_barrier_9.io.y.pr)
node pr_array_hi = cat(pr_array_hi_hi, pr_array_hi_lo)
node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo)
node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1)
node _pr_array_T_3 = or(ptw_ae_array, final_ae_array)
node _pr_array_T_4 = not(_pr_array_T_3)
node pr_array = and(_pr_array_T_2, _pr_array_T_4)
node _pw_array_T = mux(prot_w, UInt<2>(0h3), UInt<2>(0h0))
node pw_array_lo_lo_hi = cat(entries_barrier_2.io.y.pw, entries_barrier_1.io.y.pw)
node pw_array_lo_lo = cat(pw_array_lo_lo_hi, entries_barrier.io.y.pw)
node pw_array_lo_hi_hi = cat(entries_barrier_5.io.y.pw, entries_barrier_4.io.y.pw)
node pw_array_lo_hi = cat(pw_array_lo_hi_hi, entries_barrier_3.io.y.pw)
node pw_array_lo = cat(pw_array_lo_hi, pw_array_lo_lo)
node pw_array_hi_lo_hi = cat(entries_barrier_8.io.y.pw, entries_barrier_7.io.y.pw)
node pw_array_hi_lo = cat(pw_array_hi_lo_hi, entries_barrier_6.io.y.pw)
node pw_array_hi_hi_hi = cat(entries_barrier_11.io.y.pw, entries_barrier_10.io.y.pw)
node pw_array_hi_hi = cat(pw_array_hi_hi_hi, entries_barrier_9.io.y.pw)
node pw_array_hi = cat(pw_array_hi_hi, pw_array_hi_lo)
node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo)
node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1)
node _pw_array_T_3 = or(ptw_ae_array, final_ae_array)
node _pw_array_T_4 = not(_pw_array_T_3)
node pw_array = and(_pw_array_T_2, _pw_array_T_4)
node _px_array_T = mux(prot_x, UInt<2>(0h3), UInt<2>(0h0))
node px_array_lo_lo_hi = cat(entries_barrier_2.io.y.px, entries_barrier_1.io.y.px)
node px_array_lo_lo = cat(px_array_lo_lo_hi, entries_barrier.io.y.px)
node px_array_lo_hi_hi = cat(entries_barrier_5.io.y.px, entries_barrier_4.io.y.px)
node px_array_lo_hi = cat(px_array_lo_hi_hi, entries_barrier_3.io.y.px)
node px_array_lo = cat(px_array_lo_hi, px_array_lo_lo)
node px_array_hi_lo_hi = cat(entries_barrier_8.io.y.px, entries_barrier_7.io.y.px)
node px_array_hi_lo = cat(px_array_hi_lo_hi, entries_barrier_6.io.y.px)
node px_array_hi_hi_hi = cat(entries_barrier_11.io.y.px, entries_barrier_10.io.y.px)
node px_array_hi_hi = cat(px_array_hi_hi_hi, entries_barrier_9.io.y.px)
node px_array_hi = cat(px_array_hi_hi, px_array_hi_lo)
node _px_array_T_1 = cat(px_array_hi, px_array_lo)
node _px_array_T_2 = cat(_px_array_T, _px_array_T_1)
node _px_array_T_3 = or(ptw_ae_array, final_ae_array)
node _px_array_T_4 = not(_px_array_T_3)
node px_array = and(_px_array_T_2, _px_array_T_4)
node _eff_array_T = mux(pma.io.resp.eff, UInt<2>(0h3), UInt<2>(0h0))
node eff_array_lo_lo_hi = cat(entries_barrier_2.io.y.eff, entries_barrier_1.io.y.eff)
node eff_array_lo_lo = cat(eff_array_lo_lo_hi, entries_barrier.io.y.eff)
node eff_array_lo_hi_hi = cat(entries_barrier_5.io.y.eff, entries_barrier_4.io.y.eff)
node eff_array_lo_hi = cat(eff_array_lo_hi_hi, entries_barrier_3.io.y.eff)
node eff_array_lo = cat(eff_array_lo_hi, eff_array_lo_lo)
node eff_array_hi_lo_hi = cat(entries_barrier_8.io.y.eff, entries_barrier_7.io.y.eff)
node eff_array_hi_lo = cat(eff_array_hi_lo_hi, entries_barrier_6.io.y.eff)
node eff_array_hi_hi_hi = cat(entries_barrier_11.io.y.eff, entries_barrier_10.io.y.eff)
node eff_array_hi_hi = cat(eff_array_hi_hi_hi, entries_barrier_9.io.y.eff)
node eff_array_hi = cat(eff_array_hi_hi, eff_array_hi_lo)
node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo)
node eff_array = cat(_eff_array_T, _eff_array_T_1)
node _c_array_T = mux(cacheable, UInt<2>(0h3), UInt<2>(0h0))
node c_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c)
node c_array_lo_lo = cat(c_array_lo_lo_hi, entries_barrier.io.y.c)
node c_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c)
node c_array_lo_hi = cat(c_array_lo_hi_hi, entries_barrier_3.io.y.c)
node c_array_lo = cat(c_array_lo_hi, c_array_lo_lo)
node c_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c)
node c_array_hi_lo = cat(c_array_hi_lo_hi, entries_barrier_6.io.y.c)
node c_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c)
node c_array_hi_hi = cat(c_array_hi_hi_hi, entries_barrier_9.io.y.c)
node c_array_hi = cat(c_array_hi_hi, c_array_hi_lo)
node _c_array_T_1 = cat(c_array_hi, c_array_lo)
node c_array = cat(_c_array_T, _c_array_T_1)
node _ppp_array_T = mux(pma.io.resp.pp, UInt<2>(0h3), UInt<2>(0h0))
node ppp_array_lo_lo_hi = cat(entries_barrier_2.io.y.ppp, entries_barrier_1.io.y.ppp)
node ppp_array_lo_lo = cat(ppp_array_lo_lo_hi, entries_barrier.io.y.ppp)
node ppp_array_lo_hi_hi = cat(entries_barrier_5.io.y.ppp, entries_barrier_4.io.y.ppp)
node ppp_array_lo_hi = cat(ppp_array_lo_hi_hi, entries_barrier_3.io.y.ppp)
node ppp_array_lo = cat(ppp_array_lo_hi, ppp_array_lo_lo)
node ppp_array_hi_lo_hi = cat(entries_barrier_8.io.y.ppp, entries_barrier_7.io.y.ppp)
node ppp_array_hi_lo = cat(ppp_array_hi_lo_hi, entries_barrier_6.io.y.ppp)
node ppp_array_hi_hi_hi = cat(entries_barrier_11.io.y.ppp, entries_barrier_10.io.y.ppp)
node ppp_array_hi_hi = cat(ppp_array_hi_hi_hi, entries_barrier_9.io.y.ppp)
node ppp_array_hi = cat(ppp_array_hi_hi, ppp_array_hi_lo)
node _ppp_array_T_1 = cat(ppp_array_hi, ppp_array_lo)
node ppp_array = cat(_ppp_array_T, _ppp_array_T_1)
node _paa_array_T = mux(pma.io.resp.aa, UInt<2>(0h3), UInt<2>(0h0))
node paa_array_lo_lo_hi = cat(entries_barrier_2.io.y.paa, entries_barrier_1.io.y.paa)
node paa_array_lo_lo = cat(paa_array_lo_lo_hi, entries_barrier.io.y.paa)
node paa_array_lo_hi_hi = cat(entries_barrier_5.io.y.paa, entries_barrier_4.io.y.paa)
node paa_array_lo_hi = cat(paa_array_lo_hi_hi, entries_barrier_3.io.y.paa)
node paa_array_lo = cat(paa_array_lo_hi, paa_array_lo_lo)
node paa_array_hi_lo_hi = cat(entries_barrier_8.io.y.paa, entries_barrier_7.io.y.paa)
node paa_array_hi_lo = cat(paa_array_hi_lo_hi, entries_barrier_6.io.y.paa)
node paa_array_hi_hi_hi = cat(entries_barrier_11.io.y.paa, entries_barrier_10.io.y.paa)
node paa_array_hi_hi = cat(paa_array_hi_hi_hi, entries_barrier_9.io.y.paa)
node paa_array_hi = cat(paa_array_hi_hi, paa_array_hi_lo)
node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo)
node paa_array = cat(_paa_array_T, _paa_array_T_1)
node _pal_array_T = mux(pma.io.resp.al, UInt<2>(0h3), UInt<2>(0h0))
node pal_array_lo_lo_hi = cat(entries_barrier_2.io.y.pal, entries_barrier_1.io.y.pal)
node pal_array_lo_lo = cat(pal_array_lo_lo_hi, entries_barrier.io.y.pal)
node pal_array_lo_hi_hi = cat(entries_barrier_5.io.y.pal, entries_barrier_4.io.y.pal)
node pal_array_lo_hi = cat(pal_array_lo_hi_hi, entries_barrier_3.io.y.pal)
node pal_array_lo = cat(pal_array_lo_hi, pal_array_lo_lo)
node pal_array_hi_lo_hi = cat(entries_barrier_8.io.y.pal, entries_barrier_7.io.y.pal)
node pal_array_hi_lo = cat(pal_array_hi_lo_hi, entries_barrier_6.io.y.pal)
node pal_array_hi_hi_hi = cat(entries_barrier_11.io.y.pal, entries_barrier_10.io.y.pal)
node pal_array_hi_hi = cat(pal_array_hi_hi_hi, entries_barrier_9.io.y.pal)
node pal_array_hi = cat(pal_array_hi_hi, pal_array_hi_lo)
node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo)
node pal_array = cat(_pal_array_T, _pal_array_T_1)
node ppp_array_if_cached = or(ppp_array, c_array)
node paa_array_if_cached = or(paa_array, c_array)
node pal_array_if_cached = or(pal_array, c_array)
node _prefetchable_array_T = and(cacheable, homogeneous)
node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1)
node prefetchable_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c)
node prefetchable_array_lo_lo = cat(prefetchable_array_lo_lo_hi, entries_barrier.io.y.c)
node prefetchable_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c)
node prefetchable_array_lo_hi = cat(prefetchable_array_lo_hi_hi, entries_barrier_3.io.y.c)
node prefetchable_array_lo = cat(prefetchable_array_lo_hi, prefetchable_array_lo_lo)
node prefetchable_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c)
node prefetchable_array_hi_lo = cat(prefetchable_array_hi_lo_hi, entries_barrier_6.io.y.c)
node prefetchable_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c)
node prefetchable_array_hi_hi = cat(prefetchable_array_hi_hi_hi, entries_barrier_9.io.y.c)
node prefetchable_array_hi = cat(prefetchable_array_hi_hi, prefetchable_array_hi_lo)
node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo)
node prefetchable_array = cat(_prefetchable_array_T_1, _prefetchable_array_T_2)
node _misaligned_T = dshl(UInt<1>(0h1), io.req.bits.size)
node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1))
node _misaligned_T_2 = tail(_misaligned_T_1, 1)
node _misaligned_T_3 = and(io.req.bits.vaddr, _misaligned_T_2)
node misaligned = orr(_misaligned_T_3)
node _bad_va_T = and(vm_enabled, stage1_en)
node bad_va_maskedVAddr = and(io.req.bits.vaddr, UInt<40>(0hc000000000))
node _bad_va_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _bad_va_T_2 = eq(bad_va_maskedVAddr, UInt<1>(0h0))
node _bad_va_T_3 = eq(bad_va_maskedVAddr, UInt<40>(0hc000000000))
node _bad_va_T_4 = and(UInt<1>(0h1), _bad_va_T_3)
node _bad_va_T_5 = or(_bad_va_T_2, _bad_va_T_4)
node _bad_va_T_6 = eq(_bad_va_T_5, UInt<1>(0h0))
node _bad_va_T_7 = and(_bad_va_T_1, _bad_va_T_6)
node bad_va = and(_bad_va_T, _bad_va_T_7)
node _cmd_lrsc_T = eq(io.req.bits.cmd, UInt<3>(0h6))
node _cmd_lrsc_T_1 = eq(io.req.bits.cmd, UInt<3>(0h7))
node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1)
node cmd_lrsc = and(UInt<1>(0h1), _cmd_lrsc_T_2)
node _cmd_amo_logical_T = eq(io.req.bits.cmd, UInt<3>(0h4))
node _cmd_amo_logical_T_1 = eq(io.req.bits.cmd, UInt<4>(0h9))
node _cmd_amo_logical_T_2 = eq(io.req.bits.cmd, UInt<4>(0ha))
node _cmd_amo_logical_T_3 = eq(io.req.bits.cmd, UInt<4>(0hb))
node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1)
node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2)
node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3)
node cmd_amo_logical = and(UInt<1>(0h1), _cmd_amo_logical_T_6)
node _cmd_amo_arithmetic_T = eq(io.req.bits.cmd, UInt<4>(0h8))
node _cmd_amo_arithmetic_T_1 = eq(io.req.bits.cmd, UInt<4>(0hc))
node _cmd_amo_arithmetic_T_2 = eq(io.req.bits.cmd, UInt<4>(0hd))
node _cmd_amo_arithmetic_T_3 = eq(io.req.bits.cmd, UInt<4>(0he))
node _cmd_amo_arithmetic_T_4 = eq(io.req.bits.cmd, UInt<4>(0hf))
node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1)
node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2)
node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3)
node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4)
node cmd_amo_arithmetic = and(UInt<1>(0h1), _cmd_amo_arithmetic_T_8)
node cmd_put_partial = eq(io.req.bits.cmd, UInt<5>(0h11))
node _cmd_read_T = eq(io.req.bits.cmd, UInt<1>(0h0))
node _cmd_read_T_1 = eq(io.req.bits.cmd, UInt<5>(0h10))
node _cmd_read_T_2 = eq(io.req.bits.cmd, UInt<3>(0h6))
node _cmd_read_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7))
node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1)
node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2)
node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3)
node _cmd_read_T_7 = eq(io.req.bits.cmd, UInt<3>(0h4))
node _cmd_read_T_8 = eq(io.req.bits.cmd, UInt<4>(0h9))
node _cmd_read_T_9 = eq(io.req.bits.cmd, UInt<4>(0ha))
node _cmd_read_T_10 = eq(io.req.bits.cmd, UInt<4>(0hb))
node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8)
node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9)
node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10)
node _cmd_read_T_14 = eq(io.req.bits.cmd, UInt<4>(0h8))
node _cmd_read_T_15 = eq(io.req.bits.cmd, UInt<4>(0hc))
node _cmd_read_T_16 = eq(io.req.bits.cmd, UInt<4>(0hd))
node _cmd_read_T_17 = eq(io.req.bits.cmd, UInt<4>(0he))
node _cmd_read_T_18 = eq(io.req.bits.cmd, UInt<4>(0hf))
node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15)
node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16)
node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17)
node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18)
node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22)
node cmd_read = or(_cmd_read_T_6, _cmd_read_T_23)
node _cmd_readx_T = eq(io.req.bits.cmd, UInt<5>(0h10))
node cmd_readx = and(UInt<1>(0h0), _cmd_readx_T)
node _cmd_write_T = eq(io.req.bits.cmd, UInt<1>(0h1))
node _cmd_write_T_1 = eq(io.req.bits.cmd, UInt<5>(0h11))
node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1)
node _cmd_write_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7))
node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3)
node _cmd_write_T_5 = eq(io.req.bits.cmd, UInt<3>(0h4))
node _cmd_write_T_6 = eq(io.req.bits.cmd, UInt<4>(0h9))
node _cmd_write_T_7 = eq(io.req.bits.cmd, UInt<4>(0ha))
node _cmd_write_T_8 = eq(io.req.bits.cmd, UInt<4>(0hb))
node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6)
node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7)
node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8)
node _cmd_write_T_12 = eq(io.req.bits.cmd, UInt<4>(0h8))
node _cmd_write_T_13 = eq(io.req.bits.cmd, UInt<4>(0hc))
node _cmd_write_T_14 = eq(io.req.bits.cmd, UInt<4>(0hd))
node _cmd_write_T_15 = eq(io.req.bits.cmd, UInt<4>(0he))
node _cmd_write_T_16 = eq(io.req.bits.cmd, UInt<4>(0hf))
node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13)
node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14)
node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15)
node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16)
node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20)
node cmd_write = or(_cmd_write_T_4, _cmd_write_T_21)
node _cmd_write_perms_T = eq(io.req.bits.cmd, UInt<3>(0h5))
node _cmd_write_perms_T_1 = eq(io.req.bits.cmd, UInt<5>(0h17))
node _cmd_write_perms_T_2 = or(_cmd_write_perms_T, _cmd_write_perms_T_1)
node cmd_write_perms = or(cmd_write, _cmd_write_perms_T_2)
node lrscAllowed = mux(UInt<1>(0h0), UInt<1>(0h0), c_array)
node _ae_array_T = mux(misaligned, eff_array, UInt<1>(0h0))
node _ae_array_T_1 = not(lrscAllowed)
node _ae_array_T_2 = mux(cmd_lrsc, _ae_array_T_1, UInt<1>(0h0))
node ae_array = or(_ae_array_T, _ae_array_T_2)
node _ae_ld_array_T = not(pr_array)
node _ae_ld_array_T_1 = or(ae_array, _ae_ld_array_T)
node ae_ld_array = mux(cmd_read, _ae_ld_array_T_1, UInt<1>(0h0))
node _ae_st_array_T = not(pw_array)
node _ae_st_array_T_1 = or(ae_array, _ae_st_array_T)
node _ae_st_array_T_2 = mux(cmd_write_perms, _ae_st_array_T_1, UInt<1>(0h0))
node _ae_st_array_T_3 = not(ppp_array_if_cached)
node _ae_st_array_T_4 = mux(cmd_put_partial, _ae_st_array_T_3, UInt<1>(0h0))
node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4)
node _ae_st_array_T_6 = not(pal_array_if_cached)
node _ae_st_array_T_7 = mux(cmd_amo_logical, _ae_st_array_T_6, UInt<1>(0h0))
node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7)
node _ae_st_array_T_9 = not(paa_array_if_cached)
node _ae_st_array_T_10 = mux(cmd_amo_arithmetic, _ae_st_array_T_9, UInt<1>(0h0))
node ae_st_array = or(_ae_st_array_T_8, _ae_st_array_T_10)
node _must_alloc_array_T = not(ppp_array)
node _must_alloc_array_T_1 = mux(cmd_put_partial, _must_alloc_array_T, UInt<1>(0h0))
node _must_alloc_array_T_2 = not(pal_array)
node _must_alloc_array_T_3 = mux(cmd_amo_logical, _must_alloc_array_T_2, UInt<1>(0h0))
node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3)
node _must_alloc_array_T_5 = not(paa_array)
node _must_alloc_array_T_6 = mux(cmd_amo_arithmetic, _must_alloc_array_T_5, UInt<1>(0h0))
node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6)
node _must_alloc_array_T_8 = not(UInt<14>(0h0))
node _must_alloc_array_T_9 = mux(cmd_lrsc, _must_alloc_array_T_8, UInt<1>(0h0))
node must_alloc_array = or(_must_alloc_array_T_7, _must_alloc_array_T_9)
node _pf_ld_array_T = mux(cmd_readx, x_array, r_array)
node _pf_ld_array_T_1 = not(_pf_ld_array_T)
node _pf_ld_array_T_2 = not(ptw_ae_array)
node _pf_ld_array_T_3 = and(_pf_ld_array_T_1, _pf_ld_array_T_2)
node _pf_ld_array_T_4 = or(_pf_ld_array_T_3, ptw_pf_array)
node _pf_ld_array_T_5 = not(ptw_gf_array)
node _pf_ld_array_T_6 = and(_pf_ld_array_T_4, _pf_ld_array_T_5)
node pf_ld_array = mux(cmd_read, _pf_ld_array_T_6, UInt<1>(0h0))
node _pf_st_array_T = not(w_array)
node _pf_st_array_T_1 = not(ptw_ae_array)
node _pf_st_array_T_2 = and(_pf_st_array_T, _pf_st_array_T_1)
node _pf_st_array_T_3 = or(_pf_st_array_T_2, ptw_pf_array)
node _pf_st_array_T_4 = not(ptw_gf_array)
node _pf_st_array_T_5 = and(_pf_st_array_T_3, _pf_st_array_T_4)
node pf_st_array = mux(cmd_write_perms, _pf_st_array_T_5, UInt<1>(0h0))
node _pf_inst_array_T = not(x_array)
node _pf_inst_array_T_1 = not(ptw_ae_array)
node _pf_inst_array_T_2 = and(_pf_inst_array_T, _pf_inst_array_T_1)
node _pf_inst_array_T_3 = or(_pf_inst_array_T_2, ptw_pf_array)
node _pf_inst_array_T_4 = not(ptw_gf_array)
node pf_inst_array = and(_pf_inst_array_T_3, _pf_inst_array_T_4)
node _gf_ld_array_T = and(priv_v, cmd_read)
node _gf_ld_array_T_1 = mux(cmd_readx, hx_array, hr_array)
node _gf_ld_array_T_2 = not(_gf_ld_array_T_1)
node _gf_ld_array_T_3 = or(_gf_ld_array_T_2, ptw_gf_array)
node _gf_ld_array_T_4 = not(ptw_ae_array)
node _gf_ld_array_T_5 = and(_gf_ld_array_T_3, _gf_ld_array_T_4)
node gf_ld_array = mux(_gf_ld_array_T, _gf_ld_array_T_5, UInt<1>(0h0))
node _gf_st_array_T = and(priv_v, cmd_write_perms)
node _gf_st_array_T_1 = not(hw_array)
node _gf_st_array_T_2 = or(_gf_st_array_T_1, ptw_gf_array)
node _gf_st_array_T_3 = not(ptw_ae_array)
node _gf_st_array_T_4 = and(_gf_st_array_T_2, _gf_st_array_T_3)
node gf_st_array = mux(_gf_st_array_T, _gf_st_array_T_4, UInt<1>(0h0))
node _gf_inst_array_T = not(hx_array)
node _gf_inst_array_T_1 = or(_gf_inst_array_T, ptw_gf_array)
node _gf_inst_array_T_2 = not(ptw_ae_array)
node _gf_inst_array_T_3 = and(_gf_inst_array_T_1, _gf_inst_array_T_2)
node gf_inst_array = mux(priv_v, _gf_inst_array_T_3, UInt<1>(0h0))
node _gpa_hits_hit_mask_T = eq(r_gpa_vpn, vpn)
node _gpa_hits_hit_mask_T_1 = and(r_gpa_valid, _gpa_hits_hit_mask_T)
node _gpa_hits_hit_mask_T_2 = mux(_gpa_hits_hit_mask_T_1, UInt<12>(0hfff), UInt<12>(0h0))
node _gpa_hits_hit_mask_T_3 = eq(vstage1_en, UInt<1>(0h0))
node _gpa_hits_hit_mask_T_4 = mux(_gpa_hits_hit_mask_T_3, UInt<13>(0h1fff), UInt<13>(0h0))
node gpa_hits_hit_mask = or(_gpa_hits_hit_mask_T_2, _gpa_hits_hit_mask_T_4)
node _gpa_hits_T = bits(gf_inst_array, 12, 0)
node _gpa_hits_T_1 = not(_gpa_hits_T)
node gpa_hits = or(gpa_hits_hit_mask, _gpa_hits_T_1)
node tlb_hit_if_not_gpa_miss = orr(real_hits)
node _tlb_hit_T = and(real_hits, gpa_hits)
node tlb_hit = orr(_tlb_hit_T)
node _tlb_miss_T = eq(vsatp_mode_mismatch, UInt<1>(0h0))
node _tlb_miss_T_1 = and(vm_enabled, _tlb_miss_T)
node _tlb_miss_T_2 = eq(bad_va, UInt<1>(0h0))
node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2)
node _tlb_miss_T_4 = eq(tlb_hit, UInt<1>(0h0))
node tlb_miss = and(_tlb_miss_T_3, _tlb_miss_T_4)
regreset state_reg : UInt<7>, clock, reset, UInt<7>(0h0)
wire _state_vec_WIRE : UInt<7>[1]
connect _state_vec_WIRE[0], UInt<7>(0h0)
regreset state_vec : UInt<7>[1], clock, reset, _state_vec_WIRE
regreset state_reg_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _T_23 = and(io.req.valid, vm_enabled)
when _T_23 :
node _T_24 = or(sector_hits_0, sector_hits_1)
node _T_25 = or(_T_24, sector_hits_2)
node _T_26 = or(_T_25, sector_hits_3)
node _T_27 = or(_T_26, sector_hits_4)
node _T_28 = or(_T_27, sector_hits_5)
node _T_29 = or(_T_28, sector_hits_6)
node _T_30 = or(_T_29, sector_hits_7)
when _T_30 :
node lo_lo = cat(sector_hits_1, sector_hits_0)
node lo_hi = cat(sector_hits_3, sector_hits_2)
node lo = cat(lo_hi, lo_lo)
node hi_lo = cat(sector_hits_5, sector_hits_4)
node hi_hi = cat(sector_hits_7, sector_hits_6)
node hi = cat(hi_hi, hi_lo)
node _T_31 = cat(hi, lo)
node hi_1 = bits(_T_31, 7, 4)
node lo_1 = bits(_T_31, 3, 0)
node _T_32 = orr(hi_1)
node _T_33 = or(hi_1, lo_1)
node hi_2 = bits(_T_33, 3, 2)
node lo_2 = bits(_T_33, 1, 0)
node _T_34 = orr(hi_2)
node _T_35 = or(hi_2, lo_2)
node _T_36 = bits(_T_35, 1, 1)
node _T_37 = cat(_T_34, _T_36)
node _T_38 = cat(_T_32, _T_37)
node state_vec_0_touch_way_sized = bits(_T_38, 2, 0)
node _state_vec_0_set_left_older_T = bits(state_vec_0_touch_way_sized, 2, 2)
node state_vec_0_set_left_older = eq(_state_vec_0_set_left_older_T, UInt<1>(0h0))
node state_vec_0_left_subtree_state = bits(state_vec[0], 5, 3)
node state_vec_0_right_subtree_state = bits(state_vec[0], 2, 0)
node _state_vec_0_T = bits(state_vec_0_touch_way_sized, 1, 0)
node _state_vec_0_set_left_older_T_1 = bits(_state_vec_0_T, 1, 1)
node state_vec_0_set_left_older_1 = eq(_state_vec_0_set_left_older_T_1, UInt<1>(0h0))
node state_vec_0_left_subtree_state_1 = bits(state_vec_0_left_subtree_state, 1, 1)
node state_vec_0_right_subtree_state_1 = bits(state_vec_0_left_subtree_state, 0, 0)
node _state_vec_0_T_1 = bits(_state_vec_0_T, 0, 0)
node _state_vec_0_T_2 = bits(_state_vec_0_T_1, 0, 0)
node _state_vec_0_T_3 = eq(_state_vec_0_T_2, UInt<1>(0h0))
node _state_vec_0_T_4 = mux(state_vec_0_set_left_older_1, state_vec_0_left_subtree_state_1, _state_vec_0_T_3)
node _state_vec_0_T_5 = bits(_state_vec_0_T, 0, 0)
node _state_vec_0_T_6 = bits(_state_vec_0_T_5, 0, 0)
node _state_vec_0_T_7 = eq(_state_vec_0_T_6, UInt<1>(0h0))
node _state_vec_0_T_8 = mux(state_vec_0_set_left_older_1, _state_vec_0_T_7, state_vec_0_right_subtree_state_1)
node state_vec_0_hi = cat(state_vec_0_set_left_older_1, _state_vec_0_T_4)
node _state_vec_0_T_9 = cat(state_vec_0_hi, _state_vec_0_T_8)
node _state_vec_0_T_10 = mux(state_vec_0_set_left_older, state_vec_0_left_subtree_state, _state_vec_0_T_9)
node _state_vec_0_T_11 = bits(state_vec_0_touch_way_sized, 1, 0)
node _state_vec_0_set_left_older_T_2 = bits(_state_vec_0_T_11, 1, 1)
node state_vec_0_set_left_older_2 = eq(_state_vec_0_set_left_older_T_2, UInt<1>(0h0))
node state_vec_0_left_subtree_state_2 = bits(state_vec_0_right_subtree_state, 1, 1)
node state_vec_0_right_subtree_state_2 = bits(state_vec_0_right_subtree_state, 0, 0)
node _state_vec_0_T_12 = bits(_state_vec_0_T_11, 0, 0)
node _state_vec_0_T_13 = bits(_state_vec_0_T_12, 0, 0)
node _state_vec_0_T_14 = eq(_state_vec_0_T_13, UInt<1>(0h0))
node _state_vec_0_T_15 = mux(state_vec_0_set_left_older_2, state_vec_0_left_subtree_state_2, _state_vec_0_T_14)
node _state_vec_0_T_16 = bits(_state_vec_0_T_11, 0, 0)
node _state_vec_0_T_17 = bits(_state_vec_0_T_16, 0, 0)
node _state_vec_0_T_18 = eq(_state_vec_0_T_17, UInt<1>(0h0))
node _state_vec_0_T_19 = mux(state_vec_0_set_left_older_2, _state_vec_0_T_18, state_vec_0_right_subtree_state_2)
node state_vec_0_hi_1 = cat(state_vec_0_set_left_older_2, _state_vec_0_T_15)
node _state_vec_0_T_20 = cat(state_vec_0_hi_1, _state_vec_0_T_19)
node _state_vec_0_T_21 = mux(state_vec_0_set_left_older, _state_vec_0_T_20, state_vec_0_right_subtree_state)
node state_vec_0_hi_2 = cat(state_vec_0_set_left_older, _state_vec_0_T_10)
node _state_vec_0_T_22 = cat(state_vec_0_hi_2, _state_vec_0_T_21)
connect state_vec[0], _state_vec_0_T_22
node _T_39 = or(superpage_hits_0, superpage_hits_1)
node _T_40 = or(_T_39, superpage_hits_2)
node _T_41 = or(_T_40, superpage_hits_3)
when _T_41 :
node lo_3 = cat(superpage_hits_1, superpage_hits_0)
node hi_3 = cat(superpage_hits_3, superpage_hits_2)
node _T_42 = cat(hi_3, lo_3)
node hi_4 = bits(_T_42, 3, 2)
node lo_4 = bits(_T_42, 1, 0)
node _T_43 = orr(hi_4)
node _T_44 = or(hi_4, lo_4)
node _T_45 = bits(_T_44, 1, 1)
node _T_46 = cat(_T_43, _T_45)
node state_reg_touch_way_sized = bits(_T_46, 1, 0)
node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 1, 1)
node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0))
node state_reg_left_subtree_state = bits(state_reg_1, 1, 1)
node state_reg_right_subtree_state = bits(state_reg_1, 0, 0)
node _state_reg_T = bits(state_reg_touch_way_sized, 0, 0)
node _state_reg_T_1 = bits(_state_reg_T, 0, 0)
node _state_reg_T_2 = eq(_state_reg_T_1, UInt<1>(0h0))
node _state_reg_T_3 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_2)
node _state_reg_T_4 = bits(state_reg_touch_way_sized, 0, 0)
node _state_reg_T_5 = bits(_state_reg_T_4, 0, 0)
node _state_reg_T_6 = eq(_state_reg_T_5, UInt<1>(0h0))
node _state_reg_T_7 = mux(state_reg_set_left_older, _state_reg_T_6, state_reg_right_subtree_state)
node state_reg_hi = cat(state_reg_set_left_older, _state_reg_T_3)
node _state_reg_T_8 = cat(state_reg_hi, _state_reg_T_7)
connect state_reg_1, _state_reg_T_8
node _multipleHits_T = bits(real_hits, 5, 0)
node _multipleHits_T_1 = bits(_multipleHits_T, 2, 0)
node _multipleHits_T_2 = bits(_multipleHits_T_1, 0, 0)
node multipleHits_leftOne = bits(_multipleHits_T_2, 0, 0)
node _multipleHits_T_3 = bits(_multipleHits_T_1, 2, 1)
node _multipleHits_T_4 = bits(_multipleHits_T_3, 0, 0)
node multipleHits_leftOne_1 = bits(_multipleHits_T_4, 0, 0)
node _multipleHits_T_5 = bits(_multipleHits_T_3, 1, 1)
node multipleHits_rightOne = bits(_multipleHits_T_5, 0, 0)
node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne)
node _multipleHits_T_6 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_7 = and(multipleHits_leftOne_1, multipleHits_rightOne)
node multipleHits_rightTwo = or(_multipleHits_T_6, _multipleHits_T_7)
node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1)
node _multipleHits_T_8 = or(UInt<1>(0h0), multipleHits_rightTwo)
node _multipleHits_T_9 = and(multipleHits_leftOne, multipleHits_rightOne_1)
node multipleHits_leftTwo = or(_multipleHits_T_8, _multipleHits_T_9)
node _multipleHits_T_10 = bits(_multipleHits_T, 5, 3)
node _multipleHits_T_11 = bits(_multipleHits_T_10, 0, 0)
node multipleHits_leftOne_3 = bits(_multipleHits_T_11, 0, 0)
node _multipleHits_T_12 = bits(_multipleHits_T_10, 2, 1)
node _multipleHits_T_13 = bits(_multipleHits_T_12, 0, 0)
node multipleHits_leftOne_4 = bits(_multipleHits_T_13, 0, 0)
node _multipleHits_T_14 = bits(_multipleHits_T_12, 1, 1)
node multipleHits_rightOne_2 = bits(_multipleHits_T_14, 0, 0)
node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2)
node _multipleHits_T_15 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_16 = and(multipleHits_leftOne_4, multipleHits_rightOne_2)
node multipleHits_rightTwo_1 = or(_multipleHits_T_15, _multipleHits_T_16)
node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3)
node _multipleHits_T_17 = or(UInt<1>(0h0), multipleHits_rightTwo_1)
node _multipleHits_T_18 = and(multipleHits_leftOne_3, multipleHits_rightOne_3)
node multipleHits_rightTwo_2 = or(_multipleHits_T_17, _multipleHits_T_18)
node multipleHits_leftOne_5 = or(multipleHits_leftOne_2, multipleHits_rightOne_4)
node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2)
node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4)
node multipleHits_leftTwo_1 = or(_multipleHits_T_19, _multipleHits_T_20)
node _multipleHits_T_21 = bits(real_hits, 12, 6)
node _multipleHits_T_22 = bits(_multipleHits_T_21, 2, 0)
node _multipleHits_T_23 = bits(_multipleHits_T_22, 0, 0)
node multipleHits_leftOne_6 = bits(_multipleHits_T_23, 0, 0)
node _multipleHits_T_24 = bits(_multipleHits_T_22, 2, 1)
node _multipleHits_T_25 = bits(_multipleHits_T_24, 0, 0)
node multipleHits_leftOne_7 = bits(_multipleHits_T_25, 0, 0)
node _multipleHits_T_26 = bits(_multipleHits_T_24, 1, 1)
node multipleHits_rightOne_5 = bits(_multipleHits_T_26, 0, 0)
node multipleHits_rightOne_6 = or(multipleHits_leftOne_7, multipleHits_rightOne_5)
node _multipleHits_T_27 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_28 = and(multipleHits_leftOne_7, multipleHits_rightOne_5)
node multipleHits_rightTwo_3 = or(_multipleHits_T_27, _multipleHits_T_28)
node multipleHits_leftOne_8 = or(multipleHits_leftOne_6, multipleHits_rightOne_6)
node _multipleHits_T_29 = or(UInt<1>(0h0), multipleHits_rightTwo_3)
node _multipleHits_T_30 = and(multipleHits_leftOne_6, multipleHits_rightOne_6)
node multipleHits_leftTwo_2 = or(_multipleHits_T_29, _multipleHits_T_30)
node _multipleHits_T_31 = bits(_multipleHits_T_21, 6, 3)
node _multipleHits_T_32 = bits(_multipleHits_T_31, 1, 0)
node _multipleHits_T_33 = bits(_multipleHits_T_32, 0, 0)
node multipleHits_leftOne_9 = bits(_multipleHits_T_33, 0, 0)
node _multipleHits_T_34 = bits(_multipleHits_T_32, 1, 1)
node multipleHits_rightOne_7 = bits(_multipleHits_T_34, 0, 0)
node multipleHits_leftOne_10 = or(multipleHits_leftOne_9, multipleHits_rightOne_7)
node _multipleHits_T_35 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_36 = and(multipleHits_leftOne_9, multipleHits_rightOne_7)
node multipleHits_leftTwo_3 = or(_multipleHits_T_35, _multipleHits_T_36)
node _multipleHits_T_37 = bits(_multipleHits_T_31, 3, 2)
node _multipleHits_T_38 = bits(_multipleHits_T_37, 0, 0)
node multipleHits_leftOne_11 = bits(_multipleHits_T_38, 0, 0)
node _multipleHits_T_39 = bits(_multipleHits_T_37, 1, 1)
node multipleHits_rightOne_8 = bits(_multipleHits_T_39, 0, 0)
node multipleHits_rightOne_9 = or(multipleHits_leftOne_11, multipleHits_rightOne_8)
node _multipleHits_T_40 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_41 = and(multipleHits_leftOne_11, multipleHits_rightOne_8)
node multipleHits_rightTwo_4 = or(_multipleHits_T_40, _multipleHits_T_41)
node multipleHits_rightOne_10 = or(multipleHits_leftOne_10, multipleHits_rightOne_9)
node _multipleHits_T_42 = or(multipleHits_leftTwo_3, multipleHits_rightTwo_4)
node _multipleHits_T_43 = and(multipleHits_leftOne_10, multipleHits_rightOne_9)
node multipleHits_rightTwo_5 = or(_multipleHits_T_42, _multipleHits_T_43)
node multipleHits_rightOne_11 = or(multipleHits_leftOne_8, multipleHits_rightOne_10)
node _multipleHits_T_44 = or(multipleHits_leftTwo_2, multipleHits_rightTwo_5)
node _multipleHits_T_45 = and(multipleHits_leftOne_8, multipleHits_rightOne_10)
node multipleHits_rightTwo_6 = or(_multipleHits_T_44, _multipleHits_T_45)
node _multipleHits_T_46 = or(multipleHits_leftOne_5, multipleHits_rightOne_11)
node _multipleHits_T_47 = or(multipleHits_leftTwo_1, multipleHits_rightTwo_6)
node _multipleHits_T_48 = and(multipleHits_leftOne_5, multipleHits_rightOne_11)
node multipleHits = or(_multipleHits_T_47, _multipleHits_T_48)
node _io_req_ready_T = eq(state, UInt<2>(0h0))
connect io.req.ready, _io_req_ready_T
node _io_resp_pf_ld_T = and(bad_va, cmd_read)
node _io_resp_pf_ld_T_1 = and(pf_ld_array, hits)
node _io_resp_pf_ld_T_2 = orr(_io_resp_pf_ld_T_1)
node _io_resp_pf_ld_T_3 = or(_io_resp_pf_ld_T, _io_resp_pf_ld_T_2)
connect io.resp.pf.ld, _io_resp_pf_ld_T_3
node _io_resp_pf_st_T = and(bad_va, cmd_write_perms)
node _io_resp_pf_st_T_1 = and(pf_st_array, hits)
node _io_resp_pf_st_T_2 = orr(_io_resp_pf_st_T_1)
node _io_resp_pf_st_T_3 = or(_io_resp_pf_st_T, _io_resp_pf_st_T_2)
connect io.resp.pf.st, _io_resp_pf_st_T_3
node _io_resp_pf_inst_T = and(pf_inst_array, hits)
node _io_resp_pf_inst_T_1 = orr(_io_resp_pf_inst_T)
node _io_resp_pf_inst_T_2 = or(bad_va, _io_resp_pf_inst_T_1)
connect io.resp.pf.inst, _io_resp_pf_inst_T_2
node _io_resp_gf_ld_T = and(UInt<1>(0h0), cmd_read)
node _io_resp_gf_ld_T_1 = and(gf_ld_array, hits)
node _io_resp_gf_ld_T_2 = orr(_io_resp_gf_ld_T_1)
node _io_resp_gf_ld_T_3 = or(_io_resp_gf_ld_T, _io_resp_gf_ld_T_2)
connect io.resp.gf.ld, _io_resp_gf_ld_T_3
node _io_resp_gf_st_T = and(UInt<1>(0h0), cmd_write_perms)
node _io_resp_gf_st_T_1 = and(gf_st_array, hits)
node _io_resp_gf_st_T_2 = orr(_io_resp_gf_st_T_1)
node _io_resp_gf_st_T_3 = or(_io_resp_gf_st_T, _io_resp_gf_st_T_2)
connect io.resp.gf.st, _io_resp_gf_st_T_3
node _io_resp_gf_inst_T = and(gf_inst_array, hits)
node _io_resp_gf_inst_T_1 = orr(_io_resp_gf_inst_T)
node _io_resp_gf_inst_T_2 = or(UInt<1>(0h0), _io_resp_gf_inst_T_1)
connect io.resp.gf.inst, _io_resp_gf_inst_T_2
node _io_resp_ae_ld_T = and(ae_ld_array, hits)
node _io_resp_ae_ld_T_1 = orr(_io_resp_ae_ld_T)
connect io.resp.ae.ld, _io_resp_ae_ld_T_1
node _io_resp_ae_st_T = and(ae_st_array, hits)
node _io_resp_ae_st_T_1 = orr(_io_resp_ae_st_T)
connect io.resp.ae.st, _io_resp_ae_st_T_1
node _io_resp_ae_inst_T = not(px_array)
node _io_resp_ae_inst_T_1 = and(_io_resp_ae_inst_T, hits)
node _io_resp_ae_inst_T_2 = orr(_io_resp_ae_inst_T_1)
connect io.resp.ae.inst, _io_resp_ae_inst_T_2
node _io_resp_ma_ld_T = and(misaligned, cmd_read)
connect io.resp.ma.ld, _io_resp_ma_ld_T
node _io_resp_ma_st_T = and(misaligned, cmd_write)
connect io.resp.ma.st, _io_resp_ma_st_T
connect io.resp.ma.inst, UInt<1>(0h0)
node _io_resp_cacheable_T = and(c_array, hits)
node _io_resp_cacheable_T_1 = orr(_io_resp_cacheable_T)
connect io.resp.cacheable, _io_resp_cacheable_T_1
node _io_resp_must_alloc_T = and(must_alloc_array, hits)
node _io_resp_must_alloc_T_1 = orr(_io_resp_must_alloc_T)
connect io.resp.must_alloc, _io_resp_must_alloc_T_1
node _io_resp_prefetchable_T = and(prefetchable_array, hits)
node _io_resp_prefetchable_T_1 = orr(_io_resp_prefetchable_T)
node _io_resp_prefetchable_T_2 = and(_io_resp_prefetchable_T_1, UInt<1>(0h1))
connect io.resp.prefetchable, _io_resp_prefetchable_T_2
node _io_resp_miss_T = or(do_refill, vsatp_mode_mismatch)
node _io_resp_miss_T_1 = or(_io_resp_miss_T, tlb_miss)
node _io_resp_miss_T_2 = or(_io_resp_miss_T_1, multipleHits)
connect io.resp.miss, _io_resp_miss_T_2
node _io_resp_paddr_T = bits(io.req.bits.vaddr, 11, 0)
node _io_resp_paddr_T_1 = cat(ppn, _io_resp_paddr_T)
connect io.resp.paddr, _io_resp_paddr_T_1
connect io.resp.size, io.req.bits.size
connect io.resp.cmd, io.req.bits.cmd
node _io_resp_gpa_is_pte_T = and(vstage1_en, r_gpa_is_pte)
connect io.resp.gpa_is_pte, _io_resp_gpa_is_pte_T
node _io_resp_gpa_page_T = eq(vstage1_en, UInt<1>(0h0))
node _io_resp_gpa_page_T_1 = cat(UInt<1>(0h0), vpn)
node _io_resp_gpa_page_T_2 = shr(r_gpa, 12)
node io_resp_gpa_page = mux(_io_resp_gpa_page_T, _io_resp_gpa_page_T_1, _io_resp_gpa_page_T_2)
node _io_resp_gpa_offset_T = bits(r_gpa, 11, 0)
node _io_resp_gpa_offset_T_1 = bits(io.req.bits.vaddr, 11, 0)
node io_resp_gpa_offset = mux(io.resp.gpa_is_pte, _io_resp_gpa_offset_T, _io_resp_gpa_offset_T_1)
node _io_resp_gpa_T = cat(io_resp_gpa_page, io_resp_gpa_offset)
connect io.resp.gpa, _io_resp_gpa_T
node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1))
connect io.ptw.req.valid, _io_ptw_req_valid_T
node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0))
connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T
connect io.ptw.req.bits.bits.addr, r_refill_tag
connect io.ptw.req.bits.bits.vstage1, r_vstage1_en
connect io.ptw.req.bits.bits.stage2, r_stage2_en
connect io.ptw.req.bits.bits.need_gpa, r_need_gpa
node _T_47 = and(io.ptw.req.ready, io.ptw.req.valid)
node _T_48 = and(_T_47, io.ptw.req.bits.valid)
when _T_48 :
connect r_gpa_valid, UInt<1>(0h0)
connect r_gpa_vpn, r_refill_tag
node _T_49 = and(io.req.ready, io.req.valid)
node _T_50 = and(_T_49, tlb_miss)
when _T_50 :
connect state, UInt<2>(0h1)
connect r_refill_tag, vpn
connect r_need_gpa, tlb_hit_if_not_gpa_miss
connect r_vstage1_en, vstage1_en
connect r_stage2_en, stage2_en
node r_superpage_repl_addr_left_subtree_older = bits(state_reg_1, 2, 2)
node r_superpage_repl_addr_left_subtree_state = bits(state_reg_1, 1, 1)
node r_superpage_repl_addr_right_subtree_state = bits(state_reg_1, 0, 0)
node _r_superpage_repl_addr_T = bits(r_superpage_repl_addr_left_subtree_state, 0, 0)
node _r_superpage_repl_addr_T_1 = bits(r_superpage_repl_addr_right_subtree_state, 0, 0)
node _r_superpage_repl_addr_T_2 = mux(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T, _r_superpage_repl_addr_T_1)
node _r_superpage_repl_addr_T_3 = cat(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2)
node r_superpage_repl_addr_valids_lo = cat(superpage_entries[1].valid[0], superpage_entries[0].valid[0])
node r_superpage_repl_addr_valids_hi = cat(superpage_entries[3].valid[0], superpage_entries[2].valid[0])
node r_superpage_repl_addr_valids = cat(r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo)
node _r_superpage_repl_addr_T_4 = andr(r_superpage_repl_addr_valids)
node _r_superpage_repl_addr_T_5 = not(r_superpage_repl_addr_valids)
node _r_superpage_repl_addr_T_6 = bits(_r_superpage_repl_addr_T_5, 0, 0)
node _r_superpage_repl_addr_T_7 = bits(_r_superpage_repl_addr_T_5, 1, 1)
node _r_superpage_repl_addr_T_8 = bits(_r_superpage_repl_addr_T_5, 2, 2)
node _r_superpage_repl_addr_T_9 = bits(_r_superpage_repl_addr_T_5, 3, 3)
node _r_superpage_repl_addr_T_10 = mux(_r_superpage_repl_addr_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _r_superpage_repl_addr_T_11 = mux(_r_superpage_repl_addr_T_7, UInt<1>(0h1), _r_superpage_repl_addr_T_10)
node _r_superpage_repl_addr_T_12 = mux(_r_superpage_repl_addr_T_6, UInt<1>(0h0), _r_superpage_repl_addr_T_11)
node _r_superpage_repl_addr_T_13 = mux(_r_superpage_repl_addr_T_4, _r_superpage_repl_addr_T_3, _r_superpage_repl_addr_T_12)
connect r_superpage_repl_addr, _r_superpage_repl_addr_T_13
node r_sectored_repl_addr_left_subtree_older = bits(state_vec[0], 6, 6)
node r_sectored_repl_addr_left_subtree_state = bits(state_vec[0], 5, 3)
node r_sectored_repl_addr_right_subtree_state = bits(state_vec[0], 2, 0)
node r_sectored_repl_addr_left_subtree_older_1 = bits(r_sectored_repl_addr_left_subtree_state, 2, 2)
node r_sectored_repl_addr_left_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 1, 1)
node r_sectored_repl_addr_right_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 0, 0)
node _r_sectored_repl_addr_T = bits(r_sectored_repl_addr_left_subtree_state_1, 0, 0)
node _r_sectored_repl_addr_T_1 = bits(r_sectored_repl_addr_right_subtree_state_1, 0, 0)
node _r_sectored_repl_addr_T_2 = mux(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T, _r_sectored_repl_addr_T_1)
node _r_sectored_repl_addr_T_3 = cat(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2)
node r_sectored_repl_addr_left_subtree_older_2 = bits(r_sectored_repl_addr_right_subtree_state, 2, 2)
node r_sectored_repl_addr_left_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 1, 1)
node r_sectored_repl_addr_right_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 0, 0)
node _r_sectored_repl_addr_T_4 = bits(r_sectored_repl_addr_left_subtree_state_2, 0, 0)
node _r_sectored_repl_addr_T_5 = bits(r_sectored_repl_addr_right_subtree_state_2, 0, 0)
node _r_sectored_repl_addr_T_6 = mux(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_4, _r_sectored_repl_addr_T_5)
node _r_sectored_repl_addr_T_7 = cat(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6)
node _r_sectored_repl_addr_T_8 = mux(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_3, _r_sectored_repl_addr_T_7)
node _r_sectored_repl_addr_T_9 = cat(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8)
node _r_sectored_repl_addr_valids_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1])
node _r_sectored_repl_addr_valids_T_1 = or(_r_sectored_repl_addr_valids_T, sectored_entries[0][0].valid[2])
node _r_sectored_repl_addr_valids_T_2 = or(_r_sectored_repl_addr_valids_T_1, sectored_entries[0][0].valid[3])
node _r_sectored_repl_addr_valids_T_3 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1])
node _r_sectored_repl_addr_valids_T_4 = or(_r_sectored_repl_addr_valids_T_3, sectored_entries[0][1].valid[2])
node _r_sectored_repl_addr_valids_T_5 = or(_r_sectored_repl_addr_valids_T_4, sectored_entries[0][1].valid[3])
node _r_sectored_repl_addr_valids_T_6 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1])
node _r_sectored_repl_addr_valids_T_7 = or(_r_sectored_repl_addr_valids_T_6, sectored_entries[0][2].valid[2])
node _r_sectored_repl_addr_valids_T_8 = or(_r_sectored_repl_addr_valids_T_7, sectored_entries[0][2].valid[3])
node _r_sectored_repl_addr_valids_T_9 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1])
node _r_sectored_repl_addr_valids_T_10 = or(_r_sectored_repl_addr_valids_T_9, sectored_entries[0][3].valid[2])
node _r_sectored_repl_addr_valids_T_11 = or(_r_sectored_repl_addr_valids_T_10, sectored_entries[0][3].valid[3])
node _r_sectored_repl_addr_valids_T_12 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1])
node _r_sectored_repl_addr_valids_T_13 = or(_r_sectored_repl_addr_valids_T_12, sectored_entries[0][4].valid[2])
node _r_sectored_repl_addr_valids_T_14 = or(_r_sectored_repl_addr_valids_T_13, sectored_entries[0][4].valid[3])
node _r_sectored_repl_addr_valids_T_15 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1])
node _r_sectored_repl_addr_valids_T_16 = or(_r_sectored_repl_addr_valids_T_15, sectored_entries[0][5].valid[2])
node _r_sectored_repl_addr_valids_T_17 = or(_r_sectored_repl_addr_valids_T_16, sectored_entries[0][5].valid[3])
node _r_sectored_repl_addr_valids_T_18 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1])
node _r_sectored_repl_addr_valids_T_19 = or(_r_sectored_repl_addr_valids_T_18, sectored_entries[0][6].valid[2])
node _r_sectored_repl_addr_valids_T_20 = or(_r_sectored_repl_addr_valids_T_19, sectored_entries[0][6].valid[3])
node _r_sectored_repl_addr_valids_T_21 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1])
node _r_sectored_repl_addr_valids_T_22 = or(_r_sectored_repl_addr_valids_T_21, sectored_entries[0][7].valid[2])
node _r_sectored_repl_addr_valids_T_23 = or(_r_sectored_repl_addr_valids_T_22, sectored_entries[0][7].valid[3])
node r_sectored_repl_addr_valids_lo_lo = cat(_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2)
node r_sectored_repl_addr_valids_lo_hi = cat(_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8)
node r_sectored_repl_addr_valids_lo = cat(r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo)
node r_sectored_repl_addr_valids_hi_lo = cat(_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14)
node r_sectored_repl_addr_valids_hi_hi = cat(_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20)
node r_sectored_repl_addr_valids_hi = cat(r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo)
node r_sectored_repl_addr_valids = cat(r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo)
node _r_sectored_repl_addr_T_10 = andr(r_sectored_repl_addr_valids)
node _r_sectored_repl_addr_T_11 = not(r_sectored_repl_addr_valids)
node _r_sectored_repl_addr_T_12 = bits(_r_sectored_repl_addr_T_11, 0, 0)
node _r_sectored_repl_addr_T_13 = bits(_r_sectored_repl_addr_T_11, 1, 1)
node _r_sectored_repl_addr_T_14 = bits(_r_sectored_repl_addr_T_11, 2, 2)
node _r_sectored_repl_addr_T_15 = bits(_r_sectored_repl_addr_T_11, 3, 3)
node _r_sectored_repl_addr_T_16 = bits(_r_sectored_repl_addr_T_11, 4, 4)
node _r_sectored_repl_addr_T_17 = bits(_r_sectored_repl_addr_T_11, 5, 5)
node _r_sectored_repl_addr_T_18 = bits(_r_sectored_repl_addr_T_11, 6, 6)
node _r_sectored_repl_addr_T_19 = bits(_r_sectored_repl_addr_T_11, 7, 7)
node _r_sectored_repl_addr_T_20 = mux(_r_sectored_repl_addr_T_18, UInt<3>(0h6), UInt<3>(0h7))
node _r_sectored_repl_addr_T_21 = mux(_r_sectored_repl_addr_T_17, UInt<3>(0h5), _r_sectored_repl_addr_T_20)
node _r_sectored_repl_addr_T_22 = mux(_r_sectored_repl_addr_T_16, UInt<3>(0h4), _r_sectored_repl_addr_T_21)
node _r_sectored_repl_addr_T_23 = mux(_r_sectored_repl_addr_T_15, UInt<2>(0h3), _r_sectored_repl_addr_T_22)
node _r_sectored_repl_addr_T_24 = mux(_r_sectored_repl_addr_T_14, UInt<2>(0h2), _r_sectored_repl_addr_T_23)
node _r_sectored_repl_addr_T_25 = mux(_r_sectored_repl_addr_T_13, UInt<1>(0h1), _r_sectored_repl_addr_T_24)
node _r_sectored_repl_addr_T_26 = mux(_r_sectored_repl_addr_T_12, UInt<1>(0h0), _r_sectored_repl_addr_T_25)
node _r_sectored_repl_addr_T_27 = mux(_r_sectored_repl_addr_T_10, _r_sectored_repl_addr_T_9, _r_sectored_repl_addr_T_26)
connect r_sectored_repl_addr, _r_sectored_repl_addr_T_27
node _r_sectored_hit_valid_T = or(sector_hits_0, sector_hits_1)
node _r_sectored_hit_valid_T_1 = or(_r_sectored_hit_valid_T, sector_hits_2)
node _r_sectored_hit_valid_T_2 = or(_r_sectored_hit_valid_T_1, sector_hits_3)
node _r_sectored_hit_valid_T_3 = or(_r_sectored_hit_valid_T_2, sector_hits_4)
node _r_sectored_hit_valid_T_4 = or(_r_sectored_hit_valid_T_3, sector_hits_5)
node _r_sectored_hit_valid_T_5 = or(_r_sectored_hit_valid_T_4, sector_hits_6)
node _r_sectored_hit_valid_T_6 = or(_r_sectored_hit_valid_T_5, sector_hits_7)
connect r_sectored_hit.valid, _r_sectored_hit_valid_T_6
node r_sectored_hit_bits_lo_lo = cat(sector_hits_1, sector_hits_0)
node r_sectored_hit_bits_lo_hi = cat(sector_hits_3, sector_hits_2)
node r_sectored_hit_bits_lo = cat(r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo)
node r_sectored_hit_bits_hi_lo = cat(sector_hits_5, sector_hits_4)
node r_sectored_hit_bits_hi_hi = cat(sector_hits_7, sector_hits_6)
node r_sectored_hit_bits_hi = cat(r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo)
node _r_sectored_hit_bits_T = cat(r_sectored_hit_bits_hi, r_sectored_hit_bits_lo)
node r_sectored_hit_bits_hi_1 = bits(_r_sectored_hit_bits_T, 7, 4)
node r_sectored_hit_bits_lo_1 = bits(_r_sectored_hit_bits_T, 3, 0)
node _r_sectored_hit_bits_T_1 = orr(r_sectored_hit_bits_hi_1)
node _r_sectored_hit_bits_T_2 = or(r_sectored_hit_bits_hi_1, r_sectored_hit_bits_lo_1)
node r_sectored_hit_bits_hi_2 = bits(_r_sectored_hit_bits_T_2, 3, 2)
node r_sectored_hit_bits_lo_2 = bits(_r_sectored_hit_bits_T_2, 1, 0)
node _r_sectored_hit_bits_T_3 = orr(r_sectored_hit_bits_hi_2)
node _r_sectored_hit_bits_T_4 = or(r_sectored_hit_bits_hi_2, r_sectored_hit_bits_lo_2)
node _r_sectored_hit_bits_T_5 = bits(_r_sectored_hit_bits_T_4, 1, 1)
node _r_sectored_hit_bits_T_6 = cat(_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5)
node _r_sectored_hit_bits_T_7 = cat(_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6)
connect r_sectored_hit.bits, _r_sectored_hit_bits_T_7
node _r_superpage_hit_valid_T = or(superpage_hits_0, superpage_hits_1)
node _r_superpage_hit_valid_T_1 = or(_r_superpage_hit_valid_T, superpage_hits_2)
node _r_superpage_hit_valid_T_2 = or(_r_superpage_hit_valid_T_1, superpage_hits_3)
connect r_superpage_hit.valid, _r_superpage_hit_valid_T_2
node r_superpage_hit_bits_lo = cat(superpage_hits_1, superpage_hits_0)
node r_superpage_hit_bits_hi = cat(superpage_hits_3, superpage_hits_2)
node _r_superpage_hit_bits_T = cat(r_superpage_hit_bits_hi, r_superpage_hit_bits_lo)
node r_superpage_hit_bits_hi_1 = bits(_r_superpage_hit_bits_T, 3, 2)
node r_superpage_hit_bits_lo_1 = bits(_r_superpage_hit_bits_T, 1, 0)
node _r_superpage_hit_bits_T_1 = orr(r_superpage_hit_bits_hi_1)
node _r_superpage_hit_bits_T_2 = or(r_superpage_hit_bits_hi_1, r_superpage_hit_bits_lo_1)
node _r_superpage_hit_bits_T_3 = bits(_r_superpage_hit_bits_T_2, 1, 1)
node _r_superpage_hit_bits_T_4 = cat(_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3)
connect r_superpage_hit.bits, _r_superpage_hit_bits_T_4
node _T_51 = eq(state, UInt<2>(0h1))
when _T_51 :
when io.sfence.valid :
connect state, UInt<2>(0h0)
when io.ptw.req.ready :
node _state_T = mux(io.sfence.valid, UInt<2>(0h3), UInt<2>(0h2))
connect state, _state_T
when io.kill :
connect state, UInt<2>(0h0)
node _T_52 = eq(state, UInt<2>(0h2))
node _T_53 = and(_T_52, io.sfence.valid)
when _T_53 :
connect state, UInt<2>(0h3)
when io.ptw.resp.valid :
connect state, UInt<2>(0h0)
when io.sfence.valid :
node _T_54 = eq(io.sfence.bits.rs1, UInt<1>(0h0))
node _T_55 = shr(io.sfence.bits.addr, 12)
node _T_56 = eq(_T_55, vpn)
node _T_57 = or(_T_54, _T_56)
node _T_58 = asUInt(reset)
node _T_59 = eq(_T_58, UInt<1>(0h0))
when _T_59 :
node _T_60 = eq(_T_57, UInt<1>(0h0))
when _T_60 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at TLB.scala:719 assert(!io.sfence.bits.rs1 || (io.sfence.bits.addr >> pgIdxBits) === vpn)\n") : printf
assert(clock, _T_57, UInt<1>(0h1), "") : assert
node hv = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_61 = eq(hg, UInt<1>(0h0))
node _T_62 = and(_T_61, io.sfence.bits.rs1)
when _T_62 :
node _T_63 = xor(sectored_entries[0][0].tag_vpn, vpn)
node _T_64 = shr(_T_63, 2)
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = eq(sectored_entries[0][0].tag_v, hv)
node _T_67 = and(_T_65, _T_66)
when _T_67 :
wire _WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_1 : UInt<42>
connect _WIRE_1, sectored_entries[0][0].data[0]
node _T_68 = bits(_WIRE_1, 0, 0)
connect _WIRE.fragmented_superpage, _T_68
node _T_69 = bits(_WIRE_1, 1, 1)
connect _WIRE.c, _T_69
node _T_70 = bits(_WIRE_1, 2, 2)
connect _WIRE.eff, _T_70
node _T_71 = bits(_WIRE_1, 3, 3)
connect _WIRE.paa, _T_71
node _T_72 = bits(_WIRE_1, 4, 4)
connect _WIRE.pal, _T_72
node _T_73 = bits(_WIRE_1, 5, 5)
connect _WIRE.ppp, _T_73
node _T_74 = bits(_WIRE_1, 6, 6)
connect _WIRE.pr, _T_74
node _T_75 = bits(_WIRE_1, 7, 7)
connect _WIRE.px, _T_75
node _T_76 = bits(_WIRE_1, 8, 8)
connect _WIRE.pw, _T_76
node _T_77 = bits(_WIRE_1, 9, 9)
connect _WIRE.hr, _T_77
node _T_78 = bits(_WIRE_1, 10, 10)
connect _WIRE.hx, _T_78
node _T_79 = bits(_WIRE_1, 11, 11)
connect _WIRE.hw, _T_79
node _T_80 = bits(_WIRE_1, 12, 12)
connect _WIRE.sr, _T_80
node _T_81 = bits(_WIRE_1, 13, 13)
connect _WIRE.sx, _T_81
node _T_82 = bits(_WIRE_1, 14, 14)
connect _WIRE.sw, _T_82
node _T_83 = bits(_WIRE_1, 15, 15)
connect _WIRE.gf, _T_83
node _T_84 = bits(_WIRE_1, 16, 16)
connect _WIRE.pf, _T_84
node _T_85 = bits(_WIRE_1, 17, 17)
connect _WIRE.ae_stage2, _T_85
node _T_86 = bits(_WIRE_1, 18, 18)
connect _WIRE.ae_final, _T_86
node _T_87 = bits(_WIRE_1, 19, 19)
connect _WIRE.ae_ptw, _T_87
node _T_88 = bits(_WIRE_1, 20, 20)
connect _WIRE.g, _T_88
node _T_89 = bits(_WIRE_1, 21, 21)
connect _WIRE.u, _T_89
node _T_90 = bits(_WIRE_1, 41, 22)
connect _WIRE.ppn, _T_90
wire _WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_3 : UInt<42>
connect _WIRE_3, sectored_entries[0][0].data[1]
node _T_91 = bits(_WIRE_3, 0, 0)
connect _WIRE_2.fragmented_superpage, _T_91
node _T_92 = bits(_WIRE_3, 1, 1)
connect _WIRE_2.c, _T_92
node _T_93 = bits(_WIRE_3, 2, 2)
connect _WIRE_2.eff, _T_93
node _T_94 = bits(_WIRE_3, 3, 3)
connect _WIRE_2.paa, _T_94
node _T_95 = bits(_WIRE_3, 4, 4)
connect _WIRE_2.pal, _T_95
node _T_96 = bits(_WIRE_3, 5, 5)
connect _WIRE_2.ppp, _T_96
node _T_97 = bits(_WIRE_3, 6, 6)
connect _WIRE_2.pr, _T_97
node _T_98 = bits(_WIRE_3, 7, 7)
connect _WIRE_2.px, _T_98
node _T_99 = bits(_WIRE_3, 8, 8)
connect _WIRE_2.pw, _T_99
node _T_100 = bits(_WIRE_3, 9, 9)
connect _WIRE_2.hr, _T_100
node _T_101 = bits(_WIRE_3, 10, 10)
connect _WIRE_2.hx, _T_101
node _T_102 = bits(_WIRE_3, 11, 11)
connect _WIRE_2.hw, _T_102
node _T_103 = bits(_WIRE_3, 12, 12)
connect _WIRE_2.sr, _T_103
node _T_104 = bits(_WIRE_3, 13, 13)
connect _WIRE_2.sx, _T_104
node _T_105 = bits(_WIRE_3, 14, 14)
connect _WIRE_2.sw, _T_105
node _T_106 = bits(_WIRE_3, 15, 15)
connect _WIRE_2.gf, _T_106
node _T_107 = bits(_WIRE_3, 16, 16)
connect _WIRE_2.pf, _T_107
node _T_108 = bits(_WIRE_3, 17, 17)
connect _WIRE_2.ae_stage2, _T_108
node _T_109 = bits(_WIRE_3, 18, 18)
connect _WIRE_2.ae_final, _T_109
node _T_110 = bits(_WIRE_3, 19, 19)
connect _WIRE_2.ae_ptw, _T_110
node _T_111 = bits(_WIRE_3, 20, 20)
connect _WIRE_2.g, _T_111
node _T_112 = bits(_WIRE_3, 21, 21)
connect _WIRE_2.u, _T_112
node _T_113 = bits(_WIRE_3, 41, 22)
connect _WIRE_2.ppn, _T_113
wire _WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_5 : UInt<42>
connect _WIRE_5, sectored_entries[0][0].data[2]
node _T_114 = bits(_WIRE_5, 0, 0)
connect _WIRE_4.fragmented_superpage, _T_114
node _T_115 = bits(_WIRE_5, 1, 1)
connect _WIRE_4.c, _T_115
node _T_116 = bits(_WIRE_5, 2, 2)
connect _WIRE_4.eff, _T_116
node _T_117 = bits(_WIRE_5, 3, 3)
connect _WIRE_4.paa, _T_117
node _T_118 = bits(_WIRE_5, 4, 4)
connect _WIRE_4.pal, _T_118
node _T_119 = bits(_WIRE_5, 5, 5)
connect _WIRE_4.ppp, _T_119
node _T_120 = bits(_WIRE_5, 6, 6)
connect _WIRE_4.pr, _T_120
node _T_121 = bits(_WIRE_5, 7, 7)
connect _WIRE_4.px, _T_121
node _T_122 = bits(_WIRE_5, 8, 8)
connect _WIRE_4.pw, _T_122
node _T_123 = bits(_WIRE_5, 9, 9)
connect _WIRE_4.hr, _T_123
node _T_124 = bits(_WIRE_5, 10, 10)
connect _WIRE_4.hx, _T_124
node _T_125 = bits(_WIRE_5, 11, 11)
connect _WIRE_4.hw, _T_125
node _T_126 = bits(_WIRE_5, 12, 12)
connect _WIRE_4.sr, _T_126
node _T_127 = bits(_WIRE_5, 13, 13)
connect _WIRE_4.sx, _T_127
node _T_128 = bits(_WIRE_5, 14, 14)
connect _WIRE_4.sw, _T_128
node _T_129 = bits(_WIRE_5, 15, 15)
connect _WIRE_4.gf, _T_129
node _T_130 = bits(_WIRE_5, 16, 16)
connect _WIRE_4.pf, _T_130
node _T_131 = bits(_WIRE_5, 17, 17)
connect _WIRE_4.ae_stage2, _T_131
node _T_132 = bits(_WIRE_5, 18, 18)
connect _WIRE_4.ae_final, _T_132
node _T_133 = bits(_WIRE_5, 19, 19)
connect _WIRE_4.ae_ptw, _T_133
node _T_134 = bits(_WIRE_5, 20, 20)
connect _WIRE_4.g, _T_134
node _T_135 = bits(_WIRE_5, 21, 21)
connect _WIRE_4.u, _T_135
node _T_136 = bits(_WIRE_5, 41, 22)
connect _WIRE_4.ppn, _T_136
wire _WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_7 : UInt<42>
connect _WIRE_7, sectored_entries[0][0].data[3]
node _T_137 = bits(_WIRE_7, 0, 0)
connect _WIRE_6.fragmented_superpage, _T_137
node _T_138 = bits(_WIRE_7, 1, 1)
connect _WIRE_6.c, _T_138
node _T_139 = bits(_WIRE_7, 2, 2)
connect _WIRE_6.eff, _T_139
node _T_140 = bits(_WIRE_7, 3, 3)
connect _WIRE_6.paa, _T_140
node _T_141 = bits(_WIRE_7, 4, 4)
connect _WIRE_6.pal, _T_141
node _T_142 = bits(_WIRE_7, 5, 5)
connect _WIRE_6.ppp, _T_142
node _T_143 = bits(_WIRE_7, 6, 6)
connect _WIRE_6.pr, _T_143
node _T_144 = bits(_WIRE_7, 7, 7)
connect _WIRE_6.px, _T_144
node _T_145 = bits(_WIRE_7, 8, 8)
connect _WIRE_6.pw, _T_145
node _T_146 = bits(_WIRE_7, 9, 9)
connect _WIRE_6.hr, _T_146
node _T_147 = bits(_WIRE_7, 10, 10)
connect _WIRE_6.hx, _T_147
node _T_148 = bits(_WIRE_7, 11, 11)
connect _WIRE_6.hw, _T_148
node _T_149 = bits(_WIRE_7, 12, 12)
connect _WIRE_6.sr, _T_149
node _T_150 = bits(_WIRE_7, 13, 13)
connect _WIRE_6.sx, _T_150
node _T_151 = bits(_WIRE_7, 14, 14)
connect _WIRE_6.sw, _T_151
node _T_152 = bits(_WIRE_7, 15, 15)
connect _WIRE_6.gf, _T_152
node _T_153 = bits(_WIRE_7, 16, 16)
connect _WIRE_6.pf, _T_153
node _T_154 = bits(_WIRE_7, 17, 17)
connect _WIRE_6.ae_stage2, _T_154
node _T_155 = bits(_WIRE_7, 18, 18)
connect _WIRE_6.ae_final, _T_155
node _T_156 = bits(_WIRE_7, 19, 19)
connect _WIRE_6.ae_ptw, _T_156
node _T_157 = bits(_WIRE_7, 20, 20)
connect _WIRE_6.g, _T_157
node _T_158 = bits(_WIRE_7, 21, 21)
connect _WIRE_6.u, _T_158
node _T_159 = bits(_WIRE_7, 41, 22)
connect _WIRE_6.ppn, _T_159
node _T_160 = eq(sectored_entries[0][0].tag_v, hv)
node _T_161 = bits(vpn, 1, 0)
node _T_162 = eq(UInt<1>(0h0), _T_161)
node _T_163 = and(_T_160, _T_162)
when _T_163 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
node _T_164 = eq(sectored_entries[0][0].tag_v, hv)
node _T_165 = bits(vpn, 1, 0)
node _T_166 = eq(UInt<1>(0h1), _T_165)
node _T_167 = and(_T_164, _T_166)
when _T_167 :
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
node _T_168 = eq(sectored_entries[0][0].tag_v, hv)
node _T_169 = bits(vpn, 1, 0)
node _T_170 = eq(UInt<2>(0h2), _T_169)
node _T_171 = and(_T_168, _T_170)
when _T_171 :
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
node _T_172 = eq(sectored_entries[0][0].tag_v, hv)
node _T_173 = bits(vpn, 1, 0)
node _T_174 = eq(UInt<2>(0h3), _T_173)
node _T_175 = and(_T_172, _T_174)
when _T_175 :
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
node _T_176 = xor(sectored_entries[0][0].tag_vpn, vpn)
node _T_177 = shr(_T_176, 18)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
wire _WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_9 : UInt<42>
connect _WIRE_9, sectored_entries[0][0].data[0]
node _T_179 = bits(_WIRE_9, 0, 0)
connect _WIRE_8.fragmented_superpage, _T_179
node _T_180 = bits(_WIRE_9, 1, 1)
connect _WIRE_8.c, _T_180
node _T_181 = bits(_WIRE_9, 2, 2)
connect _WIRE_8.eff, _T_181
node _T_182 = bits(_WIRE_9, 3, 3)
connect _WIRE_8.paa, _T_182
node _T_183 = bits(_WIRE_9, 4, 4)
connect _WIRE_8.pal, _T_183
node _T_184 = bits(_WIRE_9, 5, 5)
connect _WIRE_8.ppp, _T_184
node _T_185 = bits(_WIRE_9, 6, 6)
connect _WIRE_8.pr, _T_185
node _T_186 = bits(_WIRE_9, 7, 7)
connect _WIRE_8.px, _T_186
node _T_187 = bits(_WIRE_9, 8, 8)
connect _WIRE_8.pw, _T_187
node _T_188 = bits(_WIRE_9, 9, 9)
connect _WIRE_8.hr, _T_188
node _T_189 = bits(_WIRE_9, 10, 10)
connect _WIRE_8.hx, _T_189
node _T_190 = bits(_WIRE_9, 11, 11)
connect _WIRE_8.hw, _T_190
node _T_191 = bits(_WIRE_9, 12, 12)
connect _WIRE_8.sr, _T_191
node _T_192 = bits(_WIRE_9, 13, 13)
connect _WIRE_8.sx, _T_192
node _T_193 = bits(_WIRE_9, 14, 14)
connect _WIRE_8.sw, _T_193
node _T_194 = bits(_WIRE_9, 15, 15)
connect _WIRE_8.gf, _T_194
node _T_195 = bits(_WIRE_9, 16, 16)
connect _WIRE_8.pf, _T_195
node _T_196 = bits(_WIRE_9, 17, 17)
connect _WIRE_8.ae_stage2, _T_196
node _T_197 = bits(_WIRE_9, 18, 18)
connect _WIRE_8.ae_final, _T_197
node _T_198 = bits(_WIRE_9, 19, 19)
connect _WIRE_8.ae_ptw, _T_198
node _T_199 = bits(_WIRE_9, 20, 20)
connect _WIRE_8.g, _T_199
node _T_200 = bits(_WIRE_9, 21, 21)
connect _WIRE_8.u, _T_200
node _T_201 = bits(_WIRE_9, 41, 22)
connect _WIRE_8.ppn, _T_201
wire _WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_11 : UInt<42>
connect _WIRE_11, sectored_entries[0][0].data[1]
node _T_202 = bits(_WIRE_11, 0, 0)
connect _WIRE_10.fragmented_superpage, _T_202
node _T_203 = bits(_WIRE_11, 1, 1)
connect _WIRE_10.c, _T_203
node _T_204 = bits(_WIRE_11, 2, 2)
connect _WIRE_10.eff, _T_204
node _T_205 = bits(_WIRE_11, 3, 3)
connect _WIRE_10.paa, _T_205
node _T_206 = bits(_WIRE_11, 4, 4)
connect _WIRE_10.pal, _T_206
node _T_207 = bits(_WIRE_11, 5, 5)
connect _WIRE_10.ppp, _T_207
node _T_208 = bits(_WIRE_11, 6, 6)
connect _WIRE_10.pr, _T_208
node _T_209 = bits(_WIRE_11, 7, 7)
connect _WIRE_10.px, _T_209
node _T_210 = bits(_WIRE_11, 8, 8)
connect _WIRE_10.pw, _T_210
node _T_211 = bits(_WIRE_11, 9, 9)
connect _WIRE_10.hr, _T_211
node _T_212 = bits(_WIRE_11, 10, 10)
connect _WIRE_10.hx, _T_212
node _T_213 = bits(_WIRE_11, 11, 11)
connect _WIRE_10.hw, _T_213
node _T_214 = bits(_WIRE_11, 12, 12)
connect _WIRE_10.sr, _T_214
node _T_215 = bits(_WIRE_11, 13, 13)
connect _WIRE_10.sx, _T_215
node _T_216 = bits(_WIRE_11, 14, 14)
connect _WIRE_10.sw, _T_216
node _T_217 = bits(_WIRE_11, 15, 15)
connect _WIRE_10.gf, _T_217
node _T_218 = bits(_WIRE_11, 16, 16)
connect _WIRE_10.pf, _T_218
node _T_219 = bits(_WIRE_11, 17, 17)
connect _WIRE_10.ae_stage2, _T_219
node _T_220 = bits(_WIRE_11, 18, 18)
connect _WIRE_10.ae_final, _T_220
node _T_221 = bits(_WIRE_11, 19, 19)
connect _WIRE_10.ae_ptw, _T_221
node _T_222 = bits(_WIRE_11, 20, 20)
connect _WIRE_10.g, _T_222
node _T_223 = bits(_WIRE_11, 21, 21)
connect _WIRE_10.u, _T_223
node _T_224 = bits(_WIRE_11, 41, 22)
connect _WIRE_10.ppn, _T_224
wire _WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_13 : UInt<42>
connect _WIRE_13, sectored_entries[0][0].data[2]
node _T_225 = bits(_WIRE_13, 0, 0)
connect _WIRE_12.fragmented_superpage, _T_225
node _T_226 = bits(_WIRE_13, 1, 1)
connect _WIRE_12.c, _T_226
node _T_227 = bits(_WIRE_13, 2, 2)
connect _WIRE_12.eff, _T_227
node _T_228 = bits(_WIRE_13, 3, 3)
connect _WIRE_12.paa, _T_228
node _T_229 = bits(_WIRE_13, 4, 4)
connect _WIRE_12.pal, _T_229
node _T_230 = bits(_WIRE_13, 5, 5)
connect _WIRE_12.ppp, _T_230
node _T_231 = bits(_WIRE_13, 6, 6)
connect _WIRE_12.pr, _T_231
node _T_232 = bits(_WIRE_13, 7, 7)
connect _WIRE_12.px, _T_232
node _T_233 = bits(_WIRE_13, 8, 8)
connect _WIRE_12.pw, _T_233
node _T_234 = bits(_WIRE_13, 9, 9)
connect _WIRE_12.hr, _T_234
node _T_235 = bits(_WIRE_13, 10, 10)
connect _WIRE_12.hx, _T_235
node _T_236 = bits(_WIRE_13, 11, 11)
connect _WIRE_12.hw, _T_236
node _T_237 = bits(_WIRE_13, 12, 12)
connect _WIRE_12.sr, _T_237
node _T_238 = bits(_WIRE_13, 13, 13)
connect _WIRE_12.sx, _T_238
node _T_239 = bits(_WIRE_13, 14, 14)
connect _WIRE_12.sw, _T_239
node _T_240 = bits(_WIRE_13, 15, 15)
connect _WIRE_12.gf, _T_240
node _T_241 = bits(_WIRE_13, 16, 16)
connect _WIRE_12.pf, _T_241
node _T_242 = bits(_WIRE_13, 17, 17)
connect _WIRE_12.ae_stage2, _T_242
node _T_243 = bits(_WIRE_13, 18, 18)
connect _WIRE_12.ae_final, _T_243
node _T_244 = bits(_WIRE_13, 19, 19)
connect _WIRE_12.ae_ptw, _T_244
node _T_245 = bits(_WIRE_13, 20, 20)
connect _WIRE_12.g, _T_245
node _T_246 = bits(_WIRE_13, 21, 21)
connect _WIRE_12.u, _T_246
node _T_247 = bits(_WIRE_13, 41, 22)
connect _WIRE_12.ppn, _T_247
wire _WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_15 : UInt<42>
connect _WIRE_15, sectored_entries[0][0].data[3]
node _T_248 = bits(_WIRE_15, 0, 0)
connect _WIRE_14.fragmented_superpage, _T_248
node _T_249 = bits(_WIRE_15, 1, 1)
connect _WIRE_14.c, _T_249
node _T_250 = bits(_WIRE_15, 2, 2)
connect _WIRE_14.eff, _T_250
node _T_251 = bits(_WIRE_15, 3, 3)
connect _WIRE_14.paa, _T_251
node _T_252 = bits(_WIRE_15, 4, 4)
connect _WIRE_14.pal, _T_252
node _T_253 = bits(_WIRE_15, 5, 5)
connect _WIRE_14.ppp, _T_253
node _T_254 = bits(_WIRE_15, 6, 6)
connect _WIRE_14.pr, _T_254
node _T_255 = bits(_WIRE_15, 7, 7)
connect _WIRE_14.px, _T_255
node _T_256 = bits(_WIRE_15, 8, 8)
connect _WIRE_14.pw, _T_256
node _T_257 = bits(_WIRE_15, 9, 9)
connect _WIRE_14.hr, _T_257
node _T_258 = bits(_WIRE_15, 10, 10)
connect _WIRE_14.hx, _T_258
node _T_259 = bits(_WIRE_15, 11, 11)
connect _WIRE_14.hw, _T_259
node _T_260 = bits(_WIRE_15, 12, 12)
connect _WIRE_14.sr, _T_260
node _T_261 = bits(_WIRE_15, 13, 13)
connect _WIRE_14.sx, _T_261
node _T_262 = bits(_WIRE_15, 14, 14)
connect _WIRE_14.sw, _T_262
node _T_263 = bits(_WIRE_15, 15, 15)
connect _WIRE_14.gf, _T_263
node _T_264 = bits(_WIRE_15, 16, 16)
connect _WIRE_14.pf, _T_264
node _T_265 = bits(_WIRE_15, 17, 17)
connect _WIRE_14.ae_stage2, _T_265
node _T_266 = bits(_WIRE_15, 18, 18)
connect _WIRE_14.ae_final, _T_266
node _T_267 = bits(_WIRE_15, 19, 19)
connect _WIRE_14.ae_ptw, _T_267
node _T_268 = bits(_WIRE_15, 20, 20)
connect _WIRE_14.g, _T_268
node _T_269 = bits(_WIRE_15, 21, 21)
connect _WIRE_14.u, _T_269
node _T_270 = bits(_WIRE_15, 41, 22)
connect _WIRE_14.ppn, _T_270
node _T_271 = eq(sectored_entries[0][0].tag_v, hv)
node _T_272 = and(_T_271, _WIRE_8.fragmented_superpage)
when _T_272 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
node _T_273 = eq(sectored_entries[0][0].tag_v, hv)
node _T_274 = and(_T_273, _WIRE_10.fragmented_superpage)
when _T_274 :
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
node _T_275 = eq(sectored_entries[0][0].tag_v, hv)
node _T_276 = and(_T_275, _WIRE_12.fragmented_superpage)
when _T_276 :
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
node _T_277 = eq(sectored_entries[0][0].tag_v, hv)
node _T_278 = and(_T_277, _WIRE_14.fragmented_superpage)
when _T_278 :
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
else :
node _T_279 = eq(hg, UInt<1>(0h0))
node _T_280 = and(_T_279, io.sfence.bits.rs2)
when _T_280 :
wire _WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_17 : UInt<42>
connect _WIRE_17, sectored_entries[0][0].data[0]
node _T_281 = bits(_WIRE_17, 0, 0)
connect _WIRE_16.fragmented_superpage, _T_281
node _T_282 = bits(_WIRE_17, 1, 1)
connect _WIRE_16.c, _T_282
node _T_283 = bits(_WIRE_17, 2, 2)
connect _WIRE_16.eff, _T_283
node _T_284 = bits(_WIRE_17, 3, 3)
connect _WIRE_16.paa, _T_284
node _T_285 = bits(_WIRE_17, 4, 4)
connect _WIRE_16.pal, _T_285
node _T_286 = bits(_WIRE_17, 5, 5)
connect _WIRE_16.ppp, _T_286
node _T_287 = bits(_WIRE_17, 6, 6)
connect _WIRE_16.pr, _T_287
node _T_288 = bits(_WIRE_17, 7, 7)
connect _WIRE_16.px, _T_288
node _T_289 = bits(_WIRE_17, 8, 8)
connect _WIRE_16.pw, _T_289
node _T_290 = bits(_WIRE_17, 9, 9)
connect _WIRE_16.hr, _T_290
node _T_291 = bits(_WIRE_17, 10, 10)
connect _WIRE_16.hx, _T_291
node _T_292 = bits(_WIRE_17, 11, 11)
connect _WIRE_16.hw, _T_292
node _T_293 = bits(_WIRE_17, 12, 12)
connect _WIRE_16.sr, _T_293
node _T_294 = bits(_WIRE_17, 13, 13)
connect _WIRE_16.sx, _T_294
node _T_295 = bits(_WIRE_17, 14, 14)
connect _WIRE_16.sw, _T_295
node _T_296 = bits(_WIRE_17, 15, 15)
connect _WIRE_16.gf, _T_296
node _T_297 = bits(_WIRE_17, 16, 16)
connect _WIRE_16.pf, _T_297
node _T_298 = bits(_WIRE_17, 17, 17)
connect _WIRE_16.ae_stage2, _T_298
node _T_299 = bits(_WIRE_17, 18, 18)
connect _WIRE_16.ae_final, _T_299
node _T_300 = bits(_WIRE_17, 19, 19)
connect _WIRE_16.ae_ptw, _T_300
node _T_301 = bits(_WIRE_17, 20, 20)
connect _WIRE_16.g, _T_301
node _T_302 = bits(_WIRE_17, 21, 21)
connect _WIRE_16.u, _T_302
node _T_303 = bits(_WIRE_17, 41, 22)
connect _WIRE_16.ppn, _T_303
wire _WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_19 : UInt<42>
connect _WIRE_19, sectored_entries[0][0].data[1]
node _T_304 = bits(_WIRE_19, 0, 0)
connect _WIRE_18.fragmented_superpage, _T_304
node _T_305 = bits(_WIRE_19, 1, 1)
connect _WIRE_18.c, _T_305
node _T_306 = bits(_WIRE_19, 2, 2)
connect _WIRE_18.eff, _T_306
node _T_307 = bits(_WIRE_19, 3, 3)
connect _WIRE_18.paa, _T_307
node _T_308 = bits(_WIRE_19, 4, 4)
connect _WIRE_18.pal, _T_308
node _T_309 = bits(_WIRE_19, 5, 5)
connect _WIRE_18.ppp, _T_309
node _T_310 = bits(_WIRE_19, 6, 6)
connect _WIRE_18.pr, _T_310
node _T_311 = bits(_WIRE_19, 7, 7)
connect _WIRE_18.px, _T_311
node _T_312 = bits(_WIRE_19, 8, 8)
connect _WIRE_18.pw, _T_312
node _T_313 = bits(_WIRE_19, 9, 9)
connect _WIRE_18.hr, _T_313
node _T_314 = bits(_WIRE_19, 10, 10)
connect _WIRE_18.hx, _T_314
node _T_315 = bits(_WIRE_19, 11, 11)
connect _WIRE_18.hw, _T_315
node _T_316 = bits(_WIRE_19, 12, 12)
connect _WIRE_18.sr, _T_316
node _T_317 = bits(_WIRE_19, 13, 13)
connect _WIRE_18.sx, _T_317
node _T_318 = bits(_WIRE_19, 14, 14)
connect _WIRE_18.sw, _T_318
node _T_319 = bits(_WIRE_19, 15, 15)
connect _WIRE_18.gf, _T_319
node _T_320 = bits(_WIRE_19, 16, 16)
connect _WIRE_18.pf, _T_320
node _T_321 = bits(_WIRE_19, 17, 17)
connect _WIRE_18.ae_stage2, _T_321
node _T_322 = bits(_WIRE_19, 18, 18)
connect _WIRE_18.ae_final, _T_322
node _T_323 = bits(_WIRE_19, 19, 19)
connect _WIRE_18.ae_ptw, _T_323
node _T_324 = bits(_WIRE_19, 20, 20)
connect _WIRE_18.g, _T_324
node _T_325 = bits(_WIRE_19, 21, 21)
connect _WIRE_18.u, _T_325
node _T_326 = bits(_WIRE_19, 41, 22)
connect _WIRE_18.ppn, _T_326
wire _WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_21 : UInt<42>
connect _WIRE_21, sectored_entries[0][0].data[2]
node _T_327 = bits(_WIRE_21, 0, 0)
connect _WIRE_20.fragmented_superpage, _T_327
node _T_328 = bits(_WIRE_21, 1, 1)
connect _WIRE_20.c, _T_328
node _T_329 = bits(_WIRE_21, 2, 2)
connect _WIRE_20.eff, _T_329
node _T_330 = bits(_WIRE_21, 3, 3)
connect _WIRE_20.paa, _T_330
node _T_331 = bits(_WIRE_21, 4, 4)
connect _WIRE_20.pal, _T_331
node _T_332 = bits(_WIRE_21, 5, 5)
connect _WIRE_20.ppp, _T_332
node _T_333 = bits(_WIRE_21, 6, 6)
connect _WIRE_20.pr, _T_333
node _T_334 = bits(_WIRE_21, 7, 7)
connect _WIRE_20.px, _T_334
node _T_335 = bits(_WIRE_21, 8, 8)
connect _WIRE_20.pw, _T_335
node _T_336 = bits(_WIRE_21, 9, 9)
connect _WIRE_20.hr, _T_336
node _T_337 = bits(_WIRE_21, 10, 10)
connect _WIRE_20.hx, _T_337
node _T_338 = bits(_WIRE_21, 11, 11)
connect _WIRE_20.hw, _T_338
node _T_339 = bits(_WIRE_21, 12, 12)
connect _WIRE_20.sr, _T_339
node _T_340 = bits(_WIRE_21, 13, 13)
connect _WIRE_20.sx, _T_340
node _T_341 = bits(_WIRE_21, 14, 14)
connect _WIRE_20.sw, _T_341
node _T_342 = bits(_WIRE_21, 15, 15)
connect _WIRE_20.gf, _T_342
node _T_343 = bits(_WIRE_21, 16, 16)
connect _WIRE_20.pf, _T_343
node _T_344 = bits(_WIRE_21, 17, 17)
connect _WIRE_20.ae_stage2, _T_344
node _T_345 = bits(_WIRE_21, 18, 18)
connect _WIRE_20.ae_final, _T_345
node _T_346 = bits(_WIRE_21, 19, 19)
connect _WIRE_20.ae_ptw, _T_346
node _T_347 = bits(_WIRE_21, 20, 20)
connect _WIRE_20.g, _T_347
node _T_348 = bits(_WIRE_21, 21, 21)
connect _WIRE_20.u, _T_348
node _T_349 = bits(_WIRE_21, 41, 22)
connect _WIRE_20.ppn, _T_349
wire _WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_23 : UInt<42>
connect _WIRE_23, sectored_entries[0][0].data[3]
node _T_350 = bits(_WIRE_23, 0, 0)
connect _WIRE_22.fragmented_superpage, _T_350
node _T_351 = bits(_WIRE_23, 1, 1)
connect _WIRE_22.c, _T_351
node _T_352 = bits(_WIRE_23, 2, 2)
connect _WIRE_22.eff, _T_352
node _T_353 = bits(_WIRE_23, 3, 3)
connect _WIRE_22.paa, _T_353
node _T_354 = bits(_WIRE_23, 4, 4)
connect _WIRE_22.pal, _T_354
node _T_355 = bits(_WIRE_23, 5, 5)
connect _WIRE_22.ppp, _T_355
node _T_356 = bits(_WIRE_23, 6, 6)
connect _WIRE_22.pr, _T_356
node _T_357 = bits(_WIRE_23, 7, 7)
connect _WIRE_22.px, _T_357
node _T_358 = bits(_WIRE_23, 8, 8)
connect _WIRE_22.pw, _T_358
node _T_359 = bits(_WIRE_23, 9, 9)
connect _WIRE_22.hr, _T_359
node _T_360 = bits(_WIRE_23, 10, 10)
connect _WIRE_22.hx, _T_360
node _T_361 = bits(_WIRE_23, 11, 11)
connect _WIRE_22.hw, _T_361
node _T_362 = bits(_WIRE_23, 12, 12)
connect _WIRE_22.sr, _T_362
node _T_363 = bits(_WIRE_23, 13, 13)
connect _WIRE_22.sx, _T_363
node _T_364 = bits(_WIRE_23, 14, 14)
connect _WIRE_22.sw, _T_364
node _T_365 = bits(_WIRE_23, 15, 15)
connect _WIRE_22.gf, _T_365
node _T_366 = bits(_WIRE_23, 16, 16)
connect _WIRE_22.pf, _T_366
node _T_367 = bits(_WIRE_23, 17, 17)
connect _WIRE_22.ae_stage2, _T_367
node _T_368 = bits(_WIRE_23, 18, 18)
connect _WIRE_22.ae_final, _T_368
node _T_369 = bits(_WIRE_23, 19, 19)
connect _WIRE_22.ae_ptw, _T_369
node _T_370 = bits(_WIRE_23, 20, 20)
connect _WIRE_22.g, _T_370
node _T_371 = bits(_WIRE_23, 21, 21)
connect _WIRE_22.u, _T_371
node _T_372 = bits(_WIRE_23, 41, 22)
connect _WIRE_22.ppn, _T_372
node _T_373 = eq(sectored_entries[0][0].tag_v, hv)
node _T_374 = eq(_WIRE_16.g, UInt<1>(0h0))
node _T_375 = and(_T_373, _T_374)
when _T_375 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
node _T_376 = eq(sectored_entries[0][0].tag_v, hv)
node _T_377 = eq(_WIRE_18.g, UInt<1>(0h0))
node _T_378 = and(_T_376, _T_377)
when _T_378 :
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
node _T_379 = eq(sectored_entries[0][0].tag_v, hv)
node _T_380 = eq(_WIRE_20.g, UInt<1>(0h0))
node _T_381 = and(_T_379, _T_380)
when _T_381 :
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
node _T_382 = eq(sectored_entries[0][0].tag_v, hv)
node _T_383 = eq(_WIRE_22.g, UInt<1>(0h0))
node _T_384 = and(_T_382, _T_383)
when _T_384 :
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
else :
node _T_385 = or(hv, hg)
wire _WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_25 : UInt<42>
connect _WIRE_25, sectored_entries[0][0].data[0]
node _T_386 = bits(_WIRE_25, 0, 0)
connect _WIRE_24.fragmented_superpage, _T_386
node _T_387 = bits(_WIRE_25, 1, 1)
connect _WIRE_24.c, _T_387
node _T_388 = bits(_WIRE_25, 2, 2)
connect _WIRE_24.eff, _T_388
node _T_389 = bits(_WIRE_25, 3, 3)
connect _WIRE_24.paa, _T_389
node _T_390 = bits(_WIRE_25, 4, 4)
connect _WIRE_24.pal, _T_390
node _T_391 = bits(_WIRE_25, 5, 5)
connect _WIRE_24.ppp, _T_391
node _T_392 = bits(_WIRE_25, 6, 6)
connect _WIRE_24.pr, _T_392
node _T_393 = bits(_WIRE_25, 7, 7)
connect _WIRE_24.px, _T_393
node _T_394 = bits(_WIRE_25, 8, 8)
connect _WIRE_24.pw, _T_394
node _T_395 = bits(_WIRE_25, 9, 9)
connect _WIRE_24.hr, _T_395
node _T_396 = bits(_WIRE_25, 10, 10)
connect _WIRE_24.hx, _T_396
node _T_397 = bits(_WIRE_25, 11, 11)
connect _WIRE_24.hw, _T_397
node _T_398 = bits(_WIRE_25, 12, 12)
connect _WIRE_24.sr, _T_398
node _T_399 = bits(_WIRE_25, 13, 13)
connect _WIRE_24.sx, _T_399
node _T_400 = bits(_WIRE_25, 14, 14)
connect _WIRE_24.sw, _T_400
node _T_401 = bits(_WIRE_25, 15, 15)
connect _WIRE_24.gf, _T_401
node _T_402 = bits(_WIRE_25, 16, 16)
connect _WIRE_24.pf, _T_402
node _T_403 = bits(_WIRE_25, 17, 17)
connect _WIRE_24.ae_stage2, _T_403
node _T_404 = bits(_WIRE_25, 18, 18)
connect _WIRE_24.ae_final, _T_404
node _T_405 = bits(_WIRE_25, 19, 19)
connect _WIRE_24.ae_ptw, _T_405
node _T_406 = bits(_WIRE_25, 20, 20)
connect _WIRE_24.g, _T_406
node _T_407 = bits(_WIRE_25, 21, 21)
connect _WIRE_24.u, _T_407
node _T_408 = bits(_WIRE_25, 41, 22)
connect _WIRE_24.ppn, _T_408
wire _WIRE_26 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_27 : UInt<42>
connect _WIRE_27, sectored_entries[0][0].data[1]
node _T_409 = bits(_WIRE_27, 0, 0)
connect _WIRE_26.fragmented_superpage, _T_409
node _T_410 = bits(_WIRE_27, 1, 1)
connect _WIRE_26.c, _T_410
node _T_411 = bits(_WIRE_27, 2, 2)
connect _WIRE_26.eff, _T_411
node _T_412 = bits(_WIRE_27, 3, 3)
connect _WIRE_26.paa, _T_412
node _T_413 = bits(_WIRE_27, 4, 4)
connect _WIRE_26.pal, _T_413
node _T_414 = bits(_WIRE_27, 5, 5)
connect _WIRE_26.ppp, _T_414
node _T_415 = bits(_WIRE_27, 6, 6)
connect _WIRE_26.pr, _T_415
node _T_416 = bits(_WIRE_27, 7, 7)
connect _WIRE_26.px, _T_416
node _T_417 = bits(_WIRE_27, 8, 8)
connect _WIRE_26.pw, _T_417
node _T_418 = bits(_WIRE_27, 9, 9)
connect _WIRE_26.hr, _T_418
node _T_419 = bits(_WIRE_27, 10, 10)
connect _WIRE_26.hx, _T_419
node _T_420 = bits(_WIRE_27, 11, 11)
connect _WIRE_26.hw, _T_420
node _T_421 = bits(_WIRE_27, 12, 12)
connect _WIRE_26.sr, _T_421
node _T_422 = bits(_WIRE_27, 13, 13)
connect _WIRE_26.sx, _T_422
node _T_423 = bits(_WIRE_27, 14, 14)
connect _WIRE_26.sw, _T_423
node _T_424 = bits(_WIRE_27, 15, 15)
connect _WIRE_26.gf, _T_424
node _T_425 = bits(_WIRE_27, 16, 16)
connect _WIRE_26.pf, _T_425
node _T_426 = bits(_WIRE_27, 17, 17)
connect _WIRE_26.ae_stage2, _T_426
node _T_427 = bits(_WIRE_27, 18, 18)
connect _WIRE_26.ae_final, _T_427
node _T_428 = bits(_WIRE_27, 19, 19)
connect _WIRE_26.ae_ptw, _T_428
node _T_429 = bits(_WIRE_27, 20, 20)
connect _WIRE_26.g, _T_429
node _T_430 = bits(_WIRE_27, 21, 21)
connect _WIRE_26.u, _T_430
node _T_431 = bits(_WIRE_27, 41, 22)
connect _WIRE_26.ppn, _T_431
wire _WIRE_28 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_29 : UInt<42>
connect _WIRE_29, sectored_entries[0][0].data[2]
node _T_432 = bits(_WIRE_29, 0, 0)
connect _WIRE_28.fragmented_superpage, _T_432
node _T_433 = bits(_WIRE_29, 1, 1)
connect _WIRE_28.c, _T_433
node _T_434 = bits(_WIRE_29, 2, 2)
connect _WIRE_28.eff, _T_434
node _T_435 = bits(_WIRE_29, 3, 3)
connect _WIRE_28.paa, _T_435
node _T_436 = bits(_WIRE_29, 4, 4)
connect _WIRE_28.pal, _T_436
node _T_437 = bits(_WIRE_29, 5, 5)
connect _WIRE_28.ppp, _T_437
node _T_438 = bits(_WIRE_29, 6, 6)
connect _WIRE_28.pr, _T_438
node _T_439 = bits(_WIRE_29, 7, 7)
connect _WIRE_28.px, _T_439
node _T_440 = bits(_WIRE_29, 8, 8)
connect _WIRE_28.pw, _T_440
node _T_441 = bits(_WIRE_29, 9, 9)
connect _WIRE_28.hr, _T_441
node _T_442 = bits(_WIRE_29, 10, 10)
connect _WIRE_28.hx, _T_442
node _T_443 = bits(_WIRE_29, 11, 11)
connect _WIRE_28.hw, _T_443
node _T_444 = bits(_WIRE_29, 12, 12)
connect _WIRE_28.sr, _T_444
node _T_445 = bits(_WIRE_29, 13, 13)
connect _WIRE_28.sx, _T_445
node _T_446 = bits(_WIRE_29, 14, 14)
connect _WIRE_28.sw, _T_446
node _T_447 = bits(_WIRE_29, 15, 15)
connect _WIRE_28.gf, _T_447
node _T_448 = bits(_WIRE_29, 16, 16)
connect _WIRE_28.pf, _T_448
node _T_449 = bits(_WIRE_29, 17, 17)
connect _WIRE_28.ae_stage2, _T_449
node _T_450 = bits(_WIRE_29, 18, 18)
connect _WIRE_28.ae_final, _T_450
node _T_451 = bits(_WIRE_29, 19, 19)
connect _WIRE_28.ae_ptw, _T_451
node _T_452 = bits(_WIRE_29, 20, 20)
connect _WIRE_28.g, _T_452
node _T_453 = bits(_WIRE_29, 21, 21)
connect _WIRE_28.u, _T_453
node _T_454 = bits(_WIRE_29, 41, 22)
connect _WIRE_28.ppn, _T_454
wire _WIRE_30 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_31 : UInt<42>
connect _WIRE_31, sectored_entries[0][0].data[3]
node _T_455 = bits(_WIRE_31, 0, 0)
connect _WIRE_30.fragmented_superpage, _T_455
node _T_456 = bits(_WIRE_31, 1, 1)
connect _WIRE_30.c, _T_456
node _T_457 = bits(_WIRE_31, 2, 2)
connect _WIRE_30.eff, _T_457
node _T_458 = bits(_WIRE_31, 3, 3)
connect _WIRE_30.paa, _T_458
node _T_459 = bits(_WIRE_31, 4, 4)
connect _WIRE_30.pal, _T_459
node _T_460 = bits(_WIRE_31, 5, 5)
connect _WIRE_30.ppp, _T_460
node _T_461 = bits(_WIRE_31, 6, 6)
connect _WIRE_30.pr, _T_461
node _T_462 = bits(_WIRE_31, 7, 7)
connect _WIRE_30.px, _T_462
node _T_463 = bits(_WIRE_31, 8, 8)
connect _WIRE_30.pw, _T_463
node _T_464 = bits(_WIRE_31, 9, 9)
connect _WIRE_30.hr, _T_464
node _T_465 = bits(_WIRE_31, 10, 10)
connect _WIRE_30.hx, _T_465
node _T_466 = bits(_WIRE_31, 11, 11)
connect _WIRE_30.hw, _T_466
node _T_467 = bits(_WIRE_31, 12, 12)
connect _WIRE_30.sr, _T_467
node _T_468 = bits(_WIRE_31, 13, 13)
connect _WIRE_30.sx, _T_468
node _T_469 = bits(_WIRE_31, 14, 14)
connect _WIRE_30.sw, _T_469
node _T_470 = bits(_WIRE_31, 15, 15)
connect _WIRE_30.gf, _T_470
node _T_471 = bits(_WIRE_31, 16, 16)
connect _WIRE_30.pf, _T_471
node _T_472 = bits(_WIRE_31, 17, 17)
connect _WIRE_30.ae_stage2, _T_472
node _T_473 = bits(_WIRE_31, 18, 18)
connect _WIRE_30.ae_final, _T_473
node _T_474 = bits(_WIRE_31, 19, 19)
connect _WIRE_30.ae_ptw, _T_474
node _T_475 = bits(_WIRE_31, 20, 20)
connect _WIRE_30.g, _T_475
node _T_476 = bits(_WIRE_31, 21, 21)
connect _WIRE_30.u, _T_476
node _T_477 = bits(_WIRE_31, 41, 22)
connect _WIRE_30.ppn, _T_477
node _T_478 = eq(sectored_entries[0][0].tag_v, _T_385)
when _T_478 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
node _T_479 = eq(sectored_entries[0][0].tag_v, _T_385)
when _T_479 :
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
node _T_480 = eq(sectored_entries[0][0].tag_v, _T_385)
when _T_480 :
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
node _T_481 = eq(sectored_entries[0][0].tag_v, _T_385)
when _T_481 :
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
node hv_1 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_1 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_482 = eq(hg_1, UInt<1>(0h0))
node _T_483 = and(_T_482, io.sfence.bits.rs1)
when _T_483 :
node _T_484 = xor(sectored_entries[0][1].tag_vpn, vpn)
node _T_485 = shr(_T_484, 2)
node _T_486 = eq(_T_485, UInt<1>(0h0))
node _T_487 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_488 = and(_T_486, _T_487)
when _T_488 :
wire _WIRE_32 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_33 : UInt<42>
connect _WIRE_33, sectored_entries[0][1].data[0]
node _T_489 = bits(_WIRE_33, 0, 0)
connect _WIRE_32.fragmented_superpage, _T_489
node _T_490 = bits(_WIRE_33, 1, 1)
connect _WIRE_32.c, _T_490
node _T_491 = bits(_WIRE_33, 2, 2)
connect _WIRE_32.eff, _T_491
node _T_492 = bits(_WIRE_33, 3, 3)
connect _WIRE_32.paa, _T_492
node _T_493 = bits(_WIRE_33, 4, 4)
connect _WIRE_32.pal, _T_493
node _T_494 = bits(_WIRE_33, 5, 5)
connect _WIRE_32.ppp, _T_494
node _T_495 = bits(_WIRE_33, 6, 6)
connect _WIRE_32.pr, _T_495
node _T_496 = bits(_WIRE_33, 7, 7)
connect _WIRE_32.px, _T_496
node _T_497 = bits(_WIRE_33, 8, 8)
connect _WIRE_32.pw, _T_497
node _T_498 = bits(_WIRE_33, 9, 9)
connect _WIRE_32.hr, _T_498
node _T_499 = bits(_WIRE_33, 10, 10)
connect _WIRE_32.hx, _T_499
node _T_500 = bits(_WIRE_33, 11, 11)
connect _WIRE_32.hw, _T_500
node _T_501 = bits(_WIRE_33, 12, 12)
connect _WIRE_32.sr, _T_501
node _T_502 = bits(_WIRE_33, 13, 13)
connect _WIRE_32.sx, _T_502
node _T_503 = bits(_WIRE_33, 14, 14)
connect _WIRE_32.sw, _T_503
node _T_504 = bits(_WIRE_33, 15, 15)
connect _WIRE_32.gf, _T_504
node _T_505 = bits(_WIRE_33, 16, 16)
connect _WIRE_32.pf, _T_505
node _T_506 = bits(_WIRE_33, 17, 17)
connect _WIRE_32.ae_stage2, _T_506
node _T_507 = bits(_WIRE_33, 18, 18)
connect _WIRE_32.ae_final, _T_507
node _T_508 = bits(_WIRE_33, 19, 19)
connect _WIRE_32.ae_ptw, _T_508
node _T_509 = bits(_WIRE_33, 20, 20)
connect _WIRE_32.g, _T_509
node _T_510 = bits(_WIRE_33, 21, 21)
connect _WIRE_32.u, _T_510
node _T_511 = bits(_WIRE_33, 41, 22)
connect _WIRE_32.ppn, _T_511
wire _WIRE_34 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_35 : UInt<42>
connect _WIRE_35, sectored_entries[0][1].data[1]
node _T_512 = bits(_WIRE_35, 0, 0)
connect _WIRE_34.fragmented_superpage, _T_512
node _T_513 = bits(_WIRE_35, 1, 1)
connect _WIRE_34.c, _T_513
node _T_514 = bits(_WIRE_35, 2, 2)
connect _WIRE_34.eff, _T_514
node _T_515 = bits(_WIRE_35, 3, 3)
connect _WIRE_34.paa, _T_515
node _T_516 = bits(_WIRE_35, 4, 4)
connect _WIRE_34.pal, _T_516
node _T_517 = bits(_WIRE_35, 5, 5)
connect _WIRE_34.ppp, _T_517
node _T_518 = bits(_WIRE_35, 6, 6)
connect _WIRE_34.pr, _T_518
node _T_519 = bits(_WIRE_35, 7, 7)
connect _WIRE_34.px, _T_519
node _T_520 = bits(_WIRE_35, 8, 8)
connect _WIRE_34.pw, _T_520
node _T_521 = bits(_WIRE_35, 9, 9)
connect _WIRE_34.hr, _T_521
node _T_522 = bits(_WIRE_35, 10, 10)
connect _WIRE_34.hx, _T_522
node _T_523 = bits(_WIRE_35, 11, 11)
connect _WIRE_34.hw, _T_523
node _T_524 = bits(_WIRE_35, 12, 12)
connect _WIRE_34.sr, _T_524
node _T_525 = bits(_WIRE_35, 13, 13)
connect _WIRE_34.sx, _T_525
node _T_526 = bits(_WIRE_35, 14, 14)
connect _WIRE_34.sw, _T_526
node _T_527 = bits(_WIRE_35, 15, 15)
connect _WIRE_34.gf, _T_527
node _T_528 = bits(_WIRE_35, 16, 16)
connect _WIRE_34.pf, _T_528
node _T_529 = bits(_WIRE_35, 17, 17)
connect _WIRE_34.ae_stage2, _T_529
node _T_530 = bits(_WIRE_35, 18, 18)
connect _WIRE_34.ae_final, _T_530
node _T_531 = bits(_WIRE_35, 19, 19)
connect _WIRE_34.ae_ptw, _T_531
node _T_532 = bits(_WIRE_35, 20, 20)
connect _WIRE_34.g, _T_532
node _T_533 = bits(_WIRE_35, 21, 21)
connect _WIRE_34.u, _T_533
node _T_534 = bits(_WIRE_35, 41, 22)
connect _WIRE_34.ppn, _T_534
wire _WIRE_36 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_37 : UInt<42>
connect _WIRE_37, sectored_entries[0][1].data[2]
node _T_535 = bits(_WIRE_37, 0, 0)
connect _WIRE_36.fragmented_superpage, _T_535
node _T_536 = bits(_WIRE_37, 1, 1)
connect _WIRE_36.c, _T_536
node _T_537 = bits(_WIRE_37, 2, 2)
connect _WIRE_36.eff, _T_537
node _T_538 = bits(_WIRE_37, 3, 3)
connect _WIRE_36.paa, _T_538
node _T_539 = bits(_WIRE_37, 4, 4)
connect _WIRE_36.pal, _T_539
node _T_540 = bits(_WIRE_37, 5, 5)
connect _WIRE_36.ppp, _T_540
node _T_541 = bits(_WIRE_37, 6, 6)
connect _WIRE_36.pr, _T_541
node _T_542 = bits(_WIRE_37, 7, 7)
connect _WIRE_36.px, _T_542
node _T_543 = bits(_WIRE_37, 8, 8)
connect _WIRE_36.pw, _T_543
node _T_544 = bits(_WIRE_37, 9, 9)
connect _WIRE_36.hr, _T_544
node _T_545 = bits(_WIRE_37, 10, 10)
connect _WIRE_36.hx, _T_545
node _T_546 = bits(_WIRE_37, 11, 11)
connect _WIRE_36.hw, _T_546
node _T_547 = bits(_WIRE_37, 12, 12)
connect _WIRE_36.sr, _T_547
node _T_548 = bits(_WIRE_37, 13, 13)
connect _WIRE_36.sx, _T_548
node _T_549 = bits(_WIRE_37, 14, 14)
connect _WIRE_36.sw, _T_549
node _T_550 = bits(_WIRE_37, 15, 15)
connect _WIRE_36.gf, _T_550
node _T_551 = bits(_WIRE_37, 16, 16)
connect _WIRE_36.pf, _T_551
node _T_552 = bits(_WIRE_37, 17, 17)
connect _WIRE_36.ae_stage2, _T_552
node _T_553 = bits(_WIRE_37, 18, 18)
connect _WIRE_36.ae_final, _T_553
node _T_554 = bits(_WIRE_37, 19, 19)
connect _WIRE_36.ae_ptw, _T_554
node _T_555 = bits(_WIRE_37, 20, 20)
connect _WIRE_36.g, _T_555
node _T_556 = bits(_WIRE_37, 21, 21)
connect _WIRE_36.u, _T_556
node _T_557 = bits(_WIRE_37, 41, 22)
connect _WIRE_36.ppn, _T_557
wire _WIRE_38 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_39 : UInt<42>
connect _WIRE_39, sectored_entries[0][1].data[3]
node _T_558 = bits(_WIRE_39, 0, 0)
connect _WIRE_38.fragmented_superpage, _T_558
node _T_559 = bits(_WIRE_39, 1, 1)
connect _WIRE_38.c, _T_559
node _T_560 = bits(_WIRE_39, 2, 2)
connect _WIRE_38.eff, _T_560
node _T_561 = bits(_WIRE_39, 3, 3)
connect _WIRE_38.paa, _T_561
node _T_562 = bits(_WIRE_39, 4, 4)
connect _WIRE_38.pal, _T_562
node _T_563 = bits(_WIRE_39, 5, 5)
connect _WIRE_38.ppp, _T_563
node _T_564 = bits(_WIRE_39, 6, 6)
connect _WIRE_38.pr, _T_564
node _T_565 = bits(_WIRE_39, 7, 7)
connect _WIRE_38.px, _T_565
node _T_566 = bits(_WIRE_39, 8, 8)
connect _WIRE_38.pw, _T_566
node _T_567 = bits(_WIRE_39, 9, 9)
connect _WIRE_38.hr, _T_567
node _T_568 = bits(_WIRE_39, 10, 10)
connect _WIRE_38.hx, _T_568
node _T_569 = bits(_WIRE_39, 11, 11)
connect _WIRE_38.hw, _T_569
node _T_570 = bits(_WIRE_39, 12, 12)
connect _WIRE_38.sr, _T_570
node _T_571 = bits(_WIRE_39, 13, 13)
connect _WIRE_38.sx, _T_571
node _T_572 = bits(_WIRE_39, 14, 14)
connect _WIRE_38.sw, _T_572
node _T_573 = bits(_WIRE_39, 15, 15)
connect _WIRE_38.gf, _T_573
node _T_574 = bits(_WIRE_39, 16, 16)
connect _WIRE_38.pf, _T_574
node _T_575 = bits(_WIRE_39, 17, 17)
connect _WIRE_38.ae_stage2, _T_575
node _T_576 = bits(_WIRE_39, 18, 18)
connect _WIRE_38.ae_final, _T_576
node _T_577 = bits(_WIRE_39, 19, 19)
connect _WIRE_38.ae_ptw, _T_577
node _T_578 = bits(_WIRE_39, 20, 20)
connect _WIRE_38.g, _T_578
node _T_579 = bits(_WIRE_39, 21, 21)
connect _WIRE_38.u, _T_579
node _T_580 = bits(_WIRE_39, 41, 22)
connect _WIRE_38.ppn, _T_580
node _T_581 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_582 = bits(vpn, 1, 0)
node _T_583 = eq(UInt<1>(0h0), _T_582)
node _T_584 = and(_T_581, _T_583)
when _T_584 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
node _T_585 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_586 = bits(vpn, 1, 0)
node _T_587 = eq(UInt<1>(0h1), _T_586)
node _T_588 = and(_T_585, _T_587)
when _T_588 :
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
node _T_589 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_590 = bits(vpn, 1, 0)
node _T_591 = eq(UInt<2>(0h2), _T_590)
node _T_592 = and(_T_589, _T_591)
when _T_592 :
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
node _T_593 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_594 = bits(vpn, 1, 0)
node _T_595 = eq(UInt<2>(0h3), _T_594)
node _T_596 = and(_T_593, _T_595)
when _T_596 :
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
node _T_597 = xor(sectored_entries[0][1].tag_vpn, vpn)
node _T_598 = shr(_T_597, 18)
node _T_599 = eq(_T_598, UInt<1>(0h0))
when _T_599 :
wire _WIRE_40 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_41 : UInt<42>
connect _WIRE_41, sectored_entries[0][1].data[0]
node _T_600 = bits(_WIRE_41, 0, 0)
connect _WIRE_40.fragmented_superpage, _T_600
node _T_601 = bits(_WIRE_41, 1, 1)
connect _WIRE_40.c, _T_601
node _T_602 = bits(_WIRE_41, 2, 2)
connect _WIRE_40.eff, _T_602
node _T_603 = bits(_WIRE_41, 3, 3)
connect _WIRE_40.paa, _T_603
node _T_604 = bits(_WIRE_41, 4, 4)
connect _WIRE_40.pal, _T_604
node _T_605 = bits(_WIRE_41, 5, 5)
connect _WIRE_40.ppp, _T_605
node _T_606 = bits(_WIRE_41, 6, 6)
connect _WIRE_40.pr, _T_606
node _T_607 = bits(_WIRE_41, 7, 7)
connect _WIRE_40.px, _T_607
node _T_608 = bits(_WIRE_41, 8, 8)
connect _WIRE_40.pw, _T_608
node _T_609 = bits(_WIRE_41, 9, 9)
connect _WIRE_40.hr, _T_609
node _T_610 = bits(_WIRE_41, 10, 10)
connect _WIRE_40.hx, _T_610
node _T_611 = bits(_WIRE_41, 11, 11)
connect _WIRE_40.hw, _T_611
node _T_612 = bits(_WIRE_41, 12, 12)
connect _WIRE_40.sr, _T_612
node _T_613 = bits(_WIRE_41, 13, 13)
connect _WIRE_40.sx, _T_613
node _T_614 = bits(_WIRE_41, 14, 14)
connect _WIRE_40.sw, _T_614
node _T_615 = bits(_WIRE_41, 15, 15)
connect _WIRE_40.gf, _T_615
node _T_616 = bits(_WIRE_41, 16, 16)
connect _WIRE_40.pf, _T_616
node _T_617 = bits(_WIRE_41, 17, 17)
connect _WIRE_40.ae_stage2, _T_617
node _T_618 = bits(_WIRE_41, 18, 18)
connect _WIRE_40.ae_final, _T_618
node _T_619 = bits(_WIRE_41, 19, 19)
connect _WIRE_40.ae_ptw, _T_619
node _T_620 = bits(_WIRE_41, 20, 20)
connect _WIRE_40.g, _T_620
node _T_621 = bits(_WIRE_41, 21, 21)
connect _WIRE_40.u, _T_621
node _T_622 = bits(_WIRE_41, 41, 22)
connect _WIRE_40.ppn, _T_622
wire _WIRE_42 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_43 : UInt<42>
connect _WIRE_43, sectored_entries[0][1].data[1]
node _T_623 = bits(_WIRE_43, 0, 0)
connect _WIRE_42.fragmented_superpage, _T_623
node _T_624 = bits(_WIRE_43, 1, 1)
connect _WIRE_42.c, _T_624
node _T_625 = bits(_WIRE_43, 2, 2)
connect _WIRE_42.eff, _T_625
node _T_626 = bits(_WIRE_43, 3, 3)
connect _WIRE_42.paa, _T_626
node _T_627 = bits(_WIRE_43, 4, 4)
connect _WIRE_42.pal, _T_627
node _T_628 = bits(_WIRE_43, 5, 5)
connect _WIRE_42.ppp, _T_628
node _T_629 = bits(_WIRE_43, 6, 6)
connect _WIRE_42.pr, _T_629
node _T_630 = bits(_WIRE_43, 7, 7)
connect _WIRE_42.px, _T_630
node _T_631 = bits(_WIRE_43, 8, 8)
connect _WIRE_42.pw, _T_631
node _T_632 = bits(_WIRE_43, 9, 9)
connect _WIRE_42.hr, _T_632
node _T_633 = bits(_WIRE_43, 10, 10)
connect _WIRE_42.hx, _T_633
node _T_634 = bits(_WIRE_43, 11, 11)
connect _WIRE_42.hw, _T_634
node _T_635 = bits(_WIRE_43, 12, 12)
connect _WIRE_42.sr, _T_635
node _T_636 = bits(_WIRE_43, 13, 13)
connect _WIRE_42.sx, _T_636
node _T_637 = bits(_WIRE_43, 14, 14)
connect _WIRE_42.sw, _T_637
node _T_638 = bits(_WIRE_43, 15, 15)
connect _WIRE_42.gf, _T_638
node _T_639 = bits(_WIRE_43, 16, 16)
connect _WIRE_42.pf, _T_639
node _T_640 = bits(_WIRE_43, 17, 17)
connect _WIRE_42.ae_stage2, _T_640
node _T_641 = bits(_WIRE_43, 18, 18)
connect _WIRE_42.ae_final, _T_641
node _T_642 = bits(_WIRE_43, 19, 19)
connect _WIRE_42.ae_ptw, _T_642
node _T_643 = bits(_WIRE_43, 20, 20)
connect _WIRE_42.g, _T_643
node _T_644 = bits(_WIRE_43, 21, 21)
connect _WIRE_42.u, _T_644
node _T_645 = bits(_WIRE_43, 41, 22)
connect _WIRE_42.ppn, _T_645
wire _WIRE_44 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_45 : UInt<42>
connect _WIRE_45, sectored_entries[0][1].data[2]
node _T_646 = bits(_WIRE_45, 0, 0)
connect _WIRE_44.fragmented_superpage, _T_646
node _T_647 = bits(_WIRE_45, 1, 1)
connect _WIRE_44.c, _T_647
node _T_648 = bits(_WIRE_45, 2, 2)
connect _WIRE_44.eff, _T_648
node _T_649 = bits(_WIRE_45, 3, 3)
connect _WIRE_44.paa, _T_649
node _T_650 = bits(_WIRE_45, 4, 4)
connect _WIRE_44.pal, _T_650
node _T_651 = bits(_WIRE_45, 5, 5)
connect _WIRE_44.ppp, _T_651
node _T_652 = bits(_WIRE_45, 6, 6)
connect _WIRE_44.pr, _T_652
node _T_653 = bits(_WIRE_45, 7, 7)
connect _WIRE_44.px, _T_653
node _T_654 = bits(_WIRE_45, 8, 8)
connect _WIRE_44.pw, _T_654
node _T_655 = bits(_WIRE_45, 9, 9)
connect _WIRE_44.hr, _T_655
node _T_656 = bits(_WIRE_45, 10, 10)
connect _WIRE_44.hx, _T_656
node _T_657 = bits(_WIRE_45, 11, 11)
connect _WIRE_44.hw, _T_657
node _T_658 = bits(_WIRE_45, 12, 12)
connect _WIRE_44.sr, _T_658
node _T_659 = bits(_WIRE_45, 13, 13)
connect _WIRE_44.sx, _T_659
node _T_660 = bits(_WIRE_45, 14, 14)
connect _WIRE_44.sw, _T_660
node _T_661 = bits(_WIRE_45, 15, 15)
connect _WIRE_44.gf, _T_661
node _T_662 = bits(_WIRE_45, 16, 16)
connect _WIRE_44.pf, _T_662
node _T_663 = bits(_WIRE_45, 17, 17)
connect _WIRE_44.ae_stage2, _T_663
node _T_664 = bits(_WIRE_45, 18, 18)
connect _WIRE_44.ae_final, _T_664
node _T_665 = bits(_WIRE_45, 19, 19)
connect _WIRE_44.ae_ptw, _T_665
node _T_666 = bits(_WIRE_45, 20, 20)
connect _WIRE_44.g, _T_666
node _T_667 = bits(_WIRE_45, 21, 21)
connect _WIRE_44.u, _T_667
node _T_668 = bits(_WIRE_45, 41, 22)
connect _WIRE_44.ppn, _T_668
wire _WIRE_46 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_47 : UInt<42>
connect _WIRE_47, sectored_entries[0][1].data[3]
node _T_669 = bits(_WIRE_47, 0, 0)
connect _WIRE_46.fragmented_superpage, _T_669
node _T_670 = bits(_WIRE_47, 1, 1)
connect _WIRE_46.c, _T_670
node _T_671 = bits(_WIRE_47, 2, 2)
connect _WIRE_46.eff, _T_671
node _T_672 = bits(_WIRE_47, 3, 3)
connect _WIRE_46.paa, _T_672
node _T_673 = bits(_WIRE_47, 4, 4)
connect _WIRE_46.pal, _T_673
node _T_674 = bits(_WIRE_47, 5, 5)
connect _WIRE_46.ppp, _T_674
node _T_675 = bits(_WIRE_47, 6, 6)
connect _WIRE_46.pr, _T_675
node _T_676 = bits(_WIRE_47, 7, 7)
connect _WIRE_46.px, _T_676
node _T_677 = bits(_WIRE_47, 8, 8)
connect _WIRE_46.pw, _T_677
node _T_678 = bits(_WIRE_47, 9, 9)
connect _WIRE_46.hr, _T_678
node _T_679 = bits(_WIRE_47, 10, 10)
connect _WIRE_46.hx, _T_679
node _T_680 = bits(_WIRE_47, 11, 11)
connect _WIRE_46.hw, _T_680
node _T_681 = bits(_WIRE_47, 12, 12)
connect _WIRE_46.sr, _T_681
node _T_682 = bits(_WIRE_47, 13, 13)
connect _WIRE_46.sx, _T_682
node _T_683 = bits(_WIRE_47, 14, 14)
connect _WIRE_46.sw, _T_683
node _T_684 = bits(_WIRE_47, 15, 15)
connect _WIRE_46.gf, _T_684
node _T_685 = bits(_WIRE_47, 16, 16)
connect _WIRE_46.pf, _T_685
node _T_686 = bits(_WIRE_47, 17, 17)
connect _WIRE_46.ae_stage2, _T_686
node _T_687 = bits(_WIRE_47, 18, 18)
connect _WIRE_46.ae_final, _T_687
node _T_688 = bits(_WIRE_47, 19, 19)
connect _WIRE_46.ae_ptw, _T_688
node _T_689 = bits(_WIRE_47, 20, 20)
connect _WIRE_46.g, _T_689
node _T_690 = bits(_WIRE_47, 21, 21)
connect _WIRE_46.u, _T_690
node _T_691 = bits(_WIRE_47, 41, 22)
connect _WIRE_46.ppn, _T_691
node _T_692 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_693 = and(_T_692, _WIRE_40.fragmented_superpage)
when _T_693 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
node _T_694 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_695 = and(_T_694, _WIRE_42.fragmented_superpage)
when _T_695 :
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
node _T_696 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_697 = and(_T_696, _WIRE_44.fragmented_superpage)
when _T_697 :
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
node _T_698 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_699 = and(_T_698, _WIRE_46.fragmented_superpage)
when _T_699 :
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
else :
node _T_700 = eq(hg_1, UInt<1>(0h0))
node _T_701 = and(_T_700, io.sfence.bits.rs2)
when _T_701 :
wire _WIRE_48 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_49 : UInt<42>
connect _WIRE_49, sectored_entries[0][1].data[0]
node _T_702 = bits(_WIRE_49, 0, 0)
connect _WIRE_48.fragmented_superpage, _T_702
node _T_703 = bits(_WIRE_49, 1, 1)
connect _WIRE_48.c, _T_703
node _T_704 = bits(_WIRE_49, 2, 2)
connect _WIRE_48.eff, _T_704
node _T_705 = bits(_WIRE_49, 3, 3)
connect _WIRE_48.paa, _T_705
node _T_706 = bits(_WIRE_49, 4, 4)
connect _WIRE_48.pal, _T_706
node _T_707 = bits(_WIRE_49, 5, 5)
connect _WIRE_48.ppp, _T_707
node _T_708 = bits(_WIRE_49, 6, 6)
connect _WIRE_48.pr, _T_708
node _T_709 = bits(_WIRE_49, 7, 7)
connect _WIRE_48.px, _T_709
node _T_710 = bits(_WIRE_49, 8, 8)
connect _WIRE_48.pw, _T_710
node _T_711 = bits(_WIRE_49, 9, 9)
connect _WIRE_48.hr, _T_711
node _T_712 = bits(_WIRE_49, 10, 10)
connect _WIRE_48.hx, _T_712
node _T_713 = bits(_WIRE_49, 11, 11)
connect _WIRE_48.hw, _T_713
node _T_714 = bits(_WIRE_49, 12, 12)
connect _WIRE_48.sr, _T_714
node _T_715 = bits(_WIRE_49, 13, 13)
connect _WIRE_48.sx, _T_715
node _T_716 = bits(_WIRE_49, 14, 14)
connect _WIRE_48.sw, _T_716
node _T_717 = bits(_WIRE_49, 15, 15)
connect _WIRE_48.gf, _T_717
node _T_718 = bits(_WIRE_49, 16, 16)
connect _WIRE_48.pf, _T_718
node _T_719 = bits(_WIRE_49, 17, 17)
connect _WIRE_48.ae_stage2, _T_719
node _T_720 = bits(_WIRE_49, 18, 18)
connect _WIRE_48.ae_final, _T_720
node _T_721 = bits(_WIRE_49, 19, 19)
connect _WIRE_48.ae_ptw, _T_721
node _T_722 = bits(_WIRE_49, 20, 20)
connect _WIRE_48.g, _T_722
node _T_723 = bits(_WIRE_49, 21, 21)
connect _WIRE_48.u, _T_723
node _T_724 = bits(_WIRE_49, 41, 22)
connect _WIRE_48.ppn, _T_724
wire _WIRE_50 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_51 : UInt<42>
connect _WIRE_51, sectored_entries[0][1].data[1]
node _T_725 = bits(_WIRE_51, 0, 0)
connect _WIRE_50.fragmented_superpage, _T_725
node _T_726 = bits(_WIRE_51, 1, 1)
connect _WIRE_50.c, _T_726
node _T_727 = bits(_WIRE_51, 2, 2)
connect _WIRE_50.eff, _T_727
node _T_728 = bits(_WIRE_51, 3, 3)
connect _WIRE_50.paa, _T_728
node _T_729 = bits(_WIRE_51, 4, 4)
connect _WIRE_50.pal, _T_729
node _T_730 = bits(_WIRE_51, 5, 5)
connect _WIRE_50.ppp, _T_730
node _T_731 = bits(_WIRE_51, 6, 6)
connect _WIRE_50.pr, _T_731
node _T_732 = bits(_WIRE_51, 7, 7)
connect _WIRE_50.px, _T_732
node _T_733 = bits(_WIRE_51, 8, 8)
connect _WIRE_50.pw, _T_733
node _T_734 = bits(_WIRE_51, 9, 9)
connect _WIRE_50.hr, _T_734
node _T_735 = bits(_WIRE_51, 10, 10)
connect _WIRE_50.hx, _T_735
node _T_736 = bits(_WIRE_51, 11, 11)
connect _WIRE_50.hw, _T_736
node _T_737 = bits(_WIRE_51, 12, 12)
connect _WIRE_50.sr, _T_737
node _T_738 = bits(_WIRE_51, 13, 13)
connect _WIRE_50.sx, _T_738
node _T_739 = bits(_WIRE_51, 14, 14)
connect _WIRE_50.sw, _T_739
node _T_740 = bits(_WIRE_51, 15, 15)
connect _WIRE_50.gf, _T_740
node _T_741 = bits(_WIRE_51, 16, 16)
connect _WIRE_50.pf, _T_741
node _T_742 = bits(_WIRE_51, 17, 17)
connect _WIRE_50.ae_stage2, _T_742
node _T_743 = bits(_WIRE_51, 18, 18)
connect _WIRE_50.ae_final, _T_743
node _T_744 = bits(_WIRE_51, 19, 19)
connect _WIRE_50.ae_ptw, _T_744
node _T_745 = bits(_WIRE_51, 20, 20)
connect _WIRE_50.g, _T_745
node _T_746 = bits(_WIRE_51, 21, 21)
connect _WIRE_50.u, _T_746
node _T_747 = bits(_WIRE_51, 41, 22)
connect _WIRE_50.ppn, _T_747
wire _WIRE_52 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_53 : UInt<42>
connect _WIRE_53, sectored_entries[0][1].data[2]
node _T_748 = bits(_WIRE_53, 0, 0)
connect _WIRE_52.fragmented_superpage, _T_748
node _T_749 = bits(_WIRE_53, 1, 1)
connect _WIRE_52.c, _T_749
node _T_750 = bits(_WIRE_53, 2, 2)
connect _WIRE_52.eff, _T_750
node _T_751 = bits(_WIRE_53, 3, 3)
connect _WIRE_52.paa, _T_751
node _T_752 = bits(_WIRE_53, 4, 4)
connect _WIRE_52.pal, _T_752
node _T_753 = bits(_WIRE_53, 5, 5)
connect _WIRE_52.ppp, _T_753
node _T_754 = bits(_WIRE_53, 6, 6)
connect _WIRE_52.pr, _T_754
node _T_755 = bits(_WIRE_53, 7, 7)
connect _WIRE_52.px, _T_755
node _T_756 = bits(_WIRE_53, 8, 8)
connect _WIRE_52.pw, _T_756
node _T_757 = bits(_WIRE_53, 9, 9)
connect _WIRE_52.hr, _T_757
node _T_758 = bits(_WIRE_53, 10, 10)
connect _WIRE_52.hx, _T_758
node _T_759 = bits(_WIRE_53, 11, 11)
connect _WIRE_52.hw, _T_759
node _T_760 = bits(_WIRE_53, 12, 12)
connect _WIRE_52.sr, _T_760
node _T_761 = bits(_WIRE_53, 13, 13)
connect _WIRE_52.sx, _T_761
node _T_762 = bits(_WIRE_53, 14, 14)
connect _WIRE_52.sw, _T_762
node _T_763 = bits(_WIRE_53, 15, 15)
connect _WIRE_52.gf, _T_763
node _T_764 = bits(_WIRE_53, 16, 16)
connect _WIRE_52.pf, _T_764
node _T_765 = bits(_WIRE_53, 17, 17)
connect _WIRE_52.ae_stage2, _T_765
node _T_766 = bits(_WIRE_53, 18, 18)
connect _WIRE_52.ae_final, _T_766
node _T_767 = bits(_WIRE_53, 19, 19)
connect _WIRE_52.ae_ptw, _T_767
node _T_768 = bits(_WIRE_53, 20, 20)
connect _WIRE_52.g, _T_768
node _T_769 = bits(_WIRE_53, 21, 21)
connect _WIRE_52.u, _T_769
node _T_770 = bits(_WIRE_53, 41, 22)
connect _WIRE_52.ppn, _T_770
wire _WIRE_54 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_55 : UInt<42>
connect _WIRE_55, sectored_entries[0][1].data[3]
node _T_771 = bits(_WIRE_55, 0, 0)
connect _WIRE_54.fragmented_superpage, _T_771
node _T_772 = bits(_WIRE_55, 1, 1)
connect _WIRE_54.c, _T_772
node _T_773 = bits(_WIRE_55, 2, 2)
connect _WIRE_54.eff, _T_773
node _T_774 = bits(_WIRE_55, 3, 3)
connect _WIRE_54.paa, _T_774
node _T_775 = bits(_WIRE_55, 4, 4)
connect _WIRE_54.pal, _T_775
node _T_776 = bits(_WIRE_55, 5, 5)
connect _WIRE_54.ppp, _T_776
node _T_777 = bits(_WIRE_55, 6, 6)
connect _WIRE_54.pr, _T_777
node _T_778 = bits(_WIRE_55, 7, 7)
connect _WIRE_54.px, _T_778
node _T_779 = bits(_WIRE_55, 8, 8)
connect _WIRE_54.pw, _T_779
node _T_780 = bits(_WIRE_55, 9, 9)
connect _WIRE_54.hr, _T_780
node _T_781 = bits(_WIRE_55, 10, 10)
connect _WIRE_54.hx, _T_781
node _T_782 = bits(_WIRE_55, 11, 11)
connect _WIRE_54.hw, _T_782
node _T_783 = bits(_WIRE_55, 12, 12)
connect _WIRE_54.sr, _T_783
node _T_784 = bits(_WIRE_55, 13, 13)
connect _WIRE_54.sx, _T_784
node _T_785 = bits(_WIRE_55, 14, 14)
connect _WIRE_54.sw, _T_785
node _T_786 = bits(_WIRE_55, 15, 15)
connect _WIRE_54.gf, _T_786
node _T_787 = bits(_WIRE_55, 16, 16)
connect _WIRE_54.pf, _T_787
node _T_788 = bits(_WIRE_55, 17, 17)
connect _WIRE_54.ae_stage2, _T_788
node _T_789 = bits(_WIRE_55, 18, 18)
connect _WIRE_54.ae_final, _T_789
node _T_790 = bits(_WIRE_55, 19, 19)
connect _WIRE_54.ae_ptw, _T_790
node _T_791 = bits(_WIRE_55, 20, 20)
connect _WIRE_54.g, _T_791
node _T_792 = bits(_WIRE_55, 21, 21)
connect _WIRE_54.u, _T_792
node _T_793 = bits(_WIRE_55, 41, 22)
connect _WIRE_54.ppn, _T_793
node _T_794 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_795 = eq(_WIRE_48.g, UInt<1>(0h0))
node _T_796 = and(_T_794, _T_795)
when _T_796 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
node _T_797 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_798 = eq(_WIRE_50.g, UInt<1>(0h0))
node _T_799 = and(_T_797, _T_798)
when _T_799 :
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
node _T_800 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_801 = eq(_WIRE_52.g, UInt<1>(0h0))
node _T_802 = and(_T_800, _T_801)
when _T_802 :
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
node _T_803 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_804 = eq(_WIRE_54.g, UInt<1>(0h0))
node _T_805 = and(_T_803, _T_804)
when _T_805 :
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
else :
node _T_806 = or(hv_1, hg_1)
wire _WIRE_56 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_57 : UInt<42>
connect _WIRE_57, sectored_entries[0][1].data[0]
node _T_807 = bits(_WIRE_57, 0, 0)
connect _WIRE_56.fragmented_superpage, _T_807
node _T_808 = bits(_WIRE_57, 1, 1)
connect _WIRE_56.c, _T_808
node _T_809 = bits(_WIRE_57, 2, 2)
connect _WIRE_56.eff, _T_809
node _T_810 = bits(_WIRE_57, 3, 3)
connect _WIRE_56.paa, _T_810
node _T_811 = bits(_WIRE_57, 4, 4)
connect _WIRE_56.pal, _T_811
node _T_812 = bits(_WIRE_57, 5, 5)
connect _WIRE_56.ppp, _T_812
node _T_813 = bits(_WIRE_57, 6, 6)
connect _WIRE_56.pr, _T_813
node _T_814 = bits(_WIRE_57, 7, 7)
connect _WIRE_56.px, _T_814
node _T_815 = bits(_WIRE_57, 8, 8)
connect _WIRE_56.pw, _T_815
node _T_816 = bits(_WIRE_57, 9, 9)
connect _WIRE_56.hr, _T_816
node _T_817 = bits(_WIRE_57, 10, 10)
connect _WIRE_56.hx, _T_817
node _T_818 = bits(_WIRE_57, 11, 11)
connect _WIRE_56.hw, _T_818
node _T_819 = bits(_WIRE_57, 12, 12)
connect _WIRE_56.sr, _T_819
node _T_820 = bits(_WIRE_57, 13, 13)
connect _WIRE_56.sx, _T_820
node _T_821 = bits(_WIRE_57, 14, 14)
connect _WIRE_56.sw, _T_821
node _T_822 = bits(_WIRE_57, 15, 15)
connect _WIRE_56.gf, _T_822
node _T_823 = bits(_WIRE_57, 16, 16)
connect _WIRE_56.pf, _T_823
node _T_824 = bits(_WIRE_57, 17, 17)
connect _WIRE_56.ae_stage2, _T_824
node _T_825 = bits(_WIRE_57, 18, 18)
connect _WIRE_56.ae_final, _T_825
node _T_826 = bits(_WIRE_57, 19, 19)
connect _WIRE_56.ae_ptw, _T_826
node _T_827 = bits(_WIRE_57, 20, 20)
connect _WIRE_56.g, _T_827
node _T_828 = bits(_WIRE_57, 21, 21)
connect _WIRE_56.u, _T_828
node _T_829 = bits(_WIRE_57, 41, 22)
connect _WIRE_56.ppn, _T_829
wire _WIRE_58 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_59 : UInt<42>
connect _WIRE_59, sectored_entries[0][1].data[1]
node _T_830 = bits(_WIRE_59, 0, 0)
connect _WIRE_58.fragmented_superpage, _T_830
node _T_831 = bits(_WIRE_59, 1, 1)
connect _WIRE_58.c, _T_831
node _T_832 = bits(_WIRE_59, 2, 2)
connect _WIRE_58.eff, _T_832
node _T_833 = bits(_WIRE_59, 3, 3)
connect _WIRE_58.paa, _T_833
node _T_834 = bits(_WIRE_59, 4, 4)
connect _WIRE_58.pal, _T_834
node _T_835 = bits(_WIRE_59, 5, 5)
connect _WIRE_58.ppp, _T_835
node _T_836 = bits(_WIRE_59, 6, 6)
connect _WIRE_58.pr, _T_836
node _T_837 = bits(_WIRE_59, 7, 7)
connect _WIRE_58.px, _T_837
node _T_838 = bits(_WIRE_59, 8, 8)
connect _WIRE_58.pw, _T_838
node _T_839 = bits(_WIRE_59, 9, 9)
connect _WIRE_58.hr, _T_839
node _T_840 = bits(_WIRE_59, 10, 10)
connect _WIRE_58.hx, _T_840
node _T_841 = bits(_WIRE_59, 11, 11)
connect _WIRE_58.hw, _T_841
node _T_842 = bits(_WIRE_59, 12, 12)
connect _WIRE_58.sr, _T_842
node _T_843 = bits(_WIRE_59, 13, 13)
connect _WIRE_58.sx, _T_843
node _T_844 = bits(_WIRE_59, 14, 14)
connect _WIRE_58.sw, _T_844
node _T_845 = bits(_WIRE_59, 15, 15)
connect _WIRE_58.gf, _T_845
node _T_846 = bits(_WIRE_59, 16, 16)
connect _WIRE_58.pf, _T_846
node _T_847 = bits(_WIRE_59, 17, 17)
connect _WIRE_58.ae_stage2, _T_847
node _T_848 = bits(_WIRE_59, 18, 18)
connect _WIRE_58.ae_final, _T_848
node _T_849 = bits(_WIRE_59, 19, 19)
connect _WIRE_58.ae_ptw, _T_849
node _T_850 = bits(_WIRE_59, 20, 20)
connect _WIRE_58.g, _T_850
node _T_851 = bits(_WIRE_59, 21, 21)
connect _WIRE_58.u, _T_851
node _T_852 = bits(_WIRE_59, 41, 22)
connect _WIRE_58.ppn, _T_852
wire _WIRE_60 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_61 : UInt<42>
connect _WIRE_61, sectored_entries[0][1].data[2]
node _T_853 = bits(_WIRE_61, 0, 0)
connect _WIRE_60.fragmented_superpage, _T_853
node _T_854 = bits(_WIRE_61, 1, 1)
connect _WIRE_60.c, _T_854
node _T_855 = bits(_WIRE_61, 2, 2)
connect _WIRE_60.eff, _T_855
node _T_856 = bits(_WIRE_61, 3, 3)
connect _WIRE_60.paa, _T_856
node _T_857 = bits(_WIRE_61, 4, 4)
connect _WIRE_60.pal, _T_857
node _T_858 = bits(_WIRE_61, 5, 5)
connect _WIRE_60.ppp, _T_858
node _T_859 = bits(_WIRE_61, 6, 6)
connect _WIRE_60.pr, _T_859
node _T_860 = bits(_WIRE_61, 7, 7)
connect _WIRE_60.px, _T_860
node _T_861 = bits(_WIRE_61, 8, 8)
connect _WIRE_60.pw, _T_861
node _T_862 = bits(_WIRE_61, 9, 9)
connect _WIRE_60.hr, _T_862
node _T_863 = bits(_WIRE_61, 10, 10)
connect _WIRE_60.hx, _T_863
node _T_864 = bits(_WIRE_61, 11, 11)
connect _WIRE_60.hw, _T_864
node _T_865 = bits(_WIRE_61, 12, 12)
connect _WIRE_60.sr, _T_865
node _T_866 = bits(_WIRE_61, 13, 13)
connect _WIRE_60.sx, _T_866
node _T_867 = bits(_WIRE_61, 14, 14)
connect _WIRE_60.sw, _T_867
node _T_868 = bits(_WIRE_61, 15, 15)
connect _WIRE_60.gf, _T_868
node _T_869 = bits(_WIRE_61, 16, 16)
connect _WIRE_60.pf, _T_869
node _T_870 = bits(_WIRE_61, 17, 17)
connect _WIRE_60.ae_stage2, _T_870
node _T_871 = bits(_WIRE_61, 18, 18)
connect _WIRE_60.ae_final, _T_871
node _T_872 = bits(_WIRE_61, 19, 19)
connect _WIRE_60.ae_ptw, _T_872
node _T_873 = bits(_WIRE_61, 20, 20)
connect _WIRE_60.g, _T_873
node _T_874 = bits(_WIRE_61, 21, 21)
connect _WIRE_60.u, _T_874
node _T_875 = bits(_WIRE_61, 41, 22)
connect _WIRE_60.ppn, _T_875
wire _WIRE_62 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_63 : UInt<42>
connect _WIRE_63, sectored_entries[0][1].data[3]
node _T_876 = bits(_WIRE_63, 0, 0)
connect _WIRE_62.fragmented_superpage, _T_876
node _T_877 = bits(_WIRE_63, 1, 1)
connect _WIRE_62.c, _T_877
node _T_878 = bits(_WIRE_63, 2, 2)
connect _WIRE_62.eff, _T_878
node _T_879 = bits(_WIRE_63, 3, 3)
connect _WIRE_62.paa, _T_879
node _T_880 = bits(_WIRE_63, 4, 4)
connect _WIRE_62.pal, _T_880
node _T_881 = bits(_WIRE_63, 5, 5)
connect _WIRE_62.ppp, _T_881
node _T_882 = bits(_WIRE_63, 6, 6)
connect _WIRE_62.pr, _T_882
node _T_883 = bits(_WIRE_63, 7, 7)
connect _WIRE_62.px, _T_883
node _T_884 = bits(_WIRE_63, 8, 8)
connect _WIRE_62.pw, _T_884
node _T_885 = bits(_WIRE_63, 9, 9)
connect _WIRE_62.hr, _T_885
node _T_886 = bits(_WIRE_63, 10, 10)
connect _WIRE_62.hx, _T_886
node _T_887 = bits(_WIRE_63, 11, 11)
connect _WIRE_62.hw, _T_887
node _T_888 = bits(_WIRE_63, 12, 12)
connect _WIRE_62.sr, _T_888
node _T_889 = bits(_WIRE_63, 13, 13)
connect _WIRE_62.sx, _T_889
node _T_890 = bits(_WIRE_63, 14, 14)
connect _WIRE_62.sw, _T_890
node _T_891 = bits(_WIRE_63, 15, 15)
connect _WIRE_62.gf, _T_891
node _T_892 = bits(_WIRE_63, 16, 16)
connect _WIRE_62.pf, _T_892
node _T_893 = bits(_WIRE_63, 17, 17)
connect _WIRE_62.ae_stage2, _T_893
node _T_894 = bits(_WIRE_63, 18, 18)
connect _WIRE_62.ae_final, _T_894
node _T_895 = bits(_WIRE_63, 19, 19)
connect _WIRE_62.ae_ptw, _T_895
node _T_896 = bits(_WIRE_63, 20, 20)
connect _WIRE_62.g, _T_896
node _T_897 = bits(_WIRE_63, 21, 21)
connect _WIRE_62.u, _T_897
node _T_898 = bits(_WIRE_63, 41, 22)
connect _WIRE_62.ppn, _T_898
node _T_899 = eq(sectored_entries[0][1].tag_v, _T_806)
when _T_899 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
node _T_900 = eq(sectored_entries[0][1].tag_v, _T_806)
when _T_900 :
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
node _T_901 = eq(sectored_entries[0][1].tag_v, _T_806)
when _T_901 :
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
node _T_902 = eq(sectored_entries[0][1].tag_v, _T_806)
when _T_902 :
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
node hv_2 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_2 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_903 = eq(hg_2, UInt<1>(0h0))
node _T_904 = and(_T_903, io.sfence.bits.rs1)
when _T_904 :
node _T_905 = xor(sectored_entries[0][2].tag_vpn, vpn)
node _T_906 = shr(_T_905, 2)
node _T_907 = eq(_T_906, UInt<1>(0h0))
node _T_908 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_909 = and(_T_907, _T_908)
when _T_909 :
wire _WIRE_64 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_65 : UInt<42>
connect _WIRE_65, sectored_entries[0][2].data[0]
node _T_910 = bits(_WIRE_65, 0, 0)
connect _WIRE_64.fragmented_superpage, _T_910
node _T_911 = bits(_WIRE_65, 1, 1)
connect _WIRE_64.c, _T_911
node _T_912 = bits(_WIRE_65, 2, 2)
connect _WIRE_64.eff, _T_912
node _T_913 = bits(_WIRE_65, 3, 3)
connect _WIRE_64.paa, _T_913
node _T_914 = bits(_WIRE_65, 4, 4)
connect _WIRE_64.pal, _T_914
node _T_915 = bits(_WIRE_65, 5, 5)
connect _WIRE_64.ppp, _T_915
node _T_916 = bits(_WIRE_65, 6, 6)
connect _WIRE_64.pr, _T_916
node _T_917 = bits(_WIRE_65, 7, 7)
connect _WIRE_64.px, _T_917
node _T_918 = bits(_WIRE_65, 8, 8)
connect _WIRE_64.pw, _T_918
node _T_919 = bits(_WIRE_65, 9, 9)
connect _WIRE_64.hr, _T_919
node _T_920 = bits(_WIRE_65, 10, 10)
connect _WIRE_64.hx, _T_920
node _T_921 = bits(_WIRE_65, 11, 11)
connect _WIRE_64.hw, _T_921
node _T_922 = bits(_WIRE_65, 12, 12)
connect _WIRE_64.sr, _T_922
node _T_923 = bits(_WIRE_65, 13, 13)
connect _WIRE_64.sx, _T_923
node _T_924 = bits(_WIRE_65, 14, 14)
connect _WIRE_64.sw, _T_924
node _T_925 = bits(_WIRE_65, 15, 15)
connect _WIRE_64.gf, _T_925
node _T_926 = bits(_WIRE_65, 16, 16)
connect _WIRE_64.pf, _T_926
node _T_927 = bits(_WIRE_65, 17, 17)
connect _WIRE_64.ae_stage2, _T_927
node _T_928 = bits(_WIRE_65, 18, 18)
connect _WIRE_64.ae_final, _T_928
node _T_929 = bits(_WIRE_65, 19, 19)
connect _WIRE_64.ae_ptw, _T_929
node _T_930 = bits(_WIRE_65, 20, 20)
connect _WIRE_64.g, _T_930
node _T_931 = bits(_WIRE_65, 21, 21)
connect _WIRE_64.u, _T_931
node _T_932 = bits(_WIRE_65, 41, 22)
connect _WIRE_64.ppn, _T_932
wire _WIRE_66 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_67 : UInt<42>
connect _WIRE_67, sectored_entries[0][2].data[1]
node _T_933 = bits(_WIRE_67, 0, 0)
connect _WIRE_66.fragmented_superpage, _T_933
node _T_934 = bits(_WIRE_67, 1, 1)
connect _WIRE_66.c, _T_934
node _T_935 = bits(_WIRE_67, 2, 2)
connect _WIRE_66.eff, _T_935
node _T_936 = bits(_WIRE_67, 3, 3)
connect _WIRE_66.paa, _T_936
node _T_937 = bits(_WIRE_67, 4, 4)
connect _WIRE_66.pal, _T_937
node _T_938 = bits(_WIRE_67, 5, 5)
connect _WIRE_66.ppp, _T_938
node _T_939 = bits(_WIRE_67, 6, 6)
connect _WIRE_66.pr, _T_939
node _T_940 = bits(_WIRE_67, 7, 7)
connect _WIRE_66.px, _T_940
node _T_941 = bits(_WIRE_67, 8, 8)
connect _WIRE_66.pw, _T_941
node _T_942 = bits(_WIRE_67, 9, 9)
connect _WIRE_66.hr, _T_942
node _T_943 = bits(_WIRE_67, 10, 10)
connect _WIRE_66.hx, _T_943
node _T_944 = bits(_WIRE_67, 11, 11)
connect _WIRE_66.hw, _T_944
node _T_945 = bits(_WIRE_67, 12, 12)
connect _WIRE_66.sr, _T_945
node _T_946 = bits(_WIRE_67, 13, 13)
connect _WIRE_66.sx, _T_946
node _T_947 = bits(_WIRE_67, 14, 14)
connect _WIRE_66.sw, _T_947
node _T_948 = bits(_WIRE_67, 15, 15)
connect _WIRE_66.gf, _T_948
node _T_949 = bits(_WIRE_67, 16, 16)
connect _WIRE_66.pf, _T_949
node _T_950 = bits(_WIRE_67, 17, 17)
connect _WIRE_66.ae_stage2, _T_950
node _T_951 = bits(_WIRE_67, 18, 18)
connect _WIRE_66.ae_final, _T_951
node _T_952 = bits(_WIRE_67, 19, 19)
connect _WIRE_66.ae_ptw, _T_952
node _T_953 = bits(_WIRE_67, 20, 20)
connect _WIRE_66.g, _T_953
node _T_954 = bits(_WIRE_67, 21, 21)
connect _WIRE_66.u, _T_954
node _T_955 = bits(_WIRE_67, 41, 22)
connect _WIRE_66.ppn, _T_955
wire _WIRE_68 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_69 : UInt<42>
connect _WIRE_69, sectored_entries[0][2].data[2]
node _T_956 = bits(_WIRE_69, 0, 0)
connect _WIRE_68.fragmented_superpage, _T_956
node _T_957 = bits(_WIRE_69, 1, 1)
connect _WIRE_68.c, _T_957
node _T_958 = bits(_WIRE_69, 2, 2)
connect _WIRE_68.eff, _T_958
node _T_959 = bits(_WIRE_69, 3, 3)
connect _WIRE_68.paa, _T_959
node _T_960 = bits(_WIRE_69, 4, 4)
connect _WIRE_68.pal, _T_960
node _T_961 = bits(_WIRE_69, 5, 5)
connect _WIRE_68.ppp, _T_961
node _T_962 = bits(_WIRE_69, 6, 6)
connect _WIRE_68.pr, _T_962
node _T_963 = bits(_WIRE_69, 7, 7)
connect _WIRE_68.px, _T_963
node _T_964 = bits(_WIRE_69, 8, 8)
connect _WIRE_68.pw, _T_964
node _T_965 = bits(_WIRE_69, 9, 9)
connect _WIRE_68.hr, _T_965
node _T_966 = bits(_WIRE_69, 10, 10)
connect _WIRE_68.hx, _T_966
node _T_967 = bits(_WIRE_69, 11, 11)
connect _WIRE_68.hw, _T_967
node _T_968 = bits(_WIRE_69, 12, 12)
connect _WIRE_68.sr, _T_968
node _T_969 = bits(_WIRE_69, 13, 13)
connect _WIRE_68.sx, _T_969
node _T_970 = bits(_WIRE_69, 14, 14)
connect _WIRE_68.sw, _T_970
node _T_971 = bits(_WIRE_69, 15, 15)
connect _WIRE_68.gf, _T_971
node _T_972 = bits(_WIRE_69, 16, 16)
connect _WIRE_68.pf, _T_972
node _T_973 = bits(_WIRE_69, 17, 17)
connect _WIRE_68.ae_stage2, _T_973
node _T_974 = bits(_WIRE_69, 18, 18)
connect _WIRE_68.ae_final, _T_974
node _T_975 = bits(_WIRE_69, 19, 19)
connect _WIRE_68.ae_ptw, _T_975
node _T_976 = bits(_WIRE_69, 20, 20)
connect _WIRE_68.g, _T_976
node _T_977 = bits(_WIRE_69, 21, 21)
connect _WIRE_68.u, _T_977
node _T_978 = bits(_WIRE_69, 41, 22)
connect _WIRE_68.ppn, _T_978
wire _WIRE_70 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_71 : UInt<42>
connect _WIRE_71, sectored_entries[0][2].data[3]
node _T_979 = bits(_WIRE_71, 0, 0)
connect _WIRE_70.fragmented_superpage, _T_979
node _T_980 = bits(_WIRE_71, 1, 1)
connect _WIRE_70.c, _T_980
node _T_981 = bits(_WIRE_71, 2, 2)
connect _WIRE_70.eff, _T_981
node _T_982 = bits(_WIRE_71, 3, 3)
connect _WIRE_70.paa, _T_982
node _T_983 = bits(_WIRE_71, 4, 4)
connect _WIRE_70.pal, _T_983
node _T_984 = bits(_WIRE_71, 5, 5)
connect _WIRE_70.ppp, _T_984
node _T_985 = bits(_WIRE_71, 6, 6)
connect _WIRE_70.pr, _T_985
node _T_986 = bits(_WIRE_71, 7, 7)
connect _WIRE_70.px, _T_986
node _T_987 = bits(_WIRE_71, 8, 8)
connect _WIRE_70.pw, _T_987
node _T_988 = bits(_WIRE_71, 9, 9)
connect _WIRE_70.hr, _T_988
node _T_989 = bits(_WIRE_71, 10, 10)
connect _WIRE_70.hx, _T_989
node _T_990 = bits(_WIRE_71, 11, 11)
connect _WIRE_70.hw, _T_990
node _T_991 = bits(_WIRE_71, 12, 12)
connect _WIRE_70.sr, _T_991
node _T_992 = bits(_WIRE_71, 13, 13)
connect _WIRE_70.sx, _T_992
node _T_993 = bits(_WIRE_71, 14, 14)
connect _WIRE_70.sw, _T_993
node _T_994 = bits(_WIRE_71, 15, 15)
connect _WIRE_70.gf, _T_994
node _T_995 = bits(_WIRE_71, 16, 16)
connect _WIRE_70.pf, _T_995
node _T_996 = bits(_WIRE_71, 17, 17)
connect _WIRE_70.ae_stage2, _T_996
node _T_997 = bits(_WIRE_71, 18, 18)
connect _WIRE_70.ae_final, _T_997
node _T_998 = bits(_WIRE_71, 19, 19)
connect _WIRE_70.ae_ptw, _T_998
node _T_999 = bits(_WIRE_71, 20, 20)
connect _WIRE_70.g, _T_999
node _T_1000 = bits(_WIRE_71, 21, 21)
connect _WIRE_70.u, _T_1000
node _T_1001 = bits(_WIRE_71, 41, 22)
connect _WIRE_70.ppn, _T_1001
node _T_1002 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1003 = bits(vpn, 1, 0)
node _T_1004 = eq(UInt<1>(0h0), _T_1003)
node _T_1005 = and(_T_1002, _T_1004)
when _T_1005 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
node _T_1006 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1007 = bits(vpn, 1, 0)
node _T_1008 = eq(UInt<1>(0h1), _T_1007)
node _T_1009 = and(_T_1006, _T_1008)
when _T_1009 :
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
node _T_1010 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1011 = bits(vpn, 1, 0)
node _T_1012 = eq(UInt<2>(0h2), _T_1011)
node _T_1013 = and(_T_1010, _T_1012)
when _T_1013 :
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
node _T_1014 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1015 = bits(vpn, 1, 0)
node _T_1016 = eq(UInt<2>(0h3), _T_1015)
node _T_1017 = and(_T_1014, _T_1016)
when _T_1017 :
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
node _T_1018 = xor(sectored_entries[0][2].tag_vpn, vpn)
node _T_1019 = shr(_T_1018, 18)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
wire _WIRE_72 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_73 : UInt<42>
connect _WIRE_73, sectored_entries[0][2].data[0]
node _T_1021 = bits(_WIRE_73, 0, 0)
connect _WIRE_72.fragmented_superpage, _T_1021
node _T_1022 = bits(_WIRE_73, 1, 1)
connect _WIRE_72.c, _T_1022
node _T_1023 = bits(_WIRE_73, 2, 2)
connect _WIRE_72.eff, _T_1023
node _T_1024 = bits(_WIRE_73, 3, 3)
connect _WIRE_72.paa, _T_1024
node _T_1025 = bits(_WIRE_73, 4, 4)
connect _WIRE_72.pal, _T_1025
node _T_1026 = bits(_WIRE_73, 5, 5)
connect _WIRE_72.ppp, _T_1026
node _T_1027 = bits(_WIRE_73, 6, 6)
connect _WIRE_72.pr, _T_1027
node _T_1028 = bits(_WIRE_73, 7, 7)
connect _WIRE_72.px, _T_1028
node _T_1029 = bits(_WIRE_73, 8, 8)
connect _WIRE_72.pw, _T_1029
node _T_1030 = bits(_WIRE_73, 9, 9)
connect _WIRE_72.hr, _T_1030
node _T_1031 = bits(_WIRE_73, 10, 10)
connect _WIRE_72.hx, _T_1031
node _T_1032 = bits(_WIRE_73, 11, 11)
connect _WIRE_72.hw, _T_1032
node _T_1033 = bits(_WIRE_73, 12, 12)
connect _WIRE_72.sr, _T_1033
node _T_1034 = bits(_WIRE_73, 13, 13)
connect _WIRE_72.sx, _T_1034
node _T_1035 = bits(_WIRE_73, 14, 14)
connect _WIRE_72.sw, _T_1035
node _T_1036 = bits(_WIRE_73, 15, 15)
connect _WIRE_72.gf, _T_1036
node _T_1037 = bits(_WIRE_73, 16, 16)
connect _WIRE_72.pf, _T_1037
node _T_1038 = bits(_WIRE_73, 17, 17)
connect _WIRE_72.ae_stage2, _T_1038
node _T_1039 = bits(_WIRE_73, 18, 18)
connect _WIRE_72.ae_final, _T_1039
node _T_1040 = bits(_WIRE_73, 19, 19)
connect _WIRE_72.ae_ptw, _T_1040
node _T_1041 = bits(_WIRE_73, 20, 20)
connect _WIRE_72.g, _T_1041
node _T_1042 = bits(_WIRE_73, 21, 21)
connect _WIRE_72.u, _T_1042
node _T_1043 = bits(_WIRE_73, 41, 22)
connect _WIRE_72.ppn, _T_1043
wire _WIRE_74 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_75 : UInt<42>
connect _WIRE_75, sectored_entries[0][2].data[1]
node _T_1044 = bits(_WIRE_75, 0, 0)
connect _WIRE_74.fragmented_superpage, _T_1044
node _T_1045 = bits(_WIRE_75, 1, 1)
connect _WIRE_74.c, _T_1045
node _T_1046 = bits(_WIRE_75, 2, 2)
connect _WIRE_74.eff, _T_1046
node _T_1047 = bits(_WIRE_75, 3, 3)
connect _WIRE_74.paa, _T_1047
node _T_1048 = bits(_WIRE_75, 4, 4)
connect _WIRE_74.pal, _T_1048
node _T_1049 = bits(_WIRE_75, 5, 5)
connect _WIRE_74.ppp, _T_1049
node _T_1050 = bits(_WIRE_75, 6, 6)
connect _WIRE_74.pr, _T_1050
node _T_1051 = bits(_WIRE_75, 7, 7)
connect _WIRE_74.px, _T_1051
node _T_1052 = bits(_WIRE_75, 8, 8)
connect _WIRE_74.pw, _T_1052
node _T_1053 = bits(_WIRE_75, 9, 9)
connect _WIRE_74.hr, _T_1053
node _T_1054 = bits(_WIRE_75, 10, 10)
connect _WIRE_74.hx, _T_1054
node _T_1055 = bits(_WIRE_75, 11, 11)
connect _WIRE_74.hw, _T_1055
node _T_1056 = bits(_WIRE_75, 12, 12)
connect _WIRE_74.sr, _T_1056
node _T_1057 = bits(_WIRE_75, 13, 13)
connect _WIRE_74.sx, _T_1057
node _T_1058 = bits(_WIRE_75, 14, 14)
connect _WIRE_74.sw, _T_1058
node _T_1059 = bits(_WIRE_75, 15, 15)
connect _WIRE_74.gf, _T_1059
node _T_1060 = bits(_WIRE_75, 16, 16)
connect _WIRE_74.pf, _T_1060
node _T_1061 = bits(_WIRE_75, 17, 17)
connect _WIRE_74.ae_stage2, _T_1061
node _T_1062 = bits(_WIRE_75, 18, 18)
connect _WIRE_74.ae_final, _T_1062
node _T_1063 = bits(_WIRE_75, 19, 19)
connect _WIRE_74.ae_ptw, _T_1063
node _T_1064 = bits(_WIRE_75, 20, 20)
connect _WIRE_74.g, _T_1064
node _T_1065 = bits(_WIRE_75, 21, 21)
connect _WIRE_74.u, _T_1065
node _T_1066 = bits(_WIRE_75, 41, 22)
connect _WIRE_74.ppn, _T_1066
wire _WIRE_76 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_77 : UInt<42>
connect _WIRE_77, sectored_entries[0][2].data[2]
node _T_1067 = bits(_WIRE_77, 0, 0)
connect _WIRE_76.fragmented_superpage, _T_1067
node _T_1068 = bits(_WIRE_77, 1, 1)
connect _WIRE_76.c, _T_1068
node _T_1069 = bits(_WIRE_77, 2, 2)
connect _WIRE_76.eff, _T_1069
node _T_1070 = bits(_WIRE_77, 3, 3)
connect _WIRE_76.paa, _T_1070
node _T_1071 = bits(_WIRE_77, 4, 4)
connect _WIRE_76.pal, _T_1071
node _T_1072 = bits(_WIRE_77, 5, 5)
connect _WIRE_76.ppp, _T_1072
node _T_1073 = bits(_WIRE_77, 6, 6)
connect _WIRE_76.pr, _T_1073
node _T_1074 = bits(_WIRE_77, 7, 7)
connect _WIRE_76.px, _T_1074
node _T_1075 = bits(_WIRE_77, 8, 8)
connect _WIRE_76.pw, _T_1075
node _T_1076 = bits(_WIRE_77, 9, 9)
connect _WIRE_76.hr, _T_1076
node _T_1077 = bits(_WIRE_77, 10, 10)
connect _WIRE_76.hx, _T_1077
node _T_1078 = bits(_WIRE_77, 11, 11)
connect _WIRE_76.hw, _T_1078
node _T_1079 = bits(_WIRE_77, 12, 12)
connect _WIRE_76.sr, _T_1079
node _T_1080 = bits(_WIRE_77, 13, 13)
connect _WIRE_76.sx, _T_1080
node _T_1081 = bits(_WIRE_77, 14, 14)
connect _WIRE_76.sw, _T_1081
node _T_1082 = bits(_WIRE_77, 15, 15)
connect _WIRE_76.gf, _T_1082
node _T_1083 = bits(_WIRE_77, 16, 16)
connect _WIRE_76.pf, _T_1083
node _T_1084 = bits(_WIRE_77, 17, 17)
connect _WIRE_76.ae_stage2, _T_1084
node _T_1085 = bits(_WIRE_77, 18, 18)
connect _WIRE_76.ae_final, _T_1085
node _T_1086 = bits(_WIRE_77, 19, 19)
connect _WIRE_76.ae_ptw, _T_1086
node _T_1087 = bits(_WIRE_77, 20, 20)
connect _WIRE_76.g, _T_1087
node _T_1088 = bits(_WIRE_77, 21, 21)
connect _WIRE_76.u, _T_1088
node _T_1089 = bits(_WIRE_77, 41, 22)
connect _WIRE_76.ppn, _T_1089
wire _WIRE_78 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_79 : UInt<42>
connect _WIRE_79, sectored_entries[0][2].data[3]
node _T_1090 = bits(_WIRE_79, 0, 0)
connect _WIRE_78.fragmented_superpage, _T_1090
node _T_1091 = bits(_WIRE_79, 1, 1)
connect _WIRE_78.c, _T_1091
node _T_1092 = bits(_WIRE_79, 2, 2)
connect _WIRE_78.eff, _T_1092
node _T_1093 = bits(_WIRE_79, 3, 3)
connect _WIRE_78.paa, _T_1093
node _T_1094 = bits(_WIRE_79, 4, 4)
connect _WIRE_78.pal, _T_1094
node _T_1095 = bits(_WIRE_79, 5, 5)
connect _WIRE_78.ppp, _T_1095
node _T_1096 = bits(_WIRE_79, 6, 6)
connect _WIRE_78.pr, _T_1096
node _T_1097 = bits(_WIRE_79, 7, 7)
connect _WIRE_78.px, _T_1097
node _T_1098 = bits(_WIRE_79, 8, 8)
connect _WIRE_78.pw, _T_1098
node _T_1099 = bits(_WIRE_79, 9, 9)
connect _WIRE_78.hr, _T_1099
node _T_1100 = bits(_WIRE_79, 10, 10)
connect _WIRE_78.hx, _T_1100
node _T_1101 = bits(_WIRE_79, 11, 11)
connect _WIRE_78.hw, _T_1101
node _T_1102 = bits(_WIRE_79, 12, 12)
connect _WIRE_78.sr, _T_1102
node _T_1103 = bits(_WIRE_79, 13, 13)
connect _WIRE_78.sx, _T_1103
node _T_1104 = bits(_WIRE_79, 14, 14)
connect _WIRE_78.sw, _T_1104
node _T_1105 = bits(_WIRE_79, 15, 15)
connect _WIRE_78.gf, _T_1105
node _T_1106 = bits(_WIRE_79, 16, 16)
connect _WIRE_78.pf, _T_1106
node _T_1107 = bits(_WIRE_79, 17, 17)
connect _WIRE_78.ae_stage2, _T_1107
node _T_1108 = bits(_WIRE_79, 18, 18)
connect _WIRE_78.ae_final, _T_1108
node _T_1109 = bits(_WIRE_79, 19, 19)
connect _WIRE_78.ae_ptw, _T_1109
node _T_1110 = bits(_WIRE_79, 20, 20)
connect _WIRE_78.g, _T_1110
node _T_1111 = bits(_WIRE_79, 21, 21)
connect _WIRE_78.u, _T_1111
node _T_1112 = bits(_WIRE_79, 41, 22)
connect _WIRE_78.ppn, _T_1112
node _T_1113 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1114 = and(_T_1113, _WIRE_72.fragmented_superpage)
when _T_1114 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
node _T_1115 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1116 = and(_T_1115, _WIRE_74.fragmented_superpage)
when _T_1116 :
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
node _T_1117 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1118 = and(_T_1117, _WIRE_76.fragmented_superpage)
when _T_1118 :
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
node _T_1119 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1120 = and(_T_1119, _WIRE_78.fragmented_superpage)
when _T_1120 :
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
else :
node _T_1121 = eq(hg_2, UInt<1>(0h0))
node _T_1122 = and(_T_1121, io.sfence.bits.rs2)
when _T_1122 :
wire _WIRE_80 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_81 : UInt<42>
connect _WIRE_81, sectored_entries[0][2].data[0]
node _T_1123 = bits(_WIRE_81, 0, 0)
connect _WIRE_80.fragmented_superpage, _T_1123
node _T_1124 = bits(_WIRE_81, 1, 1)
connect _WIRE_80.c, _T_1124
node _T_1125 = bits(_WIRE_81, 2, 2)
connect _WIRE_80.eff, _T_1125
node _T_1126 = bits(_WIRE_81, 3, 3)
connect _WIRE_80.paa, _T_1126
node _T_1127 = bits(_WIRE_81, 4, 4)
connect _WIRE_80.pal, _T_1127
node _T_1128 = bits(_WIRE_81, 5, 5)
connect _WIRE_80.ppp, _T_1128
node _T_1129 = bits(_WIRE_81, 6, 6)
connect _WIRE_80.pr, _T_1129
node _T_1130 = bits(_WIRE_81, 7, 7)
connect _WIRE_80.px, _T_1130
node _T_1131 = bits(_WIRE_81, 8, 8)
connect _WIRE_80.pw, _T_1131
node _T_1132 = bits(_WIRE_81, 9, 9)
connect _WIRE_80.hr, _T_1132
node _T_1133 = bits(_WIRE_81, 10, 10)
connect _WIRE_80.hx, _T_1133
node _T_1134 = bits(_WIRE_81, 11, 11)
connect _WIRE_80.hw, _T_1134
node _T_1135 = bits(_WIRE_81, 12, 12)
connect _WIRE_80.sr, _T_1135
node _T_1136 = bits(_WIRE_81, 13, 13)
connect _WIRE_80.sx, _T_1136
node _T_1137 = bits(_WIRE_81, 14, 14)
connect _WIRE_80.sw, _T_1137
node _T_1138 = bits(_WIRE_81, 15, 15)
connect _WIRE_80.gf, _T_1138
node _T_1139 = bits(_WIRE_81, 16, 16)
connect _WIRE_80.pf, _T_1139
node _T_1140 = bits(_WIRE_81, 17, 17)
connect _WIRE_80.ae_stage2, _T_1140
node _T_1141 = bits(_WIRE_81, 18, 18)
connect _WIRE_80.ae_final, _T_1141
node _T_1142 = bits(_WIRE_81, 19, 19)
connect _WIRE_80.ae_ptw, _T_1142
node _T_1143 = bits(_WIRE_81, 20, 20)
connect _WIRE_80.g, _T_1143
node _T_1144 = bits(_WIRE_81, 21, 21)
connect _WIRE_80.u, _T_1144
node _T_1145 = bits(_WIRE_81, 41, 22)
connect _WIRE_80.ppn, _T_1145
wire _WIRE_82 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_83 : UInt<42>
connect _WIRE_83, sectored_entries[0][2].data[1]
node _T_1146 = bits(_WIRE_83, 0, 0)
connect _WIRE_82.fragmented_superpage, _T_1146
node _T_1147 = bits(_WIRE_83, 1, 1)
connect _WIRE_82.c, _T_1147
node _T_1148 = bits(_WIRE_83, 2, 2)
connect _WIRE_82.eff, _T_1148
node _T_1149 = bits(_WIRE_83, 3, 3)
connect _WIRE_82.paa, _T_1149
node _T_1150 = bits(_WIRE_83, 4, 4)
connect _WIRE_82.pal, _T_1150
node _T_1151 = bits(_WIRE_83, 5, 5)
connect _WIRE_82.ppp, _T_1151
node _T_1152 = bits(_WIRE_83, 6, 6)
connect _WIRE_82.pr, _T_1152
node _T_1153 = bits(_WIRE_83, 7, 7)
connect _WIRE_82.px, _T_1153
node _T_1154 = bits(_WIRE_83, 8, 8)
connect _WIRE_82.pw, _T_1154
node _T_1155 = bits(_WIRE_83, 9, 9)
connect _WIRE_82.hr, _T_1155
node _T_1156 = bits(_WIRE_83, 10, 10)
connect _WIRE_82.hx, _T_1156
node _T_1157 = bits(_WIRE_83, 11, 11)
connect _WIRE_82.hw, _T_1157
node _T_1158 = bits(_WIRE_83, 12, 12)
connect _WIRE_82.sr, _T_1158
node _T_1159 = bits(_WIRE_83, 13, 13)
connect _WIRE_82.sx, _T_1159
node _T_1160 = bits(_WIRE_83, 14, 14)
connect _WIRE_82.sw, _T_1160
node _T_1161 = bits(_WIRE_83, 15, 15)
connect _WIRE_82.gf, _T_1161
node _T_1162 = bits(_WIRE_83, 16, 16)
connect _WIRE_82.pf, _T_1162
node _T_1163 = bits(_WIRE_83, 17, 17)
connect _WIRE_82.ae_stage2, _T_1163
node _T_1164 = bits(_WIRE_83, 18, 18)
connect _WIRE_82.ae_final, _T_1164
node _T_1165 = bits(_WIRE_83, 19, 19)
connect _WIRE_82.ae_ptw, _T_1165
node _T_1166 = bits(_WIRE_83, 20, 20)
connect _WIRE_82.g, _T_1166
node _T_1167 = bits(_WIRE_83, 21, 21)
connect _WIRE_82.u, _T_1167
node _T_1168 = bits(_WIRE_83, 41, 22)
connect _WIRE_82.ppn, _T_1168
wire _WIRE_84 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_85 : UInt<42>
connect _WIRE_85, sectored_entries[0][2].data[2]
node _T_1169 = bits(_WIRE_85, 0, 0)
connect _WIRE_84.fragmented_superpage, _T_1169
node _T_1170 = bits(_WIRE_85, 1, 1)
connect _WIRE_84.c, _T_1170
node _T_1171 = bits(_WIRE_85, 2, 2)
connect _WIRE_84.eff, _T_1171
node _T_1172 = bits(_WIRE_85, 3, 3)
connect _WIRE_84.paa, _T_1172
node _T_1173 = bits(_WIRE_85, 4, 4)
connect _WIRE_84.pal, _T_1173
node _T_1174 = bits(_WIRE_85, 5, 5)
connect _WIRE_84.ppp, _T_1174
node _T_1175 = bits(_WIRE_85, 6, 6)
connect _WIRE_84.pr, _T_1175
node _T_1176 = bits(_WIRE_85, 7, 7)
connect _WIRE_84.px, _T_1176
node _T_1177 = bits(_WIRE_85, 8, 8)
connect _WIRE_84.pw, _T_1177
node _T_1178 = bits(_WIRE_85, 9, 9)
connect _WIRE_84.hr, _T_1178
node _T_1179 = bits(_WIRE_85, 10, 10)
connect _WIRE_84.hx, _T_1179
node _T_1180 = bits(_WIRE_85, 11, 11)
connect _WIRE_84.hw, _T_1180
node _T_1181 = bits(_WIRE_85, 12, 12)
connect _WIRE_84.sr, _T_1181
node _T_1182 = bits(_WIRE_85, 13, 13)
connect _WIRE_84.sx, _T_1182
node _T_1183 = bits(_WIRE_85, 14, 14)
connect _WIRE_84.sw, _T_1183
node _T_1184 = bits(_WIRE_85, 15, 15)
connect _WIRE_84.gf, _T_1184
node _T_1185 = bits(_WIRE_85, 16, 16)
connect _WIRE_84.pf, _T_1185
node _T_1186 = bits(_WIRE_85, 17, 17)
connect _WIRE_84.ae_stage2, _T_1186
node _T_1187 = bits(_WIRE_85, 18, 18)
connect _WIRE_84.ae_final, _T_1187
node _T_1188 = bits(_WIRE_85, 19, 19)
connect _WIRE_84.ae_ptw, _T_1188
node _T_1189 = bits(_WIRE_85, 20, 20)
connect _WIRE_84.g, _T_1189
node _T_1190 = bits(_WIRE_85, 21, 21)
connect _WIRE_84.u, _T_1190
node _T_1191 = bits(_WIRE_85, 41, 22)
connect _WIRE_84.ppn, _T_1191
wire _WIRE_86 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_87 : UInt<42>
connect _WIRE_87, sectored_entries[0][2].data[3]
node _T_1192 = bits(_WIRE_87, 0, 0)
connect _WIRE_86.fragmented_superpage, _T_1192
node _T_1193 = bits(_WIRE_87, 1, 1)
connect _WIRE_86.c, _T_1193
node _T_1194 = bits(_WIRE_87, 2, 2)
connect _WIRE_86.eff, _T_1194
node _T_1195 = bits(_WIRE_87, 3, 3)
connect _WIRE_86.paa, _T_1195
node _T_1196 = bits(_WIRE_87, 4, 4)
connect _WIRE_86.pal, _T_1196
node _T_1197 = bits(_WIRE_87, 5, 5)
connect _WIRE_86.ppp, _T_1197
node _T_1198 = bits(_WIRE_87, 6, 6)
connect _WIRE_86.pr, _T_1198
node _T_1199 = bits(_WIRE_87, 7, 7)
connect _WIRE_86.px, _T_1199
node _T_1200 = bits(_WIRE_87, 8, 8)
connect _WIRE_86.pw, _T_1200
node _T_1201 = bits(_WIRE_87, 9, 9)
connect _WIRE_86.hr, _T_1201
node _T_1202 = bits(_WIRE_87, 10, 10)
connect _WIRE_86.hx, _T_1202
node _T_1203 = bits(_WIRE_87, 11, 11)
connect _WIRE_86.hw, _T_1203
node _T_1204 = bits(_WIRE_87, 12, 12)
connect _WIRE_86.sr, _T_1204
node _T_1205 = bits(_WIRE_87, 13, 13)
connect _WIRE_86.sx, _T_1205
node _T_1206 = bits(_WIRE_87, 14, 14)
connect _WIRE_86.sw, _T_1206
node _T_1207 = bits(_WIRE_87, 15, 15)
connect _WIRE_86.gf, _T_1207
node _T_1208 = bits(_WIRE_87, 16, 16)
connect _WIRE_86.pf, _T_1208
node _T_1209 = bits(_WIRE_87, 17, 17)
connect _WIRE_86.ae_stage2, _T_1209
node _T_1210 = bits(_WIRE_87, 18, 18)
connect _WIRE_86.ae_final, _T_1210
node _T_1211 = bits(_WIRE_87, 19, 19)
connect _WIRE_86.ae_ptw, _T_1211
node _T_1212 = bits(_WIRE_87, 20, 20)
connect _WIRE_86.g, _T_1212
node _T_1213 = bits(_WIRE_87, 21, 21)
connect _WIRE_86.u, _T_1213
node _T_1214 = bits(_WIRE_87, 41, 22)
connect _WIRE_86.ppn, _T_1214
node _T_1215 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1216 = eq(_WIRE_80.g, UInt<1>(0h0))
node _T_1217 = and(_T_1215, _T_1216)
when _T_1217 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
node _T_1218 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1219 = eq(_WIRE_82.g, UInt<1>(0h0))
node _T_1220 = and(_T_1218, _T_1219)
when _T_1220 :
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
node _T_1221 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1222 = eq(_WIRE_84.g, UInt<1>(0h0))
node _T_1223 = and(_T_1221, _T_1222)
when _T_1223 :
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
node _T_1224 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1225 = eq(_WIRE_86.g, UInt<1>(0h0))
node _T_1226 = and(_T_1224, _T_1225)
when _T_1226 :
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
else :
node _T_1227 = or(hv_2, hg_2)
wire _WIRE_88 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_89 : UInt<42>
connect _WIRE_89, sectored_entries[0][2].data[0]
node _T_1228 = bits(_WIRE_89, 0, 0)
connect _WIRE_88.fragmented_superpage, _T_1228
node _T_1229 = bits(_WIRE_89, 1, 1)
connect _WIRE_88.c, _T_1229
node _T_1230 = bits(_WIRE_89, 2, 2)
connect _WIRE_88.eff, _T_1230
node _T_1231 = bits(_WIRE_89, 3, 3)
connect _WIRE_88.paa, _T_1231
node _T_1232 = bits(_WIRE_89, 4, 4)
connect _WIRE_88.pal, _T_1232
node _T_1233 = bits(_WIRE_89, 5, 5)
connect _WIRE_88.ppp, _T_1233
node _T_1234 = bits(_WIRE_89, 6, 6)
connect _WIRE_88.pr, _T_1234
node _T_1235 = bits(_WIRE_89, 7, 7)
connect _WIRE_88.px, _T_1235
node _T_1236 = bits(_WIRE_89, 8, 8)
connect _WIRE_88.pw, _T_1236
node _T_1237 = bits(_WIRE_89, 9, 9)
connect _WIRE_88.hr, _T_1237
node _T_1238 = bits(_WIRE_89, 10, 10)
connect _WIRE_88.hx, _T_1238
node _T_1239 = bits(_WIRE_89, 11, 11)
connect _WIRE_88.hw, _T_1239
node _T_1240 = bits(_WIRE_89, 12, 12)
connect _WIRE_88.sr, _T_1240
node _T_1241 = bits(_WIRE_89, 13, 13)
connect _WIRE_88.sx, _T_1241
node _T_1242 = bits(_WIRE_89, 14, 14)
connect _WIRE_88.sw, _T_1242
node _T_1243 = bits(_WIRE_89, 15, 15)
connect _WIRE_88.gf, _T_1243
node _T_1244 = bits(_WIRE_89, 16, 16)
connect _WIRE_88.pf, _T_1244
node _T_1245 = bits(_WIRE_89, 17, 17)
connect _WIRE_88.ae_stage2, _T_1245
node _T_1246 = bits(_WIRE_89, 18, 18)
connect _WIRE_88.ae_final, _T_1246
node _T_1247 = bits(_WIRE_89, 19, 19)
connect _WIRE_88.ae_ptw, _T_1247
node _T_1248 = bits(_WIRE_89, 20, 20)
connect _WIRE_88.g, _T_1248
node _T_1249 = bits(_WIRE_89, 21, 21)
connect _WIRE_88.u, _T_1249
node _T_1250 = bits(_WIRE_89, 41, 22)
connect _WIRE_88.ppn, _T_1250
wire _WIRE_90 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_91 : UInt<42>
connect _WIRE_91, sectored_entries[0][2].data[1]
node _T_1251 = bits(_WIRE_91, 0, 0)
connect _WIRE_90.fragmented_superpage, _T_1251
node _T_1252 = bits(_WIRE_91, 1, 1)
connect _WIRE_90.c, _T_1252
node _T_1253 = bits(_WIRE_91, 2, 2)
connect _WIRE_90.eff, _T_1253
node _T_1254 = bits(_WIRE_91, 3, 3)
connect _WIRE_90.paa, _T_1254
node _T_1255 = bits(_WIRE_91, 4, 4)
connect _WIRE_90.pal, _T_1255
node _T_1256 = bits(_WIRE_91, 5, 5)
connect _WIRE_90.ppp, _T_1256
node _T_1257 = bits(_WIRE_91, 6, 6)
connect _WIRE_90.pr, _T_1257
node _T_1258 = bits(_WIRE_91, 7, 7)
connect _WIRE_90.px, _T_1258
node _T_1259 = bits(_WIRE_91, 8, 8)
connect _WIRE_90.pw, _T_1259
node _T_1260 = bits(_WIRE_91, 9, 9)
connect _WIRE_90.hr, _T_1260
node _T_1261 = bits(_WIRE_91, 10, 10)
connect _WIRE_90.hx, _T_1261
node _T_1262 = bits(_WIRE_91, 11, 11)
connect _WIRE_90.hw, _T_1262
node _T_1263 = bits(_WIRE_91, 12, 12)
connect _WIRE_90.sr, _T_1263
node _T_1264 = bits(_WIRE_91, 13, 13)
connect _WIRE_90.sx, _T_1264
node _T_1265 = bits(_WIRE_91, 14, 14)
connect _WIRE_90.sw, _T_1265
node _T_1266 = bits(_WIRE_91, 15, 15)
connect _WIRE_90.gf, _T_1266
node _T_1267 = bits(_WIRE_91, 16, 16)
connect _WIRE_90.pf, _T_1267
node _T_1268 = bits(_WIRE_91, 17, 17)
connect _WIRE_90.ae_stage2, _T_1268
node _T_1269 = bits(_WIRE_91, 18, 18)
connect _WIRE_90.ae_final, _T_1269
node _T_1270 = bits(_WIRE_91, 19, 19)
connect _WIRE_90.ae_ptw, _T_1270
node _T_1271 = bits(_WIRE_91, 20, 20)
connect _WIRE_90.g, _T_1271
node _T_1272 = bits(_WIRE_91, 21, 21)
connect _WIRE_90.u, _T_1272
node _T_1273 = bits(_WIRE_91, 41, 22)
connect _WIRE_90.ppn, _T_1273
wire _WIRE_92 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_93 : UInt<42>
connect _WIRE_93, sectored_entries[0][2].data[2]
node _T_1274 = bits(_WIRE_93, 0, 0)
connect _WIRE_92.fragmented_superpage, _T_1274
node _T_1275 = bits(_WIRE_93, 1, 1)
connect _WIRE_92.c, _T_1275
node _T_1276 = bits(_WIRE_93, 2, 2)
connect _WIRE_92.eff, _T_1276
node _T_1277 = bits(_WIRE_93, 3, 3)
connect _WIRE_92.paa, _T_1277
node _T_1278 = bits(_WIRE_93, 4, 4)
connect _WIRE_92.pal, _T_1278
node _T_1279 = bits(_WIRE_93, 5, 5)
connect _WIRE_92.ppp, _T_1279
node _T_1280 = bits(_WIRE_93, 6, 6)
connect _WIRE_92.pr, _T_1280
node _T_1281 = bits(_WIRE_93, 7, 7)
connect _WIRE_92.px, _T_1281
node _T_1282 = bits(_WIRE_93, 8, 8)
connect _WIRE_92.pw, _T_1282
node _T_1283 = bits(_WIRE_93, 9, 9)
connect _WIRE_92.hr, _T_1283
node _T_1284 = bits(_WIRE_93, 10, 10)
connect _WIRE_92.hx, _T_1284
node _T_1285 = bits(_WIRE_93, 11, 11)
connect _WIRE_92.hw, _T_1285
node _T_1286 = bits(_WIRE_93, 12, 12)
connect _WIRE_92.sr, _T_1286
node _T_1287 = bits(_WIRE_93, 13, 13)
connect _WIRE_92.sx, _T_1287
node _T_1288 = bits(_WIRE_93, 14, 14)
connect _WIRE_92.sw, _T_1288
node _T_1289 = bits(_WIRE_93, 15, 15)
connect _WIRE_92.gf, _T_1289
node _T_1290 = bits(_WIRE_93, 16, 16)
connect _WIRE_92.pf, _T_1290
node _T_1291 = bits(_WIRE_93, 17, 17)
connect _WIRE_92.ae_stage2, _T_1291
node _T_1292 = bits(_WIRE_93, 18, 18)
connect _WIRE_92.ae_final, _T_1292
node _T_1293 = bits(_WIRE_93, 19, 19)
connect _WIRE_92.ae_ptw, _T_1293
node _T_1294 = bits(_WIRE_93, 20, 20)
connect _WIRE_92.g, _T_1294
node _T_1295 = bits(_WIRE_93, 21, 21)
connect _WIRE_92.u, _T_1295
node _T_1296 = bits(_WIRE_93, 41, 22)
connect _WIRE_92.ppn, _T_1296
wire _WIRE_94 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_95 : UInt<42>
connect _WIRE_95, sectored_entries[0][2].data[3]
node _T_1297 = bits(_WIRE_95, 0, 0)
connect _WIRE_94.fragmented_superpage, _T_1297
node _T_1298 = bits(_WIRE_95, 1, 1)
connect _WIRE_94.c, _T_1298
node _T_1299 = bits(_WIRE_95, 2, 2)
connect _WIRE_94.eff, _T_1299
node _T_1300 = bits(_WIRE_95, 3, 3)
connect _WIRE_94.paa, _T_1300
node _T_1301 = bits(_WIRE_95, 4, 4)
connect _WIRE_94.pal, _T_1301
node _T_1302 = bits(_WIRE_95, 5, 5)
connect _WIRE_94.ppp, _T_1302
node _T_1303 = bits(_WIRE_95, 6, 6)
connect _WIRE_94.pr, _T_1303
node _T_1304 = bits(_WIRE_95, 7, 7)
connect _WIRE_94.px, _T_1304
node _T_1305 = bits(_WIRE_95, 8, 8)
connect _WIRE_94.pw, _T_1305
node _T_1306 = bits(_WIRE_95, 9, 9)
connect _WIRE_94.hr, _T_1306
node _T_1307 = bits(_WIRE_95, 10, 10)
connect _WIRE_94.hx, _T_1307
node _T_1308 = bits(_WIRE_95, 11, 11)
connect _WIRE_94.hw, _T_1308
node _T_1309 = bits(_WIRE_95, 12, 12)
connect _WIRE_94.sr, _T_1309
node _T_1310 = bits(_WIRE_95, 13, 13)
connect _WIRE_94.sx, _T_1310
node _T_1311 = bits(_WIRE_95, 14, 14)
connect _WIRE_94.sw, _T_1311
node _T_1312 = bits(_WIRE_95, 15, 15)
connect _WIRE_94.gf, _T_1312
node _T_1313 = bits(_WIRE_95, 16, 16)
connect _WIRE_94.pf, _T_1313
node _T_1314 = bits(_WIRE_95, 17, 17)
connect _WIRE_94.ae_stage2, _T_1314
node _T_1315 = bits(_WIRE_95, 18, 18)
connect _WIRE_94.ae_final, _T_1315
node _T_1316 = bits(_WIRE_95, 19, 19)
connect _WIRE_94.ae_ptw, _T_1316
node _T_1317 = bits(_WIRE_95, 20, 20)
connect _WIRE_94.g, _T_1317
node _T_1318 = bits(_WIRE_95, 21, 21)
connect _WIRE_94.u, _T_1318
node _T_1319 = bits(_WIRE_95, 41, 22)
connect _WIRE_94.ppn, _T_1319
node _T_1320 = eq(sectored_entries[0][2].tag_v, _T_1227)
when _T_1320 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
node _T_1321 = eq(sectored_entries[0][2].tag_v, _T_1227)
when _T_1321 :
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
node _T_1322 = eq(sectored_entries[0][2].tag_v, _T_1227)
when _T_1322 :
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
node _T_1323 = eq(sectored_entries[0][2].tag_v, _T_1227)
when _T_1323 :
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
node hv_3 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_3 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_1324 = eq(hg_3, UInt<1>(0h0))
node _T_1325 = and(_T_1324, io.sfence.bits.rs1)
when _T_1325 :
node _T_1326 = xor(sectored_entries[0][3].tag_vpn, vpn)
node _T_1327 = shr(_T_1326, 2)
node _T_1328 = eq(_T_1327, UInt<1>(0h0))
node _T_1329 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1330 = and(_T_1328, _T_1329)
when _T_1330 :
wire _WIRE_96 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_97 : UInt<42>
connect _WIRE_97, sectored_entries[0][3].data[0]
node _T_1331 = bits(_WIRE_97, 0, 0)
connect _WIRE_96.fragmented_superpage, _T_1331
node _T_1332 = bits(_WIRE_97, 1, 1)
connect _WIRE_96.c, _T_1332
node _T_1333 = bits(_WIRE_97, 2, 2)
connect _WIRE_96.eff, _T_1333
node _T_1334 = bits(_WIRE_97, 3, 3)
connect _WIRE_96.paa, _T_1334
node _T_1335 = bits(_WIRE_97, 4, 4)
connect _WIRE_96.pal, _T_1335
node _T_1336 = bits(_WIRE_97, 5, 5)
connect _WIRE_96.ppp, _T_1336
node _T_1337 = bits(_WIRE_97, 6, 6)
connect _WIRE_96.pr, _T_1337
node _T_1338 = bits(_WIRE_97, 7, 7)
connect _WIRE_96.px, _T_1338
node _T_1339 = bits(_WIRE_97, 8, 8)
connect _WIRE_96.pw, _T_1339
node _T_1340 = bits(_WIRE_97, 9, 9)
connect _WIRE_96.hr, _T_1340
node _T_1341 = bits(_WIRE_97, 10, 10)
connect _WIRE_96.hx, _T_1341
node _T_1342 = bits(_WIRE_97, 11, 11)
connect _WIRE_96.hw, _T_1342
node _T_1343 = bits(_WIRE_97, 12, 12)
connect _WIRE_96.sr, _T_1343
node _T_1344 = bits(_WIRE_97, 13, 13)
connect _WIRE_96.sx, _T_1344
node _T_1345 = bits(_WIRE_97, 14, 14)
connect _WIRE_96.sw, _T_1345
node _T_1346 = bits(_WIRE_97, 15, 15)
connect _WIRE_96.gf, _T_1346
node _T_1347 = bits(_WIRE_97, 16, 16)
connect _WIRE_96.pf, _T_1347
node _T_1348 = bits(_WIRE_97, 17, 17)
connect _WIRE_96.ae_stage2, _T_1348
node _T_1349 = bits(_WIRE_97, 18, 18)
connect _WIRE_96.ae_final, _T_1349
node _T_1350 = bits(_WIRE_97, 19, 19)
connect _WIRE_96.ae_ptw, _T_1350
node _T_1351 = bits(_WIRE_97, 20, 20)
connect _WIRE_96.g, _T_1351
node _T_1352 = bits(_WIRE_97, 21, 21)
connect _WIRE_96.u, _T_1352
node _T_1353 = bits(_WIRE_97, 41, 22)
connect _WIRE_96.ppn, _T_1353
wire _WIRE_98 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_99 : UInt<42>
connect _WIRE_99, sectored_entries[0][3].data[1]
node _T_1354 = bits(_WIRE_99, 0, 0)
connect _WIRE_98.fragmented_superpage, _T_1354
node _T_1355 = bits(_WIRE_99, 1, 1)
connect _WIRE_98.c, _T_1355
node _T_1356 = bits(_WIRE_99, 2, 2)
connect _WIRE_98.eff, _T_1356
node _T_1357 = bits(_WIRE_99, 3, 3)
connect _WIRE_98.paa, _T_1357
node _T_1358 = bits(_WIRE_99, 4, 4)
connect _WIRE_98.pal, _T_1358
node _T_1359 = bits(_WIRE_99, 5, 5)
connect _WIRE_98.ppp, _T_1359
node _T_1360 = bits(_WIRE_99, 6, 6)
connect _WIRE_98.pr, _T_1360
node _T_1361 = bits(_WIRE_99, 7, 7)
connect _WIRE_98.px, _T_1361
node _T_1362 = bits(_WIRE_99, 8, 8)
connect _WIRE_98.pw, _T_1362
node _T_1363 = bits(_WIRE_99, 9, 9)
connect _WIRE_98.hr, _T_1363
node _T_1364 = bits(_WIRE_99, 10, 10)
connect _WIRE_98.hx, _T_1364
node _T_1365 = bits(_WIRE_99, 11, 11)
connect _WIRE_98.hw, _T_1365
node _T_1366 = bits(_WIRE_99, 12, 12)
connect _WIRE_98.sr, _T_1366
node _T_1367 = bits(_WIRE_99, 13, 13)
connect _WIRE_98.sx, _T_1367
node _T_1368 = bits(_WIRE_99, 14, 14)
connect _WIRE_98.sw, _T_1368
node _T_1369 = bits(_WIRE_99, 15, 15)
connect _WIRE_98.gf, _T_1369
node _T_1370 = bits(_WIRE_99, 16, 16)
connect _WIRE_98.pf, _T_1370
node _T_1371 = bits(_WIRE_99, 17, 17)
connect _WIRE_98.ae_stage2, _T_1371
node _T_1372 = bits(_WIRE_99, 18, 18)
connect _WIRE_98.ae_final, _T_1372
node _T_1373 = bits(_WIRE_99, 19, 19)
connect _WIRE_98.ae_ptw, _T_1373
node _T_1374 = bits(_WIRE_99, 20, 20)
connect _WIRE_98.g, _T_1374
node _T_1375 = bits(_WIRE_99, 21, 21)
connect _WIRE_98.u, _T_1375
node _T_1376 = bits(_WIRE_99, 41, 22)
connect _WIRE_98.ppn, _T_1376
wire _WIRE_100 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_101 : UInt<42>
connect _WIRE_101, sectored_entries[0][3].data[2]
node _T_1377 = bits(_WIRE_101, 0, 0)
connect _WIRE_100.fragmented_superpage, _T_1377
node _T_1378 = bits(_WIRE_101, 1, 1)
connect _WIRE_100.c, _T_1378
node _T_1379 = bits(_WIRE_101, 2, 2)
connect _WIRE_100.eff, _T_1379
node _T_1380 = bits(_WIRE_101, 3, 3)
connect _WIRE_100.paa, _T_1380
node _T_1381 = bits(_WIRE_101, 4, 4)
connect _WIRE_100.pal, _T_1381
node _T_1382 = bits(_WIRE_101, 5, 5)
connect _WIRE_100.ppp, _T_1382
node _T_1383 = bits(_WIRE_101, 6, 6)
connect _WIRE_100.pr, _T_1383
node _T_1384 = bits(_WIRE_101, 7, 7)
connect _WIRE_100.px, _T_1384
node _T_1385 = bits(_WIRE_101, 8, 8)
connect _WIRE_100.pw, _T_1385
node _T_1386 = bits(_WIRE_101, 9, 9)
connect _WIRE_100.hr, _T_1386
node _T_1387 = bits(_WIRE_101, 10, 10)
connect _WIRE_100.hx, _T_1387
node _T_1388 = bits(_WIRE_101, 11, 11)
connect _WIRE_100.hw, _T_1388
node _T_1389 = bits(_WIRE_101, 12, 12)
connect _WIRE_100.sr, _T_1389
node _T_1390 = bits(_WIRE_101, 13, 13)
connect _WIRE_100.sx, _T_1390
node _T_1391 = bits(_WIRE_101, 14, 14)
connect _WIRE_100.sw, _T_1391
node _T_1392 = bits(_WIRE_101, 15, 15)
connect _WIRE_100.gf, _T_1392
node _T_1393 = bits(_WIRE_101, 16, 16)
connect _WIRE_100.pf, _T_1393
node _T_1394 = bits(_WIRE_101, 17, 17)
connect _WIRE_100.ae_stage2, _T_1394
node _T_1395 = bits(_WIRE_101, 18, 18)
connect _WIRE_100.ae_final, _T_1395
node _T_1396 = bits(_WIRE_101, 19, 19)
connect _WIRE_100.ae_ptw, _T_1396
node _T_1397 = bits(_WIRE_101, 20, 20)
connect _WIRE_100.g, _T_1397
node _T_1398 = bits(_WIRE_101, 21, 21)
connect _WIRE_100.u, _T_1398
node _T_1399 = bits(_WIRE_101, 41, 22)
connect _WIRE_100.ppn, _T_1399
wire _WIRE_102 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_103 : UInt<42>
connect _WIRE_103, sectored_entries[0][3].data[3]
node _T_1400 = bits(_WIRE_103, 0, 0)
connect _WIRE_102.fragmented_superpage, _T_1400
node _T_1401 = bits(_WIRE_103, 1, 1)
connect _WIRE_102.c, _T_1401
node _T_1402 = bits(_WIRE_103, 2, 2)
connect _WIRE_102.eff, _T_1402
node _T_1403 = bits(_WIRE_103, 3, 3)
connect _WIRE_102.paa, _T_1403
node _T_1404 = bits(_WIRE_103, 4, 4)
connect _WIRE_102.pal, _T_1404
node _T_1405 = bits(_WIRE_103, 5, 5)
connect _WIRE_102.ppp, _T_1405
node _T_1406 = bits(_WIRE_103, 6, 6)
connect _WIRE_102.pr, _T_1406
node _T_1407 = bits(_WIRE_103, 7, 7)
connect _WIRE_102.px, _T_1407
node _T_1408 = bits(_WIRE_103, 8, 8)
connect _WIRE_102.pw, _T_1408
node _T_1409 = bits(_WIRE_103, 9, 9)
connect _WIRE_102.hr, _T_1409
node _T_1410 = bits(_WIRE_103, 10, 10)
connect _WIRE_102.hx, _T_1410
node _T_1411 = bits(_WIRE_103, 11, 11)
connect _WIRE_102.hw, _T_1411
node _T_1412 = bits(_WIRE_103, 12, 12)
connect _WIRE_102.sr, _T_1412
node _T_1413 = bits(_WIRE_103, 13, 13)
connect _WIRE_102.sx, _T_1413
node _T_1414 = bits(_WIRE_103, 14, 14)
connect _WIRE_102.sw, _T_1414
node _T_1415 = bits(_WIRE_103, 15, 15)
connect _WIRE_102.gf, _T_1415
node _T_1416 = bits(_WIRE_103, 16, 16)
connect _WIRE_102.pf, _T_1416
node _T_1417 = bits(_WIRE_103, 17, 17)
connect _WIRE_102.ae_stage2, _T_1417
node _T_1418 = bits(_WIRE_103, 18, 18)
connect _WIRE_102.ae_final, _T_1418
node _T_1419 = bits(_WIRE_103, 19, 19)
connect _WIRE_102.ae_ptw, _T_1419
node _T_1420 = bits(_WIRE_103, 20, 20)
connect _WIRE_102.g, _T_1420
node _T_1421 = bits(_WIRE_103, 21, 21)
connect _WIRE_102.u, _T_1421
node _T_1422 = bits(_WIRE_103, 41, 22)
connect _WIRE_102.ppn, _T_1422
node _T_1423 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1424 = bits(vpn, 1, 0)
node _T_1425 = eq(UInt<1>(0h0), _T_1424)
node _T_1426 = and(_T_1423, _T_1425)
when _T_1426 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
node _T_1427 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1428 = bits(vpn, 1, 0)
node _T_1429 = eq(UInt<1>(0h1), _T_1428)
node _T_1430 = and(_T_1427, _T_1429)
when _T_1430 :
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
node _T_1431 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1432 = bits(vpn, 1, 0)
node _T_1433 = eq(UInt<2>(0h2), _T_1432)
node _T_1434 = and(_T_1431, _T_1433)
when _T_1434 :
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
node _T_1435 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1436 = bits(vpn, 1, 0)
node _T_1437 = eq(UInt<2>(0h3), _T_1436)
node _T_1438 = and(_T_1435, _T_1437)
when _T_1438 :
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
node _T_1439 = xor(sectored_entries[0][3].tag_vpn, vpn)
node _T_1440 = shr(_T_1439, 18)
node _T_1441 = eq(_T_1440, UInt<1>(0h0))
when _T_1441 :
wire _WIRE_104 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_105 : UInt<42>
connect _WIRE_105, sectored_entries[0][3].data[0]
node _T_1442 = bits(_WIRE_105, 0, 0)
connect _WIRE_104.fragmented_superpage, _T_1442
node _T_1443 = bits(_WIRE_105, 1, 1)
connect _WIRE_104.c, _T_1443
node _T_1444 = bits(_WIRE_105, 2, 2)
connect _WIRE_104.eff, _T_1444
node _T_1445 = bits(_WIRE_105, 3, 3)
connect _WIRE_104.paa, _T_1445
node _T_1446 = bits(_WIRE_105, 4, 4)
connect _WIRE_104.pal, _T_1446
node _T_1447 = bits(_WIRE_105, 5, 5)
connect _WIRE_104.ppp, _T_1447
node _T_1448 = bits(_WIRE_105, 6, 6)
connect _WIRE_104.pr, _T_1448
node _T_1449 = bits(_WIRE_105, 7, 7)
connect _WIRE_104.px, _T_1449
node _T_1450 = bits(_WIRE_105, 8, 8)
connect _WIRE_104.pw, _T_1450
node _T_1451 = bits(_WIRE_105, 9, 9)
connect _WIRE_104.hr, _T_1451
node _T_1452 = bits(_WIRE_105, 10, 10)
connect _WIRE_104.hx, _T_1452
node _T_1453 = bits(_WIRE_105, 11, 11)
connect _WIRE_104.hw, _T_1453
node _T_1454 = bits(_WIRE_105, 12, 12)
connect _WIRE_104.sr, _T_1454
node _T_1455 = bits(_WIRE_105, 13, 13)
connect _WIRE_104.sx, _T_1455
node _T_1456 = bits(_WIRE_105, 14, 14)
connect _WIRE_104.sw, _T_1456
node _T_1457 = bits(_WIRE_105, 15, 15)
connect _WIRE_104.gf, _T_1457
node _T_1458 = bits(_WIRE_105, 16, 16)
connect _WIRE_104.pf, _T_1458
node _T_1459 = bits(_WIRE_105, 17, 17)
connect _WIRE_104.ae_stage2, _T_1459
node _T_1460 = bits(_WIRE_105, 18, 18)
connect _WIRE_104.ae_final, _T_1460
node _T_1461 = bits(_WIRE_105, 19, 19)
connect _WIRE_104.ae_ptw, _T_1461
node _T_1462 = bits(_WIRE_105, 20, 20)
connect _WIRE_104.g, _T_1462
node _T_1463 = bits(_WIRE_105, 21, 21)
connect _WIRE_104.u, _T_1463
node _T_1464 = bits(_WIRE_105, 41, 22)
connect _WIRE_104.ppn, _T_1464
wire _WIRE_106 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_107 : UInt<42>
connect _WIRE_107, sectored_entries[0][3].data[1]
node _T_1465 = bits(_WIRE_107, 0, 0)
connect _WIRE_106.fragmented_superpage, _T_1465
node _T_1466 = bits(_WIRE_107, 1, 1)
connect _WIRE_106.c, _T_1466
node _T_1467 = bits(_WIRE_107, 2, 2)
connect _WIRE_106.eff, _T_1467
node _T_1468 = bits(_WIRE_107, 3, 3)
connect _WIRE_106.paa, _T_1468
node _T_1469 = bits(_WIRE_107, 4, 4)
connect _WIRE_106.pal, _T_1469
node _T_1470 = bits(_WIRE_107, 5, 5)
connect _WIRE_106.ppp, _T_1470
node _T_1471 = bits(_WIRE_107, 6, 6)
connect _WIRE_106.pr, _T_1471
node _T_1472 = bits(_WIRE_107, 7, 7)
connect _WIRE_106.px, _T_1472
node _T_1473 = bits(_WIRE_107, 8, 8)
connect _WIRE_106.pw, _T_1473
node _T_1474 = bits(_WIRE_107, 9, 9)
connect _WIRE_106.hr, _T_1474
node _T_1475 = bits(_WIRE_107, 10, 10)
connect _WIRE_106.hx, _T_1475
node _T_1476 = bits(_WIRE_107, 11, 11)
connect _WIRE_106.hw, _T_1476
node _T_1477 = bits(_WIRE_107, 12, 12)
connect _WIRE_106.sr, _T_1477
node _T_1478 = bits(_WIRE_107, 13, 13)
connect _WIRE_106.sx, _T_1478
node _T_1479 = bits(_WIRE_107, 14, 14)
connect _WIRE_106.sw, _T_1479
node _T_1480 = bits(_WIRE_107, 15, 15)
connect _WIRE_106.gf, _T_1480
node _T_1481 = bits(_WIRE_107, 16, 16)
connect _WIRE_106.pf, _T_1481
node _T_1482 = bits(_WIRE_107, 17, 17)
connect _WIRE_106.ae_stage2, _T_1482
node _T_1483 = bits(_WIRE_107, 18, 18)
connect _WIRE_106.ae_final, _T_1483
node _T_1484 = bits(_WIRE_107, 19, 19)
connect _WIRE_106.ae_ptw, _T_1484
node _T_1485 = bits(_WIRE_107, 20, 20)
connect _WIRE_106.g, _T_1485
node _T_1486 = bits(_WIRE_107, 21, 21)
connect _WIRE_106.u, _T_1486
node _T_1487 = bits(_WIRE_107, 41, 22)
connect _WIRE_106.ppn, _T_1487
wire _WIRE_108 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_109 : UInt<42>
connect _WIRE_109, sectored_entries[0][3].data[2]
node _T_1488 = bits(_WIRE_109, 0, 0)
connect _WIRE_108.fragmented_superpage, _T_1488
node _T_1489 = bits(_WIRE_109, 1, 1)
connect _WIRE_108.c, _T_1489
node _T_1490 = bits(_WIRE_109, 2, 2)
connect _WIRE_108.eff, _T_1490
node _T_1491 = bits(_WIRE_109, 3, 3)
connect _WIRE_108.paa, _T_1491
node _T_1492 = bits(_WIRE_109, 4, 4)
connect _WIRE_108.pal, _T_1492
node _T_1493 = bits(_WIRE_109, 5, 5)
connect _WIRE_108.ppp, _T_1493
node _T_1494 = bits(_WIRE_109, 6, 6)
connect _WIRE_108.pr, _T_1494
node _T_1495 = bits(_WIRE_109, 7, 7)
connect _WIRE_108.px, _T_1495
node _T_1496 = bits(_WIRE_109, 8, 8)
connect _WIRE_108.pw, _T_1496
node _T_1497 = bits(_WIRE_109, 9, 9)
connect _WIRE_108.hr, _T_1497
node _T_1498 = bits(_WIRE_109, 10, 10)
connect _WIRE_108.hx, _T_1498
node _T_1499 = bits(_WIRE_109, 11, 11)
connect _WIRE_108.hw, _T_1499
node _T_1500 = bits(_WIRE_109, 12, 12)
connect _WIRE_108.sr, _T_1500
node _T_1501 = bits(_WIRE_109, 13, 13)
connect _WIRE_108.sx, _T_1501
node _T_1502 = bits(_WIRE_109, 14, 14)
connect _WIRE_108.sw, _T_1502
node _T_1503 = bits(_WIRE_109, 15, 15)
connect _WIRE_108.gf, _T_1503
node _T_1504 = bits(_WIRE_109, 16, 16)
connect _WIRE_108.pf, _T_1504
node _T_1505 = bits(_WIRE_109, 17, 17)
connect _WIRE_108.ae_stage2, _T_1505
node _T_1506 = bits(_WIRE_109, 18, 18)
connect _WIRE_108.ae_final, _T_1506
node _T_1507 = bits(_WIRE_109, 19, 19)
connect _WIRE_108.ae_ptw, _T_1507
node _T_1508 = bits(_WIRE_109, 20, 20)
connect _WIRE_108.g, _T_1508
node _T_1509 = bits(_WIRE_109, 21, 21)
connect _WIRE_108.u, _T_1509
node _T_1510 = bits(_WIRE_109, 41, 22)
connect _WIRE_108.ppn, _T_1510
wire _WIRE_110 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_111 : UInt<42>
connect _WIRE_111, sectored_entries[0][3].data[3]
node _T_1511 = bits(_WIRE_111, 0, 0)
connect _WIRE_110.fragmented_superpage, _T_1511
node _T_1512 = bits(_WIRE_111, 1, 1)
connect _WIRE_110.c, _T_1512
node _T_1513 = bits(_WIRE_111, 2, 2)
connect _WIRE_110.eff, _T_1513
node _T_1514 = bits(_WIRE_111, 3, 3)
connect _WIRE_110.paa, _T_1514
node _T_1515 = bits(_WIRE_111, 4, 4)
connect _WIRE_110.pal, _T_1515
node _T_1516 = bits(_WIRE_111, 5, 5)
connect _WIRE_110.ppp, _T_1516
node _T_1517 = bits(_WIRE_111, 6, 6)
connect _WIRE_110.pr, _T_1517
node _T_1518 = bits(_WIRE_111, 7, 7)
connect _WIRE_110.px, _T_1518
node _T_1519 = bits(_WIRE_111, 8, 8)
connect _WIRE_110.pw, _T_1519
node _T_1520 = bits(_WIRE_111, 9, 9)
connect _WIRE_110.hr, _T_1520
node _T_1521 = bits(_WIRE_111, 10, 10)
connect _WIRE_110.hx, _T_1521
node _T_1522 = bits(_WIRE_111, 11, 11)
connect _WIRE_110.hw, _T_1522
node _T_1523 = bits(_WIRE_111, 12, 12)
connect _WIRE_110.sr, _T_1523
node _T_1524 = bits(_WIRE_111, 13, 13)
connect _WIRE_110.sx, _T_1524
node _T_1525 = bits(_WIRE_111, 14, 14)
connect _WIRE_110.sw, _T_1525
node _T_1526 = bits(_WIRE_111, 15, 15)
connect _WIRE_110.gf, _T_1526
node _T_1527 = bits(_WIRE_111, 16, 16)
connect _WIRE_110.pf, _T_1527
node _T_1528 = bits(_WIRE_111, 17, 17)
connect _WIRE_110.ae_stage2, _T_1528
node _T_1529 = bits(_WIRE_111, 18, 18)
connect _WIRE_110.ae_final, _T_1529
node _T_1530 = bits(_WIRE_111, 19, 19)
connect _WIRE_110.ae_ptw, _T_1530
node _T_1531 = bits(_WIRE_111, 20, 20)
connect _WIRE_110.g, _T_1531
node _T_1532 = bits(_WIRE_111, 21, 21)
connect _WIRE_110.u, _T_1532
node _T_1533 = bits(_WIRE_111, 41, 22)
connect _WIRE_110.ppn, _T_1533
node _T_1534 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1535 = and(_T_1534, _WIRE_104.fragmented_superpage)
when _T_1535 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
node _T_1536 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1537 = and(_T_1536, _WIRE_106.fragmented_superpage)
when _T_1537 :
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
node _T_1538 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1539 = and(_T_1538, _WIRE_108.fragmented_superpage)
when _T_1539 :
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
node _T_1540 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1541 = and(_T_1540, _WIRE_110.fragmented_superpage)
when _T_1541 :
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
else :
node _T_1542 = eq(hg_3, UInt<1>(0h0))
node _T_1543 = and(_T_1542, io.sfence.bits.rs2)
when _T_1543 :
wire _WIRE_112 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_113 : UInt<42>
connect _WIRE_113, sectored_entries[0][3].data[0]
node _T_1544 = bits(_WIRE_113, 0, 0)
connect _WIRE_112.fragmented_superpage, _T_1544
node _T_1545 = bits(_WIRE_113, 1, 1)
connect _WIRE_112.c, _T_1545
node _T_1546 = bits(_WIRE_113, 2, 2)
connect _WIRE_112.eff, _T_1546
node _T_1547 = bits(_WIRE_113, 3, 3)
connect _WIRE_112.paa, _T_1547
node _T_1548 = bits(_WIRE_113, 4, 4)
connect _WIRE_112.pal, _T_1548
node _T_1549 = bits(_WIRE_113, 5, 5)
connect _WIRE_112.ppp, _T_1549
node _T_1550 = bits(_WIRE_113, 6, 6)
connect _WIRE_112.pr, _T_1550
node _T_1551 = bits(_WIRE_113, 7, 7)
connect _WIRE_112.px, _T_1551
node _T_1552 = bits(_WIRE_113, 8, 8)
connect _WIRE_112.pw, _T_1552
node _T_1553 = bits(_WIRE_113, 9, 9)
connect _WIRE_112.hr, _T_1553
node _T_1554 = bits(_WIRE_113, 10, 10)
connect _WIRE_112.hx, _T_1554
node _T_1555 = bits(_WIRE_113, 11, 11)
connect _WIRE_112.hw, _T_1555
node _T_1556 = bits(_WIRE_113, 12, 12)
connect _WIRE_112.sr, _T_1556
node _T_1557 = bits(_WIRE_113, 13, 13)
connect _WIRE_112.sx, _T_1557
node _T_1558 = bits(_WIRE_113, 14, 14)
connect _WIRE_112.sw, _T_1558
node _T_1559 = bits(_WIRE_113, 15, 15)
connect _WIRE_112.gf, _T_1559
node _T_1560 = bits(_WIRE_113, 16, 16)
connect _WIRE_112.pf, _T_1560
node _T_1561 = bits(_WIRE_113, 17, 17)
connect _WIRE_112.ae_stage2, _T_1561
node _T_1562 = bits(_WIRE_113, 18, 18)
connect _WIRE_112.ae_final, _T_1562
node _T_1563 = bits(_WIRE_113, 19, 19)
connect _WIRE_112.ae_ptw, _T_1563
node _T_1564 = bits(_WIRE_113, 20, 20)
connect _WIRE_112.g, _T_1564
node _T_1565 = bits(_WIRE_113, 21, 21)
connect _WIRE_112.u, _T_1565
node _T_1566 = bits(_WIRE_113, 41, 22)
connect _WIRE_112.ppn, _T_1566
wire _WIRE_114 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_115 : UInt<42>
connect _WIRE_115, sectored_entries[0][3].data[1]
node _T_1567 = bits(_WIRE_115, 0, 0)
connect _WIRE_114.fragmented_superpage, _T_1567
node _T_1568 = bits(_WIRE_115, 1, 1)
connect _WIRE_114.c, _T_1568
node _T_1569 = bits(_WIRE_115, 2, 2)
connect _WIRE_114.eff, _T_1569
node _T_1570 = bits(_WIRE_115, 3, 3)
connect _WIRE_114.paa, _T_1570
node _T_1571 = bits(_WIRE_115, 4, 4)
connect _WIRE_114.pal, _T_1571
node _T_1572 = bits(_WIRE_115, 5, 5)
connect _WIRE_114.ppp, _T_1572
node _T_1573 = bits(_WIRE_115, 6, 6)
connect _WIRE_114.pr, _T_1573
node _T_1574 = bits(_WIRE_115, 7, 7)
connect _WIRE_114.px, _T_1574
node _T_1575 = bits(_WIRE_115, 8, 8)
connect _WIRE_114.pw, _T_1575
node _T_1576 = bits(_WIRE_115, 9, 9)
connect _WIRE_114.hr, _T_1576
node _T_1577 = bits(_WIRE_115, 10, 10)
connect _WIRE_114.hx, _T_1577
node _T_1578 = bits(_WIRE_115, 11, 11)
connect _WIRE_114.hw, _T_1578
node _T_1579 = bits(_WIRE_115, 12, 12)
connect _WIRE_114.sr, _T_1579
node _T_1580 = bits(_WIRE_115, 13, 13)
connect _WIRE_114.sx, _T_1580
node _T_1581 = bits(_WIRE_115, 14, 14)
connect _WIRE_114.sw, _T_1581
node _T_1582 = bits(_WIRE_115, 15, 15)
connect _WIRE_114.gf, _T_1582
node _T_1583 = bits(_WIRE_115, 16, 16)
connect _WIRE_114.pf, _T_1583
node _T_1584 = bits(_WIRE_115, 17, 17)
connect _WIRE_114.ae_stage2, _T_1584
node _T_1585 = bits(_WIRE_115, 18, 18)
connect _WIRE_114.ae_final, _T_1585
node _T_1586 = bits(_WIRE_115, 19, 19)
connect _WIRE_114.ae_ptw, _T_1586
node _T_1587 = bits(_WIRE_115, 20, 20)
connect _WIRE_114.g, _T_1587
node _T_1588 = bits(_WIRE_115, 21, 21)
connect _WIRE_114.u, _T_1588
node _T_1589 = bits(_WIRE_115, 41, 22)
connect _WIRE_114.ppn, _T_1589
wire _WIRE_116 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_117 : UInt<42>
connect _WIRE_117, sectored_entries[0][3].data[2]
node _T_1590 = bits(_WIRE_117, 0, 0)
connect _WIRE_116.fragmented_superpage, _T_1590
node _T_1591 = bits(_WIRE_117, 1, 1)
connect _WIRE_116.c, _T_1591
node _T_1592 = bits(_WIRE_117, 2, 2)
connect _WIRE_116.eff, _T_1592
node _T_1593 = bits(_WIRE_117, 3, 3)
connect _WIRE_116.paa, _T_1593
node _T_1594 = bits(_WIRE_117, 4, 4)
connect _WIRE_116.pal, _T_1594
node _T_1595 = bits(_WIRE_117, 5, 5)
connect _WIRE_116.ppp, _T_1595
node _T_1596 = bits(_WIRE_117, 6, 6)
connect _WIRE_116.pr, _T_1596
node _T_1597 = bits(_WIRE_117, 7, 7)
connect _WIRE_116.px, _T_1597
node _T_1598 = bits(_WIRE_117, 8, 8)
connect _WIRE_116.pw, _T_1598
node _T_1599 = bits(_WIRE_117, 9, 9)
connect _WIRE_116.hr, _T_1599
node _T_1600 = bits(_WIRE_117, 10, 10)
connect _WIRE_116.hx, _T_1600
node _T_1601 = bits(_WIRE_117, 11, 11)
connect _WIRE_116.hw, _T_1601
node _T_1602 = bits(_WIRE_117, 12, 12)
connect _WIRE_116.sr, _T_1602
node _T_1603 = bits(_WIRE_117, 13, 13)
connect _WIRE_116.sx, _T_1603
node _T_1604 = bits(_WIRE_117, 14, 14)
connect _WIRE_116.sw, _T_1604
node _T_1605 = bits(_WIRE_117, 15, 15)
connect _WIRE_116.gf, _T_1605
node _T_1606 = bits(_WIRE_117, 16, 16)
connect _WIRE_116.pf, _T_1606
node _T_1607 = bits(_WIRE_117, 17, 17)
connect _WIRE_116.ae_stage2, _T_1607
node _T_1608 = bits(_WIRE_117, 18, 18)
connect _WIRE_116.ae_final, _T_1608
node _T_1609 = bits(_WIRE_117, 19, 19)
connect _WIRE_116.ae_ptw, _T_1609
node _T_1610 = bits(_WIRE_117, 20, 20)
connect _WIRE_116.g, _T_1610
node _T_1611 = bits(_WIRE_117, 21, 21)
connect _WIRE_116.u, _T_1611
node _T_1612 = bits(_WIRE_117, 41, 22)
connect _WIRE_116.ppn, _T_1612
wire _WIRE_118 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_119 : UInt<42>
connect _WIRE_119, sectored_entries[0][3].data[3]
node _T_1613 = bits(_WIRE_119, 0, 0)
connect _WIRE_118.fragmented_superpage, _T_1613
node _T_1614 = bits(_WIRE_119, 1, 1)
connect _WIRE_118.c, _T_1614
node _T_1615 = bits(_WIRE_119, 2, 2)
connect _WIRE_118.eff, _T_1615
node _T_1616 = bits(_WIRE_119, 3, 3)
connect _WIRE_118.paa, _T_1616
node _T_1617 = bits(_WIRE_119, 4, 4)
connect _WIRE_118.pal, _T_1617
node _T_1618 = bits(_WIRE_119, 5, 5)
connect _WIRE_118.ppp, _T_1618
node _T_1619 = bits(_WIRE_119, 6, 6)
connect _WIRE_118.pr, _T_1619
node _T_1620 = bits(_WIRE_119, 7, 7)
connect _WIRE_118.px, _T_1620
node _T_1621 = bits(_WIRE_119, 8, 8)
connect _WIRE_118.pw, _T_1621
node _T_1622 = bits(_WIRE_119, 9, 9)
connect _WIRE_118.hr, _T_1622
node _T_1623 = bits(_WIRE_119, 10, 10)
connect _WIRE_118.hx, _T_1623
node _T_1624 = bits(_WIRE_119, 11, 11)
connect _WIRE_118.hw, _T_1624
node _T_1625 = bits(_WIRE_119, 12, 12)
connect _WIRE_118.sr, _T_1625
node _T_1626 = bits(_WIRE_119, 13, 13)
connect _WIRE_118.sx, _T_1626
node _T_1627 = bits(_WIRE_119, 14, 14)
connect _WIRE_118.sw, _T_1627
node _T_1628 = bits(_WIRE_119, 15, 15)
connect _WIRE_118.gf, _T_1628
node _T_1629 = bits(_WIRE_119, 16, 16)
connect _WIRE_118.pf, _T_1629
node _T_1630 = bits(_WIRE_119, 17, 17)
connect _WIRE_118.ae_stage2, _T_1630
node _T_1631 = bits(_WIRE_119, 18, 18)
connect _WIRE_118.ae_final, _T_1631
node _T_1632 = bits(_WIRE_119, 19, 19)
connect _WIRE_118.ae_ptw, _T_1632
node _T_1633 = bits(_WIRE_119, 20, 20)
connect _WIRE_118.g, _T_1633
node _T_1634 = bits(_WIRE_119, 21, 21)
connect _WIRE_118.u, _T_1634
node _T_1635 = bits(_WIRE_119, 41, 22)
connect _WIRE_118.ppn, _T_1635
node _T_1636 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1637 = eq(_WIRE_112.g, UInt<1>(0h0))
node _T_1638 = and(_T_1636, _T_1637)
when _T_1638 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
node _T_1639 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1640 = eq(_WIRE_114.g, UInt<1>(0h0))
node _T_1641 = and(_T_1639, _T_1640)
when _T_1641 :
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
node _T_1642 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1643 = eq(_WIRE_116.g, UInt<1>(0h0))
node _T_1644 = and(_T_1642, _T_1643)
when _T_1644 :
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
node _T_1645 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1646 = eq(_WIRE_118.g, UInt<1>(0h0))
node _T_1647 = and(_T_1645, _T_1646)
when _T_1647 :
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
else :
node _T_1648 = or(hv_3, hg_3)
wire _WIRE_120 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_121 : UInt<42>
connect _WIRE_121, sectored_entries[0][3].data[0]
node _T_1649 = bits(_WIRE_121, 0, 0)
connect _WIRE_120.fragmented_superpage, _T_1649
node _T_1650 = bits(_WIRE_121, 1, 1)
connect _WIRE_120.c, _T_1650
node _T_1651 = bits(_WIRE_121, 2, 2)
connect _WIRE_120.eff, _T_1651
node _T_1652 = bits(_WIRE_121, 3, 3)
connect _WIRE_120.paa, _T_1652
node _T_1653 = bits(_WIRE_121, 4, 4)
connect _WIRE_120.pal, _T_1653
node _T_1654 = bits(_WIRE_121, 5, 5)
connect _WIRE_120.ppp, _T_1654
node _T_1655 = bits(_WIRE_121, 6, 6)
connect _WIRE_120.pr, _T_1655
node _T_1656 = bits(_WIRE_121, 7, 7)
connect _WIRE_120.px, _T_1656
node _T_1657 = bits(_WIRE_121, 8, 8)
connect _WIRE_120.pw, _T_1657
node _T_1658 = bits(_WIRE_121, 9, 9)
connect _WIRE_120.hr, _T_1658
node _T_1659 = bits(_WIRE_121, 10, 10)
connect _WIRE_120.hx, _T_1659
node _T_1660 = bits(_WIRE_121, 11, 11)
connect _WIRE_120.hw, _T_1660
node _T_1661 = bits(_WIRE_121, 12, 12)
connect _WIRE_120.sr, _T_1661
node _T_1662 = bits(_WIRE_121, 13, 13)
connect _WIRE_120.sx, _T_1662
node _T_1663 = bits(_WIRE_121, 14, 14)
connect _WIRE_120.sw, _T_1663
node _T_1664 = bits(_WIRE_121, 15, 15)
connect _WIRE_120.gf, _T_1664
node _T_1665 = bits(_WIRE_121, 16, 16)
connect _WIRE_120.pf, _T_1665
node _T_1666 = bits(_WIRE_121, 17, 17)
connect _WIRE_120.ae_stage2, _T_1666
node _T_1667 = bits(_WIRE_121, 18, 18)
connect _WIRE_120.ae_final, _T_1667
node _T_1668 = bits(_WIRE_121, 19, 19)
connect _WIRE_120.ae_ptw, _T_1668
node _T_1669 = bits(_WIRE_121, 20, 20)
connect _WIRE_120.g, _T_1669
node _T_1670 = bits(_WIRE_121, 21, 21)
connect _WIRE_120.u, _T_1670
node _T_1671 = bits(_WIRE_121, 41, 22)
connect _WIRE_120.ppn, _T_1671
wire _WIRE_122 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_123 : UInt<42>
connect _WIRE_123, sectored_entries[0][3].data[1]
node _T_1672 = bits(_WIRE_123, 0, 0)
connect _WIRE_122.fragmented_superpage, _T_1672
node _T_1673 = bits(_WIRE_123, 1, 1)
connect _WIRE_122.c, _T_1673
node _T_1674 = bits(_WIRE_123, 2, 2)
connect _WIRE_122.eff, _T_1674
node _T_1675 = bits(_WIRE_123, 3, 3)
connect _WIRE_122.paa, _T_1675
node _T_1676 = bits(_WIRE_123, 4, 4)
connect _WIRE_122.pal, _T_1676
node _T_1677 = bits(_WIRE_123, 5, 5)
connect _WIRE_122.ppp, _T_1677
node _T_1678 = bits(_WIRE_123, 6, 6)
connect _WIRE_122.pr, _T_1678
node _T_1679 = bits(_WIRE_123, 7, 7)
connect _WIRE_122.px, _T_1679
node _T_1680 = bits(_WIRE_123, 8, 8)
connect _WIRE_122.pw, _T_1680
node _T_1681 = bits(_WIRE_123, 9, 9)
connect _WIRE_122.hr, _T_1681
node _T_1682 = bits(_WIRE_123, 10, 10)
connect _WIRE_122.hx, _T_1682
node _T_1683 = bits(_WIRE_123, 11, 11)
connect _WIRE_122.hw, _T_1683
node _T_1684 = bits(_WIRE_123, 12, 12)
connect _WIRE_122.sr, _T_1684
node _T_1685 = bits(_WIRE_123, 13, 13)
connect _WIRE_122.sx, _T_1685
node _T_1686 = bits(_WIRE_123, 14, 14)
connect _WIRE_122.sw, _T_1686
node _T_1687 = bits(_WIRE_123, 15, 15)
connect _WIRE_122.gf, _T_1687
node _T_1688 = bits(_WIRE_123, 16, 16)
connect _WIRE_122.pf, _T_1688
node _T_1689 = bits(_WIRE_123, 17, 17)
connect _WIRE_122.ae_stage2, _T_1689
node _T_1690 = bits(_WIRE_123, 18, 18)
connect _WIRE_122.ae_final, _T_1690
node _T_1691 = bits(_WIRE_123, 19, 19)
connect _WIRE_122.ae_ptw, _T_1691
node _T_1692 = bits(_WIRE_123, 20, 20)
connect _WIRE_122.g, _T_1692
node _T_1693 = bits(_WIRE_123, 21, 21)
connect _WIRE_122.u, _T_1693
node _T_1694 = bits(_WIRE_123, 41, 22)
connect _WIRE_122.ppn, _T_1694
wire _WIRE_124 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_125 : UInt<42>
connect _WIRE_125, sectored_entries[0][3].data[2]
node _T_1695 = bits(_WIRE_125, 0, 0)
connect _WIRE_124.fragmented_superpage, _T_1695
node _T_1696 = bits(_WIRE_125, 1, 1)
connect _WIRE_124.c, _T_1696
node _T_1697 = bits(_WIRE_125, 2, 2)
connect _WIRE_124.eff, _T_1697
node _T_1698 = bits(_WIRE_125, 3, 3)
connect _WIRE_124.paa, _T_1698
node _T_1699 = bits(_WIRE_125, 4, 4)
connect _WIRE_124.pal, _T_1699
node _T_1700 = bits(_WIRE_125, 5, 5)
connect _WIRE_124.ppp, _T_1700
node _T_1701 = bits(_WIRE_125, 6, 6)
connect _WIRE_124.pr, _T_1701
node _T_1702 = bits(_WIRE_125, 7, 7)
connect _WIRE_124.px, _T_1702
node _T_1703 = bits(_WIRE_125, 8, 8)
connect _WIRE_124.pw, _T_1703
node _T_1704 = bits(_WIRE_125, 9, 9)
connect _WIRE_124.hr, _T_1704
node _T_1705 = bits(_WIRE_125, 10, 10)
connect _WIRE_124.hx, _T_1705
node _T_1706 = bits(_WIRE_125, 11, 11)
connect _WIRE_124.hw, _T_1706
node _T_1707 = bits(_WIRE_125, 12, 12)
connect _WIRE_124.sr, _T_1707
node _T_1708 = bits(_WIRE_125, 13, 13)
connect _WIRE_124.sx, _T_1708
node _T_1709 = bits(_WIRE_125, 14, 14)
connect _WIRE_124.sw, _T_1709
node _T_1710 = bits(_WIRE_125, 15, 15)
connect _WIRE_124.gf, _T_1710
node _T_1711 = bits(_WIRE_125, 16, 16)
connect _WIRE_124.pf, _T_1711
node _T_1712 = bits(_WIRE_125, 17, 17)
connect _WIRE_124.ae_stage2, _T_1712
node _T_1713 = bits(_WIRE_125, 18, 18)
connect _WIRE_124.ae_final, _T_1713
node _T_1714 = bits(_WIRE_125, 19, 19)
connect _WIRE_124.ae_ptw, _T_1714
node _T_1715 = bits(_WIRE_125, 20, 20)
connect _WIRE_124.g, _T_1715
node _T_1716 = bits(_WIRE_125, 21, 21)
connect _WIRE_124.u, _T_1716
node _T_1717 = bits(_WIRE_125, 41, 22)
connect _WIRE_124.ppn, _T_1717
wire _WIRE_126 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_127 : UInt<42>
connect _WIRE_127, sectored_entries[0][3].data[3]
node _T_1718 = bits(_WIRE_127, 0, 0)
connect _WIRE_126.fragmented_superpage, _T_1718
node _T_1719 = bits(_WIRE_127, 1, 1)
connect _WIRE_126.c, _T_1719
node _T_1720 = bits(_WIRE_127, 2, 2)
connect _WIRE_126.eff, _T_1720
node _T_1721 = bits(_WIRE_127, 3, 3)
connect _WIRE_126.paa, _T_1721
node _T_1722 = bits(_WIRE_127, 4, 4)
connect _WIRE_126.pal, _T_1722
node _T_1723 = bits(_WIRE_127, 5, 5)
connect _WIRE_126.ppp, _T_1723
node _T_1724 = bits(_WIRE_127, 6, 6)
connect _WIRE_126.pr, _T_1724
node _T_1725 = bits(_WIRE_127, 7, 7)
connect _WIRE_126.px, _T_1725
node _T_1726 = bits(_WIRE_127, 8, 8)
connect _WIRE_126.pw, _T_1726
node _T_1727 = bits(_WIRE_127, 9, 9)
connect _WIRE_126.hr, _T_1727
node _T_1728 = bits(_WIRE_127, 10, 10)
connect _WIRE_126.hx, _T_1728
node _T_1729 = bits(_WIRE_127, 11, 11)
connect _WIRE_126.hw, _T_1729
node _T_1730 = bits(_WIRE_127, 12, 12)
connect _WIRE_126.sr, _T_1730
node _T_1731 = bits(_WIRE_127, 13, 13)
connect _WIRE_126.sx, _T_1731
node _T_1732 = bits(_WIRE_127, 14, 14)
connect _WIRE_126.sw, _T_1732
node _T_1733 = bits(_WIRE_127, 15, 15)
connect _WIRE_126.gf, _T_1733
node _T_1734 = bits(_WIRE_127, 16, 16)
connect _WIRE_126.pf, _T_1734
node _T_1735 = bits(_WIRE_127, 17, 17)
connect _WIRE_126.ae_stage2, _T_1735
node _T_1736 = bits(_WIRE_127, 18, 18)
connect _WIRE_126.ae_final, _T_1736
node _T_1737 = bits(_WIRE_127, 19, 19)
connect _WIRE_126.ae_ptw, _T_1737
node _T_1738 = bits(_WIRE_127, 20, 20)
connect _WIRE_126.g, _T_1738
node _T_1739 = bits(_WIRE_127, 21, 21)
connect _WIRE_126.u, _T_1739
node _T_1740 = bits(_WIRE_127, 41, 22)
connect _WIRE_126.ppn, _T_1740
node _T_1741 = eq(sectored_entries[0][3].tag_v, _T_1648)
when _T_1741 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
node _T_1742 = eq(sectored_entries[0][3].tag_v, _T_1648)
when _T_1742 :
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
node _T_1743 = eq(sectored_entries[0][3].tag_v, _T_1648)
when _T_1743 :
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
node _T_1744 = eq(sectored_entries[0][3].tag_v, _T_1648)
when _T_1744 :
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
node hv_4 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_4 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_1745 = eq(hg_4, UInt<1>(0h0))
node _T_1746 = and(_T_1745, io.sfence.bits.rs1)
when _T_1746 :
node _T_1747 = xor(sectored_entries[0][4].tag_vpn, vpn)
node _T_1748 = shr(_T_1747, 2)
node _T_1749 = eq(_T_1748, UInt<1>(0h0))
node _T_1750 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1751 = and(_T_1749, _T_1750)
when _T_1751 :
wire _WIRE_128 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_129 : UInt<42>
connect _WIRE_129, sectored_entries[0][4].data[0]
node _T_1752 = bits(_WIRE_129, 0, 0)
connect _WIRE_128.fragmented_superpage, _T_1752
node _T_1753 = bits(_WIRE_129, 1, 1)
connect _WIRE_128.c, _T_1753
node _T_1754 = bits(_WIRE_129, 2, 2)
connect _WIRE_128.eff, _T_1754
node _T_1755 = bits(_WIRE_129, 3, 3)
connect _WIRE_128.paa, _T_1755
node _T_1756 = bits(_WIRE_129, 4, 4)
connect _WIRE_128.pal, _T_1756
node _T_1757 = bits(_WIRE_129, 5, 5)
connect _WIRE_128.ppp, _T_1757
node _T_1758 = bits(_WIRE_129, 6, 6)
connect _WIRE_128.pr, _T_1758
node _T_1759 = bits(_WIRE_129, 7, 7)
connect _WIRE_128.px, _T_1759
node _T_1760 = bits(_WIRE_129, 8, 8)
connect _WIRE_128.pw, _T_1760
node _T_1761 = bits(_WIRE_129, 9, 9)
connect _WIRE_128.hr, _T_1761
node _T_1762 = bits(_WIRE_129, 10, 10)
connect _WIRE_128.hx, _T_1762
node _T_1763 = bits(_WIRE_129, 11, 11)
connect _WIRE_128.hw, _T_1763
node _T_1764 = bits(_WIRE_129, 12, 12)
connect _WIRE_128.sr, _T_1764
node _T_1765 = bits(_WIRE_129, 13, 13)
connect _WIRE_128.sx, _T_1765
node _T_1766 = bits(_WIRE_129, 14, 14)
connect _WIRE_128.sw, _T_1766
node _T_1767 = bits(_WIRE_129, 15, 15)
connect _WIRE_128.gf, _T_1767
node _T_1768 = bits(_WIRE_129, 16, 16)
connect _WIRE_128.pf, _T_1768
node _T_1769 = bits(_WIRE_129, 17, 17)
connect _WIRE_128.ae_stage2, _T_1769
node _T_1770 = bits(_WIRE_129, 18, 18)
connect _WIRE_128.ae_final, _T_1770
node _T_1771 = bits(_WIRE_129, 19, 19)
connect _WIRE_128.ae_ptw, _T_1771
node _T_1772 = bits(_WIRE_129, 20, 20)
connect _WIRE_128.g, _T_1772
node _T_1773 = bits(_WIRE_129, 21, 21)
connect _WIRE_128.u, _T_1773
node _T_1774 = bits(_WIRE_129, 41, 22)
connect _WIRE_128.ppn, _T_1774
wire _WIRE_130 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_131 : UInt<42>
connect _WIRE_131, sectored_entries[0][4].data[1]
node _T_1775 = bits(_WIRE_131, 0, 0)
connect _WIRE_130.fragmented_superpage, _T_1775
node _T_1776 = bits(_WIRE_131, 1, 1)
connect _WIRE_130.c, _T_1776
node _T_1777 = bits(_WIRE_131, 2, 2)
connect _WIRE_130.eff, _T_1777
node _T_1778 = bits(_WIRE_131, 3, 3)
connect _WIRE_130.paa, _T_1778
node _T_1779 = bits(_WIRE_131, 4, 4)
connect _WIRE_130.pal, _T_1779
node _T_1780 = bits(_WIRE_131, 5, 5)
connect _WIRE_130.ppp, _T_1780
node _T_1781 = bits(_WIRE_131, 6, 6)
connect _WIRE_130.pr, _T_1781
node _T_1782 = bits(_WIRE_131, 7, 7)
connect _WIRE_130.px, _T_1782
node _T_1783 = bits(_WIRE_131, 8, 8)
connect _WIRE_130.pw, _T_1783
node _T_1784 = bits(_WIRE_131, 9, 9)
connect _WIRE_130.hr, _T_1784
node _T_1785 = bits(_WIRE_131, 10, 10)
connect _WIRE_130.hx, _T_1785
node _T_1786 = bits(_WIRE_131, 11, 11)
connect _WIRE_130.hw, _T_1786
node _T_1787 = bits(_WIRE_131, 12, 12)
connect _WIRE_130.sr, _T_1787
node _T_1788 = bits(_WIRE_131, 13, 13)
connect _WIRE_130.sx, _T_1788
node _T_1789 = bits(_WIRE_131, 14, 14)
connect _WIRE_130.sw, _T_1789
node _T_1790 = bits(_WIRE_131, 15, 15)
connect _WIRE_130.gf, _T_1790
node _T_1791 = bits(_WIRE_131, 16, 16)
connect _WIRE_130.pf, _T_1791
node _T_1792 = bits(_WIRE_131, 17, 17)
connect _WIRE_130.ae_stage2, _T_1792
node _T_1793 = bits(_WIRE_131, 18, 18)
connect _WIRE_130.ae_final, _T_1793
node _T_1794 = bits(_WIRE_131, 19, 19)
connect _WIRE_130.ae_ptw, _T_1794
node _T_1795 = bits(_WIRE_131, 20, 20)
connect _WIRE_130.g, _T_1795
node _T_1796 = bits(_WIRE_131, 21, 21)
connect _WIRE_130.u, _T_1796
node _T_1797 = bits(_WIRE_131, 41, 22)
connect _WIRE_130.ppn, _T_1797
wire _WIRE_132 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_133 : UInt<42>
connect _WIRE_133, sectored_entries[0][4].data[2]
node _T_1798 = bits(_WIRE_133, 0, 0)
connect _WIRE_132.fragmented_superpage, _T_1798
node _T_1799 = bits(_WIRE_133, 1, 1)
connect _WIRE_132.c, _T_1799
node _T_1800 = bits(_WIRE_133, 2, 2)
connect _WIRE_132.eff, _T_1800
node _T_1801 = bits(_WIRE_133, 3, 3)
connect _WIRE_132.paa, _T_1801
node _T_1802 = bits(_WIRE_133, 4, 4)
connect _WIRE_132.pal, _T_1802
node _T_1803 = bits(_WIRE_133, 5, 5)
connect _WIRE_132.ppp, _T_1803
node _T_1804 = bits(_WIRE_133, 6, 6)
connect _WIRE_132.pr, _T_1804
node _T_1805 = bits(_WIRE_133, 7, 7)
connect _WIRE_132.px, _T_1805
node _T_1806 = bits(_WIRE_133, 8, 8)
connect _WIRE_132.pw, _T_1806
node _T_1807 = bits(_WIRE_133, 9, 9)
connect _WIRE_132.hr, _T_1807
node _T_1808 = bits(_WIRE_133, 10, 10)
connect _WIRE_132.hx, _T_1808
node _T_1809 = bits(_WIRE_133, 11, 11)
connect _WIRE_132.hw, _T_1809
node _T_1810 = bits(_WIRE_133, 12, 12)
connect _WIRE_132.sr, _T_1810
node _T_1811 = bits(_WIRE_133, 13, 13)
connect _WIRE_132.sx, _T_1811
node _T_1812 = bits(_WIRE_133, 14, 14)
connect _WIRE_132.sw, _T_1812
node _T_1813 = bits(_WIRE_133, 15, 15)
connect _WIRE_132.gf, _T_1813
node _T_1814 = bits(_WIRE_133, 16, 16)
connect _WIRE_132.pf, _T_1814
node _T_1815 = bits(_WIRE_133, 17, 17)
connect _WIRE_132.ae_stage2, _T_1815
node _T_1816 = bits(_WIRE_133, 18, 18)
connect _WIRE_132.ae_final, _T_1816
node _T_1817 = bits(_WIRE_133, 19, 19)
connect _WIRE_132.ae_ptw, _T_1817
node _T_1818 = bits(_WIRE_133, 20, 20)
connect _WIRE_132.g, _T_1818
node _T_1819 = bits(_WIRE_133, 21, 21)
connect _WIRE_132.u, _T_1819
node _T_1820 = bits(_WIRE_133, 41, 22)
connect _WIRE_132.ppn, _T_1820
wire _WIRE_134 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_135 : UInt<42>
connect _WIRE_135, sectored_entries[0][4].data[3]
node _T_1821 = bits(_WIRE_135, 0, 0)
connect _WIRE_134.fragmented_superpage, _T_1821
node _T_1822 = bits(_WIRE_135, 1, 1)
connect _WIRE_134.c, _T_1822
node _T_1823 = bits(_WIRE_135, 2, 2)
connect _WIRE_134.eff, _T_1823
node _T_1824 = bits(_WIRE_135, 3, 3)
connect _WIRE_134.paa, _T_1824
node _T_1825 = bits(_WIRE_135, 4, 4)
connect _WIRE_134.pal, _T_1825
node _T_1826 = bits(_WIRE_135, 5, 5)
connect _WIRE_134.ppp, _T_1826
node _T_1827 = bits(_WIRE_135, 6, 6)
connect _WIRE_134.pr, _T_1827
node _T_1828 = bits(_WIRE_135, 7, 7)
connect _WIRE_134.px, _T_1828
node _T_1829 = bits(_WIRE_135, 8, 8)
connect _WIRE_134.pw, _T_1829
node _T_1830 = bits(_WIRE_135, 9, 9)
connect _WIRE_134.hr, _T_1830
node _T_1831 = bits(_WIRE_135, 10, 10)
connect _WIRE_134.hx, _T_1831
node _T_1832 = bits(_WIRE_135, 11, 11)
connect _WIRE_134.hw, _T_1832
node _T_1833 = bits(_WIRE_135, 12, 12)
connect _WIRE_134.sr, _T_1833
node _T_1834 = bits(_WIRE_135, 13, 13)
connect _WIRE_134.sx, _T_1834
node _T_1835 = bits(_WIRE_135, 14, 14)
connect _WIRE_134.sw, _T_1835
node _T_1836 = bits(_WIRE_135, 15, 15)
connect _WIRE_134.gf, _T_1836
node _T_1837 = bits(_WIRE_135, 16, 16)
connect _WIRE_134.pf, _T_1837
node _T_1838 = bits(_WIRE_135, 17, 17)
connect _WIRE_134.ae_stage2, _T_1838
node _T_1839 = bits(_WIRE_135, 18, 18)
connect _WIRE_134.ae_final, _T_1839
node _T_1840 = bits(_WIRE_135, 19, 19)
connect _WIRE_134.ae_ptw, _T_1840
node _T_1841 = bits(_WIRE_135, 20, 20)
connect _WIRE_134.g, _T_1841
node _T_1842 = bits(_WIRE_135, 21, 21)
connect _WIRE_134.u, _T_1842
node _T_1843 = bits(_WIRE_135, 41, 22)
connect _WIRE_134.ppn, _T_1843
node _T_1844 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1845 = bits(vpn, 1, 0)
node _T_1846 = eq(UInt<1>(0h0), _T_1845)
node _T_1847 = and(_T_1844, _T_1846)
when _T_1847 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
node _T_1848 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1849 = bits(vpn, 1, 0)
node _T_1850 = eq(UInt<1>(0h1), _T_1849)
node _T_1851 = and(_T_1848, _T_1850)
when _T_1851 :
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
node _T_1852 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1853 = bits(vpn, 1, 0)
node _T_1854 = eq(UInt<2>(0h2), _T_1853)
node _T_1855 = and(_T_1852, _T_1854)
when _T_1855 :
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
node _T_1856 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1857 = bits(vpn, 1, 0)
node _T_1858 = eq(UInt<2>(0h3), _T_1857)
node _T_1859 = and(_T_1856, _T_1858)
when _T_1859 :
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
node _T_1860 = xor(sectored_entries[0][4].tag_vpn, vpn)
node _T_1861 = shr(_T_1860, 18)
node _T_1862 = eq(_T_1861, UInt<1>(0h0))
when _T_1862 :
wire _WIRE_136 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_137 : UInt<42>
connect _WIRE_137, sectored_entries[0][4].data[0]
node _T_1863 = bits(_WIRE_137, 0, 0)
connect _WIRE_136.fragmented_superpage, _T_1863
node _T_1864 = bits(_WIRE_137, 1, 1)
connect _WIRE_136.c, _T_1864
node _T_1865 = bits(_WIRE_137, 2, 2)
connect _WIRE_136.eff, _T_1865
node _T_1866 = bits(_WIRE_137, 3, 3)
connect _WIRE_136.paa, _T_1866
node _T_1867 = bits(_WIRE_137, 4, 4)
connect _WIRE_136.pal, _T_1867
node _T_1868 = bits(_WIRE_137, 5, 5)
connect _WIRE_136.ppp, _T_1868
node _T_1869 = bits(_WIRE_137, 6, 6)
connect _WIRE_136.pr, _T_1869
node _T_1870 = bits(_WIRE_137, 7, 7)
connect _WIRE_136.px, _T_1870
node _T_1871 = bits(_WIRE_137, 8, 8)
connect _WIRE_136.pw, _T_1871
node _T_1872 = bits(_WIRE_137, 9, 9)
connect _WIRE_136.hr, _T_1872
node _T_1873 = bits(_WIRE_137, 10, 10)
connect _WIRE_136.hx, _T_1873
node _T_1874 = bits(_WIRE_137, 11, 11)
connect _WIRE_136.hw, _T_1874
node _T_1875 = bits(_WIRE_137, 12, 12)
connect _WIRE_136.sr, _T_1875
node _T_1876 = bits(_WIRE_137, 13, 13)
connect _WIRE_136.sx, _T_1876
node _T_1877 = bits(_WIRE_137, 14, 14)
connect _WIRE_136.sw, _T_1877
node _T_1878 = bits(_WIRE_137, 15, 15)
connect _WIRE_136.gf, _T_1878
node _T_1879 = bits(_WIRE_137, 16, 16)
connect _WIRE_136.pf, _T_1879
node _T_1880 = bits(_WIRE_137, 17, 17)
connect _WIRE_136.ae_stage2, _T_1880
node _T_1881 = bits(_WIRE_137, 18, 18)
connect _WIRE_136.ae_final, _T_1881
node _T_1882 = bits(_WIRE_137, 19, 19)
connect _WIRE_136.ae_ptw, _T_1882
node _T_1883 = bits(_WIRE_137, 20, 20)
connect _WIRE_136.g, _T_1883
node _T_1884 = bits(_WIRE_137, 21, 21)
connect _WIRE_136.u, _T_1884
node _T_1885 = bits(_WIRE_137, 41, 22)
connect _WIRE_136.ppn, _T_1885
wire _WIRE_138 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_139 : UInt<42>
connect _WIRE_139, sectored_entries[0][4].data[1]
node _T_1886 = bits(_WIRE_139, 0, 0)
connect _WIRE_138.fragmented_superpage, _T_1886
node _T_1887 = bits(_WIRE_139, 1, 1)
connect _WIRE_138.c, _T_1887
node _T_1888 = bits(_WIRE_139, 2, 2)
connect _WIRE_138.eff, _T_1888
node _T_1889 = bits(_WIRE_139, 3, 3)
connect _WIRE_138.paa, _T_1889
node _T_1890 = bits(_WIRE_139, 4, 4)
connect _WIRE_138.pal, _T_1890
node _T_1891 = bits(_WIRE_139, 5, 5)
connect _WIRE_138.ppp, _T_1891
node _T_1892 = bits(_WIRE_139, 6, 6)
connect _WIRE_138.pr, _T_1892
node _T_1893 = bits(_WIRE_139, 7, 7)
connect _WIRE_138.px, _T_1893
node _T_1894 = bits(_WIRE_139, 8, 8)
connect _WIRE_138.pw, _T_1894
node _T_1895 = bits(_WIRE_139, 9, 9)
connect _WIRE_138.hr, _T_1895
node _T_1896 = bits(_WIRE_139, 10, 10)
connect _WIRE_138.hx, _T_1896
node _T_1897 = bits(_WIRE_139, 11, 11)
connect _WIRE_138.hw, _T_1897
node _T_1898 = bits(_WIRE_139, 12, 12)
connect _WIRE_138.sr, _T_1898
node _T_1899 = bits(_WIRE_139, 13, 13)
connect _WIRE_138.sx, _T_1899
node _T_1900 = bits(_WIRE_139, 14, 14)
connect _WIRE_138.sw, _T_1900
node _T_1901 = bits(_WIRE_139, 15, 15)
connect _WIRE_138.gf, _T_1901
node _T_1902 = bits(_WIRE_139, 16, 16)
connect _WIRE_138.pf, _T_1902
node _T_1903 = bits(_WIRE_139, 17, 17)
connect _WIRE_138.ae_stage2, _T_1903
node _T_1904 = bits(_WIRE_139, 18, 18)
connect _WIRE_138.ae_final, _T_1904
node _T_1905 = bits(_WIRE_139, 19, 19)
connect _WIRE_138.ae_ptw, _T_1905
node _T_1906 = bits(_WIRE_139, 20, 20)
connect _WIRE_138.g, _T_1906
node _T_1907 = bits(_WIRE_139, 21, 21)
connect _WIRE_138.u, _T_1907
node _T_1908 = bits(_WIRE_139, 41, 22)
connect _WIRE_138.ppn, _T_1908
wire _WIRE_140 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_141 : UInt<42>
connect _WIRE_141, sectored_entries[0][4].data[2]
node _T_1909 = bits(_WIRE_141, 0, 0)
connect _WIRE_140.fragmented_superpage, _T_1909
node _T_1910 = bits(_WIRE_141, 1, 1)
connect _WIRE_140.c, _T_1910
node _T_1911 = bits(_WIRE_141, 2, 2)
connect _WIRE_140.eff, _T_1911
node _T_1912 = bits(_WIRE_141, 3, 3)
connect _WIRE_140.paa, _T_1912
node _T_1913 = bits(_WIRE_141, 4, 4)
connect _WIRE_140.pal, _T_1913
node _T_1914 = bits(_WIRE_141, 5, 5)
connect _WIRE_140.ppp, _T_1914
node _T_1915 = bits(_WIRE_141, 6, 6)
connect _WIRE_140.pr, _T_1915
node _T_1916 = bits(_WIRE_141, 7, 7)
connect _WIRE_140.px, _T_1916
node _T_1917 = bits(_WIRE_141, 8, 8)
connect _WIRE_140.pw, _T_1917
node _T_1918 = bits(_WIRE_141, 9, 9)
connect _WIRE_140.hr, _T_1918
node _T_1919 = bits(_WIRE_141, 10, 10)
connect _WIRE_140.hx, _T_1919
node _T_1920 = bits(_WIRE_141, 11, 11)
connect _WIRE_140.hw, _T_1920
node _T_1921 = bits(_WIRE_141, 12, 12)
connect _WIRE_140.sr, _T_1921
node _T_1922 = bits(_WIRE_141, 13, 13)
connect _WIRE_140.sx, _T_1922
node _T_1923 = bits(_WIRE_141, 14, 14)
connect _WIRE_140.sw, _T_1923
node _T_1924 = bits(_WIRE_141, 15, 15)
connect _WIRE_140.gf, _T_1924
node _T_1925 = bits(_WIRE_141, 16, 16)
connect _WIRE_140.pf, _T_1925
node _T_1926 = bits(_WIRE_141, 17, 17)
connect _WIRE_140.ae_stage2, _T_1926
node _T_1927 = bits(_WIRE_141, 18, 18)
connect _WIRE_140.ae_final, _T_1927
node _T_1928 = bits(_WIRE_141, 19, 19)
connect _WIRE_140.ae_ptw, _T_1928
node _T_1929 = bits(_WIRE_141, 20, 20)
connect _WIRE_140.g, _T_1929
node _T_1930 = bits(_WIRE_141, 21, 21)
connect _WIRE_140.u, _T_1930
node _T_1931 = bits(_WIRE_141, 41, 22)
connect _WIRE_140.ppn, _T_1931
wire _WIRE_142 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_143 : UInt<42>
connect _WIRE_143, sectored_entries[0][4].data[3]
node _T_1932 = bits(_WIRE_143, 0, 0)
connect _WIRE_142.fragmented_superpage, _T_1932
node _T_1933 = bits(_WIRE_143, 1, 1)
connect _WIRE_142.c, _T_1933
node _T_1934 = bits(_WIRE_143, 2, 2)
connect _WIRE_142.eff, _T_1934
node _T_1935 = bits(_WIRE_143, 3, 3)
connect _WIRE_142.paa, _T_1935
node _T_1936 = bits(_WIRE_143, 4, 4)
connect _WIRE_142.pal, _T_1936
node _T_1937 = bits(_WIRE_143, 5, 5)
connect _WIRE_142.ppp, _T_1937
node _T_1938 = bits(_WIRE_143, 6, 6)
connect _WIRE_142.pr, _T_1938
node _T_1939 = bits(_WIRE_143, 7, 7)
connect _WIRE_142.px, _T_1939
node _T_1940 = bits(_WIRE_143, 8, 8)
connect _WIRE_142.pw, _T_1940
node _T_1941 = bits(_WIRE_143, 9, 9)
connect _WIRE_142.hr, _T_1941
node _T_1942 = bits(_WIRE_143, 10, 10)
connect _WIRE_142.hx, _T_1942
node _T_1943 = bits(_WIRE_143, 11, 11)
connect _WIRE_142.hw, _T_1943
node _T_1944 = bits(_WIRE_143, 12, 12)
connect _WIRE_142.sr, _T_1944
node _T_1945 = bits(_WIRE_143, 13, 13)
connect _WIRE_142.sx, _T_1945
node _T_1946 = bits(_WIRE_143, 14, 14)
connect _WIRE_142.sw, _T_1946
node _T_1947 = bits(_WIRE_143, 15, 15)
connect _WIRE_142.gf, _T_1947
node _T_1948 = bits(_WIRE_143, 16, 16)
connect _WIRE_142.pf, _T_1948
node _T_1949 = bits(_WIRE_143, 17, 17)
connect _WIRE_142.ae_stage2, _T_1949
node _T_1950 = bits(_WIRE_143, 18, 18)
connect _WIRE_142.ae_final, _T_1950
node _T_1951 = bits(_WIRE_143, 19, 19)
connect _WIRE_142.ae_ptw, _T_1951
node _T_1952 = bits(_WIRE_143, 20, 20)
connect _WIRE_142.g, _T_1952
node _T_1953 = bits(_WIRE_143, 21, 21)
connect _WIRE_142.u, _T_1953
node _T_1954 = bits(_WIRE_143, 41, 22)
connect _WIRE_142.ppn, _T_1954
node _T_1955 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1956 = and(_T_1955, _WIRE_136.fragmented_superpage)
when _T_1956 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
node _T_1957 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1958 = and(_T_1957, _WIRE_138.fragmented_superpage)
when _T_1958 :
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
node _T_1959 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1960 = and(_T_1959, _WIRE_140.fragmented_superpage)
when _T_1960 :
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
node _T_1961 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1962 = and(_T_1961, _WIRE_142.fragmented_superpage)
when _T_1962 :
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
else :
node _T_1963 = eq(hg_4, UInt<1>(0h0))
node _T_1964 = and(_T_1963, io.sfence.bits.rs2)
when _T_1964 :
wire _WIRE_144 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_145 : UInt<42>
connect _WIRE_145, sectored_entries[0][4].data[0]
node _T_1965 = bits(_WIRE_145, 0, 0)
connect _WIRE_144.fragmented_superpage, _T_1965
node _T_1966 = bits(_WIRE_145, 1, 1)
connect _WIRE_144.c, _T_1966
node _T_1967 = bits(_WIRE_145, 2, 2)
connect _WIRE_144.eff, _T_1967
node _T_1968 = bits(_WIRE_145, 3, 3)
connect _WIRE_144.paa, _T_1968
node _T_1969 = bits(_WIRE_145, 4, 4)
connect _WIRE_144.pal, _T_1969
node _T_1970 = bits(_WIRE_145, 5, 5)
connect _WIRE_144.ppp, _T_1970
node _T_1971 = bits(_WIRE_145, 6, 6)
connect _WIRE_144.pr, _T_1971
node _T_1972 = bits(_WIRE_145, 7, 7)
connect _WIRE_144.px, _T_1972
node _T_1973 = bits(_WIRE_145, 8, 8)
connect _WIRE_144.pw, _T_1973
node _T_1974 = bits(_WIRE_145, 9, 9)
connect _WIRE_144.hr, _T_1974
node _T_1975 = bits(_WIRE_145, 10, 10)
connect _WIRE_144.hx, _T_1975
node _T_1976 = bits(_WIRE_145, 11, 11)
connect _WIRE_144.hw, _T_1976
node _T_1977 = bits(_WIRE_145, 12, 12)
connect _WIRE_144.sr, _T_1977
node _T_1978 = bits(_WIRE_145, 13, 13)
connect _WIRE_144.sx, _T_1978
node _T_1979 = bits(_WIRE_145, 14, 14)
connect _WIRE_144.sw, _T_1979
node _T_1980 = bits(_WIRE_145, 15, 15)
connect _WIRE_144.gf, _T_1980
node _T_1981 = bits(_WIRE_145, 16, 16)
connect _WIRE_144.pf, _T_1981
node _T_1982 = bits(_WIRE_145, 17, 17)
connect _WIRE_144.ae_stage2, _T_1982
node _T_1983 = bits(_WIRE_145, 18, 18)
connect _WIRE_144.ae_final, _T_1983
node _T_1984 = bits(_WIRE_145, 19, 19)
connect _WIRE_144.ae_ptw, _T_1984
node _T_1985 = bits(_WIRE_145, 20, 20)
connect _WIRE_144.g, _T_1985
node _T_1986 = bits(_WIRE_145, 21, 21)
connect _WIRE_144.u, _T_1986
node _T_1987 = bits(_WIRE_145, 41, 22)
connect _WIRE_144.ppn, _T_1987
wire _WIRE_146 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_147 : UInt<42>
connect _WIRE_147, sectored_entries[0][4].data[1]
node _T_1988 = bits(_WIRE_147, 0, 0)
connect _WIRE_146.fragmented_superpage, _T_1988
node _T_1989 = bits(_WIRE_147, 1, 1)
connect _WIRE_146.c, _T_1989
node _T_1990 = bits(_WIRE_147, 2, 2)
connect _WIRE_146.eff, _T_1990
node _T_1991 = bits(_WIRE_147, 3, 3)
connect _WIRE_146.paa, _T_1991
node _T_1992 = bits(_WIRE_147, 4, 4)
connect _WIRE_146.pal, _T_1992
node _T_1993 = bits(_WIRE_147, 5, 5)
connect _WIRE_146.ppp, _T_1993
node _T_1994 = bits(_WIRE_147, 6, 6)
connect _WIRE_146.pr, _T_1994
node _T_1995 = bits(_WIRE_147, 7, 7)
connect _WIRE_146.px, _T_1995
node _T_1996 = bits(_WIRE_147, 8, 8)
connect _WIRE_146.pw, _T_1996
node _T_1997 = bits(_WIRE_147, 9, 9)
connect _WIRE_146.hr, _T_1997
node _T_1998 = bits(_WIRE_147, 10, 10)
connect _WIRE_146.hx, _T_1998
node _T_1999 = bits(_WIRE_147, 11, 11)
connect _WIRE_146.hw, _T_1999
node _T_2000 = bits(_WIRE_147, 12, 12)
connect _WIRE_146.sr, _T_2000
node _T_2001 = bits(_WIRE_147, 13, 13)
connect _WIRE_146.sx, _T_2001
node _T_2002 = bits(_WIRE_147, 14, 14)
connect _WIRE_146.sw, _T_2002
node _T_2003 = bits(_WIRE_147, 15, 15)
connect _WIRE_146.gf, _T_2003
node _T_2004 = bits(_WIRE_147, 16, 16)
connect _WIRE_146.pf, _T_2004
node _T_2005 = bits(_WIRE_147, 17, 17)
connect _WIRE_146.ae_stage2, _T_2005
node _T_2006 = bits(_WIRE_147, 18, 18)
connect _WIRE_146.ae_final, _T_2006
node _T_2007 = bits(_WIRE_147, 19, 19)
connect _WIRE_146.ae_ptw, _T_2007
node _T_2008 = bits(_WIRE_147, 20, 20)
connect _WIRE_146.g, _T_2008
node _T_2009 = bits(_WIRE_147, 21, 21)
connect _WIRE_146.u, _T_2009
node _T_2010 = bits(_WIRE_147, 41, 22)
connect _WIRE_146.ppn, _T_2010
wire _WIRE_148 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_149 : UInt<42>
connect _WIRE_149, sectored_entries[0][4].data[2]
node _T_2011 = bits(_WIRE_149, 0, 0)
connect _WIRE_148.fragmented_superpage, _T_2011
node _T_2012 = bits(_WIRE_149, 1, 1)
connect _WIRE_148.c, _T_2012
node _T_2013 = bits(_WIRE_149, 2, 2)
connect _WIRE_148.eff, _T_2013
node _T_2014 = bits(_WIRE_149, 3, 3)
connect _WIRE_148.paa, _T_2014
node _T_2015 = bits(_WIRE_149, 4, 4)
connect _WIRE_148.pal, _T_2015
node _T_2016 = bits(_WIRE_149, 5, 5)
connect _WIRE_148.ppp, _T_2016
node _T_2017 = bits(_WIRE_149, 6, 6)
connect _WIRE_148.pr, _T_2017
node _T_2018 = bits(_WIRE_149, 7, 7)
connect _WIRE_148.px, _T_2018
node _T_2019 = bits(_WIRE_149, 8, 8)
connect _WIRE_148.pw, _T_2019
node _T_2020 = bits(_WIRE_149, 9, 9)
connect _WIRE_148.hr, _T_2020
node _T_2021 = bits(_WIRE_149, 10, 10)
connect _WIRE_148.hx, _T_2021
node _T_2022 = bits(_WIRE_149, 11, 11)
connect _WIRE_148.hw, _T_2022
node _T_2023 = bits(_WIRE_149, 12, 12)
connect _WIRE_148.sr, _T_2023
node _T_2024 = bits(_WIRE_149, 13, 13)
connect _WIRE_148.sx, _T_2024
node _T_2025 = bits(_WIRE_149, 14, 14)
connect _WIRE_148.sw, _T_2025
node _T_2026 = bits(_WIRE_149, 15, 15)
connect _WIRE_148.gf, _T_2026
node _T_2027 = bits(_WIRE_149, 16, 16)
connect _WIRE_148.pf, _T_2027
node _T_2028 = bits(_WIRE_149, 17, 17)
connect _WIRE_148.ae_stage2, _T_2028
node _T_2029 = bits(_WIRE_149, 18, 18)
connect _WIRE_148.ae_final, _T_2029
node _T_2030 = bits(_WIRE_149, 19, 19)
connect _WIRE_148.ae_ptw, _T_2030
node _T_2031 = bits(_WIRE_149, 20, 20)
connect _WIRE_148.g, _T_2031
node _T_2032 = bits(_WIRE_149, 21, 21)
connect _WIRE_148.u, _T_2032
node _T_2033 = bits(_WIRE_149, 41, 22)
connect _WIRE_148.ppn, _T_2033
wire _WIRE_150 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_151 : UInt<42>
connect _WIRE_151, sectored_entries[0][4].data[3]
node _T_2034 = bits(_WIRE_151, 0, 0)
connect _WIRE_150.fragmented_superpage, _T_2034
node _T_2035 = bits(_WIRE_151, 1, 1)
connect _WIRE_150.c, _T_2035
node _T_2036 = bits(_WIRE_151, 2, 2)
connect _WIRE_150.eff, _T_2036
node _T_2037 = bits(_WIRE_151, 3, 3)
connect _WIRE_150.paa, _T_2037
node _T_2038 = bits(_WIRE_151, 4, 4)
connect _WIRE_150.pal, _T_2038
node _T_2039 = bits(_WIRE_151, 5, 5)
connect _WIRE_150.ppp, _T_2039
node _T_2040 = bits(_WIRE_151, 6, 6)
connect _WIRE_150.pr, _T_2040
node _T_2041 = bits(_WIRE_151, 7, 7)
connect _WIRE_150.px, _T_2041
node _T_2042 = bits(_WIRE_151, 8, 8)
connect _WIRE_150.pw, _T_2042
node _T_2043 = bits(_WIRE_151, 9, 9)
connect _WIRE_150.hr, _T_2043
node _T_2044 = bits(_WIRE_151, 10, 10)
connect _WIRE_150.hx, _T_2044
node _T_2045 = bits(_WIRE_151, 11, 11)
connect _WIRE_150.hw, _T_2045
node _T_2046 = bits(_WIRE_151, 12, 12)
connect _WIRE_150.sr, _T_2046
node _T_2047 = bits(_WIRE_151, 13, 13)
connect _WIRE_150.sx, _T_2047
node _T_2048 = bits(_WIRE_151, 14, 14)
connect _WIRE_150.sw, _T_2048
node _T_2049 = bits(_WIRE_151, 15, 15)
connect _WIRE_150.gf, _T_2049
node _T_2050 = bits(_WIRE_151, 16, 16)
connect _WIRE_150.pf, _T_2050
node _T_2051 = bits(_WIRE_151, 17, 17)
connect _WIRE_150.ae_stage2, _T_2051
node _T_2052 = bits(_WIRE_151, 18, 18)
connect _WIRE_150.ae_final, _T_2052
node _T_2053 = bits(_WIRE_151, 19, 19)
connect _WIRE_150.ae_ptw, _T_2053
node _T_2054 = bits(_WIRE_151, 20, 20)
connect _WIRE_150.g, _T_2054
node _T_2055 = bits(_WIRE_151, 21, 21)
connect _WIRE_150.u, _T_2055
node _T_2056 = bits(_WIRE_151, 41, 22)
connect _WIRE_150.ppn, _T_2056
node _T_2057 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_2058 = eq(_WIRE_144.g, UInt<1>(0h0))
node _T_2059 = and(_T_2057, _T_2058)
when _T_2059 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
node _T_2060 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_2061 = eq(_WIRE_146.g, UInt<1>(0h0))
node _T_2062 = and(_T_2060, _T_2061)
when _T_2062 :
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
node _T_2063 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_2064 = eq(_WIRE_148.g, UInt<1>(0h0))
node _T_2065 = and(_T_2063, _T_2064)
when _T_2065 :
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
node _T_2066 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_2067 = eq(_WIRE_150.g, UInt<1>(0h0))
node _T_2068 = and(_T_2066, _T_2067)
when _T_2068 :
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
else :
node _T_2069 = or(hv_4, hg_4)
wire _WIRE_152 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_153 : UInt<42>
connect _WIRE_153, sectored_entries[0][4].data[0]
node _T_2070 = bits(_WIRE_153, 0, 0)
connect _WIRE_152.fragmented_superpage, _T_2070
node _T_2071 = bits(_WIRE_153, 1, 1)
connect _WIRE_152.c, _T_2071
node _T_2072 = bits(_WIRE_153, 2, 2)
connect _WIRE_152.eff, _T_2072
node _T_2073 = bits(_WIRE_153, 3, 3)
connect _WIRE_152.paa, _T_2073
node _T_2074 = bits(_WIRE_153, 4, 4)
connect _WIRE_152.pal, _T_2074
node _T_2075 = bits(_WIRE_153, 5, 5)
connect _WIRE_152.ppp, _T_2075
node _T_2076 = bits(_WIRE_153, 6, 6)
connect _WIRE_152.pr, _T_2076
node _T_2077 = bits(_WIRE_153, 7, 7)
connect _WIRE_152.px, _T_2077
node _T_2078 = bits(_WIRE_153, 8, 8)
connect _WIRE_152.pw, _T_2078
node _T_2079 = bits(_WIRE_153, 9, 9)
connect _WIRE_152.hr, _T_2079
node _T_2080 = bits(_WIRE_153, 10, 10)
connect _WIRE_152.hx, _T_2080
node _T_2081 = bits(_WIRE_153, 11, 11)
connect _WIRE_152.hw, _T_2081
node _T_2082 = bits(_WIRE_153, 12, 12)
connect _WIRE_152.sr, _T_2082
node _T_2083 = bits(_WIRE_153, 13, 13)
connect _WIRE_152.sx, _T_2083
node _T_2084 = bits(_WIRE_153, 14, 14)
connect _WIRE_152.sw, _T_2084
node _T_2085 = bits(_WIRE_153, 15, 15)
connect _WIRE_152.gf, _T_2085
node _T_2086 = bits(_WIRE_153, 16, 16)
connect _WIRE_152.pf, _T_2086
node _T_2087 = bits(_WIRE_153, 17, 17)
connect _WIRE_152.ae_stage2, _T_2087
node _T_2088 = bits(_WIRE_153, 18, 18)
connect _WIRE_152.ae_final, _T_2088
node _T_2089 = bits(_WIRE_153, 19, 19)
connect _WIRE_152.ae_ptw, _T_2089
node _T_2090 = bits(_WIRE_153, 20, 20)
connect _WIRE_152.g, _T_2090
node _T_2091 = bits(_WIRE_153, 21, 21)
connect _WIRE_152.u, _T_2091
node _T_2092 = bits(_WIRE_153, 41, 22)
connect _WIRE_152.ppn, _T_2092
wire _WIRE_154 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_155 : UInt<42>
connect _WIRE_155, sectored_entries[0][4].data[1]
node _T_2093 = bits(_WIRE_155, 0, 0)
connect _WIRE_154.fragmented_superpage, _T_2093
node _T_2094 = bits(_WIRE_155, 1, 1)
connect _WIRE_154.c, _T_2094
node _T_2095 = bits(_WIRE_155, 2, 2)
connect _WIRE_154.eff, _T_2095
node _T_2096 = bits(_WIRE_155, 3, 3)
connect _WIRE_154.paa, _T_2096
node _T_2097 = bits(_WIRE_155, 4, 4)
connect _WIRE_154.pal, _T_2097
node _T_2098 = bits(_WIRE_155, 5, 5)
connect _WIRE_154.ppp, _T_2098
node _T_2099 = bits(_WIRE_155, 6, 6)
connect _WIRE_154.pr, _T_2099
node _T_2100 = bits(_WIRE_155, 7, 7)
connect _WIRE_154.px, _T_2100
node _T_2101 = bits(_WIRE_155, 8, 8)
connect _WIRE_154.pw, _T_2101
node _T_2102 = bits(_WIRE_155, 9, 9)
connect _WIRE_154.hr, _T_2102
node _T_2103 = bits(_WIRE_155, 10, 10)
connect _WIRE_154.hx, _T_2103
node _T_2104 = bits(_WIRE_155, 11, 11)
connect _WIRE_154.hw, _T_2104
node _T_2105 = bits(_WIRE_155, 12, 12)
connect _WIRE_154.sr, _T_2105
node _T_2106 = bits(_WIRE_155, 13, 13)
connect _WIRE_154.sx, _T_2106
node _T_2107 = bits(_WIRE_155, 14, 14)
connect _WIRE_154.sw, _T_2107
node _T_2108 = bits(_WIRE_155, 15, 15)
connect _WIRE_154.gf, _T_2108
node _T_2109 = bits(_WIRE_155, 16, 16)
connect _WIRE_154.pf, _T_2109
node _T_2110 = bits(_WIRE_155, 17, 17)
connect _WIRE_154.ae_stage2, _T_2110
node _T_2111 = bits(_WIRE_155, 18, 18)
connect _WIRE_154.ae_final, _T_2111
node _T_2112 = bits(_WIRE_155, 19, 19)
connect _WIRE_154.ae_ptw, _T_2112
node _T_2113 = bits(_WIRE_155, 20, 20)
connect _WIRE_154.g, _T_2113
node _T_2114 = bits(_WIRE_155, 21, 21)
connect _WIRE_154.u, _T_2114
node _T_2115 = bits(_WIRE_155, 41, 22)
connect _WIRE_154.ppn, _T_2115
wire _WIRE_156 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_157 : UInt<42>
connect _WIRE_157, sectored_entries[0][4].data[2]
node _T_2116 = bits(_WIRE_157, 0, 0)
connect _WIRE_156.fragmented_superpage, _T_2116
node _T_2117 = bits(_WIRE_157, 1, 1)
connect _WIRE_156.c, _T_2117
node _T_2118 = bits(_WIRE_157, 2, 2)
connect _WIRE_156.eff, _T_2118
node _T_2119 = bits(_WIRE_157, 3, 3)
connect _WIRE_156.paa, _T_2119
node _T_2120 = bits(_WIRE_157, 4, 4)
connect _WIRE_156.pal, _T_2120
node _T_2121 = bits(_WIRE_157, 5, 5)
connect _WIRE_156.ppp, _T_2121
node _T_2122 = bits(_WIRE_157, 6, 6)
connect _WIRE_156.pr, _T_2122
node _T_2123 = bits(_WIRE_157, 7, 7)
connect _WIRE_156.px, _T_2123
node _T_2124 = bits(_WIRE_157, 8, 8)
connect _WIRE_156.pw, _T_2124
node _T_2125 = bits(_WIRE_157, 9, 9)
connect _WIRE_156.hr, _T_2125
node _T_2126 = bits(_WIRE_157, 10, 10)
connect _WIRE_156.hx, _T_2126
node _T_2127 = bits(_WIRE_157, 11, 11)
connect _WIRE_156.hw, _T_2127
node _T_2128 = bits(_WIRE_157, 12, 12)
connect _WIRE_156.sr, _T_2128
node _T_2129 = bits(_WIRE_157, 13, 13)
connect _WIRE_156.sx, _T_2129
node _T_2130 = bits(_WIRE_157, 14, 14)
connect _WIRE_156.sw, _T_2130
node _T_2131 = bits(_WIRE_157, 15, 15)
connect _WIRE_156.gf, _T_2131
node _T_2132 = bits(_WIRE_157, 16, 16)
connect _WIRE_156.pf, _T_2132
node _T_2133 = bits(_WIRE_157, 17, 17)
connect _WIRE_156.ae_stage2, _T_2133
node _T_2134 = bits(_WIRE_157, 18, 18)
connect _WIRE_156.ae_final, _T_2134
node _T_2135 = bits(_WIRE_157, 19, 19)
connect _WIRE_156.ae_ptw, _T_2135
node _T_2136 = bits(_WIRE_157, 20, 20)
connect _WIRE_156.g, _T_2136
node _T_2137 = bits(_WIRE_157, 21, 21)
connect _WIRE_156.u, _T_2137
node _T_2138 = bits(_WIRE_157, 41, 22)
connect _WIRE_156.ppn, _T_2138
wire _WIRE_158 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_159 : UInt<42>
connect _WIRE_159, sectored_entries[0][4].data[3]
node _T_2139 = bits(_WIRE_159, 0, 0)
connect _WIRE_158.fragmented_superpage, _T_2139
node _T_2140 = bits(_WIRE_159, 1, 1)
connect _WIRE_158.c, _T_2140
node _T_2141 = bits(_WIRE_159, 2, 2)
connect _WIRE_158.eff, _T_2141
node _T_2142 = bits(_WIRE_159, 3, 3)
connect _WIRE_158.paa, _T_2142
node _T_2143 = bits(_WIRE_159, 4, 4)
connect _WIRE_158.pal, _T_2143
node _T_2144 = bits(_WIRE_159, 5, 5)
connect _WIRE_158.ppp, _T_2144
node _T_2145 = bits(_WIRE_159, 6, 6)
connect _WIRE_158.pr, _T_2145
node _T_2146 = bits(_WIRE_159, 7, 7)
connect _WIRE_158.px, _T_2146
node _T_2147 = bits(_WIRE_159, 8, 8)
connect _WIRE_158.pw, _T_2147
node _T_2148 = bits(_WIRE_159, 9, 9)
connect _WIRE_158.hr, _T_2148
node _T_2149 = bits(_WIRE_159, 10, 10)
connect _WIRE_158.hx, _T_2149
node _T_2150 = bits(_WIRE_159, 11, 11)
connect _WIRE_158.hw, _T_2150
node _T_2151 = bits(_WIRE_159, 12, 12)
connect _WIRE_158.sr, _T_2151
node _T_2152 = bits(_WIRE_159, 13, 13)
connect _WIRE_158.sx, _T_2152
node _T_2153 = bits(_WIRE_159, 14, 14)
connect _WIRE_158.sw, _T_2153
node _T_2154 = bits(_WIRE_159, 15, 15)
connect _WIRE_158.gf, _T_2154
node _T_2155 = bits(_WIRE_159, 16, 16)
connect _WIRE_158.pf, _T_2155
node _T_2156 = bits(_WIRE_159, 17, 17)
connect _WIRE_158.ae_stage2, _T_2156
node _T_2157 = bits(_WIRE_159, 18, 18)
connect _WIRE_158.ae_final, _T_2157
node _T_2158 = bits(_WIRE_159, 19, 19)
connect _WIRE_158.ae_ptw, _T_2158
node _T_2159 = bits(_WIRE_159, 20, 20)
connect _WIRE_158.g, _T_2159
node _T_2160 = bits(_WIRE_159, 21, 21)
connect _WIRE_158.u, _T_2160
node _T_2161 = bits(_WIRE_159, 41, 22)
connect _WIRE_158.ppn, _T_2161
node _T_2162 = eq(sectored_entries[0][4].tag_v, _T_2069)
when _T_2162 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
node _T_2163 = eq(sectored_entries[0][4].tag_v, _T_2069)
when _T_2163 :
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
node _T_2164 = eq(sectored_entries[0][4].tag_v, _T_2069)
when _T_2164 :
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
node _T_2165 = eq(sectored_entries[0][4].tag_v, _T_2069)
when _T_2165 :
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
node hv_5 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_5 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_2166 = eq(hg_5, UInt<1>(0h0))
node _T_2167 = and(_T_2166, io.sfence.bits.rs1)
when _T_2167 :
node _T_2168 = xor(sectored_entries[0][5].tag_vpn, vpn)
node _T_2169 = shr(_T_2168, 2)
node _T_2170 = eq(_T_2169, UInt<1>(0h0))
node _T_2171 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2172 = and(_T_2170, _T_2171)
when _T_2172 :
wire _WIRE_160 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_161 : UInt<42>
connect _WIRE_161, sectored_entries[0][5].data[0]
node _T_2173 = bits(_WIRE_161, 0, 0)
connect _WIRE_160.fragmented_superpage, _T_2173
node _T_2174 = bits(_WIRE_161, 1, 1)
connect _WIRE_160.c, _T_2174
node _T_2175 = bits(_WIRE_161, 2, 2)
connect _WIRE_160.eff, _T_2175
node _T_2176 = bits(_WIRE_161, 3, 3)
connect _WIRE_160.paa, _T_2176
node _T_2177 = bits(_WIRE_161, 4, 4)
connect _WIRE_160.pal, _T_2177
node _T_2178 = bits(_WIRE_161, 5, 5)
connect _WIRE_160.ppp, _T_2178
node _T_2179 = bits(_WIRE_161, 6, 6)
connect _WIRE_160.pr, _T_2179
node _T_2180 = bits(_WIRE_161, 7, 7)
connect _WIRE_160.px, _T_2180
node _T_2181 = bits(_WIRE_161, 8, 8)
connect _WIRE_160.pw, _T_2181
node _T_2182 = bits(_WIRE_161, 9, 9)
connect _WIRE_160.hr, _T_2182
node _T_2183 = bits(_WIRE_161, 10, 10)
connect _WIRE_160.hx, _T_2183
node _T_2184 = bits(_WIRE_161, 11, 11)
connect _WIRE_160.hw, _T_2184
node _T_2185 = bits(_WIRE_161, 12, 12)
connect _WIRE_160.sr, _T_2185
node _T_2186 = bits(_WIRE_161, 13, 13)
connect _WIRE_160.sx, _T_2186
node _T_2187 = bits(_WIRE_161, 14, 14)
connect _WIRE_160.sw, _T_2187
node _T_2188 = bits(_WIRE_161, 15, 15)
connect _WIRE_160.gf, _T_2188
node _T_2189 = bits(_WIRE_161, 16, 16)
connect _WIRE_160.pf, _T_2189
node _T_2190 = bits(_WIRE_161, 17, 17)
connect _WIRE_160.ae_stage2, _T_2190
node _T_2191 = bits(_WIRE_161, 18, 18)
connect _WIRE_160.ae_final, _T_2191
node _T_2192 = bits(_WIRE_161, 19, 19)
connect _WIRE_160.ae_ptw, _T_2192
node _T_2193 = bits(_WIRE_161, 20, 20)
connect _WIRE_160.g, _T_2193
node _T_2194 = bits(_WIRE_161, 21, 21)
connect _WIRE_160.u, _T_2194
node _T_2195 = bits(_WIRE_161, 41, 22)
connect _WIRE_160.ppn, _T_2195
wire _WIRE_162 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_163 : UInt<42>
connect _WIRE_163, sectored_entries[0][5].data[1]
node _T_2196 = bits(_WIRE_163, 0, 0)
connect _WIRE_162.fragmented_superpage, _T_2196
node _T_2197 = bits(_WIRE_163, 1, 1)
connect _WIRE_162.c, _T_2197
node _T_2198 = bits(_WIRE_163, 2, 2)
connect _WIRE_162.eff, _T_2198
node _T_2199 = bits(_WIRE_163, 3, 3)
connect _WIRE_162.paa, _T_2199
node _T_2200 = bits(_WIRE_163, 4, 4)
connect _WIRE_162.pal, _T_2200
node _T_2201 = bits(_WIRE_163, 5, 5)
connect _WIRE_162.ppp, _T_2201
node _T_2202 = bits(_WIRE_163, 6, 6)
connect _WIRE_162.pr, _T_2202
node _T_2203 = bits(_WIRE_163, 7, 7)
connect _WIRE_162.px, _T_2203
node _T_2204 = bits(_WIRE_163, 8, 8)
connect _WIRE_162.pw, _T_2204
node _T_2205 = bits(_WIRE_163, 9, 9)
connect _WIRE_162.hr, _T_2205
node _T_2206 = bits(_WIRE_163, 10, 10)
connect _WIRE_162.hx, _T_2206
node _T_2207 = bits(_WIRE_163, 11, 11)
connect _WIRE_162.hw, _T_2207
node _T_2208 = bits(_WIRE_163, 12, 12)
connect _WIRE_162.sr, _T_2208
node _T_2209 = bits(_WIRE_163, 13, 13)
connect _WIRE_162.sx, _T_2209
node _T_2210 = bits(_WIRE_163, 14, 14)
connect _WIRE_162.sw, _T_2210
node _T_2211 = bits(_WIRE_163, 15, 15)
connect _WIRE_162.gf, _T_2211
node _T_2212 = bits(_WIRE_163, 16, 16)
connect _WIRE_162.pf, _T_2212
node _T_2213 = bits(_WIRE_163, 17, 17)
connect _WIRE_162.ae_stage2, _T_2213
node _T_2214 = bits(_WIRE_163, 18, 18)
connect _WIRE_162.ae_final, _T_2214
node _T_2215 = bits(_WIRE_163, 19, 19)
connect _WIRE_162.ae_ptw, _T_2215
node _T_2216 = bits(_WIRE_163, 20, 20)
connect _WIRE_162.g, _T_2216
node _T_2217 = bits(_WIRE_163, 21, 21)
connect _WIRE_162.u, _T_2217
node _T_2218 = bits(_WIRE_163, 41, 22)
connect _WIRE_162.ppn, _T_2218
wire _WIRE_164 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_165 : UInt<42>
connect _WIRE_165, sectored_entries[0][5].data[2]
node _T_2219 = bits(_WIRE_165, 0, 0)
connect _WIRE_164.fragmented_superpage, _T_2219
node _T_2220 = bits(_WIRE_165, 1, 1)
connect _WIRE_164.c, _T_2220
node _T_2221 = bits(_WIRE_165, 2, 2)
connect _WIRE_164.eff, _T_2221
node _T_2222 = bits(_WIRE_165, 3, 3)
connect _WIRE_164.paa, _T_2222
node _T_2223 = bits(_WIRE_165, 4, 4)
connect _WIRE_164.pal, _T_2223
node _T_2224 = bits(_WIRE_165, 5, 5)
connect _WIRE_164.ppp, _T_2224
node _T_2225 = bits(_WIRE_165, 6, 6)
connect _WIRE_164.pr, _T_2225
node _T_2226 = bits(_WIRE_165, 7, 7)
connect _WIRE_164.px, _T_2226
node _T_2227 = bits(_WIRE_165, 8, 8)
connect _WIRE_164.pw, _T_2227
node _T_2228 = bits(_WIRE_165, 9, 9)
connect _WIRE_164.hr, _T_2228
node _T_2229 = bits(_WIRE_165, 10, 10)
connect _WIRE_164.hx, _T_2229
node _T_2230 = bits(_WIRE_165, 11, 11)
connect _WIRE_164.hw, _T_2230
node _T_2231 = bits(_WIRE_165, 12, 12)
connect _WIRE_164.sr, _T_2231
node _T_2232 = bits(_WIRE_165, 13, 13)
connect _WIRE_164.sx, _T_2232
node _T_2233 = bits(_WIRE_165, 14, 14)
connect _WIRE_164.sw, _T_2233
node _T_2234 = bits(_WIRE_165, 15, 15)
connect _WIRE_164.gf, _T_2234
node _T_2235 = bits(_WIRE_165, 16, 16)
connect _WIRE_164.pf, _T_2235
node _T_2236 = bits(_WIRE_165, 17, 17)
connect _WIRE_164.ae_stage2, _T_2236
node _T_2237 = bits(_WIRE_165, 18, 18)
connect _WIRE_164.ae_final, _T_2237
node _T_2238 = bits(_WIRE_165, 19, 19)
connect _WIRE_164.ae_ptw, _T_2238
node _T_2239 = bits(_WIRE_165, 20, 20)
connect _WIRE_164.g, _T_2239
node _T_2240 = bits(_WIRE_165, 21, 21)
connect _WIRE_164.u, _T_2240
node _T_2241 = bits(_WIRE_165, 41, 22)
connect _WIRE_164.ppn, _T_2241
wire _WIRE_166 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_167 : UInt<42>
connect _WIRE_167, sectored_entries[0][5].data[3]
node _T_2242 = bits(_WIRE_167, 0, 0)
connect _WIRE_166.fragmented_superpage, _T_2242
node _T_2243 = bits(_WIRE_167, 1, 1)
connect _WIRE_166.c, _T_2243
node _T_2244 = bits(_WIRE_167, 2, 2)
connect _WIRE_166.eff, _T_2244
node _T_2245 = bits(_WIRE_167, 3, 3)
connect _WIRE_166.paa, _T_2245
node _T_2246 = bits(_WIRE_167, 4, 4)
connect _WIRE_166.pal, _T_2246
node _T_2247 = bits(_WIRE_167, 5, 5)
connect _WIRE_166.ppp, _T_2247
node _T_2248 = bits(_WIRE_167, 6, 6)
connect _WIRE_166.pr, _T_2248
node _T_2249 = bits(_WIRE_167, 7, 7)
connect _WIRE_166.px, _T_2249
node _T_2250 = bits(_WIRE_167, 8, 8)
connect _WIRE_166.pw, _T_2250
node _T_2251 = bits(_WIRE_167, 9, 9)
connect _WIRE_166.hr, _T_2251
node _T_2252 = bits(_WIRE_167, 10, 10)
connect _WIRE_166.hx, _T_2252
node _T_2253 = bits(_WIRE_167, 11, 11)
connect _WIRE_166.hw, _T_2253
node _T_2254 = bits(_WIRE_167, 12, 12)
connect _WIRE_166.sr, _T_2254
node _T_2255 = bits(_WIRE_167, 13, 13)
connect _WIRE_166.sx, _T_2255
node _T_2256 = bits(_WIRE_167, 14, 14)
connect _WIRE_166.sw, _T_2256
node _T_2257 = bits(_WIRE_167, 15, 15)
connect _WIRE_166.gf, _T_2257
node _T_2258 = bits(_WIRE_167, 16, 16)
connect _WIRE_166.pf, _T_2258
node _T_2259 = bits(_WIRE_167, 17, 17)
connect _WIRE_166.ae_stage2, _T_2259
node _T_2260 = bits(_WIRE_167, 18, 18)
connect _WIRE_166.ae_final, _T_2260
node _T_2261 = bits(_WIRE_167, 19, 19)
connect _WIRE_166.ae_ptw, _T_2261
node _T_2262 = bits(_WIRE_167, 20, 20)
connect _WIRE_166.g, _T_2262
node _T_2263 = bits(_WIRE_167, 21, 21)
connect _WIRE_166.u, _T_2263
node _T_2264 = bits(_WIRE_167, 41, 22)
connect _WIRE_166.ppn, _T_2264
node _T_2265 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2266 = bits(vpn, 1, 0)
node _T_2267 = eq(UInt<1>(0h0), _T_2266)
node _T_2268 = and(_T_2265, _T_2267)
when _T_2268 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
node _T_2269 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2270 = bits(vpn, 1, 0)
node _T_2271 = eq(UInt<1>(0h1), _T_2270)
node _T_2272 = and(_T_2269, _T_2271)
when _T_2272 :
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
node _T_2273 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2274 = bits(vpn, 1, 0)
node _T_2275 = eq(UInt<2>(0h2), _T_2274)
node _T_2276 = and(_T_2273, _T_2275)
when _T_2276 :
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
node _T_2277 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2278 = bits(vpn, 1, 0)
node _T_2279 = eq(UInt<2>(0h3), _T_2278)
node _T_2280 = and(_T_2277, _T_2279)
when _T_2280 :
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
node _T_2281 = xor(sectored_entries[0][5].tag_vpn, vpn)
node _T_2282 = shr(_T_2281, 18)
node _T_2283 = eq(_T_2282, UInt<1>(0h0))
when _T_2283 :
wire _WIRE_168 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_169 : UInt<42>
connect _WIRE_169, sectored_entries[0][5].data[0]
node _T_2284 = bits(_WIRE_169, 0, 0)
connect _WIRE_168.fragmented_superpage, _T_2284
node _T_2285 = bits(_WIRE_169, 1, 1)
connect _WIRE_168.c, _T_2285
node _T_2286 = bits(_WIRE_169, 2, 2)
connect _WIRE_168.eff, _T_2286
node _T_2287 = bits(_WIRE_169, 3, 3)
connect _WIRE_168.paa, _T_2287
node _T_2288 = bits(_WIRE_169, 4, 4)
connect _WIRE_168.pal, _T_2288
node _T_2289 = bits(_WIRE_169, 5, 5)
connect _WIRE_168.ppp, _T_2289
node _T_2290 = bits(_WIRE_169, 6, 6)
connect _WIRE_168.pr, _T_2290
node _T_2291 = bits(_WIRE_169, 7, 7)
connect _WIRE_168.px, _T_2291
node _T_2292 = bits(_WIRE_169, 8, 8)
connect _WIRE_168.pw, _T_2292
node _T_2293 = bits(_WIRE_169, 9, 9)
connect _WIRE_168.hr, _T_2293
node _T_2294 = bits(_WIRE_169, 10, 10)
connect _WIRE_168.hx, _T_2294
node _T_2295 = bits(_WIRE_169, 11, 11)
connect _WIRE_168.hw, _T_2295
node _T_2296 = bits(_WIRE_169, 12, 12)
connect _WIRE_168.sr, _T_2296
node _T_2297 = bits(_WIRE_169, 13, 13)
connect _WIRE_168.sx, _T_2297
node _T_2298 = bits(_WIRE_169, 14, 14)
connect _WIRE_168.sw, _T_2298
node _T_2299 = bits(_WIRE_169, 15, 15)
connect _WIRE_168.gf, _T_2299
node _T_2300 = bits(_WIRE_169, 16, 16)
connect _WIRE_168.pf, _T_2300
node _T_2301 = bits(_WIRE_169, 17, 17)
connect _WIRE_168.ae_stage2, _T_2301
node _T_2302 = bits(_WIRE_169, 18, 18)
connect _WIRE_168.ae_final, _T_2302
node _T_2303 = bits(_WIRE_169, 19, 19)
connect _WIRE_168.ae_ptw, _T_2303
node _T_2304 = bits(_WIRE_169, 20, 20)
connect _WIRE_168.g, _T_2304
node _T_2305 = bits(_WIRE_169, 21, 21)
connect _WIRE_168.u, _T_2305
node _T_2306 = bits(_WIRE_169, 41, 22)
connect _WIRE_168.ppn, _T_2306
wire _WIRE_170 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_171 : UInt<42>
connect _WIRE_171, sectored_entries[0][5].data[1]
node _T_2307 = bits(_WIRE_171, 0, 0)
connect _WIRE_170.fragmented_superpage, _T_2307
node _T_2308 = bits(_WIRE_171, 1, 1)
connect _WIRE_170.c, _T_2308
node _T_2309 = bits(_WIRE_171, 2, 2)
connect _WIRE_170.eff, _T_2309
node _T_2310 = bits(_WIRE_171, 3, 3)
connect _WIRE_170.paa, _T_2310
node _T_2311 = bits(_WIRE_171, 4, 4)
connect _WIRE_170.pal, _T_2311
node _T_2312 = bits(_WIRE_171, 5, 5)
connect _WIRE_170.ppp, _T_2312
node _T_2313 = bits(_WIRE_171, 6, 6)
connect _WIRE_170.pr, _T_2313
node _T_2314 = bits(_WIRE_171, 7, 7)
connect _WIRE_170.px, _T_2314
node _T_2315 = bits(_WIRE_171, 8, 8)
connect _WIRE_170.pw, _T_2315
node _T_2316 = bits(_WIRE_171, 9, 9)
connect _WIRE_170.hr, _T_2316
node _T_2317 = bits(_WIRE_171, 10, 10)
connect _WIRE_170.hx, _T_2317
node _T_2318 = bits(_WIRE_171, 11, 11)
connect _WIRE_170.hw, _T_2318
node _T_2319 = bits(_WIRE_171, 12, 12)
connect _WIRE_170.sr, _T_2319
node _T_2320 = bits(_WIRE_171, 13, 13)
connect _WIRE_170.sx, _T_2320
node _T_2321 = bits(_WIRE_171, 14, 14)
connect _WIRE_170.sw, _T_2321
node _T_2322 = bits(_WIRE_171, 15, 15)
connect _WIRE_170.gf, _T_2322
node _T_2323 = bits(_WIRE_171, 16, 16)
connect _WIRE_170.pf, _T_2323
node _T_2324 = bits(_WIRE_171, 17, 17)
connect _WIRE_170.ae_stage2, _T_2324
node _T_2325 = bits(_WIRE_171, 18, 18)
connect _WIRE_170.ae_final, _T_2325
node _T_2326 = bits(_WIRE_171, 19, 19)
connect _WIRE_170.ae_ptw, _T_2326
node _T_2327 = bits(_WIRE_171, 20, 20)
connect _WIRE_170.g, _T_2327
node _T_2328 = bits(_WIRE_171, 21, 21)
connect _WIRE_170.u, _T_2328
node _T_2329 = bits(_WIRE_171, 41, 22)
connect _WIRE_170.ppn, _T_2329
wire _WIRE_172 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_173 : UInt<42>
connect _WIRE_173, sectored_entries[0][5].data[2]
node _T_2330 = bits(_WIRE_173, 0, 0)
connect _WIRE_172.fragmented_superpage, _T_2330
node _T_2331 = bits(_WIRE_173, 1, 1)
connect _WIRE_172.c, _T_2331
node _T_2332 = bits(_WIRE_173, 2, 2)
connect _WIRE_172.eff, _T_2332
node _T_2333 = bits(_WIRE_173, 3, 3)
connect _WIRE_172.paa, _T_2333
node _T_2334 = bits(_WIRE_173, 4, 4)
connect _WIRE_172.pal, _T_2334
node _T_2335 = bits(_WIRE_173, 5, 5)
connect _WIRE_172.ppp, _T_2335
node _T_2336 = bits(_WIRE_173, 6, 6)
connect _WIRE_172.pr, _T_2336
node _T_2337 = bits(_WIRE_173, 7, 7)
connect _WIRE_172.px, _T_2337
node _T_2338 = bits(_WIRE_173, 8, 8)
connect _WIRE_172.pw, _T_2338
node _T_2339 = bits(_WIRE_173, 9, 9)
connect _WIRE_172.hr, _T_2339
node _T_2340 = bits(_WIRE_173, 10, 10)
connect _WIRE_172.hx, _T_2340
node _T_2341 = bits(_WIRE_173, 11, 11)
connect _WIRE_172.hw, _T_2341
node _T_2342 = bits(_WIRE_173, 12, 12)
connect _WIRE_172.sr, _T_2342
node _T_2343 = bits(_WIRE_173, 13, 13)
connect _WIRE_172.sx, _T_2343
node _T_2344 = bits(_WIRE_173, 14, 14)
connect _WIRE_172.sw, _T_2344
node _T_2345 = bits(_WIRE_173, 15, 15)
connect _WIRE_172.gf, _T_2345
node _T_2346 = bits(_WIRE_173, 16, 16)
connect _WIRE_172.pf, _T_2346
node _T_2347 = bits(_WIRE_173, 17, 17)
connect _WIRE_172.ae_stage2, _T_2347
node _T_2348 = bits(_WIRE_173, 18, 18)
connect _WIRE_172.ae_final, _T_2348
node _T_2349 = bits(_WIRE_173, 19, 19)
connect _WIRE_172.ae_ptw, _T_2349
node _T_2350 = bits(_WIRE_173, 20, 20)
connect _WIRE_172.g, _T_2350
node _T_2351 = bits(_WIRE_173, 21, 21)
connect _WIRE_172.u, _T_2351
node _T_2352 = bits(_WIRE_173, 41, 22)
connect _WIRE_172.ppn, _T_2352
wire _WIRE_174 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_175 : UInt<42>
connect _WIRE_175, sectored_entries[0][5].data[3]
node _T_2353 = bits(_WIRE_175, 0, 0)
connect _WIRE_174.fragmented_superpage, _T_2353
node _T_2354 = bits(_WIRE_175, 1, 1)
connect _WIRE_174.c, _T_2354
node _T_2355 = bits(_WIRE_175, 2, 2)
connect _WIRE_174.eff, _T_2355
node _T_2356 = bits(_WIRE_175, 3, 3)
connect _WIRE_174.paa, _T_2356
node _T_2357 = bits(_WIRE_175, 4, 4)
connect _WIRE_174.pal, _T_2357
node _T_2358 = bits(_WIRE_175, 5, 5)
connect _WIRE_174.ppp, _T_2358
node _T_2359 = bits(_WIRE_175, 6, 6)
connect _WIRE_174.pr, _T_2359
node _T_2360 = bits(_WIRE_175, 7, 7)
connect _WIRE_174.px, _T_2360
node _T_2361 = bits(_WIRE_175, 8, 8)
connect _WIRE_174.pw, _T_2361
node _T_2362 = bits(_WIRE_175, 9, 9)
connect _WIRE_174.hr, _T_2362
node _T_2363 = bits(_WIRE_175, 10, 10)
connect _WIRE_174.hx, _T_2363
node _T_2364 = bits(_WIRE_175, 11, 11)
connect _WIRE_174.hw, _T_2364
node _T_2365 = bits(_WIRE_175, 12, 12)
connect _WIRE_174.sr, _T_2365
node _T_2366 = bits(_WIRE_175, 13, 13)
connect _WIRE_174.sx, _T_2366
node _T_2367 = bits(_WIRE_175, 14, 14)
connect _WIRE_174.sw, _T_2367
node _T_2368 = bits(_WIRE_175, 15, 15)
connect _WIRE_174.gf, _T_2368
node _T_2369 = bits(_WIRE_175, 16, 16)
connect _WIRE_174.pf, _T_2369
node _T_2370 = bits(_WIRE_175, 17, 17)
connect _WIRE_174.ae_stage2, _T_2370
node _T_2371 = bits(_WIRE_175, 18, 18)
connect _WIRE_174.ae_final, _T_2371
node _T_2372 = bits(_WIRE_175, 19, 19)
connect _WIRE_174.ae_ptw, _T_2372
node _T_2373 = bits(_WIRE_175, 20, 20)
connect _WIRE_174.g, _T_2373
node _T_2374 = bits(_WIRE_175, 21, 21)
connect _WIRE_174.u, _T_2374
node _T_2375 = bits(_WIRE_175, 41, 22)
connect _WIRE_174.ppn, _T_2375
node _T_2376 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2377 = and(_T_2376, _WIRE_168.fragmented_superpage)
when _T_2377 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
node _T_2378 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2379 = and(_T_2378, _WIRE_170.fragmented_superpage)
when _T_2379 :
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
node _T_2380 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2381 = and(_T_2380, _WIRE_172.fragmented_superpage)
when _T_2381 :
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
node _T_2382 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2383 = and(_T_2382, _WIRE_174.fragmented_superpage)
when _T_2383 :
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
else :
node _T_2384 = eq(hg_5, UInt<1>(0h0))
node _T_2385 = and(_T_2384, io.sfence.bits.rs2)
when _T_2385 :
wire _WIRE_176 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_177 : UInt<42>
connect _WIRE_177, sectored_entries[0][5].data[0]
node _T_2386 = bits(_WIRE_177, 0, 0)
connect _WIRE_176.fragmented_superpage, _T_2386
node _T_2387 = bits(_WIRE_177, 1, 1)
connect _WIRE_176.c, _T_2387
node _T_2388 = bits(_WIRE_177, 2, 2)
connect _WIRE_176.eff, _T_2388
node _T_2389 = bits(_WIRE_177, 3, 3)
connect _WIRE_176.paa, _T_2389
node _T_2390 = bits(_WIRE_177, 4, 4)
connect _WIRE_176.pal, _T_2390
node _T_2391 = bits(_WIRE_177, 5, 5)
connect _WIRE_176.ppp, _T_2391
node _T_2392 = bits(_WIRE_177, 6, 6)
connect _WIRE_176.pr, _T_2392
node _T_2393 = bits(_WIRE_177, 7, 7)
connect _WIRE_176.px, _T_2393
node _T_2394 = bits(_WIRE_177, 8, 8)
connect _WIRE_176.pw, _T_2394
node _T_2395 = bits(_WIRE_177, 9, 9)
connect _WIRE_176.hr, _T_2395
node _T_2396 = bits(_WIRE_177, 10, 10)
connect _WIRE_176.hx, _T_2396
node _T_2397 = bits(_WIRE_177, 11, 11)
connect _WIRE_176.hw, _T_2397
node _T_2398 = bits(_WIRE_177, 12, 12)
connect _WIRE_176.sr, _T_2398
node _T_2399 = bits(_WIRE_177, 13, 13)
connect _WIRE_176.sx, _T_2399
node _T_2400 = bits(_WIRE_177, 14, 14)
connect _WIRE_176.sw, _T_2400
node _T_2401 = bits(_WIRE_177, 15, 15)
connect _WIRE_176.gf, _T_2401
node _T_2402 = bits(_WIRE_177, 16, 16)
connect _WIRE_176.pf, _T_2402
node _T_2403 = bits(_WIRE_177, 17, 17)
connect _WIRE_176.ae_stage2, _T_2403
node _T_2404 = bits(_WIRE_177, 18, 18)
connect _WIRE_176.ae_final, _T_2404
node _T_2405 = bits(_WIRE_177, 19, 19)
connect _WIRE_176.ae_ptw, _T_2405
node _T_2406 = bits(_WIRE_177, 20, 20)
connect _WIRE_176.g, _T_2406
node _T_2407 = bits(_WIRE_177, 21, 21)
connect _WIRE_176.u, _T_2407
node _T_2408 = bits(_WIRE_177, 41, 22)
connect _WIRE_176.ppn, _T_2408
wire _WIRE_178 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_179 : UInt<42>
connect _WIRE_179, sectored_entries[0][5].data[1]
node _T_2409 = bits(_WIRE_179, 0, 0)
connect _WIRE_178.fragmented_superpage, _T_2409
node _T_2410 = bits(_WIRE_179, 1, 1)
connect _WIRE_178.c, _T_2410
node _T_2411 = bits(_WIRE_179, 2, 2)
connect _WIRE_178.eff, _T_2411
node _T_2412 = bits(_WIRE_179, 3, 3)
connect _WIRE_178.paa, _T_2412
node _T_2413 = bits(_WIRE_179, 4, 4)
connect _WIRE_178.pal, _T_2413
node _T_2414 = bits(_WIRE_179, 5, 5)
connect _WIRE_178.ppp, _T_2414
node _T_2415 = bits(_WIRE_179, 6, 6)
connect _WIRE_178.pr, _T_2415
node _T_2416 = bits(_WIRE_179, 7, 7)
connect _WIRE_178.px, _T_2416
node _T_2417 = bits(_WIRE_179, 8, 8)
connect _WIRE_178.pw, _T_2417
node _T_2418 = bits(_WIRE_179, 9, 9)
connect _WIRE_178.hr, _T_2418
node _T_2419 = bits(_WIRE_179, 10, 10)
connect _WIRE_178.hx, _T_2419
node _T_2420 = bits(_WIRE_179, 11, 11)
connect _WIRE_178.hw, _T_2420
node _T_2421 = bits(_WIRE_179, 12, 12)
connect _WIRE_178.sr, _T_2421
node _T_2422 = bits(_WIRE_179, 13, 13)
connect _WIRE_178.sx, _T_2422
node _T_2423 = bits(_WIRE_179, 14, 14)
connect _WIRE_178.sw, _T_2423
node _T_2424 = bits(_WIRE_179, 15, 15)
connect _WIRE_178.gf, _T_2424
node _T_2425 = bits(_WIRE_179, 16, 16)
connect _WIRE_178.pf, _T_2425
node _T_2426 = bits(_WIRE_179, 17, 17)
connect _WIRE_178.ae_stage2, _T_2426
node _T_2427 = bits(_WIRE_179, 18, 18)
connect _WIRE_178.ae_final, _T_2427
node _T_2428 = bits(_WIRE_179, 19, 19)
connect _WIRE_178.ae_ptw, _T_2428
node _T_2429 = bits(_WIRE_179, 20, 20)
connect _WIRE_178.g, _T_2429
node _T_2430 = bits(_WIRE_179, 21, 21)
connect _WIRE_178.u, _T_2430
node _T_2431 = bits(_WIRE_179, 41, 22)
connect _WIRE_178.ppn, _T_2431
wire _WIRE_180 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_181 : UInt<42>
connect _WIRE_181, sectored_entries[0][5].data[2]
node _T_2432 = bits(_WIRE_181, 0, 0)
connect _WIRE_180.fragmented_superpage, _T_2432
node _T_2433 = bits(_WIRE_181, 1, 1)
connect _WIRE_180.c, _T_2433
node _T_2434 = bits(_WIRE_181, 2, 2)
connect _WIRE_180.eff, _T_2434
node _T_2435 = bits(_WIRE_181, 3, 3)
connect _WIRE_180.paa, _T_2435
node _T_2436 = bits(_WIRE_181, 4, 4)
connect _WIRE_180.pal, _T_2436
node _T_2437 = bits(_WIRE_181, 5, 5)
connect _WIRE_180.ppp, _T_2437
node _T_2438 = bits(_WIRE_181, 6, 6)
connect _WIRE_180.pr, _T_2438
node _T_2439 = bits(_WIRE_181, 7, 7)
connect _WIRE_180.px, _T_2439
node _T_2440 = bits(_WIRE_181, 8, 8)
connect _WIRE_180.pw, _T_2440
node _T_2441 = bits(_WIRE_181, 9, 9)
connect _WIRE_180.hr, _T_2441
node _T_2442 = bits(_WIRE_181, 10, 10)
connect _WIRE_180.hx, _T_2442
node _T_2443 = bits(_WIRE_181, 11, 11)
connect _WIRE_180.hw, _T_2443
node _T_2444 = bits(_WIRE_181, 12, 12)
connect _WIRE_180.sr, _T_2444
node _T_2445 = bits(_WIRE_181, 13, 13)
connect _WIRE_180.sx, _T_2445
node _T_2446 = bits(_WIRE_181, 14, 14)
connect _WIRE_180.sw, _T_2446
node _T_2447 = bits(_WIRE_181, 15, 15)
connect _WIRE_180.gf, _T_2447
node _T_2448 = bits(_WIRE_181, 16, 16)
connect _WIRE_180.pf, _T_2448
node _T_2449 = bits(_WIRE_181, 17, 17)
connect _WIRE_180.ae_stage2, _T_2449
node _T_2450 = bits(_WIRE_181, 18, 18)
connect _WIRE_180.ae_final, _T_2450
node _T_2451 = bits(_WIRE_181, 19, 19)
connect _WIRE_180.ae_ptw, _T_2451
node _T_2452 = bits(_WIRE_181, 20, 20)
connect _WIRE_180.g, _T_2452
node _T_2453 = bits(_WIRE_181, 21, 21)
connect _WIRE_180.u, _T_2453
node _T_2454 = bits(_WIRE_181, 41, 22)
connect _WIRE_180.ppn, _T_2454
wire _WIRE_182 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_183 : UInt<42>
connect _WIRE_183, sectored_entries[0][5].data[3]
node _T_2455 = bits(_WIRE_183, 0, 0)
connect _WIRE_182.fragmented_superpage, _T_2455
node _T_2456 = bits(_WIRE_183, 1, 1)
connect _WIRE_182.c, _T_2456
node _T_2457 = bits(_WIRE_183, 2, 2)
connect _WIRE_182.eff, _T_2457
node _T_2458 = bits(_WIRE_183, 3, 3)
connect _WIRE_182.paa, _T_2458
node _T_2459 = bits(_WIRE_183, 4, 4)
connect _WIRE_182.pal, _T_2459
node _T_2460 = bits(_WIRE_183, 5, 5)
connect _WIRE_182.ppp, _T_2460
node _T_2461 = bits(_WIRE_183, 6, 6)
connect _WIRE_182.pr, _T_2461
node _T_2462 = bits(_WIRE_183, 7, 7)
connect _WIRE_182.px, _T_2462
node _T_2463 = bits(_WIRE_183, 8, 8)
connect _WIRE_182.pw, _T_2463
node _T_2464 = bits(_WIRE_183, 9, 9)
connect _WIRE_182.hr, _T_2464
node _T_2465 = bits(_WIRE_183, 10, 10)
connect _WIRE_182.hx, _T_2465
node _T_2466 = bits(_WIRE_183, 11, 11)
connect _WIRE_182.hw, _T_2466
node _T_2467 = bits(_WIRE_183, 12, 12)
connect _WIRE_182.sr, _T_2467
node _T_2468 = bits(_WIRE_183, 13, 13)
connect _WIRE_182.sx, _T_2468
node _T_2469 = bits(_WIRE_183, 14, 14)
connect _WIRE_182.sw, _T_2469
node _T_2470 = bits(_WIRE_183, 15, 15)
connect _WIRE_182.gf, _T_2470
node _T_2471 = bits(_WIRE_183, 16, 16)
connect _WIRE_182.pf, _T_2471
node _T_2472 = bits(_WIRE_183, 17, 17)
connect _WIRE_182.ae_stage2, _T_2472
node _T_2473 = bits(_WIRE_183, 18, 18)
connect _WIRE_182.ae_final, _T_2473
node _T_2474 = bits(_WIRE_183, 19, 19)
connect _WIRE_182.ae_ptw, _T_2474
node _T_2475 = bits(_WIRE_183, 20, 20)
connect _WIRE_182.g, _T_2475
node _T_2476 = bits(_WIRE_183, 21, 21)
connect _WIRE_182.u, _T_2476
node _T_2477 = bits(_WIRE_183, 41, 22)
connect _WIRE_182.ppn, _T_2477
node _T_2478 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2479 = eq(_WIRE_176.g, UInt<1>(0h0))
node _T_2480 = and(_T_2478, _T_2479)
when _T_2480 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
node _T_2481 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2482 = eq(_WIRE_178.g, UInt<1>(0h0))
node _T_2483 = and(_T_2481, _T_2482)
when _T_2483 :
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
node _T_2484 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2485 = eq(_WIRE_180.g, UInt<1>(0h0))
node _T_2486 = and(_T_2484, _T_2485)
when _T_2486 :
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
node _T_2487 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2488 = eq(_WIRE_182.g, UInt<1>(0h0))
node _T_2489 = and(_T_2487, _T_2488)
when _T_2489 :
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
else :
node _T_2490 = or(hv_5, hg_5)
wire _WIRE_184 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_185 : UInt<42>
connect _WIRE_185, sectored_entries[0][5].data[0]
node _T_2491 = bits(_WIRE_185, 0, 0)
connect _WIRE_184.fragmented_superpage, _T_2491
node _T_2492 = bits(_WIRE_185, 1, 1)
connect _WIRE_184.c, _T_2492
node _T_2493 = bits(_WIRE_185, 2, 2)
connect _WIRE_184.eff, _T_2493
node _T_2494 = bits(_WIRE_185, 3, 3)
connect _WIRE_184.paa, _T_2494
node _T_2495 = bits(_WIRE_185, 4, 4)
connect _WIRE_184.pal, _T_2495
node _T_2496 = bits(_WIRE_185, 5, 5)
connect _WIRE_184.ppp, _T_2496
node _T_2497 = bits(_WIRE_185, 6, 6)
connect _WIRE_184.pr, _T_2497
node _T_2498 = bits(_WIRE_185, 7, 7)
connect _WIRE_184.px, _T_2498
node _T_2499 = bits(_WIRE_185, 8, 8)
connect _WIRE_184.pw, _T_2499
node _T_2500 = bits(_WIRE_185, 9, 9)
connect _WIRE_184.hr, _T_2500
node _T_2501 = bits(_WIRE_185, 10, 10)
connect _WIRE_184.hx, _T_2501
node _T_2502 = bits(_WIRE_185, 11, 11)
connect _WIRE_184.hw, _T_2502
node _T_2503 = bits(_WIRE_185, 12, 12)
connect _WIRE_184.sr, _T_2503
node _T_2504 = bits(_WIRE_185, 13, 13)
connect _WIRE_184.sx, _T_2504
node _T_2505 = bits(_WIRE_185, 14, 14)
connect _WIRE_184.sw, _T_2505
node _T_2506 = bits(_WIRE_185, 15, 15)
connect _WIRE_184.gf, _T_2506
node _T_2507 = bits(_WIRE_185, 16, 16)
connect _WIRE_184.pf, _T_2507
node _T_2508 = bits(_WIRE_185, 17, 17)
connect _WIRE_184.ae_stage2, _T_2508
node _T_2509 = bits(_WIRE_185, 18, 18)
connect _WIRE_184.ae_final, _T_2509
node _T_2510 = bits(_WIRE_185, 19, 19)
connect _WIRE_184.ae_ptw, _T_2510
node _T_2511 = bits(_WIRE_185, 20, 20)
connect _WIRE_184.g, _T_2511
node _T_2512 = bits(_WIRE_185, 21, 21)
connect _WIRE_184.u, _T_2512
node _T_2513 = bits(_WIRE_185, 41, 22)
connect _WIRE_184.ppn, _T_2513
wire _WIRE_186 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_187 : UInt<42>
connect _WIRE_187, sectored_entries[0][5].data[1]
node _T_2514 = bits(_WIRE_187, 0, 0)
connect _WIRE_186.fragmented_superpage, _T_2514
node _T_2515 = bits(_WIRE_187, 1, 1)
connect _WIRE_186.c, _T_2515
node _T_2516 = bits(_WIRE_187, 2, 2)
connect _WIRE_186.eff, _T_2516
node _T_2517 = bits(_WIRE_187, 3, 3)
connect _WIRE_186.paa, _T_2517
node _T_2518 = bits(_WIRE_187, 4, 4)
connect _WIRE_186.pal, _T_2518
node _T_2519 = bits(_WIRE_187, 5, 5)
connect _WIRE_186.ppp, _T_2519
node _T_2520 = bits(_WIRE_187, 6, 6)
connect _WIRE_186.pr, _T_2520
node _T_2521 = bits(_WIRE_187, 7, 7)
connect _WIRE_186.px, _T_2521
node _T_2522 = bits(_WIRE_187, 8, 8)
connect _WIRE_186.pw, _T_2522
node _T_2523 = bits(_WIRE_187, 9, 9)
connect _WIRE_186.hr, _T_2523
node _T_2524 = bits(_WIRE_187, 10, 10)
connect _WIRE_186.hx, _T_2524
node _T_2525 = bits(_WIRE_187, 11, 11)
connect _WIRE_186.hw, _T_2525
node _T_2526 = bits(_WIRE_187, 12, 12)
connect _WIRE_186.sr, _T_2526
node _T_2527 = bits(_WIRE_187, 13, 13)
connect _WIRE_186.sx, _T_2527
node _T_2528 = bits(_WIRE_187, 14, 14)
connect _WIRE_186.sw, _T_2528
node _T_2529 = bits(_WIRE_187, 15, 15)
connect _WIRE_186.gf, _T_2529
node _T_2530 = bits(_WIRE_187, 16, 16)
connect _WIRE_186.pf, _T_2530
node _T_2531 = bits(_WIRE_187, 17, 17)
connect _WIRE_186.ae_stage2, _T_2531
node _T_2532 = bits(_WIRE_187, 18, 18)
connect _WIRE_186.ae_final, _T_2532
node _T_2533 = bits(_WIRE_187, 19, 19)
connect _WIRE_186.ae_ptw, _T_2533
node _T_2534 = bits(_WIRE_187, 20, 20)
connect _WIRE_186.g, _T_2534
node _T_2535 = bits(_WIRE_187, 21, 21)
connect _WIRE_186.u, _T_2535
node _T_2536 = bits(_WIRE_187, 41, 22)
connect _WIRE_186.ppn, _T_2536
wire _WIRE_188 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_189 : UInt<42>
connect _WIRE_189, sectored_entries[0][5].data[2]
node _T_2537 = bits(_WIRE_189, 0, 0)
connect _WIRE_188.fragmented_superpage, _T_2537
node _T_2538 = bits(_WIRE_189, 1, 1)
connect _WIRE_188.c, _T_2538
node _T_2539 = bits(_WIRE_189, 2, 2)
connect _WIRE_188.eff, _T_2539
node _T_2540 = bits(_WIRE_189, 3, 3)
connect _WIRE_188.paa, _T_2540
node _T_2541 = bits(_WIRE_189, 4, 4)
connect _WIRE_188.pal, _T_2541
node _T_2542 = bits(_WIRE_189, 5, 5)
connect _WIRE_188.ppp, _T_2542
node _T_2543 = bits(_WIRE_189, 6, 6)
connect _WIRE_188.pr, _T_2543
node _T_2544 = bits(_WIRE_189, 7, 7)
connect _WIRE_188.px, _T_2544
node _T_2545 = bits(_WIRE_189, 8, 8)
connect _WIRE_188.pw, _T_2545
node _T_2546 = bits(_WIRE_189, 9, 9)
connect _WIRE_188.hr, _T_2546
node _T_2547 = bits(_WIRE_189, 10, 10)
connect _WIRE_188.hx, _T_2547
node _T_2548 = bits(_WIRE_189, 11, 11)
connect _WIRE_188.hw, _T_2548
node _T_2549 = bits(_WIRE_189, 12, 12)
connect _WIRE_188.sr, _T_2549
node _T_2550 = bits(_WIRE_189, 13, 13)
connect _WIRE_188.sx, _T_2550
node _T_2551 = bits(_WIRE_189, 14, 14)
connect _WIRE_188.sw, _T_2551
node _T_2552 = bits(_WIRE_189, 15, 15)
connect _WIRE_188.gf, _T_2552
node _T_2553 = bits(_WIRE_189, 16, 16)
connect _WIRE_188.pf, _T_2553
node _T_2554 = bits(_WIRE_189, 17, 17)
connect _WIRE_188.ae_stage2, _T_2554
node _T_2555 = bits(_WIRE_189, 18, 18)
connect _WIRE_188.ae_final, _T_2555
node _T_2556 = bits(_WIRE_189, 19, 19)
connect _WIRE_188.ae_ptw, _T_2556
node _T_2557 = bits(_WIRE_189, 20, 20)
connect _WIRE_188.g, _T_2557
node _T_2558 = bits(_WIRE_189, 21, 21)
connect _WIRE_188.u, _T_2558
node _T_2559 = bits(_WIRE_189, 41, 22)
connect _WIRE_188.ppn, _T_2559
wire _WIRE_190 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_191 : UInt<42>
connect _WIRE_191, sectored_entries[0][5].data[3]
node _T_2560 = bits(_WIRE_191, 0, 0)
connect _WIRE_190.fragmented_superpage, _T_2560
node _T_2561 = bits(_WIRE_191, 1, 1)
connect _WIRE_190.c, _T_2561
node _T_2562 = bits(_WIRE_191, 2, 2)
connect _WIRE_190.eff, _T_2562
node _T_2563 = bits(_WIRE_191, 3, 3)
connect _WIRE_190.paa, _T_2563
node _T_2564 = bits(_WIRE_191, 4, 4)
connect _WIRE_190.pal, _T_2564
node _T_2565 = bits(_WIRE_191, 5, 5)
connect _WIRE_190.ppp, _T_2565
node _T_2566 = bits(_WIRE_191, 6, 6)
connect _WIRE_190.pr, _T_2566
node _T_2567 = bits(_WIRE_191, 7, 7)
connect _WIRE_190.px, _T_2567
node _T_2568 = bits(_WIRE_191, 8, 8)
connect _WIRE_190.pw, _T_2568
node _T_2569 = bits(_WIRE_191, 9, 9)
connect _WIRE_190.hr, _T_2569
node _T_2570 = bits(_WIRE_191, 10, 10)
connect _WIRE_190.hx, _T_2570
node _T_2571 = bits(_WIRE_191, 11, 11)
connect _WIRE_190.hw, _T_2571
node _T_2572 = bits(_WIRE_191, 12, 12)
connect _WIRE_190.sr, _T_2572
node _T_2573 = bits(_WIRE_191, 13, 13)
connect _WIRE_190.sx, _T_2573
node _T_2574 = bits(_WIRE_191, 14, 14)
connect _WIRE_190.sw, _T_2574
node _T_2575 = bits(_WIRE_191, 15, 15)
connect _WIRE_190.gf, _T_2575
node _T_2576 = bits(_WIRE_191, 16, 16)
connect _WIRE_190.pf, _T_2576
node _T_2577 = bits(_WIRE_191, 17, 17)
connect _WIRE_190.ae_stage2, _T_2577
node _T_2578 = bits(_WIRE_191, 18, 18)
connect _WIRE_190.ae_final, _T_2578
node _T_2579 = bits(_WIRE_191, 19, 19)
connect _WIRE_190.ae_ptw, _T_2579
node _T_2580 = bits(_WIRE_191, 20, 20)
connect _WIRE_190.g, _T_2580
node _T_2581 = bits(_WIRE_191, 21, 21)
connect _WIRE_190.u, _T_2581
node _T_2582 = bits(_WIRE_191, 41, 22)
connect _WIRE_190.ppn, _T_2582
node _T_2583 = eq(sectored_entries[0][5].tag_v, _T_2490)
when _T_2583 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
node _T_2584 = eq(sectored_entries[0][5].tag_v, _T_2490)
when _T_2584 :
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
node _T_2585 = eq(sectored_entries[0][5].tag_v, _T_2490)
when _T_2585 :
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
node _T_2586 = eq(sectored_entries[0][5].tag_v, _T_2490)
when _T_2586 :
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
node hv_6 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_6 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_2587 = eq(hg_6, UInt<1>(0h0))
node _T_2588 = and(_T_2587, io.sfence.bits.rs1)
when _T_2588 :
node _T_2589 = xor(sectored_entries[0][6].tag_vpn, vpn)
node _T_2590 = shr(_T_2589, 2)
node _T_2591 = eq(_T_2590, UInt<1>(0h0))
node _T_2592 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2593 = and(_T_2591, _T_2592)
when _T_2593 :
wire _WIRE_192 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_193 : UInt<42>
connect _WIRE_193, sectored_entries[0][6].data[0]
node _T_2594 = bits(_WIRE_193, 0, 0)
connect _WIRE_192.fragmented_superpage, _T_2594
node _T_2595 = bits(_WIRE_193, 1, 1)
connect _WIRE_192.c, _T_2595
node _T_2596 = bits(_WIRE_193, 2, 2)
connect _WIRE_192.eff, _T_2596
node _T_2597 = bits(_WIRE_193, 3, 3)
connect _WIRE_192.paa, _T_2597
node _T_2598 = bits(_WIRE_193, 4, 4)
connect _WIRE_192.pal, _T_2598
node _T_2599 = bits(_WIRE_193, 5, 5)
connect _WIRE_192.ppp, _T_2599
node _T_2600 = bits(_WIRE_193, 6, 6)
connect _WIRE_192.pr, _T_2600
node _T_2601 = bits(_WIRE_193, 7, 7)
connect _WIRE_192.px, _T_2601
node _T_2602 = bits(_WIRE_193, 8, 8)
connect _WIRE_192.pw, _T_2602
node _T_2603 = bits(_WIRE_193, 9, 9)
connect _WIRE_192.hr, _T_2603
node _T_2604 = bits(_WIRE_193, 10, 10)
connect _WIRE_192.hx, _T_2604
node _T_2605 = bits(_WIRE_193, 11, 11)
connect _WIRE_192.hw, _T_2605
node _T_2606 = bits(_WIRE_193, 12, 12)
connect _WIRE_192.sr, _T_2606
node _T_2607 = bits(_WIRE_193, 13, 13)
connect _WIRE_192.sx, _T_2607
node _T_2608 = bits(_WIRE_193, 14, 14)
connect _WIRE_192.sw, _T_2608
node _T_2609 = bits(_WIRE_193, 15, 15)
connect _WIRE_192.gf, _T_2609
node _T_2610 = bits(_WIRE_193, 16, 16)
connect _WIRE_192.pf, _T_2610
node _T_2611 = bits(_WIRE_193, 17, 17)
connect _WIRE_192.ae_stage2, _T_2611
node _T_2612 = bits(_WIRE_193, 18, 18)
connect _WIRE_192.ae_final, _T_2612
node _T_2613 = bits(_WIRE_193, 19, 19)
connect _WIRE_192.ae_ptw, _T_2613
node _T_2614 = bits(_WIRE_193, 20, 20)
connect _WIRE_192.g, _T_2614
node _T_2615 = bits(_WIRE_193, 21, 21)
connect _WIRE_192.u, _T_2615
node _T_2616 = bits(_WIRE_193, 41, 22)
connect _WIRE_192.ppn, _T_2616
wire _WIRE_194 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_195 : UInt<42>
connect _WIRE_195, sectored_entries[0][6].data[1]
node _T_2617 = bits(_WIRE_195, 0, 0)
connect _WIRE_194.fragmented_superpage, _T_2617
node _T_2618 = bits(_WIRE_195, 1, 1)
connect _WIRE_194.c, _T_2618
node _T_2619 = bits(_WIRE_195, 2, 2)
connect _WIRE_194.eff, _T_2619
node _T_2620 = bits(_WIRE_195, 3, 3)
connect _WIRE_194.paa, _T_2620
node _T_2621 = bits(_WIRE_195, 4, 4)
connect _WIRE_194.pal, _T_2621
node _T_2622 = bits(_WIRE_195, 5, 5)
connect _WIRE_194.ppp, _T_2622
node _T_2623 = bits(_WIRE_195, 6, 6)
connect _WIRE_194.pr, _T_2623
node _T_2624 = bits(_WIRE_195, 7, 7)
connect _WIRE_194.px, _T_2624
node _T_2625 = bits(_WIRE_195, 8, 8)
connect _WIRE_194.pw, _T_2625
node _T_2626 = bits(_WIRE_195, 9, 9)
connect _WIRE_194.hr, _T_2626
node _T_2627 = bits(_WIRE_195, 10, 10)
connect _WIRE_194.hx, _T_2627
node _T_2628 = bits(_WIRE_195, 11, 11)
connect _WIRE_194.hw, _T_2628
node _T_2629 = bits(_WIRE_195, 12, 12)
connect _WIRE_194.sr, _T_2629
node _T_2630 = bits(_WIRE_195, 13, 13)
connect _WIRE_194.sx, _T_2630
node _T_2631 = bits(_WIRE_195, 14, 14)
connect _WIRE_194.sw, _T_2631
node _T_2632 = bits(_WIRE_195, 15, 15)
connect _WIRE_194.gf, _T_2632
node _T_2633 = bits(_WIRE_195, 16, 16)
connect _WIRE_194.pf, _T_2633
node _T_2634 = bits(_WIRE_195, 17, 17)
connect _WIRE_194.ae_stage2, _T_2634
node _T_2635 = bits(_WIRE_195, 18, 18)
connect _WIRE_194.ae_final, _T_2635
node _T_2636 = bits(_WIRE_195, 19, 19)
connect _WIRE_194.ae_ptw, _T_2636
node _T_2637 = bits(_WIRE_195, 20, 20)
connect _WIRE_194.g, _T_2637
node _T_2638 = bits(_WIRE_195, 21, 21)
connect _WIRE_194.u, _T_2638
node _T_2639 = bits(_WIRE_195, 41, 22)
connect _WIRE_194.ppn, _T_2639
wire _WIRE_196 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_197 : UInt<42>
connect _WIRE_197, sectored_entries[0][6].data[2]
node _T_2640 = bits(_WIRE_197, 0, 0)
connect _WIRE_196.fragmented_superpage, _T_2640
node _T_2641 = bits(_WIRE_197, 1, 1)
connect _WIRE_196.c, _T_2641
node _T_2642 = bits(_WIRE_197, 2, 2)
connect _WIRE_196.eff, _T_2642
node _T_2643 = bits(_WIRE_197, 3, 3)
connect _WIRE_196.paa, _T_2643
node _T_2644 = bits(_WIRE_197, 4, 4)
connect _WIRE_196.pal, _T_2644
node _T_2645 = bits(_WIRE_197, 5, 5)
connect _WIRE_196.ppp, _T_2645
node _T_2646 = bits(_WIRE_197, 6, 6)
connect _WIRE_196.pr, _T_2646
node _T_2647 = bits(_WIRE_197, 7, 7)
connect _WIRE_196.px, _T_2647
node _T_2648 = bits(_WIRE_197, 8, 8)
connect _WIRE_196.pw, _T_2648
node _T_2649 = bits(_WIRE_197, 9, 9)
connect _WIRE_196.hr, _T_2649
node _T_2650 = bits(_WIRE_197, 10, 10)
connect _WIRE_196.hx, _T_2650
node _T_2651 = bits(_WIRE_197, 11, 11)
connect _WIRE_196.hw, _T_2651
node _T_2652 = bits(_WIRE_197, 12, 12)
connect _WIRE_196.sr, _T_2652
node _T_2653 = bits(_WIRE_197, 13, 13)
connect _WIRE_196.sx, _T_2653
node _T_2654 = bits(_WIRE_197, 14, 14)
connect _WIRE_196.sw, _T_2654
node _T_2655 = bits(_WIRE_197, 15, 15)
connect _WIRE_196.gf, _T_2655
node _T_2656 = bits(_WIRE_197, 16, 16)
connect _WIRE_196.pf, _T_2656
node _T_2657 = bits(_WIRE_197, 17, 17)
connect _WIRE_196.ae_stage2, _T_2657
node _T_2658 = bits(_WIRE_197, 18, 18)
connect _WIRE_196.ae_final, _T_2658
node _T_2659 = bits(_WIRE_197, 19, 19)
connect _WIRE_196.ae_ptw, _T_2659
node _T_2660 = bits(_WIRE_197, 20, 20)
connect _WIRE_196.g, _T_2660
node _T_2661 = bits(_WIRE_197, 21, 21)
connect _WIRE_196.u, _T_2661
node _T_2662 = bits(_WIRE_197, 41, 22)
connect _WIRE_196.ppn, _T_2662
wire _WIRE_198 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_199 : UInt<42>
connect _WIRE_199, sectored_entries[0][6].data[3]
node _T_2663 = bits(_WIRE_199, 0, 0)
connect _WIRE_198.fragmented_superpage, _T_2663
node _T_2664 = bits(_WIRE_199, 1, 1)
connect _WIRE_198.c, _T_2664
node _T_2665 = bits(_WIRE_199, 2, 2)
connect _WIRE_198.eff, _T_2665
node _T_2666 = bits(_WIRE_199, 3, 3)
connect _WIRE_198.paa, _T_2666
node _T_2667 = bits(_WIRE_199, 4, 4)
connect _WIRE_198.pal, _T_2667
node _T_2668 = bits(_WIRE_199, 5, 5)
connect _WIRE_198.ppp, _T_2668
node _T_2669 = bits(_WIRE_199, 6, 6)
connect _WIRE_198.pr, _T_2669
node _T_2670 = bits(_WIRE_199, 7, 7)
connect _WIRE_198.px, _T_2670
node _T_2671 = bits(_WIRE_199, 8, 8)
connect _WIRE_198.pw, _T_2671
node _T_2672 = bits(_WIRE_199, 9, 9)
connect _WIRE_198.hr, _T_2672
node _T_2673 = bits(_WIRE_199, 10, 10)
connect _WIRE_198.hx, _T_2673
node _T_2674 = bits(_WIRE_199, 11, 11)
connect _WIRE_198.hw, _T_2674
node _T_2675 = bits(_WIRE_199, 12, 12)
connect _WIRE_198.sr, _T_2675
node _T_2676 = bits(_WIRE_199, 13, 13)
connect _WIRE_198.sx, _T_2676
node _T_2677 = bits(_WIRE_199, 14, 14)
connect _WIRE_198.sw, _T_2677
node _T_2678 = bits(_WIRE_199, 15, 15)
connect _WIRE_198.gf, _T_2678
node _T_2679 = bits(_WIRE_199, 16, 16)
connect _WIRE_198.pf, _T_2679
node _T_2680 = bits(_WIRE_199, 17, 17)
connect _WIRE_198.ae_stage2, _T_2680
node _T_2681 = bits(_WIRE_199, 18, 18)
connect _WIRE_198.ae_final, _T_2681
node _T_2682 = bits(_WIRE_199, 19, 19)
connect _WIRE_198.ae_ptw, _T_2682
node _T_2683 = bits(_WIRE_199, 20, 20)
connect _WIRE_198.g, _T_2683
node _T_2684 = bits(_WIRE_199, 21, 21)
connect _WIRE_198.u, _T_2684
node _T_2685 = bits(_WIRE_199, 41, 22)
connect _WIRE_198.ppn, _T_2685
node _T_2686 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2687 = bits(vpn, 1, 0)
node _T_2688 = eq(UInt<1>(0h0), _T_2687)
node _T_2689 = and(_T_2686, _T_2688)
when _T_2689 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
node _T_2690 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2691 = bits(vpn, 1, 0)
node _T_2692 = eq(UInt<1>(0h1), _T_2691)
node _T_2693 = and(_T_2690, _T_2692)
when _T_2693 :
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
node _T_2694 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2695 = bits(vpn, 1, 0)
node _T_2696 = eq(UInt<2>(0h2), _T_2695)
node _T_2697 = and(_T_2694, _T_2696)
when _T_2697 :
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
node _T_2698 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2699 = bits(vpn, 1, 0)
node _T_2700 = eq(UInt<2>(0h3), _T_2699)
node _T_2701 = and(_T_2698, _T_2700)
when _T_2701 :
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
node _T_2702 = xor(sectored_entries[0][6].tag_vpn, vpn)
node _T_2703 = shr(_T_2702, 18)
node _T_2704 = eq(_T_2703, UInt<1>(0h0))
when _T_2704 :
wire _WIRE_200 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_201 : UInt<42>
connect _WIRE_201, sectored_entries[0][6].data[0]
node _T_2705 = bits(_WIRE_201, 0, 0)
connect _WIRE_200.fragmented_superpage, _T_2705
node _T_2706 = bits(_WIRE_201, 1, 1)
connect _WIRE_200.c, _T_2706
node _T_2707 = bits(_WIRE_201, 2, 2)
connect _WIRE_200.eff, _T_2707
node _T_2708 = bits(_WIRE_201, 3, 3)
connect _WIRE_200.paa, _T_2708
node _T_2709 = bits(_WIRE_201, 4, 4)
connect _WIRE_200.pal, _T_2709
node _T_2710 = bits(_WIRE_201, 5, 5)
connect _WIRE_200.ppp, _T_2710
node _T_2711 = bits(_WIRE_201, 6, 6)
connect _WIRE_200.pr, _T_2711
node _T_2712 = bits(_WIRE_201, 7, 7)
connect _WIRE_200.px, _T_2712
node _T_2713 = bits(_WIRE_201, 8, 8)
connect _WIRE_200.pw, _T_2713
node _T_2714 = bits(_WIRE_201, 9, 9)
connect _WIRE_200.hr, _T_2714
node _T_2715 = bits(_WIRE_201, 10, 10)
connect _WIRE_200.hx, _T_2715
node _T_2716 = bits(_WIRE_201, 11, 11)
connect _WIRE_200.hw, _T_2716
node _T_2717 = bits(_WIRE_201, 12, 12)
connect _WIRE_200.sr, _T_2717
node _T_2718 = bits(_WIRE_201, 13, 13)
connect _WIRE_200.sx, _T_2718
node _T_2719 = bits(_WIRE_201, 14, 14)
connect _WIRE_200.sw, _T_2719
node _T_2720 = bits(_WIRE_201, 15, 15)
connect _WIRE_200.gf, _T_2720
node _T_2721 = bits(_WIRE_201, 16, 16)
connect _WIRE_200.pf, _T_2721
node _T_2722 = bits(_WIRE_201, 17, 17)
connect _WIRE_200.ae_stage2, _T_2722
node _T_2723 = bits(_WIRE_201, 18, 18)
connect _WIRE_200.ae_final, _T_2723
node _T_2724 = bits(_WIRE_201, 19, 19)
connect _WIRE_200.ae_ptw, _T_2724
node _T_2725 = bits(_WIRE_201, 20, 20)
connect _WIRE_200.g, _T_2725
node _T_2726 = bits(_WIRE_201, 21, 21)
connect _WIRE_200.u, _T_2726
node _T_2727 = bits(_WIRE_201, 41, 22)
connect _WIRE_200.ppn, _T_2727
wire _WIRE_202 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_203 : UInt<42>
connect _WIRE_203, sectored_entries[0][6].data[1]
node _T_2728 = bits(_WIRE_203, 0, 0)
connect _WIRE_202.fragmented_superpage, _T_2728
node _T_2729 = bits(_WIRE_203, 1, 1)
connect _WIRE_202.c, _T_2729
node _T_2730 = bits(_WIRE_203, 2, 2)
connect _WIRE_202.eff, _T_2730
node _T_2731 = bits(_WIRE_203, 3, 3)
connect _WIRE_202.paa, _T_2731
node _T_2732 = bits(_WIRE_203, 4, 4)
connect _WIRE_202.pal, _T_2732
node _T_2733 = bits(_WIRE_203, 5, 5)
connect _WIRE_202.ppp, _T_2733
node _T_2734 = bits(_WIRE_203, 6, 6)
connect _WIRE_202.pr, _T_2734
node _T_2735 = bits(_WIRE_203, 7, 7)
connect _WIRE_202.px, _T_2735
node _T_2736 = bits(_WIRE_203, 8, 8)
connect _WIRE_202.pw, _T_2736
node _T_2737 = bits(_WIRE_203, 9, 9)
connect _WIRE_202.hr, _T_2737
node _T_2738 = bits(_WIRE_203, 10, 10)
connect _WIRE_202.hx, _T_2738
node _T_2739 = bits(_WIRE_203, 11, 11)
connect _WIRE_202.hw, _T_2739
node _T_2740 = bits(_WIRE_203, 12, 12)
connect _WIRE_202.sr, _T_2740
node _T_2741 = bits(_WIRE_203, 13, 13)
connect _WIRE_202.sx, _T_2741
node _T_2742 = bits(_WIRE_203, 14, 14)
connect _WIRE_202.sw, _T_2742
node _T_2743 = bits(_WIRE_203, 15, 15)
connect _WIRE_202.gf, _T_2743
node _T_2744 = bits(_WIRE_203, 16, 16)
connect _WIRE_202.pf, _T_2744
node _T_2745 = bits(_WIRE_203, 17, 17)
connect _WIRE_202.ae_stage2, _T_2745
node _T_2746 = bits(_WIRE_203, 18, 18)
connect _WIRE_202.ae_final, _T_2746
node _T_2747 = bits(_WIRE_203, 19, 19)
connect _WIRE_202.ae_ptw, _T_2747
node _T_2748 = bits(_WIRE_203, 20, 20)
connect _WIRE_202.g, _T_2748
node _T_2749 = bits(_WIRE_203, 21, 21)
connect _WIRE_202.u, _T_2749
node _T_2750 = bits(_WIRE_203, 41, 22)
connect _WIRE_202.ppn, _T_2750
wire _WIRE_204 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_205 : UInt<42>
connect _WIRE_205, sectored_entries[0][6].data[2]
node _T_2751 = bits(_WIRE_205, 0, 0)
connect _WIRE_204.fragmented_superpage, _T_2751
node _T_2752 = bits(_WIRE_205, 1, 1)
connect _WIRE_204.c, _T_2752
node _T_2753 = bits(_WIRE_205, 2, 2)
connect _WIRE_204.eff, _T_2753
node _T_2754 = bits(_WIRE_205, 3, 3)
connect _WIRE_204.paa, _T_2754
node _T_2755 = bits(_WIRE_205, 4, 4)
connect _WIRE_204.pal, _T_2755
node _T_2756 = bits(_WIRE_205, 5, 5)
connect _WIRE_204.ppp, _T_2756
node _T_2757 = bits(_WIRE_205, 6, 6)
connect _WIRE_204.pr, _T_2757
node _T_2758 = bits(_WIRE_205, 7, 7)
connect _WIRE_204.px, _T_2758
node _T_2759 = bits(_WIRE_205, 8, 8)
connect _WIRE_204.pw, _T_2759
node _T_2760 = bits(_WIRE_205, 9, 9)
connect _WIRE_204.hr, _T_2760
node _T_2761 = bits(_WIRE_205, 10, 10)
connect _WIRE_204.hx, _T_2761
node _T_2762 = bits(_WIRE_205, 11, 11)
connect _WIRE_204.hw, _T_2762
node _T_2763 = bits(_WIRE_205, 12, 12)
connect _WIRE_204.sr, _T_2763
node _T_2764 = bits(_WIRE_205, 13, 13)
connect _WIRE_204.sx, _T_2764
node _T_2765 = bits(_WIRE_205, 14, 14)
connect _WIRE_204.sw, _T_2765
node _T_2766 = bits(_WIRE_205, 15, 15)
connect _WIRE_204.gf, _T_2766
node _T_2767 = bits(_WIRE_205, 16, 16)
connect _WIRE_204.pf, _T_2767
node _T_2768 = bits(_WIRE_205, 17, 17)
connect _WIRE_204.ae_stage2, _T_2768
node _T_2769 = bits(_WIRE_205, 18, 18)
connect _WIRE_204.ae_final, _T_2769
node _T_2770 = bits(_WIRE_205, 19, 19)
connect _WIRE_204.ae_ptw, _T_2770
node _T_2771 = bits(_WIRE_205, 20, 20)
connect _WIRE_204.g, _T_2771
node _T_2772 = bits(_WIRE_205, 21, 21)
connect _WIRE_204.u, _T_2772
node _T_2773 = bits(_WIRE_205, 41, 22)
connect _WIRE_204.ppn, _T_2773
wire _WIRE_206 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_207 : UInt<42>
connect _WIRE_207, sectored_entries[0][6].data[3]
node _T_2774 = bits(_WIRE_207, 0, 0)
connect _WIRE_206.fragmented_superpage, _T_2774
node _T_2775 = bits(_WIRE_207, 1, 1)
connect _WIRE_206.c, _T_2775
node _T_2776 = bits(_WIRE_207, 2, 2)
connect _WIRE_206.eff, _T_2776
node _T_2777 = bits(_WIRE_207, 3, 3)
connect _WIRE_206.paa, _T_2777
node _T_2778 = bits(_WIRE_207, 4, 4)
connect _WIRE_206.pal, _T_2778
node _T_2779 = bits(_WIRE_207, 5, 5)
connect _WIRE_206.ppp, _T_2779
node _T_2780 = bits(_WIRE_207, 6, 6)
connect _WIRE_206.pr, _T_2780
node _T_2781 = bits(_WIRE_207, 7, 7)
connect _WIRE_206.px, _T_2781
node _T_2782 = bits(_WIRE_207, 8, 8)
connect _WIRE_206.pw, _T_2782
node _T_2783 = bits(_WIRE_207, 9, 9)
connect _WIRE_206.hr, _T_2783
node _T_2784 = bits(_WIRE_207, 10, 10)
connect _WIRE_206.hx, _T_2784
node _T_2785 = bits(_WIRE_207, 11, 11)
connect _WIRE_206.hw, _T_2785
node _T_2786 = bits(_WIRE_207, 12, 12)
connect _WIRE_206.sr, _T_2786
node _T_2787 = bits(_WIRE_207, 13, 13)
connect _WIRE_206.sx, _T_2787
node _T_2788 = bits(_WIRE_207, 14, 14)
connect _WIRE_206.sw, _T_2788
node _T_2789 = bits(_WIRE_207, 15, 15)
connect _WIRE_206.gf, _T_2789
node _T_2790 = bits(_WIRE_207, 16, 16)
connect _WIRE_206.pf, _T_2790
node _T_2791 = bits(_WIRE_207, 17, 17)
connect _WIRE_206.ae_stage2, _T_2791
node _T_2792 = bits(_WIRE_207, 18, 18)
connect _WIRE_206.ae_final, _T_2792
node _T_2793 = bits(_WIRE_207, 19, 19)
connect _WIRE_206.ae_ptw, _T_2793
node _T_2794 = bits(_WIRE_207, 20, 20)
connect _WIRE_206.g, _T_2794
node _T_2795 = bits(_WIRE_207, 21, 21)
connect _WIRE_206.u, _T_2795
node _T_2796 = bits(_WIRE_207, 41, 22)
connect _WIRE_206.ppn, _T_2796
node _T_2797 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2798 = and(_T_2797, _WIRE_200.fragmented_superpage)
when _T_2798 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
node _T_2799 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2800 = and(_T_2799, _WIRE_202.fragmented_superpage)
when _T_2800 :
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
node _T_2801 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2802 = and(_T_2801, _WIRE_204.fragmented_superpage)
when _T_2802 :
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
node _T_2803 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2804 = and(_T_2803, _WIRE_206.fragmented_superpage)
when _T_2804 :
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
else :
node _T_2805 = eq(hg_6, UInt<1>(0h0))
node _T_2806 = and(_T_2805, io.sfence.bits.rs2)
when _T_2806 :
wire _WIRE_208 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_209 : UInt<42>
connect _WIRE_209, sectored_entries[0][6].data[0]
node _T_2807 = bits(_WIRE_209, 0, 0)
connect _WIRE_208.fragmented_superpage, _T_2807
node _T_2808 = bits(_WIRE_209, 1, 1)
connect _WIRE_208.c, _T_2808
node _T_2809 = bits(_WIRE_209, 2, 2)
connect _WIRE_208.eff, _T_2809
node _T_2810 = bits(_WIRE_209, 3, 3)
connect _WIRE_208.paa, _T_2810
node _T_2811 = bits(_WIRE_209, 4, 4)
connect _WIRE_208.pal, _T_2811
node _T_2812 = bits(_WIRE_209, 5, 5)
connect _WIRE_208.ppp, _T_2812
node _T_2813 = bits(_WIRE_209, 6, 6)
connect _WIRE_208.pr, _T_2813
node _T_2814 = bits(_WIRE_209, 7, 7)
connect _WIRE_208.px, _T_2814
node _T_2815 = bits(_WIRE_209, 8, 8)
connect _WIRE_208.pw, _T_2815
node _T_2816 = bits(_WIRE_209, 9, 9)
connect _WIRE_208.hr, _T_2816
node _T_2817 = bits(_WIRE_209, 10, 10)
connect _WIRE_208.hx, _T_2817
node _T_2818 = bits(_WIRE_209, 11, 11)
connect _WIRE_208.hw, _T_2818
node _T_2819 = bits(_WIRE_209, 12, 12)
connect _WIRE_208.sr, _T_2819
node _T_2820 = bits(_WIRE_209, 13, 13)
connect _WIRE_208.sx, _T_2820
node _T_2821 = bits(_WIRE_209, 14, 14)
connect _WIRE_208.sw, _T_2821
node _T_2822 = bits(_WIRE_209, 15, 15)
connect _WIRE_208.gf, _T_2822
node _T_2823 = bits(_WIRE_209, 16, 16)
connect _WIRE_208.pf, _T_2823
node _T_2824 = bits(_WIRE_209, 17, 17)
connect _WIRE_208.ae_stage2, _T_2824
node _T_2825 = bits(_WIRE_209, 18, 18)
connect _WIRE_208.ae_final, _T_2825
node _T_2826 = bits(_WIRE_209, 19, 19)
connect _WIRE_208.ae_ptw, _T_2826
node _T_2827 = bits(_WIRE_209, 20, 20)
connect _WIRE_208.g, _T_2827
node _T_2828 = bits(_WIRE_209, 21, 21)
connect _WIRE_208.u, _T_2828
node _T_2829 = bits(_WIRE_209, 41, 22)
connect _WIRE_208.ppn, _T_2829
wire _WIRE_210 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_211 : UInt<42>
connect _WIRE_211, sectored_entries[0][6].data[1]
node _T_2830 = bits(_WIRE_211, 0, 0)
connect _WIRE_210.fragmented_superpage, _T_2830
node _T_2831 = bits(_WIRE_211, 1, 1)
connect _WIRE_210.c, _T_2831
node _T_2832 = bits(_WIRE_211, 2, 2)
connect _WIRE_210.eff, _T_2832
node _T_2833 = bits(_WIRE_211, 3, 3)
connect _WIRE_210.paa, _T_2833
node _T_2834 = bits(_WIRE_211, 4, 4)
connect _WIRE_210.pal, _T_2834
node _T_2835 = bits(_WIRE_211, 5, 5)
connect _WIRE_210.ppp, _T_2835
node _T_2836 = bits(_WIRE_211, 6, 6)
connect _WIRE_210.pr, _T_2836
node _T_2837 = bits(_WIRE_211, 7, 7)
connect _WIRE_210.px, _T_2837
node _T_2838 = bits(_WIRE_211, 8, 8)
connect _WIRE_210.pw, _T_2838
node _T_2839 = bits(_WIRE_211, 9, 9)
connect _WIRE_210.hr, _T_2839
node _T_2840 = bits(_WIRE_211, 10, 10)
connect _WIRE_210.hx, _T_2840
node _T_2841 = bits(_WIRE_211, 11, 11)
connect _WIRE_210.hw, _T_2841
node _T_2842 = bits(_WIRE_211, 12, 12)
connect _WIRE_210.sr, _T_2842
node _T_2843 = bits(_WIRE_211, 13, 13)
connect _WIRE_210.sx, _T_2843
node _T_2844 = bits(_WIRE_211, 14, 14)
connect _WIRE_210.sw, _T_2844
node _T_2845 = bits(_WIRE_211, 15, 15)
connect _WIRE_210.gf, _T_2845
node _T_2846 = bits(_WIRE_211, 16, 16)
connect _WIRE_210.pf, _T_2846
node _T_2847 = bits(_WIRE_211, 17, 17)
connect _WIRE_210.ae_stage2, _T_2847
node _T_2848 = bits(_WIRE_211, 18, 18)
connect _WIRE_210.ae_final, _T_2848
node _T_2849 = bits(_WIRE_211, 19, 19)
connect _WIRE_210.ae_ptw, _T_2849
node _T_2850 = bits(_WIRE_211, 20, 20)
connect _WIRE_210.g, _T_2850
node _T_2851 = bits(_WIRE_211, 21, 21)
connect _WIRE_210.u, _T_2851
node _T_2852 = bits(_WIRE_211, 41, 22)
connect _WIRE_210.ppn, _T_2852
wire _WIRE_212 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_213 : UInt<42>
connect _WIRE_213, sectored_entries[0][6].data[2]
node _T_2853 = bits(_WIRE_213, 0, 0)
connect _WIRE_212.fragmented_superpage, _T_2853
node _T_2854 = bits(_WIRE_213, 1, 1)
connect _WIRE_212.c, _T_2854
node _T_2855 = bits(_WIRE_213, 2, 2)
connect _WIRE_212.eff, _T_2855
node _T_2856 = bits(_WIRE_213, 3, 3)
connect _WIRE_212.paa, _T_2856
node _T_2857 = bits(_WIRE_213, 4, 4)
connect _WIRE_212.pal, _T_2857
node _T_2858 = bits(_WIRE_213, 5, 5)
connect _WIRE_212.ppp, _T_2858
node _T_2859 = bits(_WIRE_213, 6, 6)
connect _WIRE_212.pr, _T_2859
node _T_2860 = bits(_WIRE_213, 7, 7)
connect _WIRE_212.px, _T_2860
node _T_2861 = bits(_WIRE_213, 8, 8)
connect _WIRE_212.pw, _T_2861
node _T_2862 = bits(_WIRE_213, 9, 9)
connect _WIRE_212.hr, _T_2862
node _T_2863 = bits(_WIRE_213, 10, 10)
connect _WIRE_212.hx, _T_2863
node _T_2864 = bits(_WIRE_213, 11, 11)
connect _WIRE_212.hw, _T_2864
node _T_2865 = bits(_WIRE_213, 12, 12)
connect _WIRE_212.sr, _T_2865
node _T_2866 = bits(_WIRE_213, 13, 13)
connect _WIRE_212.sx, _T_2866
node _T_2867 = bits(_WIRE_213, 14, 14)
connect _WIRE_212.sw, _T_2867
node _T_2868 = bits(_WIRE_213, 15, 15)
connect _WIRE_212.gf, _T_2868
node _T_2869 = bits(_WIRE_213, 16, 16)
connect _WIRE_212.pf, _T_2869
node _T_2870 = bits(_WIRE_213, 17, 17)
connect _WIRE_212.ae_stage2, _T_2870
node _T_2871 = bits(_WIRE_213, 18, 18)
connect _WIRE_212.ae_final, _T_2871
node _T_2872 = bits(_WIRE_213, 19, 19)
connect _WIRE_212.ae_ptw, _T_2872
node _T_2873 = bits(_WIRE_213, 20, 20)
connect _WIRE_212.g, _T_2873
node _T_2874 = bits(_WIRE_213, 21, 21)
connect _WIRE_212.u, _T_2874
node _T_2875 = bits(_WIRE_213, 41, 22)
connect _WIRE_212.ppn, _T_2875
wire _WIRE_214 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_215 : UInt<42>
connect _WIRE_215, sectored_entries[0][6].data[3]
node _T_2876 = bits(_WIRE_215, 0, 0)
connect _WIRE_214.fragmented_superpage, _T_2876
node _T_2877 = bits(_WIRE_215, 1, 1)
connect _WIRE_214.c, _T_2877
node _T_2878 = bits(_WIRE_215, 2, 2)
connect _WIRE_214.eff, _T_2878
node _T_2879 = bits(_WIRE_215, 3, 3)
connect _WIRE_214.paa, _T_2879
node _T_2880 = bits(_WIRE_215, 4, 4)
connect _WIRE_214.pal, _T_2880
node _T_2881 = bits(_WIRE_215, 5, 5)
connect _WIRE_214.ppp, _T_2881
node _T_2882 = bits(_WIRE_215, 6, 6)
connect _WIRE_214.pr, _T_2882
node _T_2883 = bits(_WIRE_215, 7, 7)
connect _WIRE_214.px, _T_2883
node _T_2884 = bits(_WIRE_215, 8, 8)
connect _WIRE_214.pw, _T_2884
node _T_2885 = bits(_WIRE_215, 9, 9)
connect _WIRE_214.hr, _T_2885
node _T_2886 = bits(_WIRE_215, 10, 10)
connect _WIRE_214.hx, _T_2886
node _T_2887 = bits(_WIRE_215, 11, 11)
connect _WIRE_214.hw, _T_2887
node _T_2888 = bits(_WIRE_215, 12, 12)
connect _WIRE_214.sr, _T_2888
node _T_2889 = bits(_WIRE_215, 13, 13)
connect _WIRE_214.sx, _T_2889
node _T_2890 = bits(_WIRE_215, 14, 14)
connect _WIRE_214.sw, _T_2890
node _T_2891 = bits(_WIRE_215, 15, 15)
connect _WIRE_214.gf, _T_2891
node _T_2892 = bits(_WIRE_215, 16, 16)
connect _WIRE_214.pf, _T_2892
node _T_2893 = bits(_WIRE_215, 17, 17)
connect _WIRE_214.ae_stage2, _T_2893
node _T_2894 = bits(_WIRE_215, 18, 18)
connect _WIRE_214.ae_final, _T_2894
node _T_2895 = bits(_WIRE_215, 19, 19)
connect _WIRE_214.ae_ptw, _T_2895
node _T_2896 = bits(_WIRE_215, 20, 20)
connect _WIRE_214.g, _T_2896
node _T_2897 = bits(_WIRE_215, 21, 21)
connect _WIRE_214.u, _T_2897
node _T_2898 = bits(_WIRE_215, 41, 22)
connect _WIRE_214.ppn, _T_2898
node _T_2899 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2900 = eq(_WIRE_208.g, UInt<1>(0h0))
node _T_2901 = and(_T_2899, _T_2900)
when _T_2901 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
node _T_2902 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2903 = eq(_WIRE_210.g, UInt<1>(0h0))
node _T_2904 = and(_T_2902, _T_2903)
when _T_2904 :
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
node _T_2905 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2906 = eq(_WIRE_212.g, UInt<1>(0h0))
node _T_2907 = and(_T_2905, _T_2906)
when _T_2907 :
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
node _T_2908 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2909 = eq(_WIRE_214.g, UInt<1>(0h0))
node _T_2910 = and(_T_2908, _T_2909)
when _T_2910 :
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
else :
node _T_2911 = or(hv_6, hg_6)
wire _WIRE_216 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_217 : UInt<42>
connect _WIRE_217, sectored_entries[0][6].data[0]
node _T_2912 = bits(_WIRE_217, 0, 0)
connect _WIRE_216.fragmented_superpage, _T_2912
node _T_2913 = bits(_WIRE_217, 1, 1)
connect _WIRE_216.c, _T_2913
node _T_2914 = bits(_WIRE_217, 2, 2)
connect _WIRE_216.eff, _T_2914
node _T_2915 = bits(_WIRE_217, 3, 3)
connect _WIRE_216.paa, _T_2915
node _T_2916 = bits(_WIRE_217, 4, 4)
connect _WIRE_216.pal, _T_2916
node _T_2917 = bits(_WIRE_217, 5, 5)
connect _WIRE_216.ppp, _T_2917
node _T_2918 = bits(_WIRE_217, 6, 6)
connect _WIRE_216.pr, _T_2918
node _T_2919 = bits(_WIRE_217, 7, 7)
connect _WIRE_216.px, _T_2919
node _T_2920 = bits(_WIRE_217, 8, 8)
connect _WIRE_216.pw, _T_2920
node _T_2921 = bits(_WIRE_217, 9, 9)
connect _WIRE_216.hr, _T_2921
node _T_2922 = bits(_WIRE_217, 10, 10)
connect _WIRE_216.hx, _T_2922
node _T_2923 = bits(_WIRE_217, 11, 11)
connect _WIRE_216.hw, _T_2923
node _T_2924 = bits(_WIRE_217, 12, 12)
connect _WIRE_216.sr, _T_2924
node _T_2925 = bits(_WIRE_217, 13, 13)
connect _WIRE_216.sx, _T_2925
node _T_2926 = bits(_WIRE_217, 14, 14)
connect _WIRE_216.sw, _T_2926
node _T_2927 = bits(_WIRE_217, 15, 15)
connect _WIRE_216.gf, _T_2927
node _T_2928 = bits(_WIRE_217, 16, 16)
connect _WIRE_216.pf, _T_2928
node _T_2929 = bits(_WIRE_217, 17, 17)
connect _WIRE_216.ae_stage2, _T_2929
node _T_2930 = bits(_WIRE_217, 18, 18)
connect _WIRE_216.ae_final, _T_2930
node _T_2931 = bits(_WIRE_217, 19, 19)
connect _WIRE_216.ae_ptw, _T_2931
node _T_2932 = bits(_WIRE_217, 20, 20)
connect _WIRE_216.g, _T_2932
node _T_2933 = bits(_WIRE_217, 21, 21)
connect _WIRE_216.u, _T_2933
node _T_2934 = bits(_WIRE_217, 41, 22)
connect _WIRE_216.ppn, _T_2934
wire _WIRE_218 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_219 : UInt<42>
connect _WIRE_219, sectored_entries[0][6].data[1]
node _T_2935 = bits(_WIRE_219, 0, 0)
connect _WIRE_218.fragmented_superpage, _T_2935
node _T_2936 = bits(_WIRE_219, 1, 1)
connect _WIRE_218.c, _T_2936
node _T_2937 = bits(_WIRE_219, 2, 2)
connect _WIRE_218.eff, _T_2937
node _T_2938 = bits(_WIRE_219, 3, 3)
connect _WIRE_218.paa, _T_2938
node _T_2939 = bits(_WIRE_219, 4, 4)
connect _WIRE_218.pal, _T_2939
node _T_2940 = bits(_WIRE_219, 5, 5)
connect _WIRE_218.ppp, _T_2940
node _T_2941 = bits(_WIRE_219, 6, 6)
connect _WIRE_218.pr, _T_2941
node _T_2942 = bits(_WIRE_219, 7, 7)
connect _WIRE_218.px, _T_2942
node _T_2943 = bits(_WIRE_219, 8, 8)
connect _WIRE_218.pw, _T_2943
node _T_2944 = bits(_WIRE_219, 9, 9)
connect _WIRE_218.hr, _T_2944
node _T_2945 = bits(_WIRE_219, 10, 10)
connect _WIRE_218.hx, _T_2945
node _T_2946 = bits(_WIRE_219, 11, 11)
connect _WIRE_218.hw, _T_2946
node _T_2947 = bits(_WIRE_219, 12, 12)
connect _WIRE_218.sr, _T_2947
node _T_2948 = bits(_WIRE_219, 13, 13)
connect _WIRE_218.sx, _T_2948
node _T_2949 = bits(_WIRE_219, 14, 14)
connect _WIRE_218.sw, _T_2949
node _T_2950 = bits(_WIRE_219, 15, 15)
connect _WIRE_218.gf, _T_2950
node _T_2951 = bits(_WIRE_219, 16, 16)
connect _WIRE_218.pf, _T_2951
node _T_2952 = bits(_WIRE_219, 17, 17)
connect _WIRE_218.ae_stage2, _T_2952
node _T_2953 = bits(_WIRE_219, 18, 18)
connect _WIRE_218.ae_final, _T_2953
node _T_2954 = bits(_WIRE_219, 19, 19)
connect _WIRE_218.ae_ptw, _T_2954
node _T_2955 = bits(_WIRE_219, 20, 20)
connect _WIRE_218.g, _T_2955
node _T_2956 = bits(_WIRE_219, 21, 21)
connect _WIRE_218.u, _T_2956
node _T_2957 = bits(_WIRE_219, 41, 22)
connect _WIRE_218.ppn, _T_2957
wire _WIRE_220 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_221 : UInt<42>
connect _WIRE_221, sectored_entries[0][6].data[2]
node _T_2958 = bits(_WIRE_221, 0, 0)
connect _WIRE_220.fragmented_superpage, _T_2958
node _T_2959 = bits(_WIRE_221, 1, 1)
connect _WIRE_220.c, _T_2959
node _T_2960 = bits(_WIRE_221, 2, 2)
connect _WIRE_220.eff, _T_2960
node _T_2961 = bits(_WIRE_221, 3, 3)
connect _WIRE_220.paa, _T_2961
node _T_2962 = bits(_WIRE_221, 4, 4)
connect _WIRE_220.pal, _T_2962
node _T_2963 = bits(_WIRE_221, 5, 5)
connect _WIRE_220.ppp, _T_2963
node _T_2964 = bits(_WIRE_221, 6, 6)
connect _WIRE_220.pr, _T_2964
node _T_2965 = bits(_WIRE_221, 7, 7)
connect _WIRE_220.px, _T_2965
node _T_2966 = bits(_WIRE_221, 8, 8)
connect _WIRE_220.pw, _T_2966
node _T_2967 = bits(_WIRE_221, 9, 9)
connect _WIRE_220.hr, _T_2967
node _T_2968 = bits(_WIRE_221, 10, 10)
connect _WIRE_220.hx, _T_2968
node _T_2969 = bits(_WIRE_221, 11, 11)
connect _WIRE_220.hw, _T_2969
node _T_2970 = bits(_WIRE_221, 12, 12)
connect _WIRE_220.sr, _T_2970
node _T_2971 = bits(_WIRE_221, 13, 13)
connect _WIRE_220.sx, _T_2971
node _T_2972 = bits(_WIRE_221, 14, 14)
connect _WIRE_220.sw, _T_2972
node _T_2973 = bits(_WIRE_221, 15, 15)
connect _WIRE_220.gf, _T_2973
node _T_2974 = bits(_WIRE_221, 16, 16)
connect _WIRE_220.pf, _T_2974
node _T_2975 = bits(_WIRE_221, 17, 17)
connect _WIRE_220.ae_stage2, _T_2975
node _T_2976 = bits(_WIRE_221, 18, 18)
connect _WIRE_220.ae_final, _T_2976
node _T_2977 = bits(_WIRE_221, 19, 19)
connect _WIRE_220.ae_ptw, _T_2977
node _T_2978 = bits(_WIRE_221, 20, 20)
connect _WIRE_220.g, _T_2978
node _T_2979 = bits(_WIRE_221, 21, 21)
connect _WIRE_220.u, _T_2979
node _T_2980 = bits(_WIRE_221, 41, 22)
connect _WIRE_220.ppn, _T_2980
wire _WIRE_222 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_223 : UInt<42>
connect _WIRE_223, sectored_entries[0][6].data[3]
node _T_2981 = bits(_WIRE_223, 0, 0)
connect _WIRE_222.fragmented_superpage, _T_2981
node _T_2982 = bits(_WIRE_223, 1, 1)
connect _WIRE_222.c, _T_2982
node _T_2983 = bits(_WIRE_223, 2, 2)
connect _WIRE_222.eff, _T_2983
node _T_2984 = bits(_WIRE_223, 3, 3)
connect _WIRE_222.paa, _T_2984
node _T_2985 = bits(_WIRE_223, 4, 4)
connect _WIRE_222.pal, _T_2985
node _T_2986 = bits(_WIRE_223, 5, 5)
connect _WIRE_222.ppp, _T_2986
node _T_2987 = bits(_WIRE_223, 6, 6)
connect _WIRE_222.pr, _T_2987
node _T_2988 = bits(_WIRE_223, 7, 7)
connect _WIRE_222.px, _T_2988
node _T_2989 = bits(_WIRE_223, 8, 8)
connect _WIRE_222.pw, _T_2989
node _T_2990 = bits(_WIRE_223, 9, 9)
connect _WIRE_222.hr, _T_2990
node _T_2991 = bits(_WIRE_223, 10, 10)
connect _WIRE_222.hx, _T_2991
node _T_2992 = bits(_WIRE_223, 11, 11)
connect _WIRE_222.hw, _T_2992
node _T_2993 = bits(_WIRE_223, 12, 12)
connect _WIRE_222.sr, _T_2993
node _T_2994 = bits(_WIRE_223, 13, 13)
connect _WIRE_222.sx, _T_2994
node _T_2995 = bits(_WIRE_223, 14, 14)
connect _WIRE_222.sw, _T_2995
node _T_2996 = bits(_WIRE_223, 15, 15)
connect _WIRE_222.gf, _T_2996
node _T_2997 = bits(_WIRE_223, 16, 16)
connect _WIRE_222.pf, _T_2997
node _T_2998 = bits(_WIRE_223, 17, 17)
connect _WIRE_222.ae_stage2, _T_2998
node _T_2999 = bits(_WIRE_223, 18, 18)
connect _WIRE_222.ae_final, _T_2999
node _T_3000 = bits(_WIRE_223, 19, 19)
connect _WIRE_222.ae_ptw, _T_3000
node _T_3001 = bits(_WIRE_223, 20, 20)
connect _WIRE_222.g, _T_3001
node _T_3002 = bits(_WIRE_223, 21, 21)
connect _WIRE_222.u, _T_3002
node _T_3003 = bits(_WIRE_223, 41, 22)
connect _WIRE_222.ppn, _T_3003
node _T_3004 = eq(sectored_entries[0][6].tag_v, _T_2911)
when _T_3004 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
node _T_3005 = eq(sectored_entries[0][6].tag_v, _T_2911)
when _T_3005 :
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
node _T_3006 = eq(sectored_entries[0][6].tag_v, _T_2911)
when _T_3006 :
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
node _T_3007 = eq(sectored_entries[0][6].tag_v, _T_2911)
when _T_3007 :
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
node hv_7 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_7 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3008 = eq(hg_7, UInt<1>(0h0))
node _T_3009 = and(_T_3008, io.sfence.bits.rs1)
when _T_3009 :
node _T_3010 = xor(sectored_entries[0][7].tag_vpn, vpn)
node _T_3011 = shr(_T_3010, 2)
node _T_3012 = eq(_T_3011, UInt<1>(0h0))
node _T_3013 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3014 = and(_T_3012, _T_3013)
when _T_3014 :
wire _WIRE_224 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_225 : UInt<42>
connect _WIRE_225, sectored_entries[0][7].data[0]
node _T_3015 = bits(_WIRE_225, 0, 0)
connect _WIRE_224.fragmented_superpage, _T_3015
node _T_3016 = bits(_WIRE_225, 1, 1)
connect _WIRE_224.c, _T_3016
node _T_3017 = bits(_WIRE_225, 2, 2)
connect _WIRE_224.eff, _T_3017
node _T_3018 = bits(_WIRE_225, 3, 3)
connect _WIRE_224.paa, _T_3018
node _T_3019 = bits(_WIRE_225, 4, 4)
connect _WIRE_224.pal, _T_3019
node _T_3020 = bits(_WIRE_225, 5, 5)
connect _WIRE_224.ppp, _T_3020
node _T_3021 = bits(_WIRE_225, 6, 6)
connect _WIRE_224.pr, _T_3021
node _T_3022 = bits(_WIRE_225, 7, 7)
connect _WIRE_224.px, _T_3022
node _T_3023 = bits(_WIRE_225, 8, 8)
connect _WIRE_224.pw, _T_3023
node _T_3024 = bits(_WIRE_225, 9, 9)
connect _WIRE_224.hr, _T_3024
node _T_3025 = bits(_WIRE_225, 10, 10)
connect _WIRE_224.hx, _T_3025
node _T_3026 = bits(_WIRE_225, 11, 11)
connect _WIRE_224.hw, _T_3026
node _T_3027 = bits(_WIRE_225, 12, 12)
connect _WIRE_224.sr, _T_3027
node _T_3028 = bits(_WIRE_225, 13, 13)
connect _WIRE_224.sx, _T_3028
node _T_3029 = bits(_WIRE_225, 14, 14)
connect _WIRE_224.sw, _T_3029
node _T_3030 = bits(_WIRE_225, 15, 15)
connect _WIRE_224.gf, _T_3030
node _T_3031 = bits(_WIRE_225, 16, 16)
connect _WIRE_224.pf, _T_3031
node _T_3032 = bits(_WIRE_225, 17, 17)
connect _WIRE_224.ae_stage2, _T_3032
node _T_3033 = bits(_WIRE_225, 18, 18)
connect _WIRE_224.ae_final, _T_3033
node _T_3034 = bits(_WIRE_225, 19, 19)
connect _WIRE_224.ae_ptw, _T_3034
node _T_3035 = bits(_WIRE_225, 20, 20)
connect _WIRE_224.g, _T_3035
node _T_3036 = bits(_WIRE_225, 21, 21)
connect _WIRE_224.u, _T_3036
node _T_3037 = bits(_WIRE_225, 41, 22)
connect _WIRE_224.ppn, _T_3037
wire _WIRE_226 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_227 : UInt<42>
connect _WIRE_227, sectored_entries[0][7].data[1]
node _T_3038 = bits(_WIRE_227, 0, 0)
connect _WIRE_226.fragmented_superpage, _T_3038
node _T_3039 = bits(_WIRE_227, 1, 1)
connect _WIRE_226.c, _T_3039
node _T_3040 = bits(_WIRE_227, 2, 2)
connect _WIRE_226.eff, _T_3040
node _T_3041 = bits(_WIRE_227, 3, 3)
connect _WIRE_226.paa, _T_3041
node _T_3042 = bits(_WIRE_227, 4, 4)
connect _WIRE_226.pal, _T_3042
node _T_3043 = bits(_WIRE_227, 5, 5)
connect _WIRE_226.ppp, _T_3043
node _T_3044 = bits(_WIRE_227, 6, 6)
connect _WIRE_226.pr, _T_3044
node _T_3045 = bits(_WIRE_227, 7, 7)
connect _WIRE_226.px, _T_3045
node _T_3046 = bits(_WIRE_227, 8, 8)
connect _WIRE_226.pw, _T_3046
node _T_3047 = bits(_WIRE_227, 9, 9)
connect _WIRE_226.hr, _T_3047
node _T_3048 = bits(_WIRE_227, 10, 10)
connect _WIRE_226.hx, _T_3048
node _T_3049 = bits(_WIRE_227, 11, 11)
connect _WIRE_226.hw, _T_3049
node _T_3050 = bits(_WIRE_227, 12, 12)
connect _WIRE_226.sr, _T_3050
node _T_3051 = bits(_WIRE_227, 13, 13)
connect _WIRE_226.sx, _T_3051
node _T_3052 = bits(_WIRE_227, 14, 14)
connect _WIRE_226.sw, _T_3052
node _T_3053 = bits(_WIRE_227, 15, 15)
connect _WIRE_226.gf, _T_3053
node _T_3054 = bits(_WIRE_227, 16, 16)
connect _WIRE_226.pf, _T_3054
node _T_3055 = bits(_WIRE_227, 17, 17)
connect _WIRE_226.ae_stage2, _T_3055
node _T_3056 = bits(_WIRE_227, 18, 18)
connect _WIRE_226.ae_final, _T_3056
node _T_3057 = bits(_WIRE_227, 19, 19)
connect _WIRE_226.ae_ptw, _T_3057
node _T_3058 = bits(_WIRE_227, 20, 20)
connect _WIRE_226.g, _T_3058
node _T_3059 = bits(_WIRE_227, 21, 21)
connect _WIRE_226.u, _T_3059
node _T_3060 = bits(_WIRE_227, 41, 22)
connect _WIRE_226.ppn, _T_3060
wire _WIRE_228 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_229 : UInt<42>
connect _WIRE_229, sectored_entries[0][7].data[2]
node _T_3061 = bits(_WIRE_229, 0, 0)
connect _WIRE_228.fragmented_superpage, _T_3061
node _T_3062 = bits(_WIRE_229, 1, 1)
connect _WIRE_228.c, _T_3062
node _T_3063 = bits(_WIRE_229, 2, 2)
connect _WIRE_228.eff, _T_3063
node _T_3064 = bits(_WIRE_229, 3, 3)
connect _WIRE_228.paa, _T_3064
node _T_3065 = bits(_WIRE_229, 4, 4)
connect _WIRE_228.pal, _T_3065
node _T_3066 = bits(_WIRE_229, 5, 5)
connect _WIRE_228.ppp, _T_3066
node _T_3067 = bits(_WIRE_229, 6, 6)
connect _WIRE_228.pr, _T_3067
node _T_3068 = bits(_WIRE_229, 7, 7)
connect _WIRE_228.px, _T_3068
node _T_3069 = bits(_WIRE_229, 8, 8)
connect _WIRE_228.pw, _T_3069
node _T_3070 = bits(_WIRE_229, 9, 9)
connect _WIRE_228.hr, _T_3070
node _T_3071 = bits(_WIRE_229, 10, 10)
connect _WIRE_228.hx, _T_3071
node _T_3072 = bits(_WIRE_229, 11, 11)
connect _WIRE_228.hw, _T_3072
node _T_3073 = bits(_WIRE_229, 12, 12)
connect _WIRE_228.sr, _T_3073
node _T_3074 = bits(_WIRE_229, 13, 13)
connect _WIRE_228.sx, _T_3074
node _T_3075 = bits(_WIRE_229, 14, 14)
connect _WIRE_228.sw, _T_3075
node _T_3076 = bits(_WIRE_229, 15, 15)
connect _WIRE_228.gf, _T_3076
node _T_3077 = bits(_WIRE_229, 16, 16)
connect _WIRE_228.pf, _T_3077
node _T_3078 = bits(_WIRE_229, 17, 17)
connect _WIRE_228.ae_stage2, _T_3078
node _T_3079 = bits(_WIRE_229, 18, 18)
connect _WIRE_228.ae_final, _T_3079
node _T_3080 = bits(_WIRE_229, 19, 19)
connect _WIRE_228.ae_ptw, _T_3080
node _T_3081 = bits(_WIRE_229, 20, 20)
connect _WIRE_228.g, _T_3081
node _T_3082 = bits(_WIRE_229, 21, 21)
connect _WIRE_228.u, _T_3082
node _T_3083 = bits(_WIRE_229, 41, 22)
connect _WIRE_228.ppn, _T_3083
wire _WIRE_230 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_231 : UInt<42>
connect _WIRE_231, sectored_entries[0][7].data[3]
node _T_3084 = bits(_WIRE_231, 0, 0)
connect _WIRE_230.fragmented_superpage, _T_3084
node _T_3085 = bits(_WIRE_231, 1, 1)
connect _WIRE_230.c, _T_3085
node _T_3086 = bits(_WIRE_231, 2, 2)
connect _WIRE_230.eff, _T_3086
node _T_3087 = bits(_WIRE_231, 3, 3)
connect _WIRE_230.paa, _T_3087
node _T_3088 = bits(_WIRE_231, 4, 4)
connect _WIRE_230.pal, _T_3088
node _T_3089 = bits(_WIRE_231, 5, 5)
connect _WIRE_230.ppp, _T_3089
node _T_3090 = bits(_WIRE_231, 6, 6)
connect _WIRE_230.pr, _T_3090
node _T_3091 = bits(_WIRE_231, 7, 7)
connect _WIRE_230.px, _T_3091
node _T_3092 = bits(_WIRE_231, 8, 8)
connect _WIRE_230.pw, _T_3092
node _T_3093 = bits(_WIRE_231, 9, 9)
connect _WIRE_230.hr, _T_3093
node _T_3094 = bits(_WIRE_231, 10, 10)
connect _WIRE_230.hx, _T_3094
node _T_3095 = bits(_WIRE_231, 11, 11)
connect _WIRE_230.hw, _T_3095
node _T_3096 = bits(_WIRE_231, 12, 12)
connect _WIRE_230.sr, _T_3096
node _T_3097 = bits(_WIRE_231, 13, 13)
connect _WIRE_230.sx, _T_3097
node _T_3098 = bits(_WIRE_231, 14, 14)
connect _WIRE_230.sw, _T_3098
node _T_3099 = bits(_WIRE_231, 15, 15)
connect _WIRE_230.gf, _T_3099
node _T_3100 = bits(_WIRE_231, 16, 16)
connect _WIRE_230.pf, _T_3100
node _T_3101 = bits(_WIRE_231, 17, 17)
connect _WIRE_230.ae_stage2, _T_3101
node _T_3102 = bits(_WIRE_231, 18, 18)
connect _WIRE_230.ae_final, _T_3102
node _T_3103 = bits(_WIRE_231, 19, 19)
connect _WIRE_230.ae_ptw, _T_3103
node _T_3104 = bits(_WIRE_231, 20, 20)
connect _WIRE_230.g, _T_3104
node _T_3105 = bits(_WIRE_231, 21, 21)
connect _WIRE_230.u, _T_3105
node _T_3106 = bits(_WIRE_231, 41, 22)
connect _WIRE_230.ppn, _T_3106
node _T_3107 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3108 = bits(vpn, 1, 0)
node _T_3109 = eq(UInt<1>(0h0), _T_3108)
node _T_3110 = and(_T_3107, _T_3109)
when _T_3110 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
node _T_3111 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3112 = bits(vpn, 1, 0)
node _T_3113 = eq(UInt<1>(0h1), _T_3112)
node _T_3114 = and(_T_3111, _T_3113)
when _T_3114 :
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
node _T_3115 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3116 = bits(vpn, 1, 0)
node _T_3117 = eq(UInt<2>(0h2), _T_3116)
node _T_3118 = and(_T_3115, _T_3117)
when _T_3118 :
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
node _T_3119 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3120 = bits(vpn, 1, 0)
node _T_3121 = eq(UInt<2>(0h3), _T_3120)
node _T_3122 = and(_T_3119, _T_3121)
when _T_3122 :
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
node _T_3123 = xor(sectored_entries[0][7].tag_vpn, vpn)
node _T_3124 = shr(_T_3123, 18)
node _T_3125 = eq(_T_3124, UInt<1>(0h0))
when _T_3125 :
wire _WIRE_232 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_233 : UInt<42>
connect _WIRE_233, sectored_entries[0][7].data[0]
node _T_3126 = bits(_WIRE_233, 0, 0)
connect _WIRE_232.fragmented_superpage, _T_3126
node _T_3127 = bits(_WIRE_233, 1, 1)
connect _WIRE_232.c, _T_3127
node _T_3128 = bits(_WIRE_233, 2, 2)
connect _WIRE_232.eff, _T_3128
node _T_3129 = bits(_WIRE_233, 3, 3)
connect _WIRE_232.paa, _T_3129
node _T_3130 = bits(_WIRE_233, 4, 4)
connect _WIRE_232.pal, _T_3130
node _T_3131 = bits(_WIRE_233, 5, 5)
connect _WIRE_232.ppp, _T_3131
node _T_3132 = bits(_WIRE_233, 6, 6)
connect _WIRE_232.pr, _T_3132
node _T_3133 = bits(_WIRE_233, 7, 7)
connect _WIRE_232.px, _T_3133
node _T_3134 = bits(_WIRE_233, 8, 8)
connect _WIRE_232.pw, _T_3134
node _T_3135 = bits(_WIRE_233, 9, 9)
connect _WIRE_232.hr, _T_3135
node _T_3136 = bits(_WIRE_233, 10, 10)
connect _WIRE_232.hx, _T_3136
node _T_3137 = bits(_WIRE_233, 11, 11)
connect _WIRE_232.hw, _T_3137
node _T_3138 = bits(_WIRE_233, 12, 12)
connect _WIRE_232.sr, _T_3138
node _T_3139 = bits(_WIRE_233, 13, 13)
connect _WIRE_232.sx, _T_3139
node _T_3140 = bits(_WIRE_233, 14, 14)
connect _WIRE_232.sw, _T_3140
node _T_3141 = bits(_WIRE_233, 15, 15)
connect _WIRE_232.gf, _T_3141
node _T_3142 = bits(_WIRE_233, 16, 16)
connect _WIRE_232.pf, _T_3142
node _T_3143 = bits(_WIRE_233, 17, 17)
connect _WIRE_232.ae_stage2, _T_3143
node _T_3144 = bits(_WIRE_233, 18, 18)
connect _WIRE_232.ae_final, _T_3144
node _T_3145 = bits(_WIRE_233, 19, 19)
connect _WIRE_232.ae_ptw, _T_3145
node _T_3146 = bits(_WIRE_233, 20, 20)
connect _WIRE_232.g, _T_3146
node _T_3147 = bits(_WIRE_233, 21, 21)
connect _WIRE_232.u, _T_3147
node _T_3148 = bits(_WIRE_233, 41, 22)
connect _WIRE_232.ppn, _T_3148
wire _WIRE_234 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_235 : UInt<42>
connect _WIRE_235, sectored_entries[0][7].data[1]
node _T_3149 = bits(_WIRE_235, 0, 0)
connect _WIRE_234.fragmented_superpage, _T_3149
node _T_3150 = bits(_WIRE_235, 1, 1)
connect _WIRE_234.c, _T_3150
node _T_3151 = bits(_WIRE_235, 2, 2)
connect _WIRE_234.eff, _T_3151
node _T_3152 = bits(_WIRE_235, 3, 3)
connect _WIRE_234.paa, _T_3152
node _T_3153 = bits(_WIRE_235, 4, 4)
connect _WIRE_234.pal, _T_3153
node _T_3154 = bits(_WIRE_235, 5, 5)
connect _WIRE_234.ppp, _T_3154
node _T_3155 = bits(_WIRE_235, 6, 6)
connect _WIRE_234.pr, _T_3155
node _T_3156 = bits(_WIRE_235, 7, 7)
connect _WIRE_234.px, _T_3156
node _T_3157 = bits(_WIRE_235, 8, 8)
connect _WIRE_234.pw, _T_3157
node _T_3158 = bits(_WIRE_235, 9, 9)
connect _WIRE_234.hr, _T_3158
node _T_3159 = bits(_WIRE_235, 10, 10)
connect _WIRE_234.hx, _T_3159
node _T_3160 = bits(_WIRE_235, 11, 11)
connect _WIRE_234.hw, _T_3160
node _T_3161 = bits(_WIRE_235, 12, 12)
connect _WIRE_234.sr, _T_3161
node _T_3162 = bits(_WIRE_235, 13, 13)
connect _WIRE_234.sx, _T_3162
node _T_3163 = bits(_WIRE_235, 14, 14)
connect _WIRE_234.sw, _T_3163
node _T_3164 = bits(_WIRE_235, 15, 15)
connect _WIRE_234.gf, _T_3164
node _T_3165 = bits(_WIRE_235, 16, 16)
connect _WIRE_234.pf, _T_3165
node _T_3166 = bits(_WIRE_235, 17, 17)
connect _WIRE_234.ae_stage2, _T_3166
node _T_3167 = bits(_WIRE_235, 18, 18)
connect _WIRE_234.ae_final, _T_3167
node _T_3168 = bits(_WIRE_235, 19, 19)
connect _WIRE_234.ae_ptw, _T_3168
node _T_3169 = bits(_WIRE_235, 20, 20)
connect _WIRE_234.g, _T_3169
node _T_3170 = bits(_WIRE_235, 21, 21)
connect _WIRE_234.u, _T_3170
node _T_3171 = bits(_WIRE_235, 41, 22)
connect _WIRE_234.ppn, _T_3171
wire _WIRE_236 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_237 : UInt<42>
connect _WIRE_237, sectored_entries[0][7].data[2]
node _T_3172 = bits(_WIRE_237, 0, 0)
connect _WIRE_236.fragmented_superpage, _T_3172
node _T_3173 = bits(_WIRE_237, 1, 1)
connect _WIRE_236.c, _T_3173
node _T_3174 = bits(_WIRE_237, 2, 2)
connect _WIRE_236.eff, _T_3174
node _T_3175 = bits(_WIRE_237, 3, 3)
connect _WIRE_236.paa, _T_3175
node _T_3176 = bits(_WIRE_237, 4, 4)
connect _WIRE_236.pal, _T_3176
node _T_3177 = bits(_WIRE_237, 5, 5)
connect _WIRE_236.ppp, _T_3177
node _T_3178 = bits(_WIRE_237, 6, 6)
connect _WIRE_236.pr, _T_3178
node _T_3179 = bits(_WIRE_237, 7, 7)
connect _WIRE_236.px, _T_3179
node _T_3180 = bits(_WIRE_237, 8, 8)
connect _WIRE_236.pw, _T_3180
node _T_3181 = bits(_WIRE_237, 9, 9)
connect _WIRE_236.hr, _T_3181
node _T_3182 = bits(_WIRE_237, 10, 10)
connect _WIRE_236.hx, _T_3182
node _T_3183 = bits(_WIRE_237, 11, 11)
connect _WIRE_236.hw, _T_3183
node _T_3184 = bits(_WIRE_237, 12, 12)
connect _WIRE_236.sr, _T_3184
node _T_3185 = bits(_WIRE_237, 13, 13)
connect _WIRE_236.sx, _T_3185
node _T_3186 = bits(_WIRE_237, 14, 14)
connect _WIRE_236.sw, _T_3186
node _T_3187 = bits(_WIRE_237, 15, 15)
connect _WIRE_236.gf, _T_3187
node _T_3188 = bits(_WIRE_237, 16, 16)
connect _WIRE_236.pf, _T_3188
node _T_3189 = bits(_WIRE_237, 17, 17)
connect _WIRE_236.ae_stage2, _T_3189
node _T_3190 = bits(_WIRE_237, 18, 18)
connect _WIRE_236.ae_final, _T_3190
node _T_3191 = bits(_WIRE_237, 19, 19)
connect _WIRE_236.ae_ptw, _T_3191
node _T_3192 = bits(_WIRE_237, 20, 20)
connect _WIRE_236.g, _T_3192
node _T_3193 = bits(_WIRE_237, 21, 21)
connect _WIRE_236.u, _T_3193
node _T_3194 = bits(_WIRE_237, 41, 22)
connect _WIRE_236.ppn, _T_3194
wire _WIRE_238 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_239 : UInt<42>
connect _WIRE_239, sectored_entries[0][7].data[3]
node _T_3195 = bits(_WIRE_239, 0, 0)
connect _WIRE_238.fragmented_superpage, _T_3195
node _T_3196 = bits(_WIRE_239, 1, 1)
connect _WIRE_238.c, _T_3196
node _T_3197 = bits(_WIRE_239, 2, 2)
connect _WIRE_238.eff, _T_3197
node _T_3198 = bits(_WIRE_239, 3, 3)
connect _WIRE_238.paa, _T_3198
node _T_3199 = bits(_WIRE_239, 4, 4)
connect _WIRE_238.pal, _T_3199
node _T_3200 = bits(_WIRE_239, 5, 5)
connect _WIRE_238.ppp, _T_3200
node _T_3201 = bits(_WIRE_239, 6, 6)
connect _WIRE_238.pr, _T_3201
node _T_3202 = bits(_WIRE_239, 7, 7)
connect _WIRE_238.px, _T_3202
node _T_3203 = bits(_WIRE_239, 8, 8)
connect _WIRE_238.pw, _T_3203
node _T_3204 = bits(_WIRE_239, 9, 9)
connect _WIRE_238.hr, _T_3204
node _T_3205 = bits(_WIRE_239, 10, 10)
connect _WIRE_238.hx, _T_3205
node _T_3206 = bits(_WIRE_239, 11, 11)
connect _WIRE_238.hw, _T_3206
node _T_3207 = bits(_WIRE_239, 12, 12)
connect _WIRE_238.sr, _T_3207
node _T_3208 = bits(_WIRE_239, 13, 13)
connect _WIRE_238.sx, _T_3208
node _T_3209 = bits(_WIRE_239, 14, 14)
connect _WIRE_238.sw, _T_3209
node _T_3210 = bits(_WIRE_239, 15, 15)
connect _WIRE_238.gf, _T_3210
node _T_3211 = bits(_WIRE_239, 16, 16)
connect _WIRE_238.pf, _T_3211
node _T_3212 = bits(_WIRE_239, 17, 17)
connect _WIRE_238.ae_stage2, _T_3212
node _T_3213 = bits(_WIRE_239, 18, 18)
connect _WIRE_238.ae_final, _T_3213
node _T_3214 = bits(_WIRE_239, 19, 19)
connect _WIRE_238.ae_ptw, _T_3214
node _T_3215 = bits(_WIRE_239, 20, 20)
connect _WIRE_238.g, _T_3215
node _T_3216 = bits(_WIRE_239, 21, 21)
connect _WIRE_238.u, _T_3216
node _T_3217 = bits(_WIRE_239, 41, 22)
connect _WIRE_238.ppn, _T_3217
node _T_3218 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3219 = and(_T_3218, _WIRE_232.fragmented_superpage)
when _T_3219 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
node _T_3220 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3221 = and(_T_3220, _WIRE_234.fragmented_superpage)
when _T_3221 :
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
node _T_3222 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3223 = and(_T_3222, _WIRE_236.fragmented_superpage)
when _T_3223 :
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
node _T_3224 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3225 = and(_T_3224, _WIRE_238.fragmented_superpage)
when _T_3225 :
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
else :
node _T_3226 = eq(hg_7, UInt<1>(0h0))
node _T_3227 = and(_T_3226, io.sfence.bits.rs2)
when _T_3227 :
wire _WIRE_240 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_241 : UInt<42>
connect _WIRE_241, sectored_entries[0][7].data[0]
node _T_3228 = bits(_WIRE_241, 0, 0)
connect _WIRE_240.fragmented_superpage, _T_3228
node _T_3229 = bits(_WIRE_241, 1, 1)
connect _WIRE_240.c, _T_3229
node _T_3230 = bits(_WIRE_241, 2, 2)
connect _WIRE_240.eff, _T_3230
node _T_3231 = bits(_WIRE_241, 3, 3)
connect _WIRE_240.paa, _T_3231
node _T_3232 = bits(_WIRE_241, 4, 4)
connect _WIRE_240.pal, _T_3232
node _T_3233 = bits(_WIRE_241, 5, 5)
connect _WIRE_240.ppp, _T_3233
node _T_3234 = bits(_WIRE_241, 6, 6)
connect _WIRE_240.pr, _T_3234
node _T_3235 = bits(_WIRE_241, 7, 7)
connect _WIRE_240.px, _T_3235
node _T_3236 = bits(_WIRE_241, 8, 8)
connect _WIRE_240.pw, _T_3236
node _T_3237 = bits(_WIRE_241, 9, 9)
connect _WIRE_240.hr, _T_3237
node _T_3238 = bits(_WIRE_241, 10, 10)
connect _WIRE_240.hx, _T_3238
node _T_3239 = bits(_WIRE_241, 11, 11)
connect _WIRE_240.hw, _T_3239
node _T_3240 = bits(_WIRE_241, 12, 12)
connect _WIRE_240.sr, _T_3240
node _T_3241 = bits(_WIRE_241, 13, 13)
connect _WIRE_240.sx, _T_3241
node _T_3242 = bits(_WIRE_241, 14, 14)
connect _WIRE_240.sw, _T_3242
node _T_3243 = bits(_WIRE_241, 15, 15)
connect _WIRE_240.gf, _T_3243
node _T_3244 = bits(_WIRE_241, 16, 16)
connect _WIRE_240.pf, _T_3244
node _T_3245 = bits(_WIRE_241, 17, 17)
connect _WIRE_240.ae_stage2, _T_3245
node _T_3246 = bits(_WIRE_241, 18, 18)
connect _WIRE_240.ae_final, _T_3246
node _T_3247 = bits(_WIRE_241, 19, 19)
connect _WIRE_240.ae_ptw, _T_3247
node _T_3248 = bits(_WIRE_241, 20, 20)
connect _WIRE_240.g, _T_3248
node _T_3249 = bits(_WIRE_241, 21, 21)
connect _WIRE_240.u, _T_3249
node _T_3250 = bits(_WIRE_241, 41, 22)
connect _WIRE_240.ppn, _T_3250
wire _WIRE_242 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_243 : UInt<42>
connect _WIRE_243, sectored_entries[0][7].data[1]
node _T_3251 = bits(_WIRE_243, 0, 0)
connect _WIRE_242.fragmented_superpage, _T_3251
node _T_3252 = bits(_WIRE_243, 1, 1)
connect _WIRE_242.c, _T_3252
node _T_3253 = bits(_WIRE_243, 2, 2)
connect _WIRE_242.eff, _T_3253
node _T_3254 = bits(_WIRE_243, 3, 3)
connect _WIRE_242.paa, _T_3254
node _T_3255 = bits(_WIRE_243, 4, 4)
connect _WIRE_242.pal, _T_3255
node _T_3256 = bits(_WIRE_243, 5, 5)
connect _WIRE_242.ppp, _T_3256
node _T_3257 = bits(_WIRE_243, 6, 6)
connect _WIRE_242.pr, _T_3257
node _T_3258 = bits(_WIRE_243, 7, 7)
connect _WIRE_242.px, _T_3258
node _T_3259 = bits(_WIRE_243, 8, 8)
connect _WIRE_242.pw, _T_3259
node _T_3260 = bits(_WIRE_243, 9, 9)
connect _WIRE_242.hr, _T_3260
node _T_3261 = bits(_WIRE_243, 10, 10)
connect _WIRE_242.hx, _T_3261
node _T_3262 = bits(_WIRE_243, 11, 11)
connect _WIRE_242.hw, _T_3262
node _T_3263 = bits(_WIRE_243, 12, 12)
connect _WIRE_242.sr, _T_3263
node _T_3264 = bits(_WIRE_243, 13, 13)
connect _WIRE_242.sx, _T_3264
node _T_3265 = bits(_WIRE_243, 14, 14)
connect _WIRE_242.sw, _T_3265
node _T_3266 = bits(_WIRE_243, 15, 15)
connect _WIRE_242.gf, _T_3266
node _T_3267 = bits(_WIRE_243, 16, 16)
connect _WIRE_242.pf, _T_3267
node _T_3268 = bits(_WIRE_243, 17, 17)
connect _WIRE_242.ae_stage2, _T_3268
node _T_3269 = bits(_WIRE_243, 18, 18)
connect _WIRE_242.ae_final, _T_3269
node _T_3270 = bits(_WIRE_243, 19, 19)
connect _WIRE_242.ae_ptw, _T_3270
node _T_3271 = bits(_WIRE_243, 20, 20)
connect _WIRE_242.g, _T_3271
node _T_3272 = bits(_WIRE_243, 21, 21)
connect _WIRE_242.u, _T_3272
node _T_3273 = bits(_WIRE_243, 41, 22)
connect _WIRE_242.ppn, _T_3273
wire _WIRE_244 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_245 : UInt<42>
connect _WIRE_245, sectored_entries[0][7].data[2]
node _T_3274 = bits(_WIRE_245, 0, 0)
connect _WIRE_244.fragmented_superpage, _T_3274
node _T_3275 = bits(_WIRE_245, 1, 1)
connect _WIRE_244.c, _T_3275
node _T_3276 = bits(_WIRE_245, 2, 2)
connect _WIRE_244.eff, _T_3276
node _T_3277 = bits(_WIRE_245, 3, 3)
connect _WIRE_244.paa, _T_3277
node _T_3278 = bits(_WIRE_245, 4, 4)
connect _WIRE_244.pal, _T_3278
node _T_3279 = bits(_WIRE_245, 5, 5)
connect _WIRE_244.ppp, _T_3279
node _T_3280 = bits(_WIRE_245, 6, 6)
connect _WIRE_244.pr, _T_3280
node _T_3281 = bits(_WIRE_245, 7, 7)
connect _WIRE_244.px, _T_3281
node _T_3282 = bits(_WIRE_245, 8, 8)
connect _WIRE_244.pw, _T_3282
node _T_3283 = bits(_WIRE_245, 9, 9)
connect _WIRE_244.hr, _T_3283
node _T_3284 = bits(_WIRE_245, 10, 10)
connect _WIRE_244.hx, _T_3284
node _T_3285 = bits(_WIRE_245, 11, 11)
connect _WIRE_244.hw, _T_3285
node _T_3286 = bits(_WIRE_245, 12, 12)
connect _WIRE_244.sr, _T_3286
node _T_3287 = bits(_WIRE_245, 13, 13)
connect _WIRE_244.sx, _T_3287
node _T_3288 = bits(_WIRE_245, 14, 14)
connect _WIRE_244.sw, _T_3288
node _T_3289 = bits(_WIRE_245, 15, 15)
connect _WIRE_244.gf, _T_3289
node _T_3290 = bits(_WIRE_245, 16, 16)
connect _WIRE_244.pf, _T_3290
node _T_3291 = bits(_WIRE_245, 17, 17)
connect _WIRE_244.ae_stage2, _T_3291
node _T_3292 = bits(_WIRE_245, 18, 18)
connect _WIRE_244.ae_final, _T_3292
node _T_3293 = bits(_WIRE_245, 19, 19)
connect _WIRE_244.ae_ptw, _T_3293
node _T_3294 = bits(_WIRE_245, 20, 20)
connect _WIRE_244.g, _T_3294
node _T_3295 = bits(_WIRE_245, 21, 21)
connect _WIRE_244.u, _T_3295
node _T_3296 = bits(_WIRE_245, 41, 22)
connect _WIRE_244.ppn, _T_3296
wire _WIRE_246 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_247 : UInt<42>
connect _WIRE_247, sectored_entries[0][7].data[3]
node _T_3297 = bits(_WIRE_247, 0, 0)
connect _WIRE_246.fragmented_superpage, _T_3297
node _T_3298 = bits(_WIRE_247, 1, 1)
connect _WIRE_246.c, _T_3298
node _T_3299 = bits(_WIRE_247, 2, 2)
connect _WIRE_246.eff, _T_3299
node _T_3300 = bits(_WIRE_247, 3, 3)
connect _WIRE_246.paa, _T_3300
node _T_3301 = bits(_WIRE_247, 4, 4)
connect _WIRE_246.pal, _T_3301
node _T_3302 = bits(_WIRE_247, 5, 5)
connect _WIRE_246.ppp, _T_3302
node _T_3303 = bits(_WIRE_247, 6, 6)
connect _WIRE_246.pr, _T_3303
node _T_3304 = bits(_WIRE_247, 7, 7)
connect _WIRE_246.px, _T_3304
node _T_3305 = bits(_WIRE_247, 8, 8)
connect _WIRE_246.pw, _T_3305
node _T_3306 = bits(_WIRE_247, 9, 9)
connect _WIRE_246.hr, _T_3306
node _T_3307 = bits(_WIRE_247, 10, 10)
connect _WIRE_246.hx, _T_3307
node _T_3308 = bits(_WIRE_247, 11, 11)
connect _WIRE_246.hw, _T_3308
node _T_3309 = bits(_WIRE_247, 12, 12)
connect _WIRE_246.sr, _T_3309
node _T_3310 = bits(_WIRE_247, 13, 13)
connect _WIRE_246.sx, _T_3310
node _T_3311 = bits(_WIRE_247, 14, 14)
connect _WIRE_246.sw, _T_3311
node _T_3312 = bits(_WIRE_247, 15, 15)
connect _WIRE_246.gf, _T_3312
node _T_3313 = bits(_WIRE_247, 16, 16)
connect _WIRE_246.pf, _T_3313
node _T_3314 = bits(_WIRE_247, 17, 17)
connect _WIRE_246.ae_stage2, _T_3314
node _T_3315 = bits(_WIRE_247, 18, 18)
connect _WIRE_246.ae_final, _T_3315
node _T_3316 = bits(_WIRE_247, 19, 19)
connect _WIRE_246.ae_ptw, _T_3316
node _T_3317 = bits(_WIRE_247, 20, 20)
connect _WIRE_246.g, _T_3317
node _T_3318 = bits(_WIRE_247, 21, 21)
connect _WIRE_246.u, _T_3318
node _T_3319 = bits(_WIRE_247, 41, 22)
connect _WIRE_246.ppn, _T_3319
node _T_3320 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3321 = eq(_WIRE_240.g, UInt<1>(0h0))
node _T_3322 = and(_T_3320, _T_3321)
when _T_3322 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
node _T_3323 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3324 = eq(_WIRE_242.g, UInt<1>(0h0))
node _T_3325 = and(_T_3323, _T_3324)
when _T_3325 :
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
node _T_3326 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3327 = eq(_WIRE_244.g, UInt<1>(0h0))
node _T_3328 = and(_T_3326, _T_3327)
when _T_3328 :
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
node _T_3329 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3330 = eq(_WIRE_246.g, UInt<1>(0h0))
node _T_3331 = and(_T_3329, _T_3330)
when _T_3331 :
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
else :
node _T_3332 = or(hv_7, hg_7)
wire _WIRE_248 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_249 : UInt<42>
connect _WIRE_249, sectored_entries[0][7].data[0]
node _T_3333 = bits(_WIRE_249, 0, 0)
connect _WIRE_248.fragmented_superpage, _T_3333
node _T_3334 = bits(_WIRE_249, 1, 1)
connect _WIRE_248.c, _T_3334
node _T_3335 = bits(_WIRE_249, 2, 2)
connect _WIRE_248.eff, _T_3335
node _T_3336 = bits(_WIRE_249, 3, 3)
connect _WIRE_248.paa, _T_3336
node _T_3337 = bits(_WIRE_249, 4, 4)
connect _WIRE_248.pal, _T_3337
node _T_3338 = bits(_WIRE_249, 5, 5)
connect _WIRE_248.ppp, _T_3338
node _T_3339 = bits(_WIRE_249, 6, 6)
connect _WIRE_248.pr, _T_3339
node _T_3340 = bits(_WIRE_249, 7, 7)
connect _WIRE_248.px, _T_3340
node _T_3341 = bits(_WIRE_249, 8, 8)
connect _WIRE_248.pw, _T_3341
node _T_3342 = bits(_WIRE_249, 9, 9)
connect _WIRE_248.hr, _T_3342
node _T_3343 = bits(_WIRE_249, 10, 10)
connect _WIRE_248.hx, _T_3343
node _T_3344 = bits(_WIRE_249, 11, 11)
connect _WIRE_248.hw, _T_3344
node _T_3345 = bits(_WIRE_249, 12, 12)
connect _WIRE_248.sr, _T_3345
node _T_3346 = bits(_WIRE_249, 13, 13)
connect _WIRE_248.sx, _T_3346
node _T_3347 = bits(_WIRE_249, 14, 14)
connect _WIRE_248.sw, _T_3347
node _T_3348 = bits(_WIRE_249, 15, 15)
connect _WIRE_248.gf, _T_3348
node _T_3349 = bits(_WIRE_249, 16, 16)
connect _WIRE_248.pf, _T_3349
node _T_3350 = bits(_WIRE_249, 17, 17)
connect _WIRE_248.ae_stage2, _T_3350
node _T_3351 = bits(_WIRE_249, 18, 18)
connect _WIRE_248.ae_final, _T_3351
node _T_3352 = bits(_WIRE_249, 19, 19)
connect _WIRE_248.ae_ptw, _T_3352
node _T_3353 = bits(_WIRE_249, 20, 20)
connect _WIRE_248.g, _T_3353
node _T_3354 = bits(_WIRE_249, 21, 21)
connect _WIRE_248.u, _T_3354
node _T_3355 = bits(_WIRE_249, 41, 22)
connect _WIRE_248.ppn, _T_3355
wire _WIRE_250 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_251 : UInt<42>
connect _WIRE_251, sectored_entries[0][7].data[1]
node _T_3356 = bits(_WIRE_251, 0, 0)
connect _WIRE_250.fragmented_superpage, _T_3356
node _T_3357 = bits(_WIRE_251, 1, 1)
connect _WIRE_250.c, _T_3357
node _T_3358 = bits(_WIRE_251, 2, 2)
connect _WIRE_250.eff, _T_3358
node _T_3359 = bits(_WIRE_251, 3, 3)
connect _WIRE_250.paa, _T_3359
node _T_3360 = bits(_WIRE_251, 4, 4)
connect _WIRE_250.pal, _T_3360
node _T_3361 = bits(_WIRE_251, 5, 5)
connect _WIRE_250.ppp, _T_3361
node _T_3362 = bits(_WIRE_251, 6, 6)
connect _WIRE_250.pr, _T_3362
node _T_3363 = bits(_WIRE_251, 7, 7)
connect _WIRE_250.px, _T_3363
node _T_3364 = bits(_WIRE_251, 8, 8)
connect _WIRE_250.pw, _T_3364
node _T_3365 = bits(_WIRE_251, 9, 9)
connect _WIRE_250.hr, _T_3365
node _T_3366 = bits(_WIRE_251, 10, 10)
connect _WIRE_250.hx, _T_3366
node _T_3367 = bits(_WIRE_251, 11, 11)
connect _WIRE_250.hw, _T_3367
node _T_3368 = bits(_WIRE_251, 12, 12)
connect _WIRE_250.sr, _T_3368
node _T_3369 = bits(_WIRE_251, 13, 13)
connect _WIRE_250.sx, _T_3369
node _T_3370 = bits(_WIRE_251, 14, 14)
connect _WIRE_250.sw, _T_3370
node _T_3371 = bits(_WIRE_251, 15, 15)
connect _WIRE_250.gf, _T_3371
node _T_3372 = bits(_WIRE_251, 16, 16)
connect _WIRE_250.pf, _T_3372
node _T_3373 = bits(_WIRE_251, 17, 17)
connect _WIRE_250.ae_stage2, _T_3373
node _T_3374 = bits(_WIRE_251, 18, 18)
connect _WIRE_250.ae_final, _T_3374
node _T_3375 = bits(_WIRE_251, 19, 19)
connect _WIRE_250.ae_ptw, _T_3375
node _T_3376 = bits(_WIRE_251, 20, 20)
connect _WIRE_250.g, _T_3376
node _T_3377 = bits(_WIRE_251, 21, 21)
connect _WIRE_250.u, _T_3377
node _T_3378 = bits(_WIRE_251, 41, 22)
connect _WIRE_250.ppn, _T_3378
wire _WIRE_252 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_253 : UInt<42>
connect _WIRE_253, sectored_entries[0][7].data[2]
node _T_3379 = bits(_WIRE_253, 0, 0)
connect _WIRE_252.fragmented_superpage, _T_3379
node _T_3380 = bits(_WIRE_253, 1, 1)
connect _WIRE_252.c, _T_3380
node _T_3381 = bits(_WIRE_253, 2, 2)
connect _WIRE_252.eff, _T_3381
node _T_3382 = bits(_WIRE_253, 3, 3)
connect _WIRE_252.paa, _T_3382
node _T_3383 = bits(_WIRE_253, 4, 4)
connect _WIRE_252.pal, _T_3383
node _T_3384 = bits(_WIRE_253, 5, 5)
connect _WIRE_252.ppp, _T_3384
node _T_3385 = bits(_WIRE_253, 6, 6)
connect _WIRE_252.pr, _T_3385
node _T_3386 = bits(_WIRE_253, 7, 7)
connect _WIRE_252.px, _T_3386
node _T_3387 = bits(_WIRE_253, 8, 8)
connect _WIRE_252.pw, _T_3387
node _T_3388 = bits(_WIRE_253, 9, 9)
connect _WIRE_252.hr, _T_3388
node _T_3389 = bits(_WIRE_253, 10, 10)
connect _WIRE_252.hx, _T_3389
node _T_3390 = bits(_WIRE_253, 11, 11)
connect _WIRE_252.hw, _T_3390
node _T_3391 = bits(_WIRE_253, 12, 12)
connect _WIRE_252.sr, _T_3391
node _T_3392 = bits(_WIRE_253, 13, 13)
connect _WIRE_252.sx, _T_3392
node _T_3393 = bits(_WIRE_253, 14, 14)
connect _WIRE_252.sw, _T_3393
node _T_3394 = bits(_WIRE_253, 15, 15)
connect _WIRE_252.gf, _T_3394
node _T_3395 = bits(_WIRE_253, 16, 16)
connect _WIRE_252.pf, _T_3395
node _T_3396 = bits(_WIRE_253, 17, 17)
connect _WIRE_252.ae_stage2, _T_3396
node _T_3397 = bits(_WIRE_253, 18, 18)
connect _WIRE_252.ae_final, _T_3397
node _T_3398 = bits(_WIRE_253, 19, 19)
connect _WIRE_252.ae_ptw, _T_3398
node _T_3399 = bits(_WIRE_253, 20, 20)
connect _WIRE_252.g, _T_3399
node _T_3400 = bits(_WIRE_253, 21, 21)
connect _WIRE_252.u, _T_3400
node _T_3401 = bits(_WIRE_253, 41, 22)
connect _WIRE_252.ppn, _T_3401
wire _WIRE_254 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_255 : UInt<42>
connect _WIRE_255, sectored_entries[0][7].data[3]
node _T_3402 = bits(_WIRE_255, 0, 0)
connect _WIRE_254.fragmented_superpage, _T_3402
node _T_3403 = bits(_WIRE_255, 1, 1)
connect _WIRE_254.c, _T_3403
node _T_3404 = bits(_WIRE_255, 2, 2)
connect _WIRE_254.eff, _T_3404
node _T_3405 = bits(_WIRE_255, 3, 3)
connect _WIRE_254.paa, _T_3405
node _T_3406 = bits(_WIRE_255, 4, 4)
connect _WIRE_254.pal, _T_3406
node _T_3407 = bits(_WIRE_255, 5, 5)
connect _WIRE_254.ppp, _T_3407
node _T_3408 = bits(_WIRE_255, 6, 6)
connect _WIRE_254.pr, _T_3408
node _T_3409 = bits(_WIRE_255, 7, 7)
connect _WIRE_254.px, _T_3409
node _T_3410 = bits(_WIRE_255, 8, 8)
connect _WIRE_254.pw, _T_3410
node _T_3411 = bits(_WIRE_255, 9, 9)
connect _WIRE_254.hr, _T_3411
node _T_3412 = bits(_WIRE_255, 10, 10)
connect _WIRE_254.hx, _T_3412
node _T_3413 = bits(_WIRE_255, 11, 11)
connect _WIRE_254.hw, _T_3413
node _T_3414 = bits(_WIRE_255, 12, 12)
connect _WIRE_254.sr, _T_3414
node _T_3415 = bits(_WIRE_255, 13, 13)
connect _WIRE_254.sx, _T_3415
node _T_3416 = bits(_WIRE_255, 14, 14)
connect _WIRE_254.sw, _T_3416
node _T_3417 = bits(_WIRE_255, 15, 15)
connect _WIRE_254.gf, _T_3417
node _T_3418 = bits(_WIRE_255, 16, 16)
connect _WIRE_254.pf, _T_3418
node _T_3419 = bits(_WIRE_255, 17, 17)
connect _WIRE_254.ae_stage2, _T_3419
node _T_3420 = bits(_WIRE_255, 18, 18)
connect _WIRE_254.ae_final, _T_3420
node _T_3421 = bits(_WIRE_255, 19, 19)
connect _WIRE_254.ae_ptw, _T_3421
node _T_3422 = bits(_WIRE_255, 20, 20)
connect _WIRE_254.g, _T_3422
node _T_3423 = bits(_WIRE_255, 21, 21)
connect _WIRE_254.u, _T_3423
node _T_3424 = bits(_WIRE_255, 41, 22)
connect _WIRE_254.ppn, _T_3424
node _T_3425 = eq(sectored_entries[0][7].tag_v, _T_3332)
when _T_3425 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
node _T_3426 = eq(sectored_entries[0][7].tag_v, _T_3332)
when _T_3426 :
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
node _T_3427 = eq(sectored_entries[0][7].tag_v, _T_3332)
when _T_3427 :
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
node _T_3428 = eq(sectored_entries[0][7].tag_v, _T_3332)
when _T_3428 :
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
node hv_8 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_8 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3429 = eq(hg_8, UInt<1>(0h0))
node _T_3430 = and(_T_3429, io.sfence.bits.rs1)
when _T_3430 :
node _tagMatch_T = eq(superpage_entries[0].tag_v, hv_8)
node tagMatch = and(superpage_entries[0].valid[0], _tagMatch_T)
node _ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0))
node ignore = or(_ignore_T, UInt<1>(0h0))
node _T_3431 = xor(superpage_entries[0].tag_vpn, vpn)
node _T_3432 = bits(_T_3431, 26, 18)
node _T_3433 = eq(_T_3432, UInt<1>(0h0))
node _T_3434 = or(ignore, _T_3433)
node _T_3435 = and(tagMatch, _T_3434)
node _ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1))
node ignore_1 = or(_ignore_T_1, UInt<1>(0h0))
node _T_3436 = xor(superpage_entries[0].tag_vpn, vpn)
node _T_3437 = bits(_T_3436, 17, 9)
node _T_3438 = eq(_T_3437, UInt<1>(0h0))
node _T_3439 = or(ignore_1, _T_3438)
node _T_3440 = and(_T_3435, _T_3439)
node _ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2))
node ignore_2 = or(_ignore_T_2, UInt<1>(0h1))
node _T_3441 = xor(superpage_entries[0].tag_vpn, vpn)
node _T_3442 = bits(_T_3441, 8, 0)
node _T_3443 = eq(_T_3442, UInt<1>(0h0))
node _T_3444 = or(ignore_2, _T_3443)
node _T_3445 = and(_T_3440, _T_3444)
when _T_3445 :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
node _T_3446 = xor(superpage_entries[0].tag_vpn, vpn)
node _T_3447 = shr(_T_3446, 18)
node _T_3448 = eq(_T_3447, UInt<1>(0h0))
when _T_3448 :
wire _WIRE_256 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_257 : UInt<42>
connect _WIRE_257, superpage_entries[0].data[0]
node _T_3449 = bits(_WIRE_257, 0, 0)
connect _WIRE_256.fragmented_superpage, _T_3449
node _T_3450 = bits(_WIRE_257, 1, 1)
connect _WIRE_256.c, _T_3450
node _T_3451 = bits(_WIRE_257, 2, 2)
connect _WIRE_256.eff, _T_3451
node _T_3452 = bits(_WIRE_257, 3, 3)
connect _WIRE_256.paa, _T_3452
node _T_3453 = bits(_WIRE_257, 4, 4)
connect _WIRE_256.pal, _T_3453
node _T_3454 = bits(_WIRE_257, 5, 5)
connect _WIRE_256.ppp, _T_3454
node _T_3455 = bits(_WIRE_257, 6, 6)
connect _WIRE_256.pr, _T_3455
node _T_3456 = bits(_WIRE_257, 7, 7)
connect _WIRE_256.px, _T_3456
node _T_3457 = bits(_WIRE_257, 8, 8)
connect _WIRE_256.pw, _T_3457
node _T_3458 = bits(_WIRE_257, 9, 9)
connect _WIRE_256.hr, _T_3458
node _T_3459 = bits(_WIRE_257, 10, 10)
connect _WIRE_256.hx, _T_3459
node _T_3460 = bits(_WIRE_257, 11, 11)
connect _WIRE_256.hw, _T_3460
node _T_3461 = bits(_WIRE_257, 12, 12)
connect _WIRE_256.sr, _T_3461
node _T_3462 = bits(_WIRE_257, 13, 13)
connect _WIRE_256.sx, _T_3462
node _T_3463 = bits(_WIRE_257, 14, 14)
connect _WIRE_256.sw, _T_3463
node _T_3464 = bits(_WIRE_257, 15, 15)
connect _WIRE_256.gf, _T_3464
node _T_3465 = bits(_WIRE_257, 16, 16)
connect _WIRE_256.pf, _T_3465
node _T_3466 = bits(_WIRE_257, 17, 17)
connect _WIRE_256.ae_stage2, _T_3466
node _T_3467 = bits(_WIRE_257, 18, 18)
connect _WIRE_256.ae_final, _T_3467
node _T_3468 = bits(_WIRE_257, 19, 19)
connect _WIRE_256.ae_ptw, _T_3468
node _T_3469 = bits(_WIRE_257, 20, 20)
connect _WIRE_256.g, _T_3469
node _T_3470 = bits(_WIRE_257, 21, 21)
connect _WIRE_256.u, _T_3470
node _T_3471 = bits(_WIRE_257, 41, 22)
connect _WIRE_256.ppn, _T_3471
node _T_3472 = eq(superpage_entries[0].tag_v, hv_8)
node _T_3473 = and(_T_3472, _WIRE_256.fragmented_superpage)
when _T_3473 :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
else :
node _T_3474 = eq(hg_8, UInt<1>(0h0))
node _T_3475 = and(_T_3474, io.sfence.bits.rs2)
when _T_3475 :
wire _WIRE_258 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_259 : UInt<42>
connect _WIRE_259, superpage_entries[0].data[0]
node _T_3476 = bits(_WIRE_259, 0, 0)
connect _WIRE_258.fragmented_superpage, _T_3476
node _T_3477 = bits(_WIRE_259, 1, 1)
connect _WIRE_258.c, _T_3477
node _T_3478 = bits(_WIRE_259, 2, 2)
connect _WIRE_258.eff, _T_3478
node _T_3479 = bits(_WIRE_259, 3, 3)
connect _WIRE_258.paa, _T_3479
node _T_3480 = bits(_WIRE_259, 4, 4)
connect _WIRE_258.pal, _T_3480
node _T_3481 = bits(_WIRE_259, 5, 5)
connect _WIRE_258.ppp, _T_3481
node _T_3482 = bits(_WIRE_259, 6, 6)
connect _WIRE_258.pr, _T_3482
node _T_3483 = bits(_WIRE_259, 7, 7)
connect _WIRE_258.px, _T_3483
node _T_3484 = bits(_WIRE_259, 8, 8)
connect _WIRE_258.pw, _T_3484
node _T_3485 = bits(_WIRE_259, 9, 9)
connect _WIRE_258.hr, _T_3485
node _T_3486 = bits(_WIRE_259, 10, 10)
connect _WIRE_258.hx, _T_3486
node _T_3487 = bits(_WIRE_259, 11, 11)
connect _WIRE_258.hw, _T_3487
node _T_3488 = bits(_WIRE_259, 12, 12)
connect _WIRE_258.sr, _T_3488
node _T_3489 = bits(_WIRE_259, 13, 13)
connect _WIRE_258.sx, _T_3489
node _T_3490 = bits(_WIRE_259, 14, 14)
connect _WIRE_258.sw, _T_3490
node _T_3491 = bits(_WIRE_259, 15, 15)
connect _WIRE_258.gf, _T_3491
node _T_3492 = bits(_WIRE_259, 16, 16)
connect _WIRE_258.pf, _T_3492
node _T_3493 = bits(_WIRE_259, 17, 17)
connect _WIRE_258.ae_stage2, _T_3493
node _T_3494 = bits(_WIRE_259, 18, 18)
connect _WIRE_258.ae_final, _T_3494
node _T_3495 = bits(_WIRE_259, 19, 19)
connect _WIRE_258.ae_ptw, _T_3495
node _T_3496 = bits(_WIRE_259, 20, 20)
connect _WIRE_258.g, _T_3496
node _T_3497 = bits(_WIRE_259, 21, 21)
connect _WIRE_258.u, _T_3497
node _T_3498 = bits(_WIRE_259, 41, 22)
connect _WIRE_258.ppn, _T_3498
node _T_3499 = eq(superpage_entries[0].tag_v, hv_8)
node _T_3500 = eq(_WIRE_258.g, UInt<1>(0h0))
node _T_3501 = and(_T_3499, _T_3500)
when _T_3501 :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
else :
node _T_3502 = or(hv_8, hg_8)
wire _WIRE_260 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_261 : UInt<42>
connect _WIRE_261, superpage_entries[0].data[0]
node _T_3503 = bits(_WIRE_261, 0, 0)
connect _WIRE_260.fragmented_superpage, _T_3503
node _T_3504 = bits(_WIRE_261, 1, 1)
connect _WIRE_260.c, _T_3504
node _T_3505 = bits(_WIRE_261, 2, 2)
connect _WIRE_260.eff, _T_3505
node _T_3506 = bits(_WIRE_261, 3, 3)
connect _WIRE_260.paa, _T_3506
node _T_3507 = bits(_WIRE_261, 4, 4)
connect _WIRE_260.pal, _T_3507
node _T_3508 = bits(_WIRE_261, 5, 5)
connect _WIRE_260.ppp, _T_3508
node _T_3509 = bits(_WIRE_261, 6, 6)
connect _WIRE_260.pr, _T_3509
node _T_3510 = bits(_WIRE_261, 7, 7)
connect _WIRE_260.px, _T_3510
node _T_3511 = bits(_WIRE_261, 8, 8)
connect _WIRE_260.pw, _T_3511
node _T_3512 = bits(_WIRE_261, 9, 9)
connect _WIRE_260.hr, _T_3512
node _T_3513 = bits(_WIRE_261, 10, 10)
connect _WIRE_260.hx, _T_3513
node _T_3514 = bits(_WIRE_261, 11, 11)
connect _WIRE_260.hw, _T_3514
node _T_3515 = bits(_WIRE_261, 12, 12)
connect _WIRE_260.sr, _T_3515
node _T_3516 = bits(_WIRE_261, 13, 13)
connect _WIRE_260.sx, _T_3516
node _T_3517 = bits(_WIRE_261, 14, 14)
connect _WIRE_260.sw, _T_3517
node _T_3518 = bits(_WIRE_261, 15, 15)
connect _WIRE_260.gf, _T_3518
node _T_3519 = bits(_WIRE_261, 16, 16)
connect _WIRE_260.pf, _T_3519
node _T_3520 = bits(_WIRE_261, 17, 17)
connect _WIRE_260.ae_stage2, _T_3520
node _T_3521 = bits(_WIRE_261, 18, 18)
connect _WIRE_260.ae_final, _T_3521
node _T_3522 = bits(_WIRE_261, 19, 19)
connect _WIRE_260.ae_ptw, _T_3522
node _T_3523 = bits(_WIRE_261, 20, 20)
connect _WIRE_260.g, _T_3523
node _T_3524 = bits(_WIRE_261, 21, 21)
connect _WIRE_260.u, _T_3524
node _T_3525 = bits(_WIRE_261, 41, 22)
connect _WIRE_260.ppn, _T_3525
node _T_3526 = eq(superpage_entries[0].tag_v, _T_3502)
when _T_3526 :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
node hv_9 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_9 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3527 = eq(hg_9, UInt<1>(0h0))
node _T_3528 = and(_T_3527, io.sfence.bits.rs1)
when _T_3528 :
node _tagMatch_T_1 = eq(superpage_entries[1].tag_v, hv_9)
node tagMatch_1 = and(superpage_entries[1].valid[0], _tagMatch_T_1)
node _ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0))
node ignore_3 = or(_ignore_T_3, UInt<1>(0h0))
node _T_3529 = xor(superpage_entries[1].tag_vpn, vpn)
node _T_3530 = bits(_T_3529, 26, 18)
node _T_3531 = eq(_T_3530, UInt<1>(0h0))
node _T_3532 = or(ignore_3, _T_3531)
node _T_3533 = and(tagMatch_1, _T_3532)
node _ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1))
node ignore_4 = or(_ignore_T_4, UInt<1>(0h0))
node _T_3534 = xor(superpage_entries[1].tag_vpn, vpn)
node _T_3535 = bits(_T_3534, 17, 9)
node _T_3536 = eq(_T_3535, UInt<1>(0h0))
node _T_3537 = or(ignore_4, _T_3536)
node _T_3538 = and(_T_3533, _T_3537)
node _ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2))
node ignore_5 = or(_ignore_T_5, UInt<1>(0h1))
node _T_3539 = xor(superpage_entries[1].tag_vpn, vpn)
node _T_3540 = bits(_T_3539, 8, 0)
node _T_3541 = eq(_T_3540, UInt<1>(0h0))
node _T_3542 = or(ignore_5, _T_3541)
node _T_3543 = and(_T_3538, _T_3542)
when _T_3543 :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
node _T_3544 = xor(superpage_entries[1].tag_vpn, vpn)
node _T_3545 = shr(_T_3544, 18)
node _T_3546 = eq(_T_3545, UInt<1>(0h0))
when _T_3546 :
wire _WIRE_262 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_263 : UInt<42>
connect _WIRE_263, superpage_entries[1].data[0]
node _T_3547 = bits(_WIRE_263, 0, 0)
connect _WIRE_262.fragmented_superpage, _T_3547
node _T_3548 = bits(_WIRE_263, 1, 1)
connect _WIRE_262.c, _T_3548
node _T_3549 = bits(_WIRE_263, 2, 2)
connect _WIRE_262.eff, _T_3549
node _T_3550 = bits(_WIRE_263, 3, 3)
connect _WIRE_262.paa, _T_3550
node _T_3551 = bits(_WIRE_263, 4, 4)
connect _WIRE_262.pal, _T_3551
node _T_3552 = bits(_WIRE_263, 5, 5)
connect _WIRE_262.ppp, _T_3552
node _T_3553 = bits(_WIRE_263, 6, 6)
connect _WIRE_262.pr, _T_3553
node _T_3554 = bits(_WIRE_263, 7, 7)
connect _WIRE_262.px, _T_3554
node _T_3555 = bits(_WIRE_263, 8, 8)
connect _WIRE_262.pw, _T_3555
node _T_3556 = bits(_WIRE_263, 9, 9)
connect _WIRE_262.hr, _T_3556
node _T_3557 = bits(_WIRE_263, 10, 10)
connect _WIRE_262.hx, _T_3557
node _T_3558 = bits(_WIRE_263, 11, 11)
connect _WIRE_262.hw, _T_3558
node _T_3559 = bits(_WIRE_263, 12, 12)
connect _WIRE_262.sr, _T_3559
node _T_3560 = bits(_WIRE_263, 13, 13)
connect _WIRE_262.sx, _T_3560
node _T_3561 = bits(_WIRE_263, 14, 14)
connect _WIRE_262.sw, _T_3561
node _T_3562 = bits(_WIRE_263, 15, 15)
connect _WIRE_262.gf, _T_3562
node _T_3563 = bits(_WIRE_263, 16, 16)
connect _WIRE_262.pf, _T_3563
node _T_3564 = bits(_WIRE_263, 17, 17)
connect _WIRE_262.ae_stage2, _T_3564
node _T_3565 = bits(_WIRE_263, 18, 18)
connect _WIRE_262.ae_final, _T_3565
node _T_3566 = bits(_WIRE_263, 19, 19)
connect _WIRE_262.ae_ptw, _T_3566
node _T_3567 = bits(_WIRE_263, 20, 20)
connect _WIRE_262.g, _T_3567
node _T_3568 = bits(_WIRE_263, 21, 21)
connect _WIRE_262.u, _T_3568
node _T_3569 = bits(_WIRE_263, 41, 22)
connect _WIRE_262.ppn, _T_3569
node _T_3570 = eq(superpage_entries[1].tag_v, hv_9)
node _T_3571 = and(_T_3570, _WIRE_262.fragmented_superpage)
when _T_3571 :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
else :
node _T_3572 = eq(hg_9, UInt<1>(0h0))
node _T_3573 = and(_T_3572, io.sfence.bits.rs2)
when _T_3573 :
wire _WIRE_264 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_265 : UInt<42>
connect _WIRE_265, superpage_entries[1].data[0]
node _T_3574 = bits(_WIRE_265, 0, 0)
connect _WIRE_264.fragmented_superpage, _T_3574
node _T_3575 = bits(_WIRE_265, 1, 1)
connect _WIRE_264.c, _T_3575
node _T_3576 = bits(_WIRE_265, 2, 2)
connect _WIRE_264.eff, _T_3576
node _T_3577 = bits(_WIRE_265, 3, 3)
connect _WIRE_264.paa, _T_3577
node _T_3578 = bits(_WIRE_265, 4, 4)
connect _WIRE_264.pal, _T_3578
node _T_3579 = bits(_WIRE_265, 5, 5)
connect _WIRE_264.ppp, _T_3579
node _T_3580 = bits(_WIRE_265, 6, 6)
connect _WIRE_264.pr, _T_3580
node _T_3581 = bits(_WIRE_265, 7, 7)
connect _WIRE_264.px, _T_3581
node _T_3582 = bits(_WIRE_265, 8, 8)
connect _WIRE_264.pw, _T_3582
node _T_3583 = bits(_WIRE_265, 9, 9)
connect _WIRE_264.hr, _T_3583
node _T_3584 = bits(_WIRE_265, 10, 10)
connect _WIRE_264.hx, _T_3584
node _T_3585 = bits(_WIRE_265, 11, 11)
connect _WIRE_264.hw, _T_3585
node _T_3586 = bits(_WIRE_265, 12, 12)
connect _WIRE_264.sr, _T_3586
node _T_3587 = bits(_WIRE_265, 13, 13)
connect _WIRE_264.sx, _T_3587
node _T_3588 = bits(_WIRE_265, 14, 14)
connect _WIRE_264.sw, _T_3588
node _T_3589 = bits(_WIRE_265, 15, 15)
connect _WIRE_264.gf, _T_3589
node _T_3590 = bits(_WIRE_265, 16, 16)
connect _WIRE_264.pf, _T_3590
node _T_3591 = bits(_WIRE_265, 17, 17)
connect _WIRE_264.ae_stage2, _T_3591
node _T_3592 = bits(_WIRE_265, 18, 18)
connect _WIRE_264.ae_final, _T_3592
node _T_3593 = bits(_WIRE_265, 19, 19)
connect _WIRE_264.ae_ptw, _T_3593
node _T_3594 = bits(_WIRE_265, 20, 20)
connect _WIRE_264.g, _T_3594
node _T_3595 = bits(_WIRE_265, 21, 21)
connect _WIRE_264.u, _T_3595
node _T_3596 = bits(_WIRE_265, 41, 22)
connect _WIRE_264.ppn, _T_3596
node _T_3597 = eq(superpage_entries[1].tag_v, hv_9)
node _T_3598 = eq(_WIRE_264.g, UInt<1>(0h0))
node _T_3599 = and(_T_3597, _T_3598)
when _T_3599 :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
else :
node _T_3600 = or(hv_9, hg_9)
wire _WIRE_266 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_267 : UInt<42>
connect _WIRE_267, superpage_entries[1].data[0]
node _T_3601 = bits(_WIRE_267, 0, 0)
connect _WIRE_266.fragmented_superpage, _T_3601
node _T_3602 = bits(_WIRE_267, 1, 1)
connect _WIRE_266.c, _T_3602
node _T_3603 = bits(_WIRE_267, 2, 2)
connect _WIRE_266.eff, _T_3603
node _T_3604 = bits(_WIRE_267, 3, 3)
connect _WIRE_266.paa, _T_3604
node _T_3605 = bits(_WIRE_267, 4, 4)
connect _WIRE_266.pal, _T_3605
node _T_3606 = bits(_WIRE_267, 5, 5)
connect _WIRE_266.ppp, _T_3606
node _T_3607 = bits(_WIRE_267, 6, 6)
connect _WIRE_266.pr, _T_3607
node _T_3608 = bits(_WIRE_267, 7, 7)
connect _WIRE_266.px, _T_3608
node _T_3609 = bits(_WIRE_267, 8, 8)
connect _WIRE_266.pw, _T_3609
node _T_3610 = bits(_WIRE_267, 9, 9)
connect _WIRE_266.hr, _T_3610
node _T_3611 = bits(_WIRE_267, 10, 10)
connect _WIRE_266.hx, _T_3611
node _T_3612 = bits(_WIRE_267, 11, 11)
connect _WIRE_266.hw, _T_3612
node _T_3613 = bits(_WIRE_267, 12, 12)
connect _WIRE_266.sr, _T_3613
node _T_3614 = bits(_WIRE_267, 13, 13)
connect _WIRE_266.sx, _T_3614
node _T_3615 = bits(_WIRE_267, 14, 14)
connect _WIRE_266.sw, _T_3615
node _T_3616 = bits(_WIRE_267, 15, 15)
connect _WIRE_266.gf, _T_3616
node _T_3617 = bits(_WIRE_267, 16, 16)
connect _WIRE_266.pf, _T_3617
node _T_3618 = bits(_WIRE_267, 17, 17)
connect _WIRE_266.ae_stage2, _T_3618
node _T_3619 = bits(_WIRE_267, 18, 18)
connect _WIRE_266.ae_final, _T_3619
node _T_3620 = bits(_WIRE_267, 19, 19)
connect _WIRE_266.ae_ptw, _T_3620
node _T_3621 = bits(_WIRE_267, 20, 20)
connect _WIRE_266.g, _T_3621
node _T_3622 = bits(_WIRE_267, 21, 21)
connect _WIRE_266.u, _T_3622
node _T_3623 = bits(_WIRE_267, 41, 22)
connect _WIRE_266.ppn, _T_3623
node _T_3624 = eq(superpage_entries[1].tag_v, _T_3600)
when _T_3624 :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
node hv_10 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_10 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3625 = eq(hg_10, UInt<1>(0h0))
node _T_3626 = and(_T_3625, io.sfence.bits.rs1)
when _T_3626 :
node _tagMatch_T_2 = eq(superpage_entries[2].tag_v, hv_10)
node tagMatch_2 = and(superpage_entries[2].valid[0], _tagMatch_T_2)
node _ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0))
node ignore_6 = or(_ignore_T_6, UInt<1>(0h0))
node _T_3627 = xor(superpage_entries[2].tag_vpn, vpn)
node _T_3628 = bits(_T_3627, 26, 18)
node _T_3629 = eq(_T_3628, UInt<1>(0h0))
node _T_3630 = or(ignore_6, _T_3629)
node _T_3631 = and(tagMatch_2, _T_3630)
node _ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1))
node ignore_7 = or(_ignore_T_7, UInt<1>(0h0))
node _T_3632 = xor(superpage_entries[2].tag_vpn, vpn)
node _T_3633 = bits(_T_3632, 17, 9)
node _T_3634 = eq(_T_3633, UInt<1>(0h0))
node _T_3635 = or(ignore_7, _T_3634)
node _T_3636 = and(_T_3631, _T_3635)
node _ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2))
node ignore_8 = or(_ignore_T_8, UInt<1>(0h1))
node _T_3637 = xor(superpage_entries[2].tag_vpn, vpn)
node _T_3638 = bits(_T_3637, 8, 0)
node _T_3639 = eq(_T_3638, UInt<1>(0h0))
node _T_3640 = or(ignore_8, _T_3639)
node _T_3641 = and(_T_3636, _T_3640)
when _T_3641 :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
node _T_3642 = xor(superpage_entries[2].tag_vpn, vpn)
node _T_3643 = shr(_T_3642, 18)
node _T_3644 = eq(_T_3643, UInt<1>(0h0))
when _T_3644 :
wire _WIRE_268 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_269 : UInt<42>
connect _WIRE_269, superpage_entries[2].data[0]
node _T_3645 = bits(_WIRE_269, 0, 0)
connect _WIRE_268.fragmented_superpage, _T_3645
node _T_3646 = bits(_WIRE_269, 1, 1)
connect _WIRE_268.c, _T_3646
node _T_3647 = bits(_WIRE_269, 2, 2)
connect _WIRE_268.eff, _T_3647
node _T_3648 = bits(_WIRE_269, 3, 3)
connect _WIRE_268.paa, _T_3648
node _T_3649 = bits(_WIRE_269, 4, 4)
connect _WIRE_268.pal, _T_3649
node _T_3650 = bits(_WIRE_269, 5, 5)
connect _WIRE_268.ppp, _T_3650
node _T_3651 = bits(_WIRE_269, 6, 6)
connect _WIRE_268.pr, _T_3651
node _T_3652 = bits(_WIRE_269, 7, 7)
connect _WIRE_268.px, _T_3652
node _T_3653 = bits(_WIRE_269, 8, 8)
connect _WIRE_268.pw, _T_3653
node _T_3654 = bits(_WIRE_269, 9, 9)
connect _WIRE_268.hr, _T_3654
node _T_3655 = bits(_WIRE_269, 10, 10)
connect _WIRE_268.hx, _T_3655
node _T_3656 = bits(_WIRE_269, 11, 11)
connect _WIRE_268.hw, _T_3656
node _T_3657 = bits(_WIRE_269, 12, 12)
connect _WIRE_268.sr, _T_3657
node _T_3658 = bits(_WIRE_269, 13, 13)
connect _WIRE_268.sx, _T_3658
node _T_3659 = bits(_WIRE_269, 14, 14)
connect _WIRE_268.sw, _T_3659
node _T_3660 = bits(_WIRE_269, 15, 15)
connect _WIRE_268.gf, _T_3660
node _T_3661 = bits(_WIRE_269, 16, 16)
connect _WIRE_268.pf, _T_3661
node _T_3662 = bits(_WIRE_269, 17, 17)
connect _WIRE_268.ae_stage2, _T_3662
node _T_3663 = bits(_WIRE_269, 18, 18)
connect _WIRE_268.ae_final, _T_3663
node _T_3664 = bits(_WIRE_269, 19, 19)
connect _WIRE_268.ae_ptw, _T_3664
node _T_3665 = bits(_WIRE_269, 20, 20)
connect _WIRE_268.g, _T_3665
node _T_3666 = bits(_WIRE_269, 21, 21)
connect _WIRE_268.u, _T_3666
node _T_3667 = bits(_WIRE_269, 41, 22)
connect _WIRE_268.ppn, _T_3667
node _T_3668 = eq(superpage_entries[2].tag_v, hv_10)
node _T_3669 = and(_T_3668, _WIRE_268.fragmented_superpage)
when _T_3669 :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
else :
node _T_3670 = eq(hg_10, UInt<1>(0h0))
node _T_3671 = and(_T_3670, io.sfence.bits.rs2)
when _T_3671 :
wire _WIRE_270 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_271 : UInt<42>
connect _WIRE_271, superpage_entries[2].data[0]
node _T_3672 = bits(_WIRE_271, 0, 0)
connect _WIRE_270.fragmented_superpage, _T_3672
node _T_3673 = bits(_WIRE_271, 1, 1)
connect _WIRE_270.c, _T_3673
node _T_3674 = bits(_WIRE_271, 2, 2)
connect _WIRE_270.eff, _T_3674
node _T_3675 = bits(_WIRE_271, 3, 3)
connect _WIRE_270.paa, _T_3675
node _T_3676 = bits(_WIRE_271, 4, 4)
connect _WIRE_270.pal, _T_3676
node _T_3677 = bits(_WIRE_271, 5, 5)
connect _WIRE_270.ppp, _T_3677
node _T_3678 = bits(_WIRE_271, 6, 6)
connect _WIRE_270.pr, _T_3678
node _T_3679 = bits(_WIRE_271, 7, 7)
connect _WIRE_270.px, _T_3679
node _T_3680 = bits(_WIRE_271, 8, 8)
connect _WIRE_270.pw, _T_3680
node _T_3681 = bits(_WIRE_271, 9, 9)
connect _WIRE_270.hr, _T_3681
node _T_3682 = bits(_WIRE_271, 10, 10)
connect _WIRE_270.hx, _T_3682
node _T_3683 = bits(_WIRE_271, 11, 11)
connect _WIRE_270.hw, _T_3683
node _T_3684 = bits(_WIRE_271, 12, 12)
connect _WIRE_270.sr, _T_3684
node _T_3685 = bits(_WIRE_271, 13, 13)
connect _WIRE_270.sx, _T_3685
node _T_3686 = bits(_WIRE_271, 14, 14)
connect _WIRE_270.sw, _T_3686
node _T_3687 = bits(_WIRE_271, 15, 15)
connect _WIRE_270.gf, _T_3687
node _T_3688 = bits(_WIRE_271, 16, 16)
connect _WIRE_270.pf, _T_3688
node _T_3689 = bits(_WIRE_271, 17, 17)
connect _WIRE_270.ae_stage2, _T_3689
node _T_3690 = bits(_WIRE_271, 18, 18)
connect _WIRE_270.ae_final, _T_3690
node _T_3691 = bits(_WIRE_271, 19, 19)
connect _WIRE_270.ae_ptw, _T_3691
node _T_3692 = bits(_WIRE_271, 20, 20)
connect _WIRE_270.g, _T_3692
node _T_3693 = bits(_WIRE_271, 21, 21)
connect _WIRE_270.u, _T_3693
node _T_3694 = bits(_WIRE_271, 41, 22)
connect _WIRE_270.ppn, _T_3694
node _T_3695 = eq(superpage_entries[2].tag_v, hv_10)
node _T_3696 = eq(_WIRE_270.g, UInt<1>(0h0))
node _T_3697 = and(_T_3695, _T_3696)
when _T_3697 :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
else :
node _T_3698 = or(hv_10, hg_10)
wire _WIRE_272 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_273 : UInt<42>
connect _WIRE_273, superpage_entries[2].data[0]
node _T_3699 = bits(_WIRE_273, 0, 0)
connect _WIRE_272.fragmented_superpage, _T_3699
node _T_3700 = bits(_WIRE_273, 1, 1)
connect _WIRE_272.c, _T_3700
node _T_3701 = bits(_WIRE_273, 2, 2)
connect _WIRE_272.eff, _T_3701
node _T_3702 = bits(_WIRE_273, 3, 3)
connect _WIRE_272.paa, _T_3702
node _T_3703 = bits(_WIRE_273, 4, 4)
connect _WIRE_272.pal, _T_3703
node _T_3704 = bits(_WIRE_273, 5, 5)
connect _WIRE_272.ppp, _T_3704
node _T_3705 = bits(_WIRE_273, 6, 6)
connect _WIRE_272.pr, _T_3705
node _T_3706 = bits(_WIRE_273, 7, 7)
connect _WIRE_272.px, _T_3706
node _T_3707 = bits(_WIRE_273, 8, 8)
connect _WIRE_272.pw, _T_3707
node _T_3708 = bits(_WIRE_273, 9, 9)
connect _WIRE_272.hr, _T_3708
node _T_3709 = bits(_WIRE_273, 10, 10)
connect _WIRE_272.hx, _T_3709
node _T_3710 = bits(_WIRE_273, 11, 11)
connect _WIRE_272.hw, _T_3710
node _T_3711 = bits(_WIRE_273, 12, 12)
connect _WIRE_272.sr, _T_3711
node _T_3712 = bits(_WIRE_273, 13, 13)
connect _WIRE_272.sx, _T_3712
node _T_3713 = bits(_WIRE_273, 14, 14)
connect _WIRE_272.sw, _T_3713
node _T_3714 = bits(_WIRE_273, 15, 15)
connect _WIRE_272.gf, _T_3714
node _T_3715 = bits(_WIRE_273, 16, 16)
connect _WIRE_272.pf, _T_3715
node _T_3716 = bits(_WIRE_273, 17, 17)
connect _WIRE_272.ae_stage2, _T_3716
node _T_3717 = bits(_WIRE_273, 18, 18)
connect _WIRE_272.ae_final, _T_3717
node _T_3718 = bits(_WIRE_273, 19, 19)
connect _WIRE_272.ae_ptw, _T_3718
node _T_3719 = bits(_WIRE_273, 20, 20)
connect _WIRE_272.g, _T_3719
node _T_3720 = bits(_WIRE_273, 21, 21)
connect _WIRE_272.u, _T_3720
node _T_3721 = bits(_WIRE_273, 41, 22)
connect _WIRE_272.ppn, _T_3721
node _T_3722 = eq(superpage_entries[2].tag_v, _T_3698)
when _T_3722 :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
node hv_11 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_11 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3723 = eq(hg_11, UInt<1>(0h0))
node _T_3724 = and(_T_3723, io.sfence.bits.rs1)
when _T_3724 :
node _tagMatch_T_3 = eq(superpage_entries[3].tag_v, hv_11)
node tagMatch_3 = and(superpage_entries[3].valid[0], _tagMatch_T_3)
node _ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0))
node ignore_9 = or(_ignore_T_9, UInt<1>(0h0))
node _T_3725 = xor(superpage_entries[3].tag_vpn, vpn)
node _T_3726 = bits(_T_3725, 26, 18)
node _T_3727 = eq(_T_3726, UInt<1>(0h0))
node _T_3728 = or(ignore_9, _T_3727)
node _T_3729 = and(tagMatch_3, _T_3728)
node _ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1))
node ignore_10 = or(_ignore_T_10, UInt<1>(0h0))
node _T_3730 = xor(superpage_entries[3].tag_vpn, vpn)
node _T_3731 = bits(_T_3730, 17, 9)
node _T_3732 = eq(_T_3731, UInt<1>(0h0))
node _T_3733 = or(ignore_10, _T_3732)
node _T_3734 = and(_T_3729, _T_3733)
node _ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2))
node ignore_11 = or(_ignore_T_11, UInt<1>(0h1))
node _T_3735 = xor(superpage_entries[3].tag_vpn, vpn)
node _T_3736 = bits(_T_3735, 8, 0)
node _T_3737 = eq(_T_3736, UInt<1>(0h0))
node _T_3738 = or(ignore_11, _T_3737)
node _T_3739 = and(_T_3734, _T_3738)
when _T_3739 :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
node _T_3740 = xor(superpage_entries[3].tag_vpn, vpn)
node _T_3741 = shr(_T_3740, 18)
node _T_3742 = eq(_T_3741, UInt<1>(0h0))
when _T_3742 :
wire _WIRE_274 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_275 : UInt<42>
connect _WIRE_275, superpage_entries[3].data[0]
node _T_3743 = bits(_WIRE_275, 0, 0)
connect _WIRE_274.fragmented_superpage, _T_3743
node _T_3744 = bits(_WIRE_275, 1, 1)
connect _WIRE_274.c, _T_3744
node _T_3745 = bits(_WIRE_275, 2, 2)
connect _WIRE_274.eff, _T_3745
node _T_3746 = bits(_WIRE_275, 3, 3)
connect _WIRE_274.paa, _T_3746
node _T_3747 = bits(_WIRE_275, 4, 4)
connect _WIRE_274.pal, _T_3747
node _T_3748 = bits(_WIRE_275, 5, 5)
connect _WIRE_274.ppp, _T_3748
node _T_3749 = bits(_WIRE_275, 6, 6)
connect _WIRE_274.pr, _T_3749
node _T_3750 = bits(_WIRE_275, 7, 7)
connect _WIRE_274.px, _T_3750
node _T_3751 = bits(_WIRE_275, 8, 8)
connect _WIRE_274.pw, _T_3751
node _T_3752 = bits(_WIRE_275, 9, 9)
connect _WIRE_274.hr, _T_3752
node _T_3753 = bits(_WIRE_275, 10, 10)
connect _WIRE_274.hx, _T_3753
node _T_3754 = bits(_WIRE_275, 11, 11)
connect _WIRE_274.hw, _T_3754
node _T_3755 = bits(_WIRE_275, 12, 12)
connect _WIRE_274.sr, _T_3755
node _T_3756 = bits(_WIRE_275, 13, 13)
connect _WIRE_274.sx, _T_3756
node _T_3757 = bits(_WIRE_275, 14, 14)
connect _WIRE_274.sw, _T_3757
node _T_3758 = bits(_WIRE_275, 15, 15)
connect _WIRE_274.gf, _T_3758
node _T_3759 = bits(_WIRE_275, 16, 16)
connect _WIRE_274.pf, _T_3759
node _T_3760 = bits(_WIRE_275, 17, 17)
connect _WIRE_274.ae_stage2, _T_3760
node _T_3761 = bits(_WIRE_275, 18, 18)
connect _WIRE_274.ae_final, _T_3761
node _T_3762 = bits(_WIRE_275, 19, 19)
connect _WIRE_274.ae_ptw, _T_3762
node _T_3763 = bits(_WIRE_275, 20, 20)
connect _WIRE_274.g, _T_3763
node _T_3764 = bits(_WIRE_275, 21, 21)
connect _WIRE_274.u, _T_3764
node _T_3765 = bits(_WIRE_275, 41, 22)
connect _WIRE_274.ppn, _T_3765
node _T_3766 = eq(superpage_entries[3].tag_v, hv_11)
node _T_3767 = and(_T_3766, _WIRE_274.fragmented_superpage)
when _T_3767 :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
else :
node _T_3768 = eq(hg_11, UInt<1>(0h0))
node _T_3769 = and(_T_3768, io.sfence.bits.rs2)
when _T_3769 :
wire _WIRE_276 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_277 : UInt<42>
connect _WIRE_277, superpage_entries[3].data[0]
node _T_3770 = bits(_WIRE_277, 0, 0)
connect _WIRE_276.fragmented_superpage, _T_3770
node _T_3771 = bits(_WIRE_277, 1, 1)
connect _WIRE_276.c, _T_3771
node _T_3772 = bits(_WIRE_277, 2, 2)
connect _WIRE_276.eff, _T_3772
node _T_3773 = bits(_WIRE_277, 3, 3)
connect _WIRE_276.paa, _T_3773
node _T_3774 = bits(_WIRE_277, 4, 4)
connect _WIRE_276.pal, _T_3774
node _T_3775 = bits(_WIRE_277, 5, 5)
connect _WIRE_276.ppp, _T_3775
node _T_3776 = bits(_WIRE_277, 6, 6)
connect _WIRE_276.pr, _T_3776
node _T_3777 = bits(_WIRE_277, 7, 7)
connect _WIRE_276.px, _T_3777
node _T_3778 = bits(_WIRE_277, 8, 8)
connect _WIRE_276.pw, _T_3778
node _T_3779 = bits(_WIRE_277, 9, 9)
connect _WIRE_276.hr, _T_3779
node _T_3780 = bits(_WIRE_277, 10, 10)
connect _WIRE_276.hx, _T_3780
node _T_3781 = bits(_WIRE_277, 11, 11)
connect _WIRE_276.hw, _T_3781
node _T_3782 = bits(_WIRE_277, 12, 12)
connect _WIRE_276.sr, _T_3782
node _T_3783 = bits(_WIRE_277, 13, 13)
connect _WIRE_276.sx, _T_3783
node _T_3784 = bits(_WIRE_277, 14, 14)
connect _WIRE_276.sw, _T_3784
node _T_3785 = bits(_WIRE_277, 15, 15)
connect _WIRE_276.gf, _T_3785
node _T_3786 = bits(_WIRE_277, 16, 16)
connect _WIRE_276.pf, _T_3786
node _T_3787 = bits(_WIRE_277, 17, 17)
connect _WIRE_276.ae_stage2, _T_3787
node _T_3788 = bits(_WIRE_277, 18, 18)
connect _WIRE_276.ae_final, _T_3788
node _T_3789 = bits(_WIRE_277, 19, 19)
connect _WIRE_276.ae_ptw, _T_3789
node _T_3790 = bits(_WIRE_277, 20, 20)
connect _WIRE_276.g, _T_3790
node _T_3791 = bits(_WIRE_277, 21, 21)
connect _WIRE_276.u, _T_3791
node _T_3792 = bits(_WIRE_277, 41, 22)
connect _WIRE_276.ppn, _T_3792
node _T_3793 = eq(superpage_entries[3].tag_v, hv_11)
node _T_3794 = eq(_WIRE_276.g, UInt<1>(0h0))
node _T_3795 = and(_T_3793, _T_3794)
when _T_3795 :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
else :
node _T_3796 = or(hv_11, hg_11)
wire _WIRE_278 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_279 : UInt<42>
connect _WIRE_279, superpage_entries[3].data[0]
node _T_3797 = bits(_WIRE_279, 0, 0)
connect _WIRE_278.fragmented_superpage, _T_3797
node _T_3798 = bits(_WIRE_279, 1, 1)
connect _WIRE_278.c, _T_3798
node _T_3799 = bits(_WIRE_279, 2, 2)
connect _WIRE_278.eff, _T_3799
node _T_3800 = bits(_WIRE_279, 3, 3)
connect _WIRE_278.paa, _T_3800
node _T_3801 = bits(_WIRE_279, 4, 4)
connect _WIRE_278.pal, _T_3801
node _T_3802 = bits(_WIRE_279, 5, 5)
connect _WIRE_278.ppp, _T_3802
node _T_3803 = bits(_WIRE_279, 6, 6)
connect _WIRE_278.pr, _T_3803
node _T_3804 = bits(_WIRE_279, 7, 7)
connect _WIRE_278.px, _T_3804
node _T_3805 = bits(_WIRE_279, 8, 8)
connect _WIRE_278.pw, _T_3805
node _T_3806 = bits(_WIRE_279, 9, 9)
connect _WIRE_278.hr, _T_3806
node _T_3807 = bits(_WIRE_279, 10, 10)
connect _WIRE_278.hx, _T_3807
node _T_3808 = bits(_WIRE_279, 11, 11)
connect _WIRE_278.hw, _T_3808
node _T_3809 = bits(_WIRE_279, 12, 12)
connect _WIRE_278.sr, _T_3809
node _T_3810 = bits(_WIRE_279, 13, 13)
connect _WIRE_278.sx, _T_3810
node _T_3811 = bits(_WIRE_279, 14, 14)
connect _WIRE_278.sw, _T_3811
node _T_3812 = bits(_WIRE_279, 15, 15)
connect _WIRE_278.gf, _T_3812
node _T_3813 = bits(_WIRE_279, 16, 16)
connect _WIRE_278.pf, _T_3813
node _T_3814 = bits(_WIRE_279, 17, 17)
connect _WIRE_278.ae_stage2, _T_3814
node _T_3815 = bits(_WIRE_279, 18, 18)
connect _WIRE_278.ae_final, _T_3815
node _T_3816 = bits(_WIRE_279, 19, 19)
connect _WIRE_278.ae_ptw, _T_3816
node _T_3817 = bits(_WIRE_279, 20, 20)
connect _WIRE_278.g, _T_3817
node _T_3818 = bits(_WIRE_279, 21, 21)
connect _WIRE_278.u, _T_3818
node _T_3819 = bits(_WIRE_279, 41, 22)
connect _WIRE_278.ppn, _T_3819
node _T_3820 = eq(superpage_entries[3].tag_v, _T_3796)
when _T_3820 :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
node hv_12 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_12 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3821 = eq(hg_12, UInt<1>(0h0))
node _T_3822 = and(_T_3821, io.sfence.bits.rs1)
when _T_3822 :
node _tagMatch_T_4 = eq(special_entry.tag_v, hv_12)
node tagMatch_4 = and(special_entry.valid[0], _tagMatch_T_4)
node _ignore_T_12 = lt(special_entry.level, UInt<1>(0h0))
node ignore_12 = or(_ignore_T_12, UInt<1>(0h0))
node _T_3823 = xor(special_entry.tag_vpn, vpn)
node _T_3824 = bits(_T_3823, 26, 18)
node _T_3825 = eq(_T_3824, UInt<1>(0h0))
node _T_3826 = or(ignore_12, _T_3825)
node _T_3827 = and(tagMatch_4, _T_3826)
node _ignore_T_13 = lt(special_entry.level, UInt<1>(0h1))
node ignore_13 = or(_ignore_T_13, UInt<1>(0h0))
node _T_3828 = xor(special_entry.tag_vpn, vpn)
node _T_3829 = bits(_T_3828, 17, 9)
node _T_3830 = eq(_T_3829, UInt<1>(0h0))
node _T_3831 = or(ignore_13, _T_3830)
node _T_3832 = and(_T_3827, _T_3831)
node _ignore_T_14 = lt(special_entry.level, UInt<2>(0h2))
node ignore_14 = or(_ignore_T_14, UInt<1>(0h0))
node _T_3833 = xor(special_entry.tag_vpn, vpn)
node _T_3834 = bits(_T_3833, 8, 0)
node _T_3835 = eq(_T_3834, UInt<1>(0h0))
node _T_3836 = or(ignore_14, _T_3835)
node _T_3837 = and(_T_3832, _T_3836)
when _T_3837 :
connect special_entry.valid[0], UInt<1>(0h0)
node _T_3838 = xor(special_entry.tag_vpn, vpn)
node _T_3839 = shr(_T_3838, 18)
node _T_3840 = eq(_T_3839, UInt<1>(0h0))
when _T_3840 :
wire _WIRE_280 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_281 : UInt<42>
connect _WIRE_281, special_entry.data[0]
node _T_3841 = bits(_WIRE_281, 0, 0)
connect _WIRE_280.fragmented_superpage, _T_3841
node _T_3842 = bits(_WIRE_281, 1, 1)
connect _WIRE_280.c, _T_3842
node _T_3843 = bits(_WIRE_281, 2, 2)
connect _WIRE_280.eff, _T_3843
node _T_3844 = bits(_WIRE_281, 3, 3)
connect _WIRE_280.paa, _T_3844
node _T_3845 = bits(_WIRE_281, 4, 4)
connect _WIRE_280.pal, _T_3845
node _T_3846 = bits(_WIRE_281, 5, 5)
connect _WIRE_280.ppp, _T_3846
node _T_3847 = bits(_WIRE_281, 6, 6)
connect _WIRE_280.pr, _T_3847
node _T_3848 = bits(_WIRE_281, 7, 7)
connect _WIRE_280.px, _T_3848
node _T_3849 = bits(_WIRE_281, 8, 8)
connect _WIRE_280.pw, _T_3849
node _T_3850 = bits(_WIRE_281, 9, 9)
connect _WIRE_280.hr, _T_3850
node _T_3851 = bits(_WIRE_281, 10, 10)
connect _WIRE_280.hx, _T_3851
node _T_3852 = bits(_WIRE_281, 11, 11)
connect _WIRE_280.hw, _T_3852
node _T_3853 = bits(_WIRE_281, 12, 12)
connect _WIRE_280.sr, _T_3853
node _T_3854 = bits(_WIRE_281, 13, 13)
connect _WIRE_280.sx, _T_3854
node _T_3855 = bits(_WIRE_281, 14, 14)
connect _WIRE_280.sw, _T_3855
node _T_3856 = bits(_WIRE_281, 15, 15)
connect _WIRE_280.gf, _T_3856
node _T_3857 = bits(_WIRE_281, 16, 16)
connect _WIRE_280.pf, _T_3857
node _T_3858 = bits(_WIRE_281, 17, 17)
connect _WIRE_280.ae_stage2, _T_3858
node _T_3859 = bits(_WIRE_281, 18, 18)
connect _WIRE_280.ae_final, _T_3859
node _T_3860 = bits(_WIRE_281, 19, 19)
connect _WIRE_280.ae_ptw, _T_3860
node _T_3861 = bits(_WIRE_281, 20, 20)
connect _WIRE_280.g, _T_3861
node _T_3862 = bits(_WIRE_281, 21, 21)
connect _WIRE_280.u, _T_3862
node _T_3863 = bits(_WIRE_281, 41, 22)
connect _WIRE_280.ppn, _T_3863
node _T_3864 = eq(special_entry.tag_v, hv_12)
node _T_3865 = and(_T_3864, _WIRE_280.fragmented_superpage)
when _T_3865 :
connect special_entry.valid[0], UInt<1>(0h0)
else :
node _T_3866 = eq(hg_12, UInt<1>(0h0))
node _T_3867 = and(_T_3866, io.sfence.bits.rs2)
when _T_3867 :
wire _WIRE_282 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_283 : UInt<42>
connect _WIRE_283, special_entry.data[0]
node _T_3868 = bits(_WIRE_283, 0, 0)
connect _WIRE_282.fragmented_superpage, _T_3868
node _T_3869 = bits(_WIRE_283, 1, 1)
connect _WIRE_282.c, _T_3869
node _T_3870 = bits(_WIRE_283, 2, 2)
connect _WIRE_282.eff, _T_3870
node _T_3871 = bits(_WIRE_283, 3, 3)
connect _WIRE_282.paa, _T_3871
node _T_3872 = bits(_WIRE_283, 4, 4)
connect _WIRE_282.pal, _T_3872
node _T_3873 = bits(_WIRE_283, 5, 5)
connect _WIRE_282.ppp, _T_3873
node _T_3874 = bits(_WIRE_283, 6, 6)
connect _WIRE_282.pr, _T_3874
node _T_3875 = bits(_WIRE_283, 7, 7)
connect _WIRE_282.px, _T_3875
node _T_3876 = bits(_WIRE_283, 8, 8)
connect _WIRE_282.pw, _T_3876
node _T_3877 = bits(_WIRE_283, 9, 9)
connect _WIRE_282.hr, _T_3877
node _T_3878 = bits(_WIRE_283, 10, 10)
connect _WIRE_282.hx, _T_3878
node _T_3879 = bits(_WIRE_283, 11, 11)
connect _WIRE_282.hw, _T_3879
node _T_3880 = bits(_WIRE_283, 12, 12)
connect _WIRE_282.sr, _T_3880
node _T_3881 = bits(_WIRE_283, 13, 13)
connect _WIRE_282.sx, _T_3881
node _T_3882 = bits(_WIRE_283, 14, 14)
connect _WIRE_282.sw, _T_3882
node _T_3883 = bits(_WIRE_283, 15, 15)
connect _WIRE_282.gf, _T_3883
node _T_3884 = bits(_WIRE_283, 16, 16)
connect _WIRE_282.pf, _T_3884
node _T_3885 = bits(_WIRE_283, 17, 17)
connect _WIRE_282.ae_stage2, _T_3885
node _T_3886 = bits(_WIRE_283, 18, 18)
connect _WIRE_282.ae_final, _T_3886
node _T_3887 = bits(_WIRE_283, 19, 19)
connect _WIRE_282.ae_ptw, _T_3887
node _T_3888 = bits(_WIRE_283, 20, 20)
connect _WIRE_282.g, _T_3888
node _T_3889 = bits(_WIRE_283, 21, 21)
connect _WIRE_282.u, _T_3889
node _T_3890 = bits(_WIRE_283, 41, 22)
connect _WIRE_282.ppn, _T_3890
node _T_3891 = eq(special_entry.tag_v, hv_12)
node _T_3892 = eq(_WIRE_282.g, UInt<1>(0h0))
node _T_3893 = and(_T_3891, _T_3892)
when _T_3893 :
connect special_entry.valid[0], UInt<1>(0h0)
else :
node _T_3894 = or(hv_12, hg_12)
wire _WIRE_284 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_285 : UInt<42>
connect _WIRE_285, special_entry.data[0]
node _T_3895 = bits(_WIRE_285, 0, 0)
connect _WIRE_284.fragmented_superpage, _T_3895
node _T_3896 = bits(_WIRE_285, 1, 1)
connect _WIRE_284.c, _T_3896
node _T_3897 = bits(_WIRE_285, 2, 2)
connect _WIRE_284.eff, _T_3897
node _T_3898 = bits(_WIRE_285, 3, 3)
connect _WIRE_284.paa, _T_3898
node _T_3899 = bits(_WIRE_285, 4, 4)
connect _WIRE_284.pal, _T_3899
node _T_3900 = bits(_WIRE_285, 5, 5)
connect _WIRE_284.ppp, _T_3900
node _T_3901 = bits(_WIRE_285, 6, 6)
connect _WIRE_284.pr, _T_3901
node _T_3902 = bits(_WIRE_285, 7, 7)
connect _WIRE_284.px, _T_3902
node _T_3903 = bits(_WIRE_285, 8, 8)
connect _WIRE_284.pw, _T_3903
node _T_3904 = bits(_WIRE_285, 9, 9)
connect _WIRE_284.hr, _T_3904
node _T_3905 = bits(_WIRE_285, 10, 10)
connect _WIRE_284.hx, _T_3905
node _T_3906 = bits(_WIRE_285, 11, 11)
connect _WIRE_284.hw, _T_3906
node _T_3907 = bits(_WIRE_285, 12, 12)
connect _WIRE_284.sr, _T_3907
node _T_3908 = bits(_WIRE_285, 13, 13)
connect _WIRE_284.sx, _T_3908
node _T_3909 = bits(_WIRE_285, 14, 14)
connect _WIRE_284.sw, _T_3909
node _T_3910 = bits(_WIRE_285, 15, 15)
connect _WIRE_284.gf, _T_3910
node _T_3911 = bits(_WIRE_285, 16, 16)
connect _WIRE_284.pf, _T_3911
node _T_3912 = bits(_WIRE_285, 17, 17)
connect _WIRE_284.ae_stage2, _T_3912
node _T_3913 = bits(_WIRE_285, 18, 18)
connect _WIRE_284.ae_final, _T_3913
node _T_3914 = bits(_WIRE_285, 19, 19)
connect _WIRE_284.ae_ptw, _T_3914
node _T_3915 = bits(_WIRE_285, 20, 20)
connect _WIRE_284.g, _T_3915
node _T_3916 = bits(_WIRE_285, 21, 21)
connect _WIRE_284.u, _T_3916
node _T_3917 = bits(_WIRE_285, 41, 22)
connect _WIRE_284.ppn, _T_3917
node _T_3918 = eq(special_entry.tag_v, _T_3894)
when _T_3918 :
connect special_entry.valid[0], UInt<1>(0h0)
node _T_3919 = and(io.req.ready, io.req.valid)
node _T_3920 = and(_T_3919, vsatp_mode_mismatch)
when _T_3920 :
wire _WIRE_286 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_287 : UInt<42>
connect _WIRE_287, sectored_entries[0][0].data[0]
node _T_3921 = bits(_WIRE_287, 0, 0)
connect _WIRE_286.fragmented_superpage, _T_3921
node _T_3922 = bits(_WIRE_287, 1, 1)
connect _WIRE_286.c, _T_3922
node _T_3923 = bits(_WIRE_287, 2, 2)
connect _WIRE_286.eff, _T_3923
node _T_3924 = bits(_WIRE_287, 3, 3)
connect _WIRE_286.paa, _T_3924
node _T_3925 = bits(_WIRE_287, 4, 4)
connect _WIRE_286.pal, _T_3925
node _T_3926 = bits(_WIRE_287, 5, 5)
connect _WIRE_286.ppp, _T_3926
node _T_3927 = bits(_WIRE_287, 6, 6)
connect _WIRE_286.pr, _T_3927
node _T_3928 = bits(_WIRE_287, 7, 7)
connect _WIRE_286.px, _T_3928
node _T_3929 = bits(_WIRE_287, 8, 8)
connect _WIRE_286.pw, _T_3929
node _T_3930 = bits(_WIRE_287, 9, 9)
connect _WIRE_286.hr, _T_3930
node _T_3931 = bits(_WIRE_287, 10, 10)
connect _WIRE_286.hx, _T_3931
node _T_3932 = bits(_WIRE_287, 11, 11)
connect _WIRE_286.hw, _T_3932
node _T_3933 = bits(_WIRE_287, 12, 12)
connect _WIRE_286.sr, _T_3933
node _T_3934 = bits(_WIRE_287, 13, 13)
connect _WIRE_286.sx, _T_3934
node _T_3935 = bits(_WIRE_287, 14, 14)
connect _WIRE_286.sw, _T_3935
node _T_3936 = bits(_WIRE_287, 15, 15)
connect _WIRE_286.gf, _T_3936
node _T_3937 = bits(_WIRE_287, 16, 16)
connect _WIRE_286.pf, _T_3937
node _T_3938 = bits(_WIRE_287, 17, 17)
connect _WIRE_286.ae_stage2, _T_3938
node _T_3939 = bits(_WIRE_287, 18, 18)
connect _WIRE_286.ae_final, _T_3939
node _T_3940 = bits(_WIRE_287, 19, 19)
connect _WIRE_286.ae_ptw, _T_3940
node _T_3941 = bits(_WIRE_287, 20, 20)
connect _WIRE_286.g, _T_3941
node _T_3942 = bits(_WIRE_287, 21, 21)
connect _WIRE_286.u, _T_3942
node _T_3943 = bits(_WIRE_287, 41, 22)
connect _WIRE_286.ppn, _T_3943
wire _WIRE_288 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_289 : UInt<42>
connect _WIRE_289, sectored_entries[0][0].data[1]
node _T_3944 = bits(_WIRE_289, 0, 0)
connect _WIRE_288.fragmented_superpage, _T_3944
node _T_3945 = bits(_WIRE_289, 1, 1)
connect _WIRE_288.c, _T_3945
node _T_3946 = bits(_WIRE_289, 2, 2)
connect _WIRE_288.eff, _T_3946
node _T_3947 = bits(_WIRE_289, 3, 3)
connect _WIRE_288.paa, _T_3947
node _T_3948 = bits(_WIRE_289, 4, 4)
connect _WIRE_288.pal, _T_3948
node _T_3949 = bits(_WIRE_289, 5, 5)
connect _WIRE_288.ppp, _T_3949
node _T_3950 = bits(_WIRE_289, 6, 6)
connect _WIRE_288.pr, _T_3950
node _T_3951 = bits(_WIRE_289, 7, 7)
connect _WIRE_288.px, _T_3951
node _T_3952 = bits(_WIRE_289, 8, 8)
connect _WIRE_288.pw, _T_3952
node _T_3953 = bits(_WIRE_289, 9, 9)
connect _WIRE_288.hr, _T_3953
node _T_3954 = bits(_WIRE_289, 10, 10)
connect _WIRE_288.hx, _T_3954
node _T_3955 = bits(_WIRE_289, 11, 11)
connect _WIRE_288.hw, _T_3955
node _T_3956 = bits(_WIRE_289, 12, 12)
connect _WIRE_288.sr, _T_3956
node _T_3957 = bits(_WIRE_289, 13, 13)
connect _WIRE_288.sx, _T_3957
node _T_3958 = bits(_WIRE_289, 14, 14)
connect _WIRE_288.sw, _T_3958
node _T_3959 = bits(_WIRE_289, 15, 15)
connect _WIRE_288.gf, _T_3959
node _T_3960 = bits(_WIRE_289, 16, 16)
connect _WIRE_288.pf, _T_3960
node _T_3961 = bits(_WIRE_289, 17, 17)
connect _WIRE_288.ae_stage2, _T_3961
node _T_3962 = bits(_WIRE_289, 18, 18)
connect _WIRE_288.ae_final, _T_3962
node _T_3963 = bits(_WIRE_289, 19, 19)
connect _WIRE_288.ae_ptw, _T_3963
node _T_3964 = bits(_WIRE_289, 20, 20)
connect _WIRE_288.g, _T_3964
node _T_3965 = bits(_WIRE_289, 21, 21)
connect _WIRE_288.u, _T_3965
node _T_3966 = bits(_WIRE_289, 41, 22)
connect _WIRE_288.ppn, _T_3966
wire _WIRE_290 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_291 : UInt<42>
connect _WIRE_291, sectored_entries[0][0].data[2]
node _T_3967 = bits(_WIRE_291, 0, 0)
connect _WIRE_290.fragmented_superpage, _T_3967
node _T_3968 = bits(_WIRE_291, 1, 1)
connect _WIRE_290.c, _T_3968
node _T_3969 = bits(_WIRE_291, 2, 2)
connect _WIRE_290.eff, _T_3969
node _T_3970 = bits(_WIRE_291, 3, 3)
connect _WIRE_290.paa, _T_3970
node _T_3971 = bits(_WIRE_291, 4, 4)
connect _WIRE_290.pal, _T_3971
node _T_3972 = bits(_WIRE_291, 5, 5)
connect _WIRE_290.ppp, _T_3972
node _T_3973 = bits(_WIRE_291, 6, 6)
connect _WIRE_290.pr, _T_3973
node _T_3974 = bits(_WIRE_291, 7, 7)
connect _WIRE_290.px, _T_3974
node _T_3975 = bits(_WIRE_291, 8, 8)
connect _WIRE_290.pw, _T_3975
node _T_3976 = bits(_WIRE_291, 9, 9)
connect _WIRE_290.hr, _T_3976
node _T_3977 = bits(_WIRE_291, 10, 10)
connect _WIRE_290.hx, _T_3977
node _T_3978 = bits(_WIRE_291, 11, 11)
connect _WIRE_290.hw, _T_3978
node _T_3979 = bits(_WIRE_291, 12, 12)
connect _WIRE_290.sr, _T_3979
node _T_3980 = bits(_WIRE_291, 13, 13)
connect _WIRE_290.sx, _T_3980
node _T_3981 = bits(_WIRE_291, 14, 14)
connect _WIRE_290.sw, _T_3981
node _T_3982 = bits(_WIRE_291, 15, 15)
connect _WIRE_290.gf, _T_3982
node _T_3983 = bits(_WIRE_291, 16, 16)
connect _WIRE_290.pf, _T_3983
node _T_3984 = bits(_WIRE_291, 17, 17)
connect _WIRE_290.ae_stage2, _T_3984
node _T_3985 = bits(_WIRE_291, 18, 18)
connect _WIRE_290.ae_final, _T_3985
node _T_3986 = bits(_WIRE_291, 19, 19)
connect _WIRE_290.ae_ptw, _T_3986
node _T_3987 = bits(_WIRE_291, 20, 20)
connect _WIRE_290.g, _T_3987
node _T_3988 = bits(_WIRE_291, 21, 21)
connect _WIRE_290.u, _T_3988
node _T_3989 = bits(_WIRE_291, 41, 22)
connect _WIRE_290.ppn, _T_3989
wire _WIRE_292 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_293 : UInt<42>
connect _WIRE_293, sectored_entries[0][0].data[3]
node _T_3990 = bits(_WIRE_293, 0, 0)
connect _WIRE_292.fragmented_superpage, _T_3990
node _T_3991 = bits(_WIRE_293, 1, 1)
connect _WIRE_292.c, _T_3991
node _T_3992 = bits(_WIRE_293, 2, 2)
connect _WIRE_292.eff, _T_3992
node _T_3993 = bits(_WIRE_293, 3, 3)
connect _WIRE_292.paa, _T_3993
node _T_3994 = bits(_WIRE_293, 4, 4)
connect _WIRE_292.pal, _T_3994
node _T_3995 = bits(_WIRE_293, 5, 5)
connect _WIRE_292.ppp, _T_3995
node _T_3996 = bits(_WIRE_293, 6, 6)
connect _WIRE_292.pr, _T_3996
node _T_3997 = bits(_WIRE_293, 7, 7)
connect _WIRE_292.px, _T_3997
node _T_3998 = bits(_WIRE_293, 8, 8)
connect _WIRE_292.pw, _T_3998
node _T_3999 = bits(_WIRE_293, 9, 9)
connect _WIRE_292.hr, _T_3999
node _T_4000 = bits(_WIRE_293, 10, 10)
connect _WIRE_292.hx, _T_4000
node _T_4001 = bits(_WIRE_293, 11, 11)
connect _WIRE_292.hw, _T_4001
node _T_4002 = bits(_WIRE_293, 12, 12)
connect _WIRE_292.sr, _T_4002
node _T_4003 = bits(_WIRE_293, 13, 13)
connect _WIRE_292.sx, _T_4003
node _T_4004 = bits(_WIRE_293, 14, 14)
connect _WIRE_292.sw, _T_4004
node _T_4005 = bits(_WIRE_293, 15, 15)
connect _WIRE_292.gf, _T_4005
node _T_4006 = bits(_WIRE_293, 16, 16)
connect _WIRE_292.pf, _T_4006
node _T_4007 = bits(_WIRE_293, 17, 17)
connect _WIRE_292.ae_stage2, _T_4007
node _T_4008 = bits(_WIRE_293, 18, 18)
connect _WIRE_292.ae_final, _T_4008
node _T_4009 = bits(_WIRE_293, 19, 19)
connect _WIRE_292.ae_ptw, _T_4009
node _T_4010 = bits(_WIRE_293, 20, 20)
connect _WIRE_292.g, _T_4010
node _T_4011 = bits(_WIRE_293, 21, 21)
connect _WIRE_292.u, _T_4011
node _T_4012 = bits(_WIRE_293, 41, 22)
connect _WIRE_292.ppn, _T_4012
node _T_4013 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1))
when _T_4013 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
node _T_4014 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1))
when _T_4014 :
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
node _T_4015 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1))
when _T_4015 :
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
node _T_4016 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1))
when _T_4016 :
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
wire _WIRE_294 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_295 : UInt<42>
connect _WIRE_295, sectored_entries[0][1].data[0]
node _T_4017 = bits(_WIRE_295, 0, 0)
connect _WIRE_294.fragmented_superpage, _T_4017
node _T_4018 = bits(_WIRE_295, 1, 1)
connect _WIRE_294.c, _T_4018
node _T_4019 = bits(_WIRE_295, 2, 2)
connect _WIRE_294.eff, _T_4019
node _T_4020 = bits(_WIRE_295, 3, 3)
connect _WIRE_294.paa, _T_4020
node _T_4021 = bits(_WIRE_295, 4, 4)
connect _WIRE_294.pal, _T_4021
node _T_4022 = bits(_WIRE_295, 5, 5)
connect _WIRE_294.ppp, _T_4022
node _T_4023 = bits(_WIRE_295, 6, 6)
connect _WIRE_294.pr, _T_4023
node _T_4024 = bits(_WIRE_295, 7, 7)
connect _WIRE_294.px, _T_4024
node _T_4025 = bits(_WIRE_295, 8, 8)
connect _WIRE_294.pw, _T_4025
node _T_4026 = bits(_WIRE_295, 9, 9)
connect _WIRE_294.hr, _T_4026
node _T_4027 = bits(_WIRE_295, 10, 10)
connect _WIRE_294.hx, _T_4027
node _T_4028 = bits(_WIRE_295, 11, 11)
connect _WIRE_294.hw, _T_4028
node _T_4029 = bits(_WIRE_295, 12, 12)
connect _WIRE_294.sr, _T_4029
node _T_4030 = bits(_WIRE_295, 13, 13)
connect _WIRE_294.sx, _T_4030
node _T_4031 = bits(_WIRE_295, 14, 14)
connect _WIRE_294.sw, _T_4031
node _T_4032 = bits(_WIRE_295, 15, 15)
connect _WIRE_294.gf, _T_4032
node _T_4033 = bits(_WIRE_295, 16, 16)
connect _WIRE_294.pf, _T_4033
node _T_4034 = bits(_WIRE_295, 17, 17)
connect _WIRE_294.ae_stage2, _T_4034
node _T_4035 = bits(_WIRE_295, 18, 18)
connect _WIRE_294.ae_final, _T_4035
node _T_4036 = bits(_WIRE_295, 19, 19)
connect _WIRE_294.ae_ptw, _T_4036
node _T_4037 = bits(_WIRE_295, 20, 20)
connect _WIRE_294.g, _T_4037
node _T_4038 = bits(_WIRE_295, 21, 21)
connect _WIRE_294.u, _T_4038
node _T_4039 = bits(_WIRE_295, 41, 22)
connect _WIRE_294.ppn, _T_4039
wire _WIRE_296 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_297 : UInt<42>
connect _WIRE_297, sectored_entries[0][1].data[1]
node _T_4040 = bits(_WIRE_297, 0, 0)
connect _WIRE_296.fragmented_superpage, _T_4040
node _T_4041 = bits(_WIRE_297, 1, 1)
connect _WIRE_296.c, _T_4041
node _T_4042 = bits(_WIRE_297, 2, 2)
connect _WIRE_296.eff, _T_4042
node _T_4043 = bits(_WIRE_297, 3, 3)
connect _WIRE_296.paa, _T_4043
node _T_4044 = bits(_WIRE_297, 4, 4)
connect _WIRE_296.pal, _T_4044
node _T_4045 = bits(_WIRE_297, 5, 5)
connect _WIRE_296.ppp, _T_4045
node _T_4046 = bits(_WIRE_297, 6, 6)
connect _WIRE_296.pr, _T_4046
node _T_4047 = bits(_WIRE_297, 7, 7)
connect _WIRE_296.px, _T_4047
node _T_4048 = bits(_WIRE_297, 8, 8)
connect _WIRE_296.pw, _T_4048
node _T_4049 = bits(_WIRE_297, 9, 9)
connect _WIRE_296.hr, _T_4049
node _T_4050 = bits(_WIRE_297, 10, 10)
connect _WIRE_296.hx, _T_4050
node _T_4051 = bits(_WIRE_297, 11, 11)
connect _WIRE_296.hw, _T_4051
node _T_4052 = bits(_WIRE_297, 12, 12)
connect _WIRE_296.sr, _T_4052
node _T_4053 = bits(_WIRE_297, 13, 13)
connect _WIRE_296.sx, _T_4053
node _T_4054 = bits(_WIRE_297, 14, 14)
connect _WIRE_296.sw, _T_4054
node _T_4055 = bits(_WIRE_297, 15, 15)
connect _WIRE_296.gf, _T_4055
node _T_4056 = bits(_WIRE_297, 16, 16)
connect _WIRE_296.pf, _T_4056
node _T_4057 = bits(_WIRE_297, 17, 17)
connect _WIRE_296.ae_stage2, _T_4057
node _T_4058 = bits(_WIRE_297, 18, 18)
connect _WIRE_296.ae_final, _T_4058
node _T_4059 = bits(_WIRE_297, 19, 19)
connect _WIRE_296.ae_ptw, _T_4059
node _T_4060 = bits(_WIRE_297, 20, 20)
connect _WIRE_296.g, _T_4060
node _T_4061 = bits(_WIRE_297, 21, 21)
connect _WIRE_296.u, _T_4061
node _T_4062 = bits(_WIRE_297, 41, 22)
connect _WIRE_296.ppn, _T_4062
wire _WIRE_298 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_299 : UInt<42>
connect _WIRE_299, sectored_entries[0][1].data[2]
node _T_4063 = bits(_WIRE_299, 0, 0)
connect _WIRE_298.fragmented_superpage, _T_4063
node _T_4064 = bits(_WIRE_299, 1, 1)
connect _WIRE_298.c, _T_4064
node _T_4065 = bits(_WIRE_299, 2, 2)
connect _WIRE_298.eff, _T_4065
node _T_4066 = bits(_WIRE_299, 3, 3)
connect _WIRE_298.paa, _T_4066
node _T_4067 = bits(_WIRE_299, 4, 4)
connect _WIRE_298.pal, _T_4067
node _T_4068 = bits(_WIRE_299, 5, 5)
connect _WIRE_298.ppp, _T_4068
node _T_4069 = bits(_WIRE_299, 6, 6)
connect _WIRE_298.pr, _T_4069
node _T_4070 = bits(_WIRE_299, 7, 7)
connect _WIRE_298.px, _T_4070
node _T_4071 = bits(_WIRE_299, 8, 8)
connect _WIRE_298.pw, _T_4071
node _T_4072 = bits(_WIRE_299, 9, 9)
connect _WIRE_298.hr, _T_4072
node _T_4073 = bits(_WIRE_299, 10, 10)
connect _WIRE_298.hx, _T_4073
node _T_4074 = bits(_WIRE_299, 11, 11)
connect _WIRE_298.hw, _T_4074
node _T_4075 = bits(_WIRE_299, 12, 12)
connect _WIRE_298.sr, _T_4075
node _T_4076 = bits(_WIRE_299, 13, 13)
connect _WIRE_298.sx, _T_4076
node _T_4077 = bits(_WIRE_299, 14, 14)
connect _WIRE_298.sw, _T_4077
node _T_4078 = bits(_WIRE_299, 15, 15)
connect _WIRE_298.gf, _T_4078
node _T_4079 = bits(_WIRE_299, 16, 16)
connect _WIRE_298.pf, _T_4079
node _T_4080 = bits(_WIRE_299, 17, 17)
connect _WIRE_298.ae_stage2, _T_4080
node _T_4081 = bits(_WIRE_299, 18, 18)
connect _WIRE_298.ae_final, _T_4081
node _T_4082 = bits(_WIRE_299, 19, 19)
connect _WIRE_298.ae_ptw, _T_4082
node _T_4083 = bits(_WIRE_299, 20, 20)
connect _WIRE_298.g, _T_4083
node _T_4084 = bits(_WIRE_299, 21, 21)
connect _WIRE_298.u, _T_4084
node _T_4085 = bits(_WIRE_299, 41, 22)
connect _WIRE_298.ppn, _T_4085
wire _WIRE_300 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_301 : UInt<42>
connect _WIRE_301, sectored_entries[0][1].data[3]
node _T_4086 = bits(_WIRE_301, 0, 0)
connect _WIRE_300.fragmented_superpage, _T_4086
node _T_4087 = bits(_WIRE_301, 1, 1)
connect _WIRE_300.c, _T_4087
node _T_4088 = bits(_WIRE_301, 2, 2)
connect _WIRE_300.eff, _T_4088
node _T_4089 = bits(_WIRE_301, 3, 3)
connect _WIRE_300.paa, _T_4089
node _T_4090 = bits(_WIRE_301, 4, 4)
connect _WIRE_300.pal, _T_4090
node _T_4091 = bits(_WIRE_301, 5, 5)
connect _WIRE_300.ppp, _T_4091
node _T_4092 = bits(_WIRE_301, 6, 6)
connect _WIRE_300.pr, _T_4092
node _T_4093 = bits(_WIRE_301, 7, 7)
connect _WIRE_300.px, _T_4093
node _T_4094 = bits(_WIRE_301, 8, 8)
connect _WIRE_300.pw, _T_4094
node _T_4095 = bits(_WIRE_301, 9, 9)
connect _WIRE_300.hr, _T_4095
node _T_4096 = bits(_WIRE_301, 10, 10)
connect _WIRE_300.hx, _T_4096
node _T_4097 = bits(_WIRE_301, 11, 11)
connect _WIRE_300.hw, _T_4097
node _T_4098 = bits(_WIRE_301, 12, 12)
connect _WIRE_300.sr, _T_4098
node _T_4099 = bits(_WIRE_301, 13, 13)
connect _WIRE_300.sx, _T_4099
node _T_4100 = bits(_WIRE_301, 14, 14)
connect _WIRE_300.sw, _T_4100
node _T_4101 = bits(_WIRE_301, 15, 15)
connect _WIRE_300.gf, _T_4101
node _T_4102 = bits(_WIRE_301, 16, 16)
connect _WIRE_300.pf, _T_4102
node _T_4103 = bits(_WIRE_301, 17, 17)
connect _WIRE_300.ae_stage2, _T_4103
node _T_4104 = bits(_WIRE_301, 18, 18)
connect _WIRE_300.ae_final, _T_4104
node _T_4105 = bits(_WIRE_301, 19, 19)
connect _WIRE_300.ae_ptw, _T_4105
node _T_4106 = bits(_WIRE_301, 20, 20)
connect _WIRE_300.g, _T_4106
node _T_4107 = bits(_WIRE_301, 21, 21)
connect _WIRE_300.u, _T_4107
node _T_4108 = bits(_WIRE_301, 41, 22)
connect _WIRE_300.ppn, _T_4108
node _T_4109 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1))
when _T_4109 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
node _T_4110 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1))
when _T_4110 :
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
node _T_4111 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1))
when _T_4111 :
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
node _T_4112 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1))
when _T_4112 :
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
wire _WIRE_302 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_303 : UInt<42>
connect _WIRE_303, sectored_entries[0][2].data[0]
node _T_4113 = bits(_WIRE_303, 0, 0)
connect _WIRE_302.fragmented_superpage, _T_4113
node _T_4114 = bits(_WIRE_303, 1, 1)
connect _WIRE_302.c, _T_4114
node _T_4115 = bits(_WIRE_303, 2, 2)
connect _WIRE_302.eff, _T_4115
node _T_4116 = bits(_WIRE_303, 3, 3)
connect _WIRE_302.paa, _T_4116
node _T_4117 = bits(_WIRE_303, 4, 4)
connect _WIRE_302.pal, _T_4117
node _T_4118 = bits(_WIRE_303, 5, 5)
connect _WIRE_302.ppp, _T_4118
node _T_4119 = bits(_WIRE_303, 6, 6)
connect _WIRE_302.pr, _T_4119
node _T_4120 = bits(_WIRE_303, 7, 7)
connect _WIRE_302.px, _T_4120
node _T_4121 = bits(_WIRE_303, 8, 8)
connect _WIRE_302.pw, _T_4121
node _T_4122 = bits(_WIRE_303, 9, 9)
connect _WIRE_302.hr, _T_4122
node _T_4123 = bits(_WIRE_303, 10, 10)
connect _WIRE_302.hx, _T_4123
node _T_4124 = bits(_WIRE_303, 11, 11)
connect _WIRE_302.hw, _T_4124
node _T_4125 = bits(_WIRE_303, 12, 12)
connect _WIRE_302.sr, _T_4125
node _T_4126 = bits(_WIRE_303, 13, 13)
connect _WIRE_302.sx, _T_4126
node _T_4127 = bits(_WIRE_303, 14, 14)
connect _WIRE_302.sw, _T_4127
node _T_4128 = bits(_WIRE_303, 15, 15)
connect _WIRE_302.gf, _T_4128
node _T_4129 = bits(_WIRE_303, 16, 16)
connect _WIRE_302.pf, _T_4129
node _T_4130 = bits(_WIRE_303, 17, 17)
connect _WIRE_302.ae_stage2, _T_4130
node _T_4131 = bits(_WIRE_303, 18, 18)
connect _WIRE_302.ae_final, _T_4131
node _T_4132 = bits(_WIRE_303, 19, 19)
connect _WIRE_302.ae_ptw, _T_4132
node _T_4133 = bits(_WIRE_303, 20, 20)
connect _WIRE_302.g, _T_4133
node _T_4134 = bits(_WIRE_303, 21, 21)
connect _WIRE_302.u, _T_4134
node _T_4135 = bits(_WIRE_303, 41, 22)
connect _WIRE_302.ppn, _T_4135
wire _WIRE_304 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_305 : UInt<42>
connect _WIRE_305, sectored_entries[0][2].data[1]
node _T_4136 = bits(_WIRE_305, 0, 0)
connect _WIRE_304.fragmented_superpage, _T_4136
node _T_4137 = bits(_WIRE_305, 1, 1)
connect _WIRE_304.c, _T_4137
node _T_4138 = bits(_WIRE_305, 2, 2)
connect _WIRE_304.eff, _T_4138
node _T_4139 = bits(_WIRE_305, 3, 3)
connect _WIRE_304.paa, _T_4139
node _T_4140 = bits(_WIRE_305, 4, 4)
connect _WIRE_304.pal, _T_4140
node _T_4141 = bits(_WIRE_305, 5, 5)
connect _WIRE_304.ppp, _T_4141
node _T_4142 = bits(_WIRE_305, 6, 6)
connect _WIRE_304.pr, _T_4142
node _T_4143 = bits(_WIRE_305, 7, 7)
connect _WIRE_304.px, _T_4143
node _T_4144 = bits(_WIRE_305, 8, 8)
connect _WIRE_304.pw, _T_4144
node _T_4145 = bits(_WIRE_305, 9, 9)
connect _WIRE_304.hr, _T_4145
node _T_4146 = bits(_WIRE_305, 10, 10)
connect _WIRE_304.hx, _T_4146
node _T_4147 = bits(_WIRE_305, 11, 11)
connect _WIRE_304.hw, _T_4147
node _T_4148 = bits(_WIRE_305, 12, 12)
connect _WIRE_304.sr, _T_4148
node _T_4149 = bits(_WIRE_305, 13, 13)
connect _WIRE_304.sx, _T_4149
node _T_4150 = bits(_WIRE_305, 14, 14)
connect _WIRE_304.sw, _T_4150
node _T_4151 = bits(_WIRE_305, 15, 15)
connect _WIRE_304.gf, _T_4151
node _T_4152 = bits(_WIRE_305, 16, 16)
connect _WIRE_304.pf, _T_4152
node _T_4153 = bits(_WIRE_305, 17, 17)
connect _WIRE_304.ae_stage2, _T_4153
node _T_4154 = bits(_WIRE_305, 18, 18)
connect _WIRE_304.ae_final, _T_4154
node _T_4155 = bits(_WIRE_305, 19, 19)
connect _WIRE_304.ae_ptw, _T_4155
node _T_4156 = bits(_WIRE_305, 20, 20)
connect _WIRE_304.g, _T_4156
node _T_4157 = bits(_WIRE_305, 21, 21)
connect _WIRE_304.u, _T_4157
node _T_4158 = bits(_WIRE_305, 41, 22)
connect _WIRE_304.ppn, _T_4158
wire _WIRE_306 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_307 : UInt<42>
connect _WIRE_307, sectored_entries[0][2].data[2]
node _T_4159 = bits(_WIRE_307, 0, 0)
connect _WIRE_306.fragmented_superpage, _T_4159
node _T_4160 = bits(_WIRE_307, 1, 1)
connect _WIRE_306.c, _T_4160
node _T_4161 = bits(_WIRE_307, 2, 2)
connect _WIRE_306.eff, _T_4161
node _T_4162 = bits(_WIRE_307, 3, 3)
connect _WIRE_306.paa, _T_4162
node _T_4163 = bits(_WIRE_307, 4, 4)
connect _WIRE_306.pal, _T_4163
node _T_4164 = bits(_WIRE_307, 5, 5)
connect _WIRE_306.ppp, _T_4164
node _T_4165 = bits(_WIRE_307, 6, 6)
connect _WIRE_306.pr, _T_4165
node _T_4166 = bits(_WIRE_307, 7, 7)
connect _WIRE_306.px, _T_4166
node _T_4167 = bits(_WIRE_307, 8, 8)
connect _WIRE_306.pw, _T_4167
node _T_4168 = bits(_WIRE_307, 9, 9)
connect _WIRE_306.hr, _T_4168
node _T_4169 = bits(_WIRE_307, 10, 10)
connect _WIRE_306.hx, _T_4169
node _T_4170 = bits(_WIRE_307, 11, 11)
connect _WIRE_306.hw, _T_4170
node _T_4171 = bits(_WIRE_307, 12, 12)
connect _WIRE_306.sr, _T_4171
node _T_4172 = bits(_WIRE_307, 13, 13)
connect _WIRE_306.sx, _T_4172
node _T_4173 = bits(_WIRE_307, 14, 14)
connect _WIRE_306.sw, _T_4173
node _T_4174 = bits(_WIRE_307, 15, 15)
connect _WIRE_306.gf, _T_4174
node _T_4175 = bits(_WIRE_307, 16, 16)
connect _WIRE_306.pf, _T_4175
node _T_4176 = bits(_WIRE_307, 17, 17)
connect _WIRE_306.ae_stage2, _T_4176
node _T_4177 = bits(_WIRE_307, 18, 18)
connect _WIRE_306.ae_final, _T_4177
node _T_4178 = bits(_WIRE_307, 19, 19)
connect _WIRE_306.ae_ptw, _T_4178
node _T_4179 = bits(_WIRE_307, 20, 20)
connect _WIRE_306.g, _T_4179
node _T_4180 = bits(_WIRE_307, 21, 21)
connect _WIRE_306.u, _T_4180
node _T_4181 = bits(_WIRE_307, 41, 22)
connect _WIRE_306.ppn, _T_4181
wire _WIRE_308 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_309 : UInt<42>
connect _WIRE_309, sectored_entries[0][2].data[3]
node _T_4182 = bits(_WIRE_309, 0, 0)
connect _WIRE_308.fragmented_superpage, _T_4182
node _T_4183 = bits(_WIRE_309, 1, 1)
connect _WIRE_308.c, _T_4183
node _T_4184 = bits(_WIRE_309, 2, 2)
connect _WIRE_308.eff, _T_4184
node _T_4185 = bits(_WIRE_309, 3, 3)
connect _WIRE_308.paa, _T_4185
node _T_4186 = bits(_WIRE_309, 4, 4)
connect _WIRE_308.pal, _T_4186
node _T_4187 = bits(_WIRE_309, 5, 5)
connect _WIRE_308.ppp, _T_4187
node _T_4188 = bits(_WIRE_309, 6, 6)
connect _WIRE_308.pr, _T_4188
node _T_4189 = bits(_WIRE_309, 7, 7)
connect _WIRE_308.px, _T_4189
node _T_4190 = bits(_WIRE_309, 8, 8)
connect _WIRE_308.pw, _T_4190
node _T_4191 = bits(_WIRE_309, 9, 9)
connect _WIRE_308.hr, _T_4191
node _T_4192 = bits(_WIRE_309, 10, 10)
connect _WIRE_308.hx, _T_4192
node _T_4193 = bits(_WIRE_309, 11, 11)
connect _WIRE_308.hw, _T_4193
node _T_4194 = bits(_WIRE_309, 12, 12)
connect _WIRE_308.sr, _T_4194
node _T_4195 = bits(_WIRE_309, 13, 13)
connect _WIRE_308.sx, _T_4195
node _T_4196 = bits(_WIRE_309, 14, 14)
connect _WIRE_308.sw, _T_4196
node _T_4197 = bits(_WIRE_309, 15, 15)
connect _WIRE_308.gf, _T_4197
node _T_4198 = bits(_WIRE_309, 16, 16)
connect _WIRE_308.pf, _T_4198
node _T_4199 = bits(_WIRE_309, 17, 17)
connect _WIRE_308.ae_stage2, _T_4199
node _T_4200 = bits(_WIRE_309, 18, 18)
connect _WIRE_308.ae_final, _T_4200
node _T_4201 = bits(_WIRE_309, 19, 19)
connect _WIRE_308.ae_ptw, _T_4201
node _T_4202 = bits(_WIRE_309, 20, 20)
connect _WIRE_308.g, _T_4202
node _T_4203 = bits(_WIRE_309, 21, 21)
connect _WIRE_308.u, _T_4203
node _T_4204 = bits(_WIRE_309, 41, 22)
connect _WIRE_308.ppn, _T_4204
node _T_4205 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1))
when _T_4205 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
node _T_4206 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1))
when _T_4206 :
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
node _T_4207 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1))
when _T_4207 :
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
node _T_4208 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1))
when _T_4208 :
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
wire _WIRE_310 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_311 : UInt<42>
connect _WIRE_311, sectored_entries[0][3].data[0]
node _T_4209 = bits(_WIRE_311, 0, 0)
connect _WIRE_310.fragmented_superpage, _T_4209
node _T_4210 = bits(_WIRE_311, 1, 1)
connect _WIRE_310.c, _T_4210
node _T_4211 = bits(_WIRE_311, 2, 2)
connect _WIRE_310.eff, _T_4211
node _T_4212 = bits(_WIRE_311, 3, 3)
connect _WIRE_310.paa, _T_4212
node _T_4213 = bits(_WIRE_311, 4, 4)
connect _WIRE_310.pal, _T_4213
node _T_4214 = bits(_WIRE_311, 5, 5)
connect _WIRE_310.ppp, _T_4214
node _T_4215 = bits(_WIRE_311, 6, 6)
connect _WIRE_310.pr, _T_4215
node _T_4216 = bits(_WIRE_311, 7, 7)
connect _WIRE_310.px, _T_4216
node _T_4217 = bits(_WIRE_311, 8, 8)
connect _WIRE_310.pw, _T_4217
node _T_4218 = bits(_WIRE_311, 9, 9)
connect _WIRE_310.hr, _T_4218
node _T_4219 = bits(_WIRE_311, 10, 10)
connect _WIRE_310.hx, _T_4219
node _T_4220 = bits(_WIRE_311, 11, 11)
connect _WIRE_310.hw, _T_4220
node _T_4221 = bits(_WIRE_311, 12, 12)
connect _WIRE_310.sr, _T_4221
node _T_4222 = bits(_WIRE_311, 13, 13)
connect _WIRE_310.sx, _T_4222
node _T_4223 = bits(_WIRE_311, 14, 14)
connect _WIRE_310.sw, _T_4223
node _T_4224 = bits(_WIRE_311, 15, 15)
connect _WIRE_310.gf, _T_4224
node _T_4225 = bits(_WIRE_311, 16, 16)
connect _WIRE_310.pf, _T_4225
node _T_4226 = bits(_WIRE_311, 17, 17)
connect _WIRE_310.ae_stage2, _T_4226
node _T_4227 = bits(_WIRE_311, 18, 18)
connect _WIRE_310.ae_final, _T_4227
node _T_4228 = bits(_WIRE_311, 19, 19)
connect _WIRE_310.ae_ptw, _T_4228
node _T_4229 = bits(_WIRE_311, 20, 20)
connect _WIRE_310.g, _T_4229
node _T_4230 = bits(_WIRE_311, 21, 21)
connect _WIRE_310.u, _T_4230
node _T_4231 = bits(_WIRE_311, 41, 22)
connect _WIRE_310.ppn, _T_4231
wire _WIRE_312 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_313 : UInt<42>
connect _WIRE_313, sectored_entries[0][3].data[1]
node _T_4232 = bits(_WIRE_313, 0, 0)
connect _WIRE_312.fragmented_superpage, _T_4232
node _T_4233 = bits(_WIRE_313, 1, 1)
connect _WIRE_312.c, _T_4233
node _T_4234 = bits(_WIRE_313, 2, 2)
connect _WIRE_312.eff, _T_4234
node _T_4235 = bits(_WIRE_313, 3, 3)
connect _WIRE_312.paa, _T_4235
node _T_4236 = bits(_WIRE_313, 4, 4)
connect _WIRE_312.pal, _T_4236
node _T_4237 = bits(_WIRE_313, 5, 5)
connect _WIRE_312.ppp, _T_4237
node _T_4238 = bits(_WIRE_313, 6, 6)
connect _WIRE_312.pr, _T_4238
node _T_4239 = bits(_WIRE_313, 7, 7)
connect _WIRE_312.px, _T_4239
node _T_4240 = bits(_WIRE_313, 8, 8)
connect _WIRE_312.pw, _T_4240
node _T_4241 = bits(_WIRE_313, 9, 9)
connect _WIRE_312.hr, _T_4241
node _T_4242 = bits(_WIRE_313, 10, 10)
connect _WIRE_312.hx, _T_4242
node _T_4243 = bits(_WIRE_313, 11, 11)
connect _WIRE_312.hw, _T_4243
node _T_4244 = bits(_WIRE_313, 12, 12)
connect _WIRE_312.sr, _T_4244
node _T_4245 = bits(_WIRE_313, 13, 13)
connect _WIRE_312.sx, _T_4245
node _T_4246 = bits(_WIRE_313, 14, 14)
connect _WIRE_312.sw, _T_4246
node _T_4247 = bits(_WIRE_313, 15, 15)
connect _WIRE_312.gf, _T_4247
node _T_4248 = bits(_WIRE_313, 16, 16)
connect _WIRE_312.pf, _T_4248
node _T_4249 = bits(_WIRE_313, 17, 17)
connect _WIRE_312.ae_stage2, _T_4249
node _T_4250 = bits(_WIRE_313, 18, 18)
connect _WIRE_312.ae_final, _T_4250
node _T_4251 = bits(_WIRE_313, 19, 19)
connect _WIRE_312.ae_ptw, _T_4251
node _T_4252 = bits(_WIRE_313, 20, 20)
connect _WIRE_312.g, _T_4252
node _T_4253 = bits(_WIRE_313, 21, 21)
connect _WIRE_312.u, _T_4253
node _T_4254 = bits(_WIRE_313, 41, 22)
connect _WIRE_312.ppn, _T_4254
wire _WIRE_314 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_315 : UInt<42>
connect _WIRE_315, sectored_entries[0][3].data[2]
node _T_4255 = bits(_WIRE_315, 0, 0)
connect _WIRE_314.fragmented_superpage, _T_4255
node _T_4256 = bits(_WIRE_315, 1, 1)
connect _WIRE_314.c, _T_4256
node _T_4257 = bits(_WIRE_315, 2, 2)
connect _WIRE_314.eff, _T_4257
node _T_4258 = bits(_WIRE_315, 3, 3)
connect _WIRE_314.paa, _T_4258
node _T_4259 = bits(_WIRE_315, 4, 4)
connect _WIRE_314.pal, _T_4259
node _T_4260 = bits(_WIRE_315, 5, 5)
connect _WIRE_314.ppp, _T_4260
node _T_4261 = bits(_WIRE_315, 6, 6)
connect _WIRE_314.pr, _T_4261
node _T_4262 = bits(_WIRE_315, 7, 7)
connect _WIRE_314.px, _T_4262
node _T_4263 = bits(_WIRE_315, 8, 8)
connect _WIRE_314.pw, _T_4263
node _T_4264 = bits(_WIRE_315, 9, 9)
connect _WIRE_314.hr, _T_4264
node _T_4265 = bits(_WIRE_315, 10, 10)
connect _WIRE_314.hx, _T_4265
node _T_4266 = bits(_WIRE_315, 11, 11)
connect _WIRE_314.hw, _T_4266
node _T_4267 = bits(_WIRE_315, 12, 12)
connect _WIRE_314.sr, _T_4267
node _T_4268 = bits(_WIRE_315, 13, 13)
connect _WIRE_314.sx, _T_4268
node _T_4269 = bits(_WIRE_315, 14, 14)
connect _WIRE_314.sw, _T_4269
node _T_4270 = bits(_WIRE_315, 15, 15)
connect _WIRE_314.gf, _T_4270
node _T_4271 = bits(_WIRE_315, 16, 16)
connect _WIRE_314.pf, _T_4271
node _T_4272 = bits(_WIRE_315, 17, 17)
connect _WIRE_314.ae_stage2, _T_4272
node _T_4273 = bits(_WIRE_315, 18, 18)
connect _WIRE_314.ae_final, _T_4273
node _T_4274 = bits(_WIRE_315, 19, 19)
connect _WIRE_314.ae_ptw, _T_4274
node _T_4275 = bits(_WIRE_315, 20, 20)
connect _WIRE_314.g, _T_4275
node _T_4276 = bits(_WIRE_315, 21, 21)
connect _WIRE_314.u, _T_4276
node _T_4277 = bits(_WIRE_315, 41, 22)
connect _WIRE_314.ppn, _T_4277
wire _WIRE_316 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_317 : UInt<42>
connect _WIRE_317, sectored_entries[0][3].data[3]
node _T_4278 = bits(_WIRE_317, 0, 0)
connect _WIRE_316.fragmented_superpage, _T_4278
node _T_4279 = bits(_WIRE_317, 1, 1)
connect _WIRE_316.c, _T_4279
node _T_4280 = bits(_WIRE_317, 2, 2)
connect _WIRE_316.eff, _T_4280
node _T_4281 = bits(_WIRE_317, 3, 3)
connect _WIRE_316.paa, _T_4281
node _T_4282 = bits(_WIRE_317, 4, 4)
connect _WIRE_316.pal, _T_4282
node _T_4283 = bits(_WIRE_317, 5, 5)
connect _WIRE_316.ppp, _T_4283
node _T_4284 = bits(_WIRE_317, 6, 6)
connect _WIRE_316.pr, _T_4284
node _T_4285 = bits(_WIRE_317, 7, 7)
connect _WIRE_316.px, _T_4285
node _T_4286 = bits(_WIRE_317, 8, 8)
connect _WIRE_316.pw, _T_4286
node _T_4287 = bits(_WIRE_317, 9, 9)
connect _WIRE_316.hr, _T_4287
node _T_4288 = bits(_WIRE_317, 10, 10)
connect _WIRE_316.hx, _T_4288
node _T_4289 = bits(_WIRE_317, 11, 11)
connect _WIRE_316.hw, _T_4289
node _T_4290 = bits(_WIRE_317, 12, 12)
connect _WIRE_316.sr, _T_4290
node _T_4291 = bits(_WIRE_317, 13, 13)
connect _WIRE_316.sx, _T_4291
node _T_4292 = bits(_WIRE_317, 14, 14)
connect _WIRE_316.sw, _T_4292
node _T_4293 = bits(_WIRE_317, 15, 15)
connect _WIRE_316.gf, _T_4293
node _T_4294 = bits(_WIRE_317, 16, 16)
connect _WIRE_316.pf, _T_4294
node _T_4295 = bits(_WIRE_317, 17, 17)
connect _WIRE_316.ae_stage2, _T_4295
node _T_4296 = bits(_WIRE_317, 18, 18)
connect _WIRE_316.ae_final, _T_4296
node _T_4297 = bits(_WIRE_317, 19, 19)
connect _WIRE_316.ae_ptw, _T_4297
node _T_4298 = bits(_WIRE_317, 20, 20)
connect _WIRE_316.g, _T_4298
node _T_4299 = bits(_WIRE_317, 21, 21)
connect _WIRE_316.u, _T_4299
node _T_4300 = bits(_WIRE_317, 41, 22)
connect _WIRE_316.ppn, _T_4300
node _T_4301 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1))
when _T_4301 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
node _T_4302 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1))
when _T_4302 :
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
node _T_4303 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1))
when _T_4303 :
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
node _T_4304 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1))
when _T_4304 :
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
wire _WIRE_318 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_319 : UInt<42>
connect _WIRE_319, sectored_entries[0][4].data[0]
node _T_4305 = bits(_WIRE_319, 0, 0)
connect _WIRE_318.fragmented_superpage, _T_4305
node _T_4306 = bits(_WIRE_319, 1, 1)
connect _WIRE_318.c, _T_4306
node _T_4307 = bits(_WIRE_319, 2, 2)
connect _WIRE_318.eff, _T_4307
node _T_4308 = bits(_WIRE_319, 3, 3)
connect _WIRE_318.paa, _T_4308
node _T_4309 = bits(_WIRE_319, 4, 4)
connect _WIRE_318.pal, _T_4309
node _T_4310 = bits(_WIRE_319, 5, 5)
connect _WIRE_318.ppp, _T_4310
node _T_4311 = bits(_WIRE_319, 6, 6)
connect _WIRE_318.pr, _T_4311
node _T_4312 = bits(_WIRE_319, 7, 7)
connect _WIRE_318.px, _T_4312
node _T_4313 = bits(_WIRE_319, 8, 8)
connect _WIRE_318.pw, _T_4313
node _T_4314 = bits(_WIRE_319, 9, 9)
connect _WIRE_318.hr, _T_4314
node _T_4315 = bits(_WIRE_319, 10, 10)
connect _WIRE_318.hx, _T_4315
node _T_4316 = bits(_WIRE_319, 11, 11)
connect _WIRE_318.hw, _T_4316
node _T_4317 = bits(_WIRE_319, 12, 12)
connect _WIRE_318.sr, _T_4317
node _T_4318 = bits(_WIRE_319, 13, 13)
connect _WIRE_318.sx, _T_4318
node _T_4319 = bits(_WIRE_319, 14, 14)
connect _WIRE_318.sw, _T_4319
node _T_4320 = bits(_WIRE_319, 15, 15)
connect _WIRE_318.gf, _T_4320
node _T_4321 = bits(_WIRE_319, 16, 16)
connect _WIRE_318.pf, _T_4321
node _T_4322 = bits(_WIRE_319, 17, 17)
connect _WIRE_318.ae_stage2, _T_4322
node _T_4323 = bits(_WIRE_319, 18, 18)
connect _WIRE_318.ae_final, _T_4323
node _T_4324 = bits(_WIRE_319, 19, 19)
connect _WIRE_318.ae_ptw, _T_4324
node _T_4325 = bits(_WIRE_319, 20, 20)
connect _WIRE_318.g, _T_4325
node _T_4326 = bits(_WIRE_319, 21, 21)
connect _WIRE_318.u, _T_4326
node _T_4327 = bits(_WIRE_319, 41, 22)
connect _WIRE_318.ppn, _T_4327
wire _WIRE_320 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_321 : UInt<42>
connect _WIRE_321, sectored_entries[0][4].data[1]
node _T_4328 = bits(_WIRE_321, 0, 0)
connect _WIRE_320.fragmented_superpage, _T_4328
node _T_4329 = bits(_WIRE_321, 1, 1)
connect _WIRE_320.c, _T_4329
node _T_4330 = bits(_WIRE_321, 2, 2)
connect _WIRE_320.eff, _T_4330
node _T_4331 = bits(_WIRE_321, 3, 3)
connect _WIRE_320.paa, _T_4331
node _T_4332 = bits(_WIRE_321, 4, 4)
connect _WIRE_320.pal, _T_4332
node _T_4333 = bits(_WIRE_321, 5, 5)
connect _WIRE_320.ppp, _T_4333
node _T_4334 = bits(_WIRE_321, 6, 6)
connect _WIRE_320.pr, _T_4334
node _T_4335 = bits(_WIRE_321, 7, 7)
connect _WIRE_320.px, _T_4335
node _T_4336 = bits(_WIRE_321, 8, 8)
connect _WIRE_320.pw, _T_4336
node _T_4337 = bits(_WIRE_321, 9, 9)
connect _WIRE_320.hr, _T_4337
node _T_4338 = bits(_WIRE_321, 10, 10)
connect _WIRE_320.hx, _T_4338
node _T_4339 = bits(_WIRE_321, 11, 11)
connect _WIRE_320.hw, _T_4339
node _T_4340 = bits(_WIRE_321, 12, 12)
connect _WIRE_320.sr, _T_4340
node _T_4341 = bits(_WIRE_321, 13, 13)
connect _WIRE_320.sx, _T_4341
node _T_4342 = bits(_WIRE_321, 14, 14)
connect _WIRE_320.sw, _T_4342
node _T_4343 = bits(_WIRE_321, 15, 15)
connect _WIRE_320.gf, _T_4343
node _T_4344 = bits(_WIRE_321, 16, 16)
connect _WIRE_320.pf, _T_4344
node _T_4345 = bits(_WIRE_321, 17, 17)
connect _WIRE_320.ae_stage2, _T_4345
node _T_4346 = bits(_WIRE_321, 18, 18)
connect _WIRE_320.ae_final, _T_4346
node _T_4347 = bits(_WIRE_321, 19, 19)
connect _WIRE_320.ae_ptw, _T_4347
node _T_4348 = bits(_WIRE_321, 20, 20)
connect _WIRE_320.g, _T_4348
node _T_4349 = bits(_WIRE_321, 21, 21)
connect _WIRE_320.u, _T_4349
node _T_4350 = bits(_WIRE_321, 41, 22)
connect _WIRE_320.ppn, _T_4350
wire _WIRE_322 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_323 : UInt<42>
connect _WIRE_323, sectored_entries[0][4].data[2]
node _T_4351 = bits(_WIRE_323, 0, 0)
connect _WIRE_322.fragmented_superpage, _T_4351
node _T_4352 = bits(_WIRE_323, 1, 1)
connect _WIRE_322.c, _T_4352
node _T_4353 = bits(_WIRE_323, 2, 2)
connect _WIRE_322.eff, _T_4353
node _T_4354 = bits(_WIRE_323, 3, 3)
connect _WIRE_322.paa, _T_4354
node _T_4355 = bits(_WIRE_323, 4, 4)
connect _WIRE_322.pal, _T_4355
node _T_4356 = bits(_WIRE_323, 5, 5)
connect _WIRE_322.ppp, _T_4356
node _T_4357 = bits(_WIRE_323, 6, 6)
connect _WIRE_322.pr, _T_4357
node _T_4358 = bits(_WIRE_323, 7, 7)
connect _WIRE_322.px, _T_4358
node _T_4359 = bits(_WIRE_323, 8, 8)
connect _WIRE_322.pw, _T_4359
node _T_4360 = bits(_WIRE_323, 9, 9)
connect _WIRE_322.hr, _T_4360
node _T_4361 = bits(_WIRE_323, 10, 10)
connect _WIRE_322.hx, _T_4361
node _T_4362 = bits(_WIRE_323, 11, 11)
connect _WIRE_322.hw, _T_4362
node _T_4363 = bits(_WIRE_323, 12, 12)
connect _WIRE_322.sr, _T_4363
node _T_4364 = bits(_WIRE_323, 13, 13)
connect _WIRE_322.sx, _T_4364
node _T_4365 = bits(_WIRE_323, 14, 14)
connect _WIRE_322.sw, _T_4365
node _T_4366 = bits(_WIRE_323, 15, 15)
connect _WIRE_322.gf, _T_4366
node _T_4367 = bits(_WIRE_323, 16, 16)
connect _WIRE_322.pf, _T_4367
node _T_4368 = bits(_WIRE_323, 17, 17)
connect _WIRE_322.ae_stage2, _T_4368
node _T_4369 = bits(_WIRE_323, 18, 18)
connect _WIRE_322.ae_final, _T_4369
node _T_4370 = bits(_WIRE_323, 19, 19)
connect _WIRE_322.ae_ptw, _T_4370
node _T_4371 = bits(_WIRE_323, 20, 20)
connect _WIRE_322.g, _T_4371
node _T_4372 = bits(_WIRE_323, 21, 21)
connect _WIRE_322.u, _T_4372
node _T_4373 = bits(_WIRE_323, 41, 22)
connect _WIRE_322.ppn, _T_4373
wire _WIRE_324 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_325 : UInt<42>
connect _WIRE_325, sectored_entries[0][4].data[3]
node _T_4374 = bits(_WIRE_325, 0, 0)
connect _WIRE_324.fragmented_superpage, _T_4374
node _T_4375 = bits(_WIRE_325, 1, 1)
connect _WIRE_324.c, _T_4375
node _T_4376 = bits(_WIRE_325, 2, 2)
connect _WIRE_324.eff, _T_4376
node _T_4377 = bits(_WIRE_325, 3, 3)
connect _WIRE_324.paa, _T_4377
node _T_4378 = bits(_WIRE_325, 4, 4)
connect _WIRE_324.pal, _T_4378
node _T_4379 = bits(_WIRE_325, 5, 5)
connect _WIRE_324.ppp, _T_4379
node _T_4380 = bits(_WIRE_325, 6, 6)
connect _WIRE_324.pr, _T_4380
node _T_4381 = bits(_WIRE_325, 7, 7)
connect _WIRE_324.px, _T_4381
node _T_4382 = bits(_WIRE_325, 8, 8)
connect _WIRE_324.pw, _T_4382
node _T_4383 = bits(_WIRE_325, 9, 9)
connect _WIRE_324.hr, _T_4383
node _T_4384 = bits(_WIRE_325, 10, 10)
connect _WIRE_324.hx, _T_4384
node _T_4385 = bits(_WIRE_325, 11, 11)
connect _WIRE_324.hw, _T_4385
node _T_4386 = bits(_WIRE_325, 12, 12)
connect _WIRE_324.sr, _T_4386
node _T_4387 = bits(_WIRE_325, 13, 13)
connect _WIRE_324.sx, _T_4387
node _T_4388 = bits(_WIRE_325, 14, 14)
connect _WIRE_324.sw, _T_4388
node _T_4389 = bits(_WIRE_325, 15, 15)
connect _WIRE_324.gf, _T_4389
node _T_4390 = bits(_WIRE_325, 16, 16)
connect _WIRE_324.pf, _T_4390
node _T_4391 = bits(_WIRE_325, 17, 17)
connect _WIRE_324.ae_stage2, _T_4391
node _T_4392 = bits(_WIRE_325, 18, 18)
connect _WIRE_324.ae_final, _T_4392
node _T_4393 = bits(_WIRE_325, 19, 19)
connect _WIRE_324.ae_ptw, _T_4393
node _T_4394 = bits(_WIRE_325, 20, 20)
connect _WIRE_324.g, _T_4394
node _T_4395 = bits(_WIRE_325, 21, 21)
connect _WIRE_324.u, _T_4395
node _T_4396 = bits(_WIRE_325, 41, 22)
connect _WIRE_324.ppn, _T_4396
node _T_4397 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1))
when _T_4397 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
node _T_4398 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1))
when _T_4398 :
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
node _T_4399 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1))
when _T_4399 :
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
node _T_4400 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1))
when _T_4400 :
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
wire _WIRE_326 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_327 : UInt<42>
connect _WIRE_327, sectored_entries[0][5].data[0]
node _T_4401 = bits(_WIRE_327, 0, 0)
connect _WIRE_326.fragmented_superpage, _T_4401
node _T_4402 = bits(_WIRE_327, 1, 1)
connect _WIRE_326.c, _T_4402
node _T_4403 = bits(_WIRE_327, 2, 2)
connect _WIRE_326.eff, _T_4403
node _T_4404 = bits(_WIRE_327, 3, 3)
connect _WIRE_326.paa, _T_4404
node _T_4405 = bits(_WIRE_327, 4, 4)
connect _WIRE_326.pal, _T_4405
node _T_4406 = bits(_WIRE_327, 5, 5)
connect _WIRE_326.ppp, _T_4406
node _T_4407 = bits(_WIRE_327, 6, 6)
connect _WIRE_326.pr, _T_4407
node _T_4408 = bits(_WIRE_327, 7, 7)
connect _WIRE_326.px, _T_4408
node _T_4409 = bits(_WIRE_327, 8, 8)
connect _WIRE_326.pw, _T_4409
node _T_4410 = bits(_WIRE_327, 9, 9)
connect _WIRE_326.hr, _T_4410
node _T_4411 = bits(_WIRE_327, 10, 10)
connect _WIRE_326.hx, _T_4411
node _T_4412 = bits(_WIRE_327, 11, 11)
connect _WIRE_326.hw, _T_4412
node _T_4413 = bits(_WIRE_327, 12, 12)
connect _WIRE_326.sr, _T_4413
node _T_4414 = bits(_WIRE_327, 13, 13)
connect _WIRE_326.sx, _T_4414
node _T_4415 = bits(_WIRE_327, 14, 14)
connect _WIRE_326.sw, _T_4415
node _T_4416 = bits(_WIRE_327, 15, 15)
connect _WIRE_326.gf, _T_4416
node _T_4417 = bits(_WIRE_327, 16, 16)
connect _WIRE_326.pf, _T_4417
node _T_4418 = bits(_WIRE_327, 17, 17)
connect _WIRE_326.ae_stage2, _T_4418
node _T_4419 = bits(_WIRE_327, 18, 18)
connect _WIRE_326.ae_final, _T_4419
node _T_4420 = bits(_WIRE_327, 19, 19)
connect _WIRE_326.ae_ptw, _T_4420
node _T_4421 = bits(_WIRE_327, 20, 20)
connect _WIRE_326.g, _T_4421
node _T_4422 = bits(_WIRE_327, 21, 21)
connect _WIRE_326.u, _T_4422
node _T_4423 = bits(_WIRE_327, 41, 22)
connect _WIRE_326.ppn, _T_4423
wire _WIRE_328 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_329 : UInt<42>
connect _WIRE_329, sectored_entries[0][5].data[1]
node _T_4424 = bits(_WIRE_329, 0, 0)
connect _WIRE_328.fragmented_superpage, _T_4424
node _T_4425 = bits(_WIRE_329, 1, 1)
connect _WIRE_328.c, _T_4425
node _T_4426 = bits(_WIRE_329, 2, 2)
connect _WIRE_328.eff, _T_4426
node _T_4427 = bits(_WIRE_329, 3, 3)
connect _WIRE_328.paa, _T_4427
node _T_4428 = bits(_WIRE_329, 4, 4)
connect _WIRE_328.pal, _T_4428
node _T_4429 = bits(_WIRE_329, 5, 5)
connect _WIRE_328.ppp, _T_4429
node _T_4430 = bits(_WIRE_329, 6, 6)
connect _WIRE_328.pr, _T_4430
node _T_4431 = bits(_WIRE_329, 7, 7)
connect _WIRE_328.px, _T_4431
node _T_4432 = bits(_WIRE_329, 8, 8)
connect _WIRE_328.pw, _T_4432
node _T_4433 = bits(_WIRE_329, 9, 9)
connect _WIRE_328.hr, _T_4433
node _T_4434 = bits(_WIRE_329, 10, 10)
connect _WIRE_328.hx, _T_4434
node _T_4435 = bits(_WIRE_329, 11, 11)
connect _WIRE_328.hw, _T_4435
node _T_4436 = bits(_WIRE_329, 12, 12)
connect _WIRE_328.sr, _T_4436
node _T_4437 = bits(_WIRE_329, 13, 13)
connect _WIRE_328.sx, _T_4437
node _T_4438 = bits(_WIRE_329, 14, 14)
connect _WIRE_328.sw, _T_4438
node _T_4439 = bits(_WIRE_329, 15, 15)
connect _WIRE_328.gf, _T_4439
node _T_4440 = bits(_WIRE_329, 16, 16)
connect _WIRE_328.pf, _T_4440
node _T_4441 = bits(_WIRE_329, 17, 17)
connect _WIRE_328.ae_stage2, _T_4441
node _T_4442 = bits(_WIRE_329, 18, 18)
connect _WIRE_328.ae_final, _T_4442
node _T_4443 = bits(_WIRE_329, 19, 19)
connect _WIRE_328.ae_ptw, _T_4443
node _T_4444 = bits(_WIRE_329, 20, 20)
connect _WIRE_328.g, _T_4444
node _T_4445 = bits(_WIRE_329, 21, 21)
connect _WIRE_328.u, _T_4445
node _T_4446 = bits(_WIRE_329, 41, 22)
connect _WIRE_328.ppn, _T_4446
wire _WIRE_330 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_331 : UInt<42>
connect _WIRE_331, sectored_entries[0][5].data[2]
node _T_4447 = bits(_WIRE_331, 0, 0)
connect _WIRE_330.fragmented_superpage, _T_4447
node _T_4448 = bits(_WIRE_331, 1, 1)
connect _WIRE_330.c, _T_4448
node _T_4449 = bits(_WIRE_331, 2, 2)
connect _WIRE_330.eff, _T_4449
node _T_4450 = bits(_WIRE_331, 3, 3)
connect _WIRE_330.paa, _T_4450
node _T_4451 = bits(_WIRE_331, 4, 4)
connect _WIRE_330.pal, _T_4451
node _T_4452 = bits(_WIRE_331, 5, 5)
connect _WIRE_330.ppp, _T_4452
node _T_4453 = bits(_WIRE_331, 6, 6)
connect _WIRE_330.pr, _T_4453
node _T_4454 = bits(_WIRE_331, 7, 7)
connect _WIRE_330.px, _T_4454
node _T_4455 = bits(_WIRE_331, 8, 8)
connect _WIRE_330.pw, _T_4455
node _T_4456 = bits(_WIRE_331, 9, 9)
connect _WIRE_330.hr, _T_4456
node _T_4457 = bits(_WIRE_331, 10, 10)
connect _WIRE_330.hx, _T_4457
node _T_4458 = bits(_WIRE_331, 11, 11)
connect _WIRE_330.hw, _T_4458
node _T_4459 = bits(_WIRE_331, 12, 12)
connect _WIRE_330.sr, _T_4459
node _T_4460 = bits(_WIRE_331, 13, 13)
connect _WIRE_330.sx, _T_4460
node _T_4461 = bits(_WIRE_331, 14, 14)
connect _WIRE_330.sw, _T_4461
node _T_4462 = bits(_WIRE_331, 15, 15)
connect _WIRE_330.gf, _T_4462
node _T_4463 = bits(_WIRE_331, 16, 16)
connect _WIRE_330.pf, _T_4463
node _T_4464 = bits(_WIRE_331, 17, 17)
connect _WIRE_330.ae_stage2, _T_4464
node _T_4465 = bits(_WIRE_331, 18, 18)
connect _WIRE_330.ae_final, _T_4465
node _T_4466 = bits(_WIRE_331, 19, 19)
connect _WIRE_330.ae_ptw, _T_4466
node _T_4467 = bits(_WIRE_331, 20, 20)
connect _WIRE_330.g, _T_4467
node _T_4468 = bits(_WIRE_331, 21, 21)
connect _WIRE_330.u, _T_4468
node _T_4469 = bits(_WIRE_331, 41, 22)
connect _WIRE_330.ppn, _T_4469
wire _WIRE_332 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_333 : UInt<42>
connect _WIRE_333, sectored_entries[0][5].data[3]
node _T_4470 = bits(_WIRE_333, 0, 0)
connect _WIRE_332.fragmented_superpage, _T_4470
node _T_4471 = bits(_WIRE_333, 1, 1)
connect _WIRE_332.c, _T_4471
node _T_4472 = bits(_WIRE_333, 2, 2)
connect _WIRE_332.eff, _T_4472
node _T_4473 = bits(_WIRE_333, 3, 3)
connect _WIRE_332.paa, _T_4473
node _T_4474 = bits(_WIRE_333, 4, 4)
connect _WIRE_332.pal, _T_4474
node _T_4475 = bits(_WIRE_333, 5, 5)
connect _WIRE_332.ppp, _T_4475
node _T_4476 = bits(_WIRE_333, 6, 6)
connect _WIRE_332.pr, _T_4476
node _T_4477 = bits(_WIRE_333, 7, 7)
connect _WIRE_332.px, _T_4477
node _T_4478 = bits(_WIRE_333, 8, 8)
connect _WIRE_332.pw, _T_4478
node _T_4479 = bits(_WIRE_333, 9, 9)
connect _WIRE_332.hr, _T_4479
node _T_4480 = bits(_WIRE_333, 10, 10)
connect _WIRE_332.hx, _T_4480
node _T_4481 = bits(_WIRE_333, 11, 11)
connect _WIRE_332.hw, _T_4481
node _T_4482 = bits(_WIRE_333, 12, 12)
connect _WIRE_332.sr, _T_4482
node _T_4483 = bits(_WIRE_333, 13, 13)
connect _WIRE_332.sx, _T_4483
node _T_4484 = bits(_WIRE_333, 14, 14)
connect _WIRE_332.sw, _T_4484
node _T_4485 = bits(_WIRE_333, 15, 15)
connect _WIRE_332.gf, _T_4485
node _T_4486 = bits(_WIRE_333, 16, 16)
connect _WIRE_332.pf, _T_4486
node _T_4487 = bits(_WIRE_333, 17, 17)
connect _WIRE_332.ae_stage2, _T_4487
node _T_4488 = bits(_WIRE_333, 18, 18)
connect _WIRE_332.ae_final, _T_4488
node _T_4489 = bits(_WIRE_333, 19, 19)
connect _WIRE_332.ae_ptw, _T_4489
node _T_4490 = bits(_WIRE_333, 20, 20)
connect _WIRE_332.g, _T_4490
node _T_4491 = bits(_WIRE_333, 21, 21)
connect _WIRE_332.u, _T_4491
node _T_4492 = bits(_WIRE_333, 41, 22)
connect _WIRE_332.ppn, _T_4492
node _T_4493 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1))
when _T_4493 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
node _T_4494 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1))
when _T_4494 :
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
node _T_4495 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1))
when _T_4495 :
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
node _T_4496 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1))
when _T_4496 :
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
wire _WIRE_334 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_335 : UInt<42>
connect _WIRE_335, sectored_entries[0][6].data[0]
node _T_4497 = bits(_WIRE_335, 0, 0)
connect _WIRE_334.fragmented_superpage, _T_4497
node _T_4498 = bits(_WIRE_335, 1, 1)
connect _WIRE_334.c, _T_4498
node _T_4499 = bits(_WIRE_335, 2, 2)
connect _WIRE_334.eff, _T_4499
node _T_4500 = bits(_WIRE_335, 3, 3)
connect _WIRE_334.paa, _T_4500
node _T_4501 = bits(_WIRE_335, 4, 4)
connect _WIRE_334.pal, _T_4501
node _T_4502 = bits(_WIRE_335, 5, 5)
connect _WIRE_334.ppp, _T_4502
node _T_4503 = bits(_WIRE_335, 6, 6)
connect _WIRE_334.pr, _T_4503
node _T_4504 = bits(_WIRE_335, 7, 7)
connect _WIRE_334.px, _T_4504
node _T_4505 = bits(_WIRE_335, 8, 8)
connect _WIRE_334.pw, _T_4505
node _T_4506 = bits(_WIRE_335, 9, 9)
connect _WIRE_334.hr, _T_4506
node _T_4507 = bits(_WIRE_335, 10, 10)
connect _WIRE_334.hx, _T_4507
node _T_4508 = bits(_WIRE_335, 11, 11)
connect _WIRE_334.hw, _T_4508
node _T_4509 = bits(_WIRE_335, 12, 12)
connect _WIRE_334.sr, _T_4509
node _T_4510 = bits(_WIRE_335, 13, 13)
connect _WIRE_334.sx, _T_4510
node _T_4511 = bits(_WIRE_335, 14, 14)
connect _WIRE_334.sw, _T_4511
node _T_4512 = bits(_WIRE_335, 15, 15)
connect _WIRE_334.gf, _T_4512
node _T_4513 = bits(_WIRE_335, 16, 16)
connect _WIRE_334.pf, _T_4513
node _T_4514 = bits(_WIRE_335, 17, 17)
connect _WIRE_334.ae_stage2, _T_4514
node _T_4515 = bits(_WIRE_335, 18, 18)
connect _WIRE_334.ae_final, _T_4515
node _T_4516 = bits(_WIRE_335, 19, 19)
connect _WIRE_334.ae_ptw, _T_4516
node _T_4517 = bits(_WIRE_335, 20, 20)
connect _WIRE_334.g, _T_4517
node _T_4518 = bits(_WIRE_335, 21, 21)
connect _WIRE_334.u, _T_4518
node _T_4519 = bits(_WIRE_335, 41, 22)
connect _WIRE_334.ppn, _T_4519
wire _WIRE_336 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_337 : UInt<42>
connect _WIRE_337, sectored_entries[0][6].data[1]
node _T_4520 = bits(_WIRE_337, 0, 0)
connect _WIRE_336.fragmented_superpage, _T_4520
node _T_4521 = bits(_WIRE_337, 1, 1)
connect _WIRE_336.c, _T_4521
node _T_4522 = bits(_WIRE_337, 2, 2)
connect _WIRE_336.eff, _T_4522
node _T_4523 = bits(_WIRE_337, 3, 3)
connect _WIRE_336.paa, _T_4523
node _T_4524 = bits(_WIRE_337, 4, 4)
connect _WIRE_336.pal, _T_4524
node _T_4525 = bits(_WIRE_337, 5, 5)
connect _WIRE_336.ppp, _T_4525
node _T_4526 = bits(_WIRE_337, 6, 6)
connect _WIRE_336.pr, _T_4526
node _T_4527 = bits(_WIRE_337, 7, 7)
connect _WIRE_336.px, _T_4527
node _T_4528 = bits(_WIRE_337, 8, 8)
connect _WIRE_336.pw, _T_4528
node _T_4529 = bits(_WIRE_337, 9, 9)
connect _WIRE_336.hr, _T_4529
node _T_4530 = bits(_WIRE_337, 10, 10)
connect _WIRE_336.hx, _T_4530
node _T_4531 = bits(_WIRE_337, 11, 11)
connect _WIRE_336.hw, _T_4531
node _T_4532 = bits(_WIRE_337, 12, 12)
connect _WIRE_336.sr, _T_4532
node _T_4533 = bits(_WIRE_337, 13, 13)
connect _WIRE_336.sx, _T_4533
node _T_4534 = bits(_WIRE_337, 14, 14)
connect _WIRE_336.sw, _T_4534
node _T_4535 = bits(_WIRE_337, 15, 15)
connect _WIRE_336.gf, _T_4535
node _T_4536 = bits(_WIRE_337, 16, 16)
connect _WIRE_336.pf, _T_4536
node _T_4537 = bits(_WIRE_337, 17, 17)
connect _WIRE_336.ae_stage2, _T_4537
node _T_4538 = bits(_WIRE_337, 18, 18)
connect _WIRE_336.ae_final, _T_4538
node _T_4539 = bits(_WIRE_337, 19, 19)
connect _WIRE_336.ae_ptw, _T_4539
node _T_4540 = bits(_WIRE_337, 20, 20)
connect _WIRE_336.g, _T_4540
node _T_4541 = bits(_WIRE_337, 21, 21)
connect _WIRE_336.u, _T_4541
node _T_4542 = bits(_WIRE_337, 41, 22)
connect _WIRE_336.ppn, _T_4542
wire _WIRE_338 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_339 : UInt<42>
connect _WIRE_339, sectored_entries[0][6].data[2]
node _T_4543 = bits(_WIRE_339, 0, 0)
connect _WIRE_338.fragmented_superpage, _T_4543
node _T_4544 = bits(_WIRE_339, 1, 1)
connect _WIRE_338.c, _T_4544
node _T_4545 = bits(_WIRE_339, 2, 2)
connect _WIRE_338.eff, _T_4545
node _T_4546 = bits(_WIRE_339, 3, 3)
connect _WIRE_338.paa, _T_4546
node _T_4547 = bits(_WIRE_339, 4, 4)
connect _WIRE_338.pal, _T_4547
node _T_4548 = bits(_WIRE_339, 5, 5)
connect _WIRE_338.ppp, _T_4548
node _T_4549 = bits(_WIRE_339, 6, 6)
connect _WIRE_338.pr, _T_4549
node _T_4550 = bits(_WIRE_339, 7, 7)
connect _WIRE_338.px, _T_4550
node _T_4551 = bits(_WIRE_339, 8, 8)
connect _WIRE_338.pw, _T_4551
node _T_4552 = bits(_WIRE_339, 9, 9)
connect _WIRE_338.hr, _T_4552
node _T_4553 = bits(_WIRE_339, 10, 10)
connect _WIRE_338.hx, _T_4553
node _T_4554 = bits(_WIRE_339, 11, 11)
connect _WIRE_338.hw, _T_4554
node _T_4555 = bits(_WIRE_339, 12, 12)
connect _WIRE_338.sr, _T_4555
node _T_4556 = bits(_WIRE_339, 13, 13)
connect _WIRE_338.sx, _T_4556
node _T_4557 = bits(_WIRE_339, 14, 14)
connect _WIRE_338.sw, _T_4557
node _T_4558 = bits(_WIRE_339, 15, 15)
connect _WIRE_338.gf, _T_4558
node _T_4559 = bits(_WIRE_339, 16, 16)
connect _WIRE_338.pf, _T_4559
node _T_4560 = bits(_WIRE_339, 17, 17)
connect _WIRE_338.ae_stage2, _T_4560
node _T_4561 = bits(_WIRE_339, 18, 18)
connect _WIRE_338.ae_final, _T_4561
node _T_4562 = bits(_WIRE_339, 19, 19)
connect _WIRE_338.ae_ptw, _T_4562
node _T_4563 = bits(_WIRE_339, 20, 20)
connect _WIRE_338.g, _T_4563
node _T_4564 = bits(_WIRE_339, 21, 21)
connect _WIRE_338.u, _T_4564
node _T_4565 = bits(_WIRE_339, 41, 22)
connect _WIRE_338.ppn, _T_4565
wire _WIRE_340 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_341 : UInt<42>
connect _WIRE_341, sectored_entries[0][6].data[3]
node _T_4566 = bits(_WIRE_341, 0, 0)
connect _WIRE_340.fragmented_superpage, _T_4566
node _T_4567 = bits(_WIRE_341, 1, 1)
connect _WIRE_340.c, _T_4567
node _T_4568 = bits(_WIRE_341, 2, 2)
connect _WIRE_340.eff, _T_4568
node _T_4569 = bits(_WIRE_341, 3, 3)
connect _WIRE_340.paa, _T_4569
node _T_4570 = bits(_WIRE_341, 4, 4)
connect _WIRE_340.pal, _T_4570
node _T_4571 = bits(_WIRE_341, 5, 5)
connect _WIRE_340.ppp, _T_4571
node _T_4572 = bits(_WIRE_341, 6, 6)
connect _WIRE_340.pr, _T_4572
node _T_4573 = bits(_WIRE_341, 7, 7)
connect _WIRE_340.px, _T_4573
node _T_4574 = bits(_WIRE_341, 8, 8)
connect _WIRE_340.pw, _T_4574
node _T_4575 = bits(_WIRE_341, 9, 9)
connect _WIRE_340.hr, _T_4575
node _T_4576 = bits(_WIRE_341, 10, 10)
connect _WIRE_340.hx, _T_4576
node _T_4577 = bits(_WIRE_341, 11, 11)
connect _WIRE_340.hw, _T_4577
node _T_4578 = bits(_WIRE_341, 12, 12)
connect _WIRE_340.sr, _T_4578
node _T_4579 = bits(_WIRE_341, 13, 13)
connect _WIRE_340.sx, _T_4579
node _T_4580 = bits(_WIRE_341, 14, 14)
connect _WIRE_340.sw, _T_4580
node _T_4581 = bits(_WIRE_341, 15, 15)
connect _WIRE_340.gf, _T_4581
node _T_4582 = bits(_WIRE_341, 16, 16)
connect _WIRE_340.pf, _T_4582
node _T_4583 = bits(_WIRE_341, 17, 17)
connect _WIRE_340.ae_stage2, _T_4583
node _T_4584 = bits(_WIRE_341, 18, 18)
connect _WIRE_340.ae_final, _T_4584
node _T_4585 = bits(_WIRE_341, 19, 19)
connect _WIRE_340.ae_ptw, _T_4585
node _T_4586 = bits(_WIRE_341, 20, 20)
connect _WIRE_340.g, _T_4586
node _T_4587 = bits(_WIRE_341, 21, 21)
connect _WIRE_340.u, _T_4587
node _T_4588 = bits(_WIRE_341, 41, 22)
connect _WIRE_340.ppn, _T_4588
node _T_4589 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1))
when _T_4589 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
node _T_4590 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1))
when _T_4590 :
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
node _T_4591 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1))
when _T_4591 :
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
node _T_4592 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1))
when _T_4592 :
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
wire _WIRE_342 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_343 : UInt<42>
connect _WIRE_343, sectored_entries[0][7].data[0]
node _T_4593 = bits(_WIRE_343, 0, 0)
connect _WIRE_342.fragmented_superpage, _T_4593
node _T_4594 = bits(_WIRE_343, 1, 1)
connect _WIRE_342.c, _T_4594
node _T_4595 = bits(_WIRE_343, 2, 2)
connect _WIRE_342.eff, _T_4595
node _T_4596 = bits(_WIRE_343, 3, 3)
connect _WIRE_342.paa, _T_4596
node _T_4597 = bits(_WIRE_343, 4, 4)
connect _WIRE_342.pal, _T_4597
node _T_4598 = bits(_WIRE_343, 5, 5)
connect _WIRE_342.ppp, _T_4598
node _T_4599 = bits(_WIRE_343, 6, 6)
connect _WIRE_342.pr, _T_4599
node _T_4600 = bits(_WIRE_343, 7, 7)
connect _WIRE_342.px, _T_4600
node _T_4601 = bits(_WIRE_343, 8, 8)
connect _WIRE_342.pw, _T_4601
node _T_4602 = bits(_WIRE_343, 9, 9)
connect _WIRE_342.hr, _T_4602
node _T_4603 = bits(_WIRE_343, 10, 10)
connect _WIRE_342.hx, _T_4603
node _T_4604 = bits(_WIRE_343, 11, 11)
connect _WIRE_342.hw, _T_4604
node _T_4605 = bits(_WIRE_343, 12, 12)
connect _WIRE_342.sr, _T_4605
node _T_4606 = bits(_WIRE_343, 13, 13)
connect _WIRE_342.sx, _T_4606
node _T_4607 = bits(_WIRE_343, 14, 14)
connect _WIRE_342.sw, _T_4607
node _T_4608 = bits(_WIRE_343, 15, 15)
connect _WIRE_342.gf, _T_4608
node _T_4609 = bits(_WIRE_343, 16, 16)
connect _WIRE_342.pf, _T_4609
node _T_4610 = bits(_WIRE_343, 17, 17)
connect _WIRE_342.ae_stage2, _T_4610
node _T_4611 = bits(_WIRE_343, 18, 18)
connect _WIRE_342.ae_final, _T_4611
node _T_4612 = bits(_WIRE_343, 19, 19)
connect _WIRE_342.ae_ptw, _T_4612
node _T_4613 = bits(_WIRE_343, 20, 20)
connect _WIRE_342.g, _T_4613
node _T_4614 = bits(_WIRE_343, 21, 21)
connect _WIRE_342.u, _T_4614
node _T_4615 = bits(_WIRE_343, 41, 22)
connect _WIRE_342.ppn, _T_4615
wire _WIRE_344 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_345 : UInt<42>
connect _WIRE_345, sectored_entries[0][7].data[1]
node _T_4616 = bits(_WIRE_345, 0, 0)
connect _WIRE_344.fragmented_superpage, _T_4616
node _T_4617 = bits(_WIRE_345, 1, 1)
connect _WIRE_344.c, _T_4617
node _T_4618 = bits(_WIRE_345, 2, 2)
connect _WIRE_344.eff, _T_4618
node _T_4619 = bits(_WIRE_345, 3, 3)
connect _WIRE_344.paa, _T_4619
node _T_4620 = bits(_WIRE_345, 4, 4)
connect _WIRE_344.pal, _T_4620
node _T_4621 = bits(_WIRE_345, 5, 5)
connect _WIRE_344.ppp, _T_4621
node _T_4622 = bits(_WIRE_345, 6, 6)
connect _WIRE_344.pr, _T_4622
node _T_4623 = bits(_WIRE_345, 7, 7)
connect _WIRE_344.px, _T_4623
node _T_4624 = bits(_WIRE_345, 8, 8)
connect _WIRE_344.pw, _T_4624
node _T_4625 = bits(_WIRE_345, 9, 9)
connect _WIRE_344.hr, _T_4625
node _T_4626 = bits(_WIRE_345, 10, 10)
connect _WIRE_344.hx, _T_4626
node _T_4627 = bits(_WIRE_345, 11, 11)
connect _WIRE_344.hw, _T_4627
node _T_4628 = bits(_WIRE_345, 12, 12)
connect _WIRE_344.sr, _T_4628
node _T_4629 = bits(_WIRE_345, 13, 13)
connect _WIRE_344.sx, _T_4629
node _T_4630 = bits(_WIRE_345, 14, 14)
connect _WIRE_344.sw, _T_4630
node _T_4631 = bits(_WIRE_345, 15, 15)
connect _WIRE_344.gf, _T_4631
node _T_4632 = bits(_WIRE_345, 16, 16)
connect _WIRE_344.pf, _T_4632
node _T_4633 = bits(_WIRE_345, 17, 17)
connect _WIRE_344.ae_stage2, _T_4633
node _T_4634 = bits(_WIRE_345, 18, 18)
connect _WIRE_344.ae_final, _T_4634
node _T_4635 = bits(_WIRE_345, 19, 19)
connect _WIRE_344.ae_ptw, _T_4635
node _T_4636 = bits(_WIRE_345, 20, 20)
connect _WIRE_344.g, _T_4636
node _T_4637 = bits(_WIRE_345, 21, 21)
connect _WIRE_344.u, _T_4637
node _T_4638 = bits(_WIRE_345, 41, 22)
connect _WIRE_344.ppn, _T_4638
wire _WIRE_346 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_347 : UInt<42>
connect _WIRE_347, sectored_entries[0][7].data[2]
node _T_4639 = bits(_WIRE_347, 0, 0)
connect _WIRE_346.fragmented_superpage, _T_4639
node _T_4640 = bits(_WIRE_347, 1, 1)
connect _WIRE_346.c, _T_4640
node _T_4641 = bits(_WIRE_347, 2, 2)
connect _WIRE_346.eff, _T_4641
node _T_4642 = bits(_WIRE_347, 3, 3)
connect _WIRE_346.paa, _T_4642
node _T_4643 = bits(_WIRE_347, 4, 4)
connect _WIRE_346.pal, _T_4643
node _T_4644 = bits(_WIRE_347, 5, 5)
connect _WIRE_346.ppp, _T_4644
node _T_4645 = bits(_WIRE_347, 6, 6)
connect _WIRE_346.pr, _T_4645
node _T_4646 = bits(_WIRE_347, 7, 7)
connect _WIRE_346.px, _T_4646
node _T_4647 = bits(_WIRE_347, 8, 8)
connect _WIRE_346.pw, _T_4647
node _T_4648 = bits(_WIRE_347, 9, 9)
connect _WIRE_346.hr, _T_4648
node _T_4649 = bits(_WIRE_347, 10, 10)
connect _WIRE_346.hx, _T_4649
node _T_4650 = bits(_WIRE_347, 11, 11)
connect _WIRE_346.hw, _T_4650
node _T_4651 = bits(_WIRE_347, 12, 12)
connect _WIRE_346.sr, _T_4651
node _T_4652 = bits(_WIRE_347, 13, 13)
connect _WIRE_346.sx, _T_4652
node _T_4653 = bits(_WIRE_347, 14, 14)
connect _WIRE_346.sw, _T_4653
node _T_4654 = bits(_WIRE_347, 15, 15)
connect _WIRE_346.gf, _T_4654
node _T_4655 = bits(_WIRE_347, 16, 16)
connect _WIRE_346.pf, _T_4655
node _T_4656 = bits(_WIRE_347, 17, 17)
connect _WIRE_346.ae_stage2, _T_4656
node _T_4657 = bits(_WIRE_347, 18, 18)
connect _WIRE_346.ae_final, _T_4657
node _T_4658 = bits(_WIRE_347, 19, 19)
connect _WIRE_346.ae_ptw, _T_4658
node _T_4659 = bits(_WIRE_347, 20, 20)
connect _WIRE_346.g, _T_4659
node _T_4660 = bits(_WIRE_347, 21, 21)
connect _WIRE_346.u, _T_4660
node _T_4661 = bits(_WIRE_347, 41, 22)
connect _WIRE_346.ppn, _T_4661
wire _WIRE_348 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_349 : UInt<42>
connect _WIRE_349, sectored_entries[0][7].data[3]
node _T_4662 = bits(_WIRE_349, 0, 0)
connect _WIRE_348.fragmented_superpage, _T_4662
node _T_4663 = bits(_WIRE_349, 1, 1)
connect _WIRE_348.c, _T_4663
node _T_4664 = bits(_WIRE_349, 2, 2)
connect _WIRE_348.eff, _T_4664
node _T_4665 = bits(_WIRE_349, 3, 3)
connect _WIRE_348.paa, _T_4665
node _T_4666 = bits(_WIRE_349, 4, 4)
connect _WIRE_348.pal, _T_4666
node _T_4667 = bits(_WIRE_349, 5, 5)
connect _WIRE_348.ppp, _T_4667
node _T_4668 = bits(_WIRE_349, 6, 6)
connect _WIRE_348.pr, _T_4668
node _T_4669 = bits(_WIRE_349, 7, 7)
connect _WIRE_348.px, _T_4669
node _T_4670 = bits(_WIRE_349, 8, 8)
connect _WIRE_348.pw, _T_4670
node _T_4671 = bits(_WIRE_349, 9, 9)
connect _WIRE_348.hr, _T_4671
node _T_4672 = bits(_WIRE_349, 10, 10)
connect _WIRE_348.hx, _T_4672
node _T_4673 = bits(_WIRE_349, 11, 11)
connect _WIRE_348.hw, _T_4673
node _T_4674 = bits(_WIRE_349, 12, 12)
connect _WIRE_348.sr, _T_4674
node _T_4675 = bits(_WIRE_349, 13, 13)
connect _WIRE_348.sx, _T_4675
node _T_4676 = bits(_WIRE_349, 14, 14)
connect _WIRE_348.sw, _T_4676
node _T_4677 = bits(_WIRE_349, 15, 15)
connect _WIRE_348.gf, _T_4677
node _T_4678 = bits(_WIRE_349, 16, 16)
connect _WIRE_348.pf, _T_4678
node _T_4679 = bits(_WIRE_349, 17, 17)
connect _WIRE_348.ae_stage2, _T_4679
node _T_4680 = bits(_WIRE_349, 18, 18)
connect _WIRE_348.ae_final, _T_4680
node _T_4681 = bits(_WIRE_349, 19, 19)
connect _WIRE_348.ae_ptw, _T_4681
node _T_4682 = bits(_WIRE_349, 20, 20)
connect _WIRE_348.g, _T_4682
node _T_4683 = bits(_WIRE_349, 21, 21)
connect _WIRE_348.u, _T_4683
node _T_4684 = bits(_WIRE_349, 41, 22)
connect _WIRE_348.ppn, _T_4684
node _T_4685 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1))
when _T_4685 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
node _T_4686 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1))
when _T_4686 :
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
node _T_4687 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1))
when _T_4687 :
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
node _T_4688 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1))
when _T_4688 :
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
wire _WIRE_350 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_351 : UInt<42>
connect _WIRE_351, superpage_entries[0].data[0]
node _T_4689 = bits(_WIRE_351, 0, 0)
connect _WIRE_350.fragmented_superpage, _T_4689
node _T_4690 = bits(_WIRE_351, 1, 1)
connect _WIRE_350.c, _T_4690
node _T_4691 = bits(_WIRE_351, 2, 2)
connect _WIRE_350.eff, _T_4691
node _T_4692 = bits(_WIRE_351, 3, 3)
connect _WIRE_350.paa, _T_4692
node _T_4693 = bits(_WIRE_351, 4, 4)
connect _WIRE_350.pal, _T_4693
node _T_4694 = bits(_WIRE_351, 5, 5)
connect _WIRE_350.ppp, _T_4694
node _T_4695 = bits(_WIRE_351, 6, 6)
connect _WIRE_350.pr, _T_4695
node _T_4696 = bits(_WIRE_351, 7, 7)
connect _WIRE_350.px, _T_4696
node _T_4697 = bits(_WIRE_351, 8, 8)
connect _WIRE_350.pw, _T_4697
node _T_4698 = bits(_WIRE_351, 9, 9)
connect _WIRE_350.hr, _T_4698
node _T_4699 = bits(_WIRE_351, 10, 10)
connect _WIRE_350.hx, _T_4699
node _T_4700 = bits(_WIRE_351, 11, 11)
connect _WIRE_350.hw, _T_4700
node _T_4701 = bits(_WIRE_351, 12, 12)
connect _WIRE_350.sr, _T_4701
node _T_4702 = bits(_WIRE_351, 13, 13)
connect _WIRE_350.sx, _T_4702
node _T_4703 = bits(_WIRE_351, 14, 14)
connect _WIRE_350.sw, _T_4703
node _T_4704 = bits(_WIRE_351, 15, 15)
connect _WIRE_350.gf, _T_4704
node _T_4705 = bits(_WIRE_351, 16, 16)
connect _WIRE_350.pf, _T_4705
node _T_4706 = bits(_WIRE_351, 17, 17)
connect _WIRE_350.ae_stage2, _T_4706
node _T_4707 = bits(_WIRE_351, 18, 18)
connect _WIRE_350.ae_final, _T_4707
node _T_4708 = bits(_WIRE_351, 19, 19)
connect _WIRE_350.ae_ptw, _T_4708
node _T_4709 = bits(_WIRE_351, 20, 20)
connect _WIRE_350.g, _T_4709
node _T_4710 = bits(_WIRE_351, 21, 21)
connect _WIRE_350.u, _T_4710
node _T_4711 = bits(_WIRE_351, 41, 22)
connect _WIRE_350.ppn, _T_4711
node _T_4712 = eq(superpage_entries[0].tag_v, UInt<1>(0h1))
when _T_4712 :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
wire _WIRE_352 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_353 : UInt<42>
connect _WIRE_353, superpage_entries[1].data[0]
node _T_4713 = bits(_WIRE_353, 0, 0)
connect _WIRE_352.fragmented_superpage, _T_4713
node _T_4714 = bits(_WIRE_353, 1, 1)
connect _WIRE_352.c, _T_4714
node _T_4715 = bits(_WIRE_353, 2, 2)
connect _WIRE_352.eff, _T_4715
node _T_4716 = bits(_WIRE_353, 3, 3)
connect _WIRE_352.paa, _T_4716
node _T_4717 = bits(_WIRE_353, 4, 4)
connect _WIRE_352.pal, _T_4717
node _T_4718 = bits(_WIRE_353, 5, 5)
connect _WIRE_352.ppp, _T_4718
node _T_4719 = bits(_WIRE_353, 6, 6)
connect _WIRE_352.pr, _T_4719
node _T_4720 = bits(_WIRE_353, 7, 7)
connect _WIRE_352.px, _T_4720
node _T_4721 = bits(_WIRE_353, 8, 8)
connect _WIRE_352.pw, _T_4721
node _T_4722 = bits(_WIRE_353, 9, 9)
connect _WIRE_352.hr, _T_4722
node _T_4723 = bits(_WIRE_353, 10, 10)
connect _WIRE_352.hx, _T_4723
node _T_4724 = bits(_WIRE_353, 11, 11)
connect _WIRE_352.hw, _T_4724
node _T_4725 = bits(_WIRE_353, 12, 12)
connect _WIRE_352.sr, _T_4725
node _T_4726 = bits(_WIRE_353, 13, 13)
connect _WIRE_352.sx, _T_4726
node _T_4727 = bits(_WIRE_353, 14, 14)
connect _WIRE_352.sw, _T_4727
node _T_4728 = bits(_WIRE_353, 15, 15)
connect _WIRE_352.gf, _T_4728
node _T_4729 = bits(_WIRE_353, 16, 16)
connect _WIRE_352.pf, _T_4729
node _T_4730 = bits(_WIRE_353, 17, 17)
connect _WIRE_352.ae_stage2, _T_4730
node _T_4731 = bits(_WIRE_353, 18, 18)
connect _WIRE_352.ae_final, _T_4731
node _T_4732 = bits(_WIRE_353, 19, 19)
connect _WIRE_352.ae_ptw, _T_4732
node _T_4733 = bits(_WIRE_353, 20, 20)
connect _WIRE_352.g, _T_4733
node _T_4734 = bits(_WIRE_353, 21, 21)
connect _WIRE_352.u, _T_4734
node _T_4735 = bits(_WIRE_353, 41, 22)
connect _WIRE_352.ppn, _T_4735
node _T_4736 = eq(superpage_entries[1].tag_v, UInt<1>(0h1))
when _T_4736 :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
wire _WIRE_354 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_355 : UInt<42>
connect _WIRE_355, superpage_entries[2].data[0]
node _T_4737 = bits(_WIRE_355, 0, 0)
connect _WIRE_354.fragmented_superpage, _T_4737
node _T_4738 = bits(_WIRE_355, 1, 1)
connect _WIRE_354.c, _T_4738
node _T_4739 = bits(_WIRE_355, 2, 2)
connect _WIRE_354.eff, _T_4739
node _T_4740 = bits(_WIRE_355, 3, 3)
connect _WIRE_354.paa, _T_4740
node _T_4741 = bits(_WIRE_355, 4, 4)
connect _WIRE_354.pal, _T_4741
node _T_4742 = bits(_WIRE_355, 5, 5)
connect _WIRE_354.ppp, _T_4742
node _T_4743 = bits(_WIRE_355, 6, 6)
connect _WIRE_354.pr, _T_4743
node _T_4744 = bits(_WIRE_355, 7, 7)
connect _WIRE_354.px, _T_4744
node _T_4745 = bits(_WIRE_355, 8, 8)
connect _WIRE_354.pw, _T_4745
node _T_4746 = bits(_WIRE_355, 9, 9)
connect _WIRE_354.hr, _T_4746
node _T_4747 = bits(_WIRE_355, 10, 10)
connect _WIRE_354.hx, _T_4747
node _T_4748 = bits(_WIRE_355, 11, 11)
connect _WIRE_354.hw, _T_4748
node _T_4749 = bits(_WIRE_355, 12, 12)
connect _WIRE_354.sr, _T_4749
node _T_4750 = bits(_WIRE_355, 13, 13)
connect _WIRE_354.sx, _T_4750
node _T_4751 = bits(_WIRE_355, 14, 14)
connect _WIRE_354.sw, _T_4751
node _T_4752 = bits(_WIRE_355, 15, 15)
connect _WIRE_354.gf, _T_4752
node _T_4753 = bits(_WIRE_355, 16, 16)
connect _WIRE_354.pf, _T_4753
node _T_4754 = bits(_WIRE_355, 17, 17)
connect _WIRE_354.ae_stage2, _T_4754
node _T_4755 = bits(_WIRE_355, 18, 18)
connect _WIRE_354.ae_final, _T_4755
node _T_4756 = bits(_WIRE_355, 19, 19)
connect _WIRE_354.ae_ptw, _T_4756
node _T_4757 = bits(_WIRE_355, 20, 20)
connect _WIRE_354.g, _T_4757
node _T_4758 = bits(_WIRE_355, 21, 21)
connect _WIRE_354.u, _T_4758
node _T_4759 = bits(_WIRE_355, 41, 22)
connect _WIRE_354.ppn, _T_4759
node _T_4760 = eq(superpage_entries[2].tag_v, UInt<1>(0h1))
when _T_4760 :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
wire _WIRE_356 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_357 : UInt<42>
connect _WIRE_357, superpage_entries[3].data[0]
node _T_4761 = bits(_WIRE_357, 0, 0)
connect _WIRE_356.fragmented_superpage, _T_4761
node _T_4762 = bits(_WIRE_357, 1, 1)
connect _WIRE_356.c, _T_4762
node _T_4763 = bits(_WIRE_357, 2, 2)
connect _WIRE_356.eff, _T_4763
node _T_4764 = bits(_WIRE_357, 3, 3)
connect _WIRE_356.paa, _T_4764
node _T_4765 = bits(_WIRE_357, 4, 4)
connect _WIRE_356.pal, _T_4765
node _T_4766 = bits(_WIRE_357, 5, 5)
connect _WIRE_356.ppp, _T_4766
node _T_4767 = bits(_WIRE_357, 6, 6)
connect _WIRE_356.pr, _T_4767
node _T_4768 = bits(_WIRE_357, 7, 7)
connect _WIRE_356.px, _T_4768
node _T_4769 = bits(_WIRE_357, 8, 8)
connect _WIRE_356.pw, _T_4769
node _T_4770 = bits(_WIRE_357, 9, 9)
connect _WIRE_356.hr, _T_4770
node _T_4771 = bits(_WIRE_357, 10, 10)
connect _WIRE_356.hx, _T_4771
node _T_4772 = bits(_WIRE_357, 11, 11)
connect _WIRE_356.hw, _T_4772
node _T_4773 = bits(_WIRE_357, 12, 12)
connect _WIRE_356.sr, _T_4773
node _T_4774 = bits(_WIRE_357, 13, 13)
connect _WIRE_356.sx, _T_4774
node _T_4775 = bits(_WIRE_357, 14, 14)
connect _WIRE_356.sw, _T_4775
node _T_4776 = bits(_WIRE_357, 15, 15)
connect _WIRE_356.gf, _T_4776
node _T_4777 = bits(_WIRE_357, 16, 16)
connect _WIRE_356.pf, _T_4777
node _T_4778 = bits(_WIRE_357, 17, 17)
connect _WIRE_356.ae_stage2, _T_4778
node _T_4779 = bits(_WIRE_357, 18, 18)
connect _WIRE_356.ae_final, _T_4779
node _T_4780 = bits(_WIRE_357, 19, 19)
connect _WIRE_356.ae_ptw, _T_4780
node _T_4781 = bits(_WIRE_357, 20, 20)
connect _WIRE_356.g, _T_4781
node _T_4782 = bits(_WIRE_357, 21, 21)
connect _WIRE_356.u, _T_4782
node _T_4783 = bits(_WIRE_357, 41, 22)
connect _WIRE_356.ppn, _T_4783
node _T_4784 = eq(superpage_entries[3].tag_v, UInt<1>(0h1))
when _T_4784 :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
wire _WIRE_358 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_359 : UInt<42>
connect _WIRE_359, special_entry.data[0]
node _T_4785 = bits(_WIRE_359, 0, 0)
connect _WIRE_358.fragmented_superpage, _T_4785
node _T_4786 = bits(_WIRE_359, 1, 1)
connect _WIRE_358.c, _T_4786
node _T_4787 = bits(_WIRE_359, 2, 2)
connect _WIRE_358.eff, _T_4787
node _T_4788 = bits(_WIRE_359, 3, 3)
connect _WIRE_358.paa, _T_4788
node _T_4789 = bits(_WIRE_359, 4, 4)
connect _WIRE_358.pal, _T_4789
node _T_4790 = bits(_WIRE_359, 5, 5)
connect _WIRE_358.ppp, _T_4790
node _T_4791 = bits(_WIRE_359, 6, 6)
connect _WIRE_358.pr, _T_4791
node _T_4792 = bits(_WIRE_359, 7, 7)
connect _WIRE_358.px, _T_4792
node _T_4793 = bits(_WIRE_359, 8, 8)
connect _WIRE_358.pw, _T_4793
node _T_4794 = bits(_WIRE_359, 9, 9)
connect _WIRE_358.hr, _T_4794
node _T_4795 = bits(_WIRE_359, 10, 10)
connect _WIRE_358.hx, _T_4795
node _T_4796 = bits(_WIRE_359, 11, 11)
connect _WIRE_358.hw, _T_4796
node _T_4797 = bits(_WIRE_359, 12, 12)
connect _WIRE_358.sr, _T_4797
node _T_4798 = bits(_WIRE_359, 13, 13)
connect _WIRE_358.sx, _T_4798
node _T_4799 = bits(_WIRE_359, 14, 14)
connect _WIRE_358.sw, _T_4799
node _T_4800 = bits(_WIRE_359, 15, 15)
connect _WIRE_358.gf, _T_4800
node _T_4801 = bits(_WIRE_359, 16, 16)
connect _WIRE_358.pf, _T_4801
node _T_4802 = bits(_WIRE_359, 17, 17)
connect _WIRE_358.ae_stage2, _T_4802
node _T_4803 = bits(_WIRE_359, 18, 18)
connect _WIRE_358.ae_final, _T_4803
node _T_4804 = bits(_WIRE_359, 19, 19)
connect _WIRE_358.ae_ptw, _T_4804
node _T_4805 = bits(_WIRE_359, 20, 20)
connect _WIRE_358.g, _T_4805
node _T_4806 = bits(_WIRE_359, 21, 21)
connect _WIRE_358.u, _T_4806
node _T_4807 = bits(_WIRE_359, 41, 22)
connect _WIRE_358.ppn, _T_4807
node _T_4808 = eq(special_entry.tag_v, UInt<1>(0h1))
when _T_4808 :
connect special_entry.valid[0], UInt<1>(0h0)
connect v_entries_use_stage1, vstage1_en
node _T_4809 = asUInt(reset)
node _T_4810 = or(multipleHits, _T_4809)
when _T_4810 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
connect superpage_entries[0].valid[0], UInt<1>(0h0)
connect superpage_entries[1].valid[0], UInt<1>(0h0)
connect superpage_entries[2].valid[0], UInt<1>(0h0)
connect superpage_entries[3].valid[0], UInt<1>(0h0)
connect special_entry.valid[0], UInt<1>(0h0)
node _T_4811 = and(io.ptw.req.ready, io.ptw.req.valid)
node _T_4812 = eq(io.ptw.req.ready, UInt<1>(0h0))
node _T_4813 = and(io.ptw.req.valid, _T_4812)
node _T_4814 = eq(state, UInt<2>(0h3))
node _T_4815 = eq(io.sfence.bits.rs1, UInt<1>(0h0))
node _T_4816 = and(io.sfence.valid, _T_4815)
node _T_4817 = eq(io.sfence.bits.rs2, UInt<1>(0h0))
node _T_4818 = and(_T_4816, _T_4817)
node _T_4819 = eq(io.sfence.bits.rs1, UInt<1>(0h0))
node _T_4820 = and(io.sfence.valid, _T_4819)
node _T_4821 = and(_T_4820, io.sfence.bits.rs2)
node _T_4822 = and(io.sfence.valid, io.sfence.bits.rs1)
node _T_4823 = eq(io.sfence.bits.rs2, UInt<1>(0h0))
node _T_4824 = and(_T_4822, _T_4823)
node _T_4825 = and(io.sfence.valid, io.sfence.bits.rs1)
node _T_4826 = and(_T_4825, io.sfence.bits.rs2) | module ITLB_3( // @[TLB.scala:318:7]
input clock, // @[TLB.scala:318:7]
input reset, // @[TLB.scala:318:7]
input io_req_valid, // @[TLB.scala:320:14]
input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14]
input [1:0] io_req_bits_prv, // @[TLB.scala:320:14]
input io_req_bits_v, // @[TLB.scala:320:14]
output io_resp_miss, // @[TLB.scala:320:14]
output [31:0] io_resp_paddr, // @[TLB.scala:320:14]
output [39:0] io_resp_gpa, // @[TLB.scala:320:14]
output io_resp_pf_ld, // @[TLB.scala:320:14]
output io_resp_pf_inst, // @[TLB.scala:320:14]
output io_resp_ae_ld, // @[TLB.scala:320:14]
output io_resp_ae_inst, // @[TLB.scala:320:14]
output io_resp_ma_ld, // @[TLB.scala:320:14]
output io_resp_cacheable, // @[TLB.scala:320:14]
output io_resp_prefetchable, // @[TLB.scala:320:14]
input io_sfence_valid, // @[TLB.scala:320:14]
input io_sfence_bits_rs1, // @[TLB.scala:320:14]
input io_sfence_bits_rs2, // @[TLB.scala:320:14]
input [38:0] io_sfence_bits_addr, // @[TLB.scala:320:14]
input io_sfence_bits_asid, // @[TLB.scala:320:14]
input io_sfence_bits_hv, // @[TLB.scala:320:14]
input io_sfence_bits_hg, // @[TLB.scala:320:14]
input io_ptw_req_ready, // @[TLB.scala:320:14]
output io_ptw_req_valid, // @[TLB.scala:320:14]
output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14]
output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14]
input io_ptw_resp_valid, // @[TLB.scala:320:14]
input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14]
input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pf, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gf, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hr, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hw, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hx, // @[TLB.scala:320:14]
input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14]
input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14]
input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14]
input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14]
input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14]
input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14]
input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14]
input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14]
input io_ptw_status_debug, // @[TLB.scala:320:14]
input io_ptw_status_cease, // @[TLB.scala:320:14]
input io_ptw_status_wfi, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14]
input io_ptw_status_dv, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14]
input io_ptw_status_v, // @[TLB.scala:320:14]
input io_ptw_status_sd, // @[TLB.scala:320:14]
input io_ptw_status_mpv, // @[TLB.scala:320:14]
input io_ptw_status_gva, // @[TLB.scala:320:14]
input io_ptw_status_tsr, // @[TLB.scala:320:14]
input io_ptw_status_tw, // @[TLB.scala:320:14]
input io_ptw_status_tvm, // @[TLB.scala:320:14]
input io_ptw_status_mxr, // @[TLB.scala:320:14]
input io_ptw_status_sum, // @[TLB.scala:320:14]
input io_ptw_status_mprv, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14]
input io_ptw_status_spp, // @[TLB.scala:320:14]
input io_ptw_status_mpie, // @[TLB.scala:320:14]
input io_ptw_status_spie, // @[TLB.scala:320:14]
input io_ptw_status_mie, // @[TLB.scala:320:14]
input io_ptw_status_sie, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_7_mask // @[TLB.scala:320:14]
);
wire [19:0] _entries_barrier_12_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_hr; // @[package.scala:267:25]
wire [19:0] _entries_barrier_11_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_10_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_9_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_8_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_7_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_6_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_io_y_c; // @[package.scala:267:25]
wire _pma_io_resp_r; // @[TLB.scala:422:19]
wire _pma_io_resp_w; // @[TLB.scala:422:19]
wire _pma_io_resp_pp; // @[TLB.scala:422:19]
wire _pma_io_resp_al; // @[TLB.scala:422:19]
wire _pma_io_resp_aa; // @[TLB.scala:422:19]
wire _pma_io_resp_x; // @[TLB.scala:422:19]
wire _pma_io_resp_eff; // @[TLB.scala:422:19]
wire _pmp_io_r; // @[TLB.scala:416:19]
wire _pmp_io_w; // @[TLB.scala:416:19]
wire _pmp_io_x; // @[TLB.scala:416:19]
wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25]
wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7]
wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7]
wire [1:0] io_req_bits_prv_0 = io_req_bits_prv; // @[TLB.scala:318:7]
wire io_req_bits_v_0 = io_req_bits_v; // @[TLB.scala:318:7]
wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7]
wire io_sfence_bits_rs1_0 = io_sfence_bits_rs1; // @[TLB.scala:318:7]
wire io_sfence_bits_rs2_0 = io_sfence_bits_rs2; // @[TLB.scala:318:7]
wire [38:0] io_sfence_bits_addr_0 = io_sfence_bits_addr; // @[TLB.scala:318:7]
wire io_sfence_bits_asid_0 = io_sfence_bits_asid; // @[TLB.scala:318:7]
wire io_sfence_bits_hv_0 = io_sfence_bits_hv; // @[TLB.scala:318:7]
wire io_sfence_bits_hg_0 = io_sfence_bits_hg; // @[TLB.scala:318:7]
wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7]
wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7]
wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7]
wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7]
wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7]
wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7]
wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7]
wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7]
wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7]
wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7]
wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7]
wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7]
wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7]
wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7]
wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7]
wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7]
wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7]
wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7]
wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7]
wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7]
wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7]
wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7]
wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7]
wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7]
wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7]
wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7]
wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7]
wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[TLB.scala:318:7]
wire io_req_bits_passthrough = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7]
wire io_resp_pf_st = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7]
wire io_resp_ae_st = 1'h0; // @[TLB.scala:318:7]
wire io_resp_ma_st = 1'h0; // @[TLB.scala:318:7]
wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7]
wire io_resp_must_alloc = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_mbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_sbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_sd_rv32 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_ube = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_upie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_hie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_uie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_spvp = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_spv = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_gva = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_debug = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_cease = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_wfi = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_dv = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_v = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sd = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mpv = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_gva = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tsr = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tw = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tvm = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mxr = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sum = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mprv = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_spp = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mpie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_ube = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_spie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_upie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_hie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_uie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[TLB.scala:318:7]
wire io_kill = 1'h0; // @[TLB.scala:318:7]
wire priv_v = 1'h0; // @[TLB.scala:369:34]
wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38]
wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68]
wire vstage1_en = 1'h0; // @[TLB.scala:376:48]
wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38]
wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68]
wire stage2_en = 1'h0; // @[TLB.scala:378:48]
wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52]
wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37]
wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78]
wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28]
wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34]
wire _superpage_hits_ignore_T_3 = 1'h0; // @[TLB.scala:182:28]
wire superpage_hits_ignore_3 = 1'h0; // @[TLB.scala:182:34]
wire _superpage_hits_ignore_T_6 = 1'h0; // @[TLB.scala:182:28]
wire superpage_hits_ignore_6 = 1'h0; // @[TLB.scala:182:34]
wire _superpage_hits_ignore_T_9 = 1'h0; // @[TLB.scala:182:28]
wire superpage_hits_ignore_9 = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T_6 = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore_6 = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T_9 = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore_9 = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T_12 = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore_12 = 1'h0; // @[TLB.scala:182:34]
wire refill_v = 1'h0; // @[TLB.scala:448:33]
wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24]
wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24]
wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84]
wire _waddr_T = 1'h0; // @[TLB.scala:477:45]
wire _mxr_T = 1'h0; // @[TLB.scala:518:36]
wire _cmd_lrsc_T = 1'h0; // @[package.scala:16:47]
wire _cmd_lrsc_T_1 = 1'h0; // @[package.scala:16:47]
wire _cmd_lrsc_T_2 = 1'h0; // @[package.scala:81:59]
wire cmd_lrsc = 1'h0; // @[TLB.scala:570:33]
wire _cmd_amo_logical_T = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_logical_T_1 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_logical_T_2 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_logical_T_3 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_logical_T_4 = 1'h0; // @[package.scala:81:59]
wire _cmd_amo_logical_T_5 = 1'h0; // @[package.scala:81:59]
wire _cmd_amo_logical_T_6 = 1'h0; // @[package.scala:81:59]
wire cmd_amo_logical = 1'h0; // @[TLB.scala:571:40]
wire _cmd_amo_arithmetic_T = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_1 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_2 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_3 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_4 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_5 = 1'h0; // @[package.scala:81:59]
wire _cmd_amo_arithmetic_T_6 = 1'h0; // @[package.scala:81:59]
wire _cmd_amo_arithmetic_T_7 = 1'h0; // @[package.scala:81:59]
wire _cmd_amo_arithmetic_T_8 = 1'h0; // @[package.scala:81:59]
wire cmd_amo_arithmetic = 1'h0; // @[TLB.scala:572:43]
wire cmd_put_partial = 1'h0; // @[TLB.scala:573:41]
wire _cmd_read_T_1 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_2 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_3 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_7 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_8 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_9 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_10 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_11 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_12 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_13 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_14 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_15 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_16 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_17 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_18 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_19 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_20 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_21 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_22 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_23 = 1'h0; // @[Consts.scala:87:44]
wire _cmd_readx_T = 1'h0; // @[TLB.scala:575:56]
wire cmd_readx = 1'h0; // @[TLB.scala:575:37]
wire _cmd_write_T = 1'h0; // @[Consts.scala:90:32]
wire _cmd_write_T_1 = 1'h0; // @[Consts.scala:90:49]
wire _cmd_write_T_2 = 1'h0; // @[Consts.scala:90:42]
wire _cmd_write_T_3 = 1'h0; // @[Consts.scala:90:66]
wire _cmd_write_T_4 = 1'h0; // @[Consts.scala:90:59]
wire _cmd_write_T_5 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_6 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_7 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_8 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_9 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_10 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_11 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_12 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_13 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_14 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_15 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_16 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_17 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_18 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_19 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_20 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_21 = 1'h0; // @[Consts.scala:87:44]
wire cmd_write = 1'h0; // @[Consts.scala:90:76]
wire _cmd_write_perms_T = 1'h0; // @[package.scala:16:47]
wire _cmd_write_perms_T_1 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_perms_T_2 = 1'h0; // @[package.scala:81:59]
wire cmd_write_perms = 1'h0; // @[TLB.scala:577:35]
wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32]
wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32]
wire _multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37]
wire _io_resp_pf_st_T = 1'h0; // @[TLB.scala:634:28]
wire _io_resp_pf_st_T_2 = 1'h0; // @[TLB.scala:634:72]
wire _io_resp_pf_st_T_3 = 1'h0; // @[TLB.scala:634:48]
wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29]
wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66]
wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42]
wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29]
wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73]
wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49]
wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56]
wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30]
wire _io_resp_ae_st_T_1 = 1'h0; // @[TLB.scala:642:41]
wire _io_resp_ma_st_T = 1'h0; // @[TLB.scala:646:31]
wire _io_resp_must_alloc_T_1 = 1'h0; // @[TLB.scala:649:51]
wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36]
wire hv = 1'h0; // @[TLB.scala:721:36]
wire hg = 1'h0; // @[TLB.scala:722:36]
wire hv_1 = 1'h0; // @[TLB.scala:721:36]
wire hg_1 = 1'h0; // @[TLB.scala:722:36]
wire hv_2 = 1'h0; // @[TLB.scala:721:36]
wire hg_2 = 1'h0; // @[TLB.scala:722:36]
wire hv_3 = 1'h0; // @[TLB.scala:721:36]
wire hg_3 = 1'h0; // @[TLB.scala:722:36]
wire hv_4 = 1'h0; // @[TLB.scala:721:36]
wire hg_4 = 1'h0; // @[TLB.scala:722:36]
wire hv_5 = 1'h0; // @[TLB.scala:721:36]
wire hg_5 = 1'h0; // @[TLB.scala:722:36]
wire hv_6 = 1'h0; // @[TLB.scala:721:36]
wire hg_6 = 1'h0; // @[TLB.scala:722:36]
wire hv_7 = 1'h0; // @[TLB.scala:721:36]
wire hg_7 = 1'h0; // @[TLB.scala:722:36]
wire hv_8 = 1'h0; // @[TLB.scala:721:36]
wire hg_8 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T = 1'h0; // @[TLB.scala:182:28]
wire ignore = 1'h0; // @[TLB.scala:182:34]
wire hv_9 = 1'h0; // @[TLB.scala:721:36]
wire hg_9 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28]
wire ignore_3 = 1'h0; // @[TLB.scala:182:34]
wire hv_10 = 1'h0; // @[TLB.scala:721:36]
wire hg_10 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T_6 = 1'h0; // @[TLB.scala:182:28]
wire ignore_6 = 1'h0; // @[TLB.scala:182:34]
wire hv_11 = 1'h0; // @[TLB.scala:721:36]
wire hg_11 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T_9 = 1'h0; // @[TLB.scala:182:28]
wire ignore_9 = 1'h0; // @[TLB.scala:182:34]
wire hv_12 = 1'h0; // @[TLB.scala:721:36]
wire hg_12 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T_12 = 1'h0; // @[TLB.scala:182:28]
wire ignore_12 = 1'h0; // @[TLB.scala:182:34]
wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[TLB.scala:318:7]
wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7]
wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7]
wire [15:0] satp_asid = 16'h0; // @[TLB.scala:373:17]
wire [31:0] io_ptw_status_isa = 32'h14112D; // @[TLB.scala:318:7]
wire [22:0] io_ptw_status_zero2 = 23'h0; // @[TLB.scala:318:7]
wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[TLB.scala:318:7]
wire [7:0] io_ptw_status_zero1 = 8'h0; // @[TLB.scala:318:7]
wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_xs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_vs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [2:0] io_req_bits_size = 3'h4; // @[TLB.scala:318:7]
wire [2:0] io_resp_size = 3'h4; // @[TLB.scala:318:7]
wire [4:0] io_req_bits_cmd = 5'h0; // @[TLB.scala:318:7]
wire [4:0] io_resp_cmd = 5'h0; // @[TLB.scala:318:7]
wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_valid = 1'h1; // @[TLB.scala:318:7]
wire _vm_enabled_T_2 = 1'h1; // @[TLB.scala:399:64]
wire _vsatp_mode_mismatch_T_2 = 1'h1; // @[TLB.scala:403:81]
wire _homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22]
wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40]
wire superpage_hits_ignore_5 = 1'h1; // @[TLB.scala:182:34]
wire _superpage_hits_T_27 = 1'h1; // @[TLB.scala:183:40]
wire superpage_hits_ignore_8 = 1'h1; // @[TLB.scala:182:34]
wire _superpage_hits_T_41 = 1'h1; // @[TLB.scala:183:40]
wire superpage_hits_ignore_11 = 1'h1; // @[TLB.scala:182:34]
wire _superpage_hits_T_55 = 1'h1; // @[TLB.scala:183:40]
wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire _hitsVec_T_61 = 1'h1; // @[TLB.scala:183:40]
wire hitsVec_ignore_5 = 1'h1; // @[TLB.scala:182:34]
wire _hitsVec_T_76 = 1'h1; // @[TLB.scala:183:40]
wire hitsVec_ignore_8 = 1'h1; // @[TLB.scala:182:34]
wire _hitsVec_T_91 = 1'h1; // @[TLB.scala:183:40]
wire hitsVec_ignore_11 = 1'h1; // @[TLB.scala:182:34]
wire _hitsVec_T_106 = 1'h1; // @[TLB.scala:183:40]
wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34]
wire ppn_ignore_3 = 1'h1; // @[TLB.scala:197:34]
wire ppn_ignore_5 = 1'h1; // @[TLB.scala:197:34]
wire ppn_ignore_7 = 1'h1; // @[TLB.scala:197:34]
wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42]
wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26]
wire _cmd_read_T = 1'h1; // @[package.scala:16:47]
wire _cmd_read_T_4 = 1'h1; // @[package.scala:81:59]
wire _cmd_read_T_5 = 1'h1; // @[package.scala:81:59]
wire _cmd_read_T_6 = 1'h1; // @[package.scala:81:59]
wire cmd_read = 1'h1; // @[Consts.scala:89:68]
wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107]
wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32]
wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20]
wire _io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28]
wire ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire ignore_5 = 1'h1; // @[TLB.scala:182:34]
wire ignore_8 = 1'h1; // @[TLB.scala:182:34]
wire ignore_11 = 1'h1; // @[TLB.scala:182:34]
wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7]
wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7]
wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7]
wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_sxl = 2'h2; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_uxl = 2'h2; // @[TLB.scala:318:7]
wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7]
wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7]
wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7]
wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[TLB.scala:318:7]
wire [13:0] _ae_array_T_2 = 14'h0; // @[TLB.scala:583:8]
wire [13:0] _ae_st_array_T_2 = 14'h0; // @[TLB.scala:588:8]
wire [13:0] _ae_st_array_T_4 = 14'h0; // @[TLB.scala:589:8]
wire [13:0] _ae_st_array_T_5 = 14'h0; // @[TLB.scala:588:53]
wire [13:0] _ae_st_array_T_7 = 14'h0; // @[TLB.scala:590:8]
wire [13:0] _ae_st_array_T_8 = 14'h0; // @[TLB.scala:589:53]
wire [13:0] _ae_st_array_T_10 = 14'h0; // @[TLB.scala:591:8]
wire [13:0] ae_st_array = 14'h0; // @[TLB.scala:590:53]
wire [13:0] _must_alloc_array_T_1 = 14'h0; // @[TLB.scala:593:8]
wire [13:0] _must_alloc_array_T_3 = 14'h0; // @[TLB.scala:594:8]
wire [13:0] _must_alloc_array_T_4 = 14'h0; // @[TLB.scala:593:43]
wire [13:0] _must_alloc_array_T_6 = 14'h0; // @[TLB.scala:595:8]
wire [13:0] _must_alloc_array_T_7 = 14'h0; // @[TLB.scala:594:43]
wire [13:0] _must_alloc_array_T_9 = 14'h0; // @[TLB.scala:596:8]
wire [13:0] must_alloc_array = 14'h0; // @[TLB.scala:595:46]
wire [13:0] pf_st_array = 14'h0; // @[TLB.scala:598:24]
wire [13:0] _gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46]
wire [13:0] gf_ld_array = 14'h0; // @[TLB.scala:600:24]
wire [13:0] _gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53]
wire [13:0] gf_st_array = 14'h0; // @[TLB.scala:601:24]
wire [13:0] _gf_inst_array_T = 14'h0; // @[TLB.scala:602:36]
wire [13:0] gf_inst_array = 14'h0; // @[TLB.scala:602:26]
wire [13:0] _io_resp_pf_st_T_1 = 14'h0; // @[TLB.scala:634:64]
wire [13:0] _io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58]
wire [13:0] _io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65]
wire [13:0] _io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48]
wire [13:0] _io_resp_ae_st_T = 14'h0; // @[TLB.scala:642:33]
wire [13:0] _io_resp_must_alloc_T = 14'h0; // @[TLB.scala:649:43]
wire [6:0] _state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25]
wire [12:0] stage2_bypass = 13'h1FFF; // @[TLB.scala:523:27]
wire [12:0] _hr_array_T_4 = 13'h1FFF; // @[TLB.scala:524:111]
wire [12:0] _hw_array_T_1 = 13'h1FFF; // @[TLB.scala:525:55]
wire [12:0] _hx_array_T_1 = 13'h1FFF; // @[TLB.scala:526:55]
wire [12:0] _gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:606:88]
wire [12:0] gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:606:82]
wire [12:0] _gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:607:16]
wire [12:0] gpa_hits = 13'h1FFF; // @[TLB.scala:607:14]
wire [12:0] _stage1_bypass_T = 13'h0; // @[TLB.scala:517:27]
wire [12:0] stage1_bypass = 13'h0; // @[TLB.scala:517:61]
wire [12:0] _gpa_hits_T = 13'h0; // @[TLB.scala:607:30]
wire [13:0] hr_array = 14'h3FFF; // @[TLB.scala:524:21]
wire [13:0] hw_array = 14'h3FFF; // @[TLB.scala:525:21]
wire [13:0] hx_array = 14'h3FFF; // @[TLB.scala:526:21]
wire [13:0] _must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19]
wire [13:0] _gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50]
wire [7:0] _misaligned_T_2 = 8'hF; // @[TLB.scala:550:69]
wire [8:0] _misaligned_T_1 = 9'hF; // @[TLB.scala:550:69]
wire [7:0] _misaligned_T = 8'h10; // @[OneHot.scala:58:35]
wire _io_req_ready_T; // @[TLB.scala:631:25]
wire _io_resp_miss_T_2; // @[TLB.scala:651:64]
wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23]
wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8]
wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41]
wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29]
wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41]
wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41]
wire _io_resp_ma_ld_T; // @[TLB.scala:645:31]
wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41]
wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59]
wire _io_ptw_req_valid_T; // @[TLB.scala:662:29]
wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29]
wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24]
wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13]
wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17]
wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17]
wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31]
wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16]
wire io_req_ready; // @[TLB.scala:318:7]
wire io_resp_pf_ld_0; // @[TLB.scala:318:7]
wire io_resp_pf_inst_0; // @[TLB.scala:318:7]
wire io_resp_ae_ld_0; // @[TLB.scala:318:7]
wire io_resp_ae_inst_0; // @[TLB.scala:318:7]
wire io_resp_ma_ld_0; // @[TLB.scala:318:7]
wire io_resp_miss_0; // @[TLB.scala:318:7]
wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7]
wire [39:0] io_resp_gpa_0; // @[TLB.scala:318:7]
wire io_resp_cacheable_0; // @[TLB.scala:318:7]
wire io_resp_prefetchable_0; // @[TLB.scala:318:7]
wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7]
wire io_ptw_req_valid_0; // @[TLB.scala:318:7]
wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30]
wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] _ppn_T_13 = vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] _ppn_T_21 = vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] _ppn_T_29 = vpn; // @[TLB.scala:198:28, :335:30]
reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_0_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_0_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_0_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_0_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_0_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_0_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_1_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_1_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_1_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_1_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_1_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_1_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_1_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_2_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_2_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_2_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_2_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_2_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_2_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_2_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_3_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_3_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_3_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_3_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_3_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_3_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_3_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_4_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_4_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_4_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_4_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_4_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_4_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_4_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_4_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_4_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_4_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_4_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_5_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_5_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_5_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_5_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_5_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_5_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_5_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_5_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_5_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_5_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_5_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_6_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_6_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_6_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_6_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_6_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_6_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_6_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_6_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_6_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_6_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_6_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_7_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_7_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_7_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_7_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_7_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_7_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_7_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_7_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_7_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_7_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_7_valid_3; // @[TLB.scala:339:29]
reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30]
reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30]
reg superpage_entries_0_tag_v; // @[TLB.scala:341:30]
reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30]
wire [41:0] _entries_WIRE_17 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30]
reg superpage_entries_0_valid_0; // @[TLB.scala:341:30]
reg [1:0] superpage_entries_1_level; // @[TLB.scala:341:30]
reg [26:0] superpage_entries_1_tag_vpn; // @[TLB.scala:341:30]
reg superpage_entries_1_tag_v; // @[TLB.scala:341:30]
reg [41:0] superpage_entries_1_data_0; // @[TLB.scala:341:30]
wire [41:0] _entries_WIRE_19 = superpage_entries_1_data_0; // @[TLB.scala:170:77, :341:30]
reg superpage_entries_1_valid_0; // @[TLB.scala:341:30]
reg [1:0] superpage_entries_2_level; // @[TLB.scala:341:30]
reg [26:0] superpage_entries_2_tag_vpn; // @[TLB.scala:341:30]
reg superpage_entries_2_tag_v; // @[TLB.scala:341:30]
reg [41:0] superpage_entries_2_data_0; // @[TLB.scala:341:30]
wire [41:0] _entries_WIRE_21 = superpage_entries_2_data_0; // @[TLB.scala:170:77, :341:30]
reg superpage_entries_2_valid_0; // @[TLB.scala:341:30]
reg [1:0] superpage_entries_3_level; // @[TLB.scala:341:30]
reg [26:0] superpage_entries_3_tag_vpn; // @[TLB.scala:341:30]
reg superpage_entries_3_tag_v; // @[TLB.scala:341:30]
reg [41:0] superpage_entries_3_data_0; // @[TLB.scala:341:30]
wire [41:0] _entries_WIRE_23 = superpage_entries_3_data_0; // @[TLB.scala:170:77, :341:30]
reg superpage_entries_3_valid_0; // @[TLB.scala:341:30]
reg [1:0] special_entry_level; // @[TLB.scala:346:56]
reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56]
reg special_entry_tag_v; // @[TLB.scala:346:56]
reg [41:0] special_entry_data_0; // @[TLB.scala:346:56]
wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56]
wire [41:0] _entries_WIRE_25 = special_entry_data_0; // @[TLB.scala:170:77, :346:56]
reg special_entry_valid_0; // @[TLB.scala:346:56]
reg [1:0] state; // @[TLB.scala:352:22]
reg [26:0] r_refill_tag; // @[TLB.scala:354:25]
assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25]
reg [1:0] r_superpage_repl_addr; // @[TLB.scala:355:34]
wire [1:0] waddr = r_superpage_repl_addr; // @[TLB.scala:355:34, :477:22]
reg [2:0] r_sectored_repl_addr; // @[TLB.scala:356:33]
reg r_sectored_hit_valid; // @[TLB.scala:357:27]
reg [2:0] r_sectored_hit_bits; // @[TLB.scala:357:27]
reg r_superpage_hit_valid; // @[TLB.scala:358:28]
reg [1:0] r_superpage_hit_bits; // @[TLB.scala:358:28]
reg r_need_gpa; // @[TLB.scala:361:23]
assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23]
reg r_gpa_valid; // @[TLB.scala:362:24]
reg [38:0] r_gpa; // @[TLB.scala:363:18]
reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22]
reg r_gpa_is_pte; // @[TLB.scala:365:25]
wire priv_s = io_req_bits_prv_0[0]; // @[TLB.scala:318:7, :370:20]
wire priv_uses_vm = ~(io_req_bits_prv_0[1]); // @[TLB.scala:318:7, :372:27]
wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41]
wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}]
wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31]
wire _vm_enabled_T_1 = _vm_enabled_T & priv_uses_vm; // @[TLB.scala:372:27, :399:{31,45}]
wire vm_enabled = _vm_enabled_T_1; // @[TLB.scala:399:{45,61}]
wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32]
wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29]
wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44]
wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24]
wire _mpu_priv_T = do_refill; // @[TLB.scala:408:29, :415:52]
wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29]
wire _T_51 = state == 2'h1; // @[package.scala:16:47]
wire _invalidate_refill_T; // @[package.scala:16:47]
assign _invalidate_refill_T = _T_51; // @[package.scala:16:47]
assign _io_ptw_req_valid_T = _T_51; // @[package.scala:16:47]
wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47]
wire _invalidate_refill_T_2 = _invalidate_refill_T | _invalidate_refill_T_1; // @[package.scala:16:47, :81:59]
wire invalidate_refill = _invalidate_refill_T_2 | io_sfence_valid_0; // @[package.scala:81:59]
wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77]
wire _mpu_ppn_T_22; // @[TLB.scala:170:77]
wire _mpu_ppn_T_21; // @[TLB.scala:170:77]
wire _mpu_ppn_T_20; // @[TLB.scala:170:77]
wire _mpu_ppn_T_19; // @[TLB.scala:170:77]
wire _mpu_ppn_T_18; // @[TLB.scala:170:77]
wire _mpu_ppn_T_17; // @[TLB.scala:170:77]
wire _mpu_ppn_T_16; // @[TLB.scala:170:77]
wire _mpu_ppn_T_15; // @[TLB.scala:170:77]
wire _mpu_ppn_T_14; // @[TLB.scala:170:77]
wire _mpu_ppn_T_13; // @[TLB.scala:170:77]
wire _mpu_ppn_T_12; // @[TLB.scala:170:77]
wire _mpu_ppn_T_11; // @[TLB.scala:170:77]
wire _mpu_ppn_T_10; // @[TLB.scala:170:77]
wire _mpu_ppn_T_9; // @[TLB.scala:170:77]
wire _mpu_ppn_T_8; // @[TLB.scala:170:77]
wire _mpu_ppn_T_7; // @[TLB.scala:170:77]
wire _mpu_ppn_T_6; // @[TLB.scala:170:77]
wire _mpu_ppn_T_5; // @[TLB.scala:170:77]
wire _mpu_ppn_T_4; // @[TLB.scala:170:77]
wire _mpu_ppn_T_3; // @[TLB.scala:170:77]
wire _mpu_ppn_T_2; // @[TLB.scala:170:77]
wire _mpu_ppn_T_1; // @[TLB.scala:170:77]
assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77]
assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77]
assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77]
assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77]
assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77]
assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77]
assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77]
assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77]
assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77]
assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77]
assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77]
assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77]
assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77]
assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77]
assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77]
assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77]
assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77]
assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77]
assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77]
assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77]
assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77]
assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77]
assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77]
wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77]
wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25]
wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56]
wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28]
assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28]
wire _hitsVec_ignore_T_13; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28]
wire _ppn_ignore_T_8; // @[TLB.scala:197:28]
assign _ppn_ignore_T_8 = _GEN; // @[TLB.scala:197:28]
wire _ignore_T_13; // @[TLB.scala:182:28]
assign _ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28]
wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}]
wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}]
wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56]
wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}]
wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}]
wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146]
wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}]
wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20]
wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52]
wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46]
wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82]
wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}]
wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_67 = mpu_physaddr; // @[TLB.scala:414:25]
wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25]
wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}]
wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, io_req_bits_prv_0}; // @[TLB.scala:318:7, :415:103]
wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}]
wire cacheable; // @[TLB.scala:425:41]
wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24]
wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46]
wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_50 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65]
wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31]
assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31]
assign _homogeneous_T_72 = _GEN_0; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46]
wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31]
assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_60; // @[Parameters.scala:137:31]
assign _homogeneous_T_60 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_77; // @[Parameters.scala:137:31]
assign _homogeneous_T_77 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31]
assign _homogeneous_T_109 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_116; // @[Parameters.scala:137:31]
assign _homogeneous_T_116 = _GEN_1; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46]
wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46]
wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46]
wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46]
wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_30; // @[Parameters.scala:137:31]
assign _homogeneous_T_30 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_82; // @[Parameters.scala:137:31]
assign _homogeneous_T_82 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_97; // @[Parameters.scala:137:31]
assign _homogeneous_T_97 = _GEN_2; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46]
wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46]
wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_40 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46]
wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15]
wire [39:0] _homogeneous_T_45; // @[Parameters.scala:137:31]
assign _homogeneous_T_45 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_87; // @[Parameters.scala:137:31]
assign _homogeneous_T_87 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_102; // @[Parameters.scala:137:31]
assign _homogeneous_T_102 = _GEN_3; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46]
wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_51 = _homogeneous_T_50 | _homogeneous_T_9; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_52 = _homogeneous_T_51 | _homogeneous_T_14; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_53 = _homogeneous_T_52 | _homogeneous_T_19; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_54 = _homogeneous_T_53 | _homogeneous_T_24; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_55 = _homogeneous_T_54 | _homogeneous_T_29; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_56 = _homogeneous_T_55 | _homogeneous_T_34; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_57 = _homogeneous_T_56 | _homogeneous_T_39; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_58 = _homogeneous_T_57 | _homogeneous_T_44; // @[TLBPermissions.scala:101:65]
wire homogeneous = _homogeneous_T_58 | _homogeneous_T_49; // @[TLBPermissions.scala:101:65]
wire [40:0] _homogeneous_T_61 = {1'h0, _homogeneous_T_60}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_62 = _homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_63 = _homogeneous_T_62; // @[Parameters.scala:137:46]
wire _homogeneous_T_64 = _homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_65 = _homogeneous_T_64; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_66 = ~_homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}]
wire [40:0] _homogeneous_T_68 = {1'h0, _homogeneous_T_67}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_69 = _homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_70 = _homogeneous_T_69; // @[Parameters.scala:137:46]
wire _homogeneous_T_71 = _homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_92 = _homogeneous_T_71; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46]
wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _homogeneous_T_78 = {1'h0, _homogeneous_T_77}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_79 = _homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_80 = _homogeneous_T_79; // @[Parameters.scala:137:46]
wire _homogeneous_T_81 = _homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _homogeneous_T_83 = {1'h0, _homogeneous_T_82}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_84 = _homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_85 = _homogeneous_T_84; // @[Parameters.scala:137:46]
wire _homogeneous_T_86 = _homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _homogeneous_T_88 = {1'h0, _homogeneous_T_87}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_89 = _homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_90 = _homogeneous_T_89; // @[Parameters.scala:137:46]
wire _homogeneous_T_91 = _homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_93 = _homogeneous_T_92 | _homogeneous_T_76; // @[TLBPermissions.scala:85:66]
wire _homogeneous_T_94 = _homogeneous_T_93 | _homogeneous_T_81; // @[TLBPermissions.scala:85:66]
wire _homogeneous_T_95 = _homogeneous_T_94 | _homogeneous_T_86; // @[TLBPermissions.scala:85:66]
wire _homogeneous_T_96 = _homogeneous_T_95 | _homogeneous_T_91; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_98 = {1'h0, _homogeneous_T_97}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_99 = _homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_100 = _homogeneous_T_99; // @[Parameters.scala:137:46]
wire _homogeneous_T_101 = _homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_107 = _homogeneous_T_101; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_103 = {1'h0, _homogeneous_T_102}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_104 = _homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_105 = _homogeneous_T_104; // @[Parameters.scala:137:46]
wire _homogeneous_T_106 = _homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_108 = _homogeneous_T_107 | _homogeneous_T_106; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46]
wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_114 = _homogeneous_T_113; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_115 = ~_homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}]
wire [40:0] _homogeneous_T_117 = {1'h0, _homogeneous_T_116}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_118 = _homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_119 = _homogeneous_T_118; // @[Parameters.scala:137:46]
wire _homogeneous_T_120 = _homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_121 = _homogeneous_T_120; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_122 = ~_homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}]
wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39]
wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46]
wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}]
wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33]
wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}]
wire prot_r = _prot_r_T_1 & _pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}]
wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24]
wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33]
wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}]
wire prot_w = _prot_w_T_1 & _pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}]
wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24]
wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33]
wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}]
wire prot_x = _prot_x_T_1 & _pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}]
wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24]
wire _GEN_4 = sectored_entries_0_0_valid_0 | sectored_entries_0_0_valid_1; // @[package.scala:81:59]
wire _sector_hits_T; // @[package.scala:81:59]
assign _sector_hits_T = _GEN_4; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T = _GEN_4; // @[package.scala:81:59]
wire _sector_hits_T_1 = _sector_hits_T | sectored_entries_0_0_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_2 = _sector_hits_T_1 | sectored_entries_0_0_valid_3; // @[package.scala:81:59]
wire [26:0] _T_176 = sectored_entries_0_0_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_3; // @[TLB.scala:174:61]
assign _sector_hits_T_3 = _T_176; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T; // @[TLB.scala:174:61]
assign _hitsVec_T = _T_176; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_4 = _sector_hits_T_3[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_5 = _sector_hits_T_4 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_6 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_7 = _sector_hits_T_5 & _sector_hits_T_6; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_0 = _sector_hits_T_2 & _sector_hits_T_7; // @[package.scala:81:59]
wire _GEN_5 = sectored_entries_0_1_valid_0 | sectored_entries_0_1_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_8; // @[package.scala:81:59]
assign _sector_hits_T_8 = _GEN_5; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_3; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_3 = _GEN_5; // @[package.scala:81:59]
wire _sector_hits_T_9 = _sector_hits_T_8 | sectored_entries_0_1_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_10 = _sector_hits_T_9 | sectored_entries_0_1_valid_3; // @[package.scala:81:59]
wire [26:0] _T_597 = sectored_entries_0_1_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_11; // @[TLB.scala:174:61]
assign _sector_hits_T_11 = _T_597; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_6; // @[TLB.scala:174:61]
assign _hitsVec_T_6 = _T_597; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_12 = _sector_hits_T_11[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_13 = _sector_hits_T_12 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_14 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_15 = _sector_hits_T_13 & _sector_hits_T_14; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_1 = _sector_hits_T_10 & _sector_hits_T_15; // @[package.scala:81:59]
wire _GEN_6 = sectored_entries_0_2_valid_0 | sectored_entries_0_2_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_16; // @[package.scala:81:59]
assign _sector_hits_T_16 = _GEN_6; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_6; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_6 = _GEN_6; // @[package.scala:81:59]
wire _sector_hits_T_17 = _sector_hits_T_16 | sectored_entries_0_2_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_18 = _sector_hits_T_17 | sectored_entries_0_2_valid_3; // @[package.scala:81:59]
wire [26:0] _T_1018 = sectored_entries_0_2_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_19; // @[TLB.scala:174:61]
assign _sector_hits_T_19 = _T_1018; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_12; // @[TLB.scala:174:61]
assign _hitsVec_T_12 = _T_1018; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_20 = _sector_hits_T_19[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_21 = _sector_hits_T_20 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_22 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_23 = _sector_hits_T_21 & _sector_hits_T_22; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_2 = _sector_hits_T_18 & _sector_hits_T_23; // @[package.scala:81:59]
wire _GEN_7 = sectored_entries_0_3_valid_0 | sectored_entries_0_3_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_24; // @[package.scala:81:59]
assign _sector_hits_T_24 = _GEN_7; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_9; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_9 = _GEN_7; // @[package.scala:81:59]
wire _sector_hits_T_25 = _sector_hits_T_24 | sectored_entries_0_3_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_26 = _sector_hits_T_25 | sectored_entries_0_3_valid_3; // @[package.scala:81:59]
wire [26:0] _T_1439 = sectored_entries_0_3_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_27; // @[TLB.scala:174:61]
assign _sector_hits_T_27 = _T_1439; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_18; // @[TLB.scala:174:61]
assign _hitsVec_T_18 = _T_1439; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_28 = _sector_hits_T_27[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_29 = _sector_hits_T_28 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_30 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_31 = _sector_hits_T_29 & _sector_hits_T_30; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_3 = _sector_hits_T_26 & _sector_hits_T_31; // @[package.scala:81:59]
wire _GEN_8 = sectored_entries_0_4_valid_0 | sectored_entries_0_4_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_32; // @[package.scala:81:59]
assign _sector_hits_T_32 = _GEN_8; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_12; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_12 = _GEN_8; // @[package.scala:81:59]
wire _sector_hits_T_33 = _sector_hits_T_32 | sectored_entries_0_4_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_34 = _sector_hits_T_33 | sectored_entries_0_4_valid_3; // @[package.scala:81:59]
wire [26:0] _T_1860 = sectored_entries_0_4_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_35; // @[TLB.scala:174:61]
assign _sector_hits_T_35 = _T_1860; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_24; // @[TLB.scala:174:61]
assign _hitsVec_T_24 = _T_1860; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_36 = _sector_hits_T_35[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_37 = _sector_hits_T_36 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_38 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_39 = _sector_hits_T_37 & _sector_hits_T_38; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_4 = _sector_hits_T_34 & _sector_hits_T_39; // @[package.scala:81:59]
wire _GEN_9 = sectored_entries_0_5_valid_0 | sectored_entries_0_5_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_40; // @[package.scala:81:59]
assign _sector_hits_T_40 = _GEN_9; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_15; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_15 = _GEN_9; // @[package.scala:81:59]
wire _sector_hits_T_41 = _sector_hits_T_40 | sectored_entries_0_5_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_42 = _sector_hits_T_41 | sectored_entries_0_5_valid_3; // @[package.scala:81:59]
wire [26:0] _T_2281 = sectored_entries_0_5_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_43; // @[TLB.scala:174:61]
assign _sector_hits_T_43 = _T_2281; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_30; // @[TLB.scala:174:61]
assign _hitsVec_T_30 = _T_2281; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_44 = _sector_hits_T_43[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_45 = _sector_hits_T_44 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_46 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_47 = _sector_hits_T_45 & _sector_hits_T_46; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_5 = _sector_hits_T_42 & _sector_hits_T_47; // @[package.scala:81:59]
wire _GEN_10 = sectored_entries_0_6_valid_0 | sectored_entries_0_6_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_48; // @[package.scala:81:59]
assign _sector_hits_T_48 = _GEN_10; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_18; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_18 = _GEN_10; // @[package.scala:81:59]
wire _sector_hits_T_49 = _sector_hits_T_48 | sectored_entries_0_6_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_50 = _sector_hits_T_49 | sectored_entries_0_6_valid_3; // @[package.scala:81:59]
wire [26:0] _T_2702 = sectored_entries_0_6_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_51; // @[TLB.scala:174:61]
assign _sector_hits_T_51 = _T_2702; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_36; // @[TLB.scala:174:61]
assign _hitsVec_T_36 = _T_2702; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_52 = _sector_hits_T_51[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_53 = _sector_hits_T_52 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_54 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_55 = _sector_hits_T_53 & _sector_hits_T_54; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_6 = _sector_hits_T_50 & _sector_hits_T_55; // @[package.scala:81:59]
wire _GEN_11 = sectored_entries_0_7_valid_0 | sectored_entries_0_7_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_56; // @[package.scala:81:59]
assign _sector_hits_T_56 = _GEN_11; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_21; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_21 = _GEN_11; // @[package.scala:81:59]
wire _sector_hits_T_57 = _sector_hits_T_56 | sectored_entries_0_7_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_58 = _sector_hits_T_57 | sectored_entries_0_7_valid_3; // @[package.scala:81:59]
wire [26:0] _T_3123 = sectored_entries_0_7_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_59; // @[TLB.scala:174:61]
assign _sector_hits_T_59 = _T_3123; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_42; // @[TLB.scala:174:61]
assign _hitsVec_T_42 = _T_3123; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_60 = _sector_hits_T_59[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_61 = _sector_hits_T_60 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_62 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_63 = _sector_hits_T_61 & _sector_hits_T_62; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_7 = _sector_hits_T_58 & _sector_hits_T_63; // @[package.scala:81:59]
wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30]
wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30]
wire [26:0] _T_3446 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30]
wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52]
assign _superpage_hits_T = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52]
assign _superpage_hits_T_5 = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52]
assign _superpage_hits_T_10 = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_48; // @[TLB.scala:183:52]
assign _hitsVec_T_48 = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_53; // @[TLB.scala:183:52]
assign _hitsVec_T_53 = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_58; // @[TLB.scala:183:52]
assign _hitsVec_T_58 = _T_3446; // @[TLB.scala:183:52]
wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}]
wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}]
wire _GEN_12 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30]
wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28]
assign _superpage_hits_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28]
wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28]
wire _ppn_ignore_T; // @[TLB.scala:197:28]
assign _ppn_ignore_T = _GEN_12; // @[TLB.scala:182:28, :197:28]
wire _ignore_T_1; // @[TLB.scala:182:28]
assign _ignore_T_1 = _GEN_12; // @[TLB.scala:182:28]
wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}]
wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_8 = superpage_hits_ignore_1 | _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}]
wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}]
wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29]
wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30]
wire superpage_hits_tagMatch_1 = superpage_entries_1_valid_0 & _superpage_hits_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30]
wire [26:0] _T_3544 = superpage_entries_1_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30]
wire [26:0] _superpage_hits_T_14; // @[TLB.scala:183:52]
assign _superpage_hits_T_14 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_19; // @[TLB.scala:183:52]
assign _superpage_hits_T_19 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_24; // @[TLB.scala:183:52]
assign _superpage_hits_T_24 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_63; // @[TLB.scala:183:52]
assign _hitsVec_T_63 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_68; // @[TLB.scala:183:52]
assign _hitsVec_T_68 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_73; // @[TLB.scala:183:52]
assign _hitsVec_T_73 = _T_3544; // @[TLB.scala:183:52]
wire [8:0] _superpage_hits_T_15 = _superpage_hits_T_14[26:18]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_16 = _superpage_hits_T_15 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_17 = _superpage_hits_T_16; // @[TLB.scala:183:{40,79}]
wire _superpage_hits_T_18 = superpage_hits_tagMatch_1 & _superpage_hits_T_17; // @[TLB.scala:178:33, :183:{29,40}]
wire _GEN_13 = superpage_entries_1_level == 2'h0; // @[TLB.scala:182:28, :341:30]
wire _superpage_hits_ignore_T_4; // @[TLB.scala:182:28]
assign _superpage_hits_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28]
wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28]
wire _ppn_ignore_T_2; // @[TLB.scala:197:28]
assign _ppn_ignore_T_2 = _GEN_13; // @[TLB.scala:182:28, :197:28]
wire _ignore_T_4; // @[TLB.scala:182:28]
assign _ignore_T_4 = _GEN_13; // @[TLB.scala:182:28]
wire superpage_hits_ignore_4 = _superpage_hits_ignore_T_4; // @[TLB.scala:182:{28,34}]
wire [8:0] _superpage_hits_T_20 = _superpage_hits_T_19[17:9]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_21 = _superpage_hits_T_20 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_22 = superpage_hits_ignore_4 | _superpage_hits_T_21; // @[TLB.scala:182:34, :183:{40,79}]
wire _superpage_hits_T_23 = _superpage_hits_T_18 & _superpage_hits_T_22; // @[TLB.scala:183:{29,40}]
wire superpage_hits_1 = _superpage_hits_T_23; // @[TLB.scala:183:29]
wire _superpage_hits_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _superpage_hits_T_25 = _superpage_hits_T_24[8:0]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_26 = _superpage_hits_T_25 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30]
wire superpage_hits_tagMatch_2 = superpage_entries_2_valid_0 & _superpage_hits_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30]
wire [26:0] _T_3642 = superpage_entries_2_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30]
wire [26:0] _superpage_hits_T_28; // @[TLB.scala:183:52]
assign _superpage_hits_T_28 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_33; // @[TLB.scala:183:52]
assign _superpage_hits_T_33 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_38; // @[TLB.scala:183:52]
assign _superpage_hits_T_38 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_78; // @[TLB.scala:183:52]
assign _hitsVec_T_78 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_83; // @[TLB.scala:183:52]
assign _hitsVec_T_83 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_88; // @[TLB.scala:183:52]
assign _hitsVec_T_88 = _T_3642; // @[TLB.scala:183:52]
wire [8:0] _superpage_hits_T_29 = _superpage_hits_T_28[26:18]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_30 = _superpage_hits_T_29 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_31 = _superpage_hits_T_30; // @[TLB.scala:183:{40,79}]
wire _superpage_hits_T_32 = superpage_hits_tagMatch_2 & _superpage_hits_T_31; // @[TLB.scala:178:33, :183:{29,40}]
wire _GEN_14 = superpage_entries_2_level == 2'h0; // @[TLB.scala:182:28, :341:30]
wire _superpage_hits_ignore_T_7; // @[TLB.scala:182:28]
assign _superpage_hits_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28]
wire _hitsVec_ignore_T_7; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28]
wire _ppn_ignore_T_4; // @[TLB.scala:197:28]
assign _ppn_ignore_T_4 = _GEN_14; // @[TLB.scala:182:28, :197:28]
wire _ignore_T_7; // @[TLB.scala:182:28]
assign _ignore_T_7 = _GEN_14; // @[TLB.scala:182:28]
wire superpage_hits_ignore_7 = _superpage_hits_ignore_T_7; // @[TLB.scala:182:{28,34}]
wire [8:0] _superpage_hits_T_34 = _superpage_hits_T_33[17:9]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_35 = _superpage_hits_T_34 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_36 = superpage_hits_ignore_7 | _superpage_hits_T_35; // @[TLB.scala:182:34, :183:{40,79}]
wire _superpage_hits_T_37 = _superpage_hits_T_32 & _superpage_hits_T_36; // @[TLB.scala:183:{29,40}]
wire superpage_hits_2 = _superpage_hits_T_37; // @[TLB.scala:183:29]
wire _superpage_hits_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _superpage_hits_T_39 = _superpage_hits_T_38[8:0]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_40 = _superpage_hits_T_39 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30]
wire superpage_hits_tagMatch_3 = superpage_entries_3_valid_0 & _superpage_hits_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30]
wire [26:0] _T_3740 = superpage_entries_3_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30]
wire [26:0] _superpage_hits_T_42; // @[TLB.scala:183:52]
assign _superpage_hits_T_42 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_47; // @[TLB.scala:183:52]
assign _superpage_hits_T_47 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_52; // @[TLB.scala:183:52]
assign _superpage_hits_T_52 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_93; // @[TLB.scala:183:52]
assign _hitsVec_T_93 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_98; // @[TLB.scala:183:52]
assign _hitsVec_T_98 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_103; // @[TLB.scala:183:52]
assign _hitsVec_T_103 = _T_3740; // @[TLB.scala:183:52]
wire [8:0] _superpage_hits_T_43 = _superpage_hits_T_42[26:18]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_44 = _superpage_hits_T_43 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_45 = _superpage_hits_T_44; // @[TLB.scala:183:{40,79}]
wire _superpage_hits_T_46 = superpage_hits_tagMatch_3 & _superpage_hits_T_45; // @[TLB.scala:178:33, :183:{29,40}]
wire _GEN_15 = superpage_entries_3_level == 2'h0; // @[TLB.scala:182:28, :341:30]
wire _superpage_hits_ignore_T_10; // @[TLB.scala:182:28]
assign _superpage_hits_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28]
wire _hitsVec_ignore_T_10; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28]
wire _ppn_ignore_T_6; // @[TLB.scala:197:28]
assign _ppn_ignore_T_6 = _GEN_15; // @[TLB.scala:182:28, :197:28]
wire _ignore_T_10; // @[TLB.scala:182:28]
assign _ignore_T_10 = _GEN_15; // @[TLB.scala:182:28]
wire superpage_hits_ignore_10 = _superpage_hits_ignore_T_10; // @[TLB.scala:182:{28,34}]
wire [8:0] _superpage_hits_T_48 = _superpage_hits_T_47[17:9]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_49 = _superpage_hits_T_48 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_50 = superpage_hits_ignore_10 | _superpage_hits_T_49; // @[TLB.scala:182:34, :183:{40,79}]
wire _superpage_hits_T_51 = _superpage_hits_T_46 & _superpage_hits_T_50; // @[TLB.scala:183:{29,40}]
wire superpage_hits_3 = _superpage_hits_T_51; // @[TLB.scala:183:29]
wire _superpage_hits_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _superpage_hits_T_53 = _superpage_hits_T_52[8:0]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_54 = _superpage_hits_T_53 == 9'h0; // @[TLB.scala:183:{58,79}]
wire [1:0] hitsVec_idx = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_1 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_2 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_3 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_4 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_5 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_6 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_7 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_24 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_48 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_72 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_96 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_120 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_144 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_168 = vpn[1:0]; // @[package.scala:163:13]
wire [24:0] _hitsVec_T_1 = _hitsVec_T[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_2 = _hitsVec_T_1 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_3 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_16 = {{sectored_entries_0_0_valid_3}, {sectored_entries_0_0_valid_2}, {sectored_entries_0_0_valid_1}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_5 = _GEN_16[hitsVec_idx] & _hitsVec_T_4; // @[package.scala:163:13]
wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_7 = _hitsVec_T_6[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_8 = _hitsVec_T_7 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_9 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_17 = {{sectored_entries_0_1_valid_3}, {sectored_entries_0_1_valid_2}, {sectored_entries_0_1_valid_1}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_11 = _GEN_17[hitsVec_idx_1] & _hitsVec_T_10; // @[package.scala:163:13]
wire hitsVec_1 = vm_enabled & _hitsVec_T_11; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_13 = _hitsVec_T_12[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_14 = _hitsVec_T_13 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_15 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_18 = {{sectored_entries_0_2_valid_3}, {sectored_entries_0_2_valid_2}, {sectored_entries_0_2_valid_1}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_17 = _GEN_18[hitsVec_idx_2] & _hitsVec_T_16; // @[package.scala:163:13]
wire hitsVec_2 = vm_enabled & _hitsVec_T_17; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_19 = _hitsVec_T_18[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_20 = _hitsVec_T_19 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_21 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_19 = {{sectored_entries_0_3_valid_3}, {sectored_entries_0_3_valid_2}, {sectored_entries_0_3_valid_1}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_23 = _GEN_19[hitsVec_idx_3] & _hitsVec_T_22; // @[package.scala:163:13]
wire hitsVec_3 = vm_enabled & _hitsVec_T_23; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_25 = _hitsVec_T_24[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_26 = _hitsVec_T_25 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_27 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_28 = _hitsVec_T_26 & _hitsVec_T_27; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_20 = {{sectored_entries_0_4_valid_3}, {sectored_entries_0_4_valid_2}, {sectored_entries_0_4_valid_1}, {sectored_entries_0_4_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_29 = _GEN_20[hitsVec_idx_4] & _hitsVec_T_28; // @[package.scala:163:13]
wire hitsVec_4 = vm_enabled & _hitsVec_T_29; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_31 = _hitsVec_T_30[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_32 = _hitsVec_T_31 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_33 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_34 = _hitsVec_T_32 & _hitsVec_T_33; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_21 = {{sectored_entries_0_5_valid_3}, {sectored_entries_0_5_valid_2}, {sectored_entries_0_5_valid_1}, {sectored_entries_0_5_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_35 = _GEN_21[hitsVec_idx_5] & _hitsVec_T_34; // @[package.scala:163:13]
wire hitsVec_5 = vm_enabled & _hitsVec_T_35; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_37 = _hitsVec_T_36[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_38 = _hitsVec_T_37 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_39 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_40 = _hitsVec_T_38 & _hitsVec_T_39; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_22 = {{sectored_entries_0_6_valid_3}, {sectored_entries_0_6_valid_2}, {sectored_entries_0_6_valid_1}, {sectored_entries_0_6_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_41 = _GEN_22[hitsVec_idx_6] & _hitsVec_T_40; // @[package.scala:163:13]
wire hitsVec_6 = vm_enabled & _hitsVec_T_41; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_43 = _hitsVec_T_42[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_44 = _hitsVec_T_43 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_45 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_46 = _hitsVec_T_44 & _hitsVec_T_45; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_23 = {{sectored_entries_0_7_valid_3}, {sectored_entries_0_7_valid_2}, {sectored_entries_0_7_valid_1}, {sectored_entries_0_7_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_47 = _GEN_23[hitsVec_idx_7] & _hitsVec_T_46; // @[package.scala:163:13]
wire hitsVec_7 = vm_enabled & _hitsVec_T_47; // @[TLB.scala:188:18, :399:61, :440:44]
wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30]
wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30]
wire [8:0] _hitsVec_T_49 = _hitsVec_T_48[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_50 = _hitsVec_T_49 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_51 = _hitsVec_T_50; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_52 = hitsVec_tagMatch & _hitsVec_T_51; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_54 = _hitsVec_T_53[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_55 = _hitsVec_T_54 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_56 = hitsVec_ignore_1 | _hitsVec_T_55; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_57 = _hitsVec_T_52 & _hitsVec_T_56; // @[TLB.scala:183:{29,40}]
wire _hitsVec_T_62 = _hitsVec_T_57; // @[TLB.scala:183:29]
wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _hitsVec_T_59 = _hitsVec_T_58[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_60 = _hitsVec_T_59 == 9'h0; // @[TLB.scala:183:{58,79}]
wire hitsVec_8 = vm_enabled & _hitsVec_T_62; // @[TLB.scala:183:29, :399:61, :440:44]
wire _hitsVec_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30]
wire hitsVec_tagMatch_1 = superpage_entries_1_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30]
wire [8:0] _hitsVec_T_64 = _hitsVec_T_63[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_65 = _hitsVec_T_64 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_66 = _hitsVec_T_65; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_67 = hitsVec_tagMatch_1 & _hitsVec_T_66; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_69 = _hitsVec_T_68[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_70 = _hitsVec_T_69 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_71 = hitsVec_ignore_4 | _hitsVec_T_70; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_72 = _hitsVec_T_67 & _hitsVec_T_71; // @[TLB.scala:183:{29,40}]
wire _hitsVec_T_77 = _hitsVec_T_72; // @[TLB.scala:183:29]
wire _hitsVec_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _hitsVec_T_74 = _hitsVec_T_73[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_75 = _hitsVec_T_74 == 9'h0; // @[TLB.scala:183:{58,79}]
wire hitsVec_9 = vm_enabled & _hitsVec_T_77; // @[TLB.scala:183:29, :399:61, :440:44]
wire _hitsVec_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30]
wire hitsVec_tagMatch_2 = superpage_entries_2_valid_0 & _hitsVec_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30]
wire [8:0] _hitsVec_T_79 = _hitsVec_T_78[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_80 = _hitsVec_T_79 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_81 = _hitsVec_T_80; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_82 = hitsVec_tagMatch_2 & _hitsVec_T_81; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_7 = _hitsVec_ignore_T_7; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_84 = _hitsVec_T_83[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_85 = _hitsVec_T_84 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_86 = hitsVec_ignore_7 | _hitsVec_T_85; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_87 = _hitsVec_T_82 & _hitsVec_T_86; // @[TLB.scala:183:{29,40}]
wire _hitsVec_T_92 = _hitsVec_T_87; // @[TLB.scala:183:29]
wire _hitsVec_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _hitsVec_T_89 = _hitsVec_T_88[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_90 = _hitsVec_T_89 == 9'h0; // @[TLB.scala:183:{58,79}]
wire hitsVec_10 = vm_enabled & _hitsVec_T_92; // @[TLB.scala:183:29, :399:61, :440:44]
wire _hitsVec_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30]
wire hitsVec_tagMatch_3 = superpage_entries_3_valid_0 & _hitsVec_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30]
wire [8:0] _hitsVec_T_94 = _hitsVec_T_93[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_95 = _hitsVec_T_94 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_96 = _hitsVec_T_95; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_97 = hitsVec_tagMatch_3 & _hitsVec_T_96; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_10 = _hitsVec_ignore_T_10; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_99 = _hitsVec_T_98[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_100 = _hitsVec_T_99 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_101 = hitsVec_ignore_10 | _hitsVec_T_100; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_102 = _hitsVec_T_97 & _hitsVec_T_101; // @[TLB.scala:183:{29,40}]
wire _hitsVec_T_107 = _hitsVec_T_102; // @[TLB.scala:183:29]
wire _hitsVec_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _hitsVec_T_104 = _hitsVec_T_103[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_105 = _hitsVec_T_104 == 9'h0; // @[TLB.scala:183:{58,79}]
wire hitsVec_11 = vm_enabled & _hitsVec_T_107; // @[TLB.scala:183:29, :399:61, :440:44]
wire _hitsVec_tagMatch_T_4 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56]
wire hitsVec_tagMatch_4 = special_entry_valid_0 & _hitsVec_tagMatch_T_4; // @[TLB.scala:178:{33,43}, :346:56]
wire [26:0] _T_3838 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56]
wire [26:0] _hitsVec_T_108; // @[TLB.scala:183:52]
assign _hitsVec_T_108 = _T_3838; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_113; // @[TLB.scala:183:52]
assign _hitsVec_T_113 = _T_3838; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_118; // @[TLB.scala:183:52]
assign _hitsVec_T_118 = _T_3838; // @[TLB.scala:183:52]
wire [8:0] _hitsVec_T_109 = _hitsVec_T_108[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_110 = _hitsVec_T_109 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_111 = _hitsVec_T_110; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_112 = hitsVec_tagMatch_4 & _hitsVec_T_111; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_13 = _hitsVec_ignore_T_13; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_114 = _hitsVec_T_113[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_115 = _hitsVec_T_114 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_116 = hitsVec_ignore_13 | _hitsVec_T_115; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_117 = _hitsVec_T_112 & _hitsVec_T_116; // @[TLB.scala:183:{29,40}]
wire _hitsVec_ignore_T_14 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56]
wire hitsVec_ignore_14 = _hitsVec_ignore_T_14; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_119 = _hitsVec_T_118[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_120 = _hitsVec_T_119 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_121 = hitsVec_ignore_14 | _hitsVec_T_120; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_122 = _hitsVec_T_117 & _hitsVec_T_121; // @[TLB.scala:183:{29,40}]
wire hitsVec_12 = vm_enabled & _hitsVec_T_122; // @[TLB.scala:183:29, :399:61, :440:44]
wire [1:0] real_hits_lo_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27]
wire [2:0] real_hits_lo_lo = {real_hits_lo_lo_hi, hitsVec_0}; // @[package.scala:45:27]
wire [1:0] real_hits_lo_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27]
wire [2:0] real_hits_lo_hi = {real_hits_lo_hi_hi, hitsVec_3}; // @[package.scala:45:27]
wire [5:0] real_hits_lo = {real_hits_lo_hi, real_hits_lo_lo}; // @[package.scala:45:27]
wire [1:0] real_hits_hi_lo_hi = {hitsVec_8, hitsVec_7}; // @[package.scala:45:27]
wire [2:0] real_hits_hi_lo = {real_hits_hi_lo_hi, hitsVec_6}; // @[package.scala:45:27]
wire [1:0] real_hits_hi_hi_lo = {hitsVec_10, hitsVec_9}; // @[package.scala:45:27]
wire [1:0] real_hits_hi_hi_hi = {hitsVec_12, hitsVec_11}; // @[package.scala:45:27]
wire [3:0] real_hits_hi_hi = {real_hits_hi_hi_hi, real_hits_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] real_hits_hi = {real_hits_hi_hi, real_hits_hi_lo}; // @[package.scala:45:27]
wire [12:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27]
wire [12:0] _tlb_hit_T = real_hits; // @[package.scala:45:27]
wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18]
wire [13:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27]
wire _newEntry_g_T; // @[TLB.scala:453:25]
wire _newEntry_sw_T_6; // @[PTW.scala:151:40]
wire _newEntry_sx_T_5; // @[PTW.scala:153:35]
wire _newEntry_sr_T_5; // @[PTW.scala:149:35]
wire newEntry_g; // @[TLB.scala:449:24]
wire newEntry_sw; // @[TLB.scala:449:24]
wire newEntry_sx; // @[TLB.scala:449:24]
wire newEntry_sr; // @[TLB.scala:449:24]
wire newEntry_ppp; // @[TLB.scala:449:24]
wire newEntry_pal; // @[TLB.scala:449:24]
wire newEntry_paa; // @[TLB.scala:449:24]
wire newEntry_eff; // @[TLB.scala:449:24]
assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25]
assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25]
wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53]
wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7]
wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sr_T_1; // @[TLB.scala:318:7]
wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7]
wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7]
assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24]
wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7]
wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sw_T_1; // @[TLB.scala:318:7]
wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7]
wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7]
assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24]
wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7]
wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sx_T_1; // @[TLB.scala:318:7]
wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7]
wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7]
assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24]
wire [1:0] _GEN_24 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] _GEN_25 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [1:0] _GEN_26 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [1:0] _GEN_27 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [1:0] _GEN_28 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [1:0] _GEN_29 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [1:0] _GEN_30 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [20:0] _GEN_31 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24]
wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_0_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_1_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_2_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_3_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_4_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_5_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_6_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_7_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24]
wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire _superpage_entries_1_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire _superpage_entries_2_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire _superpage_entries_3_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_lo_lo_hi = {superpage_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_1_data_0_lo_lo = {superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_lo_hi_lo = {superpage_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_1_data_0_lo_hi_hi = {superpage_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_1_data_0_lo_hi = {superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_1_data_0_lo = {superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_hi_lo_lo = {superpage_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_1_data_0_hi_lo_hi = {superpage_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_1_data_0_hi_lo = {superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_hi_hi_lo = {superpage_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] superpage_entries_1_data_0_hi_hi_hi = {superpage_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_1_data_0_hi_hi = {superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_1_data_0_hi = {superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_1_data_0_T = {superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_lo_lo_hi = {superpage_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_2_data_0_lo_lo = {superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_lo_hi_lo = {superpage_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_2_data_0_lo_hi_hi = {superpage_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_2_data_0_lo_hi = {superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_2_data_0_lo = {superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_hi_lo_lo = {superpage_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_2_data_0_hi_lo_hi = {superpage_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_2_data_0_hi_lo = {superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_hi_hi_lo = {superpage_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] superpage_entries_2_data_0_hi_hi_hi = {superpage_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_2_data_0_hi_hi = {superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_2_data_0_hi = {superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_2_data_0_T = {superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_lo_lo_hi = {superpage_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_3_data_0_lo_lo = {superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_lo_hi_lo = {superpage_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_3_data_0_lo_hi_hi = {superpage_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_3_data_0_lo_hi = {superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_3_data_0_lo = {superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_hi_lo_lo = {superpage_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_3_data_0_hi_lo_hi = {superpage_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_3_data_0_hi_lo = {superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_hi_hi_lo = {superpage_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] superpage_entries_3_data_0_hi_hi_hi = {superpage_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_3_data_0_hi_hi = {superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_3_data_0_hi = {superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_3_data_0_T = {superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] waddr_1 = r_sectored_hit_valid ? r_sectored_hit_bits : r_sectored_repl_addr; // @[TLB.scala:356:33, :357:27, :485:22]
wire [1:0] idx = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_1 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_2 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_3 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_4 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_5 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_6 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_7 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [2:0] sectored_entries_0_0_data_lo_lo_hi = {sectored_entries_0_0_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_0_data_lo_lo = {sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_0_data_lo_hi_lo = {sectored_entries_0_0_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_0_data_lo_hi_hi = {sectored_entries_0_0_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_0_data_lo_hi = {sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_0_data_lo = {sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_0_data_hi_lo_lo = {sectored_entries_0_0_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_0_data_hi_lo_hi = {sectored_entries_0_0_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_0_data_hi_lo = {sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_0_data_hi_hi_lo = {sectored_entries_0_0_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_0_data_hi_hi_hi = {sectored_entries_0_0_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_0_data_hi_hi = {sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_0_data_hi = {sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_0_data_T = {sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_lo_lo_hi = {sectored_entries_0_1_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_1_data_lo_lo = {sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_lo_hi_lo = {sectored_entries_0_1_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_1_data_lo_hi_hi = {sectored_entries_0_1_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_1_data_lo_hi = {sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_1_data_lo = {sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_hi_lo_lo = {sectored_entries_0_1_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_1_data_hi_lo_hi = {sectored_entries_0_1_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_1_data_hi_lo = {sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_hi_hi_lo = {sectored_entries_0_1_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_1_data_hi_hi_hi = {sectored_entries_0_1_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_1_data_hi_hi = {sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_1_data_hi = {sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_1_data_T = {sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_lo_lo_hi = {sectored_entries_0_2_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_2_data_lo_lo = {sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_lo_hi_lo = {sectored_entries_0_2_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_2_data_lo_hi_hi = {sectored_entries_0_2_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_2_data_lo_hi = {sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_2_data_lo = {sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_hi_lo_lo = {sectored_entries_0_2_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_2_data_hi_lo_hi = {sectored_entries_0_2_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_2_data_hi_lo = {sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_hi_hi_lo = {sectored_entries_0_2_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_2_data_hi_hi_hi = {sectored_entries_0_2_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_2_data_hi_hi = {sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_2_data_hi = {sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_2_data_T = {sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_lo_lo_hi = {sectored_entries_0_3_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_3_data_lo_lo = {sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_lo_hi_lo = {sectored_entries_0_3_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_3_data_lo_hi_hi = {sectored_entries_0_3_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_3_data_lo_hi = {sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_3_data_lo = {sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_hi_lo_lo = {sectored_entries_0_3_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_3_data_hi_lo_hi = {sectored_entries_0_3_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_3_data_hi_lo = {sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_hi_hi_lo = {sectored_entries_0_3_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_3_data_hi_hi_hi = {sectored_entries_0_3_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_3_data_hi_hi = {sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_3_data_hi = {sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_3_data_T = {sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_lo_lo_hi = {sectored_entries_0_4_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_4_data_lo_lo = {sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_lo_hi_lo = {sectored_entries_0_4_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_4_data_lo_hi_hi = {sectored_entries_0_4_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_4_data_lo_hi = {sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_4_data_lo = {sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_hi_lo_lo = {sectored_entries_0_4_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_4_data_hi_lo_hi = {sectored_entries_0_4_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_4_data_hi_lo = {sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_hi_hi_lo = {sectored_entries_0_4_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_4_data_hi_hi_hi = {sectored_entries_0_4_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_4_data_hi_hi = {sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_4_data_hi = {sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_4_data_T = {sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_lo_lo_hi = {sectored_entries_0_5_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_5_data_lo_lo = {sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_lo_hi_lo = {sectored_entries_0_5_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_5_data_lo_hi_hi = {sectored_entries_0_5_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_5_data_lo_hi = {sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_5_data_lo = {sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_hi_lo_lo = {sectored_entries_0_5_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_5_data_hi_lo_hi = {sectored_entries_0_5_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_5_data_hi_lo = {sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_hi_hi_lo = {sectored_entries_0_5_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_5_data_hi_hi_hi = {sectored_entries_0_5_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_5_data_hi_hi = {sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_5_data_hi = {sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_5_data_T = {sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_lo_lo_hi = {sectored_entries_0_6_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_6_data_lo_lo = {sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_lo_hi_lo = {sectored_entries_0_6_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_6_data_lo_hi_hi = {sectored_entries_0_6_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_6_data_lo_hi = {sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_6_data_lo = {sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_hi_lo_lo = {sectored_entries_0_6_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_6_data_hi_lo_hi = {sectored_entries_0_6_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_6_data_hi_lo = {sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_hi_hi_lo = {sectored_entries_0_6_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_6_data_hi_hi_hi = {sectored_entries_0_6_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_6_data_hi_hi = {sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_6_data_hi = {sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_6_data_T = {sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_lo_lo_hi = {sectored_entries_0_7_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_7_data_lo_lo = {sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_lo_hi_lo = {sectored_entries_0_7_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_7_data_lo_hi_hi = {sectored_entries_0_7_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_7_data_lo_hi = {sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_7_data_lo = {sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_hi_lo_lo = {sectored_entries_0_7_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_7_data_hi_lo_hi = {sectored_entries_0_7_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_7_data_hi_lo = {sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_hi_hi_lo = {sectored_entries_0_7_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_7_data_hi_hi_hi = {sectored_entries_0_7_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_7_data_hi_hi = {sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_7_data_hi = {sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_7_data_T = {sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24]
wire [19:0] _entries_T_23; // @[TLB.scala:170:77]
wire _entries_T_22; // @[TLB.scala:170:77]
wire _entries_T_21; // @[TLB.scala:170:77]
wire _entries_T_20; // @[TLB.scala:170:77]
wire _entries_T_19; // @[TLB.scala:170:77]
wire _entries_T_18; // @[TLB.scala:170:77]
wire _entries_T_17; // @[TLB.scala:170:77]
wire _entries_T_16; // @[TLB.scala:170:77]
wire _entries_T_15; // @[TLB.scala:170:77]
wire _entries_T_14; // @[TLB.scala:170:77]
wire _entries_T_13; // @[TLB.scala:170:77]
wire _entries_T_12; // @[TLB.scala:170:77]
wire _entries_T_11; // @[TLB.scala:170:77]
wire _entries_T_10; // @[TLB.scala:170:77]
wire _entries_T_9; // @[TLB.scala:170:77]
wire _entries_T_8; // @[TLB.scala:170:77]
wire _entries_T_7; // @[TLB.scala:170:77]
wire _entries_T_6; // @[TLB.scala:170:77]
wire _entries_T_5; // @[TLB.scala:170:77]
wire _entries_T_4; // @[TLB.scala:170:77]
wire _entries_T_3; // @[TLB.scala:170:77]
wire _entries_T_2; // @[TLB.scala:170:77]
wire _entries_T_1; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_32 = {{sectored_entries_0_0_data_3}, {sectored_entries_0_0_data_2}, {sectored_entries_0_0_data_1}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_1 = _GEN_32[_entries_T]; // @[package.scala:163:13]
assign _entries_T_1 = _entries_WIRE_1[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_fragmented_superpage = _entries_T_1; // @[TLB.scala:170:77]
assign _entries_T_2 = _entries_WIRE_1[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_c = _entries_T_2; // @[TLB.scala:170:77]
assign _entries_T_3 = _entries_WIRE_1[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_eff = _entries_T_3; // @[TLB.scala:170:77]
assign _entries_T_4 = _entries_WIRE_1[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_paa = _entries_T_4; // @[TLB.scala:170:77]
assign _entries_T_5 = _entries_WIRE_1[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_pal = _entries_T_5; // @[TLB.scala:170:77]
assign _entries_T_6 = _entries_WIRE_1[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_ppp = _entries_T_6; // @[TLB.scala:170:77]
assign _entries_T_7 = _entries_WIRE_1[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_pr = _entries_T_7; // @[TLB.scala:170:77]
assign _entries_T_8 = _entries_WIRE_1[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_px = _entries_T_8; // @[TLB.scala:170:77]
assign _entries_T_9 = _entries_WIRE_1[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_pw = _entries_T_9; // @[TLB.scala:170:77]
assign _entries_T_10 = _entries_WIRE_1[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_hr = _entries_T_10; // @[TLB.scala:170:77]
assign _entries_T_11 = _entries_WIRE_1[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_hx = _entries_T_11; // @[TLB.scala:170:77]
assign _entries_T_12 = _entries_WIRE_1[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_hw = _entries_T_12; // @[TLB.scala:170:77]
assign _entries_T_13 = _entries_WIRE_1[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_sr = _entries_T_13; // @[TLB.scala:170:77]
assign _entries_T_14 = _entries_WIRE_1[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_sx = _entries_T_14; // @[TLB.scala:170:77]
assign _entries_T_15 = _entries_WIRE_1[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_sw = _entries_T_15; // @[TLB.scala:170:77]
assign _entries_T_16 = _entries_WIRE_1[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_gf = _entries_T_16; // @[TLB.scala:170:77]
assign _entries_T_17 = _entries_WIRE_1[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_pf = _entries_T_17; // @[TLB.scala:170:77]
assign _entries_T_18 = _entries_WIRE_1[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_stage2 = _entries_T_18; // @[TLB.scala:170:77]
assign _entries_T_19 = _entries_WIRE_1[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_final = _entries_T_19; // @[TLB.scala:170:77]
assign _entries_T_20 = _entries_WIRE_1[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_ptw = _entries_T_20; // @[TLB.scala:170:77]
assign _entries_T_21 = _entries_WIRE_1[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_g = _entries_T_21; // @[TLB.scala:170:77]
assign _entries_T_22 = _entries_WIRE_1[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_u = _entries_T_22; // @[TLB.scala:170:77]
assign _entries_T_23 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_ppn = _entries_T_23; // @[TLB.scala:170:77]
wire [19:0] _entries_T_47; // @[TLB.scala:170:77]
wire _entries_T_46; // @[TLB.scala:170:77]
wire _entries_T_45; // @[TLB.scala:170:77]
wire _entries_T_44; // @[TLB.scala:170:77]
wire _entries_T_43; // @[TLB.scala:170:77]
wire _entries_T_42; // @[TLB.scala:170:77]
wire _entries_T_41; // @[TLB.scala:170:77]
wire _entries_T_40; // @[TLB.scala:170:77]
wire _entries_T_39; // @[TLB.scala:170:77]
wire _entries_T_38; // @[TLB.scala:170:77]
wire _entries_T_37; // @[TLB.scala:170:77]
wire _entries_T_36; // @[TLB.scala:170:77]
wire _entries_T_35; // @[TLB.scala:170:77]
wire _entries_T_34; // @[TLB.scala:170:77]
wire _entries_T_33; // @[TLB.scala:170:77]
wire _entries_T_32; // @[TLB.scala:170:77]
wire _entries_T_31; // @[TLB.scala:170:77]
wire _entries_T_30; // @[TLB.scala:170:77]
wire _entries_T_29; // @[TLB.scala:170:77]
wire _entries_T_28; // @[TLB.scala:170:77]
wire _entries_T_27; // @[TLB.scala:170:77]
wire _entries_T_26; // @[TLB.scala:170:77]
wire _entries_T_25; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_33 = {{sectored_entries_0_1_data_3}, {sectored_entries_0_1_data_2}, {sectored_entries_0_1_data_1}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_3 = _GEN_33[_entries_T_24]; // @[package.scala:163:13]
assign _entries_T_25 = _entries_WIRE_3[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_fragmented_superpage = _entries_T_25; // @[TLB.scala:170:77]
assign _entries_T_26 = _entries_WIRE_3[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_c = _entries_T_26; // @[TLB.scala:170:77]
assign _entries_T_27 = _entries_WIRE_3[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_eff = _entries_T_27; // @[TLB.scala:170:77]
assign _entries_T_28 = _entries_WIRE_3[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_paa = _entries_T_28; // @[TLB.scala:170:77]
assign _entries_T_29 = _entries_WIRE_3[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pal = _entries_T_29; // @[TLB.scala:170:77]
assign _entries_T_30 = _entries_WIRE_3[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ppp = _entries_T_30; // @[TLB.scala:170:77]
assign _entries_T_31 = _entries_WIRE_3[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pr = _entries_T_31; // @[TLB.scala:170:77]
assign _entries_T_32 = _entries_WIRE_3[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_px = _entries_T_32; // @[TLB.scala:170:77]
assign _entries_T_33 = _entries_WIRE_3[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pw = _entries_T_33; // @[TLB.scala:170:77]
assign _entries_T_34 = _entries_WIRE_3[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hr = _entries_T_34; // @[TLB.scala:170:77]
assign _entries_T_35 = _entries_WIRE_3[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hx = _entries_T_35; // @[TLB.scala:170:77]
assign _entries_T_36 = _entries_WIRE_3[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hw = _entries_T_36; // @[TLB.scala:170:77]
assign _entries_T_37 = _entries_WIRE_3[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sr = _entries_T_37; // @[TLB.scala:170:77]
assign _entries_T_38 = _entries_WIRE_3[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sx = _entries_T_38; // @[TLB.scala:170:77]
assign _entries_T_39 = _entries_WIRE_3[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sw = _entries_T_39; // @[TLB.scala:170:77]
assign _entries_T_40 = _entries_WIRE_3[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_gf = _entries_T_40; // @[TLB.scala:170:77]
assign _entries_T_41 = _entries_WIRE_3[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pf = _entries_T_41; // @[TLB.scala:170:77]
assign _entries_T_42 = _entries_WIRE_3[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_stage2 = _entries_T_42; // @[TLB.scala:170:77]
assign _entries_T_43 = _entries_WIRE_3[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_final = _entries_T_43; // @[TLB.scala:170:77]
assign _entries_T_44 = _entries_WIRE_3[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_ptw = _entries_T_44; // @[TLB.scala:170:77]
assign _entries_T_45 = _entries_WIRE_3[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_g = _entries_T_45; // @[TLB.scala:170:77]
assign _entries_T_46 = _entries_WIRE_3[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_u = _entries_T_46; // @[TLB.scala:170:77]
assign _entries_T_47 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_2_ppn = _entries_T_47; // @[TLB.scala:170:77]
wire [19:0] _entries_T_71; // @[TLB.scala:170:77]
wire _entries_T_70; // @[TLB.scala:170:77]
wire _entries_T_69; // @[TLB.scala:170:77]
wire _entries_T_68; // @[TLB.scala:170:77]
wire _entries_T_67; // @[TLB.scala:170:77]
wire _entries_T_66; // @[TLB.scala:170:77]
wire _entries_T_65; // @[TLB.scala:170:77]
wire _entries_T_64; // @[TLB.scala:170:77]
wire _entries_T_63; // @[TLB.scala:170:77]
wire _entries_T_62; // @[TLB.scala:170:77]
wire _entries_T_61; // @[TLB.scala:170:77]
wire _entries_T_60; // @[TLB.scala:170:77]
wire _entries_T_59; // @[TLB.scala:170:77]
wire _entries_T_58; // @[TLB.scala:170:77]
wire _entries_T_57; // @[TLB.scala:170:77]
wire _entries_T_56; // @[TLB.scala:170:77]
wire _entries_T_55; // @[TLB.scala:170:77]
wire _entries_T_54; // @[TLB.scala:170:77]
wire _entries_T_53; // @[TLB.scala:170:77]
wire _entries_T_52; // @[TLB.scala:170:77]
wire _entries_T_51; // @[TLB.scala:170:77]
wire _entries_T_50; // @[TLB.scala:170:77]
wire _entries_T_49; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_34 = {{sectored_entries_0_2_data_3}, {sectored_entries_0_2_data_2}, {sectored_entries_0_2_data_1}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_5 = _GEN_34[_entries_T_48]; // @[package.scala:163:13]
assign _entries_T_49 = _entries_WIRE_5[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_fragmented_superpage = _entries_T_49; // @[TLB.scala:170:77]
assign _entries_T_50 = _entries_WIRE_5[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_c = _entries_T_50; // @[TLB.scala:170:77]
assign _entries_T_51 = _entries_WIRE_5[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_eff = _entries_T_51; // @[TLB.scala:170:77]
assign _entries_T_52 = _entries_WIRE_5[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_paa = _entries_T_52; // @[TLB.scala:170:77]
assign _entries_T_53 = _entries_WIRE_5[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pal = _entries_T_53; // @[TLB.scala:170:77]
assign _entries_T_54 = _entries_WIRE_5[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ppp = _entries_T_54; // @[TLB.scala:170:77]
assign _entries_T_55 = _entries_WIRE_5[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pr = _entries_T_55; // @[TLB.scala:170:77]
assign _entries_T_56 = _entries_WIRE_5[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_px = _entries_T_56; // @[TLB.scala:170:77]
assign _entries_T_57 = _entries_WIRE_5[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pw = _entries_T_57; // @[TLB.scala:170:77]
assign _entries_T_58 = _entries_WIRE_5[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hr = _entries_T_58; // @[TLB.scala:170:77]
assign _entries_T_59 = _entries_WIRE_5[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hx = _entries_T_59; // @[TLB.scala:170:77]
assign _entries_T_60 = _entries_WIRE_5[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hw = _entries_T_60; // @[TLB.scala:170:77]
assign _entries_T_61 = _entries_WIRE_5[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sr = _entries_T_61; // @[TLB.scala:170:77]
assign _entries_T_62 = _entries_WIRE_5[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sx = _entries_T_62; // @[TLB.scala:170:77]
assign _entries_T_63 = _entries_WIRE_5[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sw = _entries_T_63; // @[TLB.scala:170:77]
assign _entries_T_64 = _entries_WIRE_5[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_gf = _entries_T_64; // @[TLB.scala:170:77]
assign _entries_T_65 = _entries_WIRE_5[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pf = _entries_T_65; // @[TLB.scala:170:77]
assign _entries_T_66 = _entries_WIRE_5[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_stage2 = _entries_T_66; // @[TLB.scala:170:77]
assign _entries_T_67 = _entries_WIRE_5[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_final = _entries_T_67; // @[TLB.scala:170:77]
assign _entries_T_68 = _entries_WIRE_5[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_ptw = _entries_T_68; // @[TLB.scala:170:77]
assign _entries_T_69 = _entries_WIRE_5[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_g = _entries_T_69; // @[TLB.scala:170:77]
assign _entries_T_70 = _entries_WIRE_5[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_u = _entries_T_70; // @[TLB.scala:170:77]
assign _entries_T_71 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_4_ppn = _entries_T_71; // @[TLB.scala:170:77]
wire [19:0] _entries_T_95; // @[TLB.scala:170:77]
wire _entries_T_94; // @[TLB.scala:170:77]
wire _entries_T_93; // @[TLB.scala:170:77]
wire _entries_T_92; // @[TLB.scala:170:77]
wire _entries_T_91; // @[TLB.scala:170:77]
wire _entries_T_90; // @[TLB.scala:170:77]
wire _entries_T_89; // @[TLB.scala:170:77]
wire _entries_T_88; // @[TLB.scala:170:77]
wire _entries_T_87; // @[TLB.scala:170:77]
wire _entries_T_86; // @[TLB.scala:170:77]
wire _entries_T_85; // @[TLB.scala:170:77]
wire _entries_T_84; // @[TLB.scala:170:77]
wire _entries_T_83; // @[TLB.scala:170:77]
wire _entries_T_82; // @[TLB.scala:170:77]
wire _entries_T_81; // @[TLB.scala:170:77]
wire _entries_T_80; // @[TLB.scala:170:77]
wire _entries_T_79; // @[TLB.scala:170:77]
wire _entries_T_78; // @[TLB.scala:170:77]
wire _entries_T_77; // @[TLB.scala:170:77]
wire _entries_T_76; // @[TLB.scala:170:77]
wire _entries_T_75; // @[TLB.scala:170:77]
wire _entries_T_74; // @[TLB.scala:170:77]
wire _entries_T_73; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_35 = {{sectored_entries_0_3_data_3}, {sectored_entries_0_3_data_2}, {sectored_entries_0_3_data_1}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_7 = _GEN_35[_entries_T_72]; // @[package.scala:163:13]
assign _entries_T_73 = _entries_WIRE_7[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_fragmented_superpage = _entries_T_73; // @[TLB.scala:170:77]
assign _entries_T_74 = _entries_WIRE_7[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_c = _entries_T_74; // @[TLB.scala:170:77]
assign _entries_T_75 = _entries_WIRE_7[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_eff = _entries_T_75; // @[TLB.scala:170:77]
assign _entries_T_76 = _entries_WIRE_7[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_paa = _entries_T_76; // @[TLB.scala:170:77]
assign _entries_T_77 = _entries_WIRE_7[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pal = _entries_T_77; // @[TLB.scala:170:77]
assign _entries_T_78 = _entries_WIRE_7[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ppp = _entries_T_78; // @[TLB.scala:170:77]
assign _entries_T_79 = _entries_WIRE_7[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pr = _entries_T_79; // @[TLB.scala:170:77]
assign _entries_T_80 = _entries_WIRE_7[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_px = _entries_T_80; // @[TLB.scala:170:77]
assign _entries_T_81 = _entries_WIRE_7[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pw = _entries_T_81; // @[TLB.scala:170:77]
assign _entries_T_82 = _entries_WIRE_7[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hr = _entries_T_82; // @[TLB.scala:170:77]
assign _entries_T_83 = _entries_WIRE_7[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hx = _entries_T_83; // @[TLB.scala:170:77]
assign _entries_T_84 = _entries_WIRE_7[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hw = _entries_T_84; // @[TLB.scala:170:77]
assign _entries_T_85 = _entries_WIRE_7[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sr = _entries_T_85; // @[TLB.scala:170:77]
assign _entries_T_86 = _entries_WIRE_7[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sx = _entries_T_86; // @[TLB.scala:170:77]
assign _entries_T_87 = _entries_WIRE_7[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sw = _entries_T_87; // @[TLB.scala:170:77]
assign _entries_T_88 = _entries_WIRE_7[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_gf = _entries_T_88; // @[TLB.scala:170:77]
assign _entries_T_89 = _entries_WIRE_7[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pf = _entries_T_89; // @[TLB.scala:170:77]
assign _entries_T_90 = _entries_WIRE_7[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_stage2 = _entries_T_90; // @[TLB.scala:170:77]
assign _entries_T_91 = _entries_WIRE_7[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_final = _entries_T_91; // @[TLB.scala:170:77]
assign _entries_T_92 = _entries_WIRE_7[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_ptw = _entries_T_92; // @[TLB.scala:170:77]
assign _entries_T_93 = _entries_WIRE_7[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_g = _entries_T_93; // @[TLB.scala:170:77]
assign _entries_T_94 = _entries_WIRE_7[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_u = _entries_T_94; // @[TLB.scala:170:77]
assign _entries_T_95 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_6_ppn = _entries_T_95; // @[TLB.scala:170:77]
wire [19:0] _entries_T_119; // @[TLB.scala:170:77]
wire _entries_T_118; // @[TLB.scala:170:77]
wire _entries_T_117; // @[TLB.scala:170:77]
wire _entries_T_116; // @[TLB.scala:170:77]
wire _entries_T_115; // @[TLB.scala:170:77]
wire _entries_T_114; // @[TLB.scala:170:77]
wire _entries_T_113; // @[TLB.scala:170:77]
wire _entries_T_112; // @[TLB.scala:170:77]
wire _entries_T_111; // @[TLB.scala:170:77]
wire _entries_T_110; // @[TLB.scala:170:77]
wire _entries_T_109; // @[TLB.scala:170:77]
wire _entries_T_108; // @[TLB.scala:170:77]
wire _entries_T_107; // @[TLB.scala:170:77]
wire _entries_T_106; // @[TLB.scala:170:77]
wire _entries_T_105; // @[TLB.scala:170:77]
wire _entries_T_104; // @[TLB.scala:170:77]
wire _entries_T_103; // @[TLB.scala:170:77]
wire _entries_T_102; // @[TLB.scala:170:77]
wire _entries_T_101; // @[TLB.scala:170:77]
wire _entries_T_100; // @[TLB.scala:170:77]
wire _entries_T_99; // @[TLB.scala:170:77]
wire _entries_T_98; // @[TLB.scala:170:77]
wire _entries_T_97; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_36 = {{sectored_entries_0_4_data_3}, {sectored_entries_0_4_data_2}, {sectored_entries_0_4_data_1}, {sectored_entries_0_4_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_9 = _GEN_36[_entries_T_96]; // @[package.scala:163:13]
assign _entries_T_97 = _entries_WIRE_9[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_fragmented_superpage = _entries_T_97; // @[TLB.scala:170:77]
assign _entries_T_98 = _entries_WIRE_9[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_c = _entries_T_98; // @[TLB.scala:170:77]
assign _entries_T_99 = _entries_WIRE_9[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_eff = _entries_T_99; // @[TLB.scala:170:77]
assign _entries_T_100 = _entries_WIRE_9[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_paa = _entries_T_100; // @[TLB.scala:170:77]
assign _entries_T_101 = _entries_WIRE_9[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pal = _entries_T_101; // @[TLB.scala:170:77]
assign _entries_T_102 = _entries_WIRE_9[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ppp = _entries_T_102; // @[TLB.scala:170:77]
assign _entries_T_103 = _entries_WIRE_9[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pr = _entries_T_103; // @[TLB.scala:170:77]
assign _entries_T_104 = _entries_WIRE_9[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_px = _entries_T_104; // @[TLB.scala:170:77]
assign _entries_T_105 = _entries_WIRE_9[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pw = _entries_T_105; // @[TLB.scala:170:77]
assign _entries_T_106 = _entries_WIRE_9[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hr = _entries_T_106; // @[TLB.scala:170:77]
assign _entries_T_107 = _entries_WIRE_9[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hx = _entries_T_107; // @[TLB.scala:170:77]
assign _entries_T_108 = _entries_WIRE_9[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hw = _entries_T_108; // @[TLB.scala:170:77]
assign _entries_T_109 = _entries_WIRE_9[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sr = _entries_T_109; // @[TLB.scala:170:77]
assign _entries_T_110 = _entries_WIRE_9[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sx = _entries_T_110; // @[TLB.scala:170:77]
assign _entries_T_111 = _entries_WIRE_9[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sw = _entries_T_111; // @[TLB.scala:170:77]
assign _entries_T_112 = _entries_WIRE_9[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_gf = _entries_T_112; // @[TLB.scala:170:77]
assign _entries_T_113 = _entries_WIRE_9[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pf = _entries_T_113; // @[TLB.scala:170:77]
assign _entries_T_114 = _entries_WIRE_9[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_stage2 = _entries_T_114; // @[TLB.scala:170:77]
assign _entries_T_115 = _entries_WIRE_9[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_final = _entries_T_115; // @[TLB.scala:170:77]
assign _entries_T_116 = _entries_WIRE_9[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_ptw = _entries_T_116; // @[TLB.scala:170:77]
assign _entries_T_117 = _entries_WIRE_9[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_g = _entries_T_117; // @[TLB.scala:170:77]
assign _entries_T_118 = _entries_WIRE_9[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_u = _entries_T_118; // @[TLB.scala:170:77]
assign _entries_T_119 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_8_ppn = _entries_T_119; // @[TLB.scala:170:77]
wire [19:0] _entries_T_143; // @[TLB.scala:170:77]
wire _entries_T_142; // @[TLB.scala:170:77]
wire _entries_T_141; // @[TLB.scala:170:77]
wire _entries_T_140; // @[TLB.scala:170:77]
wire _entries_T_139; // @[TLB.scala:170:77]
wire _entries_T_138; // @[TLB.scala:170:77]
wire _entries_T_137; // @[TLB.scala:170:77]
wire _entries_T_136; // @[TLB.scala:170:77]
wire _entries_T_135; // @[TLB.scala:170:77]
wire _entries_T_134; // @[TLB.scala:170:77]
wire _entries_T_133; // @[TLB.scala:170:77]
wire _entries_T_132; // @[TLB.scala:170:77]
wire _entries_T_131; // @[TLB.scala:170:77]
wire _entries_T_130; // @[TLB.scala:170:77]
wire _entries_T_129; // @[TLB.scala:170:77]
wire _entries_T_128; // @[TLB.scala:170:77]
wire _entries_T_127; // @[TLB.scala:170:77]
wire _entries_T_126; // @[TLB.scala:170:77]
wire _entries_T_125; // @[TLB.scala:170:77]
wire _entries_T_124; // @[TLB.scala:170:77]
wire _entries_T_123; // @[TLB.scala:170:77]
wire _entries_T_122; // @[TLB.scala:170:77]
wire _entries_T_121; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_37 = {{sectored_entries_0_5_data_3}, {sectored_entries_0_5_data_2}, {sectored_entries_0_5_data_1}, {sectored_entries_0_5_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_11 = _GEN_37[_entries_T_120]; // @[package.scala:163:13]
assign _entries_T_121 = _entries_WIRE_11[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_fragmented_superpage = _entries_T_121; // @[TLB.scala:170:77]
assign _entries_T_122 = _entries_WIRE_11[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_c = _entries_T_122; // @[TLB.scala:170:77]
assign _entries_T_123 = _entries_WIRE_11[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_eff = _entries_T_123; // @[TLB.scala:170:77]
assign _entries_T_124 = _entries_WIRE_11[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_paa = _entries_T_124; // @[TLB.scala:170:77]
assign _entries_T_125 = _entries_WIRE_11[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pal = _entries_T_125; // @[TLB.scala:170:77]
assign _entries_T_126 = _entries_WIRE_11[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ppp = _entries_T_126; // @[TLB.scala:170:77]
assign _entries_T_127 = _entries_WIRE_11[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pr = _entries_T_127; // @[TLB.scala:170:77]
assign _entries_T_128 = _entries_WIRE_11[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_px = _entries_T_128; // @[TLB.scala:170:77]
assign _entries_T_129 = _entries_WIRE_11[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pw = _entries_T_129; // @[TLB.scala:170:77]
assign _entries_T_130 = _entries_WIRE_11[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hr = _entries_T_130; // @[TLB.scala:170:77]
assign _entries_T_131 = _entries_WIRE_11[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hx = _entries_T_131; // @[TLB.scala:170:77]
assign _entries_T_132 = _entries_WIRE_11[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hw = _entries_T_132; // @[TLB.scala:170:77]
assign _entries_T_133 = _entries_WIRE_11[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sr = _entries_T_133; // @[TLB.scala:170:77]
assign _entries_T_134 = _entries_WIRE_11[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sx = _entries_T_134; // @[TLB.scala:170:77]
assign _entries_T_135 = _entries_WIRE_11[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sw = _entries_T_135; // @[TLB.scala:170:77]
assign _entries_T_136 = _entries_WIRE_11[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_gf = _entries_T_136; // @[TLB.scala:170:77]
assign _entries_T_137 = _entries_WIRE_11[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pf = _entries_T_137; // @[TLB.scala:170:77]
assign _entries_T_138 = _entries_WIRE_11[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_stage2 = _entries_T_138; // @[TLB.scala:170:77]
assign _entries_T_139 = _entries_WIRE_11[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_final = _entries_T_139; // @[TLB.scala:170:77]
assign _entries_T_140 = _entries_WIRE_11[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_ptw = _entries_T_140; // @[TLB.scala:170:77]
assign _entries_T_141 = _entries_WIRE_11[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_g = _entries_T_141; // @[TLB.scala:170:77]
assign _entries_T_142 = _entries_WIRE_11[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_u = _entries_T_142; // @[TLB.scala:170:77]
assign _entries_T_143 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_10_ppn = _entries_T_143; // @[TLB.scala:170:77]
wire [19:0] _entries_T_167; // @[TLB.scala:170:77]
wire _entries_T_166; // @[TLB.scala:170:77]
wire _entries_T_165; // @[TLB.scala:170:77]
wire _entries_T_164; // @[TLB.scala:170:77]
wire _entries_T_163; // @[TLB.scala:170:77]
wire _entries_T_162; // @[TLB.scala:170:77]
wire _entries_T_161; // @[TLB.scala:170:77]
wire _entries_T_160; // @[TLB.scala:170:77]
wire _entries_T_159; // @[TLB.scala:170:77]
wire _entries_T_158; // @[TLB.scala:170:77]
wire _entries_T_157; // @[TLB.scala:170:77]
wire _entries_T_156; // @[TLB.scala:170:77]
wire _entries_T_155; // @[TLB.scala:170:77]
wire _entries_T_154; // @[TLB.scala:170:77]
wire _entries_T_153; // @[TLB.scala:170:77]
wire _entries_T_152; // @[TLB.scala:170:77]
wire _entries_T_151; // @[TLB.scala:170:77]
wire _entries_T_150; // @[TLB.scala:170:77]
wire _entries_T_149; // @[TLB.scala:170:77]
wire _entries_T_148; // @[TLB.scala:170:77]
wire _entries_T_147; // @[TLB.scala:170:77]
wire _entries_T_146; // @[TLB.scala:170:77]
wire _entries_T_145; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_38 = {{sectored_entries_0_6_data_3}, {sectored_entries_0_6_data_2}, {sectored_entries_0_6_data_1}, {sectored_entries_0_6_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_13 = _GEN_38[_entries_T_144]; // @[package.scala:163:13]
assign _entries_T_145 = _entries_WIRE_13[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_fragmented_superpage = _entries_T_145; // @[TLB.scala:170:77]
assign _entries_T_146 = _entries_WIRE_13[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_c = _entries_T_146; // @[TLB.scala:170:77]
assign _entries_T_147 = _entries_WIRE_13[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_eff = _entries_T_147; // @[TLB.scala:170:77]
assign _entries_T_148 = _entries_WIRE_13[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_paa = _entries_T_148; // @[TLB.scala:170:77]
assign _entries_T_149 = _entries_WIRE_13[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pal = _entries_T_149; // @[TLB.scala:170:77]
assign _entries_T_150 = _entries_WIRE_13[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ppp = _entries_T_150; // @[TLB.scala:170:77]
assign _entries_T_151 = _entries_WIRE_13[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pr = _entries_T_151; // @[TLB.scala:170:77]
assign _entries_T_152 = _entries_WIRE_13[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_px = _entries_T_152; // @[TLB.scala:170:77]
assign _entries_T_153 = _entries_WIRE_13[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pw = _entries_T_153; // @[TLB.scala:170:77]
assign _entries_T_154 = _entries_WIRE_13[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_hr = _entries_T_154; // @[TLB.scala:170:77]
assign _entries_T_155 = _entries_WIRE_13[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_hx = _entries_T_155; // @[TLB.scala:170:77]
assign _entries_T_156 = _entries_WIRE_13[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_hw = _entries_T_156; // @[TLB.scala:170:77]
assign _entries_T_157 = _entries_WIRE_13[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_sr = _entries_T_157; // @[TLB.scala:170:77]
assign _entries_T_158 = _entries_WIRE_13[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_sx = _entries_T_158; // @[TLB.scala:170:77]
assign _entries_T_159 = _entries_WIRE_13[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_sw = _entries_T_159; // @[TLB.scala:170:77]
assign _entries_T_160 = _entries_WIRE_13[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_gf = _entries_T_160; // @[TLB.scala:170:77]
assign _entries_T_161 = _entries_WIRE_13[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pf = _entries_T_161; // @[TLB.scala:170:77]
assign _entries_T_162 = _entries_WIRE_13[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ae_stage2 = _entries_T_162; // @[TLB.scala:170:77]
assign _entries_T_163 = _entries_WIRE_13[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ae_final = _entries_T_163; // @[TLB.scala:170:77]
assign _entries_T_164 = _entries_WIRE_13[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ae_ptw = _entries_T_164; // @[TLB.scala:170:77]
assign _entries_T_165 = _entries_WIRE_13[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_g = _entries_T_165; // @[TLB.scala:170:77]
assign _entries_T_166 = _entries_WIRE_13[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_u = _entries_T_166; // @[TLB.scala:170:77]
assign _entries_T_167 = _entries_WIRE_13[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_12_ppn = _entries_T_167; // @[TLB.scala:170:77]
wire [19:0] _entries_T_191; // @[TLB.scala:170:77]
wire _entries_T_190; // @[TLB.scala:170:77]
wire _entries_T_189; // @[TLB.scala:170:77]
wire _entries_T_188; // @[TLB.scala:170:77]
wire _entries_T_187; // @[TLB.scala:170:77]
wire _entries_T_186; // @[TLB.scala:170:77]
wire _entries_T_185; // @[TLB.scala:170:77]
wire _entries_T_184; // @[TLB.scala:170:77]
wire _entries_T_183; // @[TLB.scala:170:77]
wire _entries_T_182; // @[TLB.scala:170:77]
wire _entries_T_181; // @[TLB.scala:170:77]
wire _entries_T_180; // @[TLB.scala:170:77]
wire _entries_T_179; // @[TLB.scala:170:77]
wire _entries_T_178; // @[TLB.scala:170:77]
wire _entries_T_177; // @[TLB.scala:170:77]
wire _entries_T_176; // @[TLB.scala:170:77]
wire _entries_T_175; // @[TLB.scala:170:77]
wire _entries_T_174; // @[TLB.scala:170:77]
wire _entries_T_173; // @[TLB.scala:170:77]
wire _entries_T_172; // @[TLB.scala:170:77]
wire _entries_T_171; // @[TLB.scala:170:77]
wire _entries_T_170; // @[TLB.scala:170:77]
wire _entries_T_169; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_39 = {{sectored_entries_0_7_data_3}, {sectored_entries_0_7_data_2}, {sectored_entries_0_7_data_1}, {sectored_entries_0_7_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_15 = _GEN_39[_entries_T_168]; // @[package.scala:163:13]
assign _entries_T_169 = _entries_WIRE_15[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_fragmented_superpage = _entries_T_169; // @[TLB.scala:170:77]
assign _entries_T_170 = _entries_WIRE_15[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_c = _entries_T_170; // @[TLB.scala:170:77]
assign _entries_T_171 = _entries_WIRE_15[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_eff = _entries_T_171; // @[TLB.scala:170:77]
assign _entries_T_172 = _entries_WIRE_15[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_paa = _entries_T_172; // @[TLB.scala:170:77]
assign _entries_T_173 = _entries_WIRE_15[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pal = _entries_T_173; // @[TLB.scala:170:77]
assign _entries_T_174 = _entries_WIRE_15[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ppp = _entries_T_174; // @[TLB.scala:170:77]
assign _entries_T_175 = _entries_WIRE_15[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pr = _entries_T_175; // @[TLB.scala:170:77]
assign _entries_T_176 = _entries_WIRE_15[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_px = _entries_T_176; // @[TLB.scala:170:77]
assign _entries_T_177 = _entries_WIRE_15[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pw = _entries_T_177; // @[TLB.scala:170:77]
assign _entries_T_178 = _entries_WIRE_15[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_hr = _entries_T_178; // @[TLB.scala:170:77]
assign _entries_T_179 = _entries_WIRE_15[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_hx = _entries_T_179; // @[TLB.scala:170:77]
assign _entries_T_180 = _entries_WIRE_15[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_hw = _entries_T_180; // @[TLB.scala:170:77]
assign _entries_T_181 = _entries_WIRE_15[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_sr = _entries_T_181; // @[TLB.scala:170:77]
assign _entries_T_182 = _entries_WIRE_15[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_sx = _entries_T_182; // @[TLB.scala:170:77]
assign _entries_T_183 = _entries_WIRE_15[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_sw = _entries_T_183; // @[TLB.scala:170:77]
assign _entries_T_184 = _entries_WIRE_15[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_gf = _entries_T_184; // @[TLB.scala:170:77]
assign _entries_T_185 = _entries_WIRE_15[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pf = _entries_T_185; // @[TLB.scala:170:77]
assign _entries_T_186 = _entries_WIRE_15[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ae_stage2 = _entries_T_186; // @[TLB.scala:170:77]
assign _entries_T_187 = _entries_WIRE_15[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ae_final = _entries_T_187; // @[TLB.scala:170:77]
assign _entries_T_188 = _entries_WIRE_15[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ae_ptw = _entries_T_188; // @[TLB.scala:170:77]
assign _entries_T_189 = _entries_WIRE_15[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_g = _entries_T_189; // @[TLB.scala:170:77]
assign _entries_T_190 = _entries_WIRE_15[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_u = _entries_T_190; // @[TLB.scala:170:77]
assign _entries_T_191 = _entries_WIRE_15[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_14_ppn = _entries_T_191; // @[TLB.scala:170:77]
wire [19:0] _entries_T_214; // @[TLB.scala:170:77]
wire _entries_T_213; // @[TLB.scala:170:77]
wire _entries_T_212; // @[TLB.scala:170:77]
wire _entries_T_211; // @[TLB.scala:170:77]
wire _entries_T_210; // @[TLB.scala:170:77]
wire _entries_T_209; // @[TLB.scala:170:77]
wire _entries_T_208; // @[TLB.scala:170:77]
wire _entries_T_207; // @[TLB.scala:170:77]
wire _entries_T_206; // @[TLB.scala:170:77]
wire _entries_T_205; // @[TLB.scala:170:77]
wire _entries_T_204; // @[TLB.scala:170:77]
wire _entries_T_203; // @[TLB.scala:170:77]
wire _entries_T_202; // @[TLB.scala:170:77]
wire _entries_T_201; // @[TLB.scala:170:77]
wire _entries_T_200; // @[TLB.scala:170:77]
wire _entries_T_199; // @[TLB.scala:170:77]
wire _entries_T_198; // @[TLB.scala:170:77]
wire _entries_T_197; // @[TLB.scala:170:77]
wire _entries_T_196; // @[TLB.scala:170:77]
wire _entries_T_195; // @[TLB.scala:170:77]
wire _entries_T_194; // @[TLB.scala:170:77]
wire _entries_T_193; // @[TLB.scala:170:77]
wire _entries_T_192; // @[TLB.scala:170:77]
assign _entries_T_192 = _entries_WIRE_17[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_fragmented_superpage = _entries_T_192; // @[TLB.scala:170:77]
assign _entries_T_193 = _entries_WIRE_17[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_c = _entries_T_193; // @[TLB.scala:170:77]
assign _entries_T_194 = _entries_WIRE_17[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_eff = _entries_T_194; // @[TLB.scala:170:77]
assign _entries_T_195 = _entries_WIRE_17[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_paa = _entries_T_195; // @[TLB.scala:170:77]
assign _entries_T_196 = _entries_WIRE_17[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pal = _entries_T_196; // @[TLB.scala:170:77]
assign _entries_T_197 = _entries_WIRE_17[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ppp = _entries_T_197; // @[TLB.scala:170:77]
assign _entries_T_198 = _entries_WIRE_17[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pr = _entries_T_198; // @[TLB.scala:170:77]
assign _entries_T_199 = _entries_WIRE_17[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_px = _entries_T_199; // @[TLB.scala:170:77]
assign _entries_T_200 = _entries_WIRE_17[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pw = _entries_T_200; // @[TLB.scala:170:77]
assign _entries_T_201 = _entries_WIRE_17[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_hr = _entries_T_201; // @[TLB.scala:170:77]
assign _entries_T_202 = _entries_WIRE_17[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_hx = _entries_T_202; // @[TLB.scala:170:77]
assign _entries_T_203 = _entries_WIRE_17[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_hw = _entries_T_203; // @[TLB.scala:170:77]
assign _entries_T_204 = _entries_WIRE_17[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_sr = _entries_T_204; // @[TLB.scala:170:77]
assign _entries_T_205 = _entries_WIRE_17[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_sx = _entries_T_205; // @[TLB.scala:170:77]
assign _entries_T_206 = _entries_WIRE_17[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_sw = _entries_T_206; // @[TLB.scala:170:77]
assign _entries_T_207 = _entries_WIRE_17[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_gf = _entries_T_207; // @[TLB.scala:170:77]
assign _entries_T_208 = _entries_WIRE_17[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pf = _entries_T_208; // @[TLB.scala:170:77]
assign _entries_T_209 = _entries_WIRE_17[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ae_stage2 = _entries_T_209; // @[TLB.scala:170:77]
assign _entries_T_210 = _entries_WIRE_17[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ae_final = _entries_T_210; // @[TLB.scala:170:77]
assign _entries_T_211 = _entries_WIRE_17[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ae_ptw = _entries_T_211; // @[TLB.scala:170:77]
assign _entries_T_212 = _entries_WIRE_17[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_g = _entries_T_212; // @[TLB.scala:170:77]
assign _entries_T_213 = _entries_WIRE_17[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_u = _entries_T_213; // @[TLB.scala:170:77]
assign _entries_T_214 = _entries_WIRE_17[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_16_ppn = _entries_T_214; // @[TLB.scala:170:77]
wire [19:0] _entries_T_237; // @[TLB.scala:170:77]
wire _entries_T_236; // @[TLB.scala:170:77]
wire _entries_T_235; // @[TLB.scala:170:77]
wire _entries_T_234; // @[TLB.scala:170:77]
wire _entries_T_233; // @[TLB.scala:170:77]
wire _entries_T_232; // @[TLB.scala:170:77]
wire _entries_T_231; // @[TLB.scala:170:77]
wire _entries_T_230; // @[TLB.scala:170:77]
wire _entries_T_229; // @[TLB.scala:170:77]
wire _entries_T_228; // @[TLB.scala:170:77]
wire _entries_T_227; // @[TLB.scala:170:77]
wire _entries_T_226; // @[TLB.scala:170:77]
wire _entries_T_225; // @[TLB.scala:170:77]
wire _entries_T_224; // @[TLB.scala:170:77]
wire _entries_T_223; // @[TLB.scala:170:77]
wire _entries_T_222; // @[TLB.scala:170:77]
wire _entries_T_221; // @[TLB.scala:170:77]
wire _entries_T_220; // @[TLB.scala:170:77]
wire _entries_T_219; // @[TLB.scala:170:77]
wire _entries_T_218; // @[TLB.scala:170:77]
wire _entries_T_217; // @[TLB.scala:170:77]
wire _entries_T_216; // @[TLB.scala:170:77]
wire _entries_T_215; // @[TLB.scala:170:77]
assign _entries_T_215 = _entries_WIRE_19[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_fragmented_superpage = _entries_T_215; // @[TLB.scala:170:77]
assign _entries_T_216 = _entries_WIRE_19[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_c = _entries_T_216; // @[TLB.scala:170:77]
assign _entries_T_217 = _entries_WIRE_19[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_eff = _entries_T_217; // @[TLB.scala:170:77]
assign _entries_T_218 = _entries_WIRE_19[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_paa = _entries_T_218; // @[TLB.scala:170:77]
assign _entries_T_219 = _entries_WIRE_19[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pal = _entries_T_219; // @[TLB.scala:170:77]
assign _entries_T_220 = _entries_WIRE_19[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ppp = _entries_T_220; // @[TLB.scala:170:77]
assign _entries_T_221 = _entries_WIRE_19[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pr = _entries_T_221; // @[TLB.scala:170:77]
assign _entries_T_222 = _entries_WIRE_19[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_px = _entries_T_222; // @[TLB.scala:170:77]
assign _entries_T_223 = _entries_WIRE_19[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pw = _entries_T_223; // @[TLB.scala:170:77]
assign _entries_T_224 = _entries_WIRE_19[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_hr = _entries_T_224; // @[TLB.scala:170:77]
assign _entries_T_225 = _entries_WIRE_19[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_hx = _entries_T_225; // @[TLB.scala:170:77]
assign _entries_T_226 = _entries_WIRE_19[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_hw = _entries_T_226; // @[TLB.scala:170:77]
assign _entries_T_227 = _entries_WIRE_19[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_sr = _entries_T_227; // @[TLB.scala:170:77]
assign _entries_T_228 = _entries_WIRE_19[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_sx = _entries_T_228; // @[TLB.scala:170:77]
assign _entries_T_229 = _entries_WIRE_19[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_sw = _entries_T_229; // @[TLB.scala:170:77]
assign _entries_T_230 = _entries_WIRE_19[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_gf = _entries_T_230; // @[TLB.scala:170:77]
assign _entries_T_231 = _entries_WIRE_19[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pf = _entries_T_231; // @[TLB.scala:170:77]
assign _entries_T_232 = _entries_WIRE_19[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ae_stage2 = _entries_T_232; // @[TLB.scala:170:77]
assign _entries_T_233 = _entries_WIRE_19[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ae_final = _entries_T_233; // @[TLB.scala:170:77]
assign _entries_T_234 = _entries_WIRE_19[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ae_ptw = _entries_T_234; // @[TLB.scala:170:77]
assign _entries_T_235 = _entries_WIRE_19[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_g = _entries_T_235; // @[TLB.scala:170:77]
assign _entries_T_236 = _entries_WIRE_19[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_u = _entries_T_236; // @[TLB.scala:170:77]
assign _entries_T_237 = _entries_WIRE_19[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_18_ppn = _entries_T_237; // @[TLB.scala:170:77]
wire [19:0] _entries_T_260; // @[TLB.scala:170:77]
wire _entries_T_259; // @[TLB.scala:170:77]
wire _entries_T_258; // @[TLB.scala:170:77]
wire _entries_T_257; // @[TLB.scala:170:77]
wire _entries_T_256; // @[TLB.scala:170:77]
wire _entries_T_255; // @[TLB.scala:170:77]
wire _entries_T_254; // @[TLB.scala:170:77]
wire _entries_T_253; // @[TLB.scala:170:77]
wire _entries_T_252; // @[TLB.scala:170:77]
wire _entries_T_251; // @[TLB.scala:170:77]
wire _entries_T_250; // @[TLB.scala:170:77]
wire _entries_T_249; // @[TLB.scala:170:77]
wire _entries_T_248; // @[TLB.scala:170:77]
wire _entries_T_247; // @[TLB.scala:170:77]
wire _entries_T_246; // @[TLB.scala:170:77]
wire _entries_T_245; // @[TLB.scala:170:77]
wire _entries_T_244; // @[TLB.scala:170:77]
wire _entries_T_243; // @[TLB.scala:170:77]
wire _entries_T_242; // @[TLB.scala:170:77]
wire _entries_T_241; // @[TLB.scala:170:77]
wire _entries_T_240; // @[TLB.scala:170:77]
wire _entries_T_239; // @[TLB.scala:170:77]
wire _entries_T_238; // @[TLB.scala:170:77]
assign _entries_T_238 = _entries_WIRE_21[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_fragmented_superpage = _entries_T_238; // @[TLB.scala:170:77]
assign _entries_T_239 = _entries_WIRE_21[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_c = _entries_T_239; // @[TLB.scala:170:77]
assign _entries_T_240 = _entries_WIRE_21[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_eff = _entries_T_240; // @[TLB.scala:170:77]
assign _entries_T_241 = _entries_WIRE_21[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_paa = _entries_T_241; // @[TLB.scala:170:77]
assign _entries_T_242 = _entries_WIRE_21[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pal = _entries_T_242; // @[TLB.scala:170:77]
assign _entries_T_243 = _entries_WIRE_21[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ppp = _entries_T_243; // @[TLB.scala:170:77]
assign _entries_T_244 = _entries_WIRE_21[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pr = _entries_T_244; // @[TLB.scala:170:77]
assign _entries_T_245 = _entries_WIRE_21[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_px = _entries_T_245; // @[TLB.scala:170:77]
assign _entries_T_246 = _entries_WIRE_21[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pw = _entries_T_246; // @[TLB.scala:170:77]
assign _entries_T_247 = _entries_WIRE_21[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_hr = _entries_T_247; // @[TLB.scala:170:77]
assign _entries_T_248 = _entries_WIRE_21[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_hx = _entries_T_248; // @[TLB.scala:170:77]
assign _entries_T_249 = _entries_WIRE_21[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_hw = _entries_T_249; // @[TLB.scala:170:77]
assign _entries_T_250 = _entries_WIRE_21[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_sr = _entries_T_250; // @[TLB.scala:170:77]
assign _entries_T_251 = _entries_WIRE_21[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_sx = _entries_T_251; // @[TLB.scala:170:77]
assign _entries_T_252 = _entries_WIRE_21[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_sw = _entries_T_252; // @[TLB.scala:170:77]
assign _entries_T_253 = _entries_WIRE_21[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_gf = _entries_T_253; // @[TLB.scala:170:77]
assign _entries_T_254 = _entries_WIRE_21[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pf = _entries_T_254; // @[TLB.scala:170:77]
assign _entries_T_255 = _entries_WIRE_21[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ae_stage2 = _entries_T_255; // @[TLB.scala:170:77]
assign _entries_T_256 = _entries_WIRE_21[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ae_final = _entries_T_256; // @[TLB.scala:170:77]
assign _entries_T_257 = _entries_WIRE_21[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ae_ptw = _entries_T_257; // @[TLB.scala:170:77]
assign _entries_T_258 = _entries_WIRE_21[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_g = _entries_T_258; // @[TLB.scala:170:77]
assign _entries_T_259 = _entries_WIRE_21[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_u = _entries_T_259; // @[TLB.scala:170:77]
assign _entries_T_260 = _entries_WIRE_21[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_20_ppn = _entries_T_260; // @[TLB.scala:170:77]
wire [19:0] _entries_T_283; // @[TLB.scala:170:77]
wire _entries_T_282; // @[TLB.scala:170:77]
wire _entries_T_281; // @[TLB.scala:170:77]
wire _entries_T_280; // @[TLB.scala:170:77]
wire _entries_T_279; // @[TLB.scala:170:77]
wire _entries_T_278; // @[TLB.scala:170:77]
wire _entries_T_277; // @[TLB.scala:170:77]
wire _entries_T_276; // @[TLB.scala:170:77]
wire _entries_T_275; // @[TLB.scala:170:77]
wire _entries_T_274; // @[TLB.scala:170:77]
wire _entries_T_273; // @[TLB.scala:170:77]
wire _entries_T_272; // @[TLB.scala:170:77]
wire _entries_T_271; // @[TLB.scala:170:77]
wire _entries_T_270; // @[TLB.scala:170:77]
wire _entries_T_269; // @[TLB.scala:170:77]
wire _entries_T_268; // @[TLB.scala:170:77]
wire _entries_T_267; // @[TLB.scala:170:77]
wire _entries_T_266; // @[TLB.scala:170:77]
wire _entries_T_265; // @[TLB.scala:170:77]
wire _entries_T_264; // @[TLB.scala:170:77]
wire _entries_T_263; // @[TLB.scala:170:77]
wire _entries_T_262; // @[TLB.scala:170:77]
wire _entries_T_261; // @[TLB.scala:170:77]
assign _entries_T_261 = _entries_WIRE_23[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_fragmented_superpage = _entries_T_261; // @[TLB.scala:170:77]
assign _entries_T_262 = _entries_WIRE_23[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_c = _entries_T_262; // @[TLB.scala:170:77]
assign _entries_T_263 = _entries_WIRE_23[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_eff = _entries_T_263; // @[TLB.scala:170:77]
assign _entries_T_264 = _entries_WIRE_23[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_paa = _entries_T_264; // @[TLB.scala:170:77]
assign _entries_T_265 = _entries_WIRE_23[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pal = _entries_T_265; // @[TLB.scala:170:77]
assign _entries_T_266 = _entries_WIRE_23[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ppp = _entries_T_266; // @[TLB.scala:170:77]
assign _entries_T_267 = _entries_WIRE_23[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pr = _entries_T_267; // @[TLB.scala:170:77]
assign _entries_T_268 = _entries_WIRE_23[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_px = _entries_T_268; // @[TLB.scala:170:77]
assign _entries_T_269 = _entries_WIRE_23[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pw = _entries_T_269; // @[TLB.scala:170:77]
assign _entries_T_270 = _entries_WIRE_23[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_hr = _entries_T_270; // @[TLB.scala:170:77]
assign _entries_T_271 = _entries_WIRE_23[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_hx = _entries_T_271; // @[TLB.scala:170:77]
assign _entries_T_272 = _entries_WIRE_23[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_hw = _entries_T_272; // @[TLB.scala:170:77]
assign _entries_T_273 = _entries_WIRE_23[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_sr = _entries_T_273; // @[TLB.scala:170:77]
assign _entries_T_274 = _entries_WIRE_23[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_sx = _entries_T_274; // @[TLB.scala:170:77]
assign _entries_T_275 = _entries_WIRE_23[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_sw = _entries_T_275; // @[TLB.scala:170:77]
assign _entries_T_276 = _entries_WIRE_23[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_gf = _entries_T_276; // @[TLB.scala:170:77]
assign _entries_T_277 = _entries_WIRE_23[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pf = _entries_T_277; // @[TLB.scala:170:77]
assign _entries_T_278 = _entries_WIRE_23[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ae_stage2 = _entries_T_278; // @[TLB.scala:170:77]
assign _entries_T_279 = _entries_WIRE_23[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ae_final = _entries_T_279; // @[TLB.scala:170:77]
assign _entries_T_280 = _entries_WIRE_23[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ae_ptw = _entries_T_280; // @[TLB.scala:170:77]
assign _entries_T_281 = _entries_WIRE_23[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_g = _entries_T_281; // @[TLB.scala:170:77]
assign _entries_T_282 = _entries_WIRE_23[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_u = _entries_T_282; // @[TLB.scala:170:77]
assign _entries_T_283 = _entries_WIRE_23[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_22_ppn = _entries_T_283; // @[TLB.scala:170:77]
wire [19:0] _entries_T_306; // @[TLB.scala:170:77]
wire _entries_T_305; // @[TLB.scala:170:77]
wire _entries_T_304; // @[TLB.scala:170:77]
wire _entries_T_303; // @[TLB.scala:170:77]
wire _entries_T_302; // @[TLB.scala:170:77]
wire _entries_T_301; // @[TLB.scala:170:77]
wire _entries_T_300; // @[TLB.scala:170:77]
wire _entries_T_299; // @[TLB.scala:170:77]
wire _entries_T_298; // @[TLB.scala:170:77]
wire _entries_T_297; // @[TLB.scala:170:77]
wire _entries_T_296; // @[TLB.scala:170:77]
wire _entries_T_295; // @[TLB.scala:170:77]
wire _entries_T_294; // @[TLB.scala:170:77]
wire _entries_T_293; // @[TLB.scala:170:77]
wire _entries_T_292; // @[TLB.scala:170:77]
wire _entries_T_291; // @[TLB.scala:170:77]
wire _entries_T_290; // @[TLB.scala:170:77]
wire _entries_T_289; // @[TLB.scala:170:77]
wire _entries_T_288; // @[TLB.scala:170:77]
wire _entries_T_287; // @[TLB.scala:170:77]
wire _entries_T_286; // @[TLB.scala:170:77]
wire _entries_T_285; // @[TLB.scala:170:77]
wire _entries_T_284; // @[TLB.scala:170:77]
assign _entries_T_284 = _entries_WIRE_25[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_fragmented_superpage = _entries_T_284; // @[TLB.scala:170:77]
assign _entries_T_285 = _entries_WIRE_25[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_c = _entries_T_285; // @[TLB.scala:170:77]
assign _entries_T_286 = _entries_WIRE_25[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_eff = _entries_T_286; // @[TLB.scala:170:77]
assign _entries_T_287 = _entries_WIRE_25[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_paa = _entries_T_287; // @[TLB.scala:170:77]
assign _entries_T_288 = _entries_WIRE_25[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pal = _entries_T_288; // @[TLB.scala:170:77]
assign _entries_T_289 = _entries_WIRE_25[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ppp = _entries_T_289; // @[TLB.scala:170:77]
assign _entries_T_290 = _entries_WIRE_25[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pr = _entries_T_290; // @[TLB.scala:170:77]
assign _entries_T_291 = _entries_WIRE_25[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_px = _entries_T_291; // @[TLB.scala:170:77]
assign _entries_T_292 = _entries_WIRE_25[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pw = _entries_T_292; // @[TLB.scala:170:77]
assign _entries_T_293 = _entries_WIRE_25[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_hr = _entries_T_293; // @[TLB.scala:170:77]
assign _entries_T_294 = _entries_WIRE_25[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_hx = _entries_T_294; // @[TLB.scala:170:77]
assign _entries_T_295 = _entries_WIRE_25[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_hw = _entries_T_295; // @[TLB.scala:170:77]
assign _entries_T_296 = _entries_WIRE_25[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_sr = _entries_T_296; // @[TLB.scala:170:77]
assign _entries_T_297 = _entries_WIRE_25[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_sx = _entries_T_297; // @[TLB.scala:170:77]
assign _entries_T_298 = _entries_WIRE_25[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_sw = _entries_T_298; // @[TLB.scala:170:77]
assign _entries_T_299 = _entries_WIRE_25[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_gf = _entries_T_299; // @[TLB.scala:170:77]
assign _entries_T_300 = _entries_WIRE_25[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pf = _entries_T_300; // @[TLB.scala:170:77]
assign _entries_T_301 = _entries_WIRE_25[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ae_stage2 = _entries_T_301; // @[TLB.scala:170:77]
assign _entries_T_302 = _entries_WIRE_25[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ae_final = _entries_T_302; // @[TLB.scala:170:77]
assign _entries_T_303 = _entries_WIRE_25[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ae_ptw = _entries_T_303; // @[TLB.scala:170:77]
assign _entries_T_304 = _entries_WIRE_25[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_g = _entries_T_304; // @[TLB.scala:170:77]
assign _entries_T_305 = _entries_WIRE_25[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_u = _entries_T_305; // @[TLB.scala:170:77]
assign _entries_T_306 = _entries_WIRE_25[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_24_ppn = _entries_T_306; // @[TLB.scala:170:77]
wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30]
wire [1:0] ppn_res = _entries_barrier_8_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] | _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30]
wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] | _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}]
wire [1:0] ppn_res_1 = _entries_barrier_9_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] | _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_3 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :197:28, :341:30]
wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] | _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}]
wire [1:0] ppn_res_2 = _entries_barrier_10_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore_4 = _ppn_ignore_T_4; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_17 = ppn_ignore_4 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_18 = {_ppn_T_17[26:20], _ppn_T_17[19:0] | _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_19 = _ppn_T_18[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_20 = {ppn_res_2, _ppn_T_19}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_5 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :197:28, :341:30]
wire [26:0] _ppn_T_22 = {_ppn_T_21[26:20], _ppn_T_21[19:0] | _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_23 = _ppn_T_22[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_24 = {_ppn_T_20, _ppn_T_23}; // @[TLB.scala:198:{18,58}]
wire [1:0] ppn_res_3 = _entries_barrier_11_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore_6 = _ppn_ignore_T_6; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_25 = ppn_ignore_6 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_26 = {_ppn_T_25[26:20], _ppn_T_25[19:0] | _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_27 = _ppn_T_26[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_28 = {ppn_res_3, _ppn_T_27}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_7 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :197:28, :341:30]
wire [26:0] _ppn_T_30 = {_ppn_T_29[26:20], _ppn_T_29[19:0] | _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_31 = _ppn_T_30[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_32 = {_ppn_T_28, _ppn_T_31}; // @[TLB.scala:198:{18,58}]
wire [1:0] ppn_res_4 = _entries_barrier_12_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore_8 = _ppn_ignore_T_8; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_33 = ppn_ignore_8 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_34 = {_ppn_T_33[26:20], _ppn_T_33[19:0] | _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_35 = _ppn_T_34[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_36 = {ppn_res_4, _ppn_T_35}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_9 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56]
wire ppn_ignore_9 = _ppn_ignore_T_9; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_37 = ppn_ignore_9 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_38 = {_ppn_T_37[26:20], _ppn_T_37[19:0] | _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_39 = _ppn_T_38[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_40 = {_ppn_T_36, _ppn_T_39}; // @[TLB.scala:198:{18,58}]
wire [19:0] _ppn_T_41 = vpn[19:0]; // @[TLB.scala:335:30, :502:125]
wire [19:0] _ppn_T_42 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_43 = hitsVec_1 ? _entries_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_44 = hitsVec_2 ? _entries_barrier_2_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_45 = hitsVec_3 ? _entries_barrier_3_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_46 = hitsVec_4 ? _entries_barrier_4_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_47 = hitsVec_5 ? _entries_barrier_5_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_48 = hitsVec_6 ? _entries_barrier_6_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_49 = hitsVec_7 ? _entries_barrier_7_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_50 = hitsVec_8 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_51 = hitsVec_9 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_52 = hitsVec_10 ? _ppn_T_24 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_53 = hitsVec_11 ? _ppn_T_32 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_54 = hitsVec_12 ? _ppn_T_40 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_55 = _ppn_T ? _ppn_T_41 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_56 = _ppn_T_42 | _ppn_T_43; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_57 = _ppn_T_56 | _ppn_T_44; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_58 = _ppn_T_57 | _ppn_T_45; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_59 = _ppn_T_58 | _ppn_T_46; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_60 = _ppn_T_59 | _ppn_T_47; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_61 = _ppn_T_60 | _ppn_T_48; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_62 = _ppn_T_61 | _ppn_T_49; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_63 = _ppn_T_62 | _ppn_T_50; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_64 = _ppn_T_63 | _ppn_T_51; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_65 = _ppn_T_64 | _ppn_T_52; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_66 = _ppn_T_65 | _ppn_T_53; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_67 = _ppn_T_66 | _ppn_T_54; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_68 = _ppn_T_67 | _ppn_T_55; // @[Mux.scala:30:73]
wire [19:0] ppn = _ppn_T_68; // @[Mux.scala:30:73]
wire [1:0] ptw_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_ae_array_lo_lo = {ptw_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_ae_array_lo_hi = {ptw_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [5:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, ptw_ae_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ptw_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_ptw, _entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_ae_array_hi_lo = {ptw_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_ptw, _entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_ptw, _entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [3:0] ptw_ae_array_hi_hi = {ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, ptw_ae_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27]
wire [13:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27]
wire [1:0] final_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] final_ae_array_lo_lo = {final_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] final_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] final_ae_array_lo_hi = {final_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [5:0] final_ae_array_lo = {final_ae_array_lo_hi, final_ae_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] final_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_final, _entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] final_ae_array_hi_lo = {final_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] final_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_final, _entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] final_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_final, _entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [3:0] final_ae_array_hi_hi = {final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] final_ae_array_hi = {final_ae_array_hi_hi, final_ae_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27]
wire [13:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27]
wire [1:0] ptw_pf_array_lo_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_pf_array_lo_lo = {ptw_pf_array_lo_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_pf_array_lo_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_pf_array_lo_hi = {ptw_pf_array_lo_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [5:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, ptw_pf_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ptw_pf_array_hi_lo_hi = {_entries_barrier_8_io_y_pf, _entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_pf_array_hi_lo = {ptw_pf_array_hi_lo_hi, _entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_pf_array_hi_hi_lo = {_entries_barrier_10_io_y_pf, _entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_pf_array_hi_hi_hi = {_entries_barrier_12_io_y_pf, _entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [3:0] ptw_pf_array_hi_hi = {ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, ptw_pf_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27]
wire [13:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27]
wire [1:0] ptw_gf_array_lo_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_gf_array_lo_lo = {ptw_gf_array_lo_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_gf_array_lo_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_gf_array_lo_hi = {ptw_gf_array_lo_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [5:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, ptw_gf_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ptw_gf_array_hi_lo_hi = {_entries_barrier_8_io_y_gf, _entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_gf_array_hi_lo = {ptw_gf_array_hi_lo_hi, _entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_gf_array_hi_hi_lo = {_entries_barrier_10_io_y_gf, _entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_gf_array_hi_hi_hi = {_entries_barrier_12_io_y_gf, _entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [3:0] ptw_gf_array_hi_hi = {ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, ptw_gf_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27]
wire [13:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27]
wire [13:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82]
wire [13:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63]
wire [13:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46]
wire _priv_rw_ok_T = ~priv_s; // @[TLB.scala:370:20, :513:24]
wire _priv_rw_ok_T_1 = _priv_rw_ok_T | sum; // @[TLB.scala:510:16, :513:{24,32}]
wire [1:0] _GEN_40 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_lo_lo_hi; // @[package.scala:45:27]
assign priv_rw_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_lo_hi; // @[package.scala:45:27]
assign priv_x_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27]
assign priv_x_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_lo = {priv_rw_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_41 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_lo_hi_hi; // @[package.scala:45:27]
assign priv_rw_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_hi_hi; // @[package.scala:45:27]
assign priv_x_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27]
assign priv_x_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_hi = {priv_rw_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, priv_rw_ok_lo_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_42 = {_entries_barrier_8_io_y_u, _entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_hi_lo_hi; // @[package.scala:45:27]
assign priv_rw_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_lo_hi; // @[package.scala:45:27]
assign priv_x_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27]
assign priv_x_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_hi_lo = {priv_rw_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_43 = {_entries_barrier_10_io_y_u, _entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_hi_hi_lo; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_lo; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27]
wire [1:0] _GEN_44 = {_entries_barrier_12_io_y_u, _entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_hi_hi_hi; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_hi; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27]
wire [3:0] priv_rw_ok_hi_hi = {priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, priv_rw_ok_hi_lo}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_1 ? _priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_lo_1 = {priv_rw_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_rw_ok_lo_hi_1 = {priv_rw_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1}; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_hi_lo_1 = {priv_rw_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] priv_rw_ok_hi_hi_1 = {priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_6 = priv_s ? _priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}]
wire [12:0] priv_rw_ok = _priv_rw_ok_T_3 | _priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}]
wire [2:0] priv_x_ok_lo_lo = {priv_x_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_x_ok_lo_hi = {priv_x_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_x_ok_lo = {priv_x_ok_lo_hi, priv_x_ok_lo_lo}; // @[package.scala:45:27]
wire [2:0] priv_x_ok_hi_lo = {priv_x_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] priv_x_ok_hi_hi = {priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] priv_x_ok_hi = {priv_x_ok_hi_hi, priv_x_ok_hi_lo}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27]
wire [2:0] priv_x_ok_lo_lo_1 = {priv_x_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_x_ok_lo_hi_1 = {priv_x_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1}; // @[package.scala:45:27]
wire [2:0] priv_x_ok_hi_lo_1 = {priv_x_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] priv_x_ok_hi_hi_1 = {priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27]
wire [12:0] priv_x_ok = priv_s ? _priv_x_ok_T_1 : _priv_x_ok_T_2; // @[package.scala:45:27]
wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83]
wire [12:0] _stage1_bypass_T_2 = {13{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}]
wire [1:0] stage1_bypass_lo_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] stage1_bypass_lo_lo = {stage1_bypass_lo_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] stage1_bypass_lo_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] stage1_bypass_lo_hi = {stage1_bypass_lo_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [5:0] stage1_bypass_lo = {stage1_bypass_lo_hi, stage1_bypass_lo_lo}; // @[package.scala:45:27]
wire [1:0] stage1_bypass_hi_lo_hi = {_entries_barrier_8_io_y_ae_stage2, _entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] stage1_bypass_hi_lo = {stage1_bypass_hi_lo_hi, _entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] stage1_bypass_hi_hi_lo = {_entries_barrier_10_io_y_ae_stage2, _entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] stage1_bypass_hi_hi_hi = {_entries_barrier_12_io_y_ae_stage2, _entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [3:0] stage1_bypass_hi_hi = {stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] stage1_bypass_hi = {stage1_bypass_hi_hi, stage1_bypass_hi_lo}; // @[package.scala:45:27]
wire [12:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27]
wire [12:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 | _stage1_bypass_T_3; // @[package.scala:45:27]
wire [1:0] r_array_lo_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] r_array_lo_lo = {r_array_lo_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_lo_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] r_array_lo_hi = {r_array_lo_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [5:0] r_array_lo = {r_array_lo_hi, r_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] r_array_hi_lo_hi = {_entries_barrier_8_io_y_sr, _entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] r_array_hi_lo = {r_array_hi_lo_hi, _entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_lo = {_entries_barrier_10_io_y_sr, _entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_hi = {_entries_barrier_12_io_y_sr, _entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [3:0] r_array_hi_hi = {r_array_hi_hi_hi, r_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] r_array_hi = {r_array_hi_hi, r_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_45 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_lo_lo_hi_1; // @[package.scala:45:27]
assign r_array_lo_lo_hi_1 = _GEN_45; // @[package.scala:45:27]
wire [1:0] x_array_lo_lo_hi; // @[package.scala:45:27]
assign x_array_lo_lo_hi = _GEN_45; // @[package.scala:45:27]
wire [2:0] r_array_lo_lo_1 = {r_array_lo_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_46 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_lo_hi_hi_1; // @[package.scala:45:27]
assign r_array_lo_hi_hi_1 = _GEN_46; // @[package.scala:45:27]
wire [1:0] x_array_lo_hi_hi; // @[package.scala:45:27]
assign x_array_lo_hi_hi = _GEN_46; // @[package.scala:45:27]
wire [2:0] r_array_lo_hi_1 = {r_array_lo_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [5:0] r_array_lo_1 = {r_array_lo_hi_1, r_array_lo_lo_1}; // @[package.scala:45:27]
wire [1:0] _GEN_47 = {_entries_barrier_8_io_y_sx, _entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_lo_hi_1; // @[package.scala:45:27]
assign r_array_hi_lo_hi_1 = _GEN_47; // @[package.scala:45:27]
wire [1:0] x_array_hi_lo_hi; // @[package.scala:45:27]
assign x_array_hi_lo_hi = _GEN_47; // @[package.scala:45:27]
wire [2:0] r_array_hi_lo_1 = {r_array_hi_lo_hi_1, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_48 = {_entries_barrier_10_io_y_sx, _entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_lo_1; // @[package.scala:45:27]
assign r_array_hi_hi_lo_1 = _GEN_48; // @[package.scala:45:27]
wire [1:0] x_array_hi_hi_lo; // @[package.scala:45:27]
assign x_array_hi_hi_lo = _GEN_48; // @[package.scala:45:27]
wire [1:0] _GEN_49 = {_entries_barrier_12_io_y_sx, _entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_hi_1; // @[package.scala:45:27]
assign r_array_hi_hi_hi_1 = _GEN_49; // @[package.scala:45:27]
wire [1:0] x_array_hi_hi_hi; // @[package.scala:45:27]
assign x_array_hi_hi_hi = _GEN_49; // @[package.scala:45:27]
wire [3:0] r_array_hi_hi_1 = {r_array_hi_hi_hi_1, r_array_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] r_array_hi_1 = {r_array_hi_hi_1, r_array_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27]
wire [12:0] _r_array_T_2 = mxr ? _r_array_T_1 : 13'h0; // @[package.scala:45:27]
wire [12:0] _r_array_T_3 = _r_array_T | _r_array_T_2; // @[package.scala:45:27]
wire [12:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}]
wire [12:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}]
wire [13:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}]
wire [13:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41]
wire [1:0] w_array_lo_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] w_array_lo_lo = {w_array_lo_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] w_array_lo_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] w_array_lo_hi = {w_array_lo_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [5:0] w_array_lo = {w_array_lo_hi, w_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] w_array_hi_lo_hi = {_entries_barrier_8_io_y_sw, _entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] w_array_hi_lo = {w_array_hi_lo_hi, _entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] w_array_hi_hi_lo = {_entries_barrier_10_io_y_sw, _entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] w_array_hi_hi_hi = {_entries_barrier_12_io_y_sw, _entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [3:0] w_array_hi_hi = {w_array_hi_hi_hi, w_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] w_array_hi = {w_array_hi_hi, w_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27]
wire [12:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27]
wire [12:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}]
wire [13:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}]
wire [2:0] x_array_lo_lo = {x_array_lo_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [2:0] x_array_lo_hi = {x_array_lo_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [5:0] x_array_lo = {x_array_lo_hi, x_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] x_array_hi_lo = {x_array_hi_lo_hi, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [3:0] x_array_hi_hi = {x_array_hi_hi_hi, x_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] x_array_hi = {x_array_hi_hi, x_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27]
wire [12:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27]
wire [12:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}]
wire [13:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}]
wire [1:0] hr_array_lo_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] hr_array_lo_lo = {hr_array_lo_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_lo_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] hr_array_lo_hi = {hr_array_lo_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [5:0] hr_array_lo = {hr_array_lo_hi, hr_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] hr_array_hi_lo_hi = {_entries_barrier_8_io_y_hr, _entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] hr_array_hi_lo = {hr_array_hi_lo_hi, _entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_lo = {_entries_barrier_10_io_y_hr, _entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_hi = {_entries_barrier_12_io_y_hr, _entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [3:0] hr_array_hi_hi = {hr_array_hi_hi_hi, hr_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] hr_array_hi = {hr_array_hi_hi, hr_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_50 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_lo_lo_hi_1; // @[package.scala:45:27]
assign hr_array_lo_lo_hi_1 = _GEN_50; // @[package.scala:45:27]
wire [1:0] hx_array_lo_lo_hi; // @[package.scala:45:27]
assign hx_array_lo_lo_hi = _GEN_50; // @[package.scala:45:27]
wire [2:0] hr_array_lo_lo_1 = {hr_array_lo_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_51 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_lo_hi_hi_1; // @[package.scala:45:27]
assign hr_array_lo_hi_hi_1 = _GEN_51; // @[package.scala:45:27]
wire [1:0] hx_array_lo_hi_hi; // @[package.scala:45:27]
assign hx_array_lo_hi_hi = _GEN_51; // @[package.scala:45:27]
wire [2:0] hr_array_lo_hi_1 = {hr_array_lo_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [5:0] hr_array_lo_1 = {hr_array_lo_hi_1, hr_array_lo_lo_1}; // @[package.scala:45:27]
wire [1:0] _GEN_52 = {_entries_barrier_8_io_y_hx, _entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_lo_hi_1; // @[package.scala:45:27]
assign hr_array_hi_lo_hi_1 = _GEN_52; // @[package.scala:45:27]
wire [1:0] hx_array_hi_lo_hi; // @[package.scala:45:27]
assign hx_array_hi_lo_hi = _GEN_52; // @[package.scala:45:27]
wire [2:0] hr_array_hi_lo_1 = {hr_array_hi_lo_hi_1, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_53 = {_entries_barrier_10_io_y_hx, _entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_lo_1; // @[package.scala:45:27]
assign hr_array_hi_hi_lo_1 = _GEN_53; // @[package.scala:45:27]
wire [1:0] hx_array_hi_hi_lo; // @[package.scala:45:27]
assign hx_array_hi_hi_lo = _GEN_53; // @[package.scala:45:27]
wire [1:0] _GEN_54 = {_entries_barrier_12_io_y_hx, _entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_hi_1; // @[package.scala:45:27]
assign hr_array_hi_hi_hi_1 = _GEN_54; // @[package.scala:45:27]
wire [1:0] hx_array_hi_hi_hi; // @[package.scala:45:27]
assign hx_array_hi_hi_hi = _GEN_54; // @[package.scala:45:27]
wire [3:0] hr_array_hi_hi_1 = {hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] hr_array_hi_1 = {hr_array_hi_hi_1, hr_array_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27]
wire [12:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 13'h0; // @[package.scala:45:27]
wire [12:0] _hr_array_T_3 = _hr_array_T | _hr_array_T_2; // @[package.scala:45:27]
wire [1:0] hw_array_lo_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] hw_array_lo_lo = {hw_array_lo_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] hw_array_lo_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] hw_array_lo_hi = {hw_array_lo_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [5:0] hw_array_lo = {hw_array_lo_hi, hw_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] hw_array_hi_lo_hi = {_entries_barrier_8_io_y_hw, _entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] hw_array_hi_lo = {hw_array_hi_lo_hi, _entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] hw_array_hi_hi_lo = {_entries_barrier_10_io_y_hw, _entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] hw_array_hi_hi_hi = {_entries_barrier_12_io_y_hw, _entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [3:0] hw_array_hi_hi = {hw_array_hi_hi_hi, hw_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] hw_array_hi = {hw_array_hi_hi, hw_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27]
wire [2:0] hx_array_lo_lo = {hx_array_lo_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [2:0] hx_array_lo_hi = {hx_array_lo_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [5:0] hx_array_lo = {hx_array_lo_hi, hx_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] hx_array_hi_lo = {hx_array_hi_lo_hi, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [3:0] hx_array_hi_hi = {hx_array_hi_hi_hi, hx_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] hx_array_hi = {hx_array_hi_hi, hx_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27]
wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26]
wire [1:0] pr_array_lo_lo_hi = {_entries_barrier_2_io_y_pr, _entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_lo_lo = {pr_array_lo_lo_hi, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [1:0] pr_array_lo_hi_hi = {_entries_barrier_5_io_y_pr, _entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_lo_hi = {pr_array_lo_hi_hi, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [5:0] pr_array_lo = {pr_array_lo_hi, pr_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pr_array_hi_lo_hi = {_entries_barrier_8_io_y_pr, _entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_hi_lo = {pr_array_hi_lo_hi, _entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [1:0] pr_array_hi_hi_hi = {_entries_barrier_11_io_y_pr, _entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_hi_hi = {pr_array_hi_hi_hi, _entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [5:0] pr_array_hi = {pr_array_hi_hi, pr_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27]
wire [13:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27]
wire [13:0] _GEN_55 = ptw_ae_array | final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104]
wire [13:0] _pr_array_T_3; // @[TLB.scala:529:104]
assign _pr_array_T_3 = _GEN_55; // @[TLB.scala:529:104]
wire [13:0] _pw_array_T_3; // @[TLB.scala:531:104]
assign _pw_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :531:104]
wire [13:0] _px_array_T_3; // @[TLB.scala:533:104]
assign _px_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :533:104]
wire [13:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}]
wire [13:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}]
wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26]
wire [1:0] pw_array_lo_lo_hi = {_entries_barrier_2_io_y_pw, _entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_lo_lo = {pw_array_lo_lo_hi, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [1:0] pw_array_lo_hi_hi = {_entries_barrier_5_io_y_pw, _entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_lo_hi = {pw_array_lo_hi_hi, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [5:0] pw_array_lo = {pw_array_lo_hi, pw_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pw_array_hi_lo_hi = {_entries_barrier_8_io_y_pw, _entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_hi_lo = {pw_array_hi_lo_hi, _entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [1:0] pw_array_hi_hi_hi = {_entries_barrier_11_io_y_pw, _entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_hi_hi = {pw_array_hi_hi_hi, _entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [5:0] pw_array_hi = {pw_array_hi_hi, pw_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27]
wire [13:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27]
wire [13:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}]
wire [13:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}]
wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26]
wire [1:0] px_array_lo_lo_hi = {_entries_barrier_2_io_y_px, _entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_lo_lo = {px_array_lo_lo_hi, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25]
wire [1:0] px_array_lo_hi_hi = {_entries_barrier_5_io_y_px, _entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_lo_hi = {px_array_lo_hi_hi, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25]
wire [5:0] px_array_lo = {px_array_lo_hi, px_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] px_array_hi_lo_hi = {_entries_barrier_8_io_y_px, _entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_hi_lo = {px_array_hi_lo_hi, _entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25]
wire [1:0] px_array_hi_hi_hi = {_entries_barrier_11_io_y_px, _entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_hi_hi = {px_array_hi_hi_hi, _entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25]
wire [5:0] px_array_hi = {px_array_hi_hi, px_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27]
wire [13:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27]
wire [13:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}]
wire [13:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}]
wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27]
wire [1:0] eff_array_lo_lo_hi = {_entries_barrier_2_io_y_eff, _entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_lo_lo = {eff_array_lo_lo_hi, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [1:0] eff_array_lo_hi_hi = {_entries_barrier_5_io_y_eff, _entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_lo_hi = {eff_array_lo_hi_hi, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [5:0] eff_array_lo = {eff_array_lo_hi, eff_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] eff_array_hi_lo_hi = {_entries_barrier_8_io_y_eff, _entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_hi_lo = {eff_array_hi_lo_hi, _entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [1:0] eff_array_hi_hi_hi = {_entries_barrier_11_io_y_eff, _entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_hi_hi = {eff_array_hi_hi_hi, _entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [5:0] eff_array_hi = {eff_array_hi_hi, eff_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27]
wire [13:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27]
wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25]
wire [1:0] _GEN_56 = {_entries_barrier_2_io_y_c, _entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_lo_lo_hi; // @[package.scala:45:27]
assign c_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27]
wire [1:0] prefetchable_array_lo_lo_hi; // @[package.scala:45:27]
assign prefetchable_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27]
wire [2:0] c_array_lo_lo = {c_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_57 = {_entries_barrier_5_io_y_c, _entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_lo_hi_hi; // @[package.scala:45:27]
assign c_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27]
wire [1:0] prefetchable_array_lo_hi_hi; // @[package.scala:45:27]
assign prefetchable_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27]
wire [2:0] c_array_lo_hi = {c_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] c_array_lo = {c_array_lo_hi, c_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_58 = {_entries_barrier_8_io_y_c, _entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_hi_lo_hi; // @[package.scala:45:27]
assign c_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27]
wire [1:0] prefetchable_array_hi_lo_hi; // @[package.scala:45:27]
assign prefetchable_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27]
wire [2:0] c_array_hi_lo = {c_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_59 = {_entries_barrier_11_io_y_c, _entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_hi_hi_hi; // @[package.scala:45:27]
assign c_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27]
wire [1:0] prefetchable_array_hi_hi_hi; // @[package.scala:45:27]
assign prefetchable_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27]
wire [2:0] c_array_hi_hi = {c_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] c_array_hi = {c_array_hi_hi, c_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27]
wire [13:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27]
wire [13:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24]
wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27]
wire [1:0] ppp_array_lo_lo_hi = {_entries_barrier_2_io_y_ppp, _entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_lo_lo = {ppp_array_lo_lo_hi, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [1:0] ppp_array_lo_hi_hi = {_entries_barrier_5_io_y_ppp, _entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_lo_hi = {ppp_array_lo_hi_hi, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [5:0] ppp_array_lo = {ppp_array_lo_hi, ppp_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ppp_array_hi_lo_hi = {_entries_barrier_8_io_y_ppp, _entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_hi_lo = {ppp_array_hi_lo_hi, _entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [1:0] ppp_array_hi_hi_hi = {_entries_barrier_11_io_y_ppp, _entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_hi_hi = {ppp_array_hi_hi_hi, _entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [5:0] ppp_array_hi = {ppp_array_hi_hi, ppp_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27]
wire [13:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27]
wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27]
wire [1:0] paa_array_lo_lo_hi = {_entries_barrier_2_io_y_paa, _entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_lo_lo = {paa_array_lo_lo_hi, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [1:0] paa_array_lo_hi_hi = {_entries_barrier_5_io_y_paa, _entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_lo_hi = {paa_array_lo_hi_hi, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [5:0] paa_array_lo = {paa_array_lo_hi, paa_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] paa_array_hi_lo_hi = {_entries_barrier_8_io_y_paa, _entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_hi_lo = {paa_array_hi_lo_hi, _entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [1:0] paa_array_hi_hi_hi = {_entries_barrier_11_io_y_paa, _entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_hi_hi = {paa_array_hi_hi_hi, _entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [5:0] paa_array_hi = {paa_array_hi_hi, paa_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27]
wire [13:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27]
wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27]
wire [1:0] pal_array_lo_lo_hi = {_entries_barrier_2_io_y_pal, _entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_lo_lo = {pal_array_lo_lo_hi, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [1:0] pal_array_lo_hi_hi = {_entries_barrier_5_io_y_pal, _entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_lo_hi = {pal_array_lo_hi_hi, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [5:0] pal_array_lo = {pal_array_lo_hi, pal_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pal_array_hi_lo_hi = {_entries_barrier_8_io_y_pal, _entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_hi_lo = {pal_array_hi_lo_hi, _entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [1:0] pal_array_hi_hi_hi = {_entries_barrier_11_io_y_pal, _entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_hi_hi = {pal_array_hi_hi_hi, _entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [5:0] pal_array_hi = {pal_array_hi_hi, pal_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27]
wire [13:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27]
wire [13:0] ppp_array_if_cached = ppp_array | c_array; // @[TLB.scala:537:20, :539:22, :544:39]
wire [13:0] paa_array_if_cached = paa_array | c_array; // @[TLB.scala:537:20, :541:22, :545:39]
wire [13:0] pal_array_if_cached = pal_array | c_array; // @[TLB.scala:537:20, :543:22, :546:39]
wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65]
wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}]
wire [2:0] prefetchable_array_lo_lo = {prefetchable_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25]
wire [2:0] prefetchable_array_lo_hi = {prefetchable_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] prefetchable_array_lo = {prefetchable_array_lo_hi, prefetchable_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] prefetchable_array_hi_lo = {prefetchable_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25]
wire [2:0] prefetchable_array_hi_hi = {prefetchable_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] prefetchable_array_hi = {prefetchable_array_hi_hi, prefetchable_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27]
wire [13:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27]
wire [39:0] _misaligned_T_3 = {36'h0, io_req_bits_vaddr_0[3:0]}; // @[TLB.scala:318:7, :550:39]
wire misaligned = |_misaligned_T_3; // @[TLB.scala:550:{39,77}]
assign _io_resp_ma_ld_T = misaligned; // @[TLB.scala:550:77, :645:31]
wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21]
wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43]
wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:559:43, :560:51]
wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86]
wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}]
wire _bad_va_T_5 = _bad_va_T_2 | _bad_va_T_4; // @[TLB.scala:560:{51,59,71}]
wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}]
wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}]
wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}]
wire _io_resp_pf_ld_T = bad_va; // @[TLB.scala:568:34, :633:28]
wire [13:0] _ae_array_T = misaligned ? eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8]
wire [13:0] ae_array = _ae_array_T; // @[TLB.scala:582:{8,37}]
wire [13:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19]
wire [13:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46]
wire [13:0] _ae_ld_array_T_1 = ae_array | _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}]
wire [13:0] ae_ld_array = _ae_ld_array_T_1; // @[TLB.scala:586:{24,44}]
wire [13:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37]
wire [13:0] _ae_st_array_T_1 = ae_array | _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}]
wire [13:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26]
wire [13:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26]
wire [13:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29]
wire [13:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26]
wire [13:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26]
wire [13:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29]
wire [13:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}]
wire [13:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73]
wire [13:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}]
wire [13:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 | ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}]
wire [13:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106]
wire [13:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}]
wire [13:0] pf_ld_array = _pf_ld_array_T_6; // @[TLB.scala:597:{24,104}]
wire [13:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44]
wire [13:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55]
wire [13:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}]
wire [13:0] _pf_st_array_T_3 = _pf_st_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}]
wire [13:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88]
wire [13:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}]
wire [13:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25]
wire [13:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36]
wire [13:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}]
wire [13:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}]
wire [13:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69]
wire [13:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}]
wire [13:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100]
wire [13:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}]
wire [13:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81]
wire [13:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}]
wire [13:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64]
wire [13:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}]
wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73]
wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}]
wire [11:0] _gpa_hits_hit_mask_T_2 = {12{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}]
wire tlb_hit_if_not_gpa_miss = |real_hits; // @[package.scala:45:27]
wire tlb_hit = |_tlb_hit_T; // @[TLB.scala:611:{28,40}]
wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56]
wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}]
wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67]
wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}]
reg [6:0] state_vec_0; // @[Replacement.scala:305:17]
reg [2:0] state_reg_1; // @[Replacement.scala:168:70]
wire [1:0] _GEN_60 = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45]
wire [1:0] lo_lo; // @[OneHot.scala:21:45]
assign lo_lo = _GEN_60; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_lo_lo; // @[OneHot.scala:21:45]
assign r_sectored_hit_bits_lo_lo = _GEN_60; // @[OneHot.scala:21:45]
wire [1:0] _GEN_61 = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45]
wire [1:0] lo_hi; // @[OneHot.scala:21:45]
assign lo_hi = _GEN_61; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_lo_hi; // @[OneHot.scala:21:45]
assign r_sectored_hit_bits_lo_hi = _GEN_61; // @[OneHot.scala:21:45]
wire [3:0] lo = {lo_hi, lo_lo}; // @[OneHot.scala:21:45]
wire [3:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18]
wire [1:0] _GEN_62 = {sector_hits_5, sector_hits_4}; // @[OneHot.scala:21:45]
wire [1:0] hi_lo; // @[OneHot.scala:21:45]
assign hi_lo = _GEN_62; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_hi_lo; // @[OneHot.scala:21:45]
assign r_sectored_hit_bits_hi_lo = _GEN_62; // @[OneHot.scala:21:45]
wire [1:0] _GEN_63 = {sector_hits_7, sector_hits_6}; // @[OneHot.scala:21:45]
wire [1:0] hi_hi; // @[OneHot.scala:21:45]
assign hi_hi = _GEN_63; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_hi_hi; // @[OneHot.scala:21:45]
assign r_sectored_hit_bits_hi_hi = _GEN_63; // @[OneHot.scala:21:45]
wire [3:0] hi = {hi_hi, hi_lo}; // @[OneHot.scala:21:45]
wire [3:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18]
wire [3:0] _T_33 = hi_1 | lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] hi_2 = _T_33[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] lo_2 = _T_33[1:0]; // @[OneHot.scala:31:18, :32:28]
wire [2:0] state_vec_0_touch_way_sized = {|hi_1, |hi_2, hi_2[1] | lo_2[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire _state_vec_0_set_left_older_T = state_vec_0_touch_way_sized[2]; // @[package.scala:163:13]
wire state_vec_0_set_left_older = ~_state_vec_0_set_left_older_T; // @[Replacement.scala:196:{33,43}]
wire [2:0] state_vec_0_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13]
wire [2:0] r_sectored_repl_addr_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13]
wire [2:0] state_vec_0_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :305:17]
wire [2:0] r_sectored_repl_addr_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :245:38, :305:17]
wire [1:0] _state_vec_0_T = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13]
wire [1:0] _state_vec_0_T_11 = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13]
wire _state_vec_0_set_left_older_T_1 = _state_vec_0_T[1]; // @[package.scala:163:13]
wire state_vec_0_set_left_older_1 = ~_state_vec_0_set_left_older_T_1; // @[Replacement.scala:196:{33,43}]
wire state_vec_0_left_subtree_state_1 = state_vec_0_left_subtree_state[1]; // @[package.scala:163:13]
wire state_vec_0_right_subtree_state_1 = state_vec_0_left_subtree_state[0]; // @[package.scala:163:13]
wire _state_vec_0_T_1 = _state_vec_0_T[0]; // @[package.scala:163:13]
wire _state_vec_0_T_5 = _state_vec_0_T[0]; // @[package.scala:163:13]
wire _state_vec_0_T_2 = _state_vec_0_T_1; // @[package.scala:163:13]
wire _state_vec_0_T_3 = ~_state_vec_0_T_2; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_4 = state_vec_0_set_left_older_1 ? state_vec_0_left_subtree_state_1 : _state_vec_0_T_3; // @[package.scala:163:13]
wire _state_vec_0_T_6 = _state_vec_0_T_5; // @[Replacement.scala:207:62, :218:17]
wire _state_vec_0_T_7 = ~_state_vec_0_T_6; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_8 = state_vec_0_set_left_older_1 ? _state_vec_0_T_7 : state_vec_0_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_vec_0_hi = {state_vec_0_set_left_older_1, _state_vec_0_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_vec_0_T_9 = {state_vec_0_hi, _state_vec_0_T_8}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_vec_0_T_10 = state_vec_0_set_left_older ? state_vec_0_left_subtree_state : _state_vec_0_T_9; // @[package.scala:163:13]
wire _state_vec_0_set_left_older_T_2 = _state_vec_0_T_11[1]; // @[Replacement.scala:196:43, :207:62]
wire state_vec_0_set_left_older_2 = ~_state_vec_0_set_left_older_T_2; // @[Replacement.scala:196:{33,43}]
wire state_vec_0_left_subtree_state_2 = state_vec_0_right_subtree_state[1]; // @[package.scala:163:13]
wire state_vec_0_right_subtree_state_2 = state_vec_0_right_subtree_state[0]; // @[Replacement.scala:198:38]
wire _state_vec_0_T_12 = _state_vec_0_T_11[0]; // @[package.scala:163:13]
wire _state_vec_0_T_16 = _state_vec_0_T_11[0]; // @[package.scala:163:13]
wire _state_vec_0_T_13 = _state_vec_0_T_12; // @[package.scala:163:13]
wire _state_vec_0_T_14 = ~_state_vec_0_T_13; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_15 = state_vec_0_set_left_older_2 ? state_vec_0_left_subtree_state_2 : _state_vec_0_T_14; // @[package.scala:163:13]
wire _state_vec_0_T_17 = _state_vec_0_T_16; // @[Replacement.scala:207:62, :218:17]
wire _state_vec_0_T_18 = ~_state_vec_0_T_17; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_19 = state_vec_0_set_left_older_2 ? _state_vec_0_T_18 : state_vec_0_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_vec_0_hi_1 = {state_vec_0_set_left_older_2, _state_vec_0_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_vec_0_T_20 = {state_vec_0_hi_1, _state_vec_0_T_19}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_vec_0_T_21 = state_vec_0_set_left_older ? _state_vec_0_T_20 : state_vec_0_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16]
wire [3:0] state_vec_0_hi_2 = {state_vec_0_set_left_older, _state_vec_0_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [6:0] _state_vec_0_T_22 = {state_vec_0_hi_2, _state_vec_0_T_21}; // @[Replacement.scala:202:12, :206:16]
wire [1:0] _GEN_64 = {superpage_hits_1, superpage_hits_0}; // @[OneHot.scala:21:45]
wire [1:0] lo_3; // @[OneHot.scala:21:45]
assign lo_3 = _GEN_64; // @[OneHot.scala:21:45]
wire [1:0] r_superpage_hit_bits_lo; // @[OneHot.scala:21:45]
assign r_superpage_hit_bits_lo = _GEN_64; // @[OneHot.scala:21:45]
wire [1:0] lo_4 = lo_3; // @[OneHot.scala:21:45, :31:18]
wire [1:0] _GEN_65 = {superpage_hits_3, superpage_hits_2}; // @[OneHot.scala:21:45]
wire [1:0] hi_3; // @[OneHot.scala:21:45]
assign hi_3 = _GEN_65; // @[OneHot.scala:21:45]
wire [1:0] r_superpage_hit_bits_hi; // @[OneHot.scala:21:45]
assign r_superpage_hit_bits_hi = _GEN_65; // @[OneHot.scala:21:45]
wire [1:0] hi_4 = hi_3; // @[OneHot.scala:21:45, :30:18]
wire [1:0] state_reg_touch_way_sized = {|hi_4, hi_4[1] | lo_4[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire _state_reg_set_left_older_T = state_reg_touch_way_sized[1]; // @[package.scala:163:13]
wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13]
wire r_superpage_repl_addr_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38]
wire r_superpage_repl_addr_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38, :245:38]
wire _state_reg_T = state_reg_touch_way_sized[0]; // @[package.scala:163:13]
wire _state_reg_T_4 = state_reg_touch_way_sized[0]; // @[package.scala:163:13]
wire _state_reg_T_1 = _state_reg_T; // @[package.scala:163:13]
wire _state_reg_T_2 = ~_state_reg_T_1; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_3 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_2; // @[package.scala:163:13]
wire _state_reg_T_5 = _state_reg_T_4; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_6 = ~_state_reg_T_5; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_7 = state_reg_set_left_older ? _state_reg_T_6 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi = {state_reg_set_left_older, _state_reg_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_8 = {state_reg_hi, _state_reg_T_7}; // @[Replacement.scala:202:12, :206:16]
wire [5:0] _multipleHits_T = real_hits[5:0]; // @[package.scala:45:27]
wire [2:0] _multipleHits_T_1 = _multipleHits_T[2:0]; // @[Misc.scala:181:37]
wire _multipleHits_T_2 = _multipleHits_T_1[0]; // @[Misc.scala:181:37]
wire multipleHits_leftOne = _multipleHits_T_2; // @[Misc.scala:178:18, :181:37]
wire [1:0] _multipleHits_T_3 = _multipleHits_T_1[2:1]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_4 = _multipleHits_T_3[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_1 = _multipleHits_T_4; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_5 = _multipleHits_T_3[1]; // @[Misc.scala:182:39]
wire multipleHits_rightOne = _multipleHits_T_5; // @[Misc.scala:178:18, :182:39]
wire multipleHits_rightOne_1 = multipleHits_leftOne_1 | multipleHits_rightOne; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_7 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61]
wire multipleHits_rightTwo = _multipleHits_T_7; // @[Misc.scala:183:{49,61}]
wire _multipleHits_T_8 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}]
wire multipleHits_leftOne_2 = multipleHits_leftOne | multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_9 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}]
wire multipleHits_leftTwo = _multipleHits_T_8 | _multipleHits_T_9; // @[Misc.scala:183:{37,49,61}]
wire [2:0] _multipleHits_T_10 = _multipleHits_T[5:3]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_11 = _multipleHits_T_10[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_3 = _multipleHits_T_11; // @[Misc.scala:178:18, :181:37]
wire [1:0] _multipleHits_T_12 = _multipleHits_T_10[2:1]; // @[Misc.scala:182:39]
wire _multipleHits_T_13 = _multipleHits_T_12[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_4 = _multipleHits_T_13; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_14 = _multipleHits_T_12[1]; // @[Misc.scala:182:39]
wire multipleHits_rightOne_2 = _multipleHits_T_14; // @[Misc.scala:178:18, :182:39]
wire multipleHits_rightOne_3 = multipleHits_leftOne_4 | multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_16 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61]
wire multipleHits_rightTwo_1 = _multipleHits_T_16; // @[Misc.scala:183:{49,61}]
wire _multipleHits_T_17 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}]
wire multipleHits_rightOne_4 = multipleHits_leftOne_3 | multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_18 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}]
wire multipleHits_rightTwo_2 = _multipleHits_T_17 | _multipleHits_T_18; // @[Misc.scala:183:{37,49,61}]
wire multipleHits_leftOne_5 = multipleHits_leftOne_2 | multipleHits_rightOne_4; // @[Misc.scala:183:16]
wire _multipleHits_T_19 = multipleHits_leftTwo | multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}]
wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}]
wire multipleHits_leftTwo_1 = _multipleHits_T_19 | _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}]
wire [6:0] _multipleHits_T_21 = real_hits[12:6]; // @[package.scala:45:27]
wire [2:0] _multipleHits_T_22 = _multipleHits_T_21[2:0]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_23 = _multipleHits_T_22[0]; // @[Misc.scala:181:37]
wire multipleHits_leftOne_6 = _multipleHits_T_23; // @[Misc.scala:178:18, :181:37]
wire [1:0] _multipleHits_T_24 = _multipleHits_T_22[2:1]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_25 = _multipleHits_T_24[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_7 = _multipleHits_T_25; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_26 = _multipleHits_T_24[1]; // @[Misc.scala:182:39]
wire multipleHits_rightOne_5 = _multipleHits_T_26; // @[Misc.scala:178:18, :182:39]
wire multipleHits_rightOne_6 = multipleHits_leftOne_7 | multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_28 = multipleHits_leftOne_7 & multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:61]
wire multipleHits_rightTwo_3 = _multipleHits_T_28; // @[Misc.scala:183:{49,61}]
wire _multipleHits_T_29 = multipleHits_rightTwo_3; // @[Misc.scala:183:{37,49}]
wire multipleHits_leftOne_8 = multipleHits_leftOne_6 | multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_30 = multipleHits_leftOne_6 & multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:{16,61}]
wire multipleHits_leftTwo_2 = _multipleHits_T_29 | _multipleHits_T_30; // @[Misc.scala:183:{37,49,61}]
wire [3:0] _multipleHits_T_31 = _multipleHits_T_21[6:3]; // @[Misc.scala:182:39]
wire [1:0] _multipleHits_T_32 = _multipleHits_T_31[1:0]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_33 = _multipleHits_T_32[0]; // @[Misc.scala:181:37]
wire multipleHits_leftOne_9 = _multipleHits_T_33; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_34 = _multipleHits_T_32[1]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_rightOne_7 = _multipleHits_T_34; // @[Misc.scala:178:18, :182:39]
wire multipleHits_leftOne_10 = multipleHits_leftOne_9 | multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_36 = multipleHits_leftOne_9 & multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:61]
wire multipleHits_leftTwo_3 = _multipleHits_T_36; // @[Misc.scala:183:{49,61}]
wire [1:0] _multipleHits_T_37 = _multipleHits_T_31[3:2]; // @[Misc.scala:182:39]
wire _multipleHits_T_38 = _multipleHits_T_37[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_11 = _multipleHits_T_38; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_39 = _multipleHits_T_37[1]; // @[Misc.scala:182:39]
wire multipleHits_rightOne_8 = _multipleHits_T_39; // @[Misc.scala:178:18, :182:39]
wire multipleHits_rightOne_9 = multipleHits_leftOne_11 | multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_41 = multipleHits_leftOne_11 & multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:61]
wire multipleHits_rightTwo_4 = _multipleHits_T_41; // @[Misc.scala:183:{49,61}]
wire multipleHits_rightOne_10 = multipleHits_leftOne_10 | multipleHits_rightOne_9; // @[Misc.scala:183:16]
wire _multipleHits_T_42 = multipleHits_leftTwo_3 | multipleHits_rightTwo_4; // @[Misc.scala:183:{37,49}]
wire _multipleHits_T_43 = multipleHits_leftOne_10 & multipleHits_rightOne_9; // @[Misc.scala:183:{16,61}]
wire multipleHits_rightTwo_5 = _multipleHits_T_42 | _multipleHits_T_43; // @[Misc.scala:183:{37,49,61}]
wire multipleHits_rightOne_11 = multipleHits_leftOne_8 | multipleHits_rightOne_10; // @[Misc.scala:183:16]
wire _multipleHits_T_44 = multipleHits_leftTwo_2 | multipleHits_rightTwo_5; // @[Misc.scala:183:{37,49}]
wire _multipleHits_T_45 = multipleHits_leftOne_8 & multipleHits_rightOne_10; // @[Misc.scala:183:{16,61}]
wire multipleHits_rightTwo_6 = _multipleHits_T_44 | _multipleHits_T_45; // @[Misc.scala:183:{37,49,61}]
wire _multipleHits_T_46 = multipleHits_leftOne_5 | multipleHits_rightOne_11; // @[Misc.scala:183:16]
wire _multipleHits_T_47 = multipleHits_leftTwo_1 | multipleHits_rightTwo_6; // @[Misc.scala:183:{37,49}]
wire _multipleHits_T_48 = multipleHits_leftOne_5 & multipleHits_rightOne_11; // @[Misc.scala:183:{16,61}]
wire multipleHits = _multipleHits_T_47 | _multipleHits_T_48; // @[Misc.scala:183:{37,49,61}]
assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25]
assign io_req_ready = _io_req_ready_T; // @[TLB.scala:318:7, :631:25]
wire [13:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57]
wire _io_resp_pf_ld_T_2 = |_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}]
assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T | _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}]
assign io_resp_pf_ld_0 = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41]
wire [13:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47]
wire _io_resp_pf_inst_T_1 = |_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}]
assign _io_resp_pf_inst_T_2 = bad_va | _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}]
assign io_resp_pf_inst_0 = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29]
wire [13:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33]
assign _io_resp_ae_ld_T_1 = |_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}]
assign io_resp_ae_ld_0 = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41]
wire [13:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23]
wire [13:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}]
assign _io_resp_ae_inst_T_2 = |_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}]
assign io_resp_ae_inst_0 = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41]
assign io_resp_ma_ld_0 = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31]
wire [13:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33]
assign _io_resp_cacheable_T_1 = |_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}]
assign io_resp_cacheable_0 = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41]
wire [13:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47]
wire _io_resp_prefetchable_T_1 = |_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}]
assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}]
assign io_resp_prefetchable_0 = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59]
wire _io_resp_miss_T_1 = _io_resp_miss_T | tlb_miss; // @[TLB.scala:613:64, :651:{29,52}]
assign _io_resp_miss_T_2 = _io_resp_miss_T_1 | multipleHits; // @[Misc.scala:183:49]
assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64]
assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73]
assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23]
wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36]
wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}]
wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58]
wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47]
wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}]
assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8]
assign io_resp_gpa_0 = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8]
assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29]
wire r_superpage_repl_addr_left_subtree_older = state_reg_1[2]; // @[Replacement.scala:168:70, :243:38]
wire _r_superpage_repl_addr_T = r_superpage_repl_addr_left_subtree_state; // @[package.scala:163:13]
wire _r_superpage_repl_addr_T_1 = r_superpage_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12]
wire _r_superpage_repl_addr_T_2 = r_superpage_repl_addr_left_subtree_older ? _r_superpage_repl_addr_T : _r_superpage_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_superpage_repl_addr_T_3 = {r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [1:0] r_superpage_repl_addr_valids_lo = {superpage_entries_1_valid_0, superpage_entries_0_valid_0}; // @[package.scala:45:27]
wire [1:0] r_superpage_repl_addr_valids_hi = {superpage_entries_3_valid_0, superpage_entries_2_valid_0}; // @[package.scala:45:27]
wire [3:0] r_superpage_repl_addr_valids = {r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo}; // @[package.scala:45:27]
wire _r_superpage_repl_addr_T_4 = &r_superpage_repl_addr_valids; // @[package.scala:45:27]
wire [3:0] _r_superpage_repl_addr_T_5 = ~r_superpage_repl_addr_valids; // @[package.scala:45:27]
wire _r_superpage_repl_addr_T_6 = _r_superpage_repl_addr_T_5[0]; // @[OneHot.scala:48:45]
wire _r_superpage_repl_addr_T_7 = _r_superpage_repl_addr_T_5[1]; // @[OneHot.scala:48:45]
wire _r_superpage_repl_addr_T_8 = _r_superpage_repl_addr_T_5[2]; // @[OneHot.scala:48:45]
wire _r_superpage_repl_addr_T_9 = _r_superpage_repl_addr_T_5[3]; // @[OneHot.scala:48:45]
wire [1:0] _r_superpage_repl_addr_T_10 = {1'h1, ~_r_superpage_repl_addr_T_8}; // @[OneHot.scala:48:45]
wire [1:0] _r_superpage_repl_addr_T_11 = _r_superpage_repl_addr_T_7 ? 2'h1 : _r_superpage_repl_addr_T_10; // @[OneHot.scala:48:45]
wire [1:0] _r_superpage_repl_addr_T_12 = _r_superpage_repl_addr_T_6 ? 2'h0 : _r_superpage_repl_addr_T_11; // @[OneHot.scala:48:45]
wire [1:0] _r_superpage_repl_addr_T_13 = _r_superpage_repl_addr_T_4 ? _r_superpage_repl_addr_T_3 : _r_superpage_repl_addr_T_12; // @[Mux.scala:50:70]
wire r_sectored_repl_addr_left_subtree_older = state_vec_0[6]; // @[Replacement.scala:243:38, :305:17]
wire r_sectored_repl_addr_left_subtree_older_1 = r_sectored_repl_addr_left_subtree_state[2]; // @[package.scala:163:13]
wire r_sectored_repl_addr_left_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[1]; // @[package.scala:163:13]
wire _r_sectored_repl_addr_T = r_sectored_repl_addr_left_subtree_state_1; // @[package.scala:163:13]
wire r_sectored_repl_addr_right_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[0]; // @[package.scala:163:13]
wire _r_sectored_repl_addr_T_1 = r_sectored_repl_addr_right_subtree_state_1; // @[Replacement.scala:245:38, :262:12]
wire _r_sectored_repl_addr_T_2 = r_sectored_repl_addr_left_subtree_older_1 ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_sectored_repl_addr_T_3 = {r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire r_sectored_repl_addr_left_subtree_older_2 = r_sectored_repl_addr_right_subtree_state[2]; // @[Replacement.scala:243:38, :245:38]
wire r_sectored_repl_addr_left_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[1]; // @[package.scala:163:13]
wire _r_sectored_repl_addr_T_4 = r_sectored_repl_addr_left_subtree_state_2; // @[package.scala:163:13]
wire r_sectored_repl_addr_right_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[0]; // @[Replacement.scala:245:38]
wire _r_sectored_repl_addr_T_5 = r_sectored_repl_addr_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12]
wire _r_sectored_repl_addr_T_6 = r_sectored_repl_addr_left_subtree_older_2 ? _r_sectored_repl_addr_T_4 : _r_sectored_repl_addr_T_5; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_sectored_repl_addr_T_7 = {r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [1:0] _r_sectored_repl_addr_T_8 = r_sectored_repl_addr_left_subtree_older ? _r_sectored_repl_addr_T_3 : _r_sectored_repl_addr_T_7; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [2:0] _r_sectored_repl_addr_T_9 = {r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire _r_sectored_repl_addr_valids_T_1 = _r_sectored_repl_addr_valids_T | sectored_entries_0_0_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_2 = _r_sectored_repl_addr_valids_T_1 | sectored_entries_0_0_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_4 = _r_sectored_repl_addr_valids_T_3 | sectored_entries_0_1_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_5 = _r_sectored_repl_addr_valids_T_4 | sectored_entries_0_1_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_7 = _r_sectored_repl_addr_valids_T_6 | sectored_entries_0_2_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_8 = _r_sectored_repl_addr_valids_T_7 | sectored_entries_0_2_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_10 = _r_sectored_repl_addr_valids_T_9 | sectored_entries_0_3_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_11 = _r_sectored_repl_addr_valids_T_10 | sectored_entries_0_3_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_13 = _r_sectored_repl_addr_valids_T_12 | sectored_entries_0_4_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_14 = _r_sectored_repl_addr_valids_T_13 | sectored_entries_0_4_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_16 = _r_sectored_repl_addr_valids_T_15 | sectored_entries_0_5_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_17 = _r_sectored_repl_addr_valids_T_16 | sectored_entries_0_5_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_19 = _r_sectored_repl_addr_valids_T_18 | sectored_entries_0_6_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_20 = _r_sectored_repl_addr_valids_T_19 | sectored_entries_0_6_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_22 = _r_sectored_repl_addr_valids_T_21 | sectored_entries_0_7_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_23 = _r_sectored_repl_addr_valids_T_22 | sectored_entries_0_7_valid_3; // @[package.scala:81:59]
wire [1:0] r_sectored_repl_addr_valids_lo_lo = {_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2}; // @[package.scala:45:27, :81:59]
wire [1:0] r_sectored_repl_addr_valids_lo_hi = {_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8}; // @[package.scala:45:27, :81:59]
wire [3:0] r_sectored_repl_addr_valids_lo = {r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo}; // @[package.scala:45:27]
wire [1:0] r_sectored_repl_addr_valids_hi_lo = {_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14}; // @[package.scala:45:27, :81:59]
wire [1:0] r_sectored_repl_addr_valids_hi_hi = {_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20}; // @[package.scala:45:27, :81:59]
wire [3:0] r_sectored_repl_addr_valids_hi = {r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo}; // @[package.scala:45:27]
wire [7:0] r_sectored_repl_addr_valids = {r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo}; // @[package.scala:45:27]
wire _r_sectored_repl_addr_T_10 = &r_sectored_repl_addr_valids; // @[package.scala:45:27]
wire [7:0] _r_sectored_repl_addr_T_11 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27]
wire _r_sectored_repl_addr_T_12 = _r_sectored_repl_addr_T_11[0]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_13 = _r_sectored_repl_addr_T_11[1]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_14 = _r_sectored_repl_addr_T_11[2]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_15 = _r_sectored_repl_addr_T_11[3]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_16 = _r_sectored_repl_addr_T_11[4]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_17 = _r_sectored_repl_addr_T_11[5]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_18 = _r_sectored_repl_addr_T_11[6]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_19 = _r_sectored_repl_addr_T_11[7]; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_20 = {2'h3, ~_r_sectored_repl_addr_T_18}; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_21 = _r_sectored_repl_addr_T_17 ? 3'h5 : _r_sectored_repl_addr_T_20; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_22 = _r_sectored_repl_addr_T_16 ? 3'h4 : _r_sectored_repl_addr_T_21; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_23 = _r_sectored_repl_addr_T_15 ? 3'h3 : _r_sectored_repl_addr_T_22; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_24 = _r_sectored_repl_addr_T_14 ? 3'h2 : _r_sectored_repl_addr_T_23; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_25 = _r_sectored_repl_addr_T_13 ? 3'h1 : _r_sectored_repl_addr_T_24; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_26 = _r_sectored_repl_addr_T_12 ? 3'h0 : _r_sectored_repl_addr_T_25; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_27 = _r_sectored_repl_addr_T_10 ? _r_sectored_repl_addr_T_9 : _r_sectored_repl_addr_T_26; // @[Mux.scala:50:70]
wire _r_sectored_hit_valid_T = sector_hits_0 | sector_hits_1; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_1 = _r_sectored_hit_valid_T | sector_hits_2; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_2 = _r_sectored_hit_valid_T_1 | sector_hits_3; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_3 = _r_sectored_hit_valid_T_2 | sector_hits_4; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_4 = _r_sectored_hit_valid_T_3 | sector_hits_5; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_5 = _r_sectored_hit_valid_T_4 | sector_hits_6; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_6 = _r_sectored_hit_valid_T_5 | sector_hits_7; // @[package.scala:81:59]
wire [3:0] r_sectored_hit_bits_lo = {r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo}; // @[OneHot.scala:21:45]
wire [3:0] r_sectored_hit_bits_hi = {r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo}; // @[OneHot.scala:21:45]
wire [7:0] _r_sectored_hit_bits_T = {r_sectored_hit_bits_hi, r_sectored_hit_bits_lo}; // @[OneHot.scala:21:45]
wire [3:0] r_sectored_hit_bits_hi_1 = _r_sectored_hit_bits_T[7:4]; // @[OneHot.scala:21:45, :30:18]
wire [3:0] r_sectored_hit_bits_lo_1 = _r_sectored_hit_bits_T[3:0]; // @[OneHot.scala:21:45, :31:18]
wire _r_sectored_hit_bits_T_1 = |r_sectored_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _r_sectored_hit_bits_T_2 = r_sectored_hit_bits_hi_1 | r_sectored_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] r_sectored_hit_bits_hi_2 = _r_sectored_hit_bits_T_2[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] r_sectored_hit_bits_lo_2 = _r_sectored_hit_bits_T_2[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _r_sectored_hit_bits_T_3 = |r_sectored_hit_bits_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _r_sectored_hit_bits_T_4 = r_sectored_hit_bits_hi_2 | r_sectored_hit_bits_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _r_sectored_hit_bits_T_5 = _r_sectored_hit_bits_T_4[1]; // @[OneHot.scala:32:28]
wire [1:0] _r_sectored_hit_bits_T_6 = {_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _r_sectored_hit_bits_T_7 = {_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6}; // @[OneHot.scala:32:{10,14}]
wire _r_superpage_hit_valid_T = superpage_hits_0 | superpage_hits_1; // @[package.scala:81:59]
wire _r_superpage_hit_valid_T_1 = _r_superpage_hit_valid_T | superpage_hits_2; // @[package.scala:81:59]
wire _r_superpage_hit_valid_T_2 = _r_superpage_hit_valid_T_1 | superpage_hits_3; // @[package.scala:81:59]
wire [3:0] _r_superpage_hit_bits_T = {r_superpage_hit_bits_hi, r_superpage_hit_bits_lo}; // @[OneHot.scala:21:45]
wire [1:0] r_superpage_hit_bits_hi_1 = _r_superpage_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18]
wire [1:0] r_superpage_hit_bits_lo_1 = _r_superpage_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18]
wire _r_superpage_hit_bits_T_1 = |r_superpage_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _r_superpage_hit_bits_T_2 = r_superpage_hit_bits_hi_1 | r_superpage_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _r_superpage_hit_bits_T_3 = _r_superpage_hit_bits_T_2[1]; // @[OneHot.scala:32:28]
wire [1:0] _r_superpage_hit_bits_T_4 = {_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}]
wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45] |
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_93 :
input clock : Clock
input reset : Reset
output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}}
regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff)
reg value_reg : { symbol : UInt<10>}, clock
connect io.output_prev.key, key_reg
connect io.output_prev.value, value_reg
connect io.output_nxt.key, key_reg
connect io.output_nxt.value, value_reg
connect io.cur_output_keyval.key, key_reg
connect io.cur_output_keyval.value, value_reg
when io.cmd.valid :
node _T = eq(UInt<1>(0h0), io.cmd.bits)
when _T :
connect key_reg, io.input_nxt.key
connect value_reg, io.input_nxt.value
else :
node _T_1 = eq(UInt<1>(0h1), io.cmd.bits)
when _T_1 :
when io.insert_here :
connect key_reg, io.cur_input_keyval.key
connect value_reg, io.cur_input_keyval.value
else :
node _T_2 = geq(key_reg, io.cur_input_keyval.key)
when _T_2 :
connect key_reg, io.input_prev.key
connect value_reg, io.input_prev.value
else :
skip | module PriorityQueueStage_93( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_35 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_35( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_231 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_231( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_35 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<4>, q : UInt<4>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_318
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
node _output_T_2 = asAsyncReset(reset)
node _output_T_3 = bits(io.d, 1, 1)
inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_319
connect output_chain_1.clock, clock
connect output_chain_1.reset, _output_T_2
connect output_chain_1.io.d, _output_T_3
wire output_1 : UInt<1>
connect output_1, output_chain_1.io.q
node _output_T_4 = asAsyncReset(reset)
node _output_T_5 = bits(io.d, 2, 2)
inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_320
connect output_chain_2.clock, clock
connect output_chain_2.reset, _output_T_4
connect output_chain_2.io.d, _output_T_5
wire output_2 : UInt<1>
connect output_2, output_chain_2.io.q
node _output_T_6 = asAsyncReset(reset)
node _output_T_7 = bits(io.d, 3, 3)
inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_321
connect output_chain_3.clock, clock
connect output_chain_3.reset, _output_T_6
connect output_chain_3.io.d, _output_T_7
wire output_3 : UInt<1>
connect output_3, output_chain_3.io.q
node io_q_lo = cat(output_1, output_0)
node io_q_hi = cat(output_3, output_2)
node _io_q_T = cat(io_q_hi, io_q_lo)
connect io.q, _io_q_T | module AsyncResetSynchronizerShiftReg_w4_d3_i0_35( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_318 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_319 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_320 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_321 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_67 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_80
connect io_out_sink_valid.clock, clock
connect io_out_sink_valid.reset, reset
connect io_out_sink_valid.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_67( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_80 io_out_sink_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_55 :
input clock : Clock
input reset : Reset
output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>}
node _reg_T = eq(io.dir, UInt<1>(0h0))
node _reg_T_1 = mux(_reg_T, io.inR, io.inD)
reg reg : SInt<8>, clock
when io.en :
connect reg, _reg_T_1
connect io.outU, reg
connect io.outL, reg | module PE_55( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_413 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_157
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_413( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_157 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_105 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_126
connect io_out_source_valid_1.clock, clock
connect io_out_source_valid_1.reset, reset
connect io_out_source_valid_1.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid_1.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_105( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_126 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MSHR_5 :
input clock : Clock
input reset : Reset
output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<8>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<8>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<8>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}}
regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock
regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<8>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock
when meta_valid :
node _T = eq(meta.state, UInt<2>(0h0))
when _T :
node _T_1 = orr(meta.clients)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _T_6 = eq(meta.dirty, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = eq(meta.state, UInt<2>(0h1))
when _T_10 :
node _T_11 = eq(meta.dirty, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = eq(meta.state, UInt<2>(0h2))
when _T_15 :
node _T_16 = orr(meta.clients)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = sub(meta.clients, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = and(meta.clients, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4
assert(clock, _T_23, UInt<1>(0h1), "") : assert_4
node _T_27 = eq(meta.state, UInt<2>(0h3))
when _T_27 :
skip
regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1)
reg sink : UInt<3>, clock
reg gotT : UInt<1>, clock
reg bad_grant : UInt<1>, clock
reg probes_done : UInt<8>, clock
reg probes_toN : UInt<8>, clock
reg probes_noT : UInt<1>, clock
node _T_28 = neq(meta.state, UInt<2>(0h0))
node _T_29 = and(meta_valid, _T_28)
node _T_30 = eq(io.nestedwb.set, request.set)
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.nestedwb.tag, meta.tag)
node _T_33 = and(_T_31, _T_32)
when _T_33 :
when io.nestedwb.b_clr_dirty :
connect meta.dirty, UInt<1>(0h0)
when io.nestedwb.c_set_dirty :
connect meta.dirty, UInt<1>(0h1)
when io.nestedwb.b_toB :
connect meta.state, UInt<2>(0h1)
when io.nestedwb.b_toN :
connect meta.hit, UInt<1>(0h0)
connect io.status.valid, request_valid
connect io.status.bits.set, request.set
connect io.status.bits.tag, request.tag
connect io.status.bits.way, meta.way
node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0))
node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0))
node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2)
node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4)
node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6)
node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7)
connect io.status.bits.blockB, _io_status_bits_blockB_T_8
node _io_status_bits_nestB_T = and(meta_valid, w_releaseack)
node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast)
node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast)
node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3)
connect io.status.bits.nestB, _io_status_bits_nestB_T_4
node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0))
connect io.status.bits.blockC, _io_status_bits_blockC_T
node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1)
node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3)
node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4)
connect io.status.bits.nestC, _io_status_bits_nestC_T_5
node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0))
node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5
assert(clock, _T_36, UInt<1>(0h1), "") : assert_5
node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0))
node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0))
node _T_42 = or(_T_40, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6
assert(clock, _T_42, UInt<1>(0h1), "") : assert_6
node _no_wait_T = and(w_rprobeacklast, w_releaseack)
node _no_wait_T_1 = and(_no_wait_T, w_grantlast)
node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast)
node no_wait = and(_no_wait_T_2, w_grantack)
node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0))
node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release)
node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe)
connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2
node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1)
connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2
node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst)
node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst)
node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3)
connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4
node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0))
node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack)
node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant)
connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2
node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0))
node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst)
connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1
node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0))
node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack)
connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1
node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst)
node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait)
node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3)
connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4
connect io.schedule.bits.reload, no_wait
node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid)
node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid)
node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid)
node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid)
node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid)
node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid)
connect io.schedule.valid, _io_schedule_valid_T_5
when io.schedule.ready :
connect s_rprobe, UInt<1>(0h1)
when w_rprobeackfirst :
connect s_release, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
node _T_46 = and(s_release, s_pprobe)
when _T_46 :
connect s_acquire, UInt<1>(0h1)
when w_releaseack :
connect s_flush, UInt<1>(0h1)
when w_pprobeackfirst :
connect s_probeack, UInt<1>(0h1)
when w_grantfirst :
connect s_grantack, UInt<1>(0h1)
node _T_47 = and(w_pprobeack, w_grant)
when _T_47 :
connect s_execute, UInt<1>(0h1)
when no_wait :
connect s_writeback, UInt<1>(0h1)
when no_wait :
connect request_valid, UInt<1>(0h0)
connect meta_valid, UInt<1>(0h0)
wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<8>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}
connect final_meta_writeback, meta
node _req_clientBit_T = eq(request.source, UInt<6>(0h3c))
node _req_clientBit_T_1 = eq(request.source, UInt<6>(0h38))
node _req_clientBit_T_2 = eq(request.source, UInt<6>(0h34))
node _req_clientBit_T_3 = eq(request.source, UInt<6>(0h30))
node _req_clientBit_T_4 = eq(request.source, UInt<6>(0h2c))
node _req_clientBit_T_5 = eq(request.source, UInt<6>(0h28))
node _req_clientBit_T_6 = eq(request.source, UInt<6>(0h24))
node _req_clientBit_T_7 = eq(request.source, UInt<6>(0h20))
node req_clientBit_lo_lo = cat(_req_clientBit_T_1, _req_clientBit_T)
node req_clientBit_lo_hi = cat(_req_clientBit_T_3, _req_clientBit_T_2)
node req_clientBit_lo = cat(req_clientBit_lo_hi, req_clientBit_lo_lo)
node req_clientBit_hi_lo = cat(_req_clientBit_T_5, _req_clientBit_T_4)
node req_clientBit_hi_hi = cat(_req_clientBit_T_7, _req_clientBit_T_6)
node req_clientBit_hi = cat(req_clientBit_hi_hi, req_clientBit_hi_lo)
node req_clientBit = cat(req_clientBit_hi, req_clientBit_lo)
node _req_needT_T = bits(request.opcode, 2, 2)
node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0))
node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5))
node _req_needT_T_3 = eq(request.param, UInt<1>(0h1))
node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3)
node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4)
node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6))
node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7))
node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7)
node _req_needT_T_9 = neq(request.param, UInt<2>(0h0))
node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9)
node req_needT = or(_req_needT_T_5, _req_needT_T_10)
node _req_acquire_T = eq(request.opcode, UInt<3>(0h6))
node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7))
node req_acquire = or(_req_acquire_T, _req_acquire_T_1)
node _meta_no_clients_T = orr(meta.clients)
node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0))
node _req_promoteT_T = eq(meta.state, UInt<2>(0h3))
node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T)
node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT)
node req_promoteT = and(req_acquire, _req_promoteT_T_2)
node _T_48 = and(request.prio[2], UInt<1>(0h1))
when _T_48 :
node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0)
node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1
node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3))
node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2))
node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1)
node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state)
connect final_meta_writeback.state, _final_meta_writeback_state_T_3
node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1))
node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2))
node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1)
node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5))
node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3)
node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5)
node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7
connect final_meta_writeback.hit, UInt<1>(0h1)
else :
node _T_49 = and(request.control, UInt<1>(0h1))
when _T_49 :
when meta.hit :
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
node _final_meta_writeback_clients_T_8 = not(probes_toN)
node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9
connect final_meta_writeback.hit, UInt<1>(0h0)
else :
node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty)
node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2)
node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0))
node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5
node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0))
node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1))
node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire)
node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state)
node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1))
node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state)
node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11)
node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state)
node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13)
node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15)
node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16)
connect final_meta_writeback.state, _final_meta_writeback_state_T_17
node _final_meta_writeback_clients_T_10 = not(probes_toN)
node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10)
node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0))
node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14
connect final_meta_writeback.tag, request.tag
connect final_meta_writeback.hit, UInt<1>(0h1)
when bad_grant :
when meta.hit :
node _T_50 = eq(meta_valid, UInt<1>(0h0))
node _T_51 = eq(meta.state, UInt<2>(0h1))
node _T_52 = or(_T_50, _T_51)
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7
assert(clock, _T_52, UInt<1>(0h1), "") : assert_7
connect final_meta_writeback.hit, UInt<1>(0h1)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h1)
node _final_meta_writeback_clients_T_15 = not(probes_toN)
node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16
else :
connect final_meta_writeback.hit, UInt<1>(0h0)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
connect final_meta_writeback.clients, UInt<1>(0h0)
wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<8>, tag : UInt<13>}
connect invalid.dirty, UInt<1>(0h0)
connect invalid.state, UInt<2>(0h0)
connect invalid.clients, UInt<1>(0h0)
connect invalid.tag, UInt<1>(0h0)
node _honour_BtoT_T = and(meta.clients, req_clientBit)
node _honour_BtoT_T_1 = orr(_honour_BtoT_T)
node honour_BtoT = and(meta.hit, _honour_BtoT_T_1)
node _excluded_client_T = and(meta.hit, request.prio[0])
node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6))
node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7))
node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2)
node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4))
node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4)
node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5))
node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0))
node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7)
node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8)
node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0))
connect io.schedule.bits.a.bits.tag, request.tag
connect io.schedule.bits.a.bits.set, request.set
node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0))
connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1
node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6))
node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7))
node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2)
node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4)
connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5
connect io.schedule.bits.a.bits.source, UInt<1>(0h0)
node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1)
node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2)
connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3
node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag)
connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1
connect io.schedule.bits.b.bits.set, request.set
node _io_schedule_bits_b_bits_clients_T = not(excluded_client)
node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T)
connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1
node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6))
connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T
node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1))
node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1))
connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1
connect io.schedule.bits.c.bits.source, UInt<1>(0h0)
connect io.schedule.bits.c.bits.tag, meta.tag
connect io.schedule.bits.c.bits.set, request.set
connect io.schedule.bits.c.bits.way, meta.way
connect io.schedule.bits.c.bits.dirty, meta.dirty
connect io.schedule.bits.d.bits.set, request.set
connect io.schedule.bits.d.bits.put, request.put
connect io.schedule.bits.d.bits.offset, request.offset
connect io.schedule.bits.d.bits.tag, request.tag
connect io.schedule.bits.d.bits.source, request.source
connect io.schedule.bits.d.bits.size, request.size
connect io.schedule.bits.d.bits.param, request.param
connect io.schedule.bits.d.bits.opcode, request.opcode
connect io.schedule.bits.d.bits.control, request.control
connect io.schedule.bits.d.bits.prio, request.prio
node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0))
node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0))
node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param)
node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param)
node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param)
node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4)
node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param)
node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6)
node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8)
connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9
connect io.schedule.bits.d.bits.sink, UInt<1>(0h0)
connect io.schedule.bits.d.bits.way, meta.way
connect io.schedule.bits.d.bits.bad, bad_grant
connect io.schedule.bits.e.bits.sink, sink
connect io.schedule.bits.x.bits.fail, UInt<1>(0h0)
connect io.schedule.bits.dir.bits.set, request.set
connect io.schedule.bits.dir.bits.way, meta.way
node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0))
wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<8>, tag : UInt<13>}
connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag
connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients
connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state
connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty
node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE)
connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1
node _evict_T = eq(meta.hit, UInt<1>(0h0))
wire evict : UInt
connect evict, UInt<1>(0h0)
node evict_c = orr(meta.clients)
node _evict_T_1 = eq(UInt<2>(0h1), meta.state)
when _evict_T_1 :
node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1))
connect evict, _evict_out_T
else :
node _evict_T_2 = eq(UInt<2>(0h2), meta.state)
when _evict_T_2 :
node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect evict, _evict_out_T_1
else :
node _evict_T_3 = eq(UInt<2>(0h3), meta.state)
when _evict_T_3 :
node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3)
connect evict, _evict_out_T_4
else :
node _evict_T_4 = eq(UInt<2>(0h0), meta.state)
when _evict_T_4 :
connect evict, UInt<4>(0h8)
node _evict_T_5 = eq(_evict_T, UInt<1>(0h0))
when _evict_T_5 :
connect evict, UInt<4>(0h8)
wire before : UInt
connect before, UInt<1>(0h0)
node before_c = orr(meta.clients)
node _before_T = eq(UInt<2>(0h1), meta.state)
when _before_T :
node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1))
connect before, _before_out_T
else :
node _before_T_1 = eq(UInt<2>(0h2), meta.state)
when _before_T_1 :
node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect before, _before_out_T_1
else :
node _before_T_2 = eq(UInt<2>(0h3), meta.state)
when _before_T_2 :
node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3)
connect before, _before_out_T_4
else :
node _before_T_3 = eq(UInt<2>(0h0), meta.state)
when _before_T_3 :
connect before, UInt<4>(0h8)
node _before_T_4 = eq(meta.hit, UInt<1>(0h0))
when _before_T_4 :
connect before, UInt<4>(0h8)
wire after : UInt
connect after, UInt<1>(0h0)
node after_c = orr(final_meta_writeback.clients)
node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _after_T :
node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1))
connect after, _after_out_T
else :
node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _after_T_1 :
node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect after, _after_out_T_1
else :
node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _after_T_2 :
node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3)
connect after, _after_out_T_4
else :
node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _after_T_3 :
connect after, UInt<4>(0h8)
node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _after_T_4 :
connect after, UInt<4>(0h8)
node _T_56 = eq(s_release, UInt<1>(0h0))
node _T_57 = and(_T_56, w_rprobeackfirst)
node _T_58 = and(_T_57, io.schedule.ready)
when _T_58 :
node _T_59 = eq(evict, UInt<1>(0h1))
node _T_60 = eq(_T_59, UInt<1>(0h0))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8
assert(clock, _T_60, UInt<1>(0h1), "") : assert_8
node _T_64 = eq(before, UInt<1>(0h1))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(evict, UInt<1>(0h0))
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10
assert(clock, _T_70, UInt<1>(0h1), "") : assert_10
node _T_74 = eq(before, UInt<1>(0h0))
node _T_75 = eq(_T_74, UInt<1>(0h0))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11
assert(clock, _T_75, UInt<1>(0h1), "") : assert_11
node _T_79 = eq(evict, UInt<3>(0h7))
node _T_80 = eq(before, UInt<3>(0h7))
node _T_81 = eq(evict, UInt<3>(0h5))
node _T_82 = eq(before, UInt<3>(0h5))
node _T_83 = eq(evict, UInt<3>(0h4))
node _T_84 = eq(before, UInt<3>(0h4))
node _T_85 = eq(evict, UInt<3>(0h6))
node _T_86 = eq(before, UInt<3>(0h6))
node _T_87 = eq(evict, UInt<2>(0h3))
node _T_88 = eq(before, UInt<2>(0h3))
node _T_89 = eq(evict, UInt<2>(0h2))
node _T_90 = eq(before, UInt<2>(0h2))
node _T_91 = eq(s_writeback, UInt<1>(0h0))
node _T_92 = and(_T_91, no_wait)
node _T_93 = and(_T_92, io.schedule.ready)
when _T_93 :
node _T_94 = eq(before, UInt<4>(0h8))
node _T_95 = eq(after, UInt<1>(0h1))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12
assert(clock, _T_97, UInt<1>(0h1), "") : assert_12
node _T_101 = eq(before, UInt<4>(0h8))
node _T_102 = eq(after, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13
assert(clock, _T_104, UInt<1>(0h1), "") : assert_13
node _T_108 = eq(before, UInt<4>(0h8))
node _T_109 = eq(after, UInt<3>(0h7))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(before, UInt<4>(0h8))
node _T_112 = eq(after, UInt<3>(0h5))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(_T_113, UInt<1>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14
assert(clock, _T_114, UInt<1>(0h1), "") : assert_14
node _T_118 = eq(before, UInt<4>(0h8))
node _T_119 = eq(after, UInt<3>(0h4))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15
assert(clock, _T_121, UInt<1>(0h1), "") : assert_15
node _T_125 = eq(before, UInt<4>(0h8))
node _T_126 = eq(after, UInt<3>(0h6))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(before, UInt<4>(0h8))
node _T_129 = eq(after, UInt<2>(0h3))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(before, UInt<4>(0h8))
node _T_132 = eq(after, UInt<2>(0h2))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16
assert(clock, _T_134, UInt<1>(0h1), "") : assert_16
node _T_138 = eq(before, UInt<1>(0h1))
node _T_139 = eq(after, UInt<4>(0h8))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(_T_140, UInt<1>(0h0))
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17
assert(clock, _T_141, UInt<1>(0h1), "") : assert_17
node _T_145 = eq(before, UInt<1>(0h1))
node _T_146 = eq(after, UInt<1>(0h0))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(_T_147, UInt<1>(0h0))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18
assert(clock, _T_148, UInt<1>(0h1), "") : assert_18
node _T_152 = eq(before, UInt<1>(0h1))
node _T_153 = eq(after, UInt<3>(0h7))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(_T_154, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19
assert(clock, _T_155, UInt<1>(0h1), "") : assert_19
node _T_159 = eq(before, UInt<1>(0h1))
node _T_160 = eq(after, UInt<3>(0h5))
node _T_161 = and(_T_159, _T_160)
node _T_162 = eq(_T_161, UInt<1>(0h0))
node _T_163 = asUInt(reset)
node _T_164 = eq(_T_163, UInt<1>(0h0))
when _T_164 :
node _T_165 = eq(_T_162, UInt<1>(0h0))
when _T_165 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20
assert(clock, _T_162, UInt<1>(0h1), "") : assert_20
node _T_166 = eq(before, UInt<1>(0h1))
node _T_167 = eq(after, UInt<3>(0h4))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21
assert(clock, _T_169, UInt<1>(0h1), "") : assert_21
node _T_173 = eq(before, UInt<1>(0h1))
node _T_174 = eq(after, UInt<3>(0h6))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(_T_175, UInt<1>(0h0))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22
assert(clock, _T_176, UInt<1>(0h1), "") : assert_22
node _T_180 = eq(before, UInt<1>(0h1))
node _T_181 = eq(after, UInt<2>(0h3))
node _T_182 = and(_T_180, _T_181)
node _T_183 = eq(_T_182, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(before, UInt<1>(0h1))
node _T_188 = eq(after, UInt<2>(0h2))
node _T_189 = and(_T_187, _T_188)
node _T_190 = eq(_T_189, UInt<1>(0h0))
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(_T_190, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24
assert(clock, _T_190, UInt<1>(0h1), "") : assert_24
node _T_194 = eq(before, UInt<1>(0h0))
node _T_195 = eq(after, UInt<4>(0h8))
node _T_196 = and(_T_194, _T_195)
node _T_197 = eq(_T_196, UInt<1>(0h0))
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25
assert(clock, _T_197, UInt<1>(0h1), "") : assert_25
node _T_201 = eq(before, UInt<1>(0h0))
node _T_202 = eq(after, UInt<1>(0h1))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(_T_204, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26
assert(clock, _T_204, UInt<1>(0h1), "") : assert_26
node _T_208 = eq(before, UInt<1>(0h0))
node _T_209 = eq(after, UInt<3>(0h7))
node _T_210 = and(_T_208, _T_209)
node _T_211 = eq(_T_210, UInt<1>(0h0))
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27
assert(clock, _T_211, UInt<1>(0h1), "") : assert_27
node _T_215 = eq(before, UInt<1>(0h0))
node _T_216 = eq(after, UInt<3>(0h5))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(_T_217, UInt<1>(0h0))
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28
assert(clock, _T_218, UInt<1>(0h1), "") : assert_28
node _T_222 = eq(before, UInt<1>(0h0))
node _T_223 = eq(after, UInt<3>(0h6))
node _T_224 = and(_T_222, _T_223)
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29
assert(clock, _T_225, UInt<1>(0h1), "") : assert_29
node _T_229 = eq(before, UInt<1>(0h0))
node _T_230 = eq(after, UInt<3>(0h4))
node _T_231 = and(_T_229, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(before, UInt<1>(0h0))
node _T_237 = eq(after, UInt<2>(0h3))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31
assert(clock, _T_239, UInt<1>(0h1), "") : assert_31
node _T_243 = eq(before, UInt<1>(0h0))
node _T_244 = eq(after, UInt<2>(0h2))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(_T_245, UInt<1>(0h0))
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32
assert(clock, _T_246, UInt<1>(0h1), "") : assert_32
node _T_250 = eq(before, UInt<3>(0h7))
node _T_251 = eq(after, UInt<4>(0h8))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33
assert(clock, _T_253, UInt<1>(0h1), "") : assert_33
node _T_257 = eq(before, UInt<3>(0h7))
node _T_258 = eq(after, UInt<1>(0h1))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(_T_259, UInt<1>(0h0))
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34
assert(clock, _T_260, UInt<1>(0h1), "") : assert_34
node _T_264 = eq(before, UInt<3>(0h7))
node _T_265 = eq(after, UInt<1>(0h0))
node _T_266 = and(_T_264, _T_265)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35
assert(clock, _T_267, UInt<1>(0h1), "") : assert_35
node _T_271 = eq(before, UInt<3>(0h7))
node _T_272 = eq(after, UInt<3>(0h5))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(_T_273, UInt<1>(0h0))
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36
assert(clock, _T_274, UInt<1>(0h1), "") : assert_36
node _T_278 = eq(before, UInt<3>(0h7))
node _T_279 = eq(after, UInt<3>(0h6))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(before, UInt<3>(0h7))
node _T_282 = eq(after, UInt<3>(0h4))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37
assert(clock, _T_284, UInt<1>(0h1), "") : assert_37
node _T_288 = eq(before, UInt<3>(0h7))
node _T_289 = eq(after, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(before, UInt<3>(0h7))
node _T_292 = eq(after, UInt<2>(0h2))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(_T_293, UInt<1>(0h0))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38
assert(clock, _T_294, UInt<1>(0h1), "") : assert_38
node _T_298 = eq(before, UInt<3>(0h5))
node _T_299 = eq(after, UInt<4>(0h8))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(_T_300, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39
assert(clock, _T_301, UInt<1>(0h1), "") : assert_39
node _T_305 = eq(before, UInt<3>(0h5))
node _T_306 = eq(after, UInt<1>(0h1))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(_T_307, UInt<1>(0h0))
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40
assert(clock, _T_308, UInt<1>(0h1), "") : assert_40
node _T_312 = eq(before, UInt<3>(0h5))
node _T_313 = eq(after, UInt<1>(0h0))
node _T_314 = and(_T_312, _T_313)
node _T_315 = eq(_T_314, UInt<1>(0h0))
node _T_316 = asUInt(reset)
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(_T_315, UInt<1>(0h0))
when _T_318 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41
assert(clock, _T_315, UInt<1>(0h1), "") : assert_41
node _T_319 = eq(before, UInt<3>(0h5))
node _T_320 = eq(after, UInt<3>(0h7))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(before, UInt<3>(0h5))
node _T_323 = eq(after, UInt<3>(0h6))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(before, UInt<3>(0h5))
node _T_326 = eq(after, UInt<3>(0h4))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(_T_327, UInt<1>(0h0))
node _T_329 = asUInt(reset)
node _T_330 = eq(_T_329, UInt<1>(0h0))
when _T_330 :
node _T_331 = eq(_T_328, UInt<1>(0h0))
when _T_331 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42
assert(clock, _T_328, UInt<1>(0h1), "") : assert_42
node _T_332 = eq(before, UInt<3>(0h5))
node _T_333 = eq(after, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(before, UInt<3>(0h5))
node _T_336 = eq(after, UInt<2>(0h2))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(_T_337, UInt<1>(0h0))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43
assert(clock, _T_338, UInt<1>(0h1), "") : assert_43
node _T_342 = eq(before, UInt<3>(0h6))
node _T_343 = eq(after, UInt<4>(0h8))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(_T_344, UInt<1>(0h0))
node _T_346 = asUInt(reset)
node _T_347 = eq(_T_346, UInt<1>(0h0))
when _T_347 :
node _T_348 = eq(_T_345, UInt<1>(0h0))
when _T_348 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44
assert(clock, _T_345, UInt<1>(0h1), "") : assert_44
node _T_349 = eq(before, UInt<3>(0h6))
node _T_350 = eq(after, UInt<1>(0h1))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(_T_351, UInt<1>(0h0))
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(_T_352, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45
assert(clock, _T_352, UInt<1>(0h1), "") : assert_45
node _T_356 = eq(before, UInt<3>(0h6))
node _T_357 = eq(after, UInt<1>(0h0))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(_T_358, UInt<1>(0h0))
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(_T_359, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46
assert(clock, _T_359, UInt<1>(0h1), "") : assert_46
node _T_363 = eq(before, UInt<3>(0h6))
node _T_364 = eq(after, UInt<3>(0h7))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47
assert(clock, _T_366, UInt<1>(0h1), "") : assert_47
node _T_370 = eq(before, UInt<3>(0h6))
node _T_371 = eq(after, UInt<3>(0h5))
node _T_372 = and(_T_370, _T_371)
node _T_373 = eq(_T_372, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48
assert(clock, _T_373, UInt<1>(0h1), "") : assert_48
node _T_377 = eq(before, UInt<3>(0h6))
node _T_378 = eq(after, UInt<3>(0h4))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(_T_379, UInt<1>(0h0))
node _T_381 = asUInt(reset)
node _T_382 = eq(_T_381, UInt<1>(0h0))
when _T_382 :
node _T_383 = eq(_T_380, UInt<1>(0h0))
when _T_383 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49
assert(clock, _T_380, UInt<1>(0h1), "") : assert_49
node _T_384 = eq(before, UInt<3>(0h6))
node _T_385 = eq(after, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(_T_386, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50
assert(clock, _T_387, UInt<1>(0h1), "") : assert_50
node _T_391 = eq(before, UInt<3>(0h6))
node _T_392 = eq(after, UInt<2>(0h2))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(before, UInt<3>(0h4))
node _T_395 = eq(after, UInt<4>(0h8))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51
assert(clock, _T_397, UInt<1>(0h1), "") : assert_51
node _T_401 = eq(before, UInt<3>(0h4))
node _T_402 = eq(after, UInt<1>(0h1))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(_T_403, UInt<1>(0h0))
node _T_405 = asUInt(reset)
node _T_406 = eq(_T_405, UInt<1>(0h0))
when _T_406 :
node _T_407 = eq(_T_404, UInt<1>(0h0))
when _T_407 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52
assert(clock, _T_404, UInt<1>(0h1), "") : assert_52
node _T_408 = eq(before, UInt<3>(0h4))
node _T_409 = eq(after, UInt<1>(0h0))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(_T_410, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53
assert(clock, _T_411, UInt<1>(0h1), "") : assert_53
node _T_415 = eq(before, UInt<3>(0h4))
node _T_416 = eq(after, UInt<3>(0h7))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(_T_417, UInt<1>(0h0))
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54
assert(clock, _T_418, UInt<1>(0h1), "") : assert_54
node _T_422 = eq(before, UInt<3>(0h4))
node _T_423 = eq(after, UInt<3>(0h5))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(_T_424, UInt<1>(0h0))
node _T_426 = asUInt(reset)
node _T_427 = eq(_T_426, UInt<1>(0h0))
when _T_427 :
node _T_428 = eq(_T_425, UInt<1>(0h0))
when _T_428 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55
assert(clock, _T_425, UInt<1>(0h1), "") : assert_55
node _T_429 = eq(before, UInt<3>(0h4))
node _T_430 = eq(after, UInt<3>(0h6))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(before, UInt<3>(0h4))
node _T_433 = eq(after, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(_T_434, UInt<1>(0h0))
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56
assert(clock, _T_435, UInt<1>(0h1), "") : assert_56
node _T_439 = eq(before, UInt<3>(0h4))
node _T_440 = eq(after, UInt<2>(0h2))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(before, UInt<2>(0h3))
node _T_443 = eq(after, UInt<4>(0h8))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(_T_444, UInt<1>(0h0))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57
assert(clock, _T_445, UInt<1>(0h1), "") : assert_57
node _T_449 = eq(before, UInt<2>(0h3))
node _T_450 = eq(after, UInt<1>(0h1))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(_T_451, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58
assert(clock, _T_452, UInt<1>(0h1), "") : assert_58
node _T_456 = eq(before, UInt<2>(0h3))
node _T_457 = eq(after, UInt<1>(0h0))
node _T_458 = and(_T_456, _T_457)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59
assert(clock, _T_459, UInt<1>(0h1), "") : assert_59
node _T_463 = eq(before, UInt<2>(0h3))
node _T_464 = eq(after, UInt<3>(0h7))
node _T_465 = and(_T_463, _T_464)
node _T_466 = eq(before, UInt<2>(0h3))
node _T_467 = eq(after, UInt<3>(0h5))
node _T_468 = and(_T_466, _T_467)
node _T_469 = eq(before, UInt<2>(0h3))
node _T_470 = eq(after, UInt<3>(0h6))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(before, UInt<2>(0h3))
node _T_473 = eq(after, UInt<3>(0h4))
node _T_474 = and(_T_472, _T_473)
node _T_475 = eq(before, UInt<2>(0h3))
node _T_476 = eq(after, UInt<2>(0h2))
node _T_477 = and(_T_475, _T_476)
node _T_478 = eq(before, UInt<2>(0h2))
node _T_479 = eq(after, UInt<4>(0h8))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60
assert(clock, _T_481, UInt<1>(0h1), "") : assert_60
node _T_485 = eq(before, UInt<2>(0h2))
node _T_486 = eq(after, UInt<1>(0h1))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(_T_487, UInt<1>(0h0))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61
assert(clock, _T_488, UInt<1>(0h1), "") : assert_61
node _T_492 = eq(before, UInt<2>(0h2))
node _T_493 = eq(after, UInt<1>(0h0))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(_T_494, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62
assert(clock, _T_495, UInt<1>(0h1), "") : assert_62
node _T_499 = eq(before, UInt<2>(0h2))
node _T_500 = eq(after, UInt<3>(0h7))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(_T_501, UInt<1>(0h0))
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63
assert(clock, _T_502, UInt<1>(0h1), "") : assert_63
node _T_506 = eq(before, UInt<2>(0h2))
node _T_507 = eq(after, UInt<3>(0h5))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(_T_508, UInt<1>(0h0))
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64
assert(clock, _T_509, UInt<1>(0h1), "") : assert_64
node _T_513 = eq(before, UInt<2>(0h2))
node _T_514 = eq(after, UInt<3>(0h6))
node _T_515 = and(_T_513, _T_514)
node _T_516 = eq(before, UInt<2>(0h2))
node _T_517 = eq(after, UInt<3>(0h4))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(before, UInt<2>(0h2))
node _T_520 = eq(after, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _T_522 = eq(_T_521, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65
assert(clock, _T_522, UInt<1>(0h1), "") : assert_65
node _probe_bit_T = eq(io.sinkc.bits.source, UInt<6>(0h3c))
node _probe_bit_T_1 = eq(io.sinkc.bits.source, UInt<6>(0h38))
node _probe_bit_T_2 = eq(io.sinkc.bits.source, UInt<6>(0h34))
node _probe_bit_T_3 = eq(io.sinkc.bits.source, UInt<6>(0h30))
node _probe_bit_T_4 = eq(io.sinkc.bits.source, UInt<6>(0h2c))
node _probe_bit_T_5 = eq(io.sinkc.bits.source, UInt<6>(0h28))
node _probe_bit_T_6 = eq(io.sinkc.bits.source, UInt<6>(0h24))
node _probe_bit_T_7 = eq(io.sinkc.bits.source, UInt<6>(0h20))
node probe_bit_lo_lo = cat(_probe_bit_T_1, _probe_bit_T)
node probe_bit_lo_hi = cat(_probe_bit_T_3, _probe_bit_T_2)
node probe_bit_lo = cat(probe_bit_lo_hi, probe_bit_lo_lo)
node probe_bit_hi_lo = cat(_probe_bit_T_5, _probe_bit_T_4)
node probe_bit_hi_hi = cat(_probe_bit_T_7, _probe_bit_T_6)
node probe_bit_hi = cat(probe_bit_hi_hi, probe_bit_hi_lo)
node probe_bit = cat(probe_bit_hi, probe_bit_lo)
node _last_probe_T = or(probes_done, probe_bit)
node _last_probe_T_1 = not(excluded_client)
node _last_probe_T_2 = and(meta.clients, _last_probe_T_1)
node last_probe = eq(_last_probe_T, _last_probe_T_2)
node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1))
node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2))
node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1)
node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5))
node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3)
when io.sinkc.valid :
node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_527 = and(probe_toN, _T_526)
node _T_528 = eq(probe_toN, UInt<1>(0h0))
node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_530 = and(_T_528, _T_529)
node _probes_done_T = or(probes_done, probe_bit)
connect probes_done, _probes_done_T
node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0))
node _probes_toN_T_1 = or(probes_toN, _probes_toN_T)
connect probes_toN, _probes_toN_T_1
node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3))
node _probes_noT_T_1 = or(probes_noT, _probes_noT_T)
connect probes_noT, _probes_noT_T_1
node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe)
connect w_rprobeackfirst, _w_rprobeackfirst_T
node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T)
connect w_rprobeacklast, _w_rprobeacklast_T_1
node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe)
connect w_pprobeackfirst, _w_pprobeackfirst_T
node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T)
connect w_pprobeacklast, _w_pprobeacklast_T_1
node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0))
node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T)
node set_pprobeack = and(last_probe, _set_pprobeack_T_1)
node _w_pprobeack_T = or(w_pprobeack, set_pprobeack)
connect w_pprobeack, _w_pprobeack_T
node _T_531 = eq(set_pprobeack, UInt<1>(0h0))
node _T_532 = and(_T_531, w_rprobeackfirst)
node _T_533 = and(set_pprobeack, w_rprobeackfirst)
node _T_534 = neq(meta.state, UInt<2>(0h0))
node _T_535 = eq(io.sinkc.bits.tag, meta.tag)
node _T_536 = and(_T_534, _T_535)
node _T_537 = and(_T_536, io.sinkc.bits.data)
when _T_537 :
connect meta.dirty, UInt<1>(0h1)
when io.sinkd.valid :
node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4))
node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_540 = or(_T_538, _T_539)
when _T_540 :
connect sink, io.sinkd.bits.sink
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, io.sinkd.bits.last
connect bad_grant, io.sinkd.bits.denied
node _w_grant_T = eq(request.offset, UInt<1>(0h0))
node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last)
connect w_grant, _w_grant_T_1
node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_542 = eq(request.offset, UInt<1>(0h0))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_545 = neq(request.offset, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0))
connect gotT, _gotT_T
else :
node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6))
when _T_547 :
connect w_releaseack, UInt<1>(0h1)
when io.sinke.valid :
connect w_grantack, UInt<1>(0h1)
wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}
connect allocate_as_full.set, io.allocate.bits.set
connect allocate_as_full.put, io.allocate.bits.put
connect allocate_as_full.offset, io.allocate.bits.offset
connect allocate_as_full.tag, io.allocate.bits.tag
connect allocate_as_full.source, io.allocate.bits.source
connect allocate_as_full.size, io.allocate.bits.size
connect allocate_as_full.param, io.allocate.bits.param
connect allocate_as_full.opcode, io.allocate.bits.opcode
connect allocate_as_full.control, io.allocate.bits.control
connect allocate_as_full.prio, io.allocate.bits.prio
node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat)
node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits)
node new_request = mux(io.allocate.valid, allocate_as_full, request)
node _new_needT_T = bits(new_request.opcode, 2, 2)
node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0))
node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5))
node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1))
node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3)
node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4)
node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6))
node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7))
node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7)
node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0))
node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9)
node new_needT = or(_new_needT_T_5, _new_needT_T_10)
node _new_clientBit_T = eq(new_request.source, UInt<6>(0h3c))
node _new_clientBit_T_1 = eq(new_request.source, UInt<6>(0h38))
node _new_clientBit_T_2 = eq(new_request.source, UInt<6>(0h34))
node _new_clientBit_T_3 = eq(new_request.source, UInt<6>(0h30))
node _new_clientBit_T_4 = eq(new_request.source, UInt<6>(0h2c))
node _new_clientBit_T_5 = eq(new_request.source, UInt<6>(0h28))
node _new_clientBit_T_6 = eq(new_request.source, UInt<6>(0h24))
node _new_clientBit_T_7 = eq(new_request.source, UInt<6>(0h20))
node new_clientBit_lo_lo = cat(_new_clientBit_T_1, _new_clientBit_T)
node new_clientBit_lo_hi = cat(_new_clientBit_T_3, _new_clientBit_T_2)
node new_clientBit_lo = cat(new_clientBit_lo_hi, new_clientBit_lo_lo)
node new_clientBit_hi_lo = cat(_new_clientBit_T_5, _new_clientBit_T_4)
node new_clientBit_hi_hi = cat(_new_clientBit_T_7, _new_clientBit_T_6)
node new_clientBit_hi = cat(new_clientBit_hi_hi, new_clientBit_hi_lo)
node new_clientBit = cat(new_clientBit_hi, new_clientBit_lo)
node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6))
node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7))
node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1)
node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4))
node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3)
node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5))
node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0))
node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6)
node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0))
wire prior : UInt
connect prior, UInt<1>(0h0)
node prior_c = orr(final_meta_writeback.clients)
node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _prior_T :
node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1))
connect prior, _prior_out_T
else :
node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _prior_T_1 :
node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect prior, _prior_out_T_1
else :
node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _prior_T_2 :
node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3)
connect prior, _prior_out_T_4
else :
node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _prior_T_3 :
connect prior, UInt<4>(0h8)
node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _prior_T_4 :
connect prior, UInt<4>(0h8)
node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat)
when _T_548 :
node _T_549 = eq(prior, UInt<4>(0h8))
node _T_550 = eq(prior, UInt<1>(0h1))
node _T_551 = eq(_T_550, UInt<1>(0h0))
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66
assert(clock, _T_551, UInt<1>(0h1), "") : assert_66
node _T_555 = eq(prior, UInt<1>(0h0))
node _T_556 = eq(_T_555, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67
assert(clock, _T_556, UInt<1>(0h1), "") : assert_67
node _T_560 = eq(prior, UInt<3>(0h7))
node _T_561 = eq(prior, UInt<3>(0h5))
node _T_562 = eq(prior, UInt<3>(0h4))
node _T_563 = eq(prior, UInt<3>(0h6))
node _T_564 = eq(prior, UInt<2>(0h3))
node _T_565 = eq(prior, UInt<2>(0h2))
when io.allocate.valid :
node _T_566 = eq(request_valid, UInt<1>(0h0))
node _T_567 = and(io.schedule.ready, io.schedule.valid)
node _T_568 = and(no_wait, _T_567)
node _T_569 = or(_T_566, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68
assert(clock, _T_569, UInt<1>(0h1), "") : assert_68
connect request_valid, UInt<1>(0h1)
connect request.set, io.allocate.bits.set
connect request.put, io.allocate.bits.put
connect request.offset, io.allocate.bits.offset
connect request.tag, io.allocate.bits.tag
connect request.source, io.allocate.bits.source
connect request.size, io.allocate.bits.size
connect request.param, io.allocate.bits.param
connect request.opcode, io.allocate.bits.opcode
connect request.control, io.allocate.bits.control
connect request.prio, io.allocate.bits.prio
node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat)
node _T_574 = or(io.directory.valid, _T_573)
when _T_574 :
connect meta_valid, UInt<1>(0h1)
connect meta, new_meta
connect probes_done, UInt<1>(0h0)
connect probes_toN, UInt<1>(0h0)
connect probes_noT, UInt<1>(0h0)
connect gotT, UInt<1>(0h0)
connect bad_grant, UInt<1>(0h0)
connect s_rprobe, UInt<1>(0h1)
connect w_rprobeackfirst, UInt<1>(0h1)
connect w_rprobeacklast, UInt<1>(0h1)
connect s_release, UInt<1>(0h1)
connect w_releaseack, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
connect s_acquire, UInt<1>(0h1)
connect s_flush, UInt<1>(0h1)
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, UInt<1>(0h1)
connect w_grant, UInt<1>(0h1)
connect w_pprobeackfirst, UInt<1>(0h1)
connect w_pprobeacklast, UInt<1>(0h1)
connect w_pprobeack, UInt<1>(0h1)
connect s_probeack, UInt<1>(0h1)
connect s_grantack, UInt<1>(0h1)
connect s_execute, UInt<1>(0h1)
connect w_grantack, UInt<1>(0h1)
connect s_writeback, UInt<1>(0h1)
node _T_575 = and(new_request.prio[2], UInt<1>(0h1))
when _T_575 :
connect s_execute, UInt<1>(0h0)
node _T_576 = bits(new_request.opcode, 0, 0)
node _T_577 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_578 = and(_T_576, _T_577)
when _T_578 :
connect s_writeback, UInt<1>(0h0)
node _T_579 = eq(new_request.param, UInt<3>(0h0))
node _T_580 = eq(new_request.param, UInt<3>(0h4))
node _T_581 = or(_T_579, _T_580)
node _T_582 = eq(new_meta.state, UInt<2>(0h2))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
connect s_writeback, UInt<1>(0h0)
node _T_584 = eq(new_request.param, UInt<3>(0h1))
node _T_585 = eq(new_request.param, UInt<3>(0h2))
node _T_586 = or(_T_584, _T_585)
node _T_587 = eq(new_request.param, UInt<3>(0h5))
node _T_588 = or(_T_586, _T_587)
node _T_589 = and(new_meta.clients, new_clientBit)
node _T_590 = neq(_T_589, UInt<1>(0h0))
node _T_591 = and(_T_588, _T_590)
when _T_591 :
connect s_writeback, UInt<1>(0h0)
node _T_592 = asUInt(reset)
node _T_593 = eq(_T_592, UInt<1>(0h0))
when _T_593 :
node _T_594 = eq(new_meta.hit, UInt<1>(0h0))
when _T_594 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69
assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69
else :
node _T_595 = and(new_request.control, UInt<1>(0h1))
when _T_595 :
connect s_flush, UInt<1>(0h0)
when new_meta.hit :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_596 = neq(new_meta.clients, UInt<1>(0h0))
node _T_597 = and(UInt<1>(0h1), _T_596)
when _T_597 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
else :
connect s_execute, UInt<1>(0h0)
node _T_598 = eq(new_meta.hit, UInt<1>(0h0))
node _T_599 = neq(new_meta.state, UInt<2>(0h0))
node _T_600 = and(_T_598, _T_599)
when _T_600 :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_601 = neq(new_meta.clients, UInt<1>(0h0))
node _T_602 = and(UInt<1>(0h1), _T_601)
when _T_602 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
node _T_603 = eq(new_meta.hit, UInt<1>(0h0))
node _T_604 = eq(new_meta.state, UInt<2>(0h1))
node _T_605 = and(_T_604, new_needT)
node _T_606 = or(_T_603, _T_605)
when _T_606 :
connect s_acquire, UInt<1>(0h0)
connect w_grantfirst, UInt<1>(0h0)
connect w_grantlast, UInt<1>(0h0)
connect w_grant, UInt<1>(0h0)
connect s_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_607 = eq(new_meta.state, UInt<2>(0h2))
node _T_608 = or(new_needT, _T_607)
node _T_609 = and(new_meta.hit, _T_608)
node _T_610 = not(new_skipProbe)
node _T_611 = and(new_meta.clients, _T_610)
node _T_612 = neq(_T_611, UInt<1>(0h0))
node _T_613 = and(_T_609, _T_612)
node _T_614 = and(UInt<1>(0h1), _T_613)
when _T_614 :
connect s_pprobe, UInt<1>(0h0)
connect w_pprobeackfirst, UInt<1>(0h0)
connect w_pprobeacklast, UInt<1>(0h0)
connect w_pprobeack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_615 = eq(new_request.opcode, UInt<3>(0h6))
node _T_616 = eq(new_request.opcode, UInt<3>(0h7))
node _T_617 = or(_T_615, _T_616)
when _T_617 :
connect w_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_618 = bits(new_request.opcode, 2, 2)
node _T_619 = eq(_T_618, UInt<1>(0h0))
node _T_620 = and(_T_619, new_meta.hit)
node _T_621 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_622 = and(_T_620, _T_621)
when _T_622 :
connect s_writeback, UInt<1>(0h0) | module MSHR_5( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input [7:0] io_directory_bits_clients, // @[MSHR.scala:86:14]
input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [9:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [2:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output [7:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output [7:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire [7:0] final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire [7:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T = 1'h0; // @[MSHR.scala:279:38]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _excluded_client_T_9 = 1'h0; // @[MSHR.scala:279:57]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire allocate_as_full_prio_0 = 1'h0; // @[MSHR.scala:504:34]
wire new_request_prio_0 = 1'h0; // @[MSHR.scala:506:24]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire [7:0] _io_schedule_bits_b_bits_clients_T = 8'hFF; // @[MSHR.scala:289:53]
wire [7:0] _last_probe_T_1 = 8'hFF; // @[MSHR.scala:459:66]
wire [7:0] invalid_clients = 8'h0; // @[MSHR.scala:268:21]
wire [7:0] excluded_client = 8'h0; // @[MSHR.scala:279:28]
wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7]
wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire [7:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire [7:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire [7:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire [7:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [12:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [9:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg [7:0] meta_clients; // @[MSHR.scala:100:17]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients; // @[MSHR.scala:100:17, :289:51]
wire [7:0] _last_probe_T_2 = meta_clients; // @[MSHR.scala:100:17, :459:64]
reg [12:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [2:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg [7:0] probes_done; // @[MSHR.scala:150:24]
reg [7:0] probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire [7:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire _req_clientBit_T = request_source == 6'h3C; // @[Parameters.scala:46:9]
wire _req_clientBit_T_1 = request_source == 6'h38; // @[Parameters.scala:46:9]
wire _req_clientBit_T_2 = request_source == 6'h34; // @[Parameters.scala:46:9]
wire _req_clientBit_T_3 = request_source == 6'h30; // @[Parameters.scala:46:9]
wire _req_clientBit_T_4 = request_source == 6'h2C; // @[Parameters.scala:46:9]
wire _req_clientBit_T_5 = request_source == 6'h28; // @[Parameters.scala:46:9]
wire _req_clientBit_T_6 = request_source == 6'h24; // @[Parameters.scala:46:9]
wire _req_clientBit_T_7 = request_source == 6'h20; // @[Parameters.scala:46:9]
wire [1:0] req_clientBit_lo_lo = {_req_clientBit_T_1, _req_clientBit_T}; // @[Parameters.scala:46:9]
wire [1:0] req_clientBit_lo_hi = {_req_clientBit_T_3, _req_clientBit_T_2}; // @[Parameters.scala:46:9]
wire [3:0] req_clientBit_lo = {req_clientBit_lo_hi, req_clientBit_lo_lo}; // @[Parameters.scala:201:10]
wire [1:0] req_clientBit_hi_lo = {_req_clientBit_T_5, _req_clientBit_T_4}; // @[Parameters.scala:46:9]
wire [1:0] req_clientBit_hi_hi = {_req_clientBit_T_7, _req_clientBit_T_6}; // @[Parameters.scala:46:9]
wire [3:0] req_clientBit_hi = {req_clientBit_hi_hi, req_clientBit_hi_lo}; // @[Parameters.scala:201:10]
wire [7:0] req_clientBit = {req_clientBit_hi, req_clientBit_lo}; // @[Parameters.scala:201:10]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire _meta_no_clients_T = |meta_clients; // @[MSHR.scala:100:17, :220:39]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire [7:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 8'h0; // @[Parameters.scala:201:10, :282:66]
wire [7:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire [7:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire [7:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire [7:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire [7:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire [7:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire [7:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 8'h0; // @[MSHR.scala:100:17, :245:{40,64}]
wire [7:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 8'h0; // @[Parameters.scala:201:10]
wire [7:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire [7:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire [7:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 8'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire [7:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10]
wire _honour_BtoT_T_1 = |_honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 8'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire evict_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire before_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire after_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _probe_bit_T = io_sinkc_bits_source_0 == 6'h3C; // @[Parameters.scala:46:9]
wire _probe_bit_T_1 = io_sinkc_bits_source_0 == 6'h38; // @[Parameters.scala:46:9]
wire _probe_bit_T_2 = io_sinkc_bits_source_0 == 6'h34; // @[Parameters.scala:46:9]
wire _probe_bit_T_3 = io_sinkc_bits_source_0 == 6'h30; // @[Parameters.scala:46:9]
wire _probe_bit_T_4 = io_sinkc_bits_source_0 == 6'h2C; // @[Parameters.scala:46:9]
wire _probe_bit_T_5 = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9]
wire _probe_bit_T_6 = io_sinkc_bits_source_0 == 6'h24; // @[Parameters.scala:46:9]
wire _probe_bit_T_7 = io_sinkc_bits_source_0 == 6'h20; // @[Parameters.scala:46:9]
wire [1:0] probe_bit_lo_lo = {_probe_bit_T_1, _probe_bit_T}; // @[Parameters.scala:46:9]
wire [1:0] probe_bit_lo_hi = {_probe_bit_T_3, _probe_bit_T_2}; // @[Parameters.scala:46:9]
wire [3:0] probe_bit_lo = {probe_bit_lo_hi, probe_bit_lo_lo}; // @[Parameters.scala:201:10]
wire [1:0] probe_bit_hi_lo = {_probe_bit_T_5, _probe_bit_T_4}; // @[Parameters.scala:46:9]
wire [1:0] probe_bit_hi_hi = {_probe_bit_T_7, _probe_bit_T_6}; // @[Parameters.scala:46:9]
wire [3:0] probe_bit_hi = {probe_bit_hi_hi, probe_bit_hi_lo}; // @[Parameters.scala:201:10]
wire [7:0] probe_bit = {probe_bit_hi, probe_bit_lo}; // @[Parameters.scala:201:10]
wire [7:0] _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:201:10]
wire [7:0] _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire [7:0] _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire [7:0] _probes_toN_T = probe_toN ? probe_bit : 8'h0; // @[Parameters.scala:201:10, :282:66]
wire [7:0] _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [7:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _new_clientBit_T = new_request_source == 6'h3C; // @[Parameters.scala:46:9]
wire _new_clientBit_T_1 = new_request_source == 6'h38; // @[Parameters.scala:46:9]
wire _new_clientBit_T_2 = new_request_source == 6'h34; // @[Parameters.scala:46:9]
wire _new_clientBit_T_3 = new_request_source == 6'h30; // @[Parameters.scala:46:9]
wire _new_clientBit_T_4 = new_request_source == 6'h2C; // @[Parameters.scala:46:9]
wire _new_clientBit_T_5 = new_request_source == 6'h28; // @[Parameters.scala:46:9]
wire _new_clientBit_T_6 = new_request_source == 6'h24; // @[Parameters.scala:46:9]
wire _new_clientBit_T_7 = new_request_source == 6'h20; // @[Parameters.scala:46:9]
wire [1:0] new_clientBit_lo_lo = {_new_clientBit_T_1, _new_clientBit_T}; // @[Parameters.scala:46:9]
wire [1:0] new_clientBit_lo_hi = {_new_clientBit_T_3, _new_clientBit_T_2}; // @[Parameters.scala:46:9]
wire [3:0] new_clientBit_lo = {new_clientBit_lo_hi, new_clientBit_lo_lo}; // @[Parameters.scala:201:10]
wire [1:0] new_clientBit_hi_lo = {_new_clientBit_T_5, _new_clientBit_T_4}; // @[Parameters.scala:46:9]
wire [1:0] new_clientBit_hi_hi = {_new_clientBit_T_7, _new_clientBit_T_6}; // @[Parameters.scala:46:9]
wire [3:0] new_clientBit_hi = {new_clientBit_hi_hi, new_clientBit_hi_lo}; // @[Parameters.scala:201:10]
wire [7:0] new_clientBit = {new_clientBit_hi, new_clientBit_lo}; // @[Parameters.scala:201:10]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire [7:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 8'h0; // @[Parameters.scala:201:10, :279:106]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire prior_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_62 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_62( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module Router_10 :
input clock : Clock
input reset : Reset
output auto : { debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, egress_nodes_out_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}}
wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}
invalidate destNodesIn.vc_free
invalidate destNodesIn.credit_return
invalidate destNodesIn.flit[0].bits.virt_channel_id
invalidate destNodesIn.flit[0].bits.flow.egress_node_id
invalidate destNodesIn.flit[0].bits.flow.egress_node
invalidate destNodesIn.flit[0].bits.flow.ingress_node_id
invalidate destNodesIn.flit[0].bits.flow.ingress_node
invalidate destNodesIn.flit[0].bits.flow.vnet_id
invalidate destNodesIn.flit[0].bits.payload
invalidate destNodesIn.flit[0].bits.tail
invalidate destNodesIn.flit[0].bits.head
invalidate destNodesIn.flit[0].valid
inst monitor of NoCMonitor_10
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.vc_free, destNodesIn.vc_free
connect monitor.io.in.credit_return, destNodesIn.credit_return
connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id
connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id
connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node
connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id
connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node
connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id
connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload
connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail
connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head
connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid
wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}
invalidate sourceNodesOut.vc_free
invalidate sourceNodesOut.credit_return
invalidate sourceNodesOut.flit[0].bits.virt_channel_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node
invalidate sourceNodesOut.flit[0].bits.flow.vnet_id
invalidate sourceNodesOut.flit[0].bits.payload
invalidate sourceNodesOut.flit[0].bits.tail
invalidate sourceNodesOut.flit[0].bits.head
invalidate sourceNodesOut.flit[0].valid
wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesIn.flit.bits.egress_id
invalidate ingressNodesIn.flit.bits.payload
invalidate ingressNodesIn.flit.bits.tail
invalidate ingressNodesIn.flit.bits.head
invalidate ingressNodesIn.flit.valid
invalidate ingressNodesIn.flit.ready
wire ingressNodesIn_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesIn_1.flit.bits.egress_id
invalidate ingressNodesIn_1.flit.bits.payload
invalidate ingressNodesIn_1.flit.bits.tail
invalidate ingressNodesIn_1.flit.bits.head
invalidate ingressNodesIn_1.flit.valid
invalidate ingressNodesIn_1.flit.ready
wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesOut.flit.bits.ingress_id
invalidate egressNodesOut.flit.bits.payload
invalidate egressNodesOut.flit.bits.tail
invalidate egressNodesOut.flit.bits.head
invalidate egressNodesOut.flit.valid
invalidate egressNodesOut.flit.ready
wire egressNodesOut_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesOut_1.flit.bits.ingress_id
invalidate egressNodesOut_1.flit.bits.payload
invalidate egressNodesOut_1.flit.bits.tail
invalidate egressNodesOut_1.flit.bits.head
invalidate egressNodesOut_1.flit.valid
invalidate egressNodesOut_1.flit.ready
wire egressNodesOut_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesOut_2.flit.bits.ingress_id
invalidate egressNodesOut_2.flit.bits.payload
invalidate egressNodesOut_2.flit.bits.tail
invalidate egressNodesOut_2.flit.bits.head
invalidate egressNodesOut_2.flit.valid
invalidate egressNodesOut_2.flit.ready
wire debugNodeOut : { va_stall : UInt[3], sa_stall : UInt[3]}
invalidate debugNodeOut.sa_stall[0]
invalidate debugNodeOut.sa_stall[1]
invalidate debugNodeOut.sa_stall[2]
invalidate debugNodeOut.va_stall[0]
invalidate debugNodeOut.va_stall[1]
invalidate debugNodeOut.va_stall[2]
connect destNodesIn, auto.dest_nodes_in
connect auto.source_nodes_out, sourceNodesOut
connect ingressNodesIn, auto.ingress_nodes_in_0
connect ingressNodesIn_1, auto.ingress_nodes_in_1
connect auto.egress_nodes_out_0, egressNodesOut
connect auto.egress_nodes_out_1, egressNodesOut_1
connect auto.egress_nodes_out_2, egressNodesOut_2
connect auto.debug_out, debugNodeOut
inst input_unit_0_from_26 of InputUnit_10
connect input_unit_0_from_26.clock, clock
connect input_unit_0_from_26.reset, reset
inst ingress_unit_1_from_35 of IngressUnit_26
connect ingress_unit_1_from_35.clock, clock
connect ingress_unit_1_from_35.reset, reset
inst ingress_unit_2_from_36 of IngressUnit_27
connect ingress_unit_2_from_36.clock, clock
connect ingress_unit_2_from_36.reset, reset
inst output_unit_0_to_26 of OutputUnit_10
connect output_unit_0_to_26.clock, clock
connect output_unit_0_to_26.reset, reset
inst egress_unit_1_to_30 of EgressUnit_24
connect egress_unit_1_to_30.clock, clock
connect egress_unit_1_to_30.reset, reset
inst egress_unit_2_to_31 of EgressUnit_25
connect egress_unit_2_to_31.clock, clock
connect egress_unit_2_to_31.reset, reset
inst egress_unit_3_to_32 of EgressUnit_26
connect egress_unit_3_to_32.clock, clock
connect egress_unit_3_to_32.reset, reset
inst switch of Switch_10
connect switch.clock, clock
connect switch.reset, reset
inst switch_allocator of SwitchAllocator_10
connect switch_allocator.clock, clock
connect switch_allocator.reset, reset
inst vc_allocator of RotatingSingleVCAllocator_10
connect vc_allocator.clock, clock
connect vc_allocator.reset, reset
inst route_computer of RouteComputer_10
connect route_computer.clock, clock
connect route_computer.reset, reset
node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid)
node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid)
node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid)
node _fires_count_T_3 = add(_fires_count_T_1, _fires_count_T_2)
node _fires_count_T_4 = bits(_fires_count_T_3, 1, 0)
node _fires_count_T_5 = add(_fires_count_T, _fires_count_T_4)
node _fires_count_T_6 = bits(_fires_count_T_5, 1, 0)
wire fires_count : UInt
connect fires_count, _fires_count_T_6
connect input_unit_0_from_26.io.in, destNodesIn
connect ingress_unit_1_from_35.io.in, ingressNodesIn.flit
connect ingress_unit_2_from_36.io.in, ingressNodesIn_1.flit
connect output_unit_0_to_26.io.out.vc_free, sourceNodesOut.vc_free
connect output_unit_0_to_26.io.out.credit_return, sourceNodesOut.credit_return
connect sourceNodesOut.flit, output_unit_0_to_26.io.out.flit
connect egressNodesOut.flit.bits, egress_unit_1_to_30.io.out.bits
connect egressNodesOut.flit.valid, egress_unit_1_to_30.io.out.valid
connect egress_unit_1_to_30.io.out.ready, egressNodesOut.flit.ready
connect egressNodesOut_1.flit.bits, egress_unit_2_to_31.io.out.bits
connect egressNodesOut_1.flit.valid, egress_unit_2_to_31.io.out.valid
connect egress_unit_2_to_31.io.out.ready, egressNodesOut_1.flit.ready
connect egressNodesOut_2.flit.bits, egress_unit_3_to_32.io.out.bits
connect egressNodesOut_2.flit.valid, egress_unit_3_to_32.io.out.valid
connect egress_unit_3_to_32.io.out.ready, egressNodesOut_2.flit.ready
connect route_computer.io.req.`0`, input_unit_0_from_26.io.router_req
connect route_computer.io.req.`1`, ingress_unit_1_from_35.io.router_req
connect route_computer.io.req.`2`, ingress_unit_2_from_36.io.router_req
connect input_unit_0_from_26.io.router_resp, route_computer.io.resp.`0`
connect ingress_unit_1_from_35.io.router_resp, route_computer.io.resp.`1`
connect ingress_unit_2_from_36.io.router_resp, route_computer.io.resp.`2`
connect vc_allocator.io.req.`0`, input_unit_0_from_26.io.vcalloc_req
connect vc_allocator.io.req.`1`, ingress_unit_1_from_35.io.vcalloc_req
connect vc_allocator.io.req.`2`, ingress_unit_2_from_36.io.vcalloc_req
connect input_unit_0_from_26.io.vcalloc_resp, vc_allocator.io.resp.`0`
connect ingress_unit_1_from_35.io.vcalloc_resp, vc_allocator.io.resp.`1`
connect ingress_unit_2_from_36.io.vcalloc_resp, vc_allocator.io.resp.`2`
connect output_unit_0_to_26.io.allocs, vc_allocator.io.out_allocs.`0`
connect egress_unit_1_to_30.io.allocs, vc_allocator.io.out_allocs.`1`
connect egress_unit_2_to_31.io.allocs, vc_allocator.io.out_allocs.`2`
connect egress_unit_3_to_32.io.allocs, vc_allocator.io.out_allocs.`3`
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_26.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_26.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_26.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_26.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_26.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_26.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_26.io.channel_status[1].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_26.io.channel_status[1].flow.egress_node
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_26.io.channel_status[1].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_26.io.channel_status[1].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_26.io.channel_status[1].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_26.io.channel_status[1].occupied
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_26.io.channel_status[2].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_26.io.channel_status[2].flow.egress_node
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_26.io.channel_status[2].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_26.io.channel_status[2].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_26.io.channel_status[2].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_26.io.channel_status[2].occupied
connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_26.io.channel_status[3].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_26.io.channel_status[3].flow.egress_node
connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_26.io.channel_status[3].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_26.io.channel_status[3].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_26.io.channel_status[3].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_26.io.channel_status[3].occupied
connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_26.io.channel_status[4].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_26.io.channel_status[4].flow.egress_node
connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_26.io.channel_status[4].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_26.io.channel_status[4].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_26.io.channel_status[4].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_26.io.channel_status[4].occupied
connect vc_allocator.io.channel_status.`0`[5].flow.egress_node_id, output_unit_0_to_26.io.channel_status[5].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[5].flow.egress_node, output_unit_0_to_26.io.channel_status[5].flow.egress_node
connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node_id, output_unit_0_to_26.io.channel_status[5].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node, output_unit_0_to_26.io.channel_status[5].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[5].flow.vnet_id, output_unit_0_to_26.io.channel_status[5].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[5].occupied, output_unit_0_to_26.io.channel_status[5].occupied
connect vc_allocator.io.channel_status.`0`[6].flow.egress_node_id, output_unit_0_to_26.io.channel_status[6].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[6].flow.egress_node, output_unit_0_to_26.io.channel_status[6].flow.egress_node
connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node_id, output_unit_0_to_26.io.channel_status[6].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node, output_unit_0_to_26.io.channel_status[6].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[6].flow.vnet_id, output_unit_0_to_26.io.channel_status[6].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[6].occupied, output_unit_0_to_26.io.channel_status[6].occupied
connect vc_allocator.io.channel_status.`0`[7].flow.egress_node_id, output_unit_0_to_26.io.channel_status[7].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[7].flow.egress_node, output_unit_0_to_26.io.channel_status[7].flow.egress_node
connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node_id, output_unit_0_to_26.io.channel_status[7].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node, output_unit_0_to_26.io.channel_status[7].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[7].flow.vnet_id, output_unit_0_to_26.io.channel_status[7].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[7].occupied, output_unit_0_to_26.io.channel_status[7].occupied
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, egress_unit_1_to_30.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, egress_unit_1_to_30.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, egress_unit_1_to_30.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, egress_unit_1_to_30.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, egress_unit_1_to_30.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[0].occupied, egress_unit_1_to_30.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, egress_unit_2_to_31.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, egress_unit_2_to_31.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, egress_unit_2_to_31.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, egress_unit_2_to_31.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, egress_unit_2_to_31.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[0].occupied, egress_unit_2_to_31.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`3`[0].flow.egress_node_id, egress_unit_3_to_32.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`3`[0].flow.egress_node, egress_unit_3_to_32.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`3`[0].flow.ingress_node_id, egress_unit_3_to_32.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`3`[0].flow.ingress_node, egress_unit_3_to_32.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`3`[0].flow.vnet_id, egress_unit_3_to_32.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`3`[0].occupied, egress_unit_3_to_32.io.channel_status[0].occupied
connect input_unit_0_from_26.io.out_credit_available.`0`[0], output_unit_0_to_26.io.credit_available[0]
connect input_unit_0_from_26.io.out_credit_available.`0`[1], output_unit_0_to_26.io.credit_available[1]
connect input_unit_0_from_26.io.out_credit_available.`0`[2], output_unit_0_to_26.io.credit_available[2]
connect input_unit_0_from_26.io.out_credit_available.`0`[3], output_unit_0_to_26.io.credit_available[3]
connect input_unit_0_from_26.io.out_credit_available.`0`[4], output_unit_0_to_26.io.credit_available[4]
connect input_unit_0_from_26.io.out_credit_available.`0`[5], output_unit_0_to_26.io.credit_available[5]
connect input_unit_0_from_26.io.out_credit_available.`0`[6], output_unit_0_to_26.io.credit_available[6]
connect input_unit_0_from_26.io.out_credit_available.`0`[7], output_unit_0_to_26.io.credit_available[7]
connect input_unit_0_from_26.io.out_credit_available.`1`[0], egress_unit_1_to_30.io.credit_available[0]
connect input_unit_0_from_26.io.out_credit_available.`2`[0], egress_unit_2_to_31.io.credit_available[0]
connect input_unit_0_from_26.io.out_credit_available.`3`[0], egress_unit_3_to_32.io.credit_available[0]
connect ingress_unit_1_from_35.io.out_credit_available.`0`[0], output_unit_0_to_26.io.credit_available[0]
connect ingress_unit_1_from_35.io.out_credit_available.`0`[1], output_unit_0_to_26.io.credit_available[1]
connect ingress_unit_1_from_35.io.out_credit_available.`0`[2], output_unit_0_to_26.io.credit_available[2]
connect ingress_unit_1_from_35.io.out_credit_available.`0`[3], output_unit_0_to_26.io.credit_available[3]
connect ingress_unit_1_from_35.io.out_credit_available.`0`[4], output_unit_0_to_26.io.credit_available[4]
connect ingress_unit_1_from_35.io.out_credit_available.`0`[5], output_unit_0_to_26.io.credit_available[5]
connect ingress_unit_1_from_35.io.out_credit_available.`0`[6], output_unit_0_to_26.io.credit_available[6]
connect ingress_unit_1_from_35.io.out_credit_available.`0`[7], output_unit_0_to_26.io.credit_available[7]
connect ingress_unit_1_from_35.io.out_credit_available.`1`[0], egress_unit_1_to_30.io.credit_available[0]
connect ingress_unit_1_from_35.io.out_credit_available.`2`[0], egress_unit_2_to_31.io.credit_available[0]
connect ingress_unit_1_from_35.io.out_credit_available.`3`[0], egress_unit_3_to_32.io.credit_available[0]
connect ingress_unit_2_from_36.io.out_credit_available.`0`[0], output_unit_0_to_26.io.credit_available[0]
connect ingress_unit_2_from_36.io.out_credit_available.`0`[1], output_unit_0_to_26.io.credit_available[1]
connect ingress_unit_2_from_36.io.out_credit_available.`0`[2], output_unit_0_to_26.io.credit_available[2]
connect ingress_unit_2_from_36.io.out_credit_available.`0`[3], output_unit_0_to_26.io.credit_available[3]
connect ingress_unit_2_from_36.io.out_credit_available.`0`[4], output_unit_0_to_26.io.credit_available[4]
connect ingress_unit_2_from_36.io.out_credit_available.`0`[5], output_unit_0_to_26.io.credit_available[5]
connect ingress_unit_2_from_36.io.out_credit_available.`0`[6], output_unit_0_to_26.io.credit_available[6]
connect ingress_unit_2_from_36.io.out_credit_available.`0`[7], output_unit_0_to_26.io.credit_available[7]
connect ingress_unit_2_from_36.io.out_credit_available.`1`[0], egress_unit_1_to_30.io.credit_available[0]
connect ingress_unit_2_from_36.io.out_credit_available.`2`[0], egress_unit_2_to_31.io.credit_available[0]
connect ingress_unit_2_from_36.io.out_credit_available.`3`[0], egress_unit_3_to_32.io.credit_available[0]
connect switch_allocator.io.req.`0`[0], input_unit_0_from_26.io.salloc_req[0]
connect switch_allocator.io.req.`1`[0], ingress_unit_1_from_35.io.salloc_req[0]
connect switch_allocator.io.req.`2`[0], ingress_unit_2_from_36.io.salloc_req[0]
connect output_unit_0_to_26.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail
connect output_unit_0_to_26.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc
connect output_unit_0_to_26.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail
connect output_unit_0_to_26.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc
connect output_unit_0_to_26.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail
connect output_unit_0_to_26.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc
connect output_unit_0_to_26.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail
connect output_unit_0_to_26.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc
connect output_unit_0_to_26.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail
connect output_unit_0_to_26.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc
connect output_unit_0_to_26.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`0`[5].tail
connect output_unit_0_to_26.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`0`[5].alloc
connect output_unit_0_to_26.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`0`[6].tail
connect output_unit_0_to_26.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`0`[6].alloc
connect output_unit_0_to_26.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`0`[7].tail
connect output_unit_0_to_26.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`0`[7].alloc
connect egress_unit_1_to_30.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail
connect egress_unit_1_to_30.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc
connect egress_unit_2_to_31.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail
connect egress_unit_2_to_31.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc
connect egress_unit_3_to_32.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`3`[0].tail
connect egress_unit_3_to_32.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`3`[0].alloc
connect switch.io.in.`0`[0], input_unit_0_from_26.io.out[0]
connect switch.io.in.`1`[0], ingress_unit_1_from_35.io.out[0]
connect switch.io.in.`2`[0], ingress_unit_2_from_36.io.out[0]
connect output_unit_0_to_26.io.in, switch.io.out.`0`
connect egress_unit_1_to_30.io.in, switch.io.out.`1`
connect egress_unit_2_to_31.io.in, switch.io.out.`2`
connect egress_unit_3_to_32.io.in, switch.io.out.`3`
reg REG : { `3` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `2` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock
connect REG, switch_allocator.io.switch_sel
connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0]
connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0]
connect switch.io.sel.`0`[0].`2`[0], REG.`0`[0].`2`[0]
connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0]
connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0]
connect switch.io.sel.`1`[0].`2`[0], REG.`1`[0].`2`[0]
connect switch.io.sel.`2`[0].`0`[0], REG.`2`[0].`0`[0]
connect switch.io.sel.`2`[0].`1`[0], REG.`2`[0].`1`[0]
connect switch.io.sel.`2`[0].`2`[0], REG.`2`[0].`2`[0]
connect switch.io.sel.`3`[0].`0`[0], REG.`3`[0].`0`[0]
connect switch.io.sel.`3`[0].`1`[0], REG.`3`[0].`1`[0]
connect switch.io.sel.`3`[0].`2`[0], REG.`3`[0].`2`[0]
connect input_unit_0_from_26.io.block, UInt<1>(0h0)
connect ingress_unit_1_from_35.io.block, UInt<1>(0h0)
connect ingress_unit_2_from_36.io.block, UInt<1>(0h0)
connect debugNodeOut.va_stall[0], input_unit_0_from_26.io.debug.va_stall
connect debugNodeOut.va_stall[1], ingress_unit_1_from_35.io.debug.va_stall
connect debugNodeOut.va_stall[2], ingress_unit_2_from_36.io.debug.va_stall
connect debugNodeOut.sa_stall[0], input_unit_0_from_26.io.debug.sa_stall
connect debugNodeOut.sa_stall[1], ingress_unit_1_from_35.io.debug.sa_stall
connect debugNodeOut.sa_stall[2], ingress_unit_2_from_36.io.debug.sa_stall
regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1))
node _debug_tsc_T_1 = tail(_debug_tsc_T, 1)
connect debug_tsc, _debug_tsc_T_1
regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_sample_T = add(debug_sample, UInt<1>(0h1))
node _debug_sample_T_1 = tail(_debug_sample_T, 1)
connect debug_sample, _debug_sample_T_1
inst plusarg_reader of plusarg_reader_28
node _T = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_1 = tail(_T, 1)
node _T_2 = eq(debug_sample, _T_1)
when _T_2 :
connect debug_sample, UInt<1>(0h0)
regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid)
node _util_ctr_T_1 = tail(_util_ctr_T, 1)
connect util_ctr, _util_ctr_T_1
node _fired_T = or(fired, destNodesIn.flit[0].valid)
connect fired, _fired_T
node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_5 = tail(_T_4, 1)
node _T_6 = eq(debug_sample, _T_5)
node _T_7 = and(_T_3, _T_6)
node _T_8 = and(_T_7, fired)
when _T_8 :
node _T_9 = asUInt(reset)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
printf(clock, UInt<1>(0h1), "nocsample %d 26 10 %d\n", debug_tsc, util_ctr) : printf
connect fired, destNodesIn.flit[0].valid
node _T_11 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid)
regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_2 = add(util_ctr_1, _T_11)
node _util_ctr_T_3 = tail(_util_ctr_T_2, 1)
connect util_ctr_1, _util_ctr_T_3
node _fired_T_1 = or(fired_1, _T_11)
connect fired_1, _fired_T_1
node _T_12 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_13 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_14 = tail(_T_13, 1)
node _T_15 = eq(debug_sample, _T_14)
node _T_16 = and(_T_12, _T_15)
node _T_17 = and(_T_16, fired_1)
when _T_17 :
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "nocsample %d i35 10 %d\n", debug_tsc, util_ctr_1) : printf_1
connect fired_1, _T_11
node _T_20 = and(ingressNodesIn_1.flit.ready, ingressNodesIn_1.flit.valid)
regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_4 = add(util_ctr_2, _T_20)
node _util_ctr_T_5 = tail(_util_ctr_T_4, 1)
connect util_ctr_2, _util_ctr_T_5
node _fired_T_2 = or(fired_2, _T_20)
connect fired_2, _fired_T_2
node _T_21 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_22 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_23 = tail(_T_22, 1)
node _T_24 = eq(debug_sample, _T_23)
node _T_25 = and(_T_21, _T_24)
node _T_26 = and(_T_25, fired_2)
when _T_26 :
node _T_27 = asUInt(reset)
node _T_28 = eq(_T_27, UInt<1>(0h0))
when _T_28 :
printf(clock, UInt<1>(0h1), "nocsample %d i36 10 %d\n", debug_tsc, util_ctr_2) : printf_2
connect fired_2, _T_20
node _T_29 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid)
regreset util_ctr_3 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_3 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_6 = add(util_ctr_3, _T_29)
node _util_ctr_T_7 = tail(_util_ctr_T_6, 1)
connect util_ctr_3, _util_ctr_T_7
node _fired_T_3 = or(fired_3, _T_29)
connect fired_3, _fired_T_3
node _T_30 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_31 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_32 = tail(_T_31, 1)
node _T_33 = eq(debug_sample, _T_32)
node _T_34 = and(_T_30, _T_33)
node _T_35 = and(_T_34, fired_3)
when _T_35 :
node _T_36 = asUInt(reset)
node _T_37 = eq(_T_36, UInt<1>(0h0))
when _T_37 :
printf(clock, UInt<1>(0h1), "nocsample %d 10 e30 %d\n", debug_tsc, util_ctr_3) : printf_3
connect fired_3, _T_29
node _T_38 = and(egressNodesOut_1.flit.ready, egressNodesOut_1.flit.valid)
regreset util_ctr_4 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_4 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_8 = add(util_ctr_4, _T_38)
node _util_ctr_T_9 = tail(_util_ctr_T_8, 1)
connect util_ctr_4, _util_ctr_T_9
node _fired_T_4 = or(fired_4, _T_38)
connect fired_4, _fired_T_4
node _T_39 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_40 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_41 = tail(_T_40, 1)
node _T_42 = eq(debug_sample, _T_41)
node _T_43 = and(_T_39, _T_42)
node _T_44 = and(_T_43, fired_4)
when _T_44 :
node _T_45 = asUInt(reset)
node _T_46 = eq(_T_45, UInt<1>(0h0))
when _T_46 :
printf(clock, UInt<1>(0h1), "nocsample %d 10 e31 %d\n", debug_tsc, util_ctr_4) : printf_4
connect fired_4, _T_38
node _T_47 = and(egressNodesOut_2.flit.ready, egressNodesOut_2.flit.valid)
regreset util_ctr_5 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_5 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_10 = add(util_ctr_5, _T_47)
node _util_ctr_T_11 = tail(_util_ctr_T_10, 1)
connect util_ctr_5, _util_ctr_T_11
node _fired_T_5 = or(fired_5, _T_47)
connect fired_5, _fired_T_5
node _T_48 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_49 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_50 = tail(_T_49, 1)
node _T_51 = eq(debug_sample, _T_50)
node _T_52 = and(_T_48, _T_51)
node _T_53 = and(_T_52, fired_5)
when _T_53 :
node _T_54 = asUInt(reset)
node _T_55 = eq(_T_54, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "nocsample %d 10 e32 %d\n", debug_tsc, util_ctr_5) : printf_5
connect fired_5, _T_47 | module Router_10( // @[Router.scala:89:25]
input clock, // @[Router.scala:89:25]
input reset, // @[Router.scala:89:25]
output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_2_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_2_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_2_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_egress_nodes_out_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25]
);
wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_6; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_7; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_6; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_7; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_3_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_5_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_6_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_7_alloc; // @[Router.scala:133:30]
wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_3_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_3_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_5_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_6_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_7_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34]
wire _switch_io_out_3_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_3_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_3_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_3_0_bits_payload; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_3_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_3_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_2_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_1_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_0_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _egress_unit_3_to_32_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_3_to_32_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_3_to_32_io_out_valid; // @[Router.scala:125:13]
wire _egress_unit_2_to_31_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_2_to_31_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_2_to_31_io_out_valid; // @[Router.scala:125:13]
wire _egress_unit_1_to_30_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_1_to_30_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_1_to_30_io_out_valid; // @[Router.scala:125:13]
wire _output_unit_0_to_26_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_credit_available_2; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_credit_available_3; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_credit_available_4; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_credit_available_5; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_credit_available_6; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_credit_available_7; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_channel_status_2_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_channel_status_3_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_channel_status_4_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_channel_status_5_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_channel_status_6_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_channel_status_7_occupied; // @[Router.scala:122:13]
wire _ingress_unit_2_from_36_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [72:0] _ingress_unit_2_from_36_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_2_from_36_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [4:0] _ingress_unit_2_from_36_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_2_from_36_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [4:0] _ingress_unit_2_from_36_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_2_from_36_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_2_from_36_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_2_from_36_io_in_ready; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [72:0] _ingress_unit_1_from_35_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_1_from_35_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [4:0] _ingress_unit_1_from_35_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_1_from_35_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [4:0] _ingress_unit_1_from_35_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_1_from_35_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_1_from_35_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_1_from_35_io_in_ready; // @[Router.scala:116:13]
wire _input_unit_0_from_26_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_26_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_26_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_0_from_26_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_26_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_0_from_26_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_0_from_26_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_26_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_26_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_26_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_26_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_26_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_26_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_35_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_2_ready & _ingress_unit_2_from_36_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35]
reg REG_3_0_2_0; // @[Router.scala:178:14]
reg REG_3_0_1_0; // @[Router.scala:178:14]
reg REG_3_0_0_0; // @[Router.scala:178:14]
reg REG_2_0_2_0; // @[Router.scala:178:14]
reg REG_2_0_1_0; // @[Router.scala:178:14]
reg REG_2_0_0_0; // @[Router.scala:178:14]
reg REG_1_0_2_0; // @[Router.scala:178:14]
reg REG_1_0_1_0; // @[Router.scala:178:14]
reg REG_1_0_0_0; // @[Router.scala:178:14]
reg REG_0_0_2_0; // @[Router.scala:178:14]
reg REG_0_0_1_0; // @[Router.scala:178:14]
reg [63:0] debug_tsc; // @[Router.scala:195:28]
reg [63:0] debug_sample; // @[Router.scala:197:31]
wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11]
reg [63:0] util_ctr; // @[Router.scala:203:29]
reg fired; // @[Router.scala:204:26]
wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11]
wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_1; // @[Router.scala:203:29]
reg fired_1; // @[Router.scala:204:26]
wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_2; // @[Router.scala:203:29]
reg fired_2; // @[Router.scala:204:26]
wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_3; // @[Router.scala:203:29]
reg fired_3; // @[Router.scala:204:26]
wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_4; // @[Router.scala:203:29]
reg fired_4; // @[Router.scala:204:26]
wire _GEN_5 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_5; // @[Router.scala:203:29]
reg fired_5; // @[Router.scala:204:26]
wire _GEN_6 = _GEN_0 & fired_5; // @[Router.scala:204:26, :207:{33,71}] |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_88 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<5>, vc_free : UInt<5>}}
wire _in_flight_WIRE : UInt<1>[5]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
connect _in_flight_WIRE[3], UInt<1>(0h0)
connect _in_flight_WIRE[4], UInt<1>(0h0)
regreset in_flight : UInt<1>[5], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = or(_T_5, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_13 = and(_T_11, _T_12)
node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_19 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_20 = and(_T_18, _T_19)
node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_24 = and(_T_22, _T_23)
node _T_25 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_26 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_27 = and(_T_25, _T_26)
node _T_28 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_29 = and(_T_27, _T_28)
node _T_30 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_33 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_34 = and(_T_32, _T_33)
node _T_35 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_36 = and(_T_34, _T_35)
node _T_37 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_38 = and(_T_36, _T_37)
node _T_39 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_40 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_41 = and(_T_39, _T_40)
node _T_42 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_45 = and(_T_43, _T_44)
node _T_46 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_47 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_48 = and(_T_46, _T_47)
node _T_49 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_50 = and(_T_48, _T_49)
node _T_51 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_52 = and(_T_50, _T_51)
node _T_53 = or(_T_17, _T_24)
node _T_54 = or(_T_53, _T_31)
node _T_55 = or(_T_54, _T_38)
node _T_56 = or(_T_55, _T_45)
node _T_57 = or(_T_56, _T_52)
node _T_58 = or(_T_10, _T_57)
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_T_58, UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_58, UInt<1>(0h1), "") : assert_2
node _T_62 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_63 = or(_T_62, UInt<1>(0h0))
node _T_64 = asUInt(reset)
node _T_65 = eq(_T_64, UInt<1>(0h0))
when _T_65 :
node _T_66 = eq(_T_63, UInt<1>(0h0))
when _T_66 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_63, UInt<1>(0h1), "") : assert_3
node _T_67 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_68 = or(_T_67, UInt<1>(0h0))
node _T_69 = asUInt(reset)
node _T_70 = eq(_T_69, UInt<1>(0h0))
when _T_70 :
node _T_71 = eq(_T_68, UInt<1>(0h0))
when _T_71 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4
assert(clock, _T_68, UInt<1>(0h1), "") : assert_4
node _T_72 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4))
node _T_73 = or(_T_72, UInt<1>(0h0))
node _T_74 = asUInt(reset)
node _T_75 = eq(_T_74, UInt<1>(0h0))
when _T_75 :
node _T_76 = eq(_T_73, UInt<1>(0h0))
when _T_76 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5
assert(clock, _T_73, UInt<1>(0h1), "") : assert_5 | module NoCMonitor_88( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46]
wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 3'h2; // @[Monitor.scala:21:46]
wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 3'h3; // @[Monitor.scala:21:46]
wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 3'h4; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncQueue_18 :
output io : { flip enq_clock : Clock, flip enq_reset : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, flip deq_clock : Clock, flip deq_reset : UInt<1>, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}}
inst source of AsyncQueueSource_Phit_18
connect source.clock, io.enq_clock
connect source.reset, io.enq_reset
inst sink of AsyncQueueSink_Phit_18
connect sink.clock, io.deq_clock
connect sink.reset, io.deq_reset
connect source.io.enq, io.enq
connect io.deq.bits, sink.io.deq.bits
connect io.deq.valid, sink.io.deq.valid
connect sink.io.deq.ready, io.deq.ready
connect sink.io.async, source.io.async | module AsyncQueue_18( // @[AsyncQueue.scala:226:7]
input io_enq_clock, // @[AsyncQueue.scala:227:14]
input io_enq_reset, // @[AsyncQueue.scala:227:14]
output io_enq_ready, // @[AsyncQueue.scala:227:14]
input io_enq_valid, // @[AsyncQueue.scala:227:14]
input [31:0] io_enq_bits_phit, // @[AsyncQueue.scala:227:14]
input io_deq_clock, // @[AsyncQueue.scala:227:14]
input io_deq_reset, // @[AsyncQueue.scala:227:14]
input io_deq_ready, // @[AsyncQueue.scala:227:14]
output io_deq_valid, // @[AsyncQueue.scala:227:14]
output [31:0] io_deq_bits_phit // @[AsyncQueue.scala:227:14]
);
wire [3:0] _sink_io_async_ridx; // @[AsyncQueue.scala:229:70]
wire _sink_io_async_safe_ridx_valid; // @[AsyncQueue.scala:229:70]
wire _sink_io_async_safe_sink_reset_n; // @[AsyncQueue.scala:229:70]
wire [31:0] _source_io_async_mem_0_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_1_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_2_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_3_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_4_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_5_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_6_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_7_phit; // @[AsyncQueue.scala:228:70]
wire [3:0] _source_io_async_widx; // @[AsyncQueue.scala:228:70]
wire _source_io_async_safe_widx_valid; // @[AsyncQueue.scala:228:70]
wire _source_io_async_safe_source_reset_n; // @[AsyncQueue.scala:228:70]
wire io_enq_clock_0 = io_enq_clock; // @[AsyncQueue.scala:226:7]
wire io_enq_reset_0 = io_enq_reset; // @[AsyncQueue.scala:226:7]
wire io_enq_valid_0 = io_enq_valid; // @[AsyncQueue.scala:226:7]
wire [31:0] io_enq_bits_phit_0 = io_enq_bits_phit; // @[AsyncQueue.scala:226:7]
wire io_deq_clock_0 = io_deq_clock; // @[AsyncQueue.scala:226:7]
wire io_deq_reset_0 = io_deq_reset; // @[AsyncQueue.scala:226:7]
wire io_deq_ready_0 = io_deq_ready; // @[AsyncQueue.scala:226:7]
wire io_enq_ready_0; // @[AsyncQueue.scala:226:7]
wire [31:0] io_deq_bits_phit_0; // @[AsyncQueue.scala:226:7]
wire io_deq_valid_0; // @[AsyncQueue.scala:226:7]
AsyncQueueSource_Phit_18 source ( // @[AsyncQueue.scala:228:70]
.clock (io_enq_clock_0), // @[AsyncQueue.scala:226:7]
.reset (io_enq_reset_0), // @[AsyncQueue.scala:226:7]
.io_enq_ready (io_enq_ready_0),
.io_enq_valid (io_enq_valid_0), // @[AsyncQueue.scala:226:7]
.io_enq_bits_phit (io_enq_bits_phit_0), // @[AsyncQueue.scala:226:7]
.io_async_mem_0_phit (_source_io_async_mem_0_phit),
.io_async_mem_1_phit (_source_io_async_mem_1_phit),
.io_async_mem_2_phit (_source_io_async_mem_2_phit),
.io_async_mem_3_phit (_source_io_async_mem_3_phit),
.io_async_mem_4_phit (_source_io_async_mem_4_phit),
.io_async_mem_5_phit (_source_io_async_mem_5_phit),
.io_async_mem_6_phit (_source_io_async_mem_6_phit),
.io_async_mem_7_phit (_source_io_async_mem_7_phit),
.io_async_ridx (_sink_io_async_ridx), // @[AsyncQueue.scala:229:70]
.io_async_widx (_source_io_async_widx),
.io_async_safe_ridx_valid (_sink_io_async_safe_ridx_valid), // @[AsyncQueue.scala:229:70]
.io_async_safe_widx_valid (_source_io_async_safe_widx_valid),
.io_async_safe_source_reset_n (_source_io_async_safe_source_reset_n),
.io_async_safe_sink_reset_n (_sink_io_async_safe_sink_reset_n) // @[AsyncQueue.scala:229:70]
); // @[AsyncQueue.scala:228:70]
AsyncQueueSink_Phit_18 sink ( // @[AsyncQueue.scala:229:70]
.clock (io_deq_clock_0), // @[AsyncQueue.scala:226:7]
.reset (io_deq_reset_0), // @[AsyncQueue.scala:226:7]
.io_deq_ready (io_deq_ready_0), // @[AsyncQueue.scala:226:7]
.io_deq_valid (io_deq_valid_0),
.io_deq_bits_phit (io_deq_bits_phit_0),
.io_async_mem_0_phit (_source_io_async_mem_0_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_1_phit (_source_io_async_mem_1_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_2_phit (_source_io_async_mem_2_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_3_phit (_source_io_async_mem_3_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_4_phit (_source_io_async_mem_4_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_5_phit (_source_io_async_mem_5_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_6_phit (_source_io_async_mem_6_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_7_phit (_source_io_async_mem_7_phit), // @[AsyncQueue.scala:228:70]
.io_async_ridx (_sink_io_async_ridx),
.io_async_widx (_source_io_async_widx), // @[AsyncQueue.scala:228:70]
.io_async_safe_ridx_valid (_sink_io_async_safe_ridx_valid),
.io_async_safe_widx_valid (_source_io_async_safe_widx_valid), // @[AsyncQueue.scala:228:70]
.io_async_safe_source_reset_n (_source_io_async_safe_source_reset_n), // @[AsyncQueue.scala:228:70]
.io_async_safe_sink_reset_n (_sink_io_async_safe_sink_reset_n)
); // @[AsyncQueue.scala:229:70]
assign io_enq_ready = io_enq_ready_0; // @[AsyncQueue.scala:226:7]
assign io_deq_valid = io_deq_valid_0; // @[AsyncQueue.scala:226:7]
assign io_deq_bits_phit = io_deq_bits_phit_0; // @[AsyncQueue.scala:226:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue_3 :
input clock : Clock
input reset : Reset
output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<4>}
inst main of BranchKillableQueue_2
connect main.clock, clock
connect main.reset, reset
reg out_reg : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}, clock
regreset out_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock
connect main.io.enq, io.enq
connect main.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect main.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect main.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect main.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect main.io.brupdate.b2.taken, io.brupdate.b2.taken
connect main.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect main.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect main.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect main.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect main.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect main.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect main.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect main.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect main.io.brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect main.io.brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect main.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect main.io.brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect main.io.brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect main.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect main.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect main.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect main.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect main.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect main.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect main.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect main.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect main.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect main.io.brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect main.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect main.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect main.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect main.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect main.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect main.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect main.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect main.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect main.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect main.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect main.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect main.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect main.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect main.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect main.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect main.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect main.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect main.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect main.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect main.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect main.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect main.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect main.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect main.io.brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect main.io.brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect main.io.brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect main.io.brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect main.io.brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect main.io.brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect main.io.brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect main.io.brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect main.io.brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect main.io.brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect main.io.brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect main.io.brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect main.io.brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect main.io.brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect main.io.brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect main.io.brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect main.io.brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect main.io.brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect main.io.brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect main.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect main.io.brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect main.io.brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect main.io.brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect main.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect main.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect main.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect main.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect main.io.brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect main.io.brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect main.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect main.io.brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect main.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect main.io.brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect main.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect main.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect main.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect main.io.brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect main.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect main.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect main.io.brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect main.io.brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect main.io.brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect main.io.brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect main.io.brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect main.io.brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect main.io.brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect main.io.brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect main.io.brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect main.io.brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect main.io.brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect main.io.brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect main.io.brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect main.io.brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect main.io.brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect main.io.brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect main.io.brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect main.io.brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect main.io.brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect main.io.brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect main.io.brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect main.io.brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect main.io.brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect main.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect main.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect main.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect main.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect main.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect main.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect main.io.flush, io.flush
node _io_empty_T = eq(out_valid, UInt<1>(0h0))
node _io_empty_T_1 = and(main.io.empty, _io_empty_T)
connect io.empty, _io_empty_T_1
node _io_count_T = add(main.io.count, out_valid)
node _io_count_T_1 = tail(_io_count_T, 1)
connect io.count, _io_count_T_1
connect io.deq.valid, out_valid
connect io.deq.bits, out_reg
connect io.deq.bits.uop, out_uop
wire out_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect out_uop_out, out_uop
node _out_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _out_uop_out_br_mask_T_1 = and(out_uop.br_mask, _out_uop_out_br_mask_T)
connect out_uop_out.br_mask, _out_uop_out_br_mask_T_1
connect out_uop, out_uop_out
node _out_valid_T = and(io.brupdate.b1.mispredict_mask, out_uop.br_mask)
node _out_valid_T_1 = neq(_out_valid_T, UInt<1>(0h0))
node _out_valid_T_2 = or(_out_valid_T_1, UInt<1>(0h0))
node _out_valid_T_3 = eq(_out_valid_T_2, UInt<1>(0h0))
node _out_valid_T_4 = and(out_valid, _out_valid_T_3)
node _out_valid_T_5 = and(io.flush, out_uop.uses_ldq)
node _out_valid_T_6 = eq(_out_valid_T_5, UInt<1>(0h0))
node _out_valid_T_7 = and(_out_valid_T_4, _out_valid_T_6)
connect out_valid, _out_valid_T_7
connect main.io.deq.ready, UInt<1>(0h0)
node _T = and(io.deq.ready, io.deq.valid)
node _T_1 = eq(out_valid, UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
when _T_2 :
node _out_valid_T_8 = and(io.brupdate.b1.mispredict_mask, main.io.deq.bits.uop.br_mask)
node _out_valid_T_9 = neq(_out_valid_T_8, UInt<1>(0h0))
node _out_valid_T_10 = or(_out_valid_T_9, UInt<1>(0h0))
node _out_valid_T_11 = eq(_out_valid_T_10, UInt<1>(0h0))
node _out_valid_T_12 = and(main.io.deq.valid, _out_valid_T_11)
node _out_valid_T_13 = and(io.flush, main.io.deq.bits.uop.uses_ldq)
node _out_valid_T_14 = eq(_out_valid_T_13, UInt<1>(0h0))
node _out_valid_T_15 = and(_out_valid_T_12, _out_valid_T_14)
connect out_valid, _out_valid_T_15
connect out_reg, main.io.deq.bits
wire out_uop_out_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect out_uop_out_1, main.io.deq.bits.uop
node _out_uop_out_br_mask_T_2 = not(io.brupdate.b1.resolve_mask)
node _out_uop_out_br_mask_T_3 = and(main.io.deq.bits.uop.br_mask, _out_uop_out_br_mask_T_2)
connect out_uop_out_1.br_mask, _out_uop_out_br_mask_T_3
connect out_uop, out_uop_out_1
connect main.io.deq.ready, UInt<1>(0h1) | module BranchKillableQueue_3( // @[util.scala:458:7]
input clock, // @[util.scala:458:7]
input reset, // @[util.scala:458:7]
output io_enq_ready, // @[util.scala:463:14]
input io_enq_valid, // @[util.scala:463:14]
input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14]
input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14]
input io_enq_bits_uop_is_rvc, // @[util.scala:463:14]
input [39:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14]
input [15:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14]
input io_enq_bits_uop_is_sfb, // @[util.scala:463:14]
input io_enq_bits_uop_is_fence, // @[util.scala:463:14]
input io_enq_bits_uop_is_fencei, // @[util.scala:463:14]
input io_enq_bits_uop_is_sfence, // @[util.scala:463:14]
input io_enq_bits_uop_is_amo, // @[util.scala:463:14]
input io_enq_bits_uop_is_eret, // @[util.scala:463:14]
input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14]
input io_enq_bits_uop_is_rocc, // @[util.scala:463:14]
input io_enq_bits_uop_is_mov, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14]
input io_enq_bits_uop_edge_inst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14]
input io_enq_bits_uop_taken, // @[util.scala:463:14]
input io_enq_bits_uop_imm_rename, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14]
input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_pdst, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_prs1, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_prs2, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_prs3, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_ppred, // @[util.scala:463:14]
input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14]
input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14]
input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14]
input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14]
input io_enq_bits_uop_exception, // @[util.scala:463:14]
input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14]
input io_enq_bits_uop_mem_signed, // @[util.scala:463:14]
input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14]
input io_enq_bits_uop_uses_stq, // @[util.scala:463:14]
input io_enq_bits_uop_is_unique, // @[util.scala:463:14]
input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14]
input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14]
input io_enq_bits_uop_frs3_en, // @[util.scala:463:14]
input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14]
input io_enq_bits_uop_fp_val, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14]
input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14]
input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14]
input [39:0] io_enq_bits_addr, // @[util.scala:463:14]
input [63:0] io_enq_bits_data, // @[util.scala:463:14]
input io_enq_bits_is_hella, // @[util.scala:463:14]
input io_enq_bits_tag_match, // @[util.scala:463:14]
input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:463:14]
input [19:0] io_enq_bits_old_meta_tag, // @[util.scala:463:14]
input [7:0] io_enq_bits_way_en, // @[util.scala:463:14]
input [4:0] io_enq_bits_sdq_id, // @[util.scala:463:14]
input io_deq_ready, // @[util.scala:463:14]
output io_deq_valid, // @[util.scala:463:14]
output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14]
output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14]
output io_deq_bits_uop_is_rvc, // @[util.scala:463:14]
output [39:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14]
output [15:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14]
output io_deq_bits_uop_is_sfb, // @[util.scala:463:14]
output io_deq_bits_uop_is_fence, // @[util.scala:463:14]
output io_deq_bits_uop_is_fencei, // @[util.scala:463:14]
output io_deq_bits_uop_is_sfence, // @[util.scala:463:14]
output io_deq_bits_uop_is_amo, // @[util.scala:463:14]
output io_deq_bits_uop_is_eret, // @[util.scala:463:14]
output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14]
output io_deq_bits_uop_is_rocc, // @[util.scala:463:14]
output io_deq_bits_uop_is_mov, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14]
output io_deq_bits_uop_edge_inst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14]
output io_deq_bits_uop_taken, // @[util.scala:463:14]
output io_deq_bits_uop_imm_rename, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14]
output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_pdst, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_prs1, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_prs2, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_prs3, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_ppred, // @[util.scala:463:14]
output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14]
output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14]
output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14]
output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14]
output io_deq_bits_uop_exception, // @[util.scala:463:14]
output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14]
output io_deq_bits_uop_mem_signed, // @[util.scala:463:14]
output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14]
output io_deq_bits_uop_uses_stq, // @[util.scala:463:14]
output io_deq_bits_uop_is_unique, // @[util.scala:463:14]
output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14]
output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14]
output io_deq_bits_uop_frs3_en, // @[util.scala:463:14]
output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14]
output io_deq_bits_uop_fp_val, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14]
output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14]
output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14]
output [39:0] io_deq_bits_addr, // @[util.scala:463:14]
output [63:0] io_deq_bits_data, // @[util.scala:463:14]
output io_deq_bits_is_hella, // @[util.scala:463:14]
output io_deq_bits_tag_match, // @[util.scala:463:14]
output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:463:14]
output [19:0] io_deq_bits_old_meta_tag, // @[util.scala:463:14]
output [7:0] io_deq_bits_way_en, // @[util.scala:463:14]
output [4:0] io_deq_bits_sdq_id, // @[util.scala:463:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[util.scala:463:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[util.scala:463:14]
input [31:0] io_brupdate_b2_uop_inst, // @[util.scala:463:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_rvc, // @[util.scala:463:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_0, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_1, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_2, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_3, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_0, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_1, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_2, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_3, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_4, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_5, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_6, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_7, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_8, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_9, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_issued, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[util.scala:463:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[util.scala:463:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[util.scala:463:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_sfb, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_fence, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_fencei, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_sfence, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_amo, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_eret, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_rocc, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_mov, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[util.scala:463:14]
input io_brupdate_b2_uop_edge_inst, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[util.scala:463:14]
input io_brupdate_b2_uop_taken, // @[util.scala:463:14]
input io_brupdate_b2_uop_imm_rename, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[util.scala:463:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[util.scala:463:14]
input io_brupdate_b2_uop_prs1_busy, // @[util.scala:463:14]
input io_brupdate_b2_uop_prs2_busy, // @[util.scala:463:14]
input io_brupdate_b2_uop_prs3_busy, // @[util.scala:463:14]
input io_brupdate_b2_uop_ppred_busy, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[util.scala:463:14]
input io_brupdate_b2_uop_exception, // @[util.scala:463:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[util.scala:463:14]
input io_brupdate_b2_uop_mem_signed, // @[util.scala:463:14]
input io_brupdate_b2_uop_uses_ldq, // @[util.scala:463:14]
input io_brupdate_b2_uop_uses_stq, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_unique, // @[util.scala:463:14]
input io_brupdate_b2_uop_flush_on_commit, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[util.scala:463:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[util.scala:463:14]
input io_brupdate_b2_uop_frs3_en, // @[util.scala:463:14]
input io_brupdate_b2_uop_fcn_dw, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_val, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[util.scala:463:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_bp_debug_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[util.scala:463:14]
input io_brupdate_b2_mispredict, // @[util.scala:463:14]
input io_brupdate_b2_taken, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_cfi_type, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_pc_sel, // @[util.scala:463:14]
input [39:0] io_brupdate_b2_jalr_target, // @[util.scala:463:14]
input [20:0] io_brupdate_b2_target_offset, // @[util.scala:463:14]
input io_flush, // @[util.scala:463:14]
output io_empty // @[util.scala:463:14]
);
wire _main_io_deq_valid; // @[util.scala:476:22]
wire [31:0] _main_io_deq_bits_uop_inst; // @[util.scala:476:22]
wire [31:0] _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22]
wire [39:0] _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22]
wire [15:0] _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_br_type; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_taken; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_pimm; // @[util.scala:476:22]
wire [19:0] _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22]
wire [6:0] _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22]
wire [6:0] _main_io_deq_bits_uop_pdst; // @[util.scala:476:22]
wire [6:0] _main_io_deq_bits_uop_prs1; // @[util.scala:476:22]
wire [6:0] _main_io_deq_bits_uop_prs2; // @[util.scala:476:22]
wire [6:0] _main_io_deq_bits_uop_prs3; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_ppred; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22]
wire [6:0] _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_exception; // @[util.scala:476:22]
wire [63:0] _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_ldst; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22]
wire [39:0] _main_io_deq_bits_addr; // @[util.scala:476:22]
wire [63:0] _main_io_deq_bits_data; // @[util.scala:476:22]
wire _main_io_deq_bits_is_hella; // @[util.scala:476:22]
wire _main_io_deq_bits_tag_match; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22]
wire [19:0] _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22]
wire [7:0] _main_io_deq_bits_way_en; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_sdq_id; // @[util.scala:476:22]
wire _main_io_empty; // @[util.scala:476:22]
wire [3:0] _main_io_count; // @[util.scala:476:22]
wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7]
wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7]
wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7]
wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7]
wire [39:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7]
wire [15:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7]
wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7]
wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7]
wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7]
wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7]
wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7]
wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7]
wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7]
wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7]
wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7]
wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7]
wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7]
wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7]
wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7]
wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7]
wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7]
wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7]
wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7]
wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7]
wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7]
wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7]
wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7]
wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7]
wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7]
wire [39:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:458:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7]
wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:458:7]
wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:458:7]
wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:458:7]
wire [19:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:458:7]
wire [7:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:458:7]
wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:458:7]
wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[util.scala:458:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[util.scala:458:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[util.scala:458:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[util.scala:458:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[util.scala:458:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[util.scala:458:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[util.scala:458:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[util.scala:458:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[util.scala:458:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[util.scala:458:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[util.scala:458:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[util.scala:458:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[util.scala:458:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[util.scala:458:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[util.scala:458:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[util.scala:458:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[util.scala:458:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[util.scala:458:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[util.scala:458:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[util.scala:458:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[util.scala:458:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[util.scala:458:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[util.scala:458:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[util.scala:458:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[util.scala:458:7]
wire io_flush_0 = io_flush; // @[util.scala:458:7]
wire _io_empty_T_1; // @[util.scala:484:31]
wire [3:0] _io_count_T_1; // @[util.scala:485:31]
wire io_enq_ready_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7]
wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7]
wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7]
wire [39:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7]
wire [15:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7]
wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7]
wire io_deq_bits_uop_taken_0; // @[util.scala:458:7]
wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7]
wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_exception_0; // @[util.scala:458:7]
wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7]
wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7]
wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7]
wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7]
wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7]
wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7]
wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7]
wire [19:0] io_deq_bits_old_meta_tag_0; // @[util.scala:458:7]
wire [39:0] io_deq_bits_addr_0; // @[util.scala:458:7]
wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7]
wire io_deq_bits_is_hella_0; // @[util.scala:458:7]
wire io_deq_bits_tag_match_0; // @[util.scala:458:7]
wire [7:0] io_deq_bits_way_en_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:458:7]
wire io_deq_valid_0; // @[util.scala:458:7]
wire io_empty_0; // @[util.scala:458:7]
wire [3:0] io_count; // @[util.scala:458:7]
reg [31:0] out_reg_uop_inst; // @[util.scala:477:22]
reg [31:0] out_reg_uop_debug_inst; // @[util.scala:477:22]
reg out_reg_uop_is_rvc; // @[util.scala:477:22]
reg [39:0] out_reg_uop_debug_pc; // @[util.scala:477:22]
reg out_reg_uop_iq_type_0; // @[util.scala:477:22]
reg out_reg_uop_iq_type_1; // @[util.scala:477:22]
reg out_reg_uop_iq_type_2; // @[util.scala:477:22]
reg out_reg_uop_iq_type_3; // @[util.scala:477:22]
reg out_reg_uop_fu_code_0; // @[util.scala:477:22]
reg out_reg_uop_fu_code_1; // @[util.scala:477:22]
reg out_reg_uop_fu_code_2; // @[util.scala:477:22]
reg out_reg_uop_fu_code_3; // @[util.scala:477:22]
reg out_reg_uop_fu_code_4; // @[util.scala:477:22]
reg out_reg_uop_fu_code_5; // @[util.scala:477:22]
reg out_reg_uop_fu_code_6; // @[util.scala:477:22]
reg out_reg_uop_fu_code_7; // @[util.scala:477:22]
reg out_reg_uop_fu_code_8; // @[util.scala:477:22]
reg out_reg_uop_fu_code_9; // @[util.scala:477:22]
reg out_reg_uop_iw_issued; // @[util.scala:477:22]
reg out_reg_uop_iw_issued_partial_agen; // @[util.scala:477:22]
reg out_reg_uop_iw_issued_partial_dgen; // @[util.scala:477:22]
reg [2:0] out_reg_uop_iw_p1_speculative_child; // @[util.scala:477:22]
reg [2:0] out_reg_uop_iw_p2_speculative_child; // @[util.scala:477:22]
reg out_reg_uop_iw_p1_bypass_hint; // @[util.scala:477:22]
reg out_reg_uop_iw_p2_bypass_hint; // @[util.scala:477:22]
reg out_reg_uop_iw_p3_bypass_hint; // @[util.scala:477:22]
reg [2:0] out_reg_uop_dis_col_sel; // @[util.scala:477:22]
reg [15:0] out_reg_uop_br_mask; // @[util.scala:477:22]
reg [3:0] out_reg_uop_br_tag; // @[util.scala:477:22]
reg [3:0] out_reg_uop_br_type; // @[util.scala:477:22]
reg out_reg_uop_is_sfb; // @[util.scala:477:22]
reg out_reg_uop_is_fence; // @[util.scala:477:22]
reg out_reg_uop_is_fencei; // @[util.scala:477:22]
reg out_reg_uop_is_sfence; // @[util.scala:477:22]
reg out_reg_uop_is_amo; // @[util.scala:477:22]
reg out_reg_uop_is_eret; // @[util.scala:477:22]
reg out_reg_uop_is_sys_pc2epc; // @[util.scala:477:22]
reg out_reg_uop_is_rocc; // @[util.scala:477:22]
reg out_reg_uop_is_mov; // @[util.scala:477:22]
reg [4:0] out_reg_uop_ftq_idx; // @[util.scala:477:22]
reg out_reg_uop_edge_inst; // @[util.scala:477:22]
reg [5:0] out_reg_uop_pc_lob; // @[util.scala:477:22]
reg out_reg_uop_taken; // @[util.scala:477:22]
reg out_reg_uop_imm_rename; // @[util.scala:477:22]
reg [2:0] out_reg_uop_imm_sel; // @[util.scala:477:22]
reg [4:0] out_reg_uop_pimm; // @[util.scala:477:22]
reg [19:0] out_reg_uop_imm_packed; // @[util.scala:477:22]
reg [1:0] out_reg_uop_op1_sel; // @[util.scala:477:22]
reg [2:0] out_reg_uop_op2_sel; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ldst; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_wen; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ren1; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ren2; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ren3; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_swap12; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_swap23; // @[util.scala:477:22]
reg [1:0] out_reg_uop_fp_ctrl_typeTagIn; // @[util.scala:477:22]
reg [1:0] out_reg_uop_fp_ctrl_typeTagOut; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_fromint; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_toint; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_fastpipe; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_fma; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_div; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_sqrt; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_wflags; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_vec; // @[util.scala:477:22]
reg [6:0] out_reg_uop_rob_idx; // @[util.scala:477:22]
reg [4:0] out_reg_uop_ldq_idx; // @[util.scala:477:22]
reg [4:0] out_reg_uop_stq_idx; // @[util.scala:477:22]
reg [1:0] out_reg_uop_rxq_idx; // @[util.scala:477:22]
reg [6:0] out_reg_uop_pdst; // @[util.scala:477:22]
reg [6:0] out_reg_uop_prs1; // @[util.scala:477:22]
reg [6:0] out_reg_uop_prs2; // @[util.scala:477:22]
reg [6:0] out_reg_uop_prs3; // @[util.scala:477:22]
reg [4:0] out_reg_uop_ppred; // @[util.scala:477:22]
reg out_reg_uop_prs1_busy; // @[util.scala:477:22]
reg out_reg_uop_prs2_busy; // @[util.scala:477:22]
reg out_reg_uop_prs3_busy; // @[util.scala:477:22]
reg out_reg_uop_ppred_busy; // @[util.scala:477:22]
reg [6:0] out_reg_uop_stale_pdst; // @[util.scala:477:22]
reg out_reg_uop_exception; // @[util.scala:477:22]
reg [63:0] out_reg_uop_exc_cause; // @[util.scala:477:22]
reg [4:0] out_reg_uop_mem_cmd; // @[util.scala:477:22]
reg [1:0] out_reg_uop_mem_size; // @[util.scala:477:22]
reg out_reg_uop_mem_signed; // @[util.scala:477:22]
reg out_reg_uop_uses_ldq; // @[util.scala:477:22]
reg out_reg_uop_uses_stq; // @[util.scala:477:22]
reg out_reg_uop_is_unique; // @[util.scala:477:22]
reg out_reg_uop_flush_on_commit; // @[util.scala:477:22]
reg [2:0] out_reg_uop_csr_cmd; // @[util.scala:477:22]
reg out_reg_uop_ldst_is_rs1; // @[util.scala:477:22]
reg [5:0] out_reg_uop_ldst; // @[util.scala:477:22]
reg [5:0] out_reg_uop_lrs1; // @[util.scala:477:22]
reg [5:0] out_reg_uop_lrs2; // @[util.scala:477:22]
reg [5:0] out_reg_uop_lrs3; // @[util.scala:477:22]
reg [1:0] out_reg_uop_dst_rtype; // @[util.scala:477:22]
reg [1:0] out_reg_uop_lrs1_rtype; // @[util.scala:477:22]
reg [1:0] out_reg_uop_lrs2_rtype; // @[util.scala:477:22]
reg out_reg_uop_frs3_en; // @[util.scala:477:22]
reg out_reg_uop_fcn_dw; // @[util.scala:477:22]
reg [4:0] out_reg_uop_fcn_op; // @[util.scala:477:22]
reg out_reg_uop_fp_val; // @[util.scala:477:22]
reg [2:0] out_reg_uop_fp_rm; // @[util.scala:477:22]
reg [1:0] out_reg_uop_fp_typ; // @[util.scala:477:22]
reg out_reg_uop_xcpt_pf_if; // @[util.scala:477:22]
reg out_reg_uop_xcpt_ae_if; // @[util.scala:477:22]
reg out_reg_uop_xcpt_ma_if; // @[util.scala:477:22]
reg out_reg_uop_bp_debug_if; // @[util.scala:477:22]
reg out_reg_uop_bp_xcpt_if; // @[util.scala:477:22]
reg [2:0] out_reg_uop_debug_fsrc; // @[util.scala:477:22]
reg [2:0] out_reg_uop_debug_tsrc; // @[util.scala:477:22]
reg [39:0] out_reg_addr; // @[util.scala:477:22]
assign io_deq_bits_addr_0 = out_reg_addr; // @[util.scala:458:7, :477:22]
reg [63:0] out_reg_data; // @[util.scala:477:22]
assign io_deq_bits_data_0 = out_reg_data; // @[util.scala:458:7, :477:22]
reg out_reg_is_hella; // @[util.scala:477:22]
assign io_deq_bits_is_hella_0 = out_reg_is_hella; // @[util.scala:458:7, :477:22]
reg out_reg_tag_match; // @[util.scala:477:22]
assign io_deq_bits_tag_match_0 = out_reg_tag_match; // @[util.scala:458:7, :477:22]
reg [1:0] out_reg_old_meta_coh_state; // @[util.scala:477:22]
assign io_deq_bits_old_meta_coh_state_0 = out_reg_old_meta_coh_state; // @[util.scala:458:7, :477:22]
reg [19:0] out_reg_old_meta_tag; // @[util.scala:477:22]
assign io_deq_bits_old_meta_tag_0 = out_reg_old_meta_tag; // @[util.scala:458:7, :477:22]
reg [7:0] out_reg_way_en; // @[util.scala:477:22]
assign io_deq_bits_way_en_0 = out_reg_way_en; // @[util.scala:458:7, :477:22]
reg [4:0] out_reg_sdq_id; // @[util.scala:477:22]
assign io_deq_bits_sdq_id_0 = out_reg_sdq_id; // @[util.scala:458:7, :477:22]
reg out_valid; // @[util.scala:478:28]
assign io_deq_valid_0 = out_valid; // @[util.scala:458:7, :478:28]
reg [31:0] out_uop_inst; // @[util.scala:479:22]
assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :479:22]
wire [31:0] out_uop_out_inst = out_uop_inst; // @[util.scala:104:23, :479:22]
reg [31:0] out_uop_debug_inst; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :479:22]
wire [31:0] out_uop_out_debug_inst = out_uop_debug_inst; // @[util.scala:104:23, :479:22]
reg out_uop_is_rvc; // @[util.scala:479:22]
assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_rvc = out_uop_is_rvc; // @[util.scala:104:23, :479:22]
reg [39:0] out_uop_debug_pc; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :479:22]
wire [39:0] out_uop_out_debug_pc = out_uop_debug_pc; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_0; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_0 = out_uop_iq_type_0; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_1; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_1 = out_uop_iq_type_1; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_2; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_2 = out_uop_iq_type_2; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_3; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_3 = out_uop_iq_type_3; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_0; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_0 = out_uop_fu_code_0; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_1; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_1 = out_uop_fu_code_1; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_2; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_2 = out_uop_fu_code_2; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_3; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_3 = out_uop_fu_code_3; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_4; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_4 = out_uop_fu_code_4; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_5; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_5 = out_uop_fu_code_5; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_6; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_6 = out_uop_fu_code_6; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_7; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_7 = out_uop_fu_code_7; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_8; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_8 = out_uop_fu_code_8; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_9; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_9 = out_uop_fu_code_9; // @[util.scala:104:23, :479:22]
reg out_uop_iw_issued; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_issued = out_uop_iw_issued; // @[util.scala:104:23, :479:22]
reg out_uop_iw_issued_partial_agen; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_issued_partial_agen = out_uop_iw_issued_partial_agen; // @[util.scala:104:23, :479:22]
reg out_uop_iw_issued_partial_dgen; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_issued_partial_dgen = out_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_iw_p1_speculative_child; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_iw_p1_speculative_child = out_uop_iw_p1_speculative_child; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_iw_p2_speculative_child; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_iw_p2_speculative_child = out_uop_iw_p2_speculative_child; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p1_bypass_hint; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p1_bypass_hint = out_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p2_bypass_hint; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p2_bypass_hint = out_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p3_bypass_hint; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p3_bypass_hint = out_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_dis_col_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_dis_col_sel = out_uop_dis_col_sel; // @[util.scala:104:23, :479:22]
reg [15:0] out_uop_br_mask; // @[util.scala:479:22]
assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :479:22]
reg [3:0] out_uop_br_tag; // @[util.scala:479:22]
assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_br_tag = out_uop_br_tag; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_br_type; // @[util.scala:479:22]
assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_br_type = out_uop_br_type; // @[util.scala:104:23, :479:22]
reg out_uop_is_sfb; // @[util.scala:479:22]
assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_sfb = out_uop_is_sfb; // @[util.scala:104:23, :479:22]
reg out_uop_is_fence; // @[util.scala:479:22]
assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_fence = out_uop_is_fence; // @[util.scala:104:23, :479:22]
reg out_uop_is_fencei; // @[util.scala:479:22]
assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_fencei = out_uop_is_fencei; // @[util.scala:104:23, :479:22]
reg out_uop_is_sfence; // @[util.scala:479:22]
assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_sfence = out_uop_is_sfence; // @[util.scala:104:23, :479:22]
reg out_uop_is_amo; // @[util.scala:479:22]
assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_amo = out_uop_is_amo; // @[util.scala:104:23, :479:22]
reg out_uop_is_eret; // @[util.scala:479:22]
assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_eret = out_uop_is_eret; // @[util.scala:104:23, :479:22]
reg out_uop_is_sys_pc2epc; // @[util.scala:479:22]
assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_sys_pc2epc = out_uop_is_sys_pc2epc; // @[util.scala:104:23, :479:22]
reg out_uop_is_rocc; // @[util.scala:479:22]
assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_rocc = out_uop_is_rocc; // @[util.scala:104:23, :479:22]
reg out_uop_is_mov; // @[util.scala:479:22]
assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_mov = out_uop_is_mov; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_ftq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_ftq_idx = out_uop_ftq_idx; // @[util.scala:104:23, :479:22]
reg out_uop_edge_inst; // @[util.scala:479:22]
assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :479:22]
wire out_uop_out_edge_inst = out_uop_edge_inst; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_pc_lob; // @[util.scala:479:22]
assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_pc_lob = out_uop_pc_lob; // @[util.scala:104:23, :479:22]
reg out_uop_taken; // @[util.scala:479:22]
assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :479:22]
wire out_uop_out_taken = out_uop_taken; // @[util.scala:104:23, :479:22]
reg out_uop_imm_rename; // @[util.scala:479:22]
assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :479:22]
wire out_uop_out_imm_rename = out_uop_imm_rename; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_imm_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_imm_sel = out_uop_imm_sel; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_pimm; // @[util.scala:479:22]
assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_pimm = out_uop_pimm; // @[util.scala:104:23, :479:22]
reg [19:0] out_uop_imm_packed; // @[util.scala:479:22]
assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :479:22]
wire [19:0] out_uop_out_imm_packed = out_uop_imm_packed; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_op1_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_op1_sel = out_uop_op1_sel; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_op2_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_op2_sel = out_uop_op2_sel; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ldst; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ldst = out_uop_fp_ctrl_ldst; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_wen; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_wen = out_uop_fp_ctrl_wen; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ren1; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ren1 = out_uop_fp_ctrl_ren1; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ren2; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ren2 = out_uop_fp_ctrl_ren2; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ren3; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ren3 = out_uop_fp_ctrl_ren3; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_swap12; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_swap12 = out_uop_fp_ctrl_swap12; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_swap23; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_swap23 = out_uop_fp_ctrl_swap23; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_fp_ctrl_typeTagIn = out_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_fp_ctrl_typeTagOut = out_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_fromint; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_fromint = out_uop_fp_ctrl_fromint; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_toint; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_toint = out_uop_fp_ctrl_toint; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_fastpipe; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_fastpipe = out_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_fma; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_fma = out_uop_fp_ctrl_fma; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_div; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_div = out_uop_fp_ctrl_div; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_sqrt; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_sqrt = out_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_wflags; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_wflags = out_uop_fp_ctrl_wflags; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_vec; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_vec = out_uop_fp_ctrl_vec; // @[util.scala:104:23, :479:22]
reg [6:0] out_uop_rob_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :479:22]
wire [6:0] out_uop_out_rob_idx = out_uop_rob_idx; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_ldq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_ldq_idx = out_uop_ldq_idx; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_stq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_stq_idx = out_uop_stq_idx; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_rxq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_rxq_idx = out_uop_rxq_idx; // @[util.scala:104:23, :479:22]
reg [6:0] out_uop_pdst; // @[util.scala:479:22]
assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :479:22]
wire [6:0] out_uop_out_pdst = out_uop_pdst; // @[util.scala:104:23, :479:22]
reg [6:0] out_uop_prs1; // @[util.scala:479:22]
assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :479:22]
wire [6:0] out_uop_out_prs1 = out_uop_prs1; // @[util.scala:104:23, :479:22]
reg [6:0] out_uop_prs2; // @[util.scala:479:22]
assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :479:22]
wire [6:0] out_uop_out_prs2 = out_uop_prs2; // @[util.scala:104:23, :479:22]
reg [6:0] out_uop_prs3; // @[util.scala:479:22]
assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :479:22]
wire [6:0] out_uop_out_prs3 = out_uop_prs3; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_ppred; // @[util.scala:479:22]
assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_ppred = out_uop_ppred; // @[util.scala:104:23, :479:22]
reg out_uop_prs1_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_prs1_busy = out_uop_prs1_busy; // @[util.scala:104:23, :479:22]
reg out_uop_prs2_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_prs2_busy = out_uop_prs2_busy; // @[util.scala:104:23, :479:22]
reg out_uop_prs3_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_prs3_busy = out_uop_prs3_busy; // @[util.scala:104:23, :479:22]
reg out_uop_ppred_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_ppred_busy = out_uop_ppred_busy; // @[util.scala:104:23, :479:22]
reg [6:0] out_uop_stale_pdst; // @[util.scala:479:22]
assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :479:22]
wire [6:0] out_uop_out_stale_pdst = out_uop_stale_pdst; // @[util.scala:104:23, :479:22]
reg out_uop_exception; // @[util.scala:479:22]
assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :479:22]
wire out_uop_out_exception = out_uop_exception; // @[util.scala:104:23, :479:22]
reg [63:0] out_uop_exc_cause; // @[util.scala:479:22]
assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :479:22]
wire [63:0] out_uop_out_exc_cause = out_uop_exc_cause; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_mem_cmd; // @[util.scala:479:22]
assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_mem_cmd = out_uop_mem_cmd; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_mem_size; // @[util.scala:479:22]
assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_mem_size = out_uop_mem_size; // @[util.scala:104:23, :479:22]
reg out_uop_mem_signed; // @[util.scala:479:22]
assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :479:22]
wire out_uop_out_mem_signed = out_uop_mem_signed; // @[util.scala:104:23, :479:22]
reg out_uop_uses_ldq; // @[util.scala:479:22]
assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :479:22]
wire out_uop_out_uses_ldq = out_uop_uses_ldq; // @[util.scala:104:23, :479:22]
reg out_uop_uses_stq; // @[util.scala:479:22]
assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :479:22]
wire out_uop_out_uses_stq = out_uop_uses_stq; // @[util.scala:104:23, :479:22]
reg out_uop_is_unique; // @[util.scala:479:22]
assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_unique = out_uop_is_unique; // @[util.scala:104:23, :479:22]
reg out_uop_flush_on_commit; // @[util.scala:479:22]
assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :479:22]
wire out_uop_out_flush_on_commit = out_uop_flush_on_commit; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_csr_cmd; // @[util.scala:479:22]
assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_csr_cmd = out_uop_csr_cmd; // @[util.scala:104:23, :479:22]
reg out_uop_ldst_is_rs1; // @[util.scala:479:22]
assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :479:22]
wire out_uop_out_ldst_is_rs1 = out_uop_ldst_is_rs1; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_ldst; // @[util.scala:479:22]
assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_ldst = out_uop_ldst; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_lrs1; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_lrs1 = out_uop_lrs1; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_lrs2; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_lrs2 = out_uop_lrs2; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_lrs3; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_lrs3 = out_uop_lrs3; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_dst_rtype; // @[util.scala:479:22]
assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_dst_rtype = out_uop_dst_rtype; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_lrs1_rtype; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_lrs1_rtype = out_uop_lrs1_rtype; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_lrs2_rtype; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_lrs2_rtype = out_uop_lrs2_rtype; // @[util.scala:104:23, :479:22]
reg out_uop_frs3_en; // @[util.scala:479:22]
assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :479:22]
wire out_uop_out_frs3_en = out_uop_frs3_en; // @[util.scala:104:23, :479:22]
reg out_uop_fcn_dw; // @[util.scala:479:22]
assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :479:22]
wire out_uop_out_fcn_dw = out_uop_fcn_dw; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_fcn_op; // @[util.scala:479:22]
assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_fcn_op = out_uop_fcn_op; // @[util.scala:104:23, :479:22]
reg out_uop_fp_val; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_val = out_uop_fp_val; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_fp_rm; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_fp_rm = out_uop_fp_rm; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_fp_typ; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_fp_typ = out_uop_fp_typ; // @[util.scala:104:23, :479:22]
reg out_uop_xcpt_pf_if; // @[util.scala:479:22]
assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_xcpt_pf_if = out_uop_xcpt_pf_if; // @[util.scala:104:23, :479:22]
reg out_uop_xcpt_ae_if; // @[util.scala:479:22]
assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_xcpt_ae_if = out_uop_xcpt_ae_if; // @[util.scala:104:23, :479:22]
reg out_uop_xcpt_ma_if; // @[util.scala:479:22]
assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_xcpt_ma_if = out_uop_xcpt_ma_if; // @[util.scala:104:23, :479:22]
reg out_uop_bp_debug_if; // @[util.scala:479:22]
assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_bp_debug_if = out_uop_bp_debug_if; // @[util.scala:104:23, :479:22]
reg out_uop_bp_xcpt_if; // @[util.scala:479:22]
assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_bp_xcpt_if = out_uop_bp_xcpt_if; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_debug_fsrc; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_debug_fsrc = out_uop_debug_fsrc; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_debug_tsrc; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_debug_tsrc = out_uop_debug_tsrc; // @[util.scala:104:23, :479:22]
wire _io_empty_T = ~out_valid; // @[util.scala:478:28, :484:34]
assign _io_empty_T_1 = _main_io_empty & _io_empty_T; // @[util.scala:476:22, :484:{31,34}]
assign io_empty_0 = _io_empty_T_1; // @[util.scala:458:7, :484:31]
wire [4:0] _io_count_T = {1'h0, _main_io_count} + {4'h0, out_valid}; // @[util.scala:476:22, :478:28, :485:31]
assign _io_count_T_1 = _io_count_T[3:0]; // @[util.scala:485:31]
assign io_count = _io_count_T_1; // @[util.scala:458:7, :485:31]
wire [15:0] _out_uop_out_br_mask_T_1; // @[util.scala:93:25]
wire [15:0] out_uop_out_br_mask; // @[util.scala:104:23]
wire [15:0] _out_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :458:7]
assign _out_uop_out_br_mask_T_1 = out_uop_br_mask & _out_uop_out_br_mask_T; // @[util.scala:93:{25,27}, :479:22]
assign out_uop_out_br_mask = _out_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
wire [15:0] _out_valid_T = io_brupdate_b1_mispredict_mask_0 & out_uop_br_mask; // @[util.scala:126:51, :458:7, :479:22]
wire _out_valid_T_1 = |_out_valid_T; // @[util.scala:126:{51,59}]
wire _out_valid_T_2 = _out_valid_T_1; // @[util.scala:61:61, :126:59]
wire _out_valid_T_3 = ~_out_valid_T_2; // @[util.scala:61:61, :492:31]
wire _out_valid_T_4 = out_valid & _out_valid_T_3; // @[util.scala:478:28, :492:{28,31}]
wire _out_valid_T_5 = io_flush_0 & out_uop_uses_ldq; // @[util.scala:458:7, :479:22, :492:94]
wire _out_valid_T_6 = ~_out_valid_T_5; // @[util.scala:492:{83,94}]
wire _out_valid_T_7 = _out_valid_T_4 & _out_valid_T_6; // @[util.scala:492:{28,80,83}]
wire main_io_deq_ready = io_deq_ready_0 & io_deq_valid_0 | ~out_valid; // @[Decoupled.scala:51:35]
wire [15:0] _out_valid_T_8 = io_brupdate_b1_mispredict_mask_0 & _main_io_deq_bits_uop_br_mask; // @[util.scala:126:51, :458:7, :476:22]
wire _out_valid_T_9 = |_out_valid_T_8; // @[util.scala:126:{51,59}]
wire _out_valid_T_10 = _out_valid_T_9; // @[util.scala:61:61, :126:59]
wire _out_valid_T_11 = ~_out_valid_T_10; // @[util.scala:61:61, :496:41]
wire _out_valid_T_12 = _main_io_deq_valid & _out_valid_T_11; // @[util.scala:476:22, :496:{38,41}]
wire _out_valid_T_13 = io_flush_0 & _main_io_deq_bits_uop_uses_ldq; // @[util.scala:458:7, :476:22, :496:117]
wire _out_valid_T_14 = ~_out_valid_T_13; // @[util.scala:496:{106,117}]
wire _out_valid_T_15 = _out_valid_T_12 & _out_valid_T_14; // @[util.scala:496:{38,103,106}]
wire [15:0] _out_uop_out_br_mask_T_3; // @[util.scala:93:25]
wire out_uop_out_1_iq_type_0; // @[util.scala:104:23]
wire out_uop_out_1_iq_type_1; // @[util.scala:104:23]
wire out_uop_out_1_iq_type_2; // @[util.scala:104:23]
wire out_uop_out_1_iq_type_3; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_0; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_1; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_2; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_3; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_4; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_5; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_6; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_7; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_8; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_9; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ldst; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_wen; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ren1; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ren2; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ren3; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_swap12; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_swap23; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_fp_ctrl_typeTagIn; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_fp_ctrl_typeTagOut; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_fromint; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_toint; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_fastpipe; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_fma; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_div; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_sqrt; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_wflags; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_vec; // @[util.scala:104:23]
wire [31:0] out_uop_out_1_inst; // @[util.scala:104:23]
wire [31:0] out_uop_out_1_debug_inst; // @[util.scala:104:23]
wire out_uop_out_1_is_rvc; // @[util.scala:104:23]
wire [39:0] out_uop_out_1_debug_pc; // @[util.scala:104:23]
wire out_uop_out_1_iw_issued; // @[util.scala:104:23]
wire out_uop_out_1_iw_issued_partial_agen; // @[util.scala:104:23]
wire out_uop_out_1_iw_issued_partial_dgen; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_iw_p1_speculative_child; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_iw_p2_speculative_child; // @[util.scala:104:23]
wire out_uop_out_1_iw_p1_bypass_hint; // @[util.scala:104:23]
wire out_uop_out_1_iw_p2_bypass_hint; // @[util.scala:104:23]
wire out_uop_out_1_iw_p3_bypass_hint; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_dis_col_sel; // @[util.scala:104:23]
wire [15:0] out_uop_out_1_br_mask; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_br_tag; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_br_type; // @[util.scala:104:23]
wire out_uop_out_1_is_sfb; // @[util.scala:104:23]
wire out_uop_out_1_is_fence; // @[util.scala:104:23]
wire out_uop_out_1_is_fencei; // @[util.scala:104:23]
wire out_uop_out_1_is_sfence; // @[util.scala:104:23]
wire out_uop_out_1_is_amo; // @[util.scala:104:23]
wire out_uop_out_1_is_eret; // @[util.scala:104:23]
wire out_uop_out_1_is_sys_pc2epc; // @[util.scala:104:23]
wire out_uop_out_1_is_rocc; // @[util.scala:104:23]
wire out_uop_out_1_is_mov; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_ftq_idx; // @[util.scala:104:23]
wire out_uop_out_1_edge_inst; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_pc_lob; // @[util.scala:104:23]
wire out_uop_out_1_taken; // @[util.scala:104:23]
wire out_uop_out_1_imm_rename; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_imm_sel; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_pimm; // @[util.scala:104:23]
wire [19:0] out_uop_out_1_imm_packed; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_op1_sel; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_op2_sel; // @[util.scala:104:23]
wire [6:0] out_uop_out_1_rob_idx; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_ldq_idx; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_stq_idx; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_rxq_idx; // @[util.scala:104:23]
wire [6:0] out_uop_out_1_pdst; // @[util.scala:104:23]
wire [6:0] out_uop_out_1_prs1; // @[util.scala:104:23]
wire [6:0] out_uop_out_1_prs2; // @[util.scala:104:23]
wire [6:0] out_uop_out_1_prs3; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_ppred; // @[util.scala:104:23]
wire out_uop_out_1_prs1_busy; // @[util.scala:104:23]
wire out_uop_out_1_prs2_busy; // @[util.scala:104:23]
wire out_uop_out_1_prs3_busy; // @[util.scala:104:23]
wire out_uop_out_1_ppred_busy; // @[util.scala:104:23]
wire [6:0] out_uop_out_1_stale_pdst; // @[util.scala:104:23]
wire out_uop_out_1_exception; // @[util.scala:104:23]
wire [63:0] out_uop_out_1_exc_cause; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_mem_cmd; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_mem_size; // @[util.scala:104:23]
wire out_uop_out_1_mem_signed; // @[util.scala:104:23]
wire out_uop_out_1_uses_ldq; // @[util.scala:104:23]
wire out_uop_out_1_uses_stq; // @[util.scala:104:23]
wire out_uop_out_1_is_unique; // @[util.scala:104:23]
wire out_uop_out_1_flush_on_commit; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_csr_cmd; // @[util.scala:104:23]
wire out_uop_out_1_ldst_is_rs1; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_ldst; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_lrs1; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_lrs2; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_lrs3; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_dst_rtype; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_lrs1_rtype; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_lrs2_rtype; // @[util.scala:104:23]
wire out_uop_out_1_frs3_en; // @[util.scala:104:23]
wire out_uop_out_1_fcn_dw; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_fcn_op; // @[util.scala:104:23]
wire out_uop_out_1_fp_val; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_fp_rm; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_fp_typ; // @[util.scala:104:23]
wire out_uop_out_1_xcpt_pf_if; // @[util.scala:104:23]
wire out_uop_out_1_xcpt_ae_if; // @[util.scala:104:23]
wire out_uop_out_1_xcpt_ma_if; // @[util.scala:104:23]
wire out_uop_out_1_bp_debug_if; // @[util.scala:104:23]
wire out_uop_out_1_bp_xcpt_if; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_debug_fsrc; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_debug_tsrc; // @[util.scala:104:23]
wire [15:0] _out_uop_out_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :458:7]
assign _out_uop_out_br_mask_T_3 = _main_io_deq_bits_uop_br_mask & _out_uop_out_br_mask_T_2; // @[util.scala:93:{25,27}, :476:22]
assign out_uop_out_1_br_mask = _out_uop_out_br_mask_T_3; // @[util.scala:93:25, :104:23]
always @(posedge clock) begin // @[util.scala:458:7]
if (main_io_deq_ready) begin // @[util.scala:495:23]
out_reg_uop_inst <= _main_io_deq_bits_uop_inst; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_inst <= _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22, :477:22]
out_reg_uop_is_rvc <= _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_pc <= _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_0 <= _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_1 <= _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_2 <= _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_3 <= _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_0 <= _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_1 <= _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_2 <= _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_3 <= _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_4 <= _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_5 <= _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_6 <= _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_7 <= _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_8 <= _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_9 <= _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_issued <= _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_issued_partial_agen <= _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_issued_partial_dgen <= _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p1_speculative_child <= _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p2_speculative_child <= _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p1_bypass_hint <= _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p2_bypass_hint <= _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p3_bypass_hint <= _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22, :477:22]
out_reg_uop_dis_col_sel <= _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_br_mask <= _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22, :477:22]
out_reg_uop_br_tag <= _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22, :477:22]
out_reg_uop_br_type <= _main_io_deq_bits_uop_br_type; // @[util.scala:476:22, :477:22]
out_reg_uop_is_sfb <= _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22, :477:22]
out_reg_uop_is_fence <= _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22, :477:22]
out_reg_uop_is_fencei <= _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22, :477:22]
out_reg_uop_is_sfence <= _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22, :477:22]
out_reg_uop_is_amo <= _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22, :477:22]
out_reg_uop_is_eret <= _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22, :477:22]
out_reg_uop_is_sys_pc2epc <= _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22, :477:22]
out_reg_uop_is_rocc <= _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22, :477:22]
out_reg_uop_is_mov <= _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22, :477:22]
out_reg_uop_ftq_idx <= _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_edge_inst <= _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22, :477:22]
out_reg_uop_pc_lob <= _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22, :477:22]
out_reg_uop_taken <= _main_io_deq_bits_uop_taken; // @[util.scala:476:22, :477:22]
out_reg_uop_imm_rename <= _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22, :477:22]
out_reg_uop_imm_sel <= _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_pimm <= _main_io_deq_bits_uop_pimm; // @[util.scala:476:22, :477:22]
out_reg_uop_imm_packed <= _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22, :477:22]
out_reg_uop_op1_sel <= _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_op2_sel <= _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ldst <= _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_wen <= _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ren1 <= _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ren2 <= _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ren3 <= _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_swap12 <= _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_swap23 <= _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_typeTagIn <= _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_typeTagOut <= _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_fromint <= _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_toint <= _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_fastpipe <= _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_fma <= _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_div <= _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_sqrt <= _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_wflags <= _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_vec <= _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22, :477:22]
out_reg_uop_rob_idx <= _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_ldq_idx <= _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_stq_idx <= _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_rxq_idx <= _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_pdst <= _main_io_deq_bits_uop_pdst; // @[util.scala:476:22, :477:22]
out_reg_uop_prs1 <= _main_io_deq_bits_uop_prs1; // @[util.scala:476:22, :477:22]
out_reg_uop_prs2 <= _main_io_deq_bits_uop_prs2; // @[util.scala:476:22, :477:22]
out_reg_uop_prs3 <= _main_io_deq_bits_uop_prs3; // @[util.scala:476:22, :477:22]
out_reg_uop_ppred <= _main_io_deq_bits_uop_ppred; // @[util.scala:476:22, :477:22]
out_reg_uop_prs1_busy <= _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_prs2_busy <= _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_prs3_busy <= _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_ppred_busy <= _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_stale_pdst <= _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22, :477:22]
out_reg_uop_exception <= _main_io_deq_bits_uop_exception; // @[util.scala:476:22, :477:22]
out_reg_uop_exc_cause <= _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22, :477:22]
out_reg_uop_mem_cmd <= _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22, :477:22]
out_reg_uop_mem_size <= _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22, :477:22]
out_reg_uop_mem_signed <= _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22, :477:22]
out_reg_uop_uses_ldq <= _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22, :477:22]
out_reg_uop_uses_stq <= _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22, :477:22]
out_reg_uop_is_unique <= _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22, :477:22]
out_reg_uop_flush_on_commit <= _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22, :477:22]
out_reg_uop_csr_cmd <= _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22, :477:22]
out_reg_uop_ldst_is_rs1 <= _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22, :477:22]
out_reg_uop_ldst <= _main_io_deq_bits_uop_ldst; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs1 <= _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs2 <= _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs3 <= _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22, :477:22]
out_reg_uop_dst_rtype <= _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs1_rtype <= _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs2_rtype <= _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22, :477:22]
out_reg_uop_frs3_en <= _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22, :477:22]
out_reg_uop_fcn_dw <= _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22, :477:22]
out_reg_uop_fcn_op <= _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_val <= _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_rm <= _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_typ <= _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22, :477:22]
out_reg_uop_xcpt_pf_if <= _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22, :477:22]
out_reg_uop_xcpt_ae_if <= _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22, :477:22]
out_reg_uop_xcpt_ma_if <= _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22, :477:22]
out_reg_uop_bp_debug_if <= _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22, :477:22]
out_reg_uop_bp_xcpt_if <= _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_fsrc <= _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_tsrc <= _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22, :477:22]
out_reg_addr <= _main_io_deq_bits_addr; // @[util.scala:476:22, :477:22]
out_reg_data <= _main_io_deq_bits_data; // @[util.scala:476:22, :477:22]
out_reg_is_hella <= _main_io_deq_bits_is_hella; // @[util.scala:476:22, :477:22]
out_reg_tag_match <= _main_io_deq_bits_tag_match; // @[util.scala:476:22, :477:22]
out_reg_old_meta_coh_state <= _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22, :477:22]
out_reg_old_meta_tag <= _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22, :477:22]
out_reg_way_en <= _main_io_deq_bits_way_en; // @[util.scala:476:22, :477:22]
out_reg_sdq_id <= _main_io_deq_bits_sdq_id; // @[util.scala:476:22, :477:22]
end
out_uop_inst <= main_io_deq_ready ? out_uop_out_1_inst : out_uop_out_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_inst <= main_io_deq_ready ? out_uop_out_1_debug_inst : out_uop_out_debug_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_rvc <= main_io_deq_ready ? out_uop_out_1_is_rvc : out_uop_out_is_rvc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_pc <= main_io_deq_ready ? out_uop_out_1_debug_pc : out_uop_out_debug_pc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_0 <= main_io_deq_ready ? out_uop_out_1_iq_type_0 : out_uop_out_iq_type_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_1 <= main_io_deq_ready ? out_uop_out_1_iq_type_1 : out_uop_out_iq_type_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_2 <= main_io_deq_ready ? out_uop_out_1_iq_type_2 : out_uop_out_iq_type_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_3 <= main_io_deq_ready ? out_uop_out_1_iq_type_3 : out_uop_out_iq_type_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_0 <= main_io_deq_ready ? out_uop_out_1_fu_code_0 : out_uop_out_fu_code_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_1 <= main_io_deq_ready ? out_uop_out_1_fu_code_1 : out_uop_out_fu_code_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_2 <= main_io_deq_ready ? out_uop_out_1_fu_code_2 : out_uop_out_fu_code_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_3 <= main_io_deq_ready ? out_uop_out_1_fu_code_3 : out_uop_out_fu_code_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_4 <= main_io_deq_ready ? out_uop_out_1_fu_code_4 : out_uop_out_fu_code_4; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_5 <= main_io_deq_ready ? out_uop_out_1_fu_code_5 : out_uop_out_fu_code_5; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_6 <= main_io_deq_ready ? out_uop_out_1_fu_code_6 : out_uop_out_fu_code_6; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_7 <= main_io_deq_ready ? out_uop_out_1_fu_code_7 : out_uop_out_fu_code_7; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_8 <= main_io_deq_ready ? out_uop_out_1_fu_code_8 : out_uop_out_fu_code_8; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_9 <= main_io_deq_ready ? out_uop_out_1_fu_code_9 : out_uop_out_fu_code_9; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_issued <= main_io_deq_ready ? out_uop_out_1_iw_issued : out_uop_out_iw_issued; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_issued_partial_agen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_agen : out_uop_out_iw_issued_partial_agen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_issued_partial_dgen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_dgen : out_uop_out_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p1_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p1_speculative_child : out_uop_out_iw_p1_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p2_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p2_speculative_child : out_uop_out_iw_p2_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p1_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p1_bypass_hint : out_uop_out_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p2_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p2_bypass_hint : out_uop_out_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p3_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p3_bypass_hint : out_uop_out_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_dis_col_sel <= main_io_deq_ready ? out_uop_out_1_dis_col_sel : out_uop_out_dis_col_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_br_mask <= main_io_deq_ready ? out_uop_out_1_br_mask : out_uop_out_br_mask; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_br_tag <= main_io_deq_ready ? out_uop_out_1_br_tag : out_uop_out_br_tag; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_br_type <= main_io_deq_ready ? out_uop_out_1_br_type : out_uop_out_br_type; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_sfb <= main_io_deq_ready ? out_uop_out_1_is_sfb : out_uop_out_is_sfb; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_fence <= main_io_deq_ready ? out_uop_out_1_is_fence : out_uop_out_is_fence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_fencei <= main_io_deq_ready ? out_uop_out_1_is_fencei : out_uop_out_is_fencei; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_sfence <= main_io_deq_ready ? out_uop_out_1_is_sfence : out_uop_out_is_sfence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_amo <= main_io_deq_ready ? out_uop_out_1_is_amo : out_uop_out_is_amo; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_eret <= main_io_deq_ready ? out_uop_out_1_is_eret : out_uop_out_is_eret; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_sys_pc2epc <= main_io_deq_ready ? out_uop_out_1_is_sys_pc2epc : out_uop_out_is_sys_pc2epc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_rocc <= main_io_deq_ready ? out_uop_out_1_is_rocc : out_uop_out_is_rocc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_mov <= main_io_deq_ready ? out_uop_out_1_is_mov : out_uop_out_is_mov; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ftq_idx <= main_io_deq_ready ? out_uop_out_1_ftq_idx : out_uop_out_ftq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_edge_inst <= main_io_deq_ready ? out_uop_out_1_edge_inst : out_uop_out_edge_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_pc_lob <= main_io_deq_ready ? out_uop_out_1_pc_lob : out_uop_out_pc_lob; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_taken <= main_io_deq_ready ? out_uop_out_1_taken : out_uop_out_taken; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_imm_rename <= main_io_deq_ready ? out_uop_out_1_imm_rename : out_uop_out_imm_rename; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_imm_sel <= main_io_deq_ready ? out_uop_out_1_imm_sel : out_uop_out_imm_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_pimm <= main_io_deq_ready ? out_uop_out_1_pimm : out_uop_out_pimm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_imm_packed <= main_io_deq_ready ? out_uop_out_1_imm_packed : out_uop_out_imm_packed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_op1_sel <= main_io_deq_ready ? out_uop_out_1_op1_sel : out_uop_out_op1_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_op2_sel <= main_io_deq_ready ? out_uop_out_1_op2_sel : out_uop_out_op2_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ldst <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ldst : out_uop_out_fp_ctrl_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_wen <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wen : out_uop_out_fp_ctrl_wen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ren1 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren1 : out_uop_out_fp_ctrl_ren1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ren2 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren2 : out_uop_out_fp_ctrl_ren2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ren3 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren3 : out_uop_out_fp_ctrl_ren3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_swap12 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap12 : out_uop_out_fp_ctrl_swap12; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_swap23 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap23 : out_uop_out_fp_ctrl_swap23; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_typeTagIn <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagIn : out_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_typeTagOut <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagOut : out_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_fromint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fromint : out_uop_out_fp_ctrl_fromint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_toint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_toint : out_uop_out_fp_ctrl_toint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_fastpipe <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fastpipe : out_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_fma <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fma : out_uop_out_fp_ctrl_fma; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_div <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_div : out_uop_out_fp_ctrl_div; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_sqrt <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_sqrt : out_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_wflags <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wflags : out_uop_out_fp_ctrl_wflags; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_vec <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_vec : out_uop_out_fp_ctrl_vec; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_rob_idx <= main_io_deq_ready ? out_uop_out_1_rob_idx : out_uop_out_rob_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ldq_idx <= main_io_deq_ready ? out_uop_out_1_ldq_idx : out_uop_out_ldq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_stq_idx <= main_io_deq_ready ? out_uop_out_1_stq_idx : out_uop_out_stq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_rxq_idx <= main_io_deq_ready ? out_uop_out_1_rxq_idx : out_uop_out_rxq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_pdst <= main_io_deq_ready ? out_uop_out_1_pdst : out_uop_out_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs1 <= main_io_deq_ready ? out_uop_out_1_prs1 : out_uop_out_prs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs2 <= main_io_deq_ready ? out_uop_out_1_prs2 : out_uop_out_prs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs3 <= main_io_deq_ready ? out_uop_out_1_prs3 : out_uop_out_prs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ppred <= main_io_deq_ready ? out_uop_out_1_ppred : out_uop_out_ppred; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs1_busy <= main_io_deq_ready ? out_uop_out_1_prs1_busy : out_uop_out_prs1_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs2_busy <= main_io_deq_ready ? out_uop_out_1_prs2_busy : out_uop_out_prs2_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs3_busy <= main_io_deq_ready ? out_uop_out_1_prs3_busy : out_uop_out_prs3_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ppred_busy <= main_io_deq_ready ? out_uop_out_1_ppred_busy : out_uop_out_ppred_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_stale_pdst <= main_io_deq_ready ? out_uop_out_1_stale_pdst : out_uop_out_stale_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_exception <= main_io_deq_ready ? out_uop_out_1_exception : out_uop_out_exception; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_exc_cause <= main_io_deq_ready ? out_uop_out_1_exc_cause : out_uop_out_exc_cause; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_mem_cmd <= main_io_deq_ready ? out_uop_out_1_mem_cmd : out_uop_out_mem_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_mem_size <= main_io_deq_ready ? out_uop_out_1_mem_size : out_uop_out_mem_size; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_mem_signed <= main_io_deq_ready ? out_uop_out_1_mem_signed : out_uop_out_mem_signed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_uses_ldq <= main_io_deq_ready ? out_uop_out_1_uses_ldq : out_uop_out_uses_ldq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_uses_stq <= main_io_deq_ready ? out_uop_out_1_uses_stq : out_uop_out_uses_stq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_unique <= main_io_deq_ready ? out_uop_out_1_is_unique : out_uop_out_is_unique; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_flush_on_commit <= main_io_deq_ready ? out_uop_out_1_flush_on_commit : out_uop_out_flush_on_commit; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_csr_cmd <= main_io_deq_ready ? out_uop_out_1_csr_cmd : out_uop_out_csr_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ldst_is_rs1 <= main_io_deq_ready ? out_uop_out_1_ldst_is_rs1 : out_uop_out_ldst_is_rs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ldst <= main_io_deq_ready ? out_uop_out_1_ldst : out_uop_out_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs1 <= main_io_deq_ready ? out_uop_out_1_lrs1 : out_uop_out_lrs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs2 <= main_io_deq_ready ? out_uop_out_1_lrs2 : out_uop_out_lrs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs3 <= main_io_deq_ready ? out_uop_out_1_lrs3 : out_uop_out_lrs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_dst_rtype <= main_io_deq_ready ? out_uop_out_1_dst_rtype : out_uop_out_dst_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs1_rtype <= main_io_deq_ready ? out_uop_out_1_lrs1_rtype : out_uop_out_lrs1_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs2_rtype <= main_io_deq_ready ? out_uop_out_1_lrs2_rtype : out_uop_out_lrs2_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_frs3_en <= main_io_deq_ready ? out_uop_out_1_frs3_en : out_uop_out_frs3_en; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fcn_dw <= main_io_deq_ready ? out_uop_out_1_fcn_dw : out_uop_out_fcn_dw; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fcn_op <= main_io_deq_ready ? out_uop_out_1_fcn_op : out_uop_out_fcn_op; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_val <= main_io_deq_ready ? out_uop_out_1_fp_val : out_uop_out_fp_val; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_rm <= main_io_deq_ready ? out_uop_out_1_fp_rm : out_uop_out_fp_rm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_typ <= main_io_deq_ready ? out_uop_out_1_fp_typ : out_uop_out_fp_typ; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_xcpt_pf_if <= main_io_deq_ready ? out_uop_out_1_xcpt_pf_if : out_uop_out_xcpt_pf_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_xcpt_ae_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ae_if : out_uop_out_xcpt_ae_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_xcpt_ma_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ma_if : out_uop_out_xcpt_ma_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_bp_debug_if <= main_io_deq_ready ? out_uop_out_1_bp_debug_if : out_uop_out_bp_debug_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_bp_xcpt_if <= main_io_deq_ready ? out_uop_out_1_bp_xcpt_if : out_uop_out_bp_xcpt_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_fsrc <= main_io_deq_ready ? out_uop_out_1_debug_fsrc : out_uop_out_debug_fsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_tsrc <= main_io_deq_ready ? out_uop_out_1_debug_tsrc : out_uop_out_debug_tsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
if (reset) // @[util.scala:458:7]
out_valid <= 1'h0; // @[util.scala:478:28]
else // @[util.scala:458:7]
out_valid <= main_io_deq_ready ? _out_valid_T_15 : _out_valid_T_7; // @[util.scala:478:28, :492:{15,80}, :495:{23,38}, :496:{17,103}]
always @(posedge)
BranchKillableQueue_2 main ( // @[util.scala:476:22]
.clock (clock),
.reset (reset),
.io_enq_ready (io_enq_ready_0),
.io_enq_valid (io_enq_valid_0), // @[util.scala:458:7]
.io_enq_bits_uop_inst (io_enq_bits_uop_inst_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_inst (io_enq_bits_uop_debug_inst_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_rvc (io_enq_bits_uop_is_rvc_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_pc (io_enq_bits_uop_debug_pc_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_0 (io_enq_bits_uop_iq_type_0_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_1 (io_enq_bits_uop_iq_type_1_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_2 (io_enq_bits_uop_iq_type_2_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_3 (io_enq_bits_uop_iq_type_3_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_0 (io_enq_bits_uop_fu_code_0_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_1 (io_enq_bits_uop_fu_code_1_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_2 (io_enq_bits_uop_fu_code_2_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_3 (io_enq_bits_uop_fu_code_3_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_4 (io_enq_bits_uop_fu_code_4_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_5 (io_enq_bits_uop_fu_code_5_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_6 (io_enq_bits_uop_fu_code_6_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_7 (io_enq_bits_uop_fu_code_7_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_8 (io_enq_bits_uop_fu_code_8_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_9 (io_enq_bits_uop_fu_code_9_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_issued (io_enq_bits_uop_iw_issued_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_issued_partial_agen (io_enq_bits_uop_iw_issued_partial_agen_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_issued_partial_dgen (io_enq_bits_uop_iw_issued_partial_dgen_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p1_speculative_child (io_enq_bits_uop_iw_p1_speculative_child_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p2_speculative_child (io_enq_bits_uop_iw_p2_speculative_child_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p1_bypass_hint (io_enq_bits_uop_iw_p1_bypass_hint_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p2_bypass_hint (io_enq_bits_uop_iw_p2_bypass_hint_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p3_bypass_hint (io_enq_bits_uop_iw_p3_bypass_hint_0), // @[util.scala:458:7]
.io_enq_bits_uop_dis_col_sel (io_enq_bits_uop_dis_col_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_br_mask (io_enq_bits_uop_br_mask_0), // @[util.scala:458:7]
.io_enq_bits_uop_br_tag (io_enq_bits_uop_br_tag_0), // @[util.scala:458:7]
.io_enq_bits_uop_br_type (io_enq_bits_uop_br_type_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_sfb (io_enq_bits_uop_is_sfb_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_fence (io_enq_bits_uop_is_fence_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_fencei (io_enq_bits_uop_is_fencei_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_sfence (io_enq_bits_uop_is_sfence_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_amo (io_enq_bits_uop_is_amo_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_eret (io_enq_bits_uop_is_eret_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_sys_pc2epc (io_enq_bits_uop_is_sys_pc2epc_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_rocc (io_enq_bits_uop_is_rocc_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_mov (io_enq_bits_uop_is_mov_0), // @[util.scala:458:7]
.io_enq_bits_uop_ftq_idx (io_enq_bits_uop_ftq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_edge_inst (io_enq_bits_uop_edge_inst_0), // @[util.scala:458:7]
.io_enq_bits_uop_pc_lob (io_enq_bits_uop_pc_lob_0), // @[util.scala:458:7]
.io_enq_bits_uop_taken (io_enq_bits_uop_taken_0), // @[util.scala:458:7]
.io_enq_bits_uop_imm_rename (io_enq_bits_uop_imm_rename_0), // @[util.scala:458:7]
.io_enq_bits_uop_imm_sel (io_enq_bits_uop_imm_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_pimm (io_enq_bits_uop_pimm_0), // @[util.scala:458:7]
.io_enq_bits_uop_imm_packed (io_enq_bits_uop_imm_packed_0), // @[util.scala:458:7]
.io_enq_bits_uop_op1_sel (io_enq_bits_uop_op1_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_op2_sel (io_enq_bits_uop_op2_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ldst (io_enq_bits_uop_fp_ctrl_ldst_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_wen (io_enq_bits_uop_fp_ctrl_wen_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ren1 (io_enq_bits_uop_fp_ctrl_ren1_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ren2 (io_enq_bits_uop_fp_ctrl_ren2_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ren3 (io_enq_bits_uop_fp_ctrl_ren3_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_swap12 (io_enq_bits_uop_fp_ctrl_swap12_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_swap23 (io_enq_bits_uop_fp_ctrl_swap23_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_typeTagIn (io_enq_bits_uop_fp_ctrl_typeTagIn_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_typeTagOut (io_enq_bits_uop_fp_ctrl_typeTagOut_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_fromint (io_enq_bits_uop_fp_ctrl_fromint_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_toint (io_enq_bits_uop_fp_ctrl_toint_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_fastpipe (io_enq_bits_uop_fp_ctrl_fastpipe_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_fma (io_enq_bits_uop_fp_ctrl_fma_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_div (io_enq_bits_uop_fp_ctrl_div_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_sqrt (io_enq_bits_uop_fp_ctrl_sqrt_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_wflags (io_enq_bits_uop_fp_ctrl_wflags_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_vec (io_enq_bits_uop_fp_ctrl_vec_0), // @[util.scala:458:7]
.io_enq_bits_uop_rob_idx (io_enq_bits_uop_rob_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_ldq_idx (io_enq_bits_uop_ldq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_stq_idx (io_enq_bits_uop_stq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_rxq_idx (io_enq_bits_uop_rxq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_pdst (io_enq_bits_uop_pdst_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs1 (io_enq_bits_uop_prs1_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs2 (io_enq_bits_uop_prs2_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs3 (io_enq_bits_uop_prs3_0), // @[util.scala:458:7]
.io_enq_bits_uop_ppred (io_enq_bits_uop_ppred_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs1_busy (io_enq_bits_uop_prs1_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs2_busy (io_enq_bits_uop_prs2_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs3_busy (io_enq_bits_uop_prs3_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_ppred_busy (io_enq_bits_uop_ppred_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_stale_pdst (io_enq_bits_uop_stale_pdst_0), // @[util.scala:458:7]
.io_enq_bits_uop_exception (io_enq_bits_uop_exception_0), // @[util.scala:458:7]
.io_enq_bits_uop_exc_cause (io_enq_bits_uop_exc_cause_0), // @[util.scala:458:7]
.io_enq_bits_uop_mem_cmd (io_enq_bits_uop_mem_cmd_0), // @[util.scala:458:7]
.io_enq_bits_uop_mem_size (io_enq_bits_uop_mem_size_0), // @[util.scala:458:7]
.io_enq_bits_uop_mem_signed (io_enq_bits_uop_mem_signed_0), // @[util.scala:458:7]
.io_enq_bits_uop_uses_ldq (io_enq_bits_uop_uses_ldq_0), // @[util.scala:458:7]
.io_enq_bits_uop_uses_stq (io_enq_bits_uop_uses_stq_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_unique (io_enq_bits_uop_is_unique_0), // @[util.scala:458:7]
.io_enq_bits_uop_flush_on_commit (io_enq_bits_uop_flush_on_commit_0), // @[util.scala:458:7]
.io_enq_bits_uop_csr_cmd (io_enq_bits_uop_csr_cmd_0), // @[util.scala:458:7]
.io_enq_bits_uop_ldst_is_rs1 (io_enq_bits_uop_ldst_is_rs1_0), // @[util.scala:458:7]
.io_enq_bits_uop_ldst (io_enq_bits_uop_ldst_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs1 (io_enq_bits_uop_lrs1_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs2 (io_enq_bits_uop_lrs2_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs3 (io_enq_bits_uop_lrs3_0), // @[util.scala:458:7]
.io_enq_bits_uop_dst_rtype (io_enq_bits_uop_dst_rtype_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs1_rtype (io_enq_bits_uop_lrs1_rtype_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs2_rtype (io_enq_bits_uop_lrs2_rtype_0), // @[util.scala:458:7]
.io_enq_bits_uop_frs3_en (io_enq_bits_uop_frs3_en_0), // @[util.scala:458:7]
.io_enq_bits_uop_fcn_dw (io_enq_bits_uop_fcn_dw_0), // @[util.scala:458:7]
.io_enq_bits_uop_fcn_op (io_enq_bits_uop_fcn_op_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_val (io_enq_bits_uop_fp_val_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_rm (io_enq_bits_uop_fp_rm_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_typ (io_enq_bits_uop_fp_typ_0), // @[util.scala:458:7]
.io_enq_bits_uop_xcpt_pf_if (io_enq_bits_uop_xcpt_pf_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_xcpt_ae_if (io_enq_bits_uop_xcpt_ae_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_xcpt_ma_if (io_enq_bits_uop_xcpt_ma_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_bp_debug_if (io_enq_bits_uop_bp_debug_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_bp_xcpt_if (io_enq_bits_uop_bp_xcpt_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_fsrc (io_enq_bits_uop_debug_fsrc_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_tsrc (io_enq_bits_uop_debug_tsrc_0), // @[util.scala:458:7]
.io_enq_bits_addr (io_enq_bits_addr_0), // @[util.scala:458:7]
.io_enq_bits_data (io_enq_bits_data_0), // @[util.scala:458:7]
.io_enq_bits_is_hella (io_enq_bits_is_hella_0), // @[util.scala:458:7]
.io_enq_bits_tag_match (io_enq_bits_tag_match_0), // @[util.scala:458:7]
.io_enq_bits_old_meta_coh_state (io_enq_bits_old_meta_coh_state_0), // @[util.scala:458:7]
.io_enq_bits_old_meta_tag (io_enq_bits_old_meta_tag_0), // @[util.scala:458:7]
.io_enq_bits_way_en (io_enq_bits_way_en_0), // @[util.scala:458:7]
.io_enq_bits_sdq_id (io_enq_bits_sdq_id_0), // @[util.scala:458:7]
.io_deq_ready (main_io_deq_ready), // @[util.scala:495:23]
.io_deq_valid (_main_io_deq_valid),
.io_deq_bits_uop_inst (_main_io_deq_bits_uop_inst),
.io_deq_bits_uop_debug_inst (_main_io_deq_bits_uop_debug_inst),
.io_deq_bits_uop_is_rvc (_main_io_deq_bits_uop_is_rvc),
.io_deq_bits_uop_debug_pc (_main_io_deq_bits_uop_debug_pc),
.io_deq_bits_uop_iq_type_0 (_main_io_deq_bits_uop_iq_type_0),
.io_deq_bits_uop_iq_type_1 (_main_io_deq_bits_uop_iq_type_1),
.io_deq_bits_uop_iq_type_2 (_main_io_deq_bits_uop_iq_type_2),
.io_deq_bits_uop_iq_type_3 (_main_io_deq_bits_uop_iq_type_3),
.io_deq_bits_uop_fu_code_0 (_main_io_deq_bits_uop_fu_code_0),
.io_deq_bits_uop_fu_code_1 (_main_io_deq_bits_uop_fu_code_1),
.io_deq_bits_uop_fu_code_2 (_main_io_deq_bits_uop_fu_code_2),
.io_deq_bits_uop_fu_code_3 (_main_io_deq_bits_uop_fu_code_3),
.io_deq_bits_uop_fu_code_4 (_main_io_deq_bits_uop_fu_code_4),
.io_deq_bits_uop_fu_code_5 (_main_io_deq_bits_uop_fu_code_5),
.io_deq_bits_uop_fu_code_6 (_main_io_deq_bits_uop_fu_code_6),
.io_deq_bits_uop_fu_code_7 (_main_io_deq_bits_uop_fu_code_7),
.io_deq_bits_uop_fu_code_8 (_main_io_deq_bits_uop_fu_code_8),
.io_deq_bits_uop_fu_code_9 (_main_io_deq_bits_uop_fu_code_9),
.io_deq_bits_uop_iw_issued (_main_io_deq_bits_uop_iw_issued),
.io_deq_bits_uop_iw_issued_partial_agen (_main_io_deq_bits_uop_iw_issued_partial_agen),
.io_deq_bits_uop_iw_issued_partial_dgen (_main_io_deq_bits_uop_iw_issued_partial_dgen),
.io_deq_bits_uop_iw_p1_speculative_child (_main_io_deq_bits_uop_iw_p1_speculative_child),
.io_deq_bits_uop_iw_p2_speculative_child (_main_io_deq_bits_uop_iw_p2_speculative_child),
.io_deq_bits_uop_iw_p1_bypass_hint (_main_io_deq_bits_uop_iw_p1_bypass_hint),
.io_deq_bits_uop_iw_p2_bypass_hint (_main_io_deq_bits_uop_iw_p2_bypass_hint),
.io_deq_bits_uop_iw_p3_bypass_hint (_main_io_deq_bits_uop_iw_p3_bypass_hint),
.io_deq_bits_uop_dis_col_sel (_main_io_deq_bits_uop_dis_col_sel),
.io_deq_bits_uop_br_mask (_main_io_deq_bits_uop_br_mask),
.io_deq_bits_uop_br_tag (_main_io_deq_bits_uop_br_tag),
.io_deq_bits_uop_br_type (_main_io_deq_bits_uop_br_type),
.io_deq_bits_uop_is_sfb (_main_io_deq_bits_uop_is_sfb),
.io_deq_bits_uop_is_fence (_main_io_deq_bits_uop_is_fence),
.io_deq_bits_uop_is_fencei (_main_io_deq_bits_uop_is_fencei),
.io_deq_bits_uop_is_sfence (_main_io_deq_bits_uop_is_sfence),
.io_deq_bits_uop_is_amo (_main_io_deq_bits_uop_is_amo),
.io_deq_bits_uop_is_eret (_main_io_deq_bits_uop_is_eret),
.io_deq_bits_uop_is_sys_pc2epc (_main_io_deq_bits_uop_is_sys_pc2epc),
.io_deq_bits_uop_is_rocc (_main_io_deq_bits_uop_is_rocc),
.io_deq_bits_uop_is_mov (_main_io_deq_bits_uop_is_mov),
.io_deq_bits_uop_ftq_idx (_main_io_deq_bits_uop_ftq_idx),
.io_deq_bits_uop_edge_inst (_main_io_deq_bits_uop_edge_inst),
.io_deq_bits_uop_pc_lob (_main_io_deq_bits_uop_pc_lob),
.io_deq_bits_uop_taken (_main_io_deq_bits_uop_taken),
.io_deq_bits_uop_imm_rename (_main_io_deq_bits_uop_imm_rename),
.io_deq_bits_uop_imm_sel (_main_io_deq_bits_uop_imm_sel),
.io_deq_bits_uop_pimm (_main_io_deq_bits_uop_pimm),
.io_deq_bits_uop_imm_packed (_main_io_deq_bits_uop_imm_packed),
.io_deq_bits_uop_op1_sel (_main_io_deq_bits_uop_op1_sel),
.io_deq_bits_uop_op2_sel (_main_io_deq_bits_uop_op2_sel),
.io_deq_bits_uop_fp_ctrl_ldst (_main_io_deq_bits_uop_fp_ctrl_ldst),
.io_deq_bits_uop_fp_ctrl_wen (_main_io_deq_bits_uop_fp_ctrl_wen),
.io_deq_bits_uop_fp_ctrl_ren1 (_main_io_deq_bits_uop_fp_ctrl_ren1),
.io_deq_bits_uop_fp_ctrl_ren2 (_main_io_deq_bits_uop_fp_ctrl_ren2),
.io_deq_bits_uop_fp_ctrl_ren3 (_main_io_deq_bits_uop_fp_ctrl_ren3),
.io_deq_bits_uop_fp_ctrl_swap12 (_main_io_deq_bits_uop_fp_ctrl_swap12),
.io_deq_bits_uop_fp_ctrl_swap23 (_main_io_deq_bits_uop_fp_ctrl_swap23),
.io_deq_bits_uop_fp_ctrl_typeTagIn (_main_io_deq_bits_uop_fp_ctrl_typeTagIn),
.io_deq_bits_uop_fp_ctrl_typeTagOut (_main_io_deq_bits_uop_fp_ctrl_typeTagOut),
.io_deq_bits_uop_fp_ctrl_fromint (_main_io_deq_bits_uop_fp_ctrl_fromint),
.io_deq_bits_uop_fp_ctrl_toint (_main_io_deq_bits_uop_fp_ctrl_toint),
.io_deq_bits_uop_fp_ctrl_fastpipe (_main_io_deq_bits_uop_fp_ctrl_fastpipe),
.io_deq_bits_uop_fp_ctrl_fma (_main_io_deq_bits_uop_fp_ctrl_fma),
.io_deq_bits_uop_fp_ctrl_div (_main_io_deq_bits_uop_fp_ctrl_div),
.io_deq_bits_uop_fp_ctrl_sqrt (_main_io_deq_bits_uop_fp_ctrl_sqrt),
.io_deq_bits_uop_fp_ctrl_wflags (_main_io_deq_bits_uop_fp_ctrl_wflags),
.io_deq_bits_uop_fp_ctrl_vec (_main_io_deq_bits_uop_fp_ctrl_vec),
.io_deq_bits_uop_rob_idx (_main_io_deq_bits_uop_rob_idx),
.io_deq_bits_uop_ldq_idx (_main_io_deq_bits_uop_ldq_idx),
.io_deq_bits_uop_stq_idx (_main_io_deq_bits_uop_stq_idx),
.io_deq_bits_uop_rxq_idx (_main_io_deq_bits_uop_rxq_idx),
.io_deq_bits_uop_pdst (_main_io_deq_bits_uop_pdst),
.io_deq_bits_uop_prs1 (_main_io_deq_bits_uop_prs1),
.io_deq_bits_uop_prs2 (_main_io_deq_bits_uop_prs2),
.io_deq_bits_uop_prs3 (_main_io_deq_bits_uop_prs3),
.io_deq_bits_uop_ppred (_main_io_deq_bits_uop_ppred),
.io_deq_bits_uop_prs1_busy (_main_io_deq_bits_uop_prs1_busy),
.io_deq_bits_uop_prs2_busy (_main_io_deq_bits_uop_prs2_busy),
.io_deq_bits_uop_prs3_busy (_main_io_deq_bits_uop_prs3_busy),
.io_deq_bits_uop_ppred_busy (_main_io_deq_bits_uop_ppred_busy),
.io_deq_bits_uop_stale_pdst (_main_io_deq_bits_uop_stale_pdst),
.io_deq_bits_uop_exception (_main_io_deq_bits_uop_exception),
.io_deq_bits_uop_exc_cause (_main_io_deq_bits_uop_exc_cause),
.io_deq_bits_uop_mem_cmd (_main_io_deq_bits_uop_mem_cmd),
.io_deq_bits_uop_mem_size (_main_io_deq_bits_uop_mem_size),
.io_deq_bits_uop_mem_signed (_main_io_deq_bits_uop_mem_signed),
.io_deq_bits_uop_uses_ldq (_main_io_deq_bits_uop_uses_ldq),
.io_deq_bits_uop_uses_stq (_main_io_deq_bits_uop_uses_stq),
.io_deq_bits_uop_is_unique (_main_io_deq_bits_uop_is_unique),
.io_deq_bits_uop_flush_on_commit (_main_io_deq_bits_uop_flush_on_commit),
.io_deq_bits_uop_csr_cmd (_main_io_deq_bits_uop_csr_cmd),
.io_deq_bits_uop_ldst_is_rs1 (_main_io_deq_bits_uop_ldst_is_rs1),
.io_deq_bits_uop_ldst (_main_io_deq_bits_uop_ldst),
.io_deq_bits_uop_lrs1 (_main_io_deq_bits_uop_lrs1),
.io_deq_bits_uop_lrs2 (_main_io_deq_bits_uop_lrs2),
.io_deq_bits_uop_lrs3 (_main_io_deq_bits_uop_lrs3),
.io_deq_bits_uop_dst_rtype (_main_io_deq_bits_uop_dst_rtype),
.io_deq_bits_uop_lrs1_rtype (_main_io_deq_bits_uop_lrs1_rtype),
.io_deq_bits_uop_lrs2_rtype (_main_io_deq_bits_uop_lrs2_rtype),
.io_deq_bits_uop_frs3_en (_main_io_deq_bits_uop_frs3_en),
.io_deq_bits_uop_fcn_dw (_main_io_deq_bits_uop_fcn_dw),
.io_deq_bits_uop_fcn_op (_main_io_deq_bits_uop_fcn_op),
.io_deq_bits_uop_fp_val (_main_io_deq_bits_uop_fp_val),
.io_deq_bits_uop_fp_rm (_main_io_deq_bits_uop_fp_rm),
.io_deq_bits_uop_fp_typ (_main_io_deq_bits_uop_fp_typ),
.io_deq_bits_uop_xcpt_pf_if (_main_io_deq_bits_uop_xcpt_pf_if),
.io_deq_bits_uop_xcpt_ae_if (_main_io_deq_bits_uop_xcpt_ae_if),
.io_deq_bits_uop_xcpt_ma_if (_main_io_deq_bits_uop_xcpt_ma_if),
.io_deq_bits_uop_bp_debug_if (_main_io_deq_bits_uop_bp_debug_if),
.io_deq_bits_uop_bp_xcpt_if (_main_io_deq_bits_uop_bp_xcpt_if),
.io_deq_bits_uop_debug_fsrc (_main_io_deq_bits_uop_debug_fsrc),
.io_deq_bits_uop_debug_tsrc (_main_io_deq_bits_uop_debug_tsrc),
.io_deq_bits_addr (_main_io_deq_bits_addr),
.io_deq_bits_data (_main_io_deq_bits_data),
.io_deq_bits_is_hella (_main_io_deq_bits_is_hella),
.io_deq_bits_tag_match (_main_io_deq_bits_tag_match),
.io_deq_bits_old_meta_coh_state (_main_io_deq_bits_old_meta_coh_state),
.io_deq_bits_old_meta_tag (_main_io_deq_bits_old_meta_tag),
.io_deq_bits_way_en (_main_io_deq_bits_way_en),
.io_deq_bits_sdq_id (_main_io_deq_bits_sdq_id),
.io_brupdate_b1_resolve_mask (io_brupdate_b1_resolve_mask_0), // @[util.scala:458:7]
.io_brupdate_b1_mispredict_mask (io_brupdate_b1_mispredict_mask_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_inst (io_brupdate_b2_uop_inst_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_debug_inst (io_brupdate_b2_uop_debug_inst_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_rvc (io_brupdate_b2_uop_is_rvc_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_debug_pc (io_brupdate_b2_uop_debug_pc_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iq_type_0 (io_brupdate_b2_uop_iq_type_0_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iq_type_1 (io_brupdate_b2_uop_iq_type_1_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iq_type_2 (io_brupdate_b2_uop_iq_type_2_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iq_type_3 (io_brupdate_b2_uop_iq_type_3_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_0 (io_brupdate_b2_uop_fu_code_0_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_1 (io_brupdate_b2_uop_fu_code_1_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_2 (io_brupdate_b2_uop_fu_code_2_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_3 (io_brupdate_b2_uop_fu_code_3_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_4 (io_brupdate_b2_uop_fu_code_4_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_5 (io_brupdate_b2_uop_fu_code_5_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_6 (io_brupdate_b2_uop_fu_code_6_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_7 (io_brupdate_b2_uop_fu_code_7_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_8 (io_brupdate_b2_uop_fu_code_8_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_9 (io_brupdate_b2_uop_fu_code_9_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iw_issued (io_brupdate_b2_uop_iw_issued_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iw_issued_partial_agen (io_brupdate_b2_uop_iw_issued_partial_agen_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iw_issued_partial_dgen (io_brupdate_b2_uop_iw_issued_partial_dgen_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iw_p1_speculative_child (io_brupdate_b2_uop_iw_p1_speculative_child_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iw_p2_speculative_child (io_brupdate_b2_uop_iw_p2_speculative_child_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iw_p1_bypass_hint (io_brupdate_b2_uop_iw_p1_bypass_hint_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iw_p2_bypass_hint (io_brupdate_b2_uop_iw_p2_bypass_hint_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iw_p3_bypass_hint (io_brupdate_b2_uop_iw_p3_bypass_hint_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_dis_col_sel (io_brupdate_b2_uop_dis_col_sel_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_br_mask (io_brupdate_b2_uop_br_mask_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_br_tag (io_brupdate_b2_uop_br_tag_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_br_type (io_brupdate_b2_uop_br_type_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_sfb (io_brupdate_b2_uop_is_sfb_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_fence (io_brupdate_b2_uop_is_fence_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_fencei (io_brupdate_b2_uop_is_fencei_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_sfence (io_brupdate_b2_uop_is_sfence_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_amo (io_brupdate_b2_uop_is_amo_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_eret (io_brupdate_b2_uop_is_eret_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_sys_pc2epc (io_brupdate_b2_uop_is_sys_pc2epc_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_rocc (io_brupdate_b2_uop_is_rocc_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_mov (io_brupdate_b2_uop_is_mov_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_ftq_idx (io_brupdate_b2_uop_ftq_idx_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_edge_inst (io_brupdate_b2_uop_edge_inst_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_pc_lob (io_brupdate_b2_uop_pc_lob_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_taken (io_brupdate_b2_uop_taken_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_imm_rename (io_brupdate_b2_uop_imm_rename_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_imm_sel (io_brupdate_b2_uop_imm_sel_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_pimm (io_brupdate_b2_uop_pimm_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_imm_packed (io_brupdate_b2_uop_imm_packed_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_op1_sel (io_brupdate_b2_uop_op1_sel_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_op2_sel (io_brupdate_b2_uop_op2_sel_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_ldst (io_brupdate_b2_uop_fp_ctrl_ldst_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_wen (io_brupdate_b2_uop_fp_ctrl_wen_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_ren1 (io_brupdate_b2_uop_fp_ctrl_ren1_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_ren2 (io_brupdate_b2_uop_fp_ctrl_ren2_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_ren3 (io_brupdate_b2_uop_fp_ctrl_ren3_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_swap12 (io_brupdate_b2_uop_fp_ctrl_swap12_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_swap23 (io_brupdate_b2_uop_fp_ctrl_swap23_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_typeTagIn (io_brupdate_b2_uop_fp_ctrl_typeTagIn_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_typeTagOut (io_brupdate_b2_uop_fp_ctrl_typeTagOut_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_fromint (io_brupdate_b2_uop_fp_ctrl_fromint_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_toint (io_brupdate_b2_uop_fp_ctrl_toint_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_fastpipe (io_brupdate_b2_uop_fp_ctrl_fastpipe_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_fma (io_brupdate_b2_uop_fp_ctrl_fma_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_div (io_brupdate_b2_uop_fp_ctrl_div_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_sqrt (io_brupdate_b2_uop_fp_ctrl_sqrt_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_wflags (io_brupdate_b2_uop_fp_ctrl_wflags_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_vec (io_brupdate_b2_uop_fp_ctrl_vec_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_rob_idx (io_brupdate_b2_uop_rob_idx_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_ldq_idx (io_brupdate_b2_uop_ldq_idx_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_stq_idx (io_brupdate_b2_uop_stq_idx_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_rxq_idx (io_brupdate_b2_uop_rxq_idx_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_pdst (io_brupdate_b2_uop_pdst_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_prs1 (io_brupdate_b2_uop_prs1_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_prs2 (io_brupdate_b2_uop_prs2_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_prs3 (io_brupdate_b2_uop_prs3_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_ppred (io_brupdate_b2_uop_ppred_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_prs1_busy (io_brupdate_b2_uop_prs1_busy_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_prs2_busy (io_brupdate_b2_uop_prs2_busy_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_prs3_busy (io_brupdate_b2_uop_prs3_busy_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_ppred_busy (io_brupdate_b2_uop_ppred_busy_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_stale_pdst (io_brupdate_b2_uop_stale_pdst_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_exception (io_brupdate_b2_uop_exception_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_exc_cause (io_brupdate_b2_uop_exc_cause_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_mem_cmd (io_brupdate_b2_uop_mem_cmd_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_mem_size (io_brupdate_b2_uop_mem_size_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_mem_signed (io_brupdate_b2_uop_mem_signed_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_uses_ldq (io_brupdate_b2_uop_uses_ldq_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_uses_stq (io_brupdate_b2_uop_uses_stq_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_unique (io_brupdate_b2_uop_is_unique_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_flush_on_commit (io_brupdate_b2_uop_flush_on_commit_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_csr_cmd (io_brupdate_b2_uop_csr_cmd_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_ldst_is_rs1 (io_brupdate_b2_uop_ldst_is_rs1_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_ldst (io_brupdate_b2_uop_ldst_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_lrs1 (io_brupdate_b2_uop_lrs1_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_lrs2 (io_brupdate_b2_uop_lrs2_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_lrs3 (io_brupdate_b2_uop_lrs3_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_dst_rtype (io_brupdate_b2_uop_dst_rtype_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_lrs1_rtype (io_brupdate_b2_uop_lrs1_rtype_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_lrs2_rtype (io_brupdate_b2_uop_lrs2_rtype_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_frs3_en (io_brupdate_b2_uop_frs3_en_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fcn_dw (io_brupdate_b2_uop_fcn_dw_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fcn_op (io_brupdate_b2_uop_fcn_op_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_val (io_brupdate_b2_uop_fp_val_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_rm (io_brupdate_b2_uop_fp_rm_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_typ (io_brupdate_b2_uop_fp_typ_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_xcpt_pf_if (io_brupdate_b2_uop_xcpt_pf_if_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_xcpt_ae_if (io_brupdate_b2_uop_xcpt_ae_if_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_xcpt_ma_if (io_brupdate_b2_uop_xcpt_ma_if_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_bp_debug_if (io_brupdate_b2_uop_bp_debug_if_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_bp_xcpt_if (io_brupdate_b2_uop_bp_xcpt_if_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_debug_fsrc (io_brupdate_b2_uop_debug_fsrc_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_debug_tsrc (io_brupdate_b2_uop_debug_tsrc_0), // @[util.scala:458:7]
.io_brupdate_b2_mispredict (io_brupdate_b2_mispredict_0), // @[util.scala:458:7]
.io_brupdate_b2_taken (io_brupdate_b2_taken_0), // @[util.scala:458:7]
.io_brupdate_b2_cfi_type (io_brupdate_b2_cfi_type_0), // @[util.scala:458:7]
.io_brupdate_b2_pc_sel (io_brupdate_b2_pc_sel_0), // @[util.scala:458:7]
.io_brupdate_b2_jalr_target (io_brupdate_b2_jalr_target_0), // @[util.scala:458:7]
.io_brupdate_b2_target_offset (io_brupdate_b2_target_offset_0), // @[util.scala:458:7]
.io_flush (io_flush_0), // @[util.scala:458:7]
.io_empty (_main_io_empty),
.io_count (_main_io_count)
); // @[util.scala:476:22]
assign out_uop_out_1_inst = _main_io_deq_bits_uop_inst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_inst = _main_io_deq_bits_uop_debug_inst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_rvc = _main_io_deq_bits_uop_is_rvc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_pc = _main_io_deq_bits_uop_debug_pc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_0 = _main_io_deq_bits_uop_iq_type_0; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_1 = _main_io_deq_bits_uop_iq_type_1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_2 = _main_io_deq_bits_uop_iq_type_2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_3 = _main_io_deq_bits_uop_iq_type_3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_0 = _main_io_deq_bits_uop_fu_code_0; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_1 = _main_io_deq_bits_uop_fu_code_1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_2 = _main_io_deq_bits_uop_fu_code_2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_3 = _main_io_deq_bits_uop_fu_code_3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_4 = _main_io_deq_bits_uop_fu_code_4; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_5 = _main_io_deq_bits_uop_fu_code_5; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_6 = _main_io_deq_bits_uop_fu_code_6; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_7 = _main_io_deq_bits_uop_fu_code_7; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_8 = _main_io_deq_bits_uop_fu_code_8; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_9 = _main_io_deq_bits_uop_fu_code_9; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_issued = _main_io_deq_bits_uop_iw_issued; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_issued_partial_agen = _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_issued_partial_dgen = _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p1_speculative_child = _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p2_speculative_child = _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p1_bypass_hint = _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p2_bypass_hint = _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p3_bypass_hint = _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_dis_col_sel = _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_br_tag = _main_io_deq_bits_uop_br_tag; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_br_type = _main_io_deq_bits_uop_br_type; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_sfb = _main_io_deq_bits_uop_is_sfb; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_fence = _main_io_deq_bits_uop_is_fence; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_fencei = _main_io_deq_bits_uop_is_fencei; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_sfence = _main_io_deq_bits_uop_is_sfence; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_amo = _main_io_deq_bits_uop_is_amo; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_eret = _main_io_deq_bits_uop_is_eret; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_sys_pc2epc = _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_rocc = _main_io_deq_bits_uop_is_rocc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_mov = _main_io_deq_bits_uop_is_mov; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ftq_idx = _main_io_deq_bits_uop_ftq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_edge_inst = _main_io_deq_bits_uop_edge_inst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_pc_lob = _main_io_deq_bits_uop_pc_lob; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_taken = _main_io_deq_bits_uop_taken; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_imm_rename = _main_io_deq_bits_uop_imm_rename; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_imm_sel = _main_io_deq_bits_uop_imm_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_pimm = _main_io_deq_bits_uop_pimm; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_imm_packed = _main_io_deq_bits_uop_imm_packed; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_op1_sel = _main_io_deq_bits_uop_op1_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_op2_sel = _main_io_deq_bits_uop_op2_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ldst = _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_wen = _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ren1 = _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ren2 = _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ren3 = _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_swap12 = _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_swap23 = _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_typeTagIn = _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_typeTagOut = _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_fromint = _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_toint = _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_fastpipe = _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_fma = _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_div = _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_sqrt = _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_wflags = _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_vec = _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_rob_idx = _main_io_deq_bits_uop_rob_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ldq_idx = _main_io_deq_bits_uop_ldq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_stq_idx = _main_io_deq_bits_uop_stq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_rxq_idx = _main_io_deq_bits_uop_rxq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_pdst = _main_io_deq_bits_uop_pdst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs1 = _main_io_deq_bits_uop_prs1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs2 = _main_io_deq_bits_uop_prs2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs3 = _main_io_deq_bits_uop_prs3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ppred = _main_io_deq_bits_uop_ppred; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs1_busy = _main_io_deq_bits_uop_prs1_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs2_busy = _main_io_deq_bits_uop_prs2_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs3_busy = _main_io_deq_bits_uop_prs3_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ppred_busy = _main_io_deq_bits_uop_ppred_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_stale_pdst = _main_io_deq_bits_uop_stale_pdst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_exception = _main_io_deq_bits_uop_exception; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_exc_cause = _main_io_deq_bits_uop_exc_cause; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_mem_cmd = _main_io_deq_bits_uop_mem_cmd; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_mem_size = _main_io_deq_bits_uop_mem_size; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_mem_signed = _main_io_deq_bits_uop_mem_signed; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_uses_ldq = _main_io_deq_bits_uop_uses_ldq; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_uses_stq = _main_io_deq_bits_uop_uses_stq; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_unique = _main_io_deq_bits_uop_is_unique; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_flush_on_commit = _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_csr_cmd = _main_io_deq_bits_uop_csr_cmd; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ldst_is_rs1 = _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ldst = _main_io_deq_bits_uop_ldst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs1 = _main_io_deq_bits_uop_lrs1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs2 = _main_io_deq_bits_uop_lrs2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs3 = _main_io_deq_bits_uop_lrs3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_dst_rtype = _main_io_deq_bits_uop_dst_rtype; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs1_rtype = _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs2_rtype = _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_frs3_en = _main_io_deq_bits_uop_frs3_en; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fcn_dw = _main_io_deq_bits_uop_fcn_dw; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fcn_op = _main_io_deq_bits_uop_fcn_op; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_val = _main_io_deq_bits_uop_fp_val; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_rm = _main_io_deq_bits_uop_fp_rm; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_typ = _main_io_deq_bits_uop_fp_typ; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_xcpt_pf_if = _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_xcpt_ae_if = _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_xcpt_ma_if = _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_bp_debug_if = _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_bp_xcpt_if = _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_fsrc = _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_tsrc = _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:104:23, :476:22]
assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7]
assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7]
assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7]
assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7]
assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7]
assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7]
assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7]
assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7]
assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7]
assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7]
assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7]
assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:458:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7]
assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:458:7]
assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:458:7]
assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7]
assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:458:7]
assign io_deq_bits_way_en = io_deq_bits_way_en_0; // @[util.scala:458:7]
assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:458:7]
assign io_empty = io_empty_0; // @[util.scala:458:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_126 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_147
connect io_out_source_extend.clock, clock
connect io_out_source_extend.reset, reset
connect io_out_source_extend.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_extend.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_126( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_147 io_out_source_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_39 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}}[4], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<2>}
regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock
wire next_valid : UInt<1>
connect next_valid, slot_valid
wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop_out, slot_uop
node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T)
connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1
wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop, next_uop_out
node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _killed_T_1 = neq(_killed_T, UInt<1>(0h0))
node killed = or(_killed_T_1, io.kill)
connect io.valid, slot_valid
connect io.out_uop, next_uop
node _io_will_be_valid_T = eq(killed, UInt<1>(0h0))
node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T)
connect io.will_be_valid, _io_will_be_valid_T_1
when io.kill :
connect slot_valid, UInt<1>(0h0)
else :
when io.in_uop.valid :
connect slot_valid, UInt<1>(0h1)
else :
when io.clear :
connect slot_valid, UInt<1>(0h0)
else :
node _slot_valid_T = eq(killed, UInt<1>(0h0))
node _slot_valid_T_1 = and(next_valid, _slot_valid_T)
connect slot_valid, _slot_valid_T_1
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T = eq(slot_valid, UInt<1>(0h0))
node _T_1 = or(_T, io.clear)
node _T_2 = or(_T_1, io.kill)
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid || io.clear || io.kill)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
else :
connect slot_uop, next_uop
connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p1_speculative_child, UInt<1>(0h0)
connect next_uop.iw_p2_speculative_child, UInt<1>(0h0)
wire rebusied_prs1 : UInt<1>
connect rebusied_prs1, UInt<1>(0h0)
wire rebusied_prs2 : UInt<1>
connect rebusied_prs2, UInt<1>(0h0)
node rebusied = or(rebusied_prs1, rebusied_prs2)
node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs1)
node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs2)
node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs3)
node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0)
node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1)
node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2)
node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3)
node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0)
node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1)
node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2)
node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3)
node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0)
node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1)
node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2)
node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3)
node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0)
node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1)
node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2)
node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3)
node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0)
node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1)
node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2)
node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3)
node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1)
node _T_7 = or(_T_6, prs1_wakeups_2)
node _T_8 = or(_T_7, prs1_wakeups_3)
when _T_8 :
connect next_uop.prs1_busy, UInt<1>(0h0)
node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_4 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1)
node _next_uop_iw_p1_speculative_child_T_5 = or(_next_uop_iw_p1_speculative_child_T_4, _next_uop_iw_p1_speculative_child_T_2)
node _next_uop_iw_p1_speculative_child_T_6 = or(_next_uop_iw_p1_speculative_child_T_5, _next_uop_iw_p1_speculative_child_T_3)
wire _next_uop_iw_p1_speculative_child_WIRE : UInt<2>
connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_6
connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE
node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_4 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1)
node _next_uop_iw_p1_bypass_hint_T_5 = or(_next_uop_iw_p1_bypass_hint_T_4, _next_uop_iw_p1_bypass_hint_T_2)
node _next_uop_iw_p1_bypass_hint_T_6 = or(_next_uop_iw_p1_bypass_hint_T_5, _next_uop_iw_p1_bypass_hint_T_3)
wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_6
connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE
node _T_9 = or(prs1_rebusys_0, prs1_rebusys_1)
node _T_10 = or(_T_9, prs1_rebusys_2)
node _T_11 = or(_T_10, prs1_rebusys_3)
node _T_12 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child)
node _T_13 = neq(_T_12, UInt<1>(0h0))
node _T_14 = or(_T_11, _T_13)
node _T_15 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0))
node _T_16 = and(_T_14, _T_15)
when _T_16 :
connect next_uop.prs1_busy, UInt<1>(0h1)
connect rebusied_prs1, UInt<1>(0h1)
node _T_17 = or(prs2_wakeups_0, prs2_wakeups_1)
node _T_18 = or(_T_17, prs2_wakeups_2)
node _T_19 = or(_T_18, prs2_wakeups_3)
when _T_19 :
connect next_uop.prs2_busy, UInt<1>(0h0)
node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_4 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1)
node _next_uop_iw_p2_speculative_child_T_5 = or(_next_uop_iw_p2_speculative_child_T_4, _next_uop_iw_p2_speculative_child_T_2)
node _next_uop_iw_p2_speculative_child_T_6 = or(_next_uop_iw_p2_speculative_child_T_5, _next_uop_iw_p2_speculative_child_T_3)
wire _next_uop_iw_p2_speculative_child_WIRE : UInt<2>
connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_6
connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE
node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_4 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1)
node _next_uop_iw_p2_bypass_hint_T_5 = or(_next_uop_iw_p2_bypass_hint_T_4, _next_uop_iw_p2_bypass_hint_T_2)
node _next_uop_iw_p2_bypass_hint_T_6 = or(_next_uop_iw_p2_bypass_hint_T_5, _next_uop_iw_p2_bypass_hint_T_3)
wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_6
connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE
node _T_20 = or(prs2_rebusys_0, prs2_rebusys_1)
node _T_21 = or(_T_20, prs2_rebusys_2)
node _T_22 = or(_T_21, prs2_rebusys_3)
node _T_23 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child)
node _T_24 = neq(_T_23, UInt<1>(0h0))
node _T_25 = or(_T_22, _T_24)
node _T_26 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0))
node _T_27 = and(_T_25, _T_26)
when _T_27 :
connect next_uop.prs2_busy, UInt<1>(0h1)
connect rebusied_prs2, UInt<1>(0h1)
node _T_28 = or(prs3_wakeups_0, prs3_wakeups_1)
node _T_29 = or(_T_28, prs3_wakeups_2)
node _T_30 = or(_T_29, prs3_wakeups_3)
when _T_30 :
connect next_uop.prs3_busy, UInt<1>(0h0)
node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_2 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_3 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_4 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1)
node _next_uop_iw_p3_bypass_hint_T_5 = or(_next_uop_iw_p3_bypass_hint_T_4, _next_uop_iw_p3_bypass_hint_T_2)
node _next_uop_iw_p3_bypass_hint_T_6 = or(_next_uop_iw_p3_bypass_hint_T_5, _next_uop_iw_p3_bypass_hint_T_3)
wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_6
connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE
node _T_31 = eq(io.pred_wakeup_port.bits, slot_uop.ppred)
node _T_32 = and(io.pred_wakeup_port.valid, _T_31)
when _T_32 :
connect next_uop.ppred_busy, UInt<1>(0h0)
node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1)
node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0))
node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4)
node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h0))
node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0))
node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7)
node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T)
node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0))
node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3)
node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0))
node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T)
node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0))
node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3)
node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0))
node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0))
node _io_request_T_1 = and(slot_valid, _io_request_T)
node _io_request_T_2 = or(iss_ready, agen_ready)
node _io_request_T_3 = or(_io_request_T_2, dgen_ready)
node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3)
connect io.request, _io_request_T_4
connect io.iss_uop, slot_uop
connect next_uop.iw_issued, UInt<1>(0h0)
connect next_uop.iw_issued_partial_agen, UInt<1>(0h0)
connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0)
node _T_33 = eq(io.squash_grant, UInt<1>(0h0))
node _T_34 = and(io.grant, _T_33)
when _T_34 :
connect next_uop.iw_issued, UInt<1>(0h1)
node _T_35 = and(slot_valid, slot_uop.iw_issued)
when _T_35 :
connect next_valid, rebusied | module IssueSlot_39( // @[issue-slot.scala:49:7]
input clock, // @[issue-slot.scala:49:7]
input reset, // @[issue-slot.scala:49:7]
output io_valid, // @[issue-slot.scala:52:14]
output io_will_be_valid, // @[issue-slot.scala:52:14]
output io_request, // @[issue-slot.scala:52:14]
input io_grant, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [11:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_amo, // @[issue-slot.scala:52:14]
output io_iss_uop_is_eret, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_iss_uop_taken, // @[issue-slot.scala:52:14]
output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14]
output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_iss_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14]
output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_iss_uop_is_unique, // @[issue-slot.scala:52:14]
output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_in_uop_valid, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:52:14]
input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:52:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [11:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_out_uop_is_fence, // @[issue-slot.scala:52:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_out_uop_is_amo, // @[issue-slot.scala:52:14]
output io_out_uop_is_eret, // @[issue-slot.scala:52:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_out_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_out_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_out_uop_taken, // @[issue-slot.scala:52:14]
output io_out_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_out_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_out_uop_is_unique, // @[issue-slot.scala:52:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_out_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14]
input io_kill, // @[issue-slot.scala:52:14]
input io_clear, // @[issue-slot.scala:52:14]
input io_squash_grant, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14]
input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14]
input [1:0] io_child_rebusys // @[issue-slot.scala:52:14]
);
wire [11:0] next_uop_out_br_mask; // @[util.scala:104:23]
wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7]
wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7]
wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7]
wire [1:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23]
wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23]
wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28]
wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91]
wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91]
wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131]
wire agen_ready = 1'h0; // @[issue-slot.scala:137:114]
wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114]
wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7]
wire [1:0] _next_uop_iw_p1_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p2_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73]
wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110]
wire [1:0] io_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-slot.scala:49:7]
wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34]
wire _io_request_T_4; // @[issue-slot.scala:140:51]
wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28]
wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28]
wire next_uop_is_rvc; // @[issue-slot.scala:59:28]
wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_0; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_1; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_2; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_0; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_1; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_2; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_4; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_5; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_6; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_7; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_8; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_9; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28]
wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28]
wire [11:0] next_uop_br_mask; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28]
wire next_uop_is_sfb; // @[issue-slot.scala:59:28]
wire next_uop_is_fence; // @[issue-slot.scala:59:28]
wire next_uop_is_fencei; // @[issue-slot.scala:59:28]
wire next_uop_is_sfence; // @[issue-slot.scala:59:28]
wire next_uop_is_amo; // @[issue-slot.scala:59:28]
wire next_uop_is_eret; // @[issue-slot.scala:59:28]
wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28]
wire next_uop_is_rocc; // @[issue-slot.scala:59:28]
wire next_uop_is_mov; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28]
wire next_uop_edge_inst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28]
wire next_uop_taken; // @[issue-slot.scala:59:28]
wire next_uop_imm_rename; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28]
wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_rob_idx; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_stq_idx; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28]
wire next_uop_prs1_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs2_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs3_busy; // @[issue-slot.scala:59:28]
wire next_uop_ppred_busy; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28]
wire next_uop_exception; // @[issue-slot.scala:59:28]
wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28]
wire next_uop_mem_signed; // @[issue-slot.scala:59:28]
wire next_uop_uses_ldq; // @[issue-slot.scala:59:28]
wire next_uop_uses_stq; // @[issue-slot.scala:59:28]
wire next_uop_is_unique; // @[issue-slot.scala:59:28]
wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28]
wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28]
wire next_uop_frs3_en; // @[issue-slot.scala:59:28]
wire next_uop_fcn_dw; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28]
wire next_uop_fp_val; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28]
wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [11:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [11:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_valid_0; // @[issue-slot.scala:49:7]
wire io_will_be_valid_0; // @[issue-slot.scala:49:7]
wire io_request_0; // @[issue-slot.scala:49:7]
reg slot_valid; // @[issue-slot.scala:55:27]
assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23]
reg slot_uop_is_rvc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21]
wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23]
reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23]
reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23]
reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23]
reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23]
reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23]
reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23]
reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23]
reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23]
reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23]
reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23]
reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23]
reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23]
reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23]
reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23]
reg slot_uop_iw_issued; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23]
reg [1:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23]
reg [1:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23]
reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [1:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23]
reg [11:0] slot_uop_br_mask; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23]
reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23]
reg slot_uop_is_sfb; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23]
reg slot_uop_is_fence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23]
reg slot_uop_is_fencei; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23]
reg slot_uop_is_sfence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23]
reg slot_uop_is_amo; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23]
reg slot_uop_is_eret; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23]
reg slot_uop_is_rocc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23]
reg slot_uop_is_mov; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23]
reg slot_uop_edge_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21]
assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23]
reg slot_uop_taken; // @[issue-slot.scala:56:21]
assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23]
reg slot_uop_imm_rename; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23]
reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23]
reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21]
assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21]
wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23]
reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23]
reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23]
reg [5:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23]
reg [3:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23]
reg [3:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23]
reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23]
reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23]
reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23]
reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23]
wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88]
wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95]
wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23]
reg slot_uop_exception; // @[issue-slot.scala:56:21]
assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21]
assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21]
wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23]
reg slot_uop_mem_signed; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23]
reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23]
reg slot_uop_uses_stq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23]
reg slot_uop_is_unique; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21]
assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23]
reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23]
reg slot_uop_frs3_en; // @[issue-slot.scala:56:21]
assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23]
reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23]
reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23]
reg slot_uop_fp_val; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23]
reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23]
wire next_valid; // @[issue-slot.scala:58:28]
assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23]
assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23]
assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23]
assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23]
assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23]
assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23]
assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23]
assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23]
assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23]
assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23]
assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23]
assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23]
assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23]
assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23]
assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23]
assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23]
assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23]
assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23]
wire [11:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25]
assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23]
assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23]
assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23]
assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23]
assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23]
assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23]
assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23]
assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23]
assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23]
assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23]
assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23]
assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23]
assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23]
assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23]
assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23]
assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23]
assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23]
assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23]
assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23]
assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23]
assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23]
assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23]
assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23]
assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23]
assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23]
assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23]
assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23]
assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23]
assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23]
assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23]
assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23]
assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23]
assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23]
assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23]
assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23]
assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23]
assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23]
assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23]
assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23]
assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23]
assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23]
assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23]
assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23]
assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23]
assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23]
assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23]
assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23]
assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23]
assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23]
assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23]
assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23]
assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23]
assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23]
assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23]
assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23]
assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23]
assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23]
assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23]
assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23]
assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23]
assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23]
assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23]
assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23]
assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23]
assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23]
assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23]
assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23]
wire [11:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}]
assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28]
wire [11:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51]
wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}]
wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61]
assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}]
assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34]
wire _slot_valid_T = ~killed; // @[util.scala:61:61]
wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}] |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_19 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_19( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module SinkD :
input clock : Clock
input reset : Reset
output io : { resp : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, source : UInt<4>, flip way : UInt<3>, flip set : UInt<10>, bs_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, bs_dat : { data : UInt<64>}, grant_req : { set : UInt<10>, way : UInt<3>}, flip grant_safe : UInt<1>}
inst d_q of Queue2_TLBundleD_a32d64s4k3z3c
connect d_q.clock, clock
connect d_q.reset, reset
connect d_q.io.enq.valid, io.d.valid
connect d_q.io.enq.bits.corrupt, io.d.bits.corrupt
connect d_q.io.enq.bits.data, io.d.bits.data
connect d_q.io.enq.bits.denied, io.d.bits.denied
connect d_q.io.enq.bits.sink, io.d.bits.sink
connect d_q.io.enq.bits.source, io.d.bits.source
connect d_q.io.enq.bits.size, io.d.bits.size
connect d_q.io.enq.bits.param, io.d.bits.param
connect d_q.io.enq.bits.opcode, io.d.bits.opcode
connect io.d.ready, d_q.io.enq.ready
node _T = and(d_q.io.deq.ready, d_q.io.deq.valid)
node _r_beats1_decode_T = dshl(UInt<6>(0h3f), d_q.io.deq.bits.size)
node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 5, 0)
node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1)
node r_beats1_decode = shr(_r_beats1_decode_T_2, 3)
node r_beats1_opdata = bits(d_q.io.deq.bits.opcode, 0, 0)
node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0))
regreset r_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _r_counter1_T = sub(r_counter, UInt<1>(0h1))
node r_counter1 = tail(_r_counter1_T, 1)
node first = eq(r_counter, UInt<1>(0h0))
node _r_last_T = eq(r_counter, UInt<1>(0h1))
node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0))
node last = or(_r_last_T, _r_last_T_1)
node r_3 = and(last, _T)
node _r_count_T = not(r_counter1)
node beat = and(r_beats1, _r_count_T)
when _T :
node _r_counter_T = mux(first, r_beats1, r_counter1)
connect r_counter, _r_counter_T
node hasData = bits(d_q.io.deq.bits.opcode, 0, 0)
reg io_source_r : UInt<4>, clock
when d_q.io.deq.valid :
connect io_source_r, d_q.io.deq.bits.source
node _io_source_T = mux(d_q.io.deq.valid, d_q.io.deq.bits.source, io_source_r)
connect io.source, _io_source_T
connect io.grant_req.way, io.way
connect io.grant_req.set, io.set
node _io_resp_valid_T = or(first, last)
node _io_resp_valid_T_1 = and(d_q.io.deq.ready, d_q.io.deq.valid)
node _io_resp_valid_T_2 = and(_io_resp_valid_T, _io_resp_valid_T_1)
connect io.resp.valid, _io_resp_valid_T_2
node _q_io_deq_ready_T = eq(first, UInt<1>(0h0))
node _q_io_deq_ready_T_1 = or(_q_io_deq_ready_T, io.grant_safe)
node _q_io_deq_ready_T_2 = and(io.bs_adr.ready, _q_io_deq_ready_T_1)
connect d_q.io.deq.ready, _q_io_deq_ready_T_2
node _io_bs_adr_valid_T = eq(first, UInt<1>(0h0))
node _io_bs_adr_valid_T_1 = and(d_q.io.deq.valid, io.grant_safe)
node _io_bs_adr_valid_T_2 = or(_io_bs_adr_valid_T, _io_bs_adr_valid_T_1)
connect io.bs_adr.valid, _io_bs_adr_valid_T_2
node _T_1 = and(d_q.io.deq.valid, first)
node _T_2 = eq(io.grant_safe, UInt<1>(0h0))
node _T_3 = and(_T_1, _T_2)
node _T_4 = eq(io.bs_adr.ready, UInt<1>(0h0))
node _T_5 = and(io.bs_adr.valid, _T_4)
connect io.resp.bits.last, last
connect io.resp.bits.opcode, d_q.io.deq.bits.opcode
connect io.resp.bits.param, d_q.io.deq.bits.param
connect io.resp.bits.source, d_q.io.deq.bits.source
connect io.resp.bits.sink, d_q.io.deq.bits.sink
connect io.resp.bits.denied, d_q.io.deq.bits.denied
node _io_bs_adr_bits_noop_T = eq(d_q.io.deq.valid, UInt<1>(0h0))
node _io_bs_adr_bits_noop_T_1 = eq(hasData, UInt<1>(0h0))
node _io_bs_adr_bits_noop_T_2 = or(_io_bs_adr_bits_noop_T, _io_bs_adr_bits_noop_T_1)
connect io.bs_adr.bits.noop, _io_bs_adr_bits_noop_T_2
connect io.bs_adr.bits.way, io.way
connect io.bs_adr.bits.set, io.set
node _io_bs_adr_bits_beat_T = add(beat, io.bs_adr.ready)
node _io_bs_adr_bits_beat_T_1 = tail(_io_bs_adr_bits_beat_T, 1)
reg io_bs_adr_bits_beat_r : UInt<3>, clock
when d_q.io.deq.valid :
connect io_bs_adr_bits_beat_r, _io_bs_adr_bits_beat_T_1
node _io_bs_adr_bits_beat_T_2 = mux(d_q.io.deq.valid, beat, io_bs_adr_bits_beat_r)
connect io.bs_adr.bits.beat, _io_bs_adr_bits_beat_T_2
node _io_bs_adr_bits_mask_T = not(UInt<1>(0h0))
connect io.bs_adr.bits.mask, _io_bs_adr_bits_mask_T
connect io.bs_dat.data, d_q.io.deq.bits.data
node _T_6 = and(d_q.io.deq.valid, d_q.io.deq.bits.corrupt)
node _T_7 = eq(d_q.io.deq.bits.denied, UInt<1>(0h0))
node _T_8 = and(_T_6, _T_7)
node _T_9 = eq(_T_8, UInt<1>(0h0))
node _T_10 = asUInt(reset)
node _T_11 = eq(_T_10, UInt<1>(0h0))
when _T_11 :
node _T_12 = eq(_T_9, UInt<1>(0h0))
when _T_12 :
printf(clock, UInt<1>(0h1), "Assertion failed: Data poisoning unsupported\n at SinkD.scala:82 assert (!(d.valid && d.bits.corrupt && !d.bits.denied), \"Data poisoning unsupported\")\n") : printf
assert(clock, _T_9, UInt<1>(0h1), "") : assert | module SinkD( // @[SinkD.scala:34:7]
input clock, // @[SinkD.scala:34:7]
input reset, // @[SinkD.scala:34:7]
output io_resp_valid, // @[SinkD.scala:36:14]
output io_resp_bits_last, // @[SinkD.scala:36:14]
output [2:0] io_resp_bits_opcode, // @[SinkD.scala:36:14]
output [2:0] io_resp_bits_param, // @[SinkD.scala:36:14]
output [3:0] io_resp_bits_source, // @[SinkD.scala:36:14]
output [2:0] io_resp_bits_sink, // @[SinkD.scala:36:14]
output io_resp_bits_denied, // @[SinkD.scala:36:14]
output io_d_ready, // @[SinkD.scala:36:14]
input io_d_valid, // @[SinkD.scala:36:14]
input [2:0] io_d_bits_opcode, // @[SinkD.scala:36:14]
input [1:0] io_d_bits_param, // @[SinkD.scala:36:14]
input [2:0] io_d_bits_size, // @[SinkD.scala:36:14]
input [3:0] io_d_bits_source, // @[SinkD.scala:36:14]
input [2:0] io_d_bits_sink, // @[SinkD.scala:36:14]
input io_d_bits_denied, // @[SinkD.scala:36:14]
input [63:0] io_d_bits_data, // @[SinkD.scala:36:14]
input io_d_bits_corrupt, // @[SinkD.scala:36:14]
output [3:0] io_source, // @[SinkD.scala:36:14]
input [2:0] io_way, // @[SinkD.scala:36:14]
input [9:0] io_set, // @[SinkD.scala:36:14]
input io_bs_adr_ready, // @[SinkD.scala:36:14]
output io_bs_adr_valid, // @[SinkD.scala:36:14]
output io_bs_adr_bits_noop, // @[SinkD.scala:36:14]
output [2:0] io_bs_adr_bits_way, // @[SinkD.scala:36:14]
output [9:0] io_bs_adr_bits_set, // @[SinkD.scala:36:14]
output [2:0] io_bs_adr_bits_beat, // @[SinkD.scala:36:14]
output [63:0] io_bs_dat_data, // @[SinkD.scala:36:14]
output [9:0] io_grant_req_set, // @[SinkD.scala:36:14]
output [2:0] io_grant_req_way, // @[SinkD.scala:36:14]
input io_grant_safe // @[SinkD.scala:36:14]
);
wire _d_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _d_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _d_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [3:0] _d_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire _d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire _d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire io_d_valid_0 = io_d_valid; // @[SinkD.scala:34:7]
wire [2:0] io_d_bits_opcode_0 = io_d_bits_opcode; // @[SinkD.scala:34:7]
wire [1:0] io_d_bits_param_0 = io_d_bits_param; // @[SinkD.scala:34:7]
wire [2:0] io_d_bits_size_0 = io_d_bits_size; // @[SinkD.scala:34:7]
wire [3:0] io_d_bits_source_0 = io_d_bits_source; // @[SinkD.scala:34:7]
wire [2:0] io_d_bits_sink_0 = io_d_bits_sink; // @[SinkD.scala:34:7]
wire io_d_bits_denied_0 = io_d_bits_denied; // @[SinkD.scala:34:7]
wire [63:0] io_d_bits_data_0 = io_d_bits_data; // @[SinkD.scala:34:7]
wire io_d_bits_corrupt_0 = io_d_bits_corrupt; // @[SinkD.scala:34:7]
wire [2:0] io_way_0 = io_way; // @[SinkD.scala:34:7]
wire [9:0] io_set_0 = io_set; // @[SinkD.scala:34:7]
wire io_bs_adr_ready_0 = io_bs_adr_ready; // @[SinkD.scala:34:7]
wire io_grant_safe_0 = io_grant_safe; // @[SinkD.scala:34:7]
wire io_bs_adr_bits_mask = 1'h1; // @[SinkD.scala:34:7]
wire _io_bs_adr_bits_mask_T = 1'h1; // @[SinkD.scala:79:26]
wire _io_resp_valid_T_2; // @[SinkD.scala:62:36]
wire last; // @[Edges.scala:232:33]
wire [3:0] _io_source_T; // @[SinkD.scala:57:19]
wire [2:0] io_bs_adr_bits_way_0 = io_way_0; // @[SinkD.scala:34:7]
wire [2:0] io_grant_req_way_0 = io_way_0; // @[SinkD.scala:34:7]
wire [9:0] io_bs_adr_bits_set_0 = io_set_0; // @[SinkD.scala:34:7]
wire [9:0] io_grant_req_set_0 = io_set_0; // @[SinkD.scala:34:7]
wire _io_bs_adr_valid_T_2; // @[SinkD.scala:64:29]
wire _io_bs_adr_bits_noop_T_2; // @[SinkD.scala:75:35]
wire [2:0] _io_bs_adr_bits_beat_T_2; // @[SinkD.scala:78:29]
wire io_resp_bits_last_0; // @[SinkD.scala:34:7]
wire [2:0] io_resp_bits_opcode_0; // @[SinkD.scala:34:7]
wire [2:0] io_resp_bits_param_0; // @[SinkD.scala:34:7]
wire [3:0] io_resp_bits_source_0; // @[SinkD.scala:34:7]
wire [2:0] io_resp_bits_sink_0; // @[SinkD.scala:34:7]
wire io_resp_bits_denied_0; // @[SinkD.scala:34:7]
wire io_resp_valid_0; // @[SinkD.scala:34:7]
wire io_d_ready_0; // @[SinkD.scala:34:7]
wire io_bs_adr_bits_noop_0; // @[SinkD.scala:34:7]
wire [2:0] io_bs_adr_bits_beat_0; // @[SinkD.scala:34:7]
wire io_bs_adr_valid_0; // @[SinkD.scala:34:7]
wire [63:0] io_bs_dat_data_0; // @[SinkD.scala:34:7]
wire [3:0] io_source_0; // @[SinkD.scala:34:7]
wire _q_io_deq_ready_T_2; // @[SinkD.scala:63:30]
wire _io_resp_valid_T_1 = _q_io_deq_ready_T_2 & _d_q_io_deq_valid; // @[Decoupled.scala:51:35, :362:21]
wire [12:0] _r_beats1_decode_T = 13'h3F << _d_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [5:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] r_beats1_decode = _r_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire r_beats1_opdata = _d_q_io_deq_bits_opcode[0]; // @[Decoupled.scala:362:21]
wire hasData = _d_q_io_deq_bits_opcode[0]; // @[Decoupled.scala:362:21]
wire [2:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] r_counter; // @[Edges.scala:229:27]
wire [3:0] _r_counter1_T = {1'h0, r_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] r_counter1 = _r_counter1_T[2:0]; // @[Edges.scala:230:28]
wire first = r_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _r_last_T = r_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _r_last_T_1 = r_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
assign last = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}]
assign io_resp_bits_last_0 = last; // @[Edges.scala:232:33]
wire r_3 = last & _io_resp_valid_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] beat = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _r_counter_T = first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [3:0] io_source_r; // @[SinkD.scala:57:53]
assign _io_source_T = _d_q_io_deq_valid ? _d_q_io_deq_bits_source : io_source_r; // @[Decoupled.scala:362:21]
assign io_source_0 = _io_source_T; // @[SinkD.scala:34:7, :57:19]
wire _io_resp_valid_T = first | last; // @[Edges.scala:231:25, :232:33]
assign _io_resp_valid_T_2 = _io_resp_valid_T & _io_resp_valid_T_1; // @[Decoupled.scala:51:35]
assign io_resp_valid_0 = _io_resp_valid_T_2; // @[SinkD.scala:34:7, :62:36]
wire _q_io_deq_ready_T = ~first; // @[Edges.scala:231:25]
wire _q_io_deq_ready_T_1 = _q_io_deq_ready_T | io_grant_safe_0; // @[SinkD.scala:34:7, :63:{34,41}]
assign _q_io_deq_ready_T_2 = io_bs_adr_ready_0 & _q_io_deq_ready_T_1; // @[SinkD.scala:34:7, :63:{30,41}]
wire _io_bs_adr_valid_T = ~first; // @[Edges.scala:231:25]
wire _io_bs_adr_valid_T_1 = _d_q_io_deq_valid & io_grant_safe_0; // @[Decoupled.scala:362:21]
assign _io_bs_adr_valid_T_2 = _io_bs_adr_valid_T | _io_bs_adr_valid_T_1; // @[SinkD.scala:64:{22,29,41}]
assign io_bs_adr_valid_0 = _io_bs_adr_valid_T_2; // @[SinkD.scala:34:7, :64:29]
assign io_resp_bits_param_0 = {1'h0, _d_q_io_deq_bits_param}; // @[Decoupled.scala:362:21]
wire _io_bs_adr_bits_noop_T = ~_d_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire _io_bs_adr_bits_noop_T_1 = ~hasData; // @[Edges.scala:106:36]
assign _io_bs_adr_bits_noop_T_2 = _io_bs_adr_bits_noop_T | _io_bs_adr_bits_noop_T_1; // @[SinkD.scala:75:{26,35,38}]
assign io_bs_adr_bits_noop_0 = _io_bs_adr_bits_noop_T_2; // @[SinkD.scala:34:7, :75:35]
wire [3:0] _io_bs_adr_bits_beat_T = {1'h0, beat} + {3'h0, io_bs_adr_ready_0}; // @[Edges.scala:234:25]
wire [2:0] _io_bs_adr_bits_beat_T_1 = _io_bs_adr_bits_beat_T[2:0]; // @[SinkD.scala:78:60]
reg [2:0] io_bs_adr_bits_beat_r; // @[SinkD.scala:78:54]
assign _io_bs_adr_bits_beat_T_2 = _d_q_io_deq_valid ? beat : io_bs_adr_bits_beat_r; // @[Decoupled.scala:362:21]
assign io_bs_adr_bits_beat_0 = _io_bs_adr_bits_beat_T_2; // @[SinkD.scala:34:7, :78:29] |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_3 :
output io : { flip in : UInt<65>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 63, 52)
node _rawIn_isZero_T = bits(rawIn_exp, 11, 9)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 11, 10)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 9, 9)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 9, 9)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 64, 64)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 51, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie11_is53_oe8_os24_1
node _roundAnyRawFNToRecFN_io_invalidExc_T = bits(rawIn.sig, 51, 51)
node _roundAnyRawFNToRecFN_io_invalidExc_T_1 = eq(_roundAnyRawFNToRecFN_io_invalidExc_T, UInt<1>(0h0))
node _roundAnyRawFNToRecFN_io_invalidExc_T_2 = and(rawIn.isNaN, _roundAnyRawFNToRecFN_io_invalidExc_T_1)
connect roundAnyRawFNToRecFN.io.invalidExc, _roundAnyRawFNToRecFN_io_invalidExc_T_2
connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundAnyRawFNToRecFN.io.in.sig, rawIn.sig
connect roundAnyRawFNToRecFN.io.in.sExp, rawIn.sExp
connect roundAnyRawFNToRecFN.io.in.sign, rawIn.sign
connect roundAnyRawFNToRecFN.io.in.isZero, rawIn.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, rawIn.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, rawIn.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module RecFNToRecFN_3( // @[RecFNToRecFN.scala:44:5]
input [64:0] io_in, // @[RecFNToRecFN.scala:48:16]
input [2:0] io_roundingMode, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out, // @[RecFNToRecFN.scala:48:16]
output [4:0] io_exceptionFlags // @[RecFNToRecFN.scala:48:16]
);
wire [64:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16, :72:19]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags_0; // @[RecFNToRecFN.scala:44:5]
wire [11:0] rawIn_exp = io_in_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _rawIn_out_sig_T_2 = io_in_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _roundAnyRawFNToRecFN_io_invalidExc_T = rawIn_sig[51]; // @[rawFloatFromRecFN.scala:55:23]
wire _roundAnyRawFNToRecFN_io_invalidExc_T_1 = ~_roundAnyRawFNToRecFN_io_invalidExc_T; // @[common.scala:82:{49,56}]
wire _roundAnyRawFNToRecFN_io_invalidExc_T_2 = rawIn_isNaN & _roundAnyRawFNToRecFN_io_invalidExc_T_1; // @[rawFloatFromRecFN.scala:55:23]
RoundAnyRawFNToRecFN_ie11_is53_oe8_os24_1 roundAnyRawFNToRecFN ( // @[RecFNToRecFN.scala:72:19]
.io_invalidExc (_roundAnyRawFNToRecFN_io_invalidExc_T_2), // @[common.scala:82:46]
.io_in_isNaN (rawIn_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_in_isInf (rawIn_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_in_isZero (rawIn_isZero_0), // @[rawFloatFromRecFN.scala:55:23]
.io_in_sign (rawIn_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_in_sExp (rawIn_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_in_sig (rawIn_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_roundingMode (io_roundingMode_0), // @[RecFNToRecFN.scala:44:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RecFNToRecFN.scala:72:19]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ResetCatchAndSync_d3_6 :
input clock : Clock
input reset : Reset
output io : { sync_reset : UInt<1>, flip psd : { test_mode : UInt<1>, test_mode_reset : UInt<1>}}
node _post_psd_reset_T = asUInt(reset)
node post_psd_reset = mux(io.psd.test_mode, io.psd.test_mode_reset, _post_psd_reset_T)
inst io_sync_reset_chain of AsyncResetSynchronizerShiftReg_w1_d3_i0_207
connect io_sync_reset_chain.clock, clock
connect io_sync_reset_chain.reset, post_psd_reset
connect io_sync_reset_chain.io.d, UInt<1>(0h1)
wire _io_sync_reset_WIRE : UInt<1>
connect _io_sync_reset_WIRE, io_sync_reset_chain.io.q
node _io_sync_reset_T = not(_io_sync_reset_WIRE)
node _io_sync_reset_T_1 = mux(io.psd.test_mode, io.psd.test_mode_reset, _io_sync_reset_T)
connect io.sync_reset, _io_sync_reset_T_1 | module ResetCatchAndSync_d3_6( // @[ResetCatchAndSync.scala:13:7]
input clock, // @[ResetCatchAndSync.scala:13:7]
input reset, // @[ResetCatchAndSync.scala:13:7]
output io_sync_reset // @[ResetCatchAndSync.scala:17:14]
);
wire _post_psd_reset_T = reset; // @[ResetCatchAndSync.scala:26:76]
wire io_psd_test_mode = 1'h0; // @[ResetCatchAndSync.scala:13:7, :17:14]
wire io_psd_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:13:7, :17:14]
wire _io_sync_reset_T_1; // @[ResetCatchAndSync.scala:28:25]
wire io_sync_reset_0; // @[ResetCatchAndSync.scala:13:7]
wire post_psd_reset = _post_psd_reset_T; // @[ResetCatchAndSync.scala:26:{27,76}]
wire _io_sync_reset_WIRE; // @[ShiftReg.scala:48:24]
wire _io_sync_reset_T = ~_io_sync_reset_WIRE; // @[ShiftReg.scala:48:24]
assign _io_sync_reset_T_1 = _io_sync_reset_T; // @[ResetCatchAndSync.scala:28:25, :29:7]
assign io_sync_reset_0 = _io_sync_reset_T_1; // @[ResetCatchAndSync.scala:13:7, :28:25]
AsyncResetSynchronizerShiftReg_w1_d3_i0_207 io_sync_reset_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (post_psd_reset), // @[ResetCatchAndSync.scala:26:27]
.io_q (_io_sync_reset_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_sync_reset = io_sync_reset_0; // @[ResetCatchAndSync.scala:13:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_79 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2))
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_lo = cat(mask_acc_1, mask_acc)
node mask_hi = cat(mask_acc_3, mask_acc_2)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_17 = and(UInt<1>(0h0), _T_16)
node _T_18 = or(UInt<1>(0h0), _T_17)
node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_21 = cvt(_T_20)
node _T_22 = and(_T_21, asSInt(UInt<7>(0h40)))
node _T_23 = asSInt(_T_22)
node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0)))
node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_26 = cvt(_T_25)
node _T_27 = and(_T_26, asSInt(UInt<5>(0h14)))
node _T_28 = asSInt(_T_27)
node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0)))
node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_31 = cvt(_T_30)
node _T_32 = and(_T_31, asSInt(UInt<4>(0h8)))
node _T_33 = asSInt(_T_32)
node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_36 = cvt(_T_35)
node _T_37 = and(_T_36, asSInt(UInt<6>(0h20)))
node _T_38 = asSInt(_T_37)
node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0)))
node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_41 = cvt(_T_40)
node _T_42 = and(_T_41, asSInt(UInt<8>(0h80)))
node _T_43 = asSInt(_T_42)
node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0)))
node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<9>(0h100)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_24, _T_29)
node _T_51 = or(_T_50, _T_34)
node _T_52 = or(_T_51, _T_39)
node _T_53 = or(_T_52, _T_44)
node _T_54 = or(_T_53, _T_49)
node _T_55 = and(_T_19, _T_54)
node _T_56 = or(UInt<1>(0h0), _T_55)
node _T_57 = and(_T_18, _T_56)
node _T_58 = asUInt(reset)
node _T_59 = eq(_T_58, UInt<1>(0h0))
when _T_59 :
node _T_60 = eq(_T_57, UInt<1>(0h0))
when _T_60 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_57, UInt<1>(0h1), "") : assert_2
node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_63 = and(_T_61, _T_62)
node _T_64 = or(UInt<1>(0h0), _T_63)
node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_66 = cvt(_T_65)
node _T_67 = and(_T_66, asSInt(UInt<7>(0h40)))
node _T_68 = asSInt(_T_67)
node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0)))
node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_71 = cvt(_T_70)
node _T_72 = and(_T_71, asSInt(UInt<5>(0h14)))
node _T_73 = asSInt(_T_72)
node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0)))
node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_76 = cvt(_T_75)
node _T_77 = and(_T_76, asSInt(UInt<4>(0h8)))
node _T_78 = asSInt(_T_77)
node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0)))
node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_81 = cvt(_T_80)
node _T_82 = and(_T_81, asSInt(UInt<6>(0h20)))
node _T_83 = asSInt(_T_82)
node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_86 = cvt(_T_85)
node _T_87 = and(_T_86, asSInt(UInt<8>(0h80)))
node _T_88 = asSInt(_T_87)
node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<9>(0h100)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_69, _T_74)
node _T_96 = or(_T_95, _T_79)
node _T_97 = or(_T_96, _T_84)
node _T_98 = or(_T_97, _T_89)
node _T_99 = or(_T_98, _T_94)
node _T_100 = and(_T_64, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(UInt<1>(0h0), _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_102, UInt<1>(0h1), "") : assert_3
node _T_106 = asUInt(reset)
node _T_107 = eq(_T_106, UInt<1>(0h0))
when _T_107 :
node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_110 = asUInt(reset)
node _T_111 = eq(_T_110, UInt<1>(0h0))
when _T_111 :
node _T_112 = eq(_T_109, UInt<1>(0h0))
when _T_112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_109, UInt<1>(0h1), "") : assert_5
node _T_113 = asUInt(reset)
node _T_114 = eq(_T_113, UInt<1>(0h0))
when _T_114 :
node _T_115 = eq(is_aligned, UInt<1>(0h0))
when _T_115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_117 = asUInt(reset)
node _T_118 = eq(_T_117, UInt<1>(0h0))
when _T_118 :
node _T_119 = eq(_T_116, UInt<1>(0h0))
when _T_119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_116, UInt<1>(0h1), "") : assert_7
node _T_120 = not(io.in.a.bits.mask)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_121, UInt<1>(0h1), "") : assert_8
node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_126 = asUInt(reset)
node _T_127 = eq(_T_126, UInt<1>(0h0))
when _T_127 :
node _T_128 = eq(_T_125, UInt<1>(0h0))
when _T_128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_125, UInt<1>(0h1), "") : assert_9
node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_129 :
node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_131 = and(UInt<1>(0h0), _T_130)
node _T_132 = or(UInt<1>(0h0), _T_131)
node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_135 = cvt(_T_134)
node _T_136 = and(_T_135, asSInt(UInt<7>(0h40)))
node _T_137 = asSInt(_T_136)
node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0)))
node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_140 = cvt(_T_139)
node _T_141 = and(_T_140, asSInt(UInt<5>(0h14)))
node _T_142 = asSInt(_T_141)
node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0)))
node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_145 = cvt(_T_144)
node _T_146 = and(_T_145, asSInt(UInt<4>(0h8)))
node _T_147 = asSInt(_T_146)
node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_150 = cvt(_T_149)
node _T_151 = and(_T_150, asSInt(UInt<6>(0h20)))
node _T_152 = asSInt(_T_151)
node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0)))
node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<8>(0h80)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_160 = cvt(_T_159)
node _T_161 = and(_T_160, asSInt(UInt<9>(0h100)))
node _T_162 = asSInt(_T_161)
node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0)))
node _T_164 = or(_T_138, _T_143)
node _T_165 = or(_T_164, _T_148)
node _T_166 = or(_T_165, _T_153)
node _T_167 = or(_T_166, _T_158)
node _T_168 = or(_T_167, _T_163)
node _T_169 = and(_T_133, _T_168)
node _T_170 = or(UInt<1>(0h0), _T_169)
node _T_171 = and(_T_132, _T_170)
node _T_172 = asUInt(reset)
node _T_173 = eq(_T_172, UInt<1>(0h0))
when _T_173 :
node _T_174 = eq(_T_171, UInt<1>(0h0))
when _T_174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_171, UInt<1>(0h1), "") : assert_10
node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_177 = and(_T_175, _T_176)
node _T_178 = or(UInt<1>(0h0), _T_177)
node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_180 = cvt(_T_179)
node _T_181 = and(_T_180, asSInt(UInt<7>(0h40)))
node _T_182 = asSInt(_T_181)
node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0)))
node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_185 = cvt(_T_184)
node _T_186 = and(_T_185, asSInt(UInt<5>(0h14)))
node _T_187 = asSInt(_T_186)
node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_190 = cvt(_T_189)
node _T_191 = and(_T_190, asSInt(UInt<4>(0h8)))
node _T_192 = asSInt(_T_191)
node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0)))
node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<6>(0h20)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_200 = cvt(_T_199)
node _T_201 = and(_T_200, asSInt(UInt<8>(0h80)))
node _T_202 = asSInt(_T_201)
node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0)))
node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_205 = cvt(_T_204)
node _T_206 = and(_T_205, asSInt(UInt<9>(0h100)))
node _T_207 = asSInt(_T_206)
node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0)))
node _T_209 = or(_T_183, _T_188)
node _T_210 = or(_T_209, _T_193)
node _T_211 = or(_T_210, _T_198)
node _T_212 = or(_T_211, _T_203)
node _T_213 = or(_T_212, _T_208)
node _T_214 = and(_T_178, _T_213)
node _T_215 = or(UInt<1>(0h0), _T_214)
node _T_216 = and(UInt<1>(0h0), _T_215)
node _T_217 = asUInt(reset)
node _T_218 = eq(_T_217, UInt<1>(0h0))
when _T_218 :
node _T_219 = eq(_T_216, UInt<1>(0h0))
when _T_219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_216, UInt<1>(0h1), "") : assert_11
node _T_220 = asUInt(reset)
node _T_221 = eq(_T_220, UInt<1>(0h0))
when _T_221 :
node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_224 = asUInt(reset)
node _T_225 = eq(_T_224, UInt<1>(0h0))
when _T_225 :
node _T_226 = eq(_T_223, UInt<1>(0h0))
when _T_226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_223, UInt<1>(0h1), "") : assert_13
node _T_227 = asUInt(reset)
node _T_228 = eq(_T_227, UInt<1>(0h0))
when _T_228 :
node _T_229 = eq(is_aligned, UInt<1>(0h0))
when _T_229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_231 = asUInt(reset)
node _T_232 = eq(_T_231, UInt<1>(0h0))
when _T_232 :
node _T_233 = eq(_T_230, UInt<1>(0h0))
when _T_233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_230, UInt<1>(0h1), "") : assert_15
node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_235 = asUInt(reset)
node _T_236 = eq(_T_235, UInt<1>(0h0))
when _T_236 :
node _T_237 = eq(_T_234, UInt<1>(0h0))
when _T_237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_234, UInt<1>(0h1), "") : assert_16
node _T_238 = not(io.in.a.bits.mask)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_239, UInt<1>(0h1), "") : assert_17
node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_244 = asUInt(reset)
node _T_245 = eq(_T_244, UInt<1>(0h0))
when _T_245 :
node _T_246 = eq(_T_243, UInt<1>(0h0))
when _T_246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_243, UInt<1>(0h1), "") : assert_18
node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_247 :
node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = asUInt(reset)
node _T_253 = eq(_T_252, UInt<1>(0h0))
when _T_253 :
node _T_254 = eq(_T_251, UInt<1>(0h0))
when _T_254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_251, UInt<1>(0h1), "") : assert_19
node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_257 = and(_T_255, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_260 = cvt(_T_259)
node _T_261 = and(_T_260, asSInt(UInt<7>(0h40)))
node _T_262 = asSInt(_T_261)
node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0)))
node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_265 = cvt(_T_264)
node _T_266 = and(_T_265, asSInt(UInt<5>(0h14)))
node _T_267 = asSInt(_T_266)
node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0)))
node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_270 = cvt(_T_269)
node _T_271 = and(_T_270, asSInt(UInt<4>(0h8)))
node _T_272 = asSInt(_T_271)
node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0)))
node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_275 = cvt(_T_274)
node _T_276 = and(_T_275, asSInt(UInt<6>(0h20)))
node _T_277 = asSInt(_T_276)
node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0)))
node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_280 = cvt(_T_279)
node _T_281 = and(_T_280, asSInt(UInt<8>(0h80)))
node _T_282 = asSInt(_T_281)
node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0)))
node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_285 = cvt(_T_284)
node _T_286 = and(_T_285, asSInt(UInt<9>(0h100)))
node _T_287 = asSInt(_T_286)
node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0)))
node _T_289 = or(_T_263, _T_268)
node _T_290 = or(_T_289, _T_273)
node _T_291 = or(_T_290, _T_278)
node _T_292 = or(_T_291, _T_283)
node _T_293 = or(_T_292, _T_288)
node _T_294 = and(_T_258, _T_293)
node _T_295 = or(UInt<1>(0h0), _T_294)
node _T_296 = asUInt(reset)
node _T_297 = eq(_T_296, UInt<1>(0h0))
when _T_297 :
node _T_298 = eq(_T_295, UInt<1>(0h0))
when _T_298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_295, UInt<1>(0h1), "") : assert_20
node _T_299 = asUInt(reset)
node _T_300 = eq(_T_299, UInt<1>(0h0))
when _T_300 :
node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(is_aligned, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(_T_305, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_305, UInt<1>(0h1), "") : assert_23
node _T_309 = eq(io.in.a.bits.mask, mask)
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_309, UInt<1>(0h1), "") : assert_24
node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_313, UInt<1>(0h1), "") : assert_25
node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_320 = and(_T_318, _T_319)
node _T_321 = or(UInt<1>(0h0), _T_320)
node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_324 = and(_T_322, _T_323)
node _T_325 = or(UInt<1>(0h0), _T_324)
node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_327 = cvt(_T_326)
node _T_328 = and(_T_327, asSInt(UInt<7>(0h40)))
node _T_329 = asSInt(_T_328)
node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0)))
node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_332 = cvt(_T_331)
node _T_333 = and(_T_332, asSInt(UInt<5>(0h14)))
node _T_334 = asSInt(_T_333)
node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0)))
node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_337 = cvt(_T_336)
node _T_338 = and(_T_337, asSInt(UInt<4>(0h8)))
node _T_339 = asSInt(_T_338)
node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0)))
node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_342 = cvt(_T_341)
node _T_343 = and(_T_342, asSInt(UInt<6>(0h20)))
node _T_344 = asSInt(_T_343)
node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0)))
node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_347 = cvt(_T_346)
node _T_348 = and(_T_347, asSInt(UInt<8>(0h80)))
node _T_349 = asSInt(_T_348)
node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0)))
node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_352 = cvt(_T_351)
node _T_353 = and(_T_352, asSInt(UInt<9>(0h100)))
node _T_354 = asSInt(_T_353)
node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0)))
node _T_356 = or(_T_330, _T_335)
node _T_357 = or(_T_356, _T_340)
node _T_358 = or(_T_357, _T_345)
node _T_359 = or(_T_358, _T_350)
node _T_360 = or(_T_359, _T_355)
node _T_361 = and(_T_325, _T_360)
node _T_362 = or(UInt<1>(0h0), _T_361)
node _T_363 = and(_T_321, _T_362)
node _T_364 = asUInt(reset)
node _T_365 = eq(_T_364, UInt<1>(0h0))
when _T_365 :
node _T_366 = eq(_T_363, UInt<1>(0h0))
when _T_366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_363, UInt<1>(0h1), "") : assert_26
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(is_aligned, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_373, UInt<1>(0h1), "") : assert_29
node _T_377 = eq(io.in.a.bits.mask, mask)
node _T_378 = asUInt(reset)
node _T_379 = eq(_T_378, UInt<1>(0h0))
when _T_379 :
node _T_380 = eq(_T_377, UInt<1>(0h0))
when _T_380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_377, UInt<1>(0h1), "") : assert_30
node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_381 :
node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_383 = and(UInt<1>(0h0), _T_382)
node _T_384 = or(UInt<1>(0h0), _T_383)
node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_387 = and(_T_385, _T_386)
node _T_388 = or(UInt<1>(0h0), _T_387)
node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<7>(0h40)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_395 = cvt(_T_394)
node _T_396 = and(_T_395, asSInt(UInt<5>(0h14)))
node _T_397 = asSInt(_T_396)
node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0)))
node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<4>(0h8)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<6>(0h20)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<8>(0h80)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<9>(0h100)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = or(_T_393, _T_398)
node _T_420 = or(_T_419, _T_403)
node _T_421 = or(_T_420, _T_408)
node _T_422 = or(_T_421, _T_413)
node _T_423 = or(_T_422, _T_418)
node _T_424 = and(_T_388, _T_423)
node _T_425 = or(UInt<1>(0h0), _T_424)
node _T_426 = and(_T_384, _T_425)
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(_T_426, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_426, UInt<1>(0h1), "") : assert_31
node _T_430 = asUInt(reset)
node _T_431 = eq(_T_430, UInt<1>(0h0))
when _T_431 :
node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(is_aligned, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_436, UInt<1>(0h1), "") : assert_34
node _T_440 = not(mask)
node _T_441 = and(io.in.a.bits.mask, _T_440)
node _T_442 = eq(_T_441, UInt<1>(0h0))
node _T_443 = asUInt(reset)
node _T_444 = eq(_T_443, UInt<1>(0h0))
when _T_444 :
node _T_445 = eq(_T_442, UInt<1>(0h0))
when _T_445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_442, UInt<1>(0h1), "") : assert_35
node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_446 :
node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_448 = and(UInt<1>(0h0), _T_447)
node _T_449 = or(UInt<1>(0h0), _T_448)
node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_452 = cvt(_T_451)
node _T_453 = and(_T_452, asSInt(UInt<7>(0h40)))
node _T_454 = asSInt(_T_453)
node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0)))
node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_457 = cvt(_T_456)
node _T_458 = and(_T_457, asSInt(UInt<5>(0h14)))
node _T_459 = asSInt(_T_458)
node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0)))
node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_462 = cvt(_T_461)
node _T_463 = and(_T_462, asSInt(UInt<4>(0h8)))
node _T_464 = asSInt(_T_463)
node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0)))
node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_467 = cvt(_T_466)
node _T_468 = and(_T_467, asSInt(UInt<6>(0h20)))
node _T_469 = asSInt(_T_468)
node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0)))
node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_472 = cvt(_T_471)
node _T_473 = and(_T_472, asSInt(UInt<8>(0h80)))
node _T_474 = asSInt(_T_473)
node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0)))
node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_477 = cvt(_T_476)
node _T_478 = and(_T_477, asSInt(UInt<9>(0h100)))
node _T_479 = asSInt(_T_478)
node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0)))
node _T_481 = or(_T_455, _T_460)
node _T_482 = or(_T_481, _T_465)
node _T_483 = or(_T_482, _T_470)
node _T_484 = or(_T_483, _T_475)
node _T_485 = or(_T_484, _T_480)
node _T_486 = and(_T_450, _T_485)
node _T_487 = or(UInt<1>(0h0), _T_486)
node _T_488 = and(_T_449, _T_487)
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_488, UInt<1>(0h1), "") : assert_36
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_495 = asUInt(reset)
node _T_496 = eq(_T_495, UInt<1>(0h0))
when _T_496 :
node _T_497 = eq(is_aligned, UInt<1>(0h0))
when _T_497 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_499 = asUInt(reset)
node _T_500 = eq(_T_499, UInt<1>(0h0))
when _T_500 :
node _T_501 = eq(_T_498, UInt<1>(0h0))
when _T_501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_498, UInt<1>(0h1), "") : assert_39
node _T_502 = eq(io.in.a.bits.mask, mask)
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_502, UInt<1>(0h1), "") : assert_40
node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_506 :
node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_508 = and(UInt<1>(0h0), _T_507)
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_512 = cvt(_T_511)
node _T_513 = and(_T_512, asSInt(UInt<7>(0h40)))
node _T_514 = asSInt(_T_513)
node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0)))
node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_517 = cvt(_T_516)
node _T_518 = and(_T_517, asSInt(UInt<5>(0h14)))
node _T_519 = asSInt(_T_518)
node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0)))
node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_522 = cvt(_T_521)
node _T_523 = and(_T_522, asSInt(UInt<4>(0h8)))
node _T_524 = asSInt(_T_523)
node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0)))
node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_527 = cvt(_T_526)
node _T_528 = and(_T_527, asSInt(UInt<6>(0h20)))
node _T_529 = asSInt(_T_528)
node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0)))
node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_532 = cvt(_T_531)
node _T_533 = and(_T_532, asSInt(UInt<8>(0h80)))
node _T_534 = asSInt(_T_533)
node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0)))
node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_537 = cvt(_T_536)
node _T_538 = and(_T_537, asSInt(UInt<9>(0h100)))
node _T_539 = asSInt(_T_538)
node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0)))
node _T_541 = or(_T_515, _T_520)
node _T_542 = or(_T_541, _T_525)
node _T_543 = or(_T_542, _T_530)
node _T_544 = or(_T_543, _T_535)
node _T_545 = or(_T_544, _T_540)
node _T_546 = and(_T_510, _T_545)
node _T_547 = or(UInt<1>(0h0), _T_546)
node _T_548 = and(_T_509, _T_547)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_548, UInt<1>(0h1), "") : assert_41
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_555 = asUInt(reset)
node _T_556 = eq(_T_555, UInt<1>(0h0))
when _T_556 :
node _T_557 = eq(is_aligned, UInt<1>(0h0))
when _T_557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_559 = asUInt(reset)
node _T_560 = eq(_T_559, UInt<1>(0h0))
when _T_560 :
node _T_561 = eq(_T_558, UInt<1>(0h0))
when _T_561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_558, UInt<1>(0h1), "") : assert_44
node _T_562 = eq(io.in.a.bits.mask, mask)
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(_T_562, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_562, UInt<1>(0h1), "") : assert_45
node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_566 :
node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_568 = and(UInt<1>(0h0), _T_567)
node _T_569 = or(UInt<1>(0h0), _T_568)
node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_572 = cvt(_T_571)
node _T_573 = and(_T_572, asSInt(UInt<7>(0h40)))
node _T_574 = asSInt(_T_573)
node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0)))
node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_577 = cvt(_T_576)
node _T_578 = and(_T_577, asSInt(UInt<5>(0h14)))
node _T_579 = asSInt(_T_578)
node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0)))
node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_582 = cvt(_T_581)
node _T_583 = and(_T_582, asSInt(UInt<4>(0h8)))
node _T_584 = asSInt(_T_583)
node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0)))
node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_587 = cvt(_T_586)
node _T_588 = and(_T_587, asSInt(UInt<6>(0h20)))
node _T_589 = asSInt(_T_588)
node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0)))
node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_592 = cvt(_T_591)
node _T_593 = and(_T_592, asSInt(UInt<8>(0h80)))
node _T_594 = asSInt(_T_593)
node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0)))
node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_597 = cvt(_T_596)
node _T_598 = and(_T_597, asSInt(UInt<9>(0h100)))
node _T_599 = asSInt(_T_598)
node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0)))
node _T_601 = or(_T_575, _T_580)
node _T_602 = or(_T_601, _T_585)
node _T_603 = or(_T_602, _T_590)
node _T_604 = or(_T_603, _T_595)
node _T_605 = or(_T_604, _T_600)
node _T_606 = and(_T_570, _T_605)
node _T_607 = or(UInt<1>(0h0), _T_606)
node _T_608 = and(_T_569, _T_607)
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(_T_608, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_608, UInt<1>(0h1), "") : assert_46
node _T_612 = asUInt(reset)
node _T_613 = eq(_T_612, UInt<1>(0h0))
when _T_613 :
node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(is_aligned, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_619 = asUInt(reset)
node _T_620 = eq(_T_619, UInt<1>(0h0))
when _T_620 :
node _T_621 = eq(_T_618, UInt<1>(0h0))
when _T_621 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_618, UInt<1>(0h1), "") : assert_49
node _T_622 = eq(io.in.a.bits.mask, mask)
node _T_623 = asUInt(reset)
node _T_624 = eq(_T_623, UInt<1>(0h0))
when _T_624 :
node _T_625 = eq(_T_622, UInt<1>(0h0))
when _T_625 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_622, UInt<1>(0h1), "") : assert_50
node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_626, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_630, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_634 :
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(_T_638, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_638, UInt<1>(0h1), "") : assert_54
node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_642, UInt<1>(0h1), "") : assert_55
node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_647 = asUInt(reset)
node _T_648 = eq(_T_647, UInt<1>(0h0))
when _T_648 :
node _T_649 = eq(_T_646, UInt<1>(0h0))
when _T_649 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_646, UInt<1>(0h1), "") : assert_56
node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_651 = asUInt(reset)
node _T_652 = eq(_T_651, UInt<1>(0h0))
when _T_652 :
node _T_653 = eq(_T_650, UInt<1>(0h0))
when _T_653 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_650, UInt<1>(0h1), "") : assert_57
node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_654 :
node _T_655 = asUInt(reset)
node _T_656 = eq(_T_655, UInt<1>(0h0))
when _T_656 :
node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_658 = asUInt(reset)
node _T_659 = eq(_T_658, UInt<1>(0h0))
when _T_659 :
node _T_660 = eq(sink_ok, UInt<1>(0h0))
when _T_660 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_661, UInt<1>(0h1), "") : assert_60
node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_666 = asUInt(reset)
node _T_667 = eq(_T_666, UInt<1>(0h0))
when _T_667 :
node _T_668 = eq(_T_665, UInt<1>(0h0))
when _T_668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_665, UInt<1>(0h1), "") : assert_61
node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(_T_669, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_669, UInt<1>(0h1), "") : assert_62
node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_674 = asUInt(reset)
node _T_675 = eq(_T_674, UInt<1>(0h0))
when _T_675 :
node _T_676 = eq(_T_673, UInt<1>(0h0))
when _T_676 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_673, UInt<1>(0h1), "") : assert_63
node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_678 = or(UInt<1>(0h0), _T_677)
node _T_679 = asUInt(reset)
node _T_680 = eq(_T_679, UInt<1>(0h0))
when _T_680 :
node _T_681 = eq(_T_678, UInt<1>(0h0))
when _T_681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_678, UInt<1>(0h1), "") : assert_64
node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_682 :
node _T_683 = asUInt(reset)
node _T_684 = eq(_T_683, UInt<1>(0h0))
when _T_684 :
node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_685 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_686 = asUInt(reset)
node _T_687 = eq(_T_686, UInt<1>(0h0))
when _T_687 :
node _T_688 = eq(sink_ok, UInt<1>(0h0))
when _T_688 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_690 = asUInt(reset)
node _T_691 = eq(_T_690, UInt<1>(0h0))
when _T_691 :
node _T_692 = eq(_T_689, UInt<1>(0h0))
when _T_692 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_689, UInt<1>(0h1), "") : assert_67
node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_694 = asUInt(reset)
node _T_695 = eq(_T_694, UInt<1>(0h0))
when _T_695 :
node _T_696 = eq(_T_693, UInt<1>(0h0))
when _T_696 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_693, UInt<1>(0h1), "") : assert_68
node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_697, UInt<1>(0h1), "") : assert_69
node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_702 = or(_T_701, io.in.d.bits.corrupt)
node _T_703 = asUInt(reset)
node _T_704 = eq(_T_703, UInt<1>(0h0))
when _T_704 :
node _T_705 = eq(_T_702, UInt<1>(0h0))
when _T_705 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_702, UInt<1>(0h1), "") : assert_70
node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_707 = or(UInt<1>(0h0), _T_706)
node _T_708 = asUInt(reset)
node _T_709 = eq(_T_708, UInt<1>(0h0))
when _T_709 :
node _T_710 = eq(_T_707, UInt<1>(0h0))
when _T_710 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_707, UInt<1>(0h1), "") : assert_71
node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_711 :
node _T_712 = asUInt(reset)
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_714 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_716 = asUInt(reset)
node _T_717 = eq(_T_716, UInt<1>(0h0))
when _T_717 :
node _T_718 = eq(_T_715, UInt<1>(0h0))
when _T_718 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_715, UInt<1>(0h1), "") : assert_73
node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_719, UInt<1>(0h1), "") : assert_74
node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_724 = or(UInt<1>(0h0), _T_723)
node _T_725 = asUInt(reset)
node _T_726 = eq(_T_725, UInt<1>(0h0))
when _T_726 :
node _T_727 = eq(_T_724, UInt<1>(0h0))
when _T_727 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_724, UInt<1>(0h1), "") : assert_75
node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_728 :
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_733 = asUInt(reset)
node _T_734 = eq(_T_733, UInt<1>(0h0))
when _T_734 :
node _T_735 = eq(_T_732, UInt<1>(0h0))
when _T_735 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_732, UInt<1>(0h1), "") : assert_77
node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_737 = or(_T_736, io.in.d.bits.corrupt)
node _T_738 = asUInt(reset)
node _T_739 = eq(_T_738, UInt<1>(0h0))
when _T_739 :
node _T_740 = eq(_T_737, UInt<1>(0h0))
when _T_740 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_737, UInt<1>(0h1), "") : assert_78
node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_742 = or(UInt<1>(0h0), _T_741)
node _T_743 = asUInt(reset)
node _T_744 = eq(_T_743, UInt<1>(0h0))
when _T_744 :
node _T_745 = eq(_T_742, UInt<1>(0h0))
when _T_745 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_742, UInt<1>(0h1), "") : assert_79
node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_746 :
node _T_747 = asUInt(reset)
node _T_748 = eq(_T_747, UInt<1>(0h0))
when _T_748 :
node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_749 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_751 = asUInt(reset)
node _T_752 = eq(_T_751, UInt<1>(0h0))
when _T_752 :
node _T_753 = eq(_T_750, UInt<1>(0h0))
when _T_753 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_750, UInt<1>(0h1), "") : assert_81
node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_755 = asUInt(reset)
node _T_756 = eq(_T_755, UInt<1>(0h0))
when _T_756 :
node _T_757 = eq(_T_754, UInt<1>(0h0))
when _T_757 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_754, UInt<1>(0h1), "") : assert_82
node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_759 = or(UInt<1>(0h0), _T_758)
node _T_760 = asUInt(reset)
node _T_761 = eq(_T_760, UInt<1>(0h0))
when _T_761 :
node _T_762 = eq(_T_759, UInt<1>(0h0))
when _T_762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_759, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<9>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_764 = asUInt(reset)
node _T_765 = eq(_T_764, UInt<1>(0h0))
when _T_765 :
node _T_766 = eq(_T_763, UInt<1>(0h0))
when _T_766 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_763, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<9>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(_T_767, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_767, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_772 = asUInt(reset)
node _T_773 = eq(_T_772, UInt<1>(0h0))
when _T_773 :
node _T_774 = eq(_T_771, UInt<1>(0h0))
when _T_774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_771, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_775 = eq(a_first, UInt<1>(0h0))
node _T_776 = and(io.in.a.valid, _T_775)
when _T_776 :
node _T_777 = eq(io.in.a.bits.opcode, opcode)
node _T_778 = asUInt(reset)
node _T_779 = eq(_T_778, UInt<1>(0h0))
when _T_779 :
node _T_780 = eq(_T_777, UInt<1>(0h0))
when _T_780 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_777, UInt<1>(0h1), "") : assert_87
node _T_781 = eq(io.in.a.bits.param, param)
node _T_782 = asUInt(reset)
node _T_783 = eq(_T_782, UInt<1>(0h0))
when _T_783 :
node _T_784 = eq(_T_781, UInt<1>(0h0))
when _T_784 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_781, UInt<1>(0h1), "") : assert_88
node _T_785 = eq(io.in.a.bits.size, size)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_785, UInt<1>(0h1), "") : assert_89
node _T_789 = eq(io.in.a.bits.source, source)
node _T_790 = asUInt(reset)
node _T_791 = eq(_T_790, UInt<1>(0h0))
when _T_791 :
node _T_792 = eq(_T_789, UInt<1>(0h0))
when _T_792 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_789, UInt<1>(0h1), "") : assert_90
node _T_793 = eq(io.in.a.bits.address, address)
node _T_794 = asUInt(reset)
node _T_795 = eq(_T_794, UInt<1>(0h0))
when _T_795 :
node _T_796 = eq(_T_793, UInt<1>(0h0))
when _T_796 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_793, UInt<1>(0h1), "") : assert_91
node _T_797 = and(io.in.a.ready, io.in.a.valid)
node _T_798 = and(_T_797, a_first)
when _T_798 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_799 = eq(d_first, UInt<1>(0h0))
node _T_800 = and(io.in.d.valid, _T_799)
when _T_800 :
node _T_801 = eq(io.in.d.bits.opcode, opcode_1)
node _T_802 = asUInt(reset)
node _T_803 = eq(_T_802, UInt<1>(0h0))
when _T_803 :
node _T_804 = eq(_T_801, UInt<1>(0h0))
when _T_804 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_801, UInt<1>(0h1), "") : assert_92
node _T_805 = eq(io.in.d.bits.param, param_1)
node _T_806 = asUInt(reset)
node _T_807 = eq(_T_806, UInt<1>(0h0))
when _T_807 :
node _T_808 = eq(_T_805, UInt<1>(0h0))
when _T_808 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_805, UInt<1>(0h1), "") : assert_93
node _T_809 = eq(io.in.d.bits.size, size_1)
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(_T_809, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_809, UInt<1>(0h1), "") : assert_94
node _T_813 = eq(io.in.d.bits.source, source_1)
node _T_814 = asUInt(reset)
node _T_815 = eq(_T_814, UInt<1>(0h0))
when _T_815 :
node _T_816 = eq(_T_813, UInt<1>(0h0))
when _T_816 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_813, UInt<1>(0h1), "") : assert_95
node _T_817 = eq(io.in.d.bits.sink, sink)
node _T_818 = asUInt(reset)
node _T_819 = eq(_T_818, UInt<1>(0h0))
when _T_819 :
node _T_820 = eq(_T_817, UInt<1>(0h0))
when _T_820 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_817, UInt<1>(0h1), "") : assert_96
node _T_821 = eq(io.in.d.bits.denied, denied)
node _T_822 = asUInt(reset)
node _T_823 = eq(_T_822, UInt<1>(0h0))
when _T_823 :
node _T_824 = eq(_T_821, UInt<1>(0h0))
when _T_824 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_821, UInt<1>(0h1), "") : assert_97
node _T_825 = and(io.in.d.ready, io.in.d.valid)
node _T_826 = and(_T_825, d_first)
when _T_826 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<4>
connect a_sizes_set, UInt<4>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_827 = and(io.in.a.valid, a_first_1)
node _T_828 = and(_T_827, UInt<1>(0h1))
when _T_828 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_829 = and(io.in.a.ready, io.in.a.valid)
node _T_830 = and(_T_829, a_first_1)
node _T_831 = and(_T_830, UInt<1>(0h1))
when _T_831 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_832 = dshr(inflight, io.in.a.bits.source)
node _T_833 = bits(_T_832, 0, 0)
node _T_834 = eq(_T_833, UInt<1>(0h0))
node _T_835 = asUInt(reset)
node _T_836 = eq(_T_835, UInt<1>(0h0))
when _T_836 :
node _T_837 = eq(_T_834, UInt<1>(0h0))
when _T_837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_834, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<4>
connect d_sizes_clr, UInt<4>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_838 = and(io.in.d.valid, d_first_1)
node _T_839 = and(_T_838, UInt<1>(0h1))
node _T_840 = eq(d_release_ack, UInt<1>(0h0))
node _T_841 = and(_T_839, _T_840)
when _T_841 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_842 = and(io.in.d.ready, io.in.d.valid)
node _T_843 = and(_T_842, d_first_1)
node _T_844 = and(_T_843, UInt<1>(0h1))
node _T_845 = eq(d_release_ack, UInt<1>(0h0))
node _T_846 = and(_T_844, _T_845)
when _T_846 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_847 = and(io.in.d.valid, d_first_1)
node _T_848 = and(_T_847, UInt<1>(0h1))
node _T_849 = eq(d_release_ack, UInt<1>(0h0))
node _T_850 = and(_T_848, _T_849)
when _T_850 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_851 = dshr(inflight, io.in.d.bits.source)
node _T_852 = bits(_T_851, 0, 0)
node _T_853 = or(_T_852, same_cycle_resp)
node _T_854 = asUInt(reset)
node _T_855 = eq(_T_854, UInt<1>(0h0))
when _T_855 :
node _T_856 = eq(_T_853, UInt<1>(0h0))
when _T_856 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_853, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_859 = or(_T_857, _T_858)
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(_T_859, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_859, UInt<1>(0h1), "") : assert_100
node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_864 = asUInt(reset)
node _T_865 = eq(_T_864, UInt<1>(0h0))
when _T_865 :
node _T_866 = eq(_T_863, UInt<1>(0h0))
when _T_866 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_863, UInt<1>(0h1), "") : assert_101
else :
node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_869 = or(_T_867, _T_868)
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_869, UInt<1>(0h1), "") : assert_102
node _T_873 = eq(io.in.d.bits.size, a_size_lookup)
node _T_874 = asUInt(reset)
node _T_875 = eq(_T_874, UInt<1>(0h0))
when _T_875 :
node _T_876 = eq(_T_873, UInt<1>(0h0))
when _T_876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_873, UInt<1>(0h1), "") : assert_103
node _T_877 = and(io.in.d.valid, d_first_1)
node _T_878 = and(_T_877, a_first_1)
node _T_879 = and(_T_878, io.in.a.valid)
node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_881 = and(_T_879, _T_880)
node _T_882 = eq(d_release_ack, UInt<1>(0h0))
node _T_883 = and(_T_881, _T_882)
when _T_883 :
node _T_884 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_885 = or(_T_884, io.in.a.ready)
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(_T_885, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_885, UInt<1>(0h1), "") : assert_104
node _T_889 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_890 = orr(a_set_wo_ready)
node _T_891 = eq(_T_890, UInt<1>(0h0))
node _T_892 = or(_T_889, _T_891)
node _T_893 = asUInt(reset)
node _T_894 = eq(_T_893, UInt<1>(0h0))
when _T_894 :
node _T_895 = eq(_T_892, UInt<1>(0h0))
when _T_895 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_892, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_166
node _T_896 = orr(inflight)
node _T_897 = eq(_T_896, UInt<1>(0h0))
node _T_898 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_899 = or(_T_897, _T_898)
node _T_900 = lt(watchdog, plusarg_reader.out)
node _T_901 = or(_T_899, _T_900)
node _T_902 = asUInt(reset)
node _T_903 = eq(_T_902, UInt<1>(0h0))
when _T_903 :
node _T_904 = eq(_T_901, UInt<1>(0h0))
when _T_904 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_901, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_905 = and(io.in.a.ready, io.in.a.valid)
node _T_906 = and(io.in.d.ready, io.in.d.valid)
node _T_907 = or(_T_905, _T_906)
when _T_907 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<32>(0h0)
connect _c_first_WIRE.bits.address, UInt<9>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<4>
connect c_sizes_set, UInt<4>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.address, UInt<9>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_908 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<9>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_909 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_910 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_911 = and(_T_909, _T_910)
node _T_912 = and(_T_908, _T_911)
when _T_912 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<9>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_913 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_914 = and(_T_913, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<9>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_915 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_916 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_917 = and(_T_915, _T_916)
node _T_918 = and(_T_914, _T_917)
when _T_918 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<32>(0h0)
connect _WIRE_14.bits.address, UInt<9>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_919 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_920 = bits(_T_919, 0, 0)
node _T_921 = eq(_T_920, UInt<1>(0h0))
node _T_922 = asUInt(reset)
node _T_923 = eq(_T_922, UInt<1>(0h0))
when _T_923 :
node _T_924 = eq(_T_921, UInt<1>(0h0))
when _T_924 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_921, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<4>
connect d_sizes_clr_1, UInt<4>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_925 = and(io.in.d.valid, d_first_2)
node _T_926 = and(_T_925, UInt<1>(0h1))
node _T_927 = and(_T_926, d_release_ack_1)
when _T_927 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_928 = and(io.in.d.ready, io.in.d.valid)
node _T_929 = and(_T_928, d_first_2)
node _T_930 = and(_T_929, UInt<1>(0h1))
node _T_931 = and(_T_930, d_release_ack_1)
when _T_931 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_932 = and(io.in.d.valid, d_first_2)
node _T_933 = and(_T_932, UInt<1>(0h1))
node _T_934 = and(_T_933, d_release_ack_1)
when _T_934 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_935 = dshr(inflight_1, io.in.d.bits.source)
node _T_936 = bits(_T_935, 0, 0)
node _T_937 = or(_T_936, same_cycle_resp_1)
node _T_938 = asUInt(reset)
node _T_939 = eq(_T_938, UInt<1>(0h0))
when _T_939 :
node _T_940 = eq(_T_937, UInt<1>(0h0))
when _T_940 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_937, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<32>(0h0)
connect _WIRE_16.bits.address, UInt<9>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_941 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_942 = asUInt(reset)
node _T_943 = eq(_T_942, UInt<1>(0h0))
when _T_943 :
node _T_944 = eq(_T_941, UInt<1>(0h0))
when _T_944 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_941, UInt<1>(0h1), "") : assert_109
else :
node _T_945 = eq(io.in.d.bits.size, c_size_lookup)
node _T_946 = asUInt(reset)
node _T_947 = eq(_T_946, UInt<1>(0h0))
when _T_947 :
node _T_948 = eq(_T_945, UInt<1>(0h0))
when _T_948 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_945, UInt<1>(0h1), "") : assert_110
node _T_949 = and(io.in.d.valid, d_first_2)
node _T_950 = and(_T_949, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.address, UInt<9>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_951 = and(_T_950, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<9>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_952 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_953 = and(_T_951, _T_952)
node _T_954 = and(_T_953, d_release_ack_1)
node _T_955 = eq(c_probe_ack, UInt<1>(0h0))
node _T_956 = and(_T_954, _T_955)
when _T_956 :
node _T_957 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<32>(0h0)
connect _WIRE_22.bits.address, UInt<9>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_958 = or(_T_957, _WIRE_23.ready)
node _T_959 = asUInt(reset)
node _T_960 = eq(_T_959, UInt<1>(0h0))
when _T_960 :
node _T_961 = eq(_T_958, UInt<1>(0h0))
when _T_961 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_958, UInt<1>(0h1), "") : assert_111
node _T_962 = orr(c_set_wo_ready)
when _T_962 :
node _T_963 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_964 = asUInt(reset)
node _T_965 = eq(_T_964, UInt<1>(0h0))
when _T_965 :
node _T_966 = eq(_T_963, UInt<1>(0h0))
when _T_966 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_963, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_167
node _T_967 = orr(inflight_1)
node _T_968 = eq(_T_967, UInt<1>(0h0))
node _T_969 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_970 = or(_T_968, _T_969)
node _T_971 = lt(watchdog_1, plusarg_reader_1.out)
node _T_972 = or(_T_970, _T_971)
node _T_973 = asUInt(reset)
node _T_974 = eq(_T_973, UInt<1>(0h0))
when _T_974 :
node _T_975 = eq(_T_972, UInt<1>(0h0))
when _T_975 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_972, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.address, UInt<9>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_976 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_977 = and(io.in.d.ready, io.in.d.valid)
node _T_978 = or(_T_976, _T_977)
when _T_978 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_79( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [31:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49]
wire mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size = 1'h1; // @[Misc.scala:209:26]
wire mask_acc = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46]
wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46]
wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46]
wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7]
wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7]
wire [3:0] mask = 4'hF; // @[Misc.scala:222:10]
wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12]
wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27]
wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7]
wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire _T_905 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_905; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_905; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [8:0] address; // @[Monitor.scala:391:22]
wire _T_978 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_978; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_978; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_978; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71]
wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [3:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [3:0] _GEN_0 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69]
wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :641:65]
wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_0; // @[Monitor.scala:637:69, :680:101]
wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_0; // @[Monitor.scala:637:69, :681:99]
wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :749:69]
wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :750:67]
wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_0; // @[Monitor.scala:637:69, :790:101]
wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_0; // @[Monitor.scala:637:69, :791:99]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_828 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_828; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_828; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_905 & a_first_1; // @[Decoupled.scala:51:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]
assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46]
wire _T_877 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [1:0] _GEN_2 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_3 = 2'h1 << _GEN_2; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_3; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_3; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_3; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_877 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_846 = _T_978 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_846 & _d_clr_T[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_846 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [30:0] _d_sizes_clr_T_5 = 31'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_846 ? _d_sizes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_949 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_949 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35]
wire _T_931 = _T_978 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_931 & _d_clr_T_1[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_931 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [30:0] _d_sizes_clr_T_11 = 31'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_931 ? _d_sizes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_53 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<4>, q : UInt<4>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_465
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
node _output_T_2 = asAsyncReset(reset)
node _output_T_3 = bits(io.d, 1, 1)
inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_466
connect output_chain_1.clock, clock
connect output_chain_1.reset, _output_T_2
connect output_chain_1.io.d, _output_T_3
wire output_1 : UInt<1>
connect output_1, output_chain_1.io.q
node _output_T_4 = asAsyncReset(reset)
node _output_T_5 = bits(io.d, 2, 2)
inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_467
connect output_chain_2.clock, clock
connect output_chain_2.reset, _output_T_4
connect output_chain_2.io.d, _output_T_5
wire output_2 : UInt<1>
connect output_2, output_chain_2.io.q
node _output_T_6 = asAsyncReset(reset)
node _output_T_7 = bits(io.d, 3, 3)
inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_468
connect output_chain_3.clock, clock
connect output_chain_3.reset, _output_T_6
connect output_chain_3.io.d, _output_T_7
wire output_3 : UInt<1>
connect output_3, output_chain_3.io.q
node io_q_lo = cat(output_1, output_0)
node io_q_hi = cat(output_3, output_2)
node _io_q_T = cat(io_q_hi, io_q_lo)
connect io.q, _io_q_T | module AsyncResetSynchronizerShiftReg_w4_d3_i0_53( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_465 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_466 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_467 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_468 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_65 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_78
connect io_out_source_valid_1.clock, clock
connect io_out_source_valid_1.reset, reset
connect io_out_source_valid_1.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid_1.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_65( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_78 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_123 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_144
connect io_out_sink_valid.clock, clock
connect io_out_sink_valid.reset, reset
connect io_out_sink_valid.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_123( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_144 io_out_sink_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_53 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0)
node _source_ok_T = shr(io.in.a.bits.source, 4)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits = bits(_uncommonBits_T, 3, 0)
node _T_4 = shr(io.in.a.bits.source, 4)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<4>(0h9))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0)
node _T_24 = shr(io.in.a.bits.source, 4)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<4>(0h9))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h100c0)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<29>(0h100000c0)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = or(_T_37, _T_42)
node _T_44 = and(_T_32, _T_43)
node _T_45 = or(UInt<1>(0h0), _T_44)
node _T_46 = and(_T_31, _T_45)
node _T_47 = asUInt(reset)
node _T_48 = eq(_T_47, UInt<1>(0h0))
when _T_48 :
node _T_49 = eq(_T_46, UInt<1>(0h0))
when _T_49 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_46, UInt<1>(0h1), "") : assert_2
node _T_50 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_51 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_52 = and(_T_50, _T_51)
node _T_53 = or(UInt<1>(0h0), _T_52)
node _T_54 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_55 = cvt(_T_54)
node _T_56 = and(_T_55, asSInt(UInt<17>(0h100c0)))
node _T_57 = asSInt(_T_56)
node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0)))
node _T_59 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_60 = cvt(_T_59)
node _T_61 = and(_T_60, asSInt(UInt<29>(0h100000c0)))
node _T_62 = asSInt(_T_61)
node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0)))
node _T_64 = or(_T_58, _T_63)
node _T_65 = and(_T_53, _T_64)
node _T_66 = or(UInt<1>(0h0), _T_65)
node _T_67 = and(UInt<1>(0h0), _T_66)
node _T_68 = asUInt(reset)
node _T_69 = eq(_T_68, UInt<1>(0h0))
when _T_69 :
node _T_70 = eq(_T_67, UInt<1>(0h0))
when _T_70 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_67, UInt<1>(0h1), "") : assert_3
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_74 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_74, UInt<1>(0h1), "") : assert_5
node _T_78 = asUInt(reset)
node _T_79 = eq(_T_78, UInt<1>(0h0))
when _T_79 :
node _T_80 = eq(is_aligned, UInt<1>(0h0))
when _T_80 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_81 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_82 = asUInt(reset)
node _T_83 = eq(_T_82, UInt<1>(0h0))
when _T_83 :
node _T_84 = eq(_T_81, UInt<1>(0h0))
when _T_84 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_81, UInt<1>(0h1), "") : assert_7
node _T_85 = not(io.in.a.bits.mask)
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = asUInt(reset)
node _T_88 = eq(_T_87, UInt<1>(0h0))
when _T_88 :
node _T_89 = eq(_T_86, UInt<1>(0h0))
when _T_89 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_86, UInt<1>(0h1), "") : assert_8
node _T_90 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_91 = asUInt(reset)
node _T_92 = eq(_T_91, UInt<1>(0h0))
when _T_92 :
node _T_93 = eq(_T_90, UInt<1>(0h0))
when _T_93 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_90, UInt<1>(0h1), "") : assert_9
node _T_94 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_94 :
node _T_95 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_96 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_97 = and(_T_95, _T_96)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0)
node _T_98 = shr(io.in.a.bits.source, 4)
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_101 = and(_T_99, _T_100)
node _T_102 = leq(uncommonBits_2, UInt<4>(0h9))
node _T_103 = and(_T_101, _T_102)
node _T_104 = and(_T_97, _T_103)
node _T_105 = or(UInt<1>(0h0), _T_104)
node _T_106 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_107 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_108 = cvt(_T_107)
node _T_109 = and(_T_108, asSInt(UInt<17>(0h100c0)))
node _T_110 = asSInt(_T_109)
node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0)))
node _T_112 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_113 = cvt(_T_112)
node _T_114 = and(_T_113, asSInt(UInt<29>(0h100000c0)))
node _T_115 = asSInt(_T_114)
node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = or(_T_111, _T_116)
node _T_118 = and(_T_106, _T_117)
node _T_119 = or(UInt<1>(0h0), _T_118)
node _T_120 = and(_T_105, _T_119)
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_T_120, UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_120, UInt<1>(0h1), "") : assert_10
node _T_124 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_125 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_126 = and(_T_124, _T_125)
node _T_127 = or(UInt<1>(0h0), _T_126)
node _T_128 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_129 = cvt(_T_128)
node _T_130 = and(_T_129, asSInt(UInt<17>(0h100c0)))
node _T_131 = asSInt(_T_130)
node _T_132 = eq(_T_131, asSInt(UInt<1>(0h0)))
node _T_133 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_134 = cvt(_T_133)
node _T_135 = and(_T_134, asSInt(UInt<29>(0h100000c0)))
node _T_136 = asSInt(_T_135)
node _T_137 = eq(_T_136, asSInt(UInt<1>(0h0)))
node _T_138 = or(_T_132, _T_137)
node _T_139 = and(_T_127, _T_138)
node _T_140 = or(UInt<1>(0h0), _T_139)
node _T_141 = and(UInt<1>(0h0), _T_140)
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_141, UInt<1>(0h1), "") : assert_11
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_148 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_148, UInt<1>(0h1), "") : assert_13
node _T_152 = asUInt(reset)
node _T_153 = eq(_T_152, UInt<1>(0h0))
when _T_153 :
node _T_154 = eq(is_aligned, UInt<1>(0h0))
when _T_154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_155 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_155, UInt<1>(0h1), "") : assert_15
node _T_159 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_159, UInt<1>(0h1), "") : assert_16
node _T_163 = not(io.in.a.bits.mask)
node _T_164 = eq(_T_163, UInt<1>(0h0))
node _T_165 = asUInt(reset)
node _T_166 = eq(_T_165, UInt<1>(0h0))
when _T_166 :
node _T_167 = eq(_T_164, UInt<1>(0h0))
when _T_167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_164, UInt<1>(0h1), "") : assert_17
node _T_168 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_169 = asUInt(reset)
node _T_170 = eq(_T_169, UInt<1>(0h0))
when _T_170 :
node _T_171 = eq(_T_168, UInt<1>(0h0))
when _T_171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_168, UInt<1>(0h1), "") : assert_18
node _T_172 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_172 :
node _T_173 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_174 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_175 = and(_T_173, _T_174)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0)
node _T_176 = shr(io.in.a.bits.source, 4)
node _T_177 = eq(_T_176, UInt<1>(0h0))
node _T_178 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_179 = and(_T_177, _T_178)
node _T_180 = leq(uncommonBits_3, UInt<4>(0h9))
node _T_181 = and(_T_179, _T_180)
node _T_182 = and(_T_175, _T_181)
node _T_183 = or(UInt<1>(0h0), _T_182)
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_183, UInt<1>(0h1), "") : assert_19
node _T_187 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_188 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_189 = and(_T_187, _T_188)
node _T_190 = or(UInt<1>(0h0), _T_189)
node _T_191 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_192 = cvt(_T_191)
node _T_193 = and(_T_192, asSInt(UInt<17>(0h100c0)))
node _T_194 = asSInt(_T_193)
node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0)))
node _T_196 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_197 = cvt(_T_196)
node _T_198 = and(_T_197, asSInt(UInt<29>(0h100000c0)))
node _T_199 = asSInt(_T_198)
node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0)))
node _T_201 = or(_T_195, _T_200)
node _T_202 = and(_T_190, _T_201)
node _T_203 = or(UInt<1>(0h0), _T_202)
node _T_204 = asUInt(reset)
node _T_205 = eq(_T_204, UInt<1>(0h0))
when _T_205 :
node _T_206 = eq(_T_203, UInt<1>(0h0))
when _T_206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_203, UInt<1>(0h1), "") : assert_20
node _T_207 = asUInt(reset)
node _T_208 = eq(_T_207, UInt<1>(0h0))
when _T_208 :
node _T_209 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_210 = asUInt(reset)
node _T_211 = eq(_T_210, UInt<1>(0h0))
when _T_211 :
node _T_212 = eq(is_aligned, UInt<1>(0h0))
when _T_212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_213 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_214 = asUInt(reset)
node _T_215 = eq(_T_214, UInt<1>(0h0))
when _T_215 :
node _T_216 = eq(_T_213, UInt<1>(0h0))
when _T_216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_213, UInt<1>(0h1), "") : assert_23
node _T_217 = eq(io.in.a.bits.mask, mask)
node _T_218 = asUInt(reset)
node _T_219 = eq(_T_218, UInt<1>(0h0))
when _T_219 :
node _T_220 = eq(_T_217, UInt<1>(0h0))
when _T_220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_217, UInt<1>(0h1), "") : assert_24
node _T_221 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_T_221, UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_221, UInt<1>(0h1), "") : assert_25
node _T_225 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_225 :
node _T_226 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_227 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_228 = and(_T_226, _T_227)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0)
node _T_229 = shr(io.in.a.bits.source, 4)
node _T_230 = eq(_T_229, UInt<1>(0h0))
node _T_231 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_232 = and(_T_230, _T_231)
node _T_233 = leq(uncommonBits_4, UInt<4>(0h9))
node _T_234 = and(_T_232, _T_233)
node _T_235 = and(_T_228, _T_234)
node _T_236 = or(UInt<1>(0h0), _T_235)
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_239 = and(_T_237, _T_238)
node _T_240 = or(UInt<1>(0h0), _T_239)
node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<17>(0h100c0)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<29>(0h100000c0)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = or(_T_245, _T_250)
node _T_252 = and(_T_240, _T_251)
node _T_253 = or(UInt<1>(0h0), _T_252)
node _T_254 = and(_T_236, _T_253)
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_254, UInt<1>(0h1), "") : assert_26
node _T_258 = asUInt(reset)
node _T_259 = eq(_T_258, UInt<1>(0h0))
when _T_259 :
node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(is_aligned, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_264 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_265 = asUInt(reset)
node _T_266 = eq(_T_265, UInt<1>(0h0))
when _T_266 :
node _T_267 = eq(_T_264, UInt<1>(0h0))
when _T_267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_264, UInt<1>(0h1), "") : assert_29
node _T_268 = eq(io.in.a.bits.mask, mask)
node _T_269 = asUInt(reset)
node _T_270 = eq(_T_269, UInt<1>(0h0))
when _T_270 :
node _T_271 = eq(_T_268, UInt<1>(0h0))
when _T_271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_268, UInt<1>(0h1), "") : assert_30
node _T_272 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_272 :
node _T_273 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_274 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_275 = and(_T_273, _T_274)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0)
node _T_276 = shr(io.in.a.bits.source, 4)
node _T_277 = eq(_T_276, UInt<1>(0h0))
node _T_278 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_279 = and(_T_277, _T_278)
node _T_280 = leq(uncommonBits_5, UInt<4>(0h9))
node _T_281 = and(_T_279, _T_280)
node _T_282 = and(_T_275, _T_281)
node _T_283 = or(UInt<1>(0h0), _T_282)
node _T_284 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_285 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_286 = and(_T_284, _T_285)
node _T_287 = or(UInt<1>(0h0), _T_286)
node _T_288 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<17>(0h100c0)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<29>(0h100000c0)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = or(_T_292, _T_297)
node _T_299 = and(_T_287, _T_298)
node _T_300 = or(UInt<1>(0h0), _T_299)
node _T_301 = and(_T_283, _T_300)
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_301, UInt<1>(0h1), "") : assert_31
node _T_305 = asUInt(reset)
node _T_306 = eq(_T_305, UInt<1>(0h0))
when _T_306 :
node _T_307 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_307 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_308 = asUInt(reset)
node _T_309 = eq(_T_308, UInt<1>(0h0))
when _T_309 :
node _T_310 = eq(is_aligned, UInt<1>(0h0))
when _T_310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_311 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_312 = asUInt(reset)
node _T_313 = eq(_T_312, UInt<1>(0h0))
when _T_313 :
node _T_314 = eq(_T_311, UInt<1>(0h0))
when _T_314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_311, UInt<1>(0h1), "") : assert_34
node _T_315 = not(mask)
node _T_316 = and(io.in.a.bits.mask, _T_315)
node _T_317 = eq(_T_316, UInt<1>(0h0))
node _T_318 = asUInt(reset)
node _T_319 = eq(_T_318, UInt<1>(0h0))
when _T_319 :
node _T_320 = eq(_T_317, UInt<1>(0h0))
when _T_320 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_317, UInt<1>(0h1), "") : assert_35
node _T_321 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_321 :
node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_323 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_324 = and(_T_322, _T_323)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0)
node _T_325 = shr(io.in.a.bits.source, 4)
node _T_326 = eq(_T_325, UInt<1>(0h0))
node _T_327 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_328 = and(_T_326, _T_327)
node _T_329 = leq(uncommonBits_6, UInt<4>(0h9))
node _T_330 = and(_T_328, _T_329)
node _T_331 = and(_T_324, _T_330)
node _T_332 = or(UInt<1>(0h0), _T_331)
node _T_333 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_334 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_335 = cvt(_T_334)
node _T_336 = and(_T_335, asSInt(UInt<17>(0h100c0)))
node _T_337 = asSInt(_T_336)
node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0)))
node _T_339 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_340 = cvt(_T_339)
node _T_341 = and(_T_340, asSInt(UInt<29>(0h100000c0)))
node _T_342 = asSInt(_T_341)
node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0)))
node _T_344 = or(_T_338, _T_343)
node _T_345 = and(_T_333, _T_344)
node _T_346 = or(UInt<1>(0h0), _T_345)
node _T_347 = and(_T_332, _T_346)
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_347, UInt<1>(0h1), "") : assert_36
node _T_351 = asUInt(reset)
node _T_352 = eq(_T_351, UInt<1>(0h0))
when _T_352 :
node _T_353 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_354 = asUInt(reset)
node _T_355 = eq(_T_354, UInt<1>(0h0))
when _T_355 :
node _T_356 = eq(is_aligned, UInt<1>(0h0))
when _T_356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_357 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_358 = asUInt(reset)
node _T_359 = eq(_T_358, UInt<1>(0h0))
when _T_359 :
node _T_360 = eq(_T_357, UInt<1>(0h0))
when _T_360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_357, UInt<1>(0h1), "") : assert_39
node _T_361 = eq(io.in.a.bits.mask, mask)
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_361, UInt<1>(0h1), "") : assert_40
node _T_365 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_365 :
node _T_366 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_367 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_368 = and(_T_366, _T_367)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0)
node _T_369 = shr(io.in.a.bits.source, 4)
node _T_370 = eq(_T_369, UInt<1>(0h0))
node _T_371 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_372 = and(_T_370, _T_371)
node _T_373 = leq(uncommonBits_7, UInt<4>(0h9))
node _T_374 = and(_T_372, _T_373)
node _T_375 = and(_T_368, _T_374)
node _T_376 = or(UInt<1>(0h0), _T_375)
node _T_377 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_378 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_379 = cvt(_T_378)
node _T_380 = and(_T_379, asSInt(UInt<17>(0h100c0)))
node _T_381 = asSInt(_T_380)
node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0)))
node _T_383 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_384 = cvt(_T_383)
node _T_385 = and(_T_384, asSInt(UInt<29>(0h100000c0)))
node _T_386 = asSInt(_T_385)
node _T_387 = eq(_T_386, asSInt(UInt<1>(0h0)))
node _T_388 = or(_T_382, _T_387)
node _T_389 = and(_T_377, _T_388)
node _T_390 = or(UInt<1>(0h0), _T_389)
node _T_391 = and(_T_376, _T_390)
node _T_392 = asUInt(reset)
node _T_393 = eq(_T_392, UInt<1>(0h0))
when _T_393 :
node _T_394 = eq(_T_391, UInt<1>(0h0))
when _T_394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_391, UInt<1>(0h1), "") : assert_41
node _T_395 = asUInt(reset)
node _T_396 = eq(_T_395, UInt<1>(0h0))
when _T_396 :
node _T_397 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(is_aligned, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_401 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_T_401, UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_401, UInt<1>(0h1), "") : assert_44
node _T_405 = eq(io.in.a.bits.mask, mask)
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_405, UInt<1>(0h1), "") : assert_45
node _T_409 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_409 :
node _T_410 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_411 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_412 = and(_T_410, _T_411)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0)
node _T_413 = shr(io.in.a.bits.source, 4)
node _T_414 = eq(_T_413, UInt<1>(0h0))
node _T_415 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_416 = and(_T_414, _T_415)
node _T_417 = leq(uncommonBits_8, UInt<4>(0h9))
node _T_418 = and(_T_416, _T_417)
node _T_419 = and(_T_412, _T_418)
node _T_420 = or(UInt<1>(0h0), _T_419)
node _T_421 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_422 = xor(io.in.a.bits.address, UInt<28>(0h8000040))
node _T_423 = cvt(_T_422)
node _T_424 = and(_T_423, asSInt(UInt<17>(0h100c0)))
node _T_425 = asSInt(_T_424)
node _T_426 = eq(_T_425, asSInt(UInt<1>(0h0)))
node _T_427 = xor(io.in.a.bits.address, UInt<32>(0h80000040))
node _T_428 = cvt(_T_427)
node _T_429 = and(_T_428, asSInt(UInt<29>(0h100000c0)))
node _T_430 = asSInt(_T_429)
node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0)))
node _T_432 = or(_T_426, _T_431)
node _T_433 = and(_T_421, _T_432)
node _T_434 = or(UInt<1>(0h0), _T_433)
node _T_435 = and(_T_420, _T_434)
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_435, UInt<1>(0h1), "") : assert_46
node _T_439 = asUInt(reset)
node _T_440 = eq(_T_439, UInt<1>(0h0))
when _T_440 :
node _T_441 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_441 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_442 = asUInt(reset)
node _T_443 = eq(_T_442, UInt<1>(0h0))
when _T_443 :
node _T_444 = eq(is_aligned, UInt<1>(0h0))
when _T_444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_445 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_445, UInt<1>(0h1), "") : assert_49
node _T_449 = eq(io.in.a.bits.mask, mask)
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_T_449, UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_449, UInt<1>(0h1), "") : assert_50
node _T_453 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_454 = asUInt(reset)
node _T_455 = eq(_T_454, UInt<1>(0h0))
when _T_455 :
node _T_456 = eq(_T_453, UInt<1>(0h0))
when _T_456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_453, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_457 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_T_457, UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_457, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 4)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_461 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_461 :
node _T_462 = asUInt(reset)
node _T_463 = eq(_T_462, UInt<1>(0h0))
when _T_463 :
node _T_464 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_465 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_466 = asUInt(reset)
node _T_467 = eq(_T_466, UInt<1>(0h0))
when _T_467 :
node _T_468 = eq(_T_465, UInt<1>(0h0))
when _T_468 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_465, UInt<1>(0h1), "") : assert_54
node _T_469 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_469, UInt<1>(0h1), "") : assert_55
node _T_473 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_474 = asUInt(reset)
node _T_475 = eq(_T_474, UInt<1>(0h0))
when _T_475 :
node _T_476 = eq(_T_473, UInt<1>(0h0))
when _T_476 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_473, UInt<1>(0h1), "") : assert_56
node _T_477 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_477, UInt<1>(0h1), "") : assert_57
node _T_481 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_481 :
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_485 = asUInt(reset)
node _T_486 = eq(_T_485, UInt<1>(0h0))
when _T_486 :
node _T_487 = eq(sink_ok, UInt<1>(0h0))
when _T_487 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_488 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_488, UInt<1>(0h1), "") : assert_60
node _T_492 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(_T_492, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_492, UInt<1>(0h1), "") : assert_61
node _T_496 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_497 = asUInt(reset)
node _T_498 = eq(_T_497, UInt<1>(0h0))
when _T_498 :
node _T_499 = eq(_T_496, UInt<1>(0h0))
when _T_499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_496, UInt<1>(0h1), "") : assert_62
node _T_500 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_501 = asUInt(reset)
node _T_502 = eq(_T_501, UInt<1>(0h0))
when _T_502 :
node _T_503 = eq(_T_500, UInt<1>(0h0))
when _T_503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_500, UInt<1>(0h1), "") : assert_63
node _T_504 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_505 = or(UInt<1>(0h1), _T_504)
node _T_506 = asUInt(reset)
node _T_507 = eq(_T_506, UInt<1>(0h0))
when _T_507 :
node _T_508 = eq(_T_505, UInt<1>(0h0))
when _T_508 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_505, UInt<1>(0h1), "") : assert_64
node _T_509 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_509 :
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_513 = asUInt(reset)
node _T_514 = eq(_T_513, UInt<1>(0h0))
when _T_514 :
node _T_515 = eq(sink_ok, UInt<1>(0h0))
when _T_515 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_516 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_517 = asUInt(reset)
node _T_518 = eq(_T_517, UInt<1>(0h0))
when _T_518 :
node _T_519 = eq(_T_516, UInt<1>(0h0))
when _T_519 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_516, UInt<1>(0h1), "") : assert_67
node _T_520 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_521 = asUInt(reset)
node _T_522 = eq(_T_521, UInt<1>(0h0))
when _T_522 :
node _T_523 = eq(_T_520, UInt<1>(0h0))
when _T_523 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_520, UInt<1>(0h1), "") : assert_68
node _T_524 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_525 = asUInt(reset)
node _T_526 = eq(_T_525, UInt<1>(0h0))
when _T_526 :
node _T_527 = eq(_T_524, UInt<1>(0h0))
when _T_527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_524, UInt<1>(0h1), "") : assert_69
node _T_528 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_529 = or(_T_528, io.in.d.bits.corrupt)
node _T_530 = asUInt(reset)
node _T_531 = eq(_T_530, UInt<1>(0h0))
when _T_531 :
node _T_532 = eq(_T_529, UInt<1>(0h0))
when _T_532 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_529, UInt<1>(0h1), "") : assert_70
node _T_533 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_534 = or(UInt<1>(0h1), _T_533)
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_534, UInt<1>(0h1), "") : assert_71
node _T_538 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_538 :
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_542 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_543 = asUInt(reset)
node _T_544 = eq(_T_543, UInt<1>(0h0))
when _T_544 :
node _T_545 = eq(_T_542, UInt<1>(0h0))
when _T_545 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_542, UInt<1>(0h1), "") : assert_73
node _T_546 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_547 = asUInt(reset)
node _T_548 = eq(_T_547, UInt<1>(0h0))
when _T_548 :
node _T_549 = eq(_T_546, UInt<1>(0h0))
when _T_549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_546, UInt<1>(0h1), "") : assert_74
node _T_550 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_551 = or(UInt<1>(0h1), _T_550)
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_551, UInt<1>(0h1), "") : assert_75
node _T_555 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_555 :
node _T_556 = asUInt(reset)
node _T_557 = eq(_T_556, UInt<1>(0h0))
when _T_557 :
node _T_558 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_558 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_559 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_559, UInt<1>(0h1), "") : assert_77
node _T_563 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_564 = or(_T_563, io.in.d.bits.corrupt)
node _T_565 = asUInt(reset)
node _T_566 = eq(_T_565, UInt<1>(0h0))
when _T_566 :
node _T_567 = eq(_T_564, UInt<1>(0h0))
when _T_567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_564, UInt<1>(0h1), "") : assert_78
node _T_568 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_569 = or(UInt<1>(0h1), _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_569, UInt<1>(0h1), "") : assert_79
node _T_573 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_573 :
node _T_574 = asUInt(reset)
node _T_575 = eq(_T_574, UInt<1>(0h0))
when _T_575 :
node _T_576 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_577 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(_T_577, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_577, UInt<1>(0h1), "") : assert_81
node _T_581 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_582 = asUInt(reset)
node _T_583 = eq(_T_582, UInt<1>(0h0))
when _T_583 :
node _T_584 = eq(_T_581, UInt<1>(0h0))
when _T_584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_581, UInt<1>(0h1), "") : assert_82
node _T_585 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_586 = or(UInt<1>(0h1), _T_585)
node _T_587 = asUInt(reset)
node _T_588 = eq(_T_587, UInt<1>(0h0))
when _T_588 :
node _T_589 = eq(_T_586, UInt<1>(0h0))
when _T_589 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_586, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_590 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_591 = asUInt(reset)
node _T_592 = eq(_T_591, UInt<1>(0h0))
when _T_592 :
node _T_593 = eq(_T_590, UInt<1>(0h0))
when _T_593 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_590, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_594 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_594, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_598 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_599 = asUInt(reset)
node _T_600 = eq(_T_599, UInt<1>(0h0))
when _T_600 :
node _T_601 = eq(_T_598, UInt<1>(0h0))
when _T_601 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_598, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_602 = eq(a_first, UInt<1>(0h0))
node _T_603 = and(io.in.a.valid, _T_602)
when _T_603 :
node _T_604 = eq(io.in.a.bits.opcode, opcode)
node _T_605 = asUInt(reset)
node _T_606 = eq(_T_605, UInt<1>(0h0))
when _T_606 :
node _T_607 = eq(_T_604, UInt<1>(0h0))
when _T_607 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_604, UInt<1>(0h1), "") : assert_87
node _T_608 = eq(io.in.a.bits.param, param)
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(_T_608, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_608, UInt<1>(0h1), "") : assert_88
node _T_612 = eq(io.in.a.bits.size, size)
node _T_613 = asUInt(reset)
node _T_614 = eq(_T_613, UInt<1>(0h0))
when _T_614 :
node _T_615 = eq(_T_612, UInt<1>(0h0))
when _T_615 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_612, UInt<1>(0h1), "") : assert_89
node _T_616 = eq(io.in.a.bits.source, source)
node _T_617 = asUInt(reset)
node _T_618 = eq(_T_617, UInt<1>(0h0))
when _T_618 :
node _T_619 = eq(_T_616, UInt<1>(0h0))
when _T_619 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_616, UInt<1>(0h1), "") : assert_90
node _T_620 = eq(io.in.a.bits.address, address)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_620, UInt<1>(0h1), "") : assert_91
node _T_624 = and(io.in.a.ready, io.in.a.valid)
node _T_625 = and(_T_624, a_first)
when _T_625 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_626 = eq(d_first, UInt<1>(0h0))
node _T_627 = and(io.in.d.valid, _T_626)
when _T_627 :
node _T_628 = eq(io.in.d.bits.opcode, opcode_1)
node _T_629 = asUInt(reset)
node _T_630 = eq(_T_629, UInt<1>(0h0))
when _T_630 :
node _T_631 = eq(_T_628, UInt<1>(0h0))
when _T_631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_628, UInt<1>(0h1), "") : assert_92
node _T_632 = eq(io.in.d.bits.param, param_1)
node _T_633 = asUInt(reset)
node _T_634 = eq(_T_633, UInt<1>(0h0))
when _T_634 :
node _T_635 = eq(_T_632, UInt<1>(0h0))
when _T_635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_632, UInt<1>(0h1), "") : assert_93
node _T_636 = eq(io.in.d.bits.size, size_1)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_636, UInt<1>(0h1), "") : assert_94
node _T_640 = eq(io.in.d.bits.source, source_1)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_640, UInt<1>(0h1), "") : assert_95
node _T_644 = eq(io.in.d.bits.sink, sink)
node _T_645 = asUInt(reset)
node _T_646 = eq(_T_645, UInt<1>(0h0))
when _T_646 :
node _T_647 = eq(_T_644, UInt<1>(0h0))
when _T_647 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_644, UInt<1>(0h1), "") : assert_96
node _T_648 = eq(io.in.d.bits.denied, denied)
node _T_649 = asUInt(reset)
node _T_650 = eq(_T_649, UInt<1>(0h0))
when _T_650 :
node _T_651 = eq(_T_648, UInt<1>(0h0))
when _T_651 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_648, UInt<1>(0h1), "") : assert_97
node _T_652 = and(io.in.d.ready, io.in.d.valid)
node _T_653 = and(_T_652, d_first)
when _T_653 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<10>
connect a_set, UInt<10>(0h0)
wire a_set_wo_ready : UInt<10>
connect a_set_wo_ready, UInt<10>(0h0)
wire a_opcodes_set : UInt<40>
connect a_opcodes_set, UInt<40>(0h0)
wire a_sizes_set : UInt<40>
connect a_sizes_set, UInt<40>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_654 = and(io.in.a.valid, a_first_1)
node _T_655 = and(_T_654, UInt<1>(0h1))
when _T_655 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_656 = and(io.in.a.ready, io.in.a.valid)
node _T_657 = and(_T_656, a_first_1)
node _T_658 = and(_T_657, UInt<1>(0h1))
when _T_658 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_659 = dshr(inflight, io.in.a.bits.source)
node _T_660 = bits(_T_659, 0, 0)
node _T_661 = eq(_T_660, UInt<1>(0h0))
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_661, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<10>
connect d_clr, UInt<10>(0h0)
wire d_clr_wo_ready : UInt<10>
connect d_clr_wo_ready, UInt<10>(0h0)
wire d_opcodes_clr : UInt<40>
connect d_opcodes_clr, UInt<40>(0h0)
wire d_sizes_clr : UInt<40>
connect d_sizes_clr, UInt<40>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_665 = and(io.in.d.valid, d_first_1)
node _T_666 = and(_T_665, UInt<1>(0h1))
node _T_667 = eq(d_release_ack, UInt<1>(0h0))
node _T_668 = and(_T_666, _T_667)
when _T_668 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_669 = and(io.in.d.ready, io.in.d.valid)
node _T_670 = and(_T_669, d_first_1)
node _T_671 = and(_T_670, UInt<1>(0h1))
node _T_672 = eq(d_release_ack, UInt<1>(0h0))
node _T_673 = and(_T_671, _T_672)
when _T_673 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_674 = and(io.in.d.valid, d_first_1)
node _T_675 = and(_T_674, UInt<1>(0h1))
node _T_676 = eq(d_release_ack, UInt<1>(0h0))
node _T_677 = and(_T_675, _T_676)
when _T_677 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_678 = dshr(inflight, io.in.d.bits.source)
node _T_679 = bits(_T_678, 0, 0)
node _T_680 = or(_T_679, same_cycle_resp)
node _T_681 = asUInt(reset)
node _T_682 = eq(_T_681, UInt<1>(0h0))
when _T_682 :
node _T_683 = eq(_T_680, UInt<1>(0h0))
when _T_683 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_680, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_684 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_685 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_686 = or(_T_684, _T_685)
node _T_687 = asUInt(reset)
node _T_688 = eq(_T_687, UInt<1>(0h0))
when _T_688 :
node _T_689 = eq(_T_686, UInt<1>(0h0))
when _T_689 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_686, UInt<1>(0h1), "") : assert_100
node _T_690 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_691 = asUInt(reset)
node _T_692 = eq(_T_691, UInt<1>(0h0))
when _T_692 :
node _T_693 = eq(_T_690, UInt<1>(0h0))
when _T_693 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_690, UInt<1>(0h1), "") : assert_101
else :
node _T_694 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_695 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_696 = or(_T_694, _T_695)
node _T_697 = asUInt(reset)
node _T_698 = eq(_T_697, UInt<1>(0h0))
when _T_698 :
node _T_699 = eq(_T_696, UInt<1>(0h0))
when _T_699 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_696, UInt<1>(0h1), "") : assert_102
node _T_700 = eq(io.in.d.bits.size, a_size_lookup)
node _T_701 = asUInt(reset)
node _T_702 = eq(_T_701, UInt<1>(0h0))
when _T_702 :
node _T_703 = eq(_T_700, UInt<1>(0h0))
when _T_703 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_700, UInt<1>(0h1), "") : assert_103
node _T_704 = and(io.in.d.valid, d_first_1)
node _T_705 = and(_T_704, a_first_1)
node _T_706 = and(_T_705, io.in.a.valid)
node _T_707 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_708 = and(_T_706, _T_707)
node _T_709 = eq(d_release_ack, UInt<1>(0h0))
node _T_710 = and(_T_708, _T_709)
when _T_710 :
node _T_711 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_712 = or(_T_711, io.in.a.ready)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_712, UInt<1>(0h1), "") : assert_104
node _T_716 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_717 = orr(a_set_wo_ready)
node _T_718 = eq(_T_717, UInt<1>(0h0))
node _T_719 = or(_T_716, _T_718)
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_719, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_115
node _T_723 = orr(inflight)
node _T_724 = eq(_T_723, UInt<1>(0h0))
node _T_725 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_726 = or(_T_724, _T_725)
node _T_727 = lt(watchdog, plusarg_reader.out)
node _T_728 = or(_T_726, _T_727)
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_T_728, UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_728, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_732 = and(io.in.a.ready, io.in.a.valid)
node _T_733 = and(io.in.d.ready, io.in.d.valid)
node _T_734 = or(_T_732, _T_733)
when _T_734 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<4>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<10>
connect c_set, UInt<10>(0h0)
wire c_set_wo_ready : UInt<10>
connect c_set_wo_ready, UInt<10>(0h0)
wire c_opcodes_set : UInt<40>
connect c_opcodes_set, UInt<40>(0h0)
wire c_sizes_set : UInt<40>
connect c_sizes_set, UInt<40>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_735 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_736 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_737 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_738 = and(_T_736, _T_737)
node _T_739 = and(_T_735, _T_738)
when _T_739 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<4>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_740 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_741 = and(_T_740, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<4>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_742 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_743 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_744 = and(_T_742, _T_743)
node _T_745 = and(_T_741, _T_744)
when _T_745 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<4>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_746 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_747 = bits(_T_746, 0, 0)
node _T_748 = eq(_T_747, UInt<1>(0h0))
node _T_749 = asUInt(reset)
node _T_750 = eq(_T_749, UInt<1>(0h0))
when _T_750 :
node _T_751 = eq(_T_748, UInt<1>(0h0))
when _T_751 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_748, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<10>
connect d_clr_1, UInt<10>(0h0)
wire d_clr_wo_ready_1 : UInt<10>
connect d_clr_wo_ready_1, UInt<10>(0h0)
wire d_opcodes_clr_1 : UInt<40>
connect d_opcodes_clr_1, UInt<40>(0h0)
wire d_sizes_clr_1 : UInt<40>
connect d_sizes_clr_1, UInt<40>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_752 = and(io.in.d.valid, d_first_2)
node _T_753 = and(_T_752, UInt<1>(0h1))
node _T_754 = and(_T_753, d_release_ack_1)
when _T_754 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_755 = and(io.in.d.ready, io.in.d.valid)
node _T_756 = and(_T_755, d_first_2)
node _T_757 = and(_T_756, UInt<1>(0h1))
node _T_758 = and(_T_757, d_release_ack_1)
when _T_758 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_759 = and(io.in.d.valid, d_first_2)
node _T_760 = and(_T_759, UInt<1>(0h1))
node _T_761 = and(_T_760, d_release_ack_1)
when _T_761 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_762 = dshr(inflight_1, io.in.d.bits.source)
node _T_763 = bits(_T_762, 0, 0)
node _T_764 = or(_T_763, same_cycle_resp_1)
node _T_765 = asUInt(reset)
node _T_766 = eq(_T_765, UInt<1>(0h0))
when _T_766 :
node _T_767 = eq(_T_764, UInt<1>(0h0))
when _T_767 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_764, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<4>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_768 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_769 = asUInt(reset)
node _T_770 = eq(_T_769, UInt<1>(0h0))
when _T_770 :
node _T_771 = eq(_T_768, UInt<1>(0h0))
when _T_771 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_768, UInt<1>(0h1), "") : assert_109
else :
node _T_772 = eq(io.in.d.bits.size, c_size_lookup)
node _T_773 = asUInt(reset)
node _T_774 = eq(_T_773, UInt<1>(0h0))
when _T_774 :
node _T_775 = eq(_T_772, UInt<1>(0h0))
when _T_775 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_772, UInt<1>(0h1), "") : assert_110
node _T_776 = and(io.in.d.valid, d_first_2)
node _T_777 = and(_T_776, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<4>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_778 = and(_T_777, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<4>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_779 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_780 = and(_T_778, _T_779)
node _T_781 = and(_T_780, d_release_ack_1)
node _T_782 = eq(c_probe_ack, UInt<1>(0h0))
node _T_783 = and(_T_781, _T_782)
when _T_783 :
node _T_784 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<4>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_785 = or(_T_784, _WIRE_23.ready)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_785, UInt<1>(0h1), "") : assert_111
node _T_789 = orr(c_set_wo_ready)
when _T_789 :
node _T_790 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_791 = asUInt(reset)
node _T_792 = eq(_T_791, UInt<1>(0h0))
when _T_792 :
node _T_793 = eq(_T_790, UInt<1>(0h0))
when _T_793 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_790, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_116
node _T_794 = orr(inflight_1)
node _T_795 = eq(_T_794, UInt<1>(0h0))
node _T_796 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_797 = or(_T_795, _T_796)
node _T_798 = lt(watchdog_1, plusarg_reader_1.out)
node _T_799 = or(_T_797, _T_798)
node _T_800 = asUInt(reset)
node _T_801 = eq(_T_800, UInt<1>(0h0))
when _T_801 :
node _T_802 = eq(_T_799, UInt<1>(0h0))
when _T_802 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_799, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<4>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_803 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_804 = and(io.in.d.ready, io.in.d.valid)
node _T_805 = or(_T_803, _T_804)
when _T_805 :
connect watchdog_1, UInt<1>(0h0)
extmodule plusarg_reader_117 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_118 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_53( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [9:0] inflight; // @[Monitor.scala:614:27]
reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [39:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [15:0] _GEN_0 = {12'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [15:0] _GEN_3 = {12'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [9:0] inflight_1; // @[Monitor.scala:726:35]
reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_37 :
output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}}
node rawA_exp = bits(io.a, 31, 23)
node _rawA_isZero_T = bits(rawA_exp, 8, 6)
node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0))
node _rawA_isSpecial_T = bits(rawA_exp, 8, 7)
node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3))
wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6)
node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T)
connect rawA.isNaN, _rawA_out_isNaN_T_1
node _rawA_out_isInf_T = bits(rawA_exp, 6, 6)
node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0))
node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1)
connect rawA.isInf, _rawA_out_isInf_T_2
connect rawA.isZero, rawA_isZero
node _rawA_out_sign_T = bits(io.a, 32, 32)
connect rawA.sign, _rawA_out_sign_T
node _rawA_out_sExp_T = cvt(rawA_exp)
connect rawA.sExp, _rawA_out_sExp_T
node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0))
node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T)
node _rawA_out_sig_T_2 = bits(io.a, 22, 0)
node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2)
connect rawA.sig, _rawA_out_sig_T_3
node rawB_exp = bits(io.b, 31, 23)
node _rawB_isZero_T = bits(rawB_exp, 8, 6)
node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0))
node _rawB_isSpecial_T = bits(rawB_exp, 8, 7)
node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3))
wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6)
node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T)
connect rawB.isNaN, _rawB_out_isNaN_T_1
node _rawB_out_isInf_T = bits(rawB_exp, 6, 6)
node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0))
node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1)
connect rawB.isInf, _rawB_out_isInf_T_2
connect rawB.isZero, rawB_isZero
node _rawB_out_sign_T = bits(io.b, 32, 32)
connect rawB.sign, _rawB_out_sign_T
node _rawB_out_sExp_T = cvt(rawB_exp)
connect rawB.sExp, _rawB_out_sExp_T
node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0))
node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T)
node _rawB_out_sig_T_2 = bits(io.b, 22, 0)
node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2)
connect rawB.sig, _rawB_out_sig_T_3
node rawC_exp = bits(io.c, 31, 23)
node _rawC_isZero_T = bits(rawC_exp, 8, 6)
node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0))
node _rawC_isSpecial_T = bits(rawC_exp, 8, 7)
node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3))
wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6)
node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T)
connect rawC.isNaN, _rawC_out_isNaN_T_1
node _rawC_out_isInf_T = bits(rawC_exp, 6, 6)
node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0))
node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1)
connect rawC.isInf, _rawC_out_isInf_T_2
connect rawC.isZero, rawC_isZero
node _rawC_out_sign_T = bits(io.c, 32, 32)
connect rawC.sign, _rawC_out_sign_T
node _rawC_out_sExp_T = cvt(rawC_exp)
connect rawC.sExp, _rawC_out_sExp_T
node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0))
node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T)
node _rawC_out_sig_T_2 = bits(io.c, 22, 0)
node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2)
connect rawC.sig, _rawC_out_sig_T_3
node _signProd_T = xor(rawA.sign, rawB.sign)
node _signProd_T_1 = bits(io.op, 1, 1)
node signProd = xor(_signProd_T, _signProd_T_1)
node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp)
node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b)))
node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1)
node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2)
node _doSubMags_T = xor(signProd, rawC.sign)
node _doSubMags_T_1 = bits(io.op, 0, 0)
node doSubMags = xor(_doSubMags_T, _doSubMags_T_1)
node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp)
node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1)
node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1)
node posNatCAlignDist = bits(sNatCAlignDist, 9, 0)
node _isMinCAlign_T = or(rawA.isZero, rawB.isZero)
node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0)))
node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1)
node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0))
node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18))
node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1)
node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2)
node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a))
node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0)
node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a))
node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2)
node _mainAlignedSigC_T = not(rawC.sig)
node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig)
node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0))
node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2)
node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3)
node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist)
node _reduced4CExtra_T = shl(rawC.sig, 2)
wire reduced4CExtra_reducedVec : UInt<1>[7]
node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0)
node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T)
connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1
node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4)
node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T)
connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1
node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8)
node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T)
connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1
node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12)
node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T)
connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1
node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16)
node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T)
connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1
node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20)
node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T)
connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1
node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24)
node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T)
connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1
node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1])
node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0])
node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3])
node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5])
node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo)
node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo)
node _reduced4CExtra_T_2 = shr(CAlignDist, 2)
node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2)
node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14)
node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0)
node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0)
node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0)
node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1)
node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7)
node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2)
node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0)
node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1)
node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11)
node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12)
node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4)
node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0)
node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1)
node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16)
node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17)
node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18)
node reduced4CExtra = orr(_reduced4CExtra_T_19)
node _alignedSigC_T = shr(mainAlignedSigC, 3)
node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_2 = andr(_alignedSigC_T_1)
node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0))
node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3)
node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_6 = orr(_alignedSigC_T_5)
node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra)
node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7)
node alignedSigC_hi = asUInt(_alignedSigC_T)
node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8)
connect io.mulAddA, rawA.sig
connect io.mulAddB, rawB.sig
node _io_mulAddC_T = bits(alignedSigC, 48, 1)
connect io.mulAddC, _io_mulAddC_T
node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1)
node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4)
node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5)
node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8)
node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9)
connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10
node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN)
connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T
connect io.toPostMul.isInfA, rawA.isInf
connect io.toPostMul.isZeroA, rawA.isZero
connect io.toPostMul.isInfB, rawB.isInf
connect io.toPostMul.isZeroB, rawB.isZero
connect io.toPostMul.signProd, signProd
connect io.toPostMul.isNaNC, rawC.isNaN
connect io.toPostMul.isInfC, rawC.isInf
connect io.toPostMul.isZeroC, rawC.isZero
node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18)))
node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1)
node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1)
node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2)
connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3
connect io.toPostMul.doSubMags, doSubMags
connect io.toPostMul.CIsDominant, CIsDominant
node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0)
connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T
node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49)
connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T
node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0)
connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T | module MulAddRecFNToRaw_preMul_e8_s24_37( // @[MulAddRecFN.scala:71:7]
input [32:0] io_a, // @[MulAddRecFN.scala:74:16]
input [32:0] io_b, // @[MulAddRecFN.scala:74:16]
input [32:0] io_c, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16]
output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16]
output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16]
output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16]
output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7]
wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7]
wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7]
wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49]
wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:71:7, :74:16]
wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30]
wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58]
wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42]
wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire signProd; // @[MulAddRecFN.scala:97:42]
wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire doSubMags; // @[MulAddRecFN.scala:102:42]
wire CIsDominant; // @[MulAddRecFN.scala:110:23]
wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47]
wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20]
wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48]
wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}]
assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42]
wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}]
wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32]
wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32]
wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}]
assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42]
wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42]
wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42]
wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42]
wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42]
wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69]
wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}]
wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60]
wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}]
assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}]
assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23]
wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34]
wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33]
wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33]
wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16]
wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53]
wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}]
wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}]
wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}]
wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23]
wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15]
assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20]
wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28]
wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56]
wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20]
wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22]
wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20]
wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20]
wire reduced4CExtra = |_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11]
wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28]
wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}]
wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32]
wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32]
wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}]
wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47]
wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}]
wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}]
wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}]
wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44]
wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16]
assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23]
assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23]
assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30]
assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30]
wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46]
wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23]
assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46]
assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58]
assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42]
wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53]
wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12]
assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47]
assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47]
assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20]
assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20]
assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48]
assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48]
assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_6 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_6
connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc
connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc
connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig
connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp
connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign
connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module RoundRawFNToRecFN_e8_s24_6( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_6 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_216 :
input clock : Clock
input reset : Reset
output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}}
regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff)
reg value_reg : { symbol : UInt<10>}, clock
connect io.output_prev.key, key_reg
connect io.output_prev.value, value_reg
connect io.output_nxt.key, key_reg
connect io.output_nxt.value, value_reg
connect io.cur_output_keyval.key, key_reg
connect io.cur_output_keyval.value, value_reg
when io.cmd.valid :
node _T = eq(UInt<1>(0h0), io.cmd.bits)
when _T :
connect key_reg, io.input_nxt.key
connect value_reg, io.input_nxt.value
else :
node _T_1 = eq(UInt<1>(0h1), io.cmd.bits)
when _T_1 :
when io.insert_here :
connect key_reg, io.cur_input_keyval.key
connect value_reg, io.cur_input_keyval.value
else :
node _T_2 = geq(key_reg, io.cur_input_keyval.key)
when _T_2 :
connect key_reg, io.input_prev.key
connect value_reg, io.input_prev.value
else :
skip | module PriorityQueueStage_216( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_47 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2))
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_lo = cat(mask_acc_1, mask_acc)
node mask_hi = cat(mask_acc_3, mask_acc_2)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_17 = and(UInt<1>(0h0), _T_16)
node _T_18 = or(UInt<1>(0h0), _T_17)
node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_21 = cvt(_T_20)
node _T_22 = and(_T_21, asSInt(UInt<7>(0h40)))
node _T_23 = asSInt(_T_22)
node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0)))
node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_26 = cvt(_T_25)
node _T_27 = and(_T_26, asSInt(UInt<5>(0h14)))
node _T_28 = asSInt(_T_27)
node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0)))
node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_31 = cvt(_T_30)
node _T_32 = and(_T_31, asSInt(UInt<4>(0h8)))
node _T_33 = asSInt(_T_32)
node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_36 = cvt(_T_35)
node _T_37 = and(_T_36, asSInt(UInt<6>(0h20)))
node _T_38 = asSInt(_T_37)
node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0)))
node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_41 = cvt(_T_40)
node _T_42 = and(_T_41, asSInt(UInt<8>(0h80)))
node _T_43 = asSInt(_T_42)
node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0)))
node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<9>(0h100)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_24, _T_29)
node _T_51 = or(_T_50, _T_34)
node _T_52 = or(_T_51, _T_39)
node _T_53 = or(_T_52, _T_44)
node _T_54 = or(_T_53, _T_49)
node _T_55 = and(_T_19, _T_54)
node _T_56 = or(UInt<1>(0h0), _T_55)
node _T_57 = and(_T_18, _T_56)
node _T_58 = asUInt(reset)
node _T_59 = eq(_T_58, UInt<1>(0h0))
when _T_59 :
node _T_60 = eq(_T_57, UInt<1>(0h0))
when _T_60 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_57, UInt<1>(0h1), "") : assert_2
node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_63 = and(_T_61, _T_62)
node _T_64 = or(UInt<1>(0h0), _T_63)
node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_66 = cvt(_T_65)
node _T_67 = and(_T_66, asSInt(UInt<7>(0h40)))
node _T_68 = asSInt(_T_67)
node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0)))
node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_71 = cvt(_T_70)
node _T_72 = and(_T_71, asSInt(UInt<5>(0h14)))
node _T_73 = asSInt(_T_72)
node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0)))
node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_76 = cvt(_T_75)
node _T_77 = and(_T_76, asSInt(UInt<4>(0h8)))
node _T_78 = asSInt(_T_77)
node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0)))
node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_81 = cvt(_T_80)
node _T_82 = and(_T_81, asSInt(UInt<6>(0h20)))
node _T_83 = asSInt(_T_82)
node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_86 = cvt(_T_85)
node _T_87 = and(_T_86, asSInt(UInt<8>(0h80)))
node _T_88 = asSInt(_T_87)
node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<9>(0h100)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_69, _T_74)
node _T_96 = or(_T_95, _T_79)
node _T_97 = or(_T_96, _T_84)
node _T_98 = or(_T_97, _T_89)
node _T_99 = or(_T_98, _T_94)
node _T_100 = and(_T_64, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(UInt<1>(0h0), _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_102, UInt<1>(0h1), "") : assert_3
node _T_106 = asUInt(reset)
node _T_107 = eq(_T_106, UInt<1>(0h0))
when _T_107 :
node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_110 = asUInt(reset)
node _T_111 = eq(_T_110, UInt<1>(0h0))
when _T_111 :
node _T_112 = eq(_T_109, UInt<1>(0h0))
when _T_112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_109, UInt<1>(0h1), "") : assert_5
node _T_113 = asUInt(reset)
node _T_114 = eq(_T_113, UInt<1>(0h0))
when _T_114 :
node _T_115 = eq(is_aligned, UInt<1>(0h0))
when _T_115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_117 = asUInt(reset)
node _T_118 = eq(_T_117, UInt<1>(0h0))
when _T_118 :
node _T_119 = eq(_T_116, UInt<1>(0h0))
when _T_119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_116, UInt<1>(0h1), "") : assert_7
node _T_120 = not(io.in.a.bits.mask)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_121, UInt<1>(0h1), "") : assert_8
node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_126 = asUInt(reset)
node _T_127 = eq(_T_126, UInt<1>(0h0))
when _T_127 :
node _T_128 = eq(_T_125, UInt<1>(0h0))
when _T_128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_125, UInt<1>(0h1), "") : assert_9
node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_129 :
node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_131 = and(UInt<1>(0h0), _T_130)
node _T_132 = or(UInt<1>(0h0), _T_131)
node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_135 = cvt(_T_134)
node _T_136 = and(_T_135, asSInt(UInt<7>(0h40)))
node _T_137 = asSInt(_T_136)
node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0)))
node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_140 = cvt(_T_139)
node _T_141 = and(_T_140, asSInt(UInt<5>(0h14)))
node _T_142 = asSInt(_T_141)
node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0)))
node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_145 = cvt(_T_144)
node _T_146 = and(_T_145, asSInt(UInt<4>(0h8)))
node _T_147 = asSInt(_T_146)
node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_150 = cvt(_T_149)
node _T_151 = and(_T_150, asSInt(UInt<6>(0h20)))
node _T_152 = asSInt(_T_151)
node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0)))
node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<8>(0h80)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_160 = cvt(_T_159)
node _T_161 = and(_T_160, asSInt(UInt<9>(0h100)))
node _T_162 = asSInt(_T_161)
node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0)))
node _T_164 = or(_T_138, _T_143)
node _T_165 = or(_T_164, _T_148)
node _T_166 = or(_T_165, _T_153)
node _T_167 = or(_T_166, _T_158)
node _T_168 = or(_T_167, _T_163)
node _T_169 = and(_T_133, _T_168)
node _T_170 = or(UInt<1>(0h0), _T_169)
node _T_171 = and(_T_132, _T_170)
node _T_172 = asUInt(reset)
node _T_173 = eq(_T_172, UInt<1>(0h0))
when _T_173 :
node _T_174 = eq(_T_171, UInt<1>(0h0))
when _T_174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_171, UInt<1>(0h1), "") : assert_10
node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_177 = and(_T_175, _T_176)
node _T_178 = or(UInt<1>(0h0), _T_177)
node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_180 = cvt(_T_179)
node _T_181 = and(_T_180, asSInt(UInt<7>(0h40)))
node _T_182 = asSInt(_T_181)
node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0)))
node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_185 = cvt(_T_184)
node _T_186 = and(_T_185, asSInt(UInt<5>(0h14)))
node _T_187 = asSInt(_T_186)
node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_190 = cvt(_T_189)
node _T_191 = and(_T_190, asSInt(UInt<4>(0h8)))
node _T_192 = asSInt(_T_191)
node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0)))
node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<6>(0h20)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_200 = cvt(_T_199)
node _T_201 = and(_T_200, asSInt(UInt<8>(0h80)))
node _T_202 = asSInt(_T_201)
node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0)))
node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_205 = cvt(_T_204)
node _T_206 = and(_T_205, asSInt(UInt<9>(0h100)))
node _T_207 = asSInt(_T_206)
node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0)))
node _T_209 = or(_T_183, _T_188)
node _T_210 = or(_T_209, _T_193)
node _T_211 = or(_T_210, _T_198)
node _T_212 = or(_T_211, _T_203)
node _T_213 = or(_T_212, _T_208)
node _T_214 = and(_T_178, _T_213)
node _T_215 = or(UInt<1>(0h0), _T_214)
node _T_216 = and(UInt<1>(0h0), _T_215)
node _T_217 = asUInt(reset)
node _T_218 = eq(_T_217, UInt<1>(0h0))
when _T_218 :
node _T_219 = eq(_T_216, UInt<1>(0h0))
when _T_219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_216, UInt<1>(0h1), "") : assert_11
node _T_220 = asUInt(reset)
node _T_221 = eq(_T_220, UInt<1>(0h0))
when _T_221 :
node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_224 = asUInt(reset)
node _T_225 = eq(_T_224, UInt<1>(0h0))
when _T_225 :
node _T_226 = eq(_T_223, UInt<1>(0h0))
when _T_226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_223, UInt<1>(0h1), "") : assert_13
node _T_227 = asUInt(reset)
node _T_228 = eq(_T_227, UInt<1>(0h0))
when _T_228 :
node _T_229 = eq(is_aligned, UInt<1>(0h0))
when _T_229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_231 = asUInt(reset)
node _T_232 = eq(_T_231, UInt<1>(0h0))
when _T_232 :
node _T_233 = eq(_T_230, UInt<1>(0h0))
when _T_233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_230, UInt<1>(0h1), "") : assert_15
node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_235 = asUInt(reset)
node _T_236 = eq(_T_235, UInt<1>(0h0))
when _T_236 :
node _T_237 = eq(_T_234, UInt<1>(0h0))
when _T_237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_234, UInt<1>(0h1), "") : assert_16
node _T_238 = not(io.in.a.bits.mask)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_239, UInt<1>(0h1), "") : assert_17
node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_244 = asUInt(reset)
node _T_245 = eq(_T_244, UInt<1>(0h0))
when _T_245 :
node _T_246 = eq(_T_243, UInt<1>(0h0))
when _T_246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_243, UInt<1>(0h1), "") : assert_18
node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_247 :
node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = asUInt(reset)
node _T_253 = eq(_T_252, UInt<1>(0h0))
when _T_253 :
node _T_254 = eq(_T_251, UInt<1>(0h0))
when _T_254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_251, UInt<1>(0h1), "") : assert_19
node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_257 = and(_T_255, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_260 = cvt(_T_259)
node _T_261 = and(_T_260, asSInt(UInt<7>(0h40)))
node _T_262 = asSInt(_T_261)
node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0)))
node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_265 = cvt(_T_264)
node _T_266 = and(_T_265, asSInt(UInt<5>(0h14)))
node _T_267 = asSInt(_T_266)
node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0)))
node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_270 = cvt(_T_269)
node _T_271 = and(_T_270, asSInt(UInt<4>(0h8)))
node _T_272 = asSInt(_T_271)
node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0)))
node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_275 = cvt(_T_274)
node _T_276 = and(_T_275, asSInt(UInt<6>(0h20)))
node _T_277 = asSInt(_T_276)
node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0)))
node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_280 = cvt(_T_279)
node _T_281 = and(_T_280, asSInt(UInt<8>(0h80)))
node _T_282 = asSInt(_T_281)
node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0)))
node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_285 = cvt(_T_284)
node _T_286 = and(_T_285, asSInt(UInt<9>(0h100)))
node _T_287 = asSInt(_T_286)
node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0)))
node _T_289 = or(_T_263, _T_268)
node _T_290 = or(_T_289, _T_273)
node _T_291 = or(_T_290, _T_278)
node _T_292 = or(_T_291, _T_283)
node _T_293 = or(_T_292, _T_288)
node _T_294 = and(_T_258, _T_293)
node _T_295 = or(UInt<1>(0h0), _T_294)
node _T_296 = asUInt(reset)
node _T_297 = eq(_T_296, UInt<1>(0h0))
when _T_297 :
node _T_298 = eq(_T_295, UInt<1>(0h0))
when _T_298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_295, UInt<1>(0h1), "") : assert_20
node _T_299 = asUInt(reset)
node _T_300 = eq(_T_299, UInt<1>(0h0))
when _T_300 :
node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(is_aligned, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(_T_305, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_305, UInt<1>(0h1), "") : assert_23
node _T_309 = eq(io.in.a.bits.mask, mask)
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_309, UInt<1>(0h1), "") : assert_24
node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_313, UInt<1>(0h1), "") : assert_25
node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_320 = and(_T_318, _T_319)
node _T_321 = or(UInt<1>(0h0), _T_320)
node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_324 = and(_T_322, _T_323)
node _T_325 = or(UInt<1>(0h0), _T_324)
node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_327 = cvt(_T_326)
node _T_328 = and(_T_327, asSInt(UInt<7>(0h40)))
node _T_329 = asSInt(_T_328)
node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0)))
node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_332 = cvt(_T_331)
node _T_333 = and(_T_332, asSInt(UInt<5>(0h14)))
node _T_334 = asSInt(_T_333)
node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0)))
node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_337 = cvt(_T_336)
node _T_338 = and(_T_337, asSInt(UInt<4>(0h8)))
node _T_339 = asSInt(_T_338)
node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0)))
node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_342 = cvt(_T_341)
node _T_343 = and(_T_342, asSInt(UInt<6>(0h20)))
node _T_344 = asSInt(_T_343)
node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0)))
node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_347 = cvt(_T_346)
node _T_348 = and(_T_347, asSInt(UInt<8>(0h80)))
node _T_349 = asSInt(_T_348)
node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0)))
node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_352 = cvt(_T_351)
node _T_353 = and(_T_352, asSInt(UInt<9>(0h100)))
node _T_354 = asSInt(_T_353)
node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0)))
node _T_356 = or(_T_330, _T_335)
node _T_357 = or(_T_356, _T_340)
node _T_358 = or(_T_357, _T_345)
node _T_359 = or(_T_358, _T_350)
node _T_360 = or(_T_359, _T_355)
node _T_361 = and(_T_325, _T_360)
node _T_362 = or(UInt<1>(0h0), _T_361)
node _T_363 = and(_T_321, _T_362)
node _T_364 = asUInt(reset)
node _T_365 = eq(_T_364, UInt<1>(0h0))
when _T_365 :
node _T_366 = eq(_T_363, UInt<1>(0h0))
when _T_366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_363, UInt<1>(0h1), "") : assert_26
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(is_aligned, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_373, UInt<1>(0h1), "") : assert_29
node _T_377 = eq(io.in.a.bits.mask, mask)
node _T_378 = asUInt(reset)
node _T_379 = eq(_T_378, UInt<1>(0h0))
when _T_379 :
node _T_380 = eq(_T_377, UInt<1>(0h0))
when _T_380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_377, UInt<1>(0h1), "") : assert_30
node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_381 :
node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_383 = and(UInt<1>(0h0), _T_382)
node _T_384 = or(UInt<1>(0h0), _T_383)
node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_387 = and(_T_385, _T_386)
node _T_388 = or(UInt<1>(0h0), _T_387)
node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<7>(0h40)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_395 = cvt(_T_394)
node _T_396 = and(_T_395, asSInt(UInt<5>(0h14)))
node _T_397 = asSInt(_T_396)
node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0)))
node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<4>(0h8)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<6>(0h20)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<8>(0h80)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<9>(0h100)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = or(_T_393, _T_398)
node _T_420 = or(_T_419, _T_403)
node _T_421 = or(_T_420, _T_408)
node _T_422 = or(_T_421, _T_413)
node _T_423 = or(_T_422, _T_418)
node _T_424 = and(_T_388, _T_423)
node _T_425 = or(UInt<1>(0h0), _T_424)
node _T_426 = and(_T_384, _T_425)
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(_T_426, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_426, UInt<1>(0h1), "") : assert_31
node _T_430 = asUInt(reset)
node _T_431 = eq(_T_430, UInt<1>(0h0))
when _T_431 :
node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(is_aligned, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_436, UInt<1>(0h1), "") : assert_34
node _T_440 = not(mask)
node _T_441 = and(io.in.a.bits.mask, _T_440)
node _T_442 = eq(_T_441, UInt<1>(0h0))
node _T_443 = asUInt(reset)
node _T_444 = eq(_T_443, UInt<1>(0h0))
when _T_444 :
node _T_445 = eq(_T_442, UInt<1>(0h0))
when _T_445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_442, UInt<1>(0h1), "") : assert_35
node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_446 :
node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_448 = and(UInt<1>(0h0), _T_447)
node _T_449 = or(UInt<1>(0h0), _T_448)
node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_452 = cvt(_T_451)
node _T_453 = and(_T_452, asSInt(UInt<7>(0h40)))
node _T_454 = asSInt(_T_453)
node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0)))
node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_457 = cvt(_T_456)
node _T_458 = and(_T_457, asSInt(UInt<5>(0h14)))
node _T_459 = asSInt(_T_458)
node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0)))
node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_462 = cvt(_T_461)
node _T_463 = and(_T_462, asSInt(UInt<4>(0h8)))
node _T_464 = asSInt(_T_463)
node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0)))
node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_467 = cvt(_T_466)
node _T_468 = and(_T_467, asSInt(UInt<6>(0h20)))
node _T_469 = asSInt(_T_468)
node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0)))
node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_472 = cvt(_T_471)
node _T_473 = and(_T_472, asSInt(UInt<8>(0h80)))
node _T_474 = asSInt(_T_473)
node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0)))
node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_477 = cvt(_T_476)
node _T_478 = and(_T_477, asSInt(UInt<9>(0h100)))
node _T_479 = asSInt(_T_478)
node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0)))
node _T_481 = or(_T_455, _T_460)
node _T_482 = or(_T_481, _T_465)
node _T_483 = or(_T_482, _T_470)
node _T_484 = or(_T_483, _T_475)
node _T_485 = or(_T_484, _T_480)
node _T_486 = and(_T_450, _T_485)
node _T_487 = or(UInt<1>(0h0), _T_486)
node _T_488 = and(_T_449, _T_487)
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_488, UInt<1>(0h1), "") : assert_36
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_495 = asUInt(reset)
node _T_496 = eq(_T_495, UInt<1>(0h0))
when _T_496 :
node _T_497 = eq(is_aligned, UInt<1>(0h0))
when _T_497 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_499 = asUInt(reset)
node _T_500 = eq(_T_499, UInt<1>(0h0))
when _T_500 :
node _T_501 = eq(_T_498, UInt<1>(0h0))
when _T_501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_498, UInt<1>(0h1), "") : assert_39
node _T_502 = eq(io.in.a.bits.mask, mask)
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_502, UInt<1>(0h1), "") : assert_40
node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_506 :
node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_508 = and(UInt<1>(0h0), _T_507)
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_512 = cvt(_T_511)
node _T_513 = and(_T_512, asSInt(UInt<7>(0h40)))
node _T_514 = asSInt(_T_513)
node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0)))
node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_517 = cvt(_T_516)
node _T_518 = and(_T_517, asSInt(UInt<5>(0h14)))
node _T_519 = asSInt(_T_518)
node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0)))
node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_522 = cvt(_T_521)
node _T_523 = and(_T_522, asSInt(UInt<4>(0h8)))
node _T_524 = asSInt(_T_523)
node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0)))
node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_527 = cvt(_T_526)
node _T_528 = and(_T_527, asSInt(UInt<6>(0h20)))
node _T_529 = asSInt(_T_528)
node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0)))
node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_532 = cvt(_T_531)
node _T_533 = and(_T_532, asSInt(UInt<8>(0h80)))
node _T_534 = asSInt(_T_533)
node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0)))
node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_537 = cvt(_T_536)
node _T_538 = and(_T_537, asSInt(UInt<9>(0h100)))
node _T_539 = asSInt(_T_538)
node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0)))
node _T_541 = or(_T_515, _T_520)
node _T_542 = or(_T_541, _T_525)
node _T_543 = or(_T_542, _T_530)
node _T_544 = or(_T_543, _T_535)
node _T_545 = or(_T_544, _T_540)
node _T_546 = and(_T_510, _T_545)
node _T_547 = or(UInt<1>(0h0), _T_546)
node _T_548 = and(_T_509, _T_547)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_548, UInt<1>(0h1), "") : assert_41
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_555 = asUInt(reset)
node _T_556 = eq(_T_555, UInt<1>(0h0))
when _T_556 :
node _T_557 = eq(is_aligned, UInt<1>(0h0))
when _T_557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_559 = asUInt(reset)
node _T_560 = eq(_T_559, UInt<1>(0h0))
when _T_560 :
node _T_561 = eq(_T_558, UInt<1>(0h0))
when _T_561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_558, UInt<1>(0h1), "") : assert_44
node _T_562 = eq(io.in.a.bits.mask, mask)
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(_T_562, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_562, UInt<1>(0h1), "") : assert_45
node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_566 :
node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_568 = and(UInt<1>(0h0), _T_567)
node _T_569 = or(UInt<1>(0h0), _T_568)
node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_572 = cvt(_T_571)
node _T_573 = and(_T_572, asSInt(UInt<7>(0h40)))
node _T_574 = asSInt(_T_573)
node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0)))
node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_577 = cvt(_T_576)
node _T_578 = and(_T_577, asSInt(UInt<5>(0h14)))
node _T_579 = asSInt(_T_578)
node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0)))
node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_582 = cvt(_T_581)
node _T_583 = and(_T_582, asSInt(UInt<4>(0h8)))
node _T_584 = asSInt(_T_583)
node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0)))
node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_587 = cvt(_T_586)
node _T_588 = and(_T_587, asSInt(UInt<6>(0h20)))
node _T_589 = asSInt(_T_588)
node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0)))
node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_592 = cvt(_T_591)
node _T_593 = and(_T_592, asSInt(UInt<8>(0h80)))
node _T_594 = asSInt(_T_593)
node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0)))
node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_597 = cvt(_T_596)
node _T_598 = and(_T_597, asSInt(UInt<9>(0h100)))
node _T_599 = asSInt(_T_598)
node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0)))
node _T_601 = or(_T_575, _T_580)
node _T_602 = or(_T_601, _T_585)
node _T_603 = or(_T_602, _T_590)
node _T_604 = or(_T_603, _T_595)
node _T_605 = or(_T_604, _T_600)
node _T_606 = and(_T_570, _T_605)
node _T_607 = or(UInt<1>(0h0), _T_606)
node _T_608 = and(_T_569, _T_607)
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(_T_608, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_608, UInt<1>(0h1), "") : assert_46
node _T_612 = asUInt(reset)
node _T_613 = eq(_T_612, UInt<1>(0h0))
when _T_613 :
node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(is_aligned, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_619 = asUInt(reset)
node _T_620 = eq(_T_619, UInt<1>(0h0))
when _T_620 :
node _T_621 = eq(_T_618, UInt<1>(0h0))
when _T_621 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_618, UInt<1>(0h1), "") : assert_49
node _T_622 = eq(io.in.a.bits.mask, mask)
node _T_623 = asUInt(reset)
node _T_624 = eq(_T_623, UInt<1>(0h0))
when _T_624 :
node _T_625 = eq(_T_622, UInt<1>(0h0))
when _T_625 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_622, UInt<1>(0h1), "") : assert_50
node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_626, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_630, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_634 :
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(_T_638, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_638, UInt<1>(0h1), "") : assert_54
node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_642, UInt<1>(0h1), "") : assert_55
node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_647 = asUInt(reset)
node _T_648 = eq(_T_647, UInt<1>(0h0))
when _T_648 :
node _T_649 = eq(_T_646, UInt<1>(0h0))
when _T_649 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_646, UInt<1>(0h1), "") : assert_56
node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_651 = asUInt(reset)
node _T_652 = eq(_T_651, UInt<1>(0h0))
when _T_652 :
node _T_653 = eq(_T_650, UInt<1>(0h0))
when _T_653 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_650, UInt<1>(0h1), "") : assert_57
node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_654 :
node _T_655 = asUInt(reset)
node _T_656 = eq(_T_655, UInt<1>(0h0))
when _T_656 :
node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_658 = asUInt(reset)
node _T_659 = eq(_T_658, UInt<1>(0h0))
when _T_659 :
node _T_660 = eq(sink_ok, UInt<1>(0h0))
when _T_660 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_661, UInt<1>(0h1), "") : assert_60
node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_666 = asUInt(reset)
node _T_667 = eq(_T_666, UInt<1>(0h0))
when _T_667 :
node _T_668 = eq(_T_665, UInt<1>(0h0))
when _T_668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_665, UInt<1>(0h1), "") : assert_61
node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(_T_669, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_669, UInt<1>(0h1), "") : assert_62
node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_674 = asUInt(reset)
node _T_675 = eq(_T_674, UInt<1>(0h0))
when _T_675 :
node _T_676 = eq(_T_673, UInt<1>(0h0))
when _T_676 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_673, UInt<1>(0h1), "") : assert_63
node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_678 = or(UInt<1>(0h1), _T_677)
node _T_679 = asUInt(reset)
node _T_680 = eq(_T_679, UInt<1>(0h0))
when _T_680 :
node _T_681 = eq(_T_678, UInt<1>(0h0))
when _T_681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_678, UInt<1>(0h1), "") : assert_64
node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_682 :
node _T_683 = asUInt(reset)
node _T_684 = eq(_T_683, UInt<1>(0h0))
when _T_684 :
node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_685 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_686 = asUInt(reset)
node _T_687 = eq(_T_686, UInt<1>(0h0))
when _T_687 :
node _T_688 = eq(sink_ok, UInt<1>(0h0))
when _T_688 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_690 = asUInt(reset)
node _T_691 = eq(_T_690, UInt<1>(0h0))
when _T_691 :
node _T_692 = eq(_T_689, UInt<1>(0h0))
when _T_692 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_689, UInt<1>(0h1), "") : assert_67
node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_694 = asUInt(reset)
node _T_695 = eq(_T_694, UInt<1>(0h0))
when _T_695 :
node _T_696 = eq(_T_693, UInt<1>(0h0))
when _T_696 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_693, UInt<1>(0h1), "") : assert_68
node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_697, UInt<1>(0h1), "") : assert_69
node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_702 = or(_T_701, io.in.d.bits.corrupt)
node _T_703 = asUInt(reset)
node _T_704 = eq(_T_703, UInt<1>(0h0))
when _T_704 :
node _T_705 = eq(_T_702, UInt<1>(0h0))
when _T_705 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_702, UInt<1>(0h1), "") : assert_70
node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_707 = or(UInt<1>(0h1), _T_706)
node _T_708 = asUInt(reset)
node _T_709 = eq(_T_708, UInt<1>(0h0))
when _T_709 :
node _T_710 = eq(_T_707, UInt<1>(0h0))
when _T_710 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_707, UInt<1>(0h1), "") : assert_71
node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_711 :
node _T_712 = asUInt(reset)
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_714 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_716 = asUInt(reset)
node _T_717 = eq(_T_716, UInt<1>(0h0))
when _T_717 :
node _T_718 = eq(_T_715, UInt<1>(0h0))
when _T_718 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_715, UInt<1>(0h1), "") : assert_73
node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_719, UInt<1>(0h1), "") : assert_74
node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_724 = or(UInt<1>(0h1), _T_723)
node _T_725 = asUInt(reset)
node _T_726 = eq(_T_725, UInt<1>(0h0))
when _T_726 :
node _T_727 = eq(_T_724, UInt<1>(0h0))
when _T_727 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_724, UInt<1>(0h1), "") : assert_75
node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_728 :
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_733 = asUInt(reset)
node _T_734 = eq(_T_733, UInt<1>(0h0))
when _T_734 :
node _T_735 = eq(_T_732, UInt<1>(0h0))
when _T_735 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_732, UInt<1>(0h1), "") : assert_77
node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_737 = or(_T_736, io.in.d.bits.corrupt)
node _T_738 = asUInt(reset)
node _T_739 = eq(_T_738, UInt<1>(0h0))
when _T_739 :
node _T_740 = eq(_T_737, UInt<1>(0h0))
when _T_740 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_737, UInt<1>(0h1), "") : assert_78
node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_742 = or(UInt<1>(0h1), _T_741)
node _T_743 = asUInt(reset)
node _T_744 = eq(_T_743, UInt<1>(0h0))
when _T_744 :
node _T_745 = eq(_T_742, UInt<1>(0h0))
when _T_745 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_742, UInt<1>(0h1), "") : assert_79
node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_746 :
node _T_747 = asUInt(reset)
node _T_748 = eq(_T_747, UInt<1>(0h0))
when _T_748 :
node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_749 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_751 = asUInt(reset)
node _T_752 = eq(_T_751, UInt<1>(0h0))
when _T_752 :
node _T_753 = eq(_T_750, UInt<1>(0h0))
when _T_753 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_750, UInt<1>(0h1), "") : assert_81
node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_755 = asUInt(reset)
node _T_756 = eq(_T_755, UInt<1>(0h0))
when _T_756 :
node _T_757 = eq(_T_754, UInt<1>(0h0))
when _T_757 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_754, UInt<1>(0h1), "") : assert_82
node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_759 = or(UInt<1>(0h1), _T_758)
node _T_760 = asUInt(reset)
node _T_761 = eq(_T_760, UInt<1>(0h0))
when _T_761 :
node _T_762 = eq(_T_759, UInt<1>(0h0))
when _T_762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_759, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<9>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_764 = asUInt(reset)
node _T_765 = eq(_T_764, UInt<1>(0h0))
when _T_765 :
node _T_766 = eq(_T_763, UInt<1>(0h0))
when _T_766 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_763, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<9>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(_T_767, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_767, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_772 = asUInt(reset)
node _T_773 = eq(_T_772, UInt<1>(0h0))
when _T_773 :
node _T_774 = eq(_T_771, UInt<1>(0h0))
when _T_774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_771, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_775 = eq(a_first, UInt<1>(0h0))
node _T_776 = and(io.in.a.valid, _T_775)
when _T_776 :
node _T_777 = eq(io.in.a.bits.opcode, opcode)
node _T_778 = asUInt(reset)
node _T_779 = eq(_T_778, UInt<1>(0h0))
when _T_779 :
node _T_780 = eq(_T_777, UInt<1>(0h0))
when _T_780 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_777, UInt<1>(0h1), "") : assert_87
node _T_781 = eq(io.in.a.bits.param, param)
node _T_782 = asUInt(reset)
node _T_783 = eq(_T_782, UInt<1>(0h0))
when _T_783 :
node _T_784 = eq(_T_781, UInt<1>(0h0))
when _T_784 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_781, UInt<1>(0h1), "") : assert_88
node _T_785 = eq(io.in.a.bits.size, size)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_785, UInt<1>(0h1), "") : assert_89
node _T_789 = eq(io.in.a.bits.source, source)
node _T_790 = asUInt(reset)
node _T_791 = eq(_T_790, UInt<1>(0h0))
when _T_791 :
node _T_792 = eq(_T_789, UInt<1>(0h0))
when _T_792 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_789, UInt<1>(0h1), "") : assert_90
node _T_793 = eq(io.in.a.bits.address, address)
node _T_794 = asUInt(reset)
node _T_795 = eq(_T_794, UInt<1>(0h0))
when _T_795 :
node _T_796 = eq(_T_793, UInt<1>(0h0))
when _T_796 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_793, UInt<1>(0h1), "") : assert_91
node _T_797 = and(io.in.a.ready, io.in.a.valid)
node _T_798 = and(_T_797, a_first)
when _T_798 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_799 = eq(d_first, UInt<1>(0h0))
node _T_800 = and(io.in.d.valid, _T_799)
when _T_800 :
node _T_801 = eq(io.in.d.bits.opcode, opcode_1)
node _T_802 = asUInt(reset)
node _T_803 = eq(_T_802, UInt<1>(0h0))
when _T_803 :
node _T_804 = eq(_T_801, UInt<1>(0h0))
when _T_804 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_801, UInt<1>(0h1), "") : assert_92
node _T_805 = eq(io.in.d.bits.param, param_1)
node _T_806 = asUInt(reset)
node _T_807 = eq(_T_806, UInt<1>(0h0))
when _T_807 :
node _T_808 = eq(_T_805, UInt<1>(0h0))
when _T_808 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_805, UInt<1>(0h1), "") : assert_93
node _T_809 = eq(io.in.d.bits.size, size_1)
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(_T_809, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_809, UInt<1>(0h1), "") : assert_94
node _T_813 = eq(io.in.d.bits.source, source_1)
node _T_814 = asUInt(reset)
node _T_815 = eq(_T_814, UInt<1>(0h0))
when _T_815 :
node _T_816 = eq(_T_813, UInt<1>(0h0))
when _T_816 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_813, UInt<1>(0h1), "") : assert_95
node _T_817 = eq(io.in.d.bits.sink, sink)
node _T_818 = asUInt(reset)
node _T_819 = eq(_T_818, UInt<1>(0h0))
when _T_819 :
node _T_820 = eq(_T_817, UInt<1>(0h0))
when _T_820 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_817, UInt<1>(0h1), "") : assert_96
node _T_821 = eq(io.in.d.bits.denied, denied)
node _T_822 = asUInt(reset)
node _T_823 = eq(_T_822, UInt<1>(0h0))
when _T_823 :
node _T_824 = eq(_T_821, UInt<1>(0h0))
when _T_824 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_821, UInt<1>(0h1), "") : assert_97
node _T_825 = and(io.in.d.ready, io.in.d.valid)
node _T_826 = and(_T_825, d_first)
when _T_826 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<4>
connect a_sizes_set, UInt<4>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_827 = and(io.in.a.valid, a_first_1)
node _T_828 = and(_T_827, UInt<1>(0h1))
when _T_828 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_829 = and(io.in.a.ready, io.in.a.valid)
node _T_830 = and(_T_829, a_first_1)
node _T_831 = and(_T_830, UInt<1>(0h1))
when _T_831 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_832 = dshr(inflight, io.in.a.bits.source)
node _T_833 = bits(_T_832, 0, 0)
node _T_834 = eq(_T_833, UInt<1>(0h0))
node _T_835 = asUInt(reset)
node _T_836 = eq(_T_835, UInt<1>(0h0))
when _T_836 :
node _T_837 = eq(_T_834, UInt<1>(0h0))
when _T_837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_834, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<4>
connect d_sizes_clr, UInt<4>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_838 = and(io.in.d.valid, d_first_1)
node _T_839 = and(_T_838, UInt<1>(0h1))
node _T_840 = eq(d_release_ack, UInt<1>(0h0))
node _T_841 = and(_T_839, _T_840)
when _T_841 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_842 = and(io.in.d.ready, io.in.d.valid)
node _T_843 = and(_T_842, d_first_1)
node _T_844 = and(_T_843, UInt<1>(0h1))
node _T_845 = eq(d_release_ack, UInt<1>(0h0))
node _T_846 = and(_T_844, _T_845)
when _T_846 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_847 = and(io.in.d.valid, d_first_1)
node _T_848 = and(_T_847, UInt<1>(0h1))
node _T_849 = eq(d_release_ack, UInt<1>(0h0))
node _T_850 = and(_T_848, _T_849)
when _T_850 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_851 = dshr(inflight, io.in.d.bits.source)
node _T_852 = bits(_T_851, 0, 0)
node _T_853 = or(_T_852, same_cycle_resp)
node _T_854 = asUInt(reset)
node _T_855 = eq(_T_854, UInt<1>(0h0))
when _T_855 :
node _T_856 = eq(_T_853, UInt<1>(0h0))
when _T_856 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_853, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_859 = or(_T_857, _T_858)
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(_T_859, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_859, UInt<1>(0h1), "") : assert_100
node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_864 = asUInt(reset)
node _T_865 = eq(_T_864, UInt<1>(0h0))
when _T_865 :
node _T_866 = eq(_T_863, UInt<1>(0h0))
when _T_866 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_863, UInt<1>(0h1), "") : assert_101
else :
node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_869 = or(_T_867, _T_868)
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_869, UInt<1>(0h1), "") : assert_102
node _T_873 = eq(io.in.d.bits.size, a_size_lookup)
node _T_874 = asUInt(reset)
node _T_875 = eq(_T_874, UInt<1>(0h0))
when _T_875 :
node _T_876 = eq(_T_873, UInt<1>(0h0))
when _T_876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_873, UInt<1>(0h1), "") : assert_103
node _T_877 = and(io.in.d.valid, d_first_1)
node _T_878 = and(_T_877, a_first_1)
node _T_879 = and(_T_878, io.in.a.valid)
node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_881 = and(_T_879, _T_880)
node _T_882 = eq(d_release_ack, UInt<1>(0h0))
node _T_883 = and(_T_881, _T_882)
when _T_883 :
node _T_884 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_885 = or(_T_884, io.in.a.ready)
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(_T_885, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_885, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_94
node _T_889 = orr(inflight)
node _T_890 = eq(_T_889, UInt<1>(0h0))
node _T_891 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_892 = or(_T_890, _T_891)
node _T_893 = lt(watchdog, plusarg_reader.out)
node _T_894 = or(_T_892, _T_893)
node _T_895 = asUInt(reset)
node _T_896 = eq(_T_895, UInt<1>(0h0))
when _T_896 :
node _T_897 = eq(_T_894, UInt<1>(0h0))
when _T_897 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_894, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_898 = and(io.in.a.ready, io.in.a.valid)
node _T_899 = and(io.in.d.ready, io.in.d.valid)
node _T_900 = or(_T_898, _T_899)
when _T_900 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<32>(0h0)
connect _c_first_WIRE.bits.address, UInt<9>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<4>
connect c_sizes_set, UInt<4>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.address, UInt<9>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_901 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<9>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_902 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_903 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_904 = and(_T_902, _T_903)
node _T_905 = and(_T_901, _T_904)
when _T_905 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<9>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_906 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_907 = and(_T_906, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<9>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_908 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_909 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_910 = and(_T_908, _T_909)
node _T_911 = and(_T_907, _T_910)
when _T_911 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<32>(0h0)
connect _WIRE_14.bits.address, UInt<9>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_912 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_913 = bits(_T_912, 0, 0)
node _T_914 = eq(_T_913, UInt<1>(0h0))
node _T_915 = asUInt(reset)
node _T_916 = eq(_T_915, UInt<1>(0h0))
when _T_916 :
node _T_917 = eq(_T_914, UInt<1>(0h0))
when _T_917 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_914, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<4>
connect d_sizes_clr_1, UInt<4>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_918 = and(io.in.d.valid, d_first_2)
node _T_919 = and(_T_918, UInt<1>(0h1))
node _T_920 = and(_T_919, d_release_ack_1)
when _T_920 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_921 = and(io.in.d.ready, io.in.d.valid)
node _T_922 = and(_T_921, d_first_2)
node _T_923 = and(_T_922, UInt<1>(0h1))
node _T_924 = and(_T_923, d_release_ack_1)
when _T_924 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_925 = and(io.in.d.valid, d_first_2)
node _T_926 = and(_T_925, UInt<1>(0h1))
node _T_927 = and(_T_926, d_release_ack_1)
when _T_927 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_928 = dshr(inflight_1, io.in.d.bits.source)
node _T_929 = bits(_T_928, 0, 0)
node _T_930 = or(_T_929, same_cycle_resp_1)
node _T_931 = asUInt(reset)
node _T_932 = eq(_T_931, UInt<1>(0h0))
when _T_932 :
node _T_933 = eq(_T_930, UInt<1>(0h0))
when _T_933 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_930, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<32>(0h0)
connect _WIRE_16.bits.address, UInt<9>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_934 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_935 = asUInt(reset)
node _T_936 = eq(_T_935, UInt<1>(0h0))
when _T_936 :
node _T_937 = eq(_T_934, UInt<1>(0h0))
when _T_937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_934, UInt<1>(0h1), "") : assert_108
else :
node _T_938 = eq(io.in.d.bits.size, c_size_lookup)
node _T_939 = asUInt(reset)
node _T_940 = eq(_T_939, UInt<1>(0h0))
when _T_940 :
node _T_941 = eq(_T_938, UInt<1>(0h0))
when _T_941 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_938, UInt<1>(0h1), "") : assert_109
node _T_942 = and(io.in.d.valid, d_first_2)
node _T_943 = and(_T_942, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.address, UInt<9>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_944 = and(_T_943, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<9>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_945 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_946 = and(_T_944, _T_945)
node _T_947 = and(_T_946, d_release_ack_1)
node _T_948 = eq(c_probe_ack, UInt<1>(0h0))
node _T_949 = and(_T_947, _T_948)
when _T_949 :
node _T_950 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<32>(0h0)
connect _WIRE_22.bits.address, UInt<9>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_951 = or(_T_950, _WIRE_23.ready)
node _T_952 = asUInt(reset)
node _T_953 = eq(_T_952, UInt<1>(0h0))
when _T_953 :
node _T_954 = eq(_T_951, UInt<1>(0h0))
when _T_954 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_951, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_95
node _T_955 = orr(inflight_1)
node _T_956 = eq(_T_955, UInt<1>(0h0))
node _T_957 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_958 = or(_T_956, _T_957)
node _T_959 = lt(watchdog_1, plusarg_reader_1.out)
node _T_960 = or(_T_958, _T_959)
node _T_961 = asUInt(reset)
node _T_962 = eq(_T_961, UInt<1>(0h0))
when _T_962 :
node _T_963 = eq(_T_960, UInt<1>(0h0))
when _T_963 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_960, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.address, UInt<9>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_964 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_965 = and(io.in.d.ready, io.in.d.valid)
node _T_966 = or(_T_964, _T_965)
when _T_966 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_47( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [31:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49]
wire mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size = 1'h1; // @[Misc.scala:209:26]
wire mask_acc = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46]
wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46]
wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46]
wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7]
wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7]
wire [3:0] mask = 4'hF; // @[Misc.scala:222:10]
wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12]
wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27]
wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7]
wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire _T_898 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_898; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_898; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [8:0] address; // @[Monitor.scala:391:22]
wire _T_966 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_966; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_966; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_966; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71]
wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [3:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [3:0] _GEN_0 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69]
wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :641:65]
wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_0; // @[Monitor.scala:637:69, :680:101]
wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_0; // @[Monitor.scala:637:69, :681:99]
wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :749:69]
wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :750:67]
wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_0; // @[Monitor.scala:637:69, :790:101]
wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_0; // @[Monitor.scala:637:69, :791:99]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_828 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_828; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_828; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_898 & a_first_1; // @[Decoupled.scala:51:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]
assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46]
wire _T_877 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [1:0] _GEN_2 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_3 = 2'h1 << _GEN_2; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_3; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_3; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_3; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_877 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_846 = _T_966 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_846 & _d_clr_T[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_846 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [30:0] _d_sizes_clr_T_5 = 31'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_846 ? _d_sizes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_942 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_942 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35]
wire _T_924 = _T_966 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_924 & _d_clr_T_1[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_924 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [30:0] _d_sizes_clr_T_11 = 31'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_924 ? _d_sizes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module MulFullRawFN_47 :
output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<48>}}
node _notSigNaN_invalidExc_T = and(io.a.isInf, io.b.isZero)
node _notSigNaN_invalidExc_T_1 = and(io.a.isZero, io.b.isInf)
node notSigNaN_invalidExc = or(_notSigNaN_invalidExc_T, _notSigNaN_invalidExc_T_1)
node notNaN_isInfOut = or(io.a.isInf, io.b.isInf)
node notNaN_isZeroOut = or(io.a.isZero, io.b.isZero)
node notNaN_signOut = xor(io.a.sign, io.b.sign)
node _common_sExpOut_T = add(io.a.sExp, io.b.sExp)
node _common_sExpOut_T_1 = tail(_common_sExpOut_T, 1)
node _common_sExpOut_T_2 = asSInt(_common_sExpOut_T_1)
node _common_sExpOut_T_3 = sub(_common_sExpOut_T_2, asSInt(UInt<10>(0h100)))
node _common_sExpOut_T_4 = tail(_common_sExpOut_T_3, 1)
node common_sExpOut = asSInt(_common_sExpOut_T_4)
node _common_sigOut_T = mul(io.a.sig, io.b.sig)
node common_sigOut = bits(_common_sigOut_T, 47, 0)
node _io_invalidExc_T = bits(io.a.sig, 22, 22)
node _io_invalidExc_T_1 = eq(_io_invalidExc_T, UInt<1>(0h0))
node _io_invalidExc_T_2 = and(io.a.isNaN, _io_invalidExc_T_1)
node _io_invalidExc_T_3 = bits(io.b.sig, 22, 22)
node _io_invalidExc_T_4 = eq(_io_invalidExc_T_3, UInt<1>(0h0))
node _io_invalidExc_T_5 = and(io.b.isNaN, _io_invalidExc_T_4)
node _io_invalidExc_T_6 = or(_io_invalidExc_T_2, _io_invalidExc_T_5)
node _io_invalidExc_T_7 = or(_io_invalidExc_T_6, notSigNaN_invalidExc)
connect io.invalidExc, _io_invalidExc_T_7
connect io.rawOut.isInf, notNaN_isInfOut
connect io.rawOut.isZero, notNaN_isZeroOut
connect io.rawOut.sExp, common_sExpOut
node _io_rawOut_isNaN_T = or(io.a.isNaN, io.b.isNaN)
connect io.rawOut.isNaN, _io_rawOut_isNaN_T
connect io.rawOut.sign, notNaN_signOut
connect io.rawOut.sig, common_sigOut | module MulFullRawFN_47( // @[MulRecFN.scala:47:7]
input io_a_isNaN, // @[MulRecFN.scala:49:16]
input io_a_isInf, // @[MulRecFN.scala:49:16]
input io_a_isZero, // @[MulRecFN.scala:49:16]
input io_a_sign, // @[MulRecFN.scala:49:16]
input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16]
input [24:0] io_a_sig, // @[MulRecFN.scala:49:16]
input io_b_isNaN, // @[MulRecFN.scala:49:16]
input io_b_isInf, // @[MulRecFN.scala:49:16]
input io_b_isZero, // @[MulRecFN.scala:49:16]
input io_b_sign, // @[MulRecFN.scala:49:16]
input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16]
input [24:0] io_b_sig, // @[MulRecFN.scala:49:16]
output io_invalidExc, // @[MulRecFN.scala:49:16]
output io_rawOut_isNaN, // @[MulRecFN.scala:49:16]
output io_rawOut_isInf, // @[MulRecFN.scala:49:16]
output io_rawOut_isZero, // @[MulRecFN.scala:49:16]
output io_rawOut_sign, // @[MulRecFN.scala:49:16]
output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16]
output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16]
);
wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7]
wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7]
wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7]
wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7]
wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7]
wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7]
wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7]
wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7]
wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7]
wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7]
wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7]
wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7]
wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71]
wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35]
wire notNaN_isInfOut; // @[MulRecFN.scala:59:38]
wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40]
wire notNaN_signOut; // @[MulRecFN.scala:61:36]
wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48]
wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46]
wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7]
wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7]
wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7]
wire io_invalidExc_0; // @[MulRecFN.scala:47:7]
wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44]
wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76]
wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T | _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}]
assign notNaN_isInfOut = io_a_isInf_0 | io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38]
assign notNaN_isZeroOut = io_a_isZero_0 | io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40]
assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40]
assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36]
assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36]
wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36]
wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36]
wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36]
wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}]
wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48]
assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48]
assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48]
wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35]
assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}]
assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46]
wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56]
wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}]
wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}]
wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56]
wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}]
wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}]
wire _io_invalidExc_T_6 = _io_invalidExc_T_2 | _io_invalidExc_T_5; // @[common.scala:82:46]
assign _io_invalidExc_T_7 = _io_invalidExc_T_6 | notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}]
assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71]
assign _io_rawOut_isNaN_T = io_a_isNaN_0 | io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35]
assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLDToBeat_serial_tl_0_a64d64s8k8z8c :
input clock : Clock
input reset : Reset
output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, sink : UInt<8>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, beat : { flip ready : UInt<1>, valid : UInt<1>, bits : { payload : UInt<65>, head : UInt<1>, tail : UInt<1>}}}
inst q of Queue1_TLBundleD_a64d64s8k8z8c
connect q.clock, clock
connect q.reset, reset
connect q.io.enq, io.protocol
wire has_body : UInt<1>
node _head_T = and(q.io.deq.ready, q.io.deq.valid)
node _head_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size)
node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 11, 0)
node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1)
node head_beats1_decode = shr(_head_beats1_decode_T_2, 3)
node head_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0)
node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0))
regreset head_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _head_counter1_T = sub(head_counter, UInt<1>(0h1))
node head_counter1 = tail(_head_counter1_T, 1)
node head = eq(head_counter, UInt<1>(0h0))
node _head_last_T = eq(head_counter, UInt<1>(0h1))
node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0))
node head_last = or(_head_last_T, _head_last_T_1)
node head_done = and(head_last, _head_T)
node _head_count_T = not(head_counter1)
node head_count = and(head_beats1, _head_count_T)
when _head_T :
node _head_counter_T = mux(head, head_beats1, head_counter1)
connect head_counter, _head_counter_T
node _tail_T = and(q.io.deq.ready, q.io.deq.valid)
node _tail_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size)
node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 11, 0)
node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1)
node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 3)
node tail_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0)
node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0))
regreset tail_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1))
node tail_counter1 = tail(_tail_counter1_T, 1)
node tail_first = eq(tail_counter, UInt<1>(0h0))
node _tail_last_T = eq(tail_counter, UInt<1>(0h1))
node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0))
node tail = or(_tail_last_T, _tail_last_T_1)
node tail_done = and(tail, _tail_T)
node _tail_count_T = not(tail_counter1)
node tail_count = and(tail_beats1, _tail_count_T)
when _tail_T :
node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1)
connect tail_counter, _tail_counter_T
node body = cat(q.io.deq.bits.data, q.io.deq.bits.corrupt)
node const_lo_hi = cat(q.io.deq.bits.source, q.io.deq.bits.sink)
node const_lo = cat(const_lo_hi, q.io.deq.bits.denied)
node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param)
node const_hi = cat(const_hi_hi, q.io.deq.bits.size)
node const = cat(const_hi, const_lo)
regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0)
connect io.beat.valid, q.io.deq.valid
node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0))
node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T)
node _q_io_deq_ready_T_2 = and(io.beat.ready, _q_io_deq_ready_T_1)
connect q.io.deq.ready, _q_io_deq_ready_T_2
node _io_beat_bits_head_T = eq(is_body, UInt<1>(0h0))
node _io_beat_bits_head_T_1 = and(head, _io_beat_bits_head_T)
connect io.beat.bits.head, _io_beat_bits_head_T_1
node _io_beat_bits_tail_T = eq(has_body, UInt<1>(0h0))
node _io_beat_bits_tail_T_1 = or(is_body, _io_beat_bits_tail_T)
node _io_beat_bits_tail_T_2 = and(tail, _io_beat_bits_tail_T_1)
connect io.beat.bits.tail, _io_beat_bits_tail_T_2
node _io_beat_bits_payload_T = mux(is_body, body, const)
connect io.beat.bits.payload, _io_beat_bits_payload_T
node _T = and(io.beat.ready, io.beat.valid)
node _T_1 = and(_T, io.beat.bits.head)
when _T_1 :
connect is_body, UInt<1>(0h1)
node _T_2 = and(io.beat.ready, io.beat.valid)
node _T_3 = and(_T_2, io.beat.bits.tail)
when _T_3 :
connect is_body, UInt<1>(0h0)
node has_body_opdata = bits(q.io.deq.bits.opcode, 0, 0)
connect has_body, has_body_opdata | module TLDToBeat_serial_tl_0_a64d64s8k8z8c( // @[TLChannelCompactor.scala:130:7]
input clock, // @[TLChannelCompactor.scala:130:7]
input reset, // @[TLChannelCompactor.scala:130:7]
output io_protocol_ready, // @[TLChannelCompactor.scala:40:14]
input io_protocol_valid, // @[TLChannelCompactor.scala:40:14]
input [2:0] io_protocol_bits_opcode, // @[TLChannelCompactor.scala:40:14]
input [1:0] io_protocol_bits_param, // @[TLChannelCompactor.scala:40:14]
input [7:0] io_protocol_bits_size, // @[TLChannelCompactor.scala:40:14]
input [7:0] io_protocol_bits_source, // @[TLChannelCompactor.scala:40:14]
input [7:0] io_protocol_bits_sink, // @[TLChannelCompactor.scala:40:14]
input io_protocol_bits_denied, // @[TLChannelCompactor.scala:40:14]
input [63:0] io_protocol_bits_data, // @[TLChannelCompactor.scala:40:14]
input io_protocol_bits_corrupt, // @[TLChannelCompactor.scala:40:14]
input io_beat_ready, // @[TLChannelCompactor.scala:40:14]
output io_beat_valid, // @[TLChannelCompactor.scala:40:14]
output [64:0] io_beat_bits_payload, // @[TLChannelCompactor.scala:40:14]
output io_beat_bits_head, // @[TLChannelCompactor.scala:40:14]
output io_beat_bits_tail // @[TLChannelCompactor.scala:40:14]
);
wire _q_io_deq_valid; // @[TLChannelCompactor.scala:47:17]
wire [2:0] _q_io_deq_bits_opcode; // @[TLChannelCompactor.scala:47:17]
wire [1:0] _q_io_deq_bits_param; // @[TLChannelCompactor.scala:47:17]
wire [7:0] _q_io_deq_bits_size; // @[TLChannelCompactor.scala:47:17]
wire [7:0] _q_io_deq_bits_source; // @[TLChannelCompactor.scala:47:17]
wire [7:0] _q_io_deq_bits_sink; // @[TLChannelCompactor.scala:47:17]
wire _q_io_deq_bits_denied; // @[TLChannelCompactor.scala:47:17]
wire [63:0] _q_io_deq_bits_data; // @[TLChannelCompactor.scala:47:17]
wire _q_io_deq_bits_corrupt; // @[TLChannelCompactor.scala:47:17]
wire [266:0] _tail_beats1_decode_T = 267'hFFF << _q_io_deq_bits_size; // @[TLChannelCompactor.scala:47:17]
reg [8:0] head_counter; // @[Edges.scala:229:27]
wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire [8:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:3]) : 9'h0; // @[TLChannelCompactor.scala:47:17]
reg [8:0] tail_counter; // @[Edges.scala:229:27]
reg is_body; // @[TLChannelCompactor.scala:60:24]
wire q_io_deq_ready = io_beat_ready & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[TLChannelCompactor.scala:47:17, :60:24, :62:{35,47,50}]
wire io_beat_bits_head_0 = head & ~is_body; // @[TLChannelCompactor.scala:60:24, :64:{35,38}]
wire io_beat_bits_tail_0 = (tail_counter == 9'h1 | tail_beats1 == 9'h0) & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[TLChannelCompactor.scala:47:17, :60:24, :62:50, :65:{35,47}]
wire _GEN = io_beat_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TLChannelCompactor.scala:130:7]
if (reset) begin // @[TLChannelCompactor.scala:130:7]
head_counter <= 9'h0; // @[Edges.scala:229:27]
tail_counter <= 9'h0; // @[Edges.scala:229:27]
is_body <= 1'h0; // @[TLChannelCompactor.scala:60:24, :130:7]
end
else begin // @[TLChannelCompactor.scala:130:7]
if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35]
head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:3]) : 9'h0) : head_counter - 9'h1; // @[TLChannelCompactor.scala:47:17]
tail_counter <= tail_counter == 9'h0 ? tail_beats1 : tail_counter - 9'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21]
end
is_body <= ~(_GEN & io_beat_bits_tail_0) & (_GEN & io_beat_bits_head_0 | is_body); // @[Decoupled.scala:51:35]
end
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_24 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<4>, q : UInt<4>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_231
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
node _output_T_2 = asAsyncReset(reset)
node _output_T_3 = bits(io.d, 1, 1)
inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_232
connect output_chain_1.clock, clock
connect output_chain_1.reset, _output_T_2
connect output_chain_1.io.d, _output_T_3
wire output_1 : UInt<1>
connect output_1, output_chain_1.io.q
node _output_T_4 = asAsyncReset(reset)
node _output_T_5 = bits(io.d, 2, 2)
inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_233
connect output_chain_2.clock, clock
connect output_chain_2.reset, _output_T_4
connect output_chain_2.io.d, _output_T_5
wire output_2 : UInt<1>
connect output_2, output_chain_2.io.q
node _output_T_6 = asAsyncReset(reset)
node _output_T_7 = bits(io.d, 3, 3)
inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_234
connect output_chain_3.clock, clock
connect output_chain_3.reset, _output_T_6
connect output_chain_3.io.d, _output_T_7
wire output_3 : UInt<1>
connect output_3, output_chain_3.io.q
node io_q_lo = cat(output_1, output_0)
node io_q_hi = cat(output_3, output_2)
node _io_q_T = cat(io_q_hi, io_q_lo)
connect io.q, _io_q_T | module AsyncResetSynchronizerShiftReg_w4_d3_i0_24( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_231 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_232 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_233 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_234 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_53 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<8>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 7, 0)
node _source_ok_T = shr(io.in.a.bits.source, 8)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<8>(0h9f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<8>(0h0))
node uncommonBits = bits(_uncommonBits_T, 7, 0)
node _T_4 = shr(io.in.a.bits.source, 8)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<8>(0h9f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<8>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 7, 0)
node _T_24 = shr(io.in.a.bits.source, 8)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<8>(0h9f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<8>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 7, 0)
node _T_86 = shr(io.in.a.bits.source, 8)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<8>(0h9f))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<8>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 7, 0)
node _T_152 = shr(io.in.a.bits.source, 8)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<8>(0h9f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<8>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 7, 0)
node _T_199 = shr(io.in.a.bits.source, 8)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<8>(0h9f))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<8>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 7, 0)
node _T_240 = shr(io.in.a.bits.source, 8)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<8>(0h9f))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<8>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 7, 0)
node _T_283 = shr(io.in.a.bits.source, 8)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<8>(0h9f))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<8>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 7, 0)
node _T_321 = shr(io.in.a.bits.source, 8)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<8>(0h9f))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<8>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 7, 0)
node _T_359 = shr(io.in.a.bits.source, 8)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<8>(0h9f))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<8>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 7, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 8)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<8>(0h9f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<28>(0h0)
connect _WIRE.bits.source, UInt<8>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<28>(0h0)
connect _WIRE_2.bits.source, UInt<8>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<160>, clock, reset, UInt<160>(0h0)
regreset inflight_opcodes : UInt<640>, clock, reset, UInt<640>(0h0)
regreset inflight_sizes : UInt<640>, clock, reset, UInt<640>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<160>
connect a_set, UInt<160>(0h0)
wire a_set_wo_ready : UInt<160>
connect a_set_wo_ready, UInt<160>(0h0)
wire a_opcodes_set : UInt<640>
connect a_opcodes_set, UInt<640>(0h0)
wire a_sizes_set : UInt<640>
connect a_sizes_set, UInt<640>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<160>
connect d_clr, UInt<160>(0h0)
wire d_clr_wo_ready : UInt<160>
connect d_clr_wo_ready, UInt<160>(0h0)
wire d_opcodes_clr : UInt<640>
connect d_opcodes_clr, UInt<640>(0h0)
wire d_sizes_clr : UInt<640>
connect d_sizes_clr, UInt<640>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_657 = orr(a_set_wo_ready)
node _T_658 = eq(_T_657, UInt<1>(0h0))
node _T_659 = or(_T_656, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_659, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_107
node _T_663 = orr(inflight)
node _T_664 = eq(_T_663, UInt<1>(0h0))
node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_666 = or(_T_664, _T_665)
node _T_667 = lt(watchdog, plusarg_reader.out)
node _T_668 = or(_T_666, _T_667)
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(_T_668, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_668, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_672 = and(io.in.a.ready, io.in.a.valid)
node _T_673 = and(io.in.d.ready, io.in.d.valid)
node _T_674 = or(_T_672, _T_673)
when _T_674 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<160>, clock, reset, UInt<160>(0h0)
regreset inflight_opcodes_1 : UInt<640>, clock, reset, UInt<640>(0h0)
regreset inflight_sizes_1 : UInt<640>, clock, reset, UInt<640>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<28>(0h0)
connect _c_first_WIRE.bits.source, UInt<8>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<160>
connect c_set, UInt<160>(0h0)
wire c_set_wo_ready : UInt<160>
connect c_set_wo_ready, UInt<160>(0h0)
wire c_opcodes_set : UInt<640>
connect c_opcodes_set, UInt<640>(0h0)
wire c_sizes_set : UInt<640>
connect c_sizes_set, UInt<640>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<28>(0h0)
connect _WIRE_6.bits.source, UInt<8>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_675 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<28>(0h0)
connect _WIRE_8.bits.source, UInt<8>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_678 = and(_T_676, _T_677)
node _T_679 = and(_T_675, _T_678)
when _T_679 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<28>(0h0)
connect _WIRE_10.bits.source, UInt<8>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_681 = and(_T_680, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<28>(0h0)
connect _WIRE_12.bits.source, UInt<8>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_684 = and(_T_682, _T_683)
node _T_685 = and(_T_681, _T_684)
when _T_685 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<28>(0h0)
connect _WIRE_14.bits.source, UInt<8>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_686 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_687 = bits(_T_686, 0, 0)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_688, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<160>
connect d_clr_1, UInt<160>(0h0)
wire d_clr_wo_ready_1 : UInt<160>
connect d_clr_wo_ready_1, UInt<160>(0h0)
wire d_opcodes_clr_1 : UInt<640>
connect d_opcodes_clr_1, UInt<640>(0h0)
wire d_sizes_clr_1 : UInt<640>
connect d_sizes_clr_1, UInt<640>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_695 = and(io.in.d.ready, io.in.d.valid)
node _T_696 = and(_T_695, d_first_2)
node _T_697 = and(_T_696, UInt<1>(0h1))
node _T_698 = and(_T_697, d_release_ack_1)
when _T_698 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_699 = and(io.in.d.valid, d_first_2)
node _T_700 = and(_T_699, UInt<1>(0h1))
node _T_701 = and(_T_700, d_release_ack_1)
when _T_701 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_702 = dshr(inflight_1, io.in.d.bits.source)
node _T_703 = bits(_T_702, 0, 0)
node _T_704 = or(_T_703, same_cycle_resp_1)
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_704, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<28>(0h0)
connect _WIRE_16.bits.source, UInt<8>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_709 = asUInt(reset)
node _T_710 = eq(_T_709, UInt<1>(0h0))
when _T_710 :
node _T_711 = eq(_T_708, UInt<1>(0h0))
when _T_711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_708, UInt<1>(0h1), "") : assert_109
else :
node _T_712 = eq(io.in.d.bits.size, c_size_lookup)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _T_716 = and(io.in.d.valid, d_first_2)
node _T_717 = and(_T_716, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<28>(0h0)
connect _WIRE_18.bits.source, UInt<8>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_718 = and(_T_717, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<28>(0h0)
connect _WIRE_20.bits.source, UInt<8>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_720 = and(_T_718, _T_719)
node _T_721 = and(_T_720, d_release_ack_1)
node _T_722 = eq(c_probe_ack, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
when _T_723 :
node _T_724 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<28>(0h0)
connect _WIRE_22.bits.source, UInt<8>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_725 = or(_T_724, _WIRE_23.ready)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_725, UInt<1>(0h1), "") : assert_111
node _T_729 = orr(c_set_wo_ready)
when _T_729 :
node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_730, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_108
node _T_734 = orr(inflight_1)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_737 = or(_T_735, _T_736)
node _T_738 = lt(watchdog_1, plusarg_reader_1.out)
node _T_739 = or(_T_737, _T_738)
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_739, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<28>(0h0)
connect _WIRE_24.bits.source, UInt<8>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_744 = and(io.in.d.ready, io.in.d.valid)
node _T_745 = or(_T_743, _T_744)
when _T_745 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_53( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg [159:0] inflight; // @[Monitor.scala:614:27]
reg [639:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [639:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire [255:0] _GEN = {248'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_0 = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [255:0] _GEN_2 = {248'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [159:0] inflight_1; // @[Monitor.scala:726:35]
reg [639:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module BreakpointUnit_9 :
input clock : Clock
input reset : Reset
output io : { flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[0], flip pc : UInt<39>, flip ea : UInt<39>, flip mcontext : UInt<0>, flip scontext : UInt<0>, xcpt_if : UInt<1>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, debug_if : UInt<1>, debug_ld : UInt<1>, debug_st : UInt<1>, bpwatch : { valid : UInt<1>[1], rvalid : UInt<1>[1], wvalid : UInt<1>[1], ivalid : UInt<1>[1], action : UInt<3>}[0]}
connect io.xcpt_if, UInt<1>(0h0)
connect io.xcpt_ld, UInt<1>(0h0)
connect io.xcpt_st, UInt<1>(0h0)
connect io.debug_if, UInt<1>(0h0)
connect io.debug_ld, UInt<1>(0h0)
connect io.debug_st, UInt<1>(0h0) | module BreakpointUnit_9( // @[Breakpoint.scala:79:7]
input clock, // @[Breakpoint.scala:79:7]
input reset, // @[Breakpoint.scala:79:7]
input io_status_debug, // @[Breakpoint.scala:80:14]
input io_status_cease, // @[Breakpoint.scala:80:14]
input io_status_wfi, // @[Breakpoint.scala:80:14]
input [1:0] io_status_dprv, // @[Breakpoint.scala:80:14]
input io_status_dv, // @[Breakpoint.scala:80:14]
input [1:0] io_status_prv, // @[Breakpoint.scala:80:14]
input io_status_v, // @[Breakpoint.scala:80:14]
input io_status_sd, // @[Breakpoint.scala:80:14]
input io_status_mpv, // @[Breakpoint.scala:80:14]
input io_status_gva, // @[Breakpoint.scala:80:14]
input io_status_tsr, // @[Breakpoint.scala:80:14]
input io_status_tw, // @[Breakpoint.scala:80:14]
input io_status_tvm, // @[Breakpoint.scala:80:14]
input io_status_mxr, // @[Breakpoint.scala:80:14]
input io_status_sum, // @[Breakpoint.scala:80:14]
input io_status_mprv, // @[Breakpoint.scala:80:14]
input [1:0] io_status_fs, // @[Breakpoint.scala:80:14]
input [1:0] io_status_mpp, // @[Breakpoint.scala:80:14]
input io_status_spp, // @[Breakpoint.scala:80:14]
input io_status_mpie, // @[Breakpoint.scala:80:14]
input io_status_spie, // @[Breakpoint.scala:80:14]
input io_status_mie, // @[Breakpoint.scala:80:14]
input io_status_sie, // @[Breakpoint.scala:80:14]
input [38:0] io_ea // @[Breakpoint.scala:80:14]
);
wire io_status_debug_0 = io_status_debug; // @[Breakpoint.scala:79:7]
wire io_status_cease_0 = io_status_cease; // @[Breakpoint.scala:79:7]
wire io_status_wfi_0 = io_status_wfi; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_dprv_0 = io_status_dprv; // @[Breakpoint.scala:79:7]
wire io_status_dv_0 = io_status_dv; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_prv_0 = io_status_prv; // @[Breakpoint.scala:79:7]
wire io_status_v_0 = io_status_v; // @[Breakpoint.scala:79:7]
wire io_status_sd_0 = io_status_sd; // @[Breakpoint.scala:79:7]
wire io_status_mpv_0 = io_status_mpv; // @[Breakpoint.scala:79:7]
wire io_status_gva_0 = io_status_gva; // @[Breakpoint.scala:79:7]
wire io_status_tsr_0 = io_status_tsr; // @[Breakpoint.scala:79:7]
wire io_status_tw_0 = io_status_tw; // @[Breakpoint.scala:79:7]
wire io_status_tvm_0 = io_status_tvm; // @[Breakpoint.scala:79:7]
wire io_status_mxr_0 = io_status_mxr; // @[Breakpoint.scala:79:7]
wire io_status_sum_0 = io_status_sum; // @[Breakpoint.scala:79:7]
wire io_status_mprv_0 = io_status_mprv; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_fs_0 = io_status_fs; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_mpp_0 = io_status_mpp; // @[Breakpoint.scala:79:7]
wire io_status_spp_0 = io_status_spp; // @[Breakpoint.scala:79:7]
wire io_status_mpie_0 = io_status_mpie; // @[Breakpoint.scala:79:7]
wire io_status_spie_0 = io_status_spie; // @[Breakpoint.scala:79:7]
wire io_status_mie_0 = io_status_mie; // @[Breakpoint.scala:79:7]
wire io_status_sie_0 = io_status_sie; // @[Breakpoint.scala:79:7]
wire [38:0] io_ea_0 = io_ea; // @[Breakpoint.scala:79:7]
wire [38:0] io_pc = 39'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_sxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_uxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_xs = 2'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_vs = 2'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [7:0] io_status_zero1 = 8'h0; // @[Breakpoint.scala:79:7, :80:14]
wire io_status_mbe = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_sbe = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_sd_rv32 = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_ube = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_upie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_hie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_uie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_if = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_ld = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_st = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_if = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_ld = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_st = 1'h0; // @[Breakpoint.scala:79:7]
wire [22:0] io_status_zero2 = 23'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [31:0] io_status_isa = 32'h14112D; // @[Breakpoint.scala:79:7, :80:14]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_45 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_EntryData_45( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_g, // @[package.scala:268:18]
output io_y_ae, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c, // @[package.scala:268:18]
output io_y_fragmented_superpage // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_g = io_y_g_0; // @[package.scala:267:30]
assign io_y_ae = io_y_ae_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ZstdCompressorMemWriter :
input clock : Clock
input reset : Reset
output io : { flip memwrites_in : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>, validbytes : UInt<6>, end_of_message : UInt<1>}}, l2io : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, flip dest_info : { flip ready : UInt<1>, valid : UInt<1>, bits : { op : UInt<64>, cmpflag : UInt<64>, cmpval : UInt<64>}}, bufs_completed : UInt<64>, no_writes_inflight : UInt<1>}
inst incoming_writes_Q of Queue4_WriterBundle
connect incoming_writes_Q.clock, clock
connect incoming_writes_Q.reset, reset
connect incoming_writes_Q.io.enq, io.memwrites_in
inst dest_info_Q of Queue4_DstWithValInfo
connect dest_info_Q.clock, clock
connect dest_info_Q.reset, reset
connect dest_info_Q.io.enq, io.dest_info
node _decompress_dest_last_fire_T = and(dest_info_Q.io.deq.ready, dest_info_Q.io.deq.valid)
reg decompress_dest_last_fire : UInt<1>, clock
connect decompress_dest_last_fire, _decompress_dest_last_fire_T
reg decompress_dest_last_valid : UInt<1>, clock
connect decompress_dest_last_valid, dest_info_Q.io.deq.valid
node _decompress_dest_printhelp_T = eq(decompress_dest_last_valid, UInt<1>(0h0))
node _decompress_dest_printhelp_T_1 = or(decompress_dest_last_fire, _decompress_dest_printhelp_T)
node decompress_dest_printhelp = and(dest_info_Q.io.deq.valid, _decompress_dest_printhelp_T_1)
when decompress_dest_printhelp :
regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1))
node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1)
connect loginfo_cycles, _loginfo_cycles_T_1
node _T = asUInt(reset)
node _T_1 = eq(_T, UInt<1>(0h0))
when _T_1 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "[config-memwriter] got dest info op: 0x%x, cmpflag 0x%x\n", dest_info_Q.io.deq.bits.op, dest_info_Q.io.deq.bits.cmpflag) : printf_1
inst buf_lens_Q of Queue10_UInt64
connect buf_lens_Q.clock, clock
connect buf_lens_Q.reset, reset
node _T_4 = and(buf_lens_Q.io.enq.ready, buf_lens_Q.io.enq.valid)
when _T_4 :
regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1))
node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1)
connect loginfo_cycles_1, _loginfo_cycles_T_3
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "[fhdr_memwriter] enqueued buf len: %d\n", buf_lens_Q.io.enq.bits) : printf_3
regreset buf_len_tracker : UInt<64>, clock, reset, UInt<64>(0h0)
node _T_9 = and(incoming_writes_Q.io.deq.ready, incoming_writes_Q.io.deq.valid)
when _T_9 :
when incoming_writes_Q.io.deq.bits.end_of_message :
connect buf_len_tracker, UInt<1>(0h0)
else :
node _buf_len_tracker_T = add(buf_len_tracker, incoming_writes_Q.io.deq.bits.validbytes)
connect buf_len_tracker, _buf_len_tracker_T
node _T_10 = and(incoming_writes_Q.io.deq.ready, incoming_writes_Q.io.deq.valid)
when _T_10 :
regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1))
node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1)
connect loginfo_cycles_2, _loginfo_cycles_T_5
node _T_11 = asUInt(reset)
node _T_12 = eq(_T_11, UInt<1>(0h0))
when _T_12 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_2) : printf_4
node _T_13 = asUInt(reset)
node _T_14 = eq(_T_13, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "[fhdr_memwriter] dat: 0x%x, bytes: 0x%x, EOM: %d\n", incoming_writes_Q.io.deq.bits.data, incoming_writes_Q.io.deq.bits.validbytes, incoming_writes_Q.io.deq.bits.end_of_message) : printf_5
regreset write_start_index : UInt<6>, clock, reset, UInt<6>(0h0)
inst Queue2_UInt8 of Queue2_UInt8
connect Queue2_UInt8.clock, clock
connect Queue2_UInt8.reset, reset
inst Queue2_UInt8_1 of Queue2_UInt8_1
connect Queue2_UInt8_1.clock, clock
connect Queue2_UInt8_1.reset, reset
inst Queue2_UInt8_2 of Queue2_UInt8_2
connect Queue2_UInt8_2.clock, clock
connect Queue2_UInt8_2.reset, reset
inst Queue2_UInt8_3 of Queue2_UInt8_3
connect Queue2_UInt8_3.clock, clock
connect Queue2_UInt8_3.reset, reset
inst Queue2_UInt8_4 of Queue2_UInt8_4
connect Queue2_UInt8_4.clock, clock
connect Queue2_UInt8_4.reset, reset
inst Queue2_UInt8_5 of Queue2_UInt8_5
connect Queue2_UInt8_5.clock, clock
connect Queue2_UInt8_5.reset, reset
inst Queue2_UInt8_6 of Queue2_UInt8_6
connect Queue2_UInt8_6.clock, clock
connect Queue2_UInt8_6.reset, reset
inst Queue2_UInt8_7 of Queue2_UInt8_7
connect Queue2_UInt8_7.clock, clock
connect Queue2_UInt8_7.reset, reset
inst Queue2_UInt8_8 of Queue2_UInt8_8
connect Queue2_UInt8_8.clock, clock
connect Queue2_UInt8_8.reset, reset
inst Queue2_UInt8_9 of Queue2_UInt8_9
connect Queue2_UInt8_9.clock, clock
connect Queue2_UInt8_9.reset, reset
inst Queue2_UInt8_10 of Queue2_UInt8_10
connect Queue2_UInt8_10.clock, clock
connect Queue2_UInt8_10.reset, reset
inst Queue2_UInt8_11 of Queue2_UInt8_11
connect Queue2_UInt8_11.clock, clock
connect Queue2_UInt8_11.reset, reset
inst Queue2_UInt8_12 of Queue2_UInt8_12
connect Queue2_UInt8_12.clock, clock
connect Queue2_UInt8_12.reset, reset
inst Queue2_UInt8_13 of Queue2_UInt8_13
connect Queue2_UInt8_13.clock, clock
connect Queue2_UInt8_13.reset, reset
inst Queue2_UInt8_14 of Queue2_UInt8_14
connect Queue2_UInt8_14.clock, clock
connect Queue2_UInt8_14.reset, reset
inst Queue2_UInt8_15 of Queue2_UInt8_15
connect Queue2_UInt8_15.clock, clock
connect Queue2_UInt8_15.reset, reset
inst Queue2_UInt8_16 of Queue2_UInt8_16
connect Queue2_UInt8_16.clock, clock
connect Queue2_UInt8_16.reset, reset
inst Queue2_UInt8_17 of Queue2_UInt8_17
connect Queue2_UInt8_17.clock, clock
connect Queue2_UInt8_17.reset, reset
inst Queue2_UInt8_18 of Queue2_UInt8_18
connect Queue2_UInt8_18.clock, clock
connect Queue2_UInt8_18.reset, reset
inst Queue2_UInt8_19 of Queue2_UInt8_19
connect Queue2_UInt8_19.clock, clock
connect Queue2_UInt8_19.reset, reset
inst Queue2_UInt8_20 of Queue2_UInt8_20
connect Queue2_UInt8_20.clock, clock
connect Queue2_UInt8_20.reset, reset
inst Queue2_UInt8_21 of Queue2_UInt8_21
connect Queue2_UInt8_21.clock, clock
connect Queue2_UInt8_21.reset, reset
inst Queue2_UInt8_22 of Queue2_UInt8_22
connect Queue2_UInt8_22.clock, clock
connect Queue2_UInt8_22.reset, reset
inst Queue2_UInt8_23 of Queue2_UInt8_23
connect Queue2_UInt8_23.clock, clock
connect Queue2_UInt8_23.reset, reset
inst Queue2_UInt8_24 of Queue2_UInt8_24
connect Queue2_UInt8_24.clock, clock
connect Queue2_UInt8_24.reset, reset
inst Queue2_UInt8_25 of Queue2_UInt8_25
connect Queue2_UInt8_25.clock, clock
connect Queue2_UInt8_25.reset, reset
inst Queue2_UInt8_26 of Queue2_UInt8_26
connect Queue2_UInt8_26.clock, clock
connect Queue2_UInt8_26.reset, reset
inst Queue2_UInt8_27 of Queue2_UInt8_27
connect Queue2_UInt8_27.clock, clock
connect Queue2_UInt8_27.reset, reset
inst Queue2_UInt8_28 of Queue2_UInt8_28
connect Queue2_UInt8_28.clock, clock
connect Queue2_UInt8_28.reset, reset
inst Queue2_UInt8_29 of Queue2_UInt8_29
connect Queue2_UInt8_29.clock, clock
connect Queue2_UInt8_29.reset, reset
inst Queue2_UInt8_30 of Queue2_UInt8_30
connect Queue2_UInt8_30.clock, clock
connect Queue2_UInt8_30.reset, reset
inst Queue2_UInt8_31 of Queue2_UInt8_31
connect Queue2_UInt8_31.clock, clock
connect Queue2_UInt8_31.reset, reset
connect Queue2_UInt8.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_1.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_2.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_3.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_4.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_5.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_6.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_7.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_8.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_9.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_10.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_11.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_12.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_13.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_14.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_15.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_16.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_17.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_18.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_19.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_20.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_21.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_22.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_23.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_24.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_25.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_26.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_27.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_28.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_29.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_30.io.enq.bits, UInt<1>(0h0)
connect Queue2_UInt8_31.io.enq.bits, UInt<1>(0h0)
node _idx_T = add(write_start_index, UInt<1>(0h0))
node idx = rem(_idx_T, UInt<6>(0h20))
node _T_15 = eq(UInt<1>(0h0), idx)
when _T_15 :
node _T_16 = shl(UInt<1>(0h0), 3)
node _T_17 = dshr(incoming_writes_Q.io.deq.bits.data, _T_16)
node _T_18 = bits(_T_17, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_18
node _T_19 = eq(UInt<1>(0h1), idx)
when _T_19 :
node _T_20 = shl(UInt<1>(0h0), 3)
node _T_21 = dshr(incoming_writes_Q.io.deq.bits.data, _T_20)
node _T_22 = bits(_T_21, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_22
node _T_23 = eq(UInt<2>(0h2), idx)
when _T_23 :
node _T_24 = shl(UInt<1>(0h0), 3)
node _T_25 = dshr(incoming_writes_Q.io.deq.bits.data, _T_24)
node _T_26 = bits(_T_25, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_26
node _T_27 = eq(UInt<2>(0h3), idx)
when _T_27 :
node _T_28 = shl(UInt<1>(0h0), 3)
node _T_29 = dshr(incoming_writes_Q.io.deq.bits.data, _T_28)
node _T_30 = bits(_T_29, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_30
node _T_31 = eq(UInt<3>(0h4), idx)
when _T_31 :
node _T_32 = shl(UInt<1>(0h0), 3)
node _T_33 = dshr(incoming_writes_Q.io.deq.bits.data, _T_32)
node _T_34 = bits(_T_33, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_34
node _T_35 = eq(UInt<3>(0h5), idx)
when _T_35 :
node _T_36 = shl(UInt<1>(0h0), 3)
node _T_37 = dshr(incoming_writes_Q.io.deq.bits.data, _T_36)
node _T_38 = bits(_T_37, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_38
node _T_39 = eq(UInt<3>(0h6), idx)
when _T_39 :
node _T_40 = shl(UInt<1>(0h0), 3)
node _T_41 = dshr(incoming_writes_Q.io.deq.bits.data, _T_40)
node _T_42 = bits(_T_41, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_42
node _T_43 = eq(UInt<3>(0h7), idx)
when _T_43 :
node _T_44 = shl(UInt<1>(0h0), 3)
node _T_45 = dshr(incoming_writes_Q.io.deq.bits.data, _T_44)
node _T_46 = bits(_T_45, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_46
node _T_47 = eq(UInt<4>(0h8), idx)
when _T_47 :
node _T_48 = shl(UInt<1>(0h0), 3)
node _T_49 = dshr(incoming_writes_Q.io.deq.bits.data, _T_48)
node _T_50 = bits(_T_49, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_50
node _T_51 = eq(UInt<4>(0h9), idx)
when _T_51 :
node _T_52 = shl(UInt<1>(0h0), 3)
node _T_53 = dshr(incoming_writes_Q.io.deq.bits.data, _T_52)
node _T_54 = bits(_T_53, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_54
node _T_55 = eq(UInt<4>(0ha), idx)
when _T_55 :
node _T_56 = shl(UInt<1>(0h0), 3)
node _T_57 = dshr(incoming_writes_Q.io.deq.bits.data, _T_56)
node _T_58 = bits(_T_57, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_58
node _T_59 = eq(UInt<4>(0hb), idx)
when _T_59 :
node _T_60 = shl(UInt<1>(0h0), 3)
node _T_61 = dshr(incoming_writes_Q.io.deq.bits.data, _T_60)
node _T_62 = bits(_T_61, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_62
node _T_63 = eq(UInt<4>(0hc), idx)
when _T_63 :
node _T_64 = shl(UInt<1>(0h0), 3)
node _T_65 = dshr(incoming_writes_Q.io.deq.bits.data, _T_64)
node _T_66 = bits(_T_65, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_66
node _T_67 = eq(UInt<4>(0hd), idx)
when _T_67 :
node _T_68 = shl(UInt<1>(0h0), 3)
node _T_69 = dshr(incoming_writes_Q.io.deq.bits.data, _T_68)
node _T_70 = bits(_T_69, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_70
node _T_71 = eq(UInt<4>(0he), idx)
when _T_71 :
node _T_72 = shl(UInt<1>(0h0), 3)
node _T_73 = dshr(incoming_writes_Q.io.deq.bits.data, _T_72)
node _T_74 = bits(_T_73, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_74
node _T_75 = eq(UInt<4>(0hf), idx)
when _T_75 :
node _T_76 = shl(UInt<1>(0h0), 3)
node _T_77 = dshr(incoming_writes_Q.io.deq.bits.data, _T_76)
node _T_78 = bits(_T_77, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_78
node _T_79 = eq(UInt<5>(0h10), idx)
when _T_79 :
node _T_80 = shl(UInt<1>(0h0), 3)
node _T_81 = dshr(incoming_writes_Q.io.deq.bits.data, _T_80)
node _T_82 = bits(_T_81, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_82
node _T_83 = eq(UInt<5>(0h11), idx)
when _T_83 :
node _T_84 = shl(UInt<1>(0h0), 3)
node _T_85 = dshr(incoming_writes_Q.io.deq.bits.data, _T_84)
node _T_86 = bits(_T_85, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_86
node _T_87 = eq(UInt<5>(0h12), idx)
when _T_87 :
node _T_88 = shl(UInt<1>(0h0), 3)
node _T_89 = dshr(incoming_writes_Q.io.deq.bits.data, _T_88)
node _T_90 = bits(_T_89, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_90
node _T_91 = eq(UInt<5>(0h13), idx)
when _T_91 :
node _T_92 = shl(UInt<1>(0h0), 3)
node _T_93 = dshr(incoming_writes_Q.io.deq.bits.data, _T_92)
node _T_94 = bits(_T_93, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_94
node _T_95 = eq(UInt<5>(0h14), idx)
when _T_95 :
node _T_96 = shl(UInt<1>(0h0), 3)
node _T_97 = dshr(incoming_writes_Q.io.deq.bits.data, _T_96)
node _T_98 = bits(_T_97, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_98
node _T_99 = eq(UInt<5>(0h15), idx)
when _T_99 :
node _T_100 = shl(UInt<1>(0h0), 3)
node _T_101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_100)
node _T_102 = bits(_T_101, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_102
node _T_103 = eq(UInt<5>(0h16), idx)
when _T_103 :
node _T_104 = shl(UInt<1>(0h0), 3)
node _T_105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_104)
node _T_106 = bits(_T_105, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_106
node _T_107 = eq(UInt<5>(0h17), idx)
when _T_107 :
node _T_108 = shl(UInt<1>(0h0), 3)
node _T_109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_108)
node _T_110 = bits(_T_109, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_110
node _T_111 = eq(UInt<5>(0h18), idx)
when _T_111 :
node _T_112 = shl(UInt<1>(0h0), 3)
node _T_113 = dshr(incoming_writes_Q.io.deq.bits.data, _T_112)
node _T_114 = bits(_T_113, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_114
node _T_115 = eq(UInt<5>(0h19), idx)
when _T_115 :
node _T_116 = shl(UInt<1>(0h0), 3)
node _T_117 = dshr(incoming_writes_Q.io.deq.bits.data, _T_116)
node _T_118 = bits(_T_117, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_118
node _T_119 = eq(UInt<5>(0h1a), idx)
when _T_119 :
node _T_120 = shl(UInt<1>(0h0), 3)
node _T_121 = dshr(incoming_writes_Q.io.deq.bits.data, _T_120)
node _T_122 = bits(_T_121, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_122
node _T_123 = eq(UInt<5>(0h1b), idx)
when _T_123 :
node _T_124 = shl(UInt<1>(0h0), 3)
node _T_125 = dshr(incoming_writes_Q.io.deq.bits.data, _T_124)
node _T_126 = bits(_T_125, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_126
node _T_127 = eq(UInt<5>(0h1c), idx)
when _T_127 :
node _T_128 = shl(UInt<1>(0h0), 3)
node _T_129 = dshr(incoming_writes_Q.io.deq.bits.data, _T_128)
node _T_130 = bits(_T_129, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_130
node _T_131 = eq(UInt<5>(0h1d), idx)
when _T_131 :
node _T_132 = shl(UInt<1>(0h0), 3)
node _T_133 = dshr(incoming_writes_Q.io.deq.bits.data, _T_132)
node _T_134 = bits(_T_133, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_134
node _T_135 = eq(UInt<5>(0h1e), idx)
when _T_135 :
node _T_136 = shl(UInt<1>(0h0), 3)
node _T_137 = dshr(incoming_writes_Q.io.deq.bits.data, _T_136)
node _T_138 = bits(_T_137, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_138
node _T_139 = eq(UInt<5>(0h1f), idx)
when _T_139 :
node _T_140 = shl(UInt<1>(0h0), 3)
node _T_141 = dshr(incoming_writes_Q.io.deq.bits.data, _T_140)
node _T_142 = bits(_T_141, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_142
node _idx_T_1 = add(write_start_index, UInt<1>(0h1))
node idx_1 = rem(_idx_T_1, UInt<6>(0h20))
node _T_143 = eq(UInt<1>(0h0), idx_1)
when _T_143 :
node _T_144 = shl(UInt<1>(0h1), 3)
node _T_145 = dshr(incoming_writes_Q.io.deq.bits.data, _T_144)
node _T_146 = bits(_T_145, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_146
node _T_147 = eq(UInt<1>(0h1), idx_1)
when _T_147 :
node _T_148 = shl(UInt<1>(0h1), 3)
node _T_149 = dshr(incoming_writes_Q.io.deq.bits.data, _T_148)
node _T_150 = bits(_T_149, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_150
node _T_151 = eq(UInt<2>(0h2), idx_1)
when _T_151 :
node _T_152 = shl(UInt<1>(0h1), 3)
node _T_153 = dshr(incoming_writes_Q.io.deq.bits.data, _T_152)
node _T_154 = bits(_T_153, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_154
node _T_155 = eq(UInt<2>(0h3), idx_1)
when _T_155 :
node _T_156 = shl(UInt<1>(0h1), 3)
node _T_157 = dshr(incoming_writes_Q.io.deq.bits.data, _T_156)
node _T_158 = bits(_T_157, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_158
node _T_159 = eq(UInt<3>(0h4), idx_1)
when _T_159 :
node _T_160 = shl(UInt<1>(0h1), 3)
node _T_161 = dshr(incoming_writes_Q.io.deq.bits.data, _T_160)
node _T_162 = bits(_T_161, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_162
node _T_163 = eq(UInt<3>(0h5), idx_1)
when _T_163 :
node _T_164 = shl(UInt<1>(0h1), 3)
node _T_165 = dshr(incoming_writes_Q.io.deq.bits.data, _T_164)
node _T_166 = bits(_T_165, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_166
node _T_167 = eq(UInt<3>(0h6), idx_1)
when _T_167 :
node _T_168 = shl(UInt<1>(0h1), 3)
node _T_169 = dshr(incoming_writes_Q.io.deq.bits.data, _T_168)
node _T_170 = bits(_T_169, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_170
node _T_171 = eq(UInt<3>(0h7), idx_1)
when _T_171 :
node _T_172 = shl(UInt<1>(0h1), 3)
node _T_173 = dshr(incoming_writes_Q.io.deq.bits.data, _T_172)
node _T_174 = bits(_T_173, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_174
node _T_175 = eq(UInt<4>(0h8), idx_1)
when _T_175 :
node _T_176 = shl(UInt<1>(0h1), 3)
node _T_177 = dshr(incoming_writes_Q.io.deq.bits.data, _T_176)
node _T_178 = bits(_T_177, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_178
node _T_179 = eq(UInt<4>(0h9), idx_1)
when _T_179 :
node _T_180 = shl(UInt<1>(0h1), 3)
node _T_181 = dshr(incoming_writes_Q.io.deq.bits.data, _T_180)
node _T_182 = bits(_T_181, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_182
node _T_183 = eq(UInt<4>(0ha), idx_1)
when _T_183 :
node _T_184 = shl(UInt<1>(0h1), 3)
node _T_185 = dshr(incoming_writes_Q.io.deq.bits.data, _T_184)
node _T_186 = bits(_T_185, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_186
node _T_187 = eq(UInt<4>(0hb), idx_1)
when _T_187 :
node _T_188 = shl(UInt<1>(0h1), 3)
node _T_189 = dshr(incoming_writes_Q.io.deq.bits.data, _T_188)
node _T_190 = bits(_T_189, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_190
node _T_191 = eq(UInt<4>(0hc), idx_1)
when _T_191 :
node _T_192 = shl(UInt<1>(0h1), 3)
node _T_193 = dshr(incoming_writes_Q.io.deq.bits.data, _T_192)
node _T_194 = bits(_T_193, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_194
node _T_195 = eq(UInt<4>(0hd), idx_1)
when _T_195 :
node _T_196 = shl(UInt<1>(0h1), 3)
node _T_197 = dshr(incoming_writes_Q.io.deq.bits.data, _T_196)
node _T_198 = bits(_T_197, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_198
node _T_199 = eq(UInt<4>(0he), idx_1)
when _T_199 :
node _T_200 = shl(UInt<1>(0h1), 3)
node _T_201 = dshr(incoming_writes_Q.io.deq.bits.data, _T_200)
node _T_202 = bits(_T_201, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_202
node _T_203 = eq(UInt<4>(0hf), idx_1)
when _T_203 :
node _T_204 = shl(UInt<1>(0h1), 3)
node _T_205 = dshr(incoming_writes_Q.io.deq.bits.data, _T_204)
node _T_206 = bits(_T_205, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_206
node _T_207 = eq(UInt<5>(0h10), idx_1)
when _T_207 :
node _T_208 = shl(UInt<1>(0h1), 3)
node _T_209 = dshr(incoming_writes_Q.io.deq.bits.data, _T_208)
node _T_210 = bits(_T_209, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_210
node _T_211 = eq(UInt<5>(0h11), idx_1)
when _T_211 :
node _T_212 = shl(UInt<1>(0h1), 3)
node _T_213 = dshr(incoming_writes_Q.io.deq.bits.data, _T_212)
node _T_214 = bits(_T_213, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_214
node _T_215 = eq(UInt<5>(0h12), idx_1)
when _T_215 :
node _T_216 = shl(UInt<1>(0h1), 3)
node _T_217 = dshr(incoming_writes_Q.io.deq.bits.data, _T_216)
node _T_218 = bits(_T_217, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_218
node _T_219 = eq(UInt<5>(0h13), idx_1)
when _T_219 :
node _T_220 = shl(UInt<1>(0h1), 3)
node _T_221 = dshr(incoming_writes_Q.io.deq.bits.data, _T_220)
node _T_222 = bits(_T_221, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_222
node _T_223 = eq(UInt<5>(0h14), idx_1)
when _T_223 :
node _T_224 = shl(UInt<1>(0h1), 3)
node _T_225 = dshr(incoming_writes_Q.io.deq.bits.data, _T_224)
node _T_226 = bits(_T_225, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_226
node _T_227 = eq(UInt<5>(0h15), idx_1)
when _T_227 :
node _T_228 = shl(UInt<1>(0h1), 3)
node _T_229 = dshr(incoming_writes_Q.io.deq.bits.data, _T_228)
node _T_230 = bits(_T_229, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_230
node _T_231 = eq(UInt<5>(0h16), idx_1)
when _T_231 :
node _T_232 = shl(UInt<1>(0h1), 3)
node _T_233 = dshr(incoming_writes_Q.io.deq.bits.data, _T_232)
node _T_234 = bits(_T_233, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_234
node _T_235 = eq(UInt<5>(0h17), idx_1)
when _T_235 :
node _T_236 = shl(UInt<1>(0h1), 3)
node _T_237 = dshr(incoming_writes_Q.io.deq.bits.data, _T_236)
node _T_238 = bits(_T_237, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_238
node _T_239 = eq(UInt<5>(0h18), idx_1)
when _T_239 :
node _T_240 = shl(UInt<1>(0h1), 3)
node _T_241 = dshr(incoming_writes_Q.io.deq.bits.data, _T_240)
node _T_242 = bits(_T_241, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_242
node _T_243 = eq(UInt<5>(0h19), idx_1)
when _T_243 :
node _T_244 = shl(UInt<1>(0h1), 3)
node _T_245 = dshr(incoming_writes_Q.io.deq.bits.data, _T_244)
node _T_246 = bits(_T_245, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_246
node _T_247 = eq(UInt<5>(0h1a), idx_1)
when _T_247 :
node _T_248 = shl(UInt<1>(0h1), 3)
node _T_249 = dshr(incoming_writes_Q.io.deq.bits.data, _T_248)
node _T_250 = bits(_T_249, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_250
node _T_251 = eq(UInt<5>(0h1b), idx_1)
when _T_251 :
node _T_252 = shl(UInt<1>(0h1), 3)
node _T_253 = dshr(incoming_writes_Q.io.deq.bits.data, _T_252)
node _T_254 = bits(_T_253, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_254
node _T_255 = eq(UInt<5>(0h1c), idx_1)
when _T_255 :
node _T_256 = shl(UInt<1>(0h1), 3)
node _T_257 = dshr(incoming_writes_Q.io.deq.bits.data, _T_256)
node _T_258 = bits(_T_257, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_258
node _T_259 = eq(UInt<5>(0h1d), idx_1)
when _T_259 :
node _T_260 = shl(UInt<1>(0h1), 3)
node _T_261 = dshr(incoming_writes_Q.io.deq.bits.data, _T_260)
node _T_262 = bits(_T_261, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_262
node _T_263 = eq(UInt<5>(0h1e), idx_1)
when _T_263 :
node _T_264 = shl(UInt<1>(0h1), 3)
node _T_265 = dshr(incoming_writes_Q.io.deq.bits.data, _T_264)
node _T_266 = bits(_T_265, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_266
node _T_267 = eq(UInt<5>(0h1f), idx_1)
when _T_267 :
node _T_268 = shl(UInt<1>(0h1), 3)
node _T_269 = dshr(incoming_writes_Q.io.deq.bits.data, _T_268)
node _T_270 = bits(_T_269, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_270
node _idx_T_2 = add(write_start_index, UInt<2>(0h2))
node idx_2 = rem(_idx_T_2, UInt<6>(0h20))
node _T_271 = eq(UInt<1>(0h0), idx_2)
when _T_271 :
node _T_272 = shl(UInt<2>(0h2), 3)
node _T_273 = dshr(incoming_writes_Q.io.deq.bits.data, _T_272)
node _T_274 = bits(_T_273, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_274
node _T_275 = eq(UInt<1>(0h1), idx_2)
when _T_275 :
node _T_276 = shl(UInt<2>(0h2), 3)
node _T_277 = dshr(incoming_writes_Q.io.deq.bits.data, _T_276)
node _T_278 = bits(_T_277, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_278
node _T_279 = eq(UInt<2>(0h2), idx_2)
when _T_279 :
node _T_280 = shl(UInt<2>(0h2), 3)
node _T_281 = dshr(incoming_writes_Q.io.deq.bits.data, _T_280)
node _T_282 = bits(_T_281, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_282
node _T_283 = eq(UInt<2>(0h3), idx_2)
when _T_283 :
node _T_284 = shl(UInt<2>(0h2), 3)
node _T_285 = dshr(incoming_writes_Q.io.deq.bits.data, _T_284)
node _T_286 = bits(_T_285, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_286
node _T_287 = eq(UInt<3>(0h4), idx_2)
when _T_287 :
node _T_288 = shl(UInt<2>(0h2), 3)
node _T_289 = dshr(incoming_writes_Q.io.deq.bits.data, _T_288)
node _T_290 = bits(_T_289, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_290
node _T_291 = eq(UInt<3>(0h5), idx_2)
when _T_291 :
node _T_292 = shl(UInt<2>(0h2), 3)
node _T_293 = dshr(incoming_writes_Q.io.deq.bits.data, _T_292)
node _T_294 = bits(_T_293, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_294
node _T_295 = eq(UInt<3>(0h6), idx_2)
when _T_295 :
node _T_296 = shl(UInt<2>(0h2), 3)
node _T_297 = dshr(incoming_writes_Q.io.deq.bits.data, _T_296)
node _T_298 = bits(_T_297, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_298
node _T_299 = eq(UInt<3>(0h7), idx_2)
when _T_299 :
node _T_300 = shl(UInt<2>(0h2), 3)
node _T_301 = dshr(incoming_writes_Q.io.deq.bits.data, _T_300)
node _T_302 = bits(_T_301, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_302
node _T_303 = eq(UInt<4>(0h8), idx_2)
when _T_303 :
node _T_304 = shl(UInt<2>(0h2), 3)
node _T_305 = dshr(incoming_writes_Q.io.deq.bits.data, _T_304)
node _T_306 = bits(_T_305, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_306
node _T_307 = eq(UInt<4>(0h9), idx_2)
when _T_307 :
node _T_308 = shl(UInt<2>(0h2), 3)
node _T_309 = dshr(incoming_writes_Q.io.deq.bits.data, _T_308)
node _T_310 = bits(_T_309, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_310
node _T_311 = eq(UInt<4>(0ha), idx_2)
when _T_311 :
node _T_312 = shl(UInt<2>(0h2), 3)
node _T_313 = dshr(incoming_writes_Q.io.deq.bits.data, _T_312)
node _T_314 = bits(_T_313, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_314
node _T_315 = eq(UInt<4>(0hb), idx_2)
when _T_315 :
node _T_316 = shl(UInt<2>(0h2), 3)
node _T_317 = dshr(incoming_writes_Q.io.deq.bits.data, _T_316)
node _T_318 = bits(_T_317, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_318
node _T_319 = eq(UInt<4>(0hc), idx_2)
when _T_319 :
node _T_320 = shl(UInt<2>(0h2), 3)
node _T_321 = dshr(incoming_writes_Q.io.deq.bits.data, _T_320)
node _T_322 = bits(_T_321, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_322
node _T_323 = eq(UInt<4>(0hd), idx_2)
when _T_323 :
node _T_324 = shl(UInt<2>(0h2), 3)
node _T_325 = dshr(incoming_writes_Q.io.deq.bits.data, _T_324)
node _T_326 = bits(_T_325, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_326
node _T_327 = eq(UInt<4>(0he), idx_2)
when _T_327 :
node _T_328 = shl(UInt<2>(0h2), 3)
node _T_329 = dshr(incoming_writes_Q.io.deq.bits.data, _T_328)
node _T_330 = bits(_T_329, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_330
node _T_331 = eq(UInt<4>(0hf), idx_2)
when _T_331 :
node _T_332 = shl(UInt<2>(0h2), 3)
node _T_333 = dshr(incoming_writes_Q.io.deq.bits.data, _T_332)
node _T_334 = bits(_T_333, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_334
node _T_335 = eq(UInt<5>(0h10), idx_2)
when _T_335 :
node _T_336 = shl(UInt<2>(0h2), 3)
node _T_337 = dshr(incoming_writes_Q.io.deq.bits.data, _T_336)
node _T_338 = bits(_T_337, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_338
node _T_339 = eq(UInt<5>(0h11), idx_2)
when _T_339 :
node _T_340 = shl(UInt<2>(0h2), 3)
node _T_341 = dshr(incoming_writes_Q.io.deq.bits.data, _T_340)
node _T_342 = bits(_T_341, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_342
node _T_343 = eq(UInt<5>(0h12), idx_2)
when _T_343 :
node _T_344 = shl(UInt<2>(0h2), 3)
node _T_345 = dshr(incoming_writes_Q.io.deq.bits.data, _T_344)
node _T_346 = bits(_T_345, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_346
node _T_347 = eq(UInt<5>(0h13), idx_2)
when _T_347 :
node _T_348 = shl(UInt<2>(0h2), 3)
node _T_349 = dshr(incoming_writes_Q.io.deq.bits.data, _T_348)
node _T_350 = bits(_T_349, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_350
node _T_351 = eq(UInt<5>(0h14), idx_2)
when _T_351 :
node _T_352 = shl(UInt<2>(0h2), 3)
node _T_353 = dshr(incoming_writes_Q.io.deq.bits.data, _T_352)
node _T_354 = bits(_T_353, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_354
node _T_355 = eq(UInt<5>(0h15), idx_2)
when _T_355 :
node _T_356 = shl(UInt<2>(0h2), 3)
node _T_357 = dshr(incoming_writes_Q.io.deq.bits.data, _T_356)
node _T_358 = bits(_T_357, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_358
node _T_359 = eq(UInt<5>(0h16), idx_2)
when _T_359 :
node _T_360 = shl(UInt<2>(0h2), 3)
node _T_361 = dshr(incoming_writes_Q.io.deq.bits.data, _T_360)
node _T_362 = bits(_T_361, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_362
node _T_363 = eq(UInt<5>(0h17), idx_2)
when _T_363 :
node _T_364 = shl(UInt<2>(0h2), 3)
node _T_365 = dshr(incoming_writes_Q.io.deq.bits.data, _T_364)
node _T_366 = bits(_T_365, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_366
node _T_367 = eq(UInt<5>(0h18), idx_2)
when _T_367 :
node _T_368 = shl(UInt<2>(0h2), 3)
node _T_369 = dshr(incoming_writes_Q.io.deq.bits.data, _T_368)
node _T_370 = bits(_T_369, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_370
node _T_371 = eq(UInt<5>(0h19), idx_2)
when _T_371 :
node _T_372 = shl(UInt<2>(0h2), 3)
node _T_373 = dshr(incoming_writes_Q.io.deq.bits.data, _T_372)
node _T_374 = bits(_T_373, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_374
node _T_375 = eq(UInt<5>(0h1a), idx_2)
when _T_375 :
node _T_376 = shl(UInt<2>(0h2), 3)
node _T_377 = dshr(incoming_writes_Q.io.deq.bits.data, _T_376)
node _T_378 = bits(_T_377, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_378
node _T_379 = eq(UInt<5>(0h1b), idx_2)
when _T_379 :
node _T_380 = shl(UInt<2>(0h2), 3)
node _T_381 = dshr(incoming_writes_Q.io.deq.bits.data, _T_380)
node _T_382 = bits(_T_381, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_382
node _T_383 = eq(UInt<5>(0h1c), idx_2)
when _T_383 :
node _T_384 = shl(UInt<2>(0h2), 3)
node _T_385 = dshr(incoming_writes_Q.io.deq.bits.data, _T_384)
node _T_386 = bits(_T_385, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_386
node _T_387 = eq(UInt<5>(0h1d), idx_2)
when _T_387 :
node _T_388 = shl(UInt<2>(0h2), 3)
node _T_389 = dshr(incoming_writes_Q.io.deq.bits.data, _T_388)
node _T_390 = bits(_T_389, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_390
node _T_391 = eq(UInt<5>(0h1e), idx_2)
when _T_391 :
node _T_392 = shl(UInt<2>(0h2), 3)
node _T_393 = dshr(incoming_writes_Q.io.deq.bits.data, _T_392)
node _T_394 = bits(_T_393, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_394
node _T_395 = eq(UInt<5>(0h1f), idx_2)
when _T_395 :
node _T_396 = shl(UInt<2>(0h2), 3)
node _T_397 = dshr(incoming_writes_Q.io.deq.bits.data, _T_396)
node _T_398 = bits(_T_397, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_398
node _idx_T_3 = add(write_start_index, UInt<2>(0h3))
node idx_3 = rem(_idx_T_3, UInt<6>(0h20))
node _T_399 = eq(UInt<1>(0h0), idx_3)
when _T_399 :
node _T_400 = shl(UInt<2>(0h3), 3)
node _T_401 = dshr(incoming_writes_Q.io.deq.bits.data, _T_400)
node _T_402 = bits(_T_401, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_402
node _T_403 = eq(UInt<1>(0h1), idx_3)
when _T_403 :
node _T_404 = shl(UInt<2>(0h3), 3)
node _T_405 = dshr(incoming_writes_Q.io.deq.bits.data, _T_404)
node _T_406 = bits(_T_405, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_406
node _T_407 = eq(UInt<2>(0h2), idx_3)
when _T_407 :
node _T_408 = shl(UInt<2>(0h3), 3)
node _T_409 = dshr(incoming_writes_Q.io.deq.bits.data, _T_408)
node _T_410 = bits(_T_409, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_410
node _T_411 = eq(UInt<2>(0h3), idx_3)
when _T_411 :
node _T_412 = shl(UInt<2>(0h3), 3)
node _T_413 = dshr(incoming_writes_Q.io.deq.bits.data, _T_412)
node _T_414 = bits(_T_413, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_414
node _T_415 = eq(UInt<3>(0h4), idx_3)
when _T_415 :
node _T_416 = shl(UInt<2>(0h3), 3)
node _T_417 = dshr(incoming_writes_Q.io.deq.bits.data, _T_416)
node _T_418 = bits(_T_417, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_418
node _T_419 = eq(UInt<3>(0h5), idx_3)
when _T_419 :
node _T_420 = shl(UInt<2>(0h3), 3)
node _T_421 = dshr(incoming_writes_Q.io.deq.bits.data, _T_420)
node _T_422 = bits(_T_421, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_422
node _T_423 = eq(UInt<3>(0h6), idx_3)
when _T_423 :
node _T_424 = shl(UInt<2>(0h3), 3)
node _T_425 = dshr(incoming_writes_Q.io.deq.bits.data, _T_424)
node _T_426 = bits(_T_425, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_426
node _T_427 = eq(UInt<3>(0h7), idx_3)
when _T_427 :
node _T_428 = shl(UInt<2>(0h3), 3)
node _T_429 = dshr(incoming_writes_Q.io.deq.bits.data, _T_428)
node _T_430 = bits(_T_429, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_430
node _T_431 = eq(UInt<4>(0h8), idx_3)
when _T_431 :
node _T_432 = shl(UInt<2>(0h3), 3)
node _T_433 = dshr(incoming_writes_Q.io.deq.bits.data, _T_432)
node _T_434 = bits(_T_433, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_434
node _T_435 = eq(UInt<4>(0h9), idx_3)
when _T_435 :
node _T_436 = shl(UInt<2>(0h3), 3)
node _T_437 = dshr(incoming_writes_Q.io.deq.bits.data, _T_436)
node _T_438 = bits(_T_437, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_438
node _T_439 = eq(UInt<4>(0ha), idx_3)
when _T_439 :
node _T_440 = shl(UInt<2>(0h3), 3)
node _T_441 = dshr(incoming_writes_Q.io.deq.bits.data, _T_440)
node _T_442 = bits(_T_441, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_442
node _T_443 = eq(UInt<4>(0hb), idx_3)
when _T_443 :
node _T_444 = shl(UInt<2>(0h3), 3)
node _T_445 = dshr(incoming_writes_Q.io.deq.bits.data, _T_444)
node _T_446 = bits(_T_445, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_446
node _T_447 = eq(UInt<4>(0hc), idx_3)
when _T_447 :
node _T_448 = shl(UInt<2>(0h3), 3)
node _T_449 = dshr(incoming_writes_Q.io.deq.bits.data, _T_448)
node _T_450 = bits(_T_449, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_450
node _T_451 = eq(UInt<4>(0hd), idx_3)
when _T_451 :
node _T_452 = shl(UInt<2>(0h3), 3)
node _T_453 = dshr(incoming_writes_Q.io.deq.bits.data, _T_452)
node _T_454 = bits(_T_453, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_454
node _T_455 = eq(UInt<4>(0he), idx_3)
when _T_455 :
node _T_456 = shl(UInt<2>(0h3), 3)
node _T_457 = dshr(incoming_writes_Q.io.deq.bits.data, _T_456)
node _T_458 = bits(_T_457, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_458
node _T_459 = eq(UInt<4>(0hf), idx_3)
when _T_459 :
node _T_460 = shl(UInt<2>(0h3), 3)
node _T_461 = dshr(incoming_writes_Q.io.deq.bits.data, _T_460)
node _T_462 = bits(_T_461, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_462
node _T_463 = eq(UInt<5>(0h10), idx_3)
when _T_463 :
node _T_464 = shl(UInt<2>(0h3), 3)
node _T_465 = dshr(incoming_writes_Q.io.deq.bits.data, _T_464)
node _T_466 = bits(_T_465, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_466
node _T_467 = eq(UInt<5>(0h11), idx_3)
when _T_467 :
node _T_468 = shl(UInt<2>(0h3), 3)
node _T_469 = dshr(incoming_writes_Q.io.deq.bits.data, _T_468)
node _T_470 = bits(_T_469, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_470
node _T_471 = eq(UInt<5>(0h12), idx_3)
when _T_471 :
node _T_472 = shl(UInt<2>(0h3), 3)
node _T_473 = dshr(incoming_writes_Q.io.deq.bits.data, _T_472)
node _T_474 = bits(_T_473, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_474
node _T_475 = eq(UInt<5>(0h13), idx_3)
when _T_475 :
node _T_476 = shl(UInt<2>(0h3), 3)
node _T_477 = dshr(incoming_writes_Q.io.deq.bits.data, _T_476)
node _T_478 = bits(_T_477, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_478
node _T_479 = eq(UInt<5>(0h14), idx_3)
when _T_479 :
node _T_480 = shl(UInt<2>(0h3), 3)
node _T_481 = dshr(incoming_writes_Q.io.deq.bits.data, _T_480)
node _T_482 = bits(_T_481, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_482
node _T_483 = eq(UInt<5>(0h15), idx_3)
when _T_483 :
node _T_484 = shl(UInt<2>(0h3), 3)
node _T_485 = dshr(incoming_writes_Q.io.deq.bits.data, _T_484)
node _T_486 = bits(_T_485, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_486
node _T_487 = eq(UInt<5>(0h16), idx_3)
when _T_487 :
node _T_488 = shl(UInt<2>(0h3), 3)
node _T_489 = dshr(incoming_writes_Q.io.deq.bits.data, _T_488)
node _T_490 = bits(_T_489, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_490
node _T_491 = eq(UInt<5>(0h17), idx_3)
when _T_491 :
node _T_492 = shl(UInt<2>(0h3), 3)
node _T_493 = dshr(incoming_writes_Q.io.deq.bits.data, _T_492)
node _T_494 = bits(_T_493, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_494
node _T_495 = eq(UInt<5>(0h18), idx_3)
when _T_495 :
node _T_496 = shl(UInt<2>(0h3), 3)
node _T_497 = dshr(incoming_writes_Q.io.deq.bits.data, _T_496)
node _T_498 = bits(_T_497, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_498
node _T_499 = eq(UInt<5>(0h19), idx_3)
when _T_499 :
node _T_500 = shl(UInt<2>(0h3), 3)
node _T_501 = dshr(incoming_writes_Q.io.deq.bits.data, _T_500)
node _T_502 = bits(_T_501, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_502
node _T_503 = eq(UInt<5>(0h1a), idx_3)
when _T_503 :
node _T_504 = shl(UInt<2>(0h3), 3)
node _T_505 = dshr(incoming_writes_Q.io.deq.bits.data, _T_504)
node _T_506 = bits(_T_505, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_506
node _T_507 = eq(UInt<5>(0h1b), idx_3)
when _T_507 :
node _T_508 = shl(UInt<2>(0h3), 3)
node _T_509 = dshr(incoming_writes_Q.io.deq.bits.data, _T_508)
node _T_510 = bits(_T_509, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_510
node _T_511 = eq(UInt<5>(0h1c), idx_3)
when _T_511 :
node _T_512 = shl(UInt<2>(0h3), 3)
node _T_513 = dshr(incoming_writes_Q.io.deq.bits.data, _T_512)
node _T_514 = bits(_T_513, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_514
node _T_515 = eq(UInt<5>(0h1d), idx_3)
when _T_515 :
node _T_516 = shl(UInt<2>(0h3), 3)
node _T_517 = dshr(incoming_writes_Q.io.deq.bits.data, _T_516)
node _T_518 = bits(_T_517, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_518
node _T_519 = eq(UInt<5>(0h1e), idx_3)
when _T_519 :
node _T_520 = shl(UInt<2>(0h3), 3)
node _T_521 = dshr(incoming_writes_Q.io.deq.bits.data, _T_520)
node _T_522 = bits(_T_521, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_522
node _T_523 = eq(UInt<5>(0h1f), idx_3)
when _T_523 :
node _T_524 = shl(UInt<2>(0h3), 3)
node _T_525 = dshr(incoming_writes_Q.io.deq.bits.data, _T_524)
node _T_526 = bits(_T_525, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_526
node _idx_T_4 = add(write_start_index, UInt<3>(0h4))
node idx_4 = rem(_idx_T_4, UInt<6>(0h20))
node _T_527 = eq(UInt<1>(0h0), idx_4)
when _T_527 :
node _T_528 = shl(UInt<3>(0h4), 3)
node _T_529 = dshr(incoming_writes_Q.io.deq.bits.data, _T_528)
node _T_530 = bits(_T_529, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_530
node _T_531 = eq(UInt<1>(0h1), idx_4)
when _T_531 :
node _T_532 = shl(UInt<3>(0h4), 3)
node _T_533 = dshr(incoming_writes_Q.io.deq.bits.data, _T_532)
node _T_534 = bits(_T_533, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_534
node _T_535 = eq(UInt<2>(0h2), idx_4)
when _T_535 :
node _T_536 = shl(UInt<3>(0h4), 3)
node _T_537 = dshr(incoming_writes_Q.io.deq.bits.data, _T_536)
node _T_538 = bits(_T_537, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_538
node _T_539 = eq(UInt<2>(0h3), idx_4)
when _T_539 :
node _T_540 = shl(UInt<3>(0h4), 3)
node _T_541 = dshr(incoming_writes_Q.io.deq.bits.data, _T_540)
node _T_542 = bits(_T_541, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_542
node _T_543 = eq(UInt<3>(0h4), idx_4)
when _T_543 :
node _T_544 = shl(UInt<3>(0h4), 3)
node _T_545 = dshr(incoming_writes_Q.io.deq.bits.data, _T_544)
node _T_546 = bits(_T_545, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_546
node _T_547 = eq(UInt<3>(0h5), idx_4)
when _T_547 :
node _T_548 = shl(UInt<3>(0h4), 3)
node _T_549 = dshr(incoming_writes_Q.io.deq.bits.data, _T_548)
node _T_550 = bits(_T_549, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_550
node _T_551 = eq(UInt<3>(0h6), idx_4)
when _T_551 :
node _T_552 = shl(UInt<3>(0h4), 3)
node _T_553 = dshr(incoming_writes_Q.io.deq.bits.data, _T_552)
node _T_554 = bits(_T_553, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_554
node _T_555 = eq(UInt<3>(0h7), idx_4)
when _T_555 :
node _T_556 = shl(UInt<3>(0h4), 3)
node _T_557 = dshr(incoming_writes_Q.io.deq.bits.data, _T_556)
node _T_558 = bits(_T_557, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_558
node _T_559 = eq(UInt<4>(0h8), idx_4)
when _T_559 :
node _T_560 = shl(UInt<3>(0h4), 3)
node _T_561 = dshr(incoming_writes_Q.io.deq.bits.data, _T_560)
node _T_562 = bits(_T_561, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_562
node _T_563 = eq(UInt<4>(0h9), idx_4)
when _T_563 :
node _T_564 = shl(UInt<3>(0h4), 3)
node _T_565 = dshr(incoming_writes_Q.io.deq.bits.data, _T_564)
node _T_566 = bits(_T_565, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_566
node _T_567 = eq(UInt<4>(0ha), idx_4)
when _T_567 :
node _T_568 = shl(UInt<3>(0h4), 3)
node _T_569 = dshr(incoming_writes_Q.io.deq.bits.data, _T_568)
node _T_570 = bits(_T_569, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_570
node _T_571 = eq(UInt<4>(0hb), idx_4)
when _T_571 :
node _T_572 = shl(UInt<3>(0h4), 3)
node _T_573 = dshr(incoming_writes_Q.io.deq.bits.data, _T_572)
node _T_574 = bits(_T_573, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_574
node _T_575 = eq(UInt<4>(0hc), idx_4)
when _T_575 :
node _T_576 = shl(UInt<3>(0h4), 3)
node _T_577 = dshr(incoming_writes_Q.io.deq.bits.data, _T_576)
node _T_578 = bits(_T_577, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_578
node _T_579 = eq(UInt<4>(0hd), idx_4)
when _T_579 :
node _T_580 = shl(UInt<3>(0h4), 3)
node _T_581 = dshr(incoming_writes_Q.io.deq.bits.data, _T_580)
node _T_582 = bits(_T_581, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_582
node _T_583 = eq(UInt<4>(0he), idx_4)
when _T_583 :
node _T_584 = shl(UInt<3>(0h4), 3)
node _T_585 = dshr(incoming_writes_Q.io.deq.bits.data, _T_584)
node _T_586 = bits(_T_585, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_586
node _T_587 = eq(UInt<4>(0hf), idx_4)
when _T_587 :
node _T_588 = shl(UInt<3>(0h4), 3)
node _T_589 = dshr(incoming_writes_Q.io.deq.bits.data, _T_588)
node _T_590 = bits(_T_589, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_590
node _T_591 = eq(UInt<5>(0h10), idx_4)
when _T_591 :
node _T_592 = shl(UInt<3>(0h4), 3)
node _T_593 = dshr(incoming_writes_Q.io.deq.bits.data, _T_592)
node _T_594 = bits(_T_593, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_594
node _T_595 = eq(UInt<5>(0h11), idx_4)
when _T_595 :
node _T_596 = shl(UInt<3>(0h4), 3)
node _T_597 = dshr(incoming_writes_Q.io.deq.bits.data, _T_596)
node _T_598 = bits(_T_597, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_598
node _T_599 = eq(UInt<5>(0h12), idx_4)
when _T_599 :
node _T_600 = shl(UInt<3>(0h4), 3)
node _T_601 = dshr(incoming_writes_Q.io.deq.bits.data, _T_600)
node _T_602 = bits(_T_601, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_602
node _T_603 = eq(UInt<5>(0h13), idx_4)
when _T_603 :
node _T_604 = shl(UInt<3>(0h4), 3)
node _T_605 = dshr(incoming_writes_Q.io.deq.bits.data, _T_604)
node _T_606 = bits(_T_605, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_606
node _T_607 = eq(UInt<5>(0h14), idx_4)
when _T_607 :
node _T_608 = shl(UInt<3>(0h4), 3)
node _T_609 = dshr(incoming_writes_Q.io.deq.bits.data, _T_608)
node _T_610 = bits(_T_609, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_610
node _T_611 = eq(UInt<5>(0h15), idx_4)
when _T_611 :
node _T_612 = shl(UInt<3>(0h4), 3)
node _T_613 = dshr(incoming_writes_Q.io.deq.bits.data, _T_612)
node _T_614 = bits(_T_613, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_614
node _T_615 = eq(UInt<5>(0h16), idx_4)
when _T_615 :
node _T_616 = shl(UInt<3>(0h4), 3)
node _T_617 = dshr(incoming_writes_Q.io.deq.bits.data, _T_616)
node _T_618 = bits(_T_617, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_618
node _T_619 = eq(UInt<5>(0h17), idx_4)
when _T_619 :
node _T_620 = shl(UInt<3>(0h4), 3)
node _T_621 = dshr(incoming_writes_Q.io.deq.bits.data, _T_620)
node _T_622 = bits(_T_621, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_622
node _T_623 = eq(UInt<5>(0h18), idx_4)
when _T_623 :
node _T_624 = shl(UInt<3>(0h4), 3)
node _T_625 = dshr(incoming_writes_Q.io.deq.bits.data, _T_624)
node _T_626 = bits(_T_625, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_626
node _T_627 = eq(UInt<5>(0h19), idx_4)
when _T_627 :
node _T_628 = shl(UInt<3>(0h4), 3)
node _T_629 = dshr(incoming_writes_Q.io.deq.bits.data, _T_628)
node _T_630 = bits(_T_629, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_630
node _T_631 = eq(UInt<5>(0h1a), idx_4)
when _T_631 :
node _T_632 = shl(UInt<3>(0h4), 3)
node _T_633 = dshr(incoming_writes_Q.io.deq.bits.data, _T_632)
node _T_634 = bits(_T_633, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_634
node _T_635 = eq(UInt<5>(0h1b), idx_4)
when _T_635 :
node _T_636 = shl(UInt<3>(0h4), 3)
node _T_637 = dshr(incoming_writes_Q.io.deq.bits.data, _T_636)
node _T_638 = bits(_T_637, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_638
node _T_639 = eq(UInt<5>(0h1c), idx_4)
when _T_639 :
node _T_640 = shl(UInt<3>(0h4), 3)
node _T_641 = dshr(incoming_writes_Q.io.deq.bits.data, _T_640)
node _T_642 = bits(_T_641, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_642
node _T_643 = eq(UInt<5>(0h1d), idx_4)
when _T_643 :
node _T_644 = shl(UInt<3>(0h4), 3)
node _T_645 = dshr(incoming_writes_Q.io.deq.bits.data, _T_644)
node _T_646 = bits(_T_645, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_646
node _T_647 = eq(UInt<5>(0h1e), idx_4)
when _T_647 :
node _T_648 = shl(UInt<3>(0h4), 3)
node _T_649 = dshr(incoming_writes_Q.io.deq.bits.data, _T_648)
node _T_650 = bits(_T_649, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_650
node _T_651 = eq(UInt<5>(0h1f), idx_4)
when _T_651 :
node _T_652 = shl(UInt<3>(0h4), 3)
node _T_653 = dshr(incoming_writes_Q.io.deq.bits.data, _T_652)
node _T_654 = bits(_T_653, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_654
node _idx_T_5 = add(write_start_index, UInt<3>(0h5))
node idx_5 = rem(_idx_T_5, UInt<6>(0h20))
node _T_655 = eq(UInt<1>(0h0), idx_5)
when _T_655 :
node _T_656 = shl(UInt<3>(0h5), 3)
node _T_657 = dshr(incoming_writes_Q.io.deq.bits.data, _T_656)
node _T_658 = bits(_T_657, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_658
node _T_659 = eq(UInt<1>(0h1), idx_5)
when _T_659 :
node _T_660 = shl(UInt<3>(0h5), 3)
node _T_661 = dshr(incoming_writes_Q.io.deq.bits.data, _T_660)
node _T_662 = bits(_T_661, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_662
node _T_663 = eq(UInt<2>(0h2), idx_5)
when _T_663 :
node _T_664 = shl(UInt<3>(0h5), 3)
node _T_665 = dshr(incoming_writes_Q.io.deq.bits.data, _T_664)
node _T_666 = bits(_T_665, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_666
node _T_667 = eq(UInt<2>(0h3), idx_5)
when _T_667 :
node _T_668 = shl(UInt<3>(0h5), 3)
node _T_669 = dshr(incoming_writes_Q.io.deq.bits.data, _T_668)
node _T_670 = bits(_T_669, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_670
node _T_671 = eq(UInt<3>(0h4), idx_5)
when _T_671 :
node _T_672 = shl(UInt<3>(0h5), 3)
node _T_673 = dshr(incoming_writes_Q.io.deq.bits.data, _T_672)
node _T_674 = bits(_T_673, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_674
node _T_675 = eq(UInt<3>(0h5), idx_5)
when _T_675 :
node _T_676 = shl(UInt<3>(0h5), 3)
node _T_677 = dshr(incoming_writes_Q.io.deq.bits.data, _T_676)
node _T_678 = bits(_T_677, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_678
node _T_679 = eq(UInt<3>(0h6), idx_5)
when _T_679 :
node _T_680 = shl(UInt<3>(0h5), 3)
node _T_681 = dshr(incoming_writes_Q.io.deq.bits.data, _T_680)
node _T_682 = bits(_T_681, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_682
node _T_683 = eq(UInt<3>(0h7), idx_5)
when _T_683 :
node _T_684 = shl(UInt<3>(0h5), 3)
node _T_685 = dshr(incoming_writes_Q.io.deq.bits.data, _T_684)
node _T_686 = bits(_T_685, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_686
node _T_687 = eq(UInt<4>(0h8), idx_5)
when _T_687 :
node _T_688 = shl(UInt<3>(0h5), 3)
node _T_689 = dshr(incoming_writes_Q.io.deq.bits.data, _T_688)
node _T_690 = bits(_T_689, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_690
node _T_691 = eq(UInt<4>(0h9), idx_5)
when _T_691 :
node _T_692 = shl(UInt<3>(0h5), 3)
node _T_693 = dshr(incoming_writes_Q.io.deq.bits.data, _T_692)
node _T_694 = bits(_T_693, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_694
node _T_695 = eq(UInt<4>(0ha), idx_5)
when _T_695 :
node _T_696 = shl(UInt<3>(0h5), 3)
node _T_697 = dshr(incoming_writes_Q.io.deq.bits.data, _T_696)
node _T_698 = bits(_T_697, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_698
node _T_699 = eq(UInt<4>(0hb), idx_5)
when _T_699 :
node _T_700 = shl(UInt<3>(0h5), 3)
node _T_701 = dshr(incoming_writes_Q.io.deq.bits.data, _T_700)
node _T_702 = bits(_T_701, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_702
node _T_703 = eq(UInt<4>(0hc), idx_5)
when _T_703 :
node _T_704 = shl(UInt<3>(0h5), 3)
node _T_705 = dshr(incoming_writes_Q.io.deq.bits.data, _T_704)
node _T_706 = bits(_T_705, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_706
node _T_707 = eq(UInt<4>(0hd), idx_5)
when _T_707 :
node _T_708 = shl(UInt<3>(0h5), 3)
node _T_709 = dshr(incoming_writes_Q.io.deq.bits.data, _T_708)
node _T_710 = bits(_T_709, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_710
node _T_711 = eq(UInt<4>(0he), idx_5)
when _T_711 :
node _T_712 = shl(UInt<3>(0h5), 3)
node _T_713 = dshr(incoming_writes_Q.io.deq.bits.data, _T_712)
node _T_714 = bits(_T_713, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_714
node _T_715 = eq(UInt<4>(0hf), idx_5)
when _T_715 :
node _T_716 = shl(UInt<3>(0h5), 3)
node _T_717 = dshr(incoming_writes_Q.io.deq.bits.data, _T_716)
node _T_718 = bits(_T_717, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_718
node _T_719 = eq(UInt<5>(0h10), idx_5)
when _T_719 :
node _T_720 = shl(UInt<3>(0h5), 3)
node _T_721 = dshr(incoming_writes_Q.io.deq.bits.data, _T_720)
node _T_722 = bits(_T_721, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_722
node _T_723 = eq(UInt<5>(0h11), idx_5)
when _T_723 :
node _T_724 = shl(UInt<3>(0h5), 3)
node _T_725 = dshr(incoming_writes_Q.io.deq.bits.data, _T_724)
node _T_726 = bits(_T_725, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_726
node _T_727 = eq(UInt<5>(0h12), idx_5)
when _T_727 :
node _T_728 = shl(UInt<3>(0h5), 3)
node _T_729 = dshr(incoming_writes_Q.io.deq.bits.data, _T_728)
node _T_730 = bits(_T_729, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_730
node _T_731 = eq(UInt<5>(0h13), idx_5)
when _T_731 :
node _T_732 = shl(UInt<3>(0h5), 3)
node _T_733 = dshr(incoming_writes_Q.io.deq.bits.data, _T_732)
node _T_734 = bits(_T_733, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_734
node _T_735 = eq(UInt<5>(0h14), idx_5)
when _T_735 :
node _T_736 = shl(UInt<3>(0h5), 3)
node _T_737 = dshr(incoming_writes_Q.io.deq.bits.data, _T_736)
node _T_738 = bits(_T_737, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_738
node _T_739 = eq(UInt<5>(0h15), idx_5)
when _T_739 :
node _T_740 = shl(UInt<3>(0h5), 3)
node _T_741 = dshr(incoming_writes_Q.io.deq.bits.data, _T_740)
node _T_742 = bits(_T_741, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_742
node _T_743 = eq(UInt<5>(0h16), idx_5)
when _T_743 :
node _T_744 = shl(UInt<3>(0h5), 3)
node _T_745 = dshr(incoming_writes_Q.io.deq.bits.data, _T_744)
node _T_746 = bits(_T_745, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_746
node _T_747 = eq(UInt<5>(0h17), idx_5)
when _T_747 :
node _T_748 = shl(UInt<3>(0h5), 3)
node _T_749 = dshr(incoming_writes_Q.io.deq.bits.data, _T_748)
node _T_750 = bits(_T_749, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_750
node _T_751 = eq(UInt<5>(0h18), idx_5)
when _T_751 :
node _T_752 = shl(UInt<3>(0h5), 3)
node _T_753 = dshr(incoming_writes_Q.io.deq.bits.data, _T_752)
node _T_754 = bits(_T_753, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_754
node _T_755 = eq(UInt<5>(0h19), idx_5)
when _T_755 :
node _T_756 = shl(UInt<3>(0h5), 3)
node _T_757 = dshr(incoming_writes_Q.io.deq.bits.data, _T_756)
node _T_758 = bits(_T_757, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_758
node _T_759 = eq(UInt<5>(0h1a), idx_5)
when _T_759 :
node _T_760 = shl(UInt<3>(0h5), 3)
node _T_761 = dshr(incoming_writes_Q.io.deq.bits.data, _T_760)
node _T_762 = bits(_T_761, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_762
node _T_763 = eq(UInt<5>(0h1b), idx_5)
when _T_763 :
node _T_764 = shl(UInt<3>(0h5), 3)
node _T_765 = dshr(incoming_writes_Q.io.deq.bits.data, _T_764)
node _T_766 = bits(_T_765, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_766
node _T_767 = eq(UInt<5>(0h1c), idx_5)
when _T_767 :
node _T_768 = shl(UInt<3>(0h5), 3)
node _T_769 = dshr(incoming_writes_Q.io.deq.bits.data, _T_768)
node _T_770 = bits(_T_769, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_770
node _T_771 = eq(UInt<5>(0h1d), idx_5)
when _T_771 :
node _T_772 = shl(UInt<3>(0h5), 3)
node _T_773 = dshr(incoming_writes_Q.io.deq.bits.data, _T_772)
node _T_774 = bits(_T_773, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_774
node _T_775 = eq(UInt<5>(0h1e), idx_5)
when _T_775 :
node _T_776 = shl(UInt<3>(0h5), 3)
node _T_777 = dshr(incoming_writes_Q.io.deq.bits.data, _T_776)
node _T_778 = bits(_T_777, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_778
node _T_779 = eq(UInt<5>(0h1f), idx_5)
when _T_779 :
node _T_780 = shl(UInt<3>(0h5), 3)
node _T_781 = dshr(incoming_writes_Q.io.deq.bits.data, _T_780)
node _T_782 = bits(_T_781, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_782
node _idx_T_6 = add(write_start_index, UInt<3>(0h6))
node idx_6 = rem(_idx_T_6, UInt<6>(0h20))
node _T_783 = eq(UInt<1>(0h0), idx_6)
when _T_783 :
node _T_784 = shl(UInt<3>(0h6), 3)
node _T_785 = dshr(incoming_writes_Q.io.deq.bits.data, _T_784)
node _T_786 = bits(_T_785, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_786
node _T_787 = eq(UInt<1>(0h1), idx_6)
when _T_787 :
node _T_788 = shl(UInt<3>(0h6), 3)
node _T_789 = dshr(incoming_writes_Q.io.deq.bits.data, _T_788)
node _T_790 = bits(_T_789, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_790
node _T_791 = eq(UInt<2>(0h2), idx_6)
when _T_791 :
node _T_792 = shl(UInt<3>(0h6), 3)
node _T_793 = dshr(incoming_writes_Q.io.deq.bits.data, _T_792)
node _T_794 = bits(_T_793, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_794
node _T_795 = eq(UInt<2>(0h3), idx_6)
when _T_795 :
node _T_796 = shl(UInt<3>(0h6), 3)
node _T_797 = dshr(incoming_writes_Q.io.deq.bits.data, _T_796)
node _T_798 = bits(_T_797, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_798
node _T_799 = eq(UInt<3>(0h4), idx_6)
when _T_799 :
node _T_800 = shl(UInt<3>(0h6), 3)
node _T_801 = dshr(incoming_writes_Q.io.deq.bits.data, _T_800)
node _T_802 = bits(_T_801, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_802
node _T_803 = eq(UInt<3>(0h5), idx_6)
when _T_803 :
node _T_804 = shl(UInt<3>(0h6), 3)
node _T_805 = dshr(incoming_writes_Q.io.deq.bits.data, _T_804)
node _T_806 = bits(_T_805, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_806
node _T_807 = eq(UInt<3>(0h6), idx_6)
when _T_807 :
node _T_808 = shl(UInt<3>(0h6), 3)
node _T_809 = dshr(incoming_writes_Q.io.deq.bits.data, _T_808)
node _T_810 = bits(_T_809, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_810
node _T_811 = eq(UInt<3>(0h7), idx_6)
when _T_811 :
node _T_812 = shl(UInt<3>(0h6), 3)
node _T_813 = dshr(incoming_writes_Q.io.deq.bits.data, _T_812)
node _T_814 = bits(_T_813, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_814
node _T_815 = eq(UInt<4>(0h8), idx_6)
when _T_815 :
node _T_816 = shl(UInt<3>(0h6), 3)
node _T_817 = dshr(incoming_writes_Q.io.deq.bits.data, _T_816)
node _T_818 = bits(_T_817, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_818
node _T_819 = eq(UInt<4>(0h9), idx_6)
when _T_819 :
node _T_820 = shl(UInt<3>(0h6), 3)
node _T_821 = dshr(incoming_writes_Q.io.deq.bits.data, _T_820)
node _T_822 = bits(_T_821, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_822
node _T_823 = eq(UInt<4>(0ha), idx_6)
when _T_823 :
node _T_824 = shl(UInt<3>(0h6), 3)
node _T_825 = dshr(incoming_writes_Q.io.deq.bits.data, _T_824)
node _T_826 = bits(_T_825, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_826
node _T_827 = eq(UInt<4>(0hb), idx_6)
when _T_827 :
node _T_828 = shl(UInt<3>(0h6), 3)
node _T_829 = dshr(incoming_writes_Q.io.deq.bits.data, _T_828)
node _T_830 = bits(_T_829, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_830
node _T_831 = eq(UInt<4>(0hc), idx_6)
when _T_831 :
node _T_832 = shl(UInt<3>(0h6), 3)
node _T_833 = dshr(incoming_writes_Q.io.deq.bits.data, _T_832)
node _T_834 = bits(_T_833, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_834
node _T_835 = eq(UInt<4>(0hd), idx_6)
when _T_835 :
node _T_836 = shl(UInt<3>(0h6), 3)
node _T_837 = dshr(incoming_writes_Q.io.deq.bits.data, _T_836)
node _T_838 = bits(_T_837, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_838
node _T_839 = eq(UInt<4>(0he), idx_6)
when _T_839 :
node _T_840 = shl(UInt<3>(0h6), 3)
node _T_841 = dshr(incoming_writes_Q.io.deq.bits.data, _T_840)
node _T_842 = bits(_T_841, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_842
node _T_843 = eq(UInt<4>(0hf), idx_6)
when _T_843 :
node _T_844 = shl(UInt<3>(0h6), 3)
node _T_845 = dshr(incoming_writes_Q.io.deq.bits.data, _T_844)
node _T_846 = bits(_T_845, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_846
node _T_847 = eq(UInt<5>(0h10), idx_6)
when _T_847 :
node _T_848 = shl(UInt<3>(0h6), 3)
node _T_849 = dshr(incoming_writes_Q.io.deq.bits.data, _T_848)
node _T_850 = bits(_T_849, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_850
node _T_851 = eq(UInt<5>(0h11), idx_6)
when _T_851 :
node _T_852 = shl(UInt<3>(0h6), 3)
node _T_853 = dshr(incoming_writes_Q.io.deq.bits.data, _T_852)
node _T_854 = bits(_T_853, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_854
node _T_855 = eq(UInt<5>(0h12), idx_6)
when _T_855 :
node _T_856 = shl(UInt<3>(0h6), 3)
node _T_857 = dshr(incoming_writes_Q.io.deq.bits.data, _T_856)
node _T_858 = bits(_T_857, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_858
node _T_859 = eq(UInt<5>(0h13), idx_6)
when _T_859 :
node _T_860 = shl(UInt<3>(0h6), 3)
node _T_861 = dshr(incoming_writes_Q.io.deq.bits.data, _T_860)
node _T_862 = bits(_T_861, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_862
node _T_863 = eq(UInt<5>(0h14), idx_6)
when _T_863 :
node _T_864 = shl(UInt<3>(0h6), 3)
node _T_865 = dshr(incoming_writes_Q.io.deq.bits.data, _T_864)
node _T_866 = bits(_T_865, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_866
node _T_867 = eq(UInt<5>(0h15), idx_6)
when _T_867 :
node _T_868 = shl(UInt<3>(0h6), 3)
node _T_869 = dshr(incoming_writes_Q.io.deq.bits.data, _T_868)
node _T_870 = bits(_T_869, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_870
node _T_871 = eq(UInt<5>(0h16), idx_6)
when _T_871 :
node _T_872 = shl(UInt<3>(0h6), 3)
node _T_873 = dshr(incoming_writes_Q.io.deq.bits.data, _T_872)
node _T_874 = bits(_T_873, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_874
node _T_875 = eq(UInt<5>(0h17), idx_6)
when _T_875 :
node _T_876 = shl(UInt<3>(0h6), 3)
node _T_877 = dshr(incoming_writes_Q.io.deq.bits.data, _T_876)
node _T_878 = bits(_T_877, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_878
node _T_879 = eq(UInt<5>(0h18), idx_6)
when _T_879 :
node _T_880 = shl(UInt<3>(0h6), 3)
node _T_881 = dshr(incoming_writes_Q.io.deq.bits.data, _T_880)
node _T_882 = bits(_T_881, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_882
node _T_883 = eq(UInt<5>(0h19), idx_6)
when _T_883 :
node _T_884 = shl(UInt<3>(0h6), 3)
node _T_885 = dshr(incoming_writes_Q.io.deq.bits.data, _T_884)
node _T_886 = bits(_T_885, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_886
node _T_887 = eq(UInt<5>(0h1a), idx_6)
when _T_887 :
node _T_888 = shl(UInt<3>(0h6), 3)
node _T_889 = dshr(incoming_writes_Q.io.deq.bits.data, _T_888)
node _T_890 = bits(_T_889, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_890
node _T_891 = eq(UInt<5>(0h1b), idx_6)
when _T_891 :
node _T_892 = shl(UInt<3>(0h6), 3)
node _T_893 = dshr(incoming_writes_Q.io.deq.bits.data, _T_892)
node _T_894 = bits(_T_893, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_894
node _T_895 = eq(UInt<5>(0h1c), idx_6)
when _T_895 :
node _T_896 = shl(UInt<3>(0h6), 3)
node _T_897 = dshr(incoming_writes_Q.io.deq.bits.data, _T_896)
node _T_898 = bits(_T_897, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_898
node _T_899 = eq(UInt<5>(0h1d), idx_6)
when _T_899 :
node _T_900 = shl(UInt<3>(0h6), 3)
node _T_901 = dshr(incoming_writes_Q.io.deq.bits.data, _T_900)
node _T_902 = bits(_T_901, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_902
node _T_903 = eq(UInt<5>(0h1e), idx_6)
when _T_903 :
node _T_904 = shl(UInt<3>(0h6), 3)
node _T_905 = dshr(incoming_writes_Q.io.deq.bits.data, _T_904)
node _T_906 = bits(_T_905, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_906
node _T_907 = eq(UInt<5>(0h1f), idx_6)
when _T_907 :
node _T_908 = shl(UInt<3>(0h6), 3)
node _T_909 = dshr(incoming_writes_Q.io.deq.bits.data, _T_908)
node _T_910 = bits(_T_909, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_910
node _idx_T_7 = add(write_start_index, UInt<3>(0h7))
node idx_7 = rem(_idx_T_7, UInt<6>(0h20))
node _T_911 = eq(UInt<1>(0h0), idx_7)
when _T_911 :
node _T_912 = shl(UInt<3>(0h7), 3)
node _T_913 = dshr(incoming_writes_Q.io.deq.bits.data, _T_912)
node _T_914 = bits(_T_913, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_914
node _T_915 = eq(UInt<1>(0h1), idx_7)
when _T_915 :
node _T_916 = shl(UInt<3>(0h7), 3)
node _T_917 = dshr(incoming_writes_Q.io.deq.bits.data, _T_916)
node _T_918 = bits(_T_917, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_918
node _T_919 = eq(UInt<2>(0h2), idx_7)
when _T_919 :
node _T_920 = shl(UInt<3>(0h7), 3)
node _T_921 = dshr(incoming_writes_Q.io.deq.bits.data, _T_920)
node _T_922 = bits(_T_921, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_922
node _T_923 = eq(UInt<2>(0h3), idx_7)
when _T_923 :
node _T_924 = shl(UInt<3>(0h7), 3)
node _T_925 = dshr(incoming_writes_Q.io.deq.bits.data, _T_924)
node _T_926 = bits(_T_925, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_926
node _T_927 = eq(UInt<3>(0h4), idx_7)
when _T_927 :
node _T_928 = shl(UInt<3>(0h7), 3)
node _T_929 = dshr(incoming_writes_Q.io.deq.bits.data, _T_928)
node _T_930 = bits(_T_929, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_930
node _T_931 = eq(UInt<3>(0h5), idx_7)
when _T_931 :
node _T_932 = shl(UInt<3>(0h7), 3)
node _T_933 = dshr(incoming_writes_Q.io.deq.bits.data, _T_932)
node _T_934 = bits(_T_933, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_934
node _T_935 = eq(UInt<3>(0h6), idx_7)
when _T_935 :
node _T_936 = shl(UInt<3>(0h7), 3)
node _T_937 = dshr(incoming_writes_Q.io.deq.bits.data, _T_936)
node _T_938 = bits(_T_937, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_938
node _T_939 = eq(UInt<3>(0h7), idx_7)
when _T_939 :
node _T_940 = shl(UInt<3>(0h7), 3)
node _T_941 = dshr(incoming_writes_Q.io.deq.bits.data, _T_940)
node _T_942 = bits(_T_941, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_942
node _T_943 = eq(UInt<4>(0h8), idx_7)
when _T_943 :
node _T_944 = shl(UInt<3>(0h7), 3)
node _T_945 = dshr(incoming_writes_Q.io.deq.bits.data, _T_944)
node _T_946 = bits(_T_945, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_946
node _T_947 = eq(UInt<4>(0h9), idx_7)
when _T_947 :
node _T_948 = shl(UInt<3>(0h7), 3)
node _T_949 = dshr(incoming_writes_Q.io.deq.bits.data, _T_948)
node _T_950 = bits(_T_949, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_950
node _T_951 = eq(UInt<4>(0ha), idx_7)
when _T_951 :
node _T_952 = shl(UInt<3>(0h7), 3)
node _T_953 = dshr(incoming_writes_Q.io.deq.bits.data, _T_952)
node _T_954 = bits(_T_953, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_954
node _T_955 = eq(UInt<4>(0hb), idx_7)
when _T_955 :
node _T_956 = shl(UInt<3>(0h7), 3)
node _T_957 = dshr(incoming_writes_Q.io.deq.bits.data, _T_956)
node _T_958 = bits(_T_957, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_958
node _T_959 = eq(UInt<4>(0hc), idx_7)
when _T_959 :
node _T_960 = shl(UInt<3>(0h7), 3)
node _T_961 = dshr(incoming_writes_Q.io.deq.bits.data, _T_960)
node _T_962 = bits(_T_961, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_962
node _T_963 = eq(UInt<4>(0hd), idx_7)
when _T_963 :
node _T_964 = shl(UInt<3>(0h7), 3)
node _T_965 = dshr(incoming_writes_Q.io.deq.bits.data, _T_964)
node _T_966 = bits(_T_965, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_966
node _T_967 = eq(UInt<4>(0he), idx_7)
when _T_967 :
node _T_968 = shl(UInt<3>(0h7), 3)
node _T_969 = dshr(incoming_writes_Q.io.deq.bits.data, _T_968)
node _T_970 = bits(_T_969, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_970
node _T_971 = eq(UInt<4>(0hf), idx_7)
when _T_971 :
node _T_972 = shl(UInt<3>(0h7), 3)
node _T_973 = dshr(incoming_writes_Q.io.deq.bits.data, _T_972)
node _T_974 = bits(_T_973, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_974
node _T_975 = eq(UInt<5>(0h10), idx_7)
when _T_975 :
node _T_976 = shl(UInt<3>(0h7), 3)
node _T_977 = dshr(incoming_writes_Q.io.deq.bits.data, _T_976)
node _T_978 = bits(_T_977, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_978
node _T_979 = eq(UInt<5>(0h11), idx_7)
when _T_979 :
node _T_980 = shl(UInt<3>(0h7), 3)
node _T_981 = dshr(incoming_writes_Q.io.deq.bits.data, _T_980)
node _T_982 = bits(_T_981, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_982
node _T_983 = eq(UInt<5>(0h12), idx_7)
when _T_983 :
node _T_984 = shl(UInt<3>(0h7), 3)
node _T_985 = dshr(incoming_writes_Q.io.deq.bits.data, _T_984)
node _T_986 = bits(_T_985, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_986
node _T_987 = eq(UInt<5>(0h13), idx_7)
when _T_987 :
node _T_988 = shl(UInt<3>(0h7), 3)
node _T_989 = dshr(incoming_writes_Q.io.deq.bits.data, _T_988)
node _T_990 = bits(_T_989, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_990
node _T_991 = eq(UInt<5>(0h14), idx_7)
when _T_991 :
node _T_992 = shl(UInt<3>(0h7), 3)
node _T_993 = dshr(incoming_writes_Q.io.deq.bits.data, _T_992)
node _T_994 = bits(_T_993, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_994
node _T_995 = eq(UInt<5>(0h15), idx_7)
when _T_995 :
node _T_996 = shl(UInt<3>(0h7), 3)
node _T_997 = dshr(incoming_writes_Q.io.deq.bits.data, _T_996)
node _T_998 = bits(_T_997, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_998
node _T_999 = eq(UInt<5>(0h16), idx_7)
when _T_999 :
node _T_1000 = shl(UInt<3>(0h7), 3)
node _T_1001 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1000)
node _T_1002 = bits(_T_1001, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_1002
node _T_1003 = eq(UInt<5>(0h17), idx_7)
when _T_1003 :
node _T_1004 = shl(UInt<3>(0h7), 3)
node _T_1005 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1004)
node _T_1006 = bits(_T_1005, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_1006
node _T_1007 = eq(UInt<5>(0h18), idx_7)
when _T_1007 :
node _T_1008 = shl(UInt<3>(0h7), 3)
node _T_1009 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1008)
node _T_1010 = bits(_T_1009, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_1010
node _T_1011 = eq(UInt<5>(0h19), idx_7)
when _T_1011 :
node _T_1012 = shl(UInt<3>(0h7), 3)
node _T_1013 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1012)
node _T_1014 = bits(_T_1013, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_1014
node _T_1015 = eq(UInt<5>(0h1a), idx_7)
when _T_1015 :
node _T_1016 = shl(UInt<3>(0h7), 3)
node _T_1017 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1016)
node _T_1018 = bits(_T_1017, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_1018
node _T_1019 = eq(UInt<5>(0h1b), idx_7)
when _T_1019 :
node _T_1020 = shl(UInt<3>(0h7), 3)
node _T_1021 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1020)
node _T_1022 = bits(_T_1021, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_1022
node _T_1023 = eq(UInt<5>(0h1c), idx_7)
when _T_1023 :
node _T_1024 = shl(UInt<3>(0h7), 3)
node _T_1025 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1024)
node _T_1026 = bits(_T_1025, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_1026
node _T_1027 = eq(UInt<5>(0h1d), idx_7)
when _T_1027 :
node _T_1028 = shl(UInt<3>(0h7), 3)
node _T_1029 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1028)
node _T_1030 = bits(_T_1029, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_1030
node _T_1031 = eq(UInt<5>(0h1e), idx_7)
when _T_1031 :
node _T_1032 = shl(UInt<3>(0h7), 3)
node _T_1033 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1032)
node _T_1034 = bits(_T_1033, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_1034
node _T_1035 = eq(UInt<5>(0h1f), idx_7)
when _T_1035 :
node _T_1036 = shl(UInt<3>(0h7), 3)
node _T_1037 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1036)
node _T_1038 = bits(_T_1037, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_1038
node _idx_T_8 = add(write_start_index, UInt<4>(0h8))
node idx_8 = rem(_idx_T_8, UInt<6>(0h20))
node _T_1039 = eq(UInt<1>(0h0), idx_8)
when _T_1039 :
node _T_1040 = shl(UInt<4>(0h8), 3)
node _T_1041 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1040)
node _T_1042 = bits(_T_1041, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_1042
node _T_1043 = eq(UInt<1>(0h1), idx_8)
when _T_1043 :
node _T_1044 = shl(UInt<4>(0h8), 3)
node _T_1045 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1044)
node _T_1046 = bits(_T_1045, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_1046
node _T_1047 = eq(UInt<2>(0h2), idx_8)
when _T_1047 :
node _T_1048 = shl(UInt<4>(0h8), 3)
node _T_1049 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1048)
node _T_1050 = bits(_T_1049, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_1050
node _T_1051 = eq(UInt<2>(0h3), idx_8)
when _T_1051 :
node _T_1052 = shl(UInt<4>(0h8), 3)
node _T_1053 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1052)
node _T_1054 = bits(_T_1053, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_1054
node _T_1055 = eq(UInt<3>(0h4), idx_8)
when _T_1055 :
node _T_1056 = shl(UInt<4>(0h8), 3)
node _T_1057 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1056)
node _T_1058 = bits(_T_1057, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_1058
node _T_1059 = eq(UInt<3>(0h5), idx_8)
when _T_1059 :
node _T_1060 = shl(UInt<4>(0h8), 3)
node _T_1061 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1060)
node _T_1062 = bits(_T_1061, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_1062
node _T_1063 = eq(UInt<3>(0h6), idx_8)
when _T_1063 :
node _T_1064 = shl(UInt<4>(0h8), 3)
node _T_1065 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1064)
node _T_1066 = bits(_T_1065, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_1066
node _T_1067 = eq(UInt<3>(0h7), idx_8)
when _T_1067 :
node _T_1068 = shl(UInt<4>(0h8), 3)
node _T_1069 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1068)
node _T_1070 = bits(_T_1069, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_1070
node _T_1071 = eq(UInt<4>(0h8), idx_8)
when _T_1071 :
node _T_1072 = shl(UInt<4>(0h8), 3)
node _T_1073 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1072)
node _T_1074 = bits(_T_1073, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_1074
node _T_1075 = eq(UInt<4>(0h9), idx_8)
when _T_1075 :
node _T_1076 = shl(UInt<4>(0h8), 3)
node _T_1077 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1076)
node _T_1078 = bits(_T_1077, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_1078
node _T_1079 = eq(UInt<4>(0ha), idx_8)
when _T_1079 :
node _T_1080 = shl(UInt<4>(0h8), 3)
node _T_1081 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1080)
node _T_1082 = bits(_T_1081, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_1082
node _T_1083 = eq(UInt<4>(0hb), idx_8)
when _T_1083 :
node _T_1084 = shl(UInt<4>(0h8), 3)
node _T_1085 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1084)
node _T_1086 = bits(_T_1085, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_1086
node _T_1087 = eq(UInt<4>(0hc), idx_8)
when _T_1087 :
node _T_1088 = shl(UInt<4>(0h8), 3)
node _T_1089 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1088)
node _T_1090 = bits(_T_1089, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_1090
node _T_1091 = eq(UInt<4>(0hd), idx_8)
when _T_1091 :
node _T_1092 = shl(UInt<4>(0h8), 3)
node _T_1093 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1092)
node _T_1094 = bits(_T_1093, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_1094
node _T_1095 = eq(UInt<4>(0he), idx_8)
when _T_1095 :
node _T_1096 = shl(UInt<4>(0h8), 3)
node _T_1097 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1096)
node _T_1098 = bits(_T_1097, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_1098
node _T_1099 = eq(UInt<4>(0hf), idx_8)
when _T_1099 :
node _T_1100 = shl(UInt<4>(0h8), 3)
node _T_1101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1100)
node _T_1102 = bits(_T_1101, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_1102
node _T_1103 = eq(UInt<5>(0h10), idx_8)
when _T_1103 :
node _T_1104 = shl(UInt<4>(0h8), 3)
node _T_1105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1104)
node _T_1106 = bits(_T_1105, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_1106
node _T_1107 = eq(UInt<5>(0h11), idx_8)
when _T_1107 :
node _T_1108 = shl(UInt<4>(0h8), 3)
node _T_1109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1108)
node _T_1110 = bits(_T_1109, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_1110
node _T_1111 = eq(UInt<5>(0h12), idx_8)
when _T_1111 :
node _T_1112 = shl(UInt<4>(0h8), 3)
node _T_1113 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1112)
node _T_1114 = bits(_T_1113, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_1114
node _T_1115 = eq(UInt<5>(0h13), idx_8)
when _T_1115 :
node _T_1116 = shl(UInt<4>(0h8), 3)
node _T_1117 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1116)
node _T_1118 = bits(_T_1117, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_1118
node _T_1119 = eq(UInt<5>(0h14), idx_8)
when _T_1119 :
node _T_1120 = shl(UInt<4>(0h8), 3)
node _T_1121 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1120)
node _T_1122 = bits(_T_1121, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_1122
node _T_1123 = eq(UInt<5>(0h15), idx_8)
when _T_1123 :
node _T_1124 = shl(UInt<4>(0h8), 3)
node _T_1125 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1124)
node _T_1126 = bits(_T_1125, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_1126
node _T_1127 = eq(UInt<5>(0h16), idx_8)
when _T_1127 :
node _T_1128 = shl(UInt<4>(0h8), 3)
node _T_1129 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1128)
node _T_1130 = bits(_T_1129, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_1130
node _T_1131 = eq(UInt<5>(0h17), idx_8)
when _T_1131 :
node _T_1132 = shl(UInt<4>(0h8), 3)
node _T_1133 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1132)
node _T_1134 = bits(_T_1133, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_1134
node _T_1135 = eq(UInt<5>(0h18), idx_8)
when _T_1135 :
node _T_1136 = shl(UInt<4>(0h8), 3)
node _T_1137 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1136)
node _T_1138 = bits(_T_1137, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_1138
node _T_1139 = eq(UInt<5>(0h19), idx_8)
when _T_1139 :
node _T_1140 = shl(UInt<4>(0h8), 3)
node _T_1141 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1140)
node _T_1142 = bits(_T_1141, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_1142
node _T_1143 = eq(UInt<5>(0h1a), idx_8)
when _T_1143 :
node _T_1144 = shl(UInt<4>(0h8), 3)
node _T_1145 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1144)
node _T_1146 = bits(_T_1145, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_1146
node _T_1147 = eq(UInt<5>(0h1b), idx_8)
when _T_1147 :
node _T_1148 = shl(UInt<4>(0h8), 3)
node _T_1149 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1148)
node _T_1150 = bits(_T_1149, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_1150
node _T_1151 = eq(UInt<5>(0h1c), idx_8)
when _T_1151 :
node _T_1152 = shl(UInt<4>(0h8), 3)
node _T_1153 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1152)
node _T_1154 = bits(_T_1153, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_1154
node _T_1155 = eq(UInt<5>(0h1d), idx_8)
when _T_1155 :
node _T_1156 = shl(UInt<4>(0h8), 3)
node _T_1157 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1156)
node _T_1158 = bits(_T_1157, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_1158
node _T_1159 = eq(UInt<5>(0h1e), idx_8)
when _T_1159 :
node _T_1160 = shl(UInt<4>(0h8), 3)
node _T_1161 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1160)
node _T_1162 = bits(_T_1161, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_1162
node _T_1163 = eq(UInt<5>(0h1f), idx_8)
when _T_1163 :
node _T_1164 = shl(UInt<4>(0h8), 3)
node _T_1165 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1164)
node _T_1166 = bits(_T_1165, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_1166
node _idx_T_9 = add(write_start_index, UInt<4>(0h9))
node idx_9 = rem(_idx_T_9, UInt<6>(0h20))
node _T_1167 = eq(UInt<1>(0h0), idx_9)
when _T_1167 :
node _T_1168 = shl(UInt<4>(0h9), 3)
node _T_1169 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1168)
node _T_1170 = bits(_T_1169, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_1170
node _T_1171 = eq(UInt<1>(0h1), idx_9)
when _T_1171 :
node _T_1172 = shl(UInt<4>(0h9), 3)
node _T_1173 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1172)
node _T_1174 = bits(_T_1173, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_1174
node _T_1175 = eq(UInt<2>(0h2), idx_9)
when _T_1175 :
node _T_1176 = shl(UInt<4>(0h9), 3)
node _T_1177 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1176)
node _T_1178 = bits(_T_1177, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_1178
node _T_1179 = eq(UInt<2>(0h3), idx_9)
when _T_1179 :
node _T_1180 = shl(UInt<4>(0h9), 3)
node _T_1181 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1180)
node _T_1182 = bits(_T_1181, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_1182
node _T_1183 = eq(UInt<3>(0h4), idx_9)
when _T_1183 :
node _T_1184 = shl(UInt<4>(0h9), 3)
node _T_1185 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1184)
node _T_1186 = bits(_T_1185, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_1186
node _T_1187 = eq(UInt<3>(0h5), idx_9)
when _T_1187 :
node _T_1188 = shl(UInt<4>(0h9), 3)
node _T_1189 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1188)
node _T_1190 = bits(_T_1189, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_1190
node _T_1191 = eq(UInt<3>(0h6), idx_9)
when _T_1191 :
node _T_1192 = shl(UInt<4>(0h9), 3)
node _T_1193 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1192)
node _T_1194 = bits(_T_1193, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_1194
node _T_1195 = eq(UInt<3>(0h7), idx_9)
when _T_1195 :
node _T_1196 = shl(UInt<4>(0h9), 3)
node _T_1197 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1196)
node _T_1198 = bits(_T_1197, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_1198
node _T_1199 = eq(UInt<4>(0h8), idx_9)
when _T_1199 :
node _T_1200 = shl(UInt<4>(0h9), 3)
node _T_1201 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1200)
node _T_1202 = bits(_T_1201, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_1202
node _T_1203 = eq(UInt<4>(0h9), idx_9)
when _T_1203 :
node _T_1204 = shl(UInt<4>(0h9), 3)
node _T_1205 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1204)
node _T_1206 = bits(_T_1205, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_1206
node _T_1207 = eq(UInt<4>(0ha), idx_9)
when _T_1207 :
node _T_1208 = shl(UInt<4>(0h9), 3)
node _T_1209 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1208)
node _T_1210 = bits(_T_1209, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_1210
node _T_1211 = eq(UInt<4>(0hb), idx_9)
when _T_1211 :
node _T_1212 = shl(UInt<4>(0h9), 3)
node _T_1213 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1212)
node _T_1214 = bits(_T_1213, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_1214
node _T_1215 = eq(UInt<4>(0hc), idx_9)
when _T_1215 :
node _T_1216 = shl(UInt<4>(0h9), 3)
node _T_1217 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1216)
node _T_1218 = bits(_T_1217, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_1218
node _T_1219 = eq(UInt<4>(0hd), idx_9)
when _T_1219 :
node _T_1220 = shl(UInt<4>(0h9), 3)
node _T_1221 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1220)
node _T_1222 = bits(_T_1221, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_1222
node _T_1223 = eq(UInt<4>(0he), idx_9)
when _T_1223 :
node _T_1224 = shl(UInt<4>(0h9), 3)
node _T_1225 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1224)
node _T_1226 = bits(_T_1225, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_1226
node _T_1227 = eq(UInt<4>(0hf), idx_9)
when _T_1227 :
node _T_1228 = shl(UInt<4>(0h9), 3)
node _T_1229 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1228)
node _T_1230 = bits(_T_1229, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_1230
node _T_1231 = eq(UInt<5>(0h10), idx_9)
when _T_1231 :
node _T_1232 = shl(UInt<4>(0h9), 3)
node _T_1233 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1232)
node _T_1234 = bits(_T_1233, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_1234
node _T_1235 = eq(UInt<5>(0h11), idx_9)
when _T_1235 :
node _T_1236 = shl(UInt<4>(0h9), 3)
node _T_1237 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1236)
node _T_1238 = bits(_T_1237, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_1238
node _T_1239 = eq(UInt<5>(0h12), idx_9)
when _T_1239 :
node _T_1240 = shl(UInt<4>(0h9), 3)
node _T_1241 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1240)
node _T_1242 = bits(_T_1241, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_1242
node _T_1243 = eq(UInt<5>(0h13), idx_9)
when _T_1243 :
node _T_1244 = shl(UInt<4>(0h9), 3)
node _T_1245 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1244)
node _T_1246 = bits(_T_1245, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_1246
node _T_1247 = eq(UInt<5>(0h14), idx_9)
when _T_1247 :
node _T_1248 = shl(UInt<4>(0h9), 3)
node _T_1249 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1248)
node _T_1250 = bits(_T_1249, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_1250
node _T_1251 = eq(UInt<5>(0h15), idx_9)
when _T_1251 :
node _T_1252 = shl(UInt<4>(0h9), 3)
node _T_1253 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1252)
node _T_1254 = bits(_T_1253, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_1254
node _T_1255 = eq(UInt<5>(0h16), idx_9)
when _T_1255 :
node _T_1256 = shl(UInt<4>(0h9), 3)
node _T_1257 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1256)
node _T_1258 = bits(_T_1257, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_1258
node _T_1259 = eq(UInt<5>(0h17), idx_9)
when _T_1259 :
node _T_1260 = shl(UInt<4>(0h9), 3)
node _T_1261 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1260)
node _T_1262 = bits(_T_1261, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_1262
node _T_1263 = eq(UInt<5>(0h18), idx_9)
when _T_1263 :
node _T_1264 = shl(UInt<4>(0h9), 3)
node _T_1265 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1264)
node _T_1266 = bits(_T_1265, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_1266
node _T_1267 = eq(UInt<5>(0h19), idx_9)
when _T_1267 :
node _T_1268 = shl(UInt<4>(0h9), 3)
node _T_1269 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1268)
node _T_1270 = bits(_T_1269, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_1270
node _T_1271 = eq(UInt<5>(0h1a), idx_9)
when _T_1271 :
node _T_1272 = shl(UInt<4>(0h9), 3)
node _T_1273 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1272)
node _T_1274 = bits(_T_1273, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_1274
node _T_1275 = eq(UInt<5>(0h1b), idx_9)
when _T_1275 :
node _T_1276 = shl(UInt<4>(0h9), 3)
node _T_1277 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1276)
node _T_1278 = bits(_T_1277, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_1278
node _T_1279 = eq(UInt<5>(0h1c), idx_9)
when _T_1279 :
node _T_1280 = shl(UInt<4>(0h9), 3)
node _T_1281 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1280)
node _T_1282 = bits(_T_1281, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_1282
node _T_1283 = eq(UInt<5>(0h1d), idx_9)
when _T_1283 :
node _T_1284 = shl(UInt<4>(0h9), 3)
node _T_1285 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1284)
node _T_1286 = bits(_T_1285, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_1286
node _T_1287 = eq(UInt<5>(0h1e), idx_9)
when _T_1287 :
node _T_1288 = shl(UInt<4>(0h9), 3)
node _T_1289 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1288)
node _T_1290 = bits(_T_1289, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_1290
node _T_1291 = eq(UInt<5>(0h1f), idx_9)
when _T_1291 :
node _T_1292 = shl(UInt<4>(0h9), 3)
node _T_1293 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1292)
node _T_1294 = bits(_T_1293, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_1294
node _idx_T_10 = add(write_start_index, UInt<4>(0ha))
node idx_10 = rem(_idx_T_10, UInt<6>(0h20))
node _T_1295 = eq(UInt<1>(0h0), idx_10)
when _T_1295 :
node _T_1296 = shl(UInt<4>(0ha), 3)
node _T_1297 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1296)
node _T_1298 = bits(_T_1297, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_1298
node _T_1299 = eq(UInt<1>(0h1), idx_10)
when _T_1299 :
node _T_1300 = shl(UInt<4>(0ha), 3)
node _T_1301 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1300)
node _T_1302 = bits(_T_1301, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_1302
node _T_1303 = eq(UInt<2>(0h2), idx_10)
when _T_1303 :
node _T_1304 = shl(UInt<4>(0ha), 3)
node _T_1305 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1304)
node _T_1306 = bits(_T_1305, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_1306
node _T_1307 = eq(UInt<2>(0h3), idx_10)
when _T_1307 :
node _T_1308 = shl(UInt<4>(0ha), 3)
node _T_1309 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1308)
node _T_1310 = bits(_T_1309, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_1310
node _T_1311 = eq(UInt<3>(0h4), idx_10)
when _T_1311 :
node _T_1312 = shl(UInt<4>(0ha), 3)
node _T_1313 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1312)
node _T_1314 = bits(_T_1313, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_1314
node _T_1315 = eq(UInt<3>(0h5), idx_10)
when _T_1315 :
node _T_1316 = shl(UInt<4>(0ha), 3)
node _T_1317 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1316)
node _T_1318 = bits(_T_1317, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_1318
node _T_1319 = eq(UInt<3>(0h6), idx_10)
when _T_1319 :
node _T_1320 = shl(UInt<4>(0ha), 3)
node _T_1321 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1320)
node _T_1322 = bits(_T_1321, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_1322
node _T_1323 = eq(UInt<3>(0h7), idx_10)
when _T_1323 :
node _T_1324 = shl(UInt<4>(0ha), 3)
node _T_1325 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1324)
node _T_1326 = bits(_T_1325, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_1326
node _T_1327 = eq(UInt<4>(0h8), idx_10)
when _T_1327 :
node _T_1328 = shl(UInt<4>(0ha), 3)
node _T_1329 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1328)
node _T_1330 = bits(_T_1329, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_1330
node _T_1331 = eq(UInt<4>(0h9), idx_10)
when _T_1331 :
node _T_1332 = shl(UInt<4>(0ha), 3)
node _T_1333 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1332)
node _T_1334 = bits(_T_1333, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_1334
node _T_1335 = eq(UInt<4>(0ha), idx_10)
when _T_1335 :
node _T_1336 = shl(UInt<4>(0ha), 3)
node _T_1337 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1336)
node _T_1338 = bits(_T_1337, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_1338
node _T_1339 = eq(UInt<4>(0hb), idx_10)
when _T_1339 :
node _T_1340 = shl(UInt<4>(0ha), 3)
node _T_1341 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1340)
node _T_1342 = bits(_T_1341, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_1342
node _T_1343 = eq(UInt<4>(0hc), idx_10)
when _T_1343 :
node _T_1344 = shl(UInt<4>(0ha), 3)
node _T_1345 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1344)
node _T_1346 = bits(_T_1345, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_1346
node _T_1347 = eq(UInt<4>(0hd), idx_10)
when _T_1347 :
node _T_1348 = shl(UInt<4>(0ha), 3)
node _T_1349 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1348)
node _T_1350 = bits(_T_1349, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_1350
node _T_1351 = eq(UInt<4>(0he), idx_10)
when _T_1351 :
node _T_1352 = shl(UInt<4>(0ha), 3)
node _T_1353 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1352)
node _T_1354 = bits(_T_1353, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_1354
node _T_1355 = eq(UInt<4>(0hf), idx_10)
when _T_1355 :
node _T_1356 = shl(UInt<4>(0ha), 3)
node _T_1357 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1356)
node _T_1358 = bits(_T_1357, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_1358
node _T_1359 = eq(UInt<5>(0h10), idx_10)
when _T_1359 :
node _T_1360 = shl(UInt<4>(0ha), 3)
node _T_1361 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1360)
node _T_1362 = bits(_T_1361, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_1362
node _T_1363 = eq(UInt<5>(0h11), idx_10)
when _T_1363 :
node _T_1364 = shl(UInt<4>(0ha), 3)
node _T_1365 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1364)
node _T_1366 = bits(_T_1365, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_1366
node _T_1367 = eq(UInt<5>(0h12), idx_10)
when _T_1367 :
node _T_1368 = shl(UInt<4>(0ha), 3)
node _T_1369 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1368)
node _T_1370 = bits(_T_1369, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_1370
node _T_1371 = eq(UInt<5>(0h13), idx_10)
when _T_1371 :
node _T_1372 = shl(UInt<4>(0ha), 3)
node _T_1373 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1372)
node _T_1374 = bits(_T_1373, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_1374
node _T_1375 = eq(UInt<5>(0h14), idx_10)
when _T_1375 :
node _T_1376 = shl(UInt<4>(0ha), 3)
node _T_1377 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1376)
node _T_1378 = bits(_T_1377, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_1378
node _T_1379 = eq(UInt<5>(0h15), idx_10)
when _T_1379 :
node _T_1380 = shl(UInt<4>(0ha), 3)
node _T_1381 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1380)
node _T_1382 = bits(_T_1381, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_1382
node _T_1383 = eq(UInt<5>(0h16), idx_10)
when _T_1383 :
node _T_1384 = shl(UInt<4>(0ha), 3)
node _T_1385 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1384)
node _T_1386 = bits(_T_1385, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_1386
node _T_1387 = eq(UInt<5>(0h17), idx_10)
when _T_1387 :
node _T_1388 = shl(UInt<4>(0ha), 3)
node _T_1389 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1388)
node _T_1390 = bits(_T_1389, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_1390
node _T_1391 = eq(UInt<5>(0h18), idx_10)
when _T_1391 :
node _T_1392 = shl(UInt<4>(0ha), 3)
node _T_1393 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1392)
node _T_1394 = bits(_T_1393, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_1394
node _T_1395 = eq(UInt<5>(0h19), idx_10)
when _T_1395 :
node _T_1396 = shl(UInt<4>(0ha), 3)
node _T_1397 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1396)
node _T_1398 = bits(_T_1397, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_1398
node _T_1399 = eq(UInt<5>(0h1a), idx_10)
when _T_1399 :
node _T_1400 = shl(UInt<4>(0ha), 3)
node _T_1401 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1400)
node _T_1402 = bits(_T_1401, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_1402
node _T_1403 = eq(UInt<5>(0h1b), idx_10)
when _T_1403 :
node _T_1404 = shl(UInt<4>(0ha), 3)
node _T_1405 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1404)
node _T_1406 = bits(_T_1405, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_1406
node _T_1407 = eq(UInt<5>(0h1c), idx_10)
when _T_1407 :
node _T_1408 = shl(UInt<4>(0ha), 3)
node _T_1409 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1408)
node _T_1410 = bits(_T_1409, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_1410
node _T_1411 = eq(UInt<5>(0h1d), idx_10)
when _T_1411 :
node _T_1412 = shl(UInt<4>(0ha), 3)
node _T_1413 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1412)
node _T_1414 = bits(_T_1413, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_1414
node _T_1415 = eq(UInt<5>(0h1e), idx_10)
when _T_1415 :
node _T_1416 = shl(UInt<4>(0ha), 3)
node _T_1417 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1416)
node _T_1418 = bits(_T_1417, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_1418
node _T_1419 = eq(UInt<5>(0h1f), idx_10)
when _T_1419 :
node _T_1420 = shl(UInt<4>(0ha), 3)
node _T_1421 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1420)
node _T_1422 = bits(_T_1421, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_1422
node _idx_T_11 = add(write_start_index, UInt<4>(0hb))
node idx_11 = rem(_idx_T_11, UInt<6>(0h20))
node _T_1423 = eq(UInt<1>(0h0), idx_11)
when _T_1423 :
node _T_1424 = shl(UInt<4>(0hb), 3)
node _T_1425 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1424)
node _T_1426 = bits(_T_1425, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_1426
node _T_1427 = eq(UInt<1>(0h1), idx_11)
when _T_1427 :
node _T_1428 = shl(UInt<4>(0hb), 3)
node _T_1429 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1428)
node _T_1430 = bits(_T_1429, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_1430
node _T_1431 = eq(UInt<2>(0h2), idx_11)
when _T_1431 :
node _T_1432 = shl(UInt<4>(0hb), 3)
node _T_1433 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1432)
node _T_1434 = bits(_T_1433, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_1434
node _T_1435 = eq(UInt<2>(0h3), idx_11)
when _T_1435 :
node _T_1436 = shl(UInt<4>(0hb), 3)
node _T_1437 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1436)
node _T_1438 = bits(_T_1437, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_1438
node _T_1439 = eq(UInt<3>(0h4), idx_11)
when _T_1439 :
node _T_1440 = shl(UInt<4>(0hb), 3)
node _T_1441 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1440)
node _T_1442 = bits(_T_1441, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_1442
node _T_1443 = eq(UInt<3>(0h5), idx_11)
when _T_1443 :
node _T_1444 = shl(UInt<4>(0hb), 3)
node _T_1445 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1444)
node _T_1446 = bits(_T_1445, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_1446
node _T_1447 = eq(UInt<3>(0h6), idx_11)
when _T_1447 :
node _T_1448 = shl(UInt<4>(0hb), 3)
node _T_1449 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1448)
node _T_1450 = bits(_T_1449, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_1450
node _T_1451 = eq(UInt<3>(0h7), idx_11)
when _T_1451 :
node _T_1452 = shl(UInt<4>(0hb), 3)
node _T_1453 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1452)
node _T_1454 = bits(_T_1453, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_1454
node _T_1455 = eq(UInt<4>(0h8), idx_11)
when _T_1455 :
node _T_1456 = shl(UInt<4>(0hb), 3)
node _T_1457 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1456)
node _T_1458 = bits(_T_1457, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_1458
node _T_1459 = eq(UInt<4>(0h9), idx_11)
when _T_1459 :
node _T_1460 = shl(UInt<4>(0hb), 3)
node _T_1461 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1460)
node _T_1462 = bits(_T_1461, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_1462
node _T_1463 = eq(UInt<4>(0ha), idx_11)
when _T_1463 :
node _T_1464 = shl(UInt<4>(0hb), 3)
node _T_1465 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1464)
node _T_1466 = bits(_T_1465, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_1466
node _T_1467 = eq(UInt<4>(0hb), idx_11)
when _T_1467 :
node _T_1468 = shl(UInt<4>(0hb), 3)
node _T_1469 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1468)
node _T_1470 = bits(_T_1469, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_1470
node _T_1471 = eq(UInt<4>(0hc), idx_11)
when _T_1471 :
node _T_1472 = shl(UInt<4>(0hb), 3)
node _T_1473 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1472)
node _T_1474 = bits(_T_1473, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_1474
node _T_1475 = eq(UInt<4>(0hd), idx_11)
when _T_1475 :
node _T_1476 = shl(UInt<4>(0hb), 3)
node _T_1477 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1476)
node _T_1478 = bits(_T_1477, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_1478
node _T_1479 = eq(UInt<4>(0he), idx_11)
when _T_1479 :
node _T_1480 = shl(UInt<4>(0hb), 3)
node _T_1481 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1480)
node _T_1482 = bits(_T_1481, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_1482
node _T_1483 = eq(UInt<4>(0hf), idx_11)
when _T_1483 :
node _T_1484 = shl(UInt<4>(0hb), 3)
node _T_1485 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1484)
node _T_1486 = bits(_T_1485, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_1486
node _T_1487 = eq(UInt<5>(0h10), idx_11)
when _T_1487 :
node _T_1488 = shl(UInt<4>(0hb), 3)
node _T_1489 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1488)
node _T_1490 = bits(_T_1489, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_1490
node _T_1491 = eq(UInt<5>(0h11), idx_11)
when _T_1491 :
node _T_1492 = shl(UInt<4>(0hb), 3)
node _T_1493 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1492)
node _T_1494 = bits(_T_1493, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_1494
node _T_1495 = eq(UInt<5>(0h12), idx_11)
when _T_1495 :
node _T_1496 = shl(UInt<4>(0hb), 3)
node _T_1497 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1496)
node _T_1498 = bits(_T_1497, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_1498
node _T_1499 = eq(UInt<5>(0h13), idx_11)
when _T_1499 :
node _T_1500 = shl(UInt<4>(0hb), 3)
node _T_1501 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1500)
node _T_1502 = bits(_T_1501, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_1502
node _T_1503 = eq(UInt<5>(0h14), idx_11)
when _T_1503 :
node _T_1504 = shl(UInt<4>(0hb), 3)
node _T_1505 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1504)
node _T_1506 = bits(_T_1505, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_1506
node _T_1507 = eq(UInt<5>(0h15), idx_11)
when _T_1507 :
node _T_1508 = shl(UInt<4>(0hb), 3)
node _T_1509 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1508)
node _T_1510 = bits(_T_1509, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_1510
node _T_1511 = eq(UInt<5>(0h16), idx_11)
when _T_1511 :
node _T_1512 = shl(UInt<4>(0hb), 3)
node _T_1513 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1512)
node _T_1514 = bits(_T_1513, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_1514
node _T_1515 = eq(UInt<5>(0h17), idx_11)
when _T_1515 :
node _T_1516 = shl(UInt<4>(0hb), 3)
node _T_1517 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1516)
node _T_1518 = bits(_T_1517, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_1518
node _T_1519 = eq(UInt<5>(0h18), idx_11)
when _T_1519 :
node _T_1520 = shl(UInt<4>(0hb), 3)
node _T_1521 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1520)
node _T_1522 = bits(_T_1521, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_1522
node _T_1523 = eq(UInt<5>(0h19), idx_11)
when _T_1523 :
node _T_1524 = shl(UInt<4>(0hb), 3)
node _T_1525 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1524)
node _T_1526 = bits(_T_1525, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_1526
node _T_1527 = eq(UInt<5>(0h1a), idx_11)
when _T_1527 :
node _T_1528 = shl(UInt<4>(0hb), 3)
node _T_1529 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1528)
node _T_1530 = bits(_T_1529, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_1530
node _T_1531 = eq(UInt<5>(0h1b), idx_11)
when _T_1531 :
node _T_1532 = shl(UInt<4>(0hb), 3)
node _T_1533 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1532)
node _T_1534 = bits(_T_1533, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_1534
node _T_1535 = eq(UInt<5>(0h1c), idx_11)
when _T_1535 :
node _T_1536 = shl(UInt<4>(0hb), 3)
node _T_1537 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1536)
node _T_1538 = bits(_T_1537, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_1538
node _T_1539 = eq(UInt<5>(0h1d), idx_11)
when _T_1539 :
node _T_1540 = shl(UInt<4>(0hb), 3)
node _T_1541 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1540)
node _T_1542 = bits(_T_1541, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_1542
node _T_1543 = eq(UInt<5>(0h1e), idx_11)
when _T_1543 :
node _T_1544 = shl(UInt<4>(0hb), 3)
node _T_1545 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1544)
node _T_1546 = bits(_T_1545, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_1546
node _T_1547 = eq(UInt<5>(0h1f), idx_11)
when _T_1547 :
node _T_1548 = shl(UInt<4>(0hb), 3)
node _T_1549 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1548)
node _T_1550 = bits(_T_1549, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_1550
node _idx_T_12 = add(write_start_index, UInt<4>(0hc))
node idx_12 = rem(_idx_T_12, UInt<6>(0h20))
node _T_1551 = eq(UInt<1>(0h0), idx_12)
when _T_1551 :
node _T_1552 = shl(UInt<4>(0hc), 3)
node _T_1553 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1552)
node _T_1554 = bits(_T_1553, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_1554
node _T_1555 = eq(UInt<1>(0h1), idx_12)
when _T_1555 :
node _T_1556 = shl(UInt<4>(0hc), 3)
node _T_1557 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1556)
node _T_1558 = bits(_T_1557, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_1558
node _T_1559 = eq(UInt<2>(0h2), idx_12)
when _T_1559 :
node _T_1560 = shl(UInt<4>(0hc), 3)
node _T_1561 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1560)
node _T_1562 = bits(_T_1561, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_1562
node _T_1563 = eq(UInt<2>(0h3), idx_12)
when _T_1563 :
node _T_1564 = shl(UInt<4>(0hc), 3)
node _T_1565 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1564)
node _T_1566 = bits(_T_1565, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_1566
node _T_1567 = eq(UInt<3>(0h4), idx_12)
when _T_1567 :
node _T_1568 = shl(UInt<4>(0hc), 3)
node _T_1569 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1568)
node _T_1570 = bits(_T_1569, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_1570
node _T_1571 = eq(UInt<3>(0h5), idx_12)
when _T_1571 :
node _T_1572 = shl(UInt<4>(0hc), 3)
node _T_1573 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1572)
node _T_1574 = bits(_T_1573, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_1574
node _T_1575 = eq(UInt<3>(0h6), idx_12)
when _T_1575 :
node _T_1576 = shl(UInt<4>(0hc), 3)
node _T_1577 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1576)
node _T_1578 = bits(_T_1577, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_1578
node _T_1579 = eq(UInt<3>(0h7), idx_12)
when _T_1579 :
node _T_1580 = shl(UInt<4>(0hc), 3)
node _T_1581 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1580)
node _T_1582 = bits(_T_1581, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_1582
node _T_1583 = eq(UInt<4>(0h8), idx_12)
when _T_1583 :
node _T_1584 = shl(UInt<4>(0hc), 3)
node _T_1585 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1584)
node _T_1586 = bits(_T_1585, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_1586
node _T_1587 = eq(UInt<4>(0h9), idx_12)
when _T_1587 :
node _T_1588 = shl(UInt<4>(0hc), 3)
node _T_1589 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1588)
node _T_1590 = bits(_T_1589, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_1590
node _T_1591 = eq(UInt<4>(0ha), idx_12)
when _T_1591 :
node _T_1592 = shl(UInt<4>(0hc), 3)
node _T_1593 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1592)
node _T_1594 = bits(_T_1593, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_1594
node _T_1595 = eq(UInt<4>(0hb), idx_12)
when _T_1595 :
node _T_1596 = shl(UInt<4>(0hc), 3)
node _T_1597 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1596)
node _T_1598 = bits(_T_1597, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_1598
node _T_1599 = eq(UInt<4>(0hc), idx_12)
when _T_1599 :
node _T_1600 = shl(UInt<4>(0hc), 3)
node _T_1601 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1600)
node _T_1602 = bits(_T_1601, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_1602
node _T_1603 = eq(UInt<4>(0hd), idx_12)
when _T_1603 :
node _T_1604 = shl(UInt<4>(0hc), 3)
node _T_1605 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1604)
node _T_1606 = bits(_T_1605, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_1606
node _T_1607 = eq(UInt<4>(0he), idx_12)
when _T_1607 :
node _T_1608 = shl(UInt<4>(0hc), 3)
node _T_1609 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1608)
node _T_1610 = bits(_T_1609, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_1610
node _T_1611 = eq(UInt<4>(0hf), idx_12)
when _T_1611 :
node _T_1612 = shl(UInt<4>(0hc), 3)
node _T_1613 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1612)
node _T_1614 = bits(_T_1613, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_1614
node _T_1615 = eq(UInt<5>(0h10), idx_12)
when _T_1615 :
node _T_1616 = shl(UInt<4>(0hc), 3)
node _T_1617 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1616)
node _T_1618 = bits(_T_1617, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_1618
node _T_1619 = eq(UInt<5>(0h11), idx_12)
when _T_1619 :
node _T_1620 = shl(UInt<4>(0hc), 3)
node _T_1621 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1620)
node _T_1622 = bits(_T_1621, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_1622
node _T_1623 = eq(UInt<5>(0h12), idx_12)
when _T_1623 :
node _T_1624 = shl(UInt<4>(0hc), 3)
node _T_1625 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1624)
node _T_1626 = bits(_T_1625, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_1626
node _T_1627 = eq(UInt<5>(0h13), idx_12)
when _T_1627 :
node _T_1628 = shl(UInt<4>(0hc), 3)
node _T_1629 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1628)
node _T_1630 = bits(_T_1629, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_1630
node _T_1631 = eq(UInt<5>(0h14), idx_12)
when _T_1631 :
node _T_1632 = shl(UInt<4>(0hc), 3)
node _T_1633 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1632)
node _T_1634 = bits(_T_1633, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_1634
node _T_1635 = eq(UInt<5>(0h15), idx_12)
when _T_1635 :
node _T_1636 = shl(UInt<4>(0hc), 3)
node _T_1637 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1636)
node _T_1638 = bits(_T_1637, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_1638
node _T_1639 = eq(UInt<5>(0h16), idx_12)
when _T_1639 :
node _T_1640 = shl(UInt<4>(0hc), 3)
node _T_1641 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1640)
node _T_1642 = bits(_T_1641, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_1642
node _T_1643 = eq(UInt<5>(0h17), idx_12)
when _T_1643 :
node _T_1644 = shl(UInt<4>(0hc), 3)
node _T_1645 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1644)
node _T_1646 = bits(_T_1645, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_1646
node _T_1647 = eq(UInt<5>(0h18), idx_12)
when _T_1647 :
node _T_1648 = shl(UInt<4>(0hc), 3)
node _T_1649 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1648)
node _T_1650 = bits(_T_1649, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_1650
node _T_1651 = eq(UInt<5>(0h19), idx_12)
when _T_1651 :
node _T_1652 = shl(UInt<4>(0hc), 3)
node _T_1653 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1652)
node _T_1654 = bits(_T_1653, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_1654
node _T_1655 = eq(UInt<5>(0h1a), idx_12)
when _T_1655 :
node _T_1656 = shl(UInt<4>(0hc), 3)
node _T_1657 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1656)
node _T_1658 = bits(_T_1657, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_1658
node _T_1659 = eq(UInt<5>(0h1b), idx_12)
when _T_1659 :
node _T_1660 = shl(UInt<4>(0hc), 3)
node _T_1661 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1660)
node _T_1662 = bits(_T_1661, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_1662
node _T_1663 = eq(UInt<5>(0h1c), idx_12)
when _T_1663 :
node _T_1664 = shl(UInt<4>(0hc), 3)
node _T_1665 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1664)
node _T_1666 = bits(_T_1665, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_1666
node _T_1667 = eq(UInt<5>(0h1d), idx_12)
when _T_1667 :
node _T_1668 = shl(UInt<4>(0hc), 3)
node _T_1669 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1668)
node _T_1670 = bits(_T_1669, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_1670
node _T_1671 = eq(UInt<5>(0h1e), idx_12)
when _T_1671 :
node _T_1672 = shl(UInt<4>(0hc), 3)
node _T_1673 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1672)
node _T_1674 = bits(_T_1673, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_1674
node _T_1675 = eq(UInt<5>(0h1f), idx_12)
when _T_1675 :
node _T_1676 = shl(UInt<4>(0hc), 3)
node _T_1677 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1676)
node _T_1678 = bits(_T_1677, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_1678
node _idx_T_13 = add(write_start_index, UInt<4>(0hd))
node idx_13 = rem(_idx_T_13, UInt<6>(0h20))
node _T_1679 = eq(UInt<1>(0h0), idx_13)
when _T_1679 :
node _T_1680 = shl(UInt<4>(0hd), 3)
node _T_1681 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1680)
node _T_1682 = bits(_T_1681, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_1682
node _T_1683 = eq(UInt<1>(0h1), idx_13)
when _T_1683 :
node _T_1684 = shl(UInt<4>(0hd), 3)
node _T_1685 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1684)
node _T_1686 = bits(_T_1685, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_1686
node _T_1687 = eq(UInt<2>(0h2), idx_13)
when _T_1687 :
node _T_1688 = shl(UInt<4>(0hd), 3)
node _T_1689 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1688)
node _T_1690 = bits(_T_1689, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_1690
node _T_1691 = eq(UInt<2>(0h3), idx_13)
when _T_1691 :
node _T_1692 = shl(UInt<4>(0hd), 3)
node _T_1693 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1692)
node _T_1694 = bits(_T_1693, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_1694
node _T_1695 = eq(UInt<3>(0h4), idx_13)
when _T_1695 :
node _T_1696 = shl(UInt<4>(0hd), 3)
node _T_1697 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1696)
node _T_1698 = bits(_T_1697, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_1698
node _T_1699 = eq(UInt<3>(0h5), idx_13)
when _T_1699 :
node _T_1700 = shl(UInt<4>(0hd), 3)
node _T_1701 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1700)
node _T_1702 = bits(_T_1701, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_1702
node _T_1703 = eq(UInt<3>(0h6), idx_13)
when _T_1703 :
node _T_1704 = shl(UInt<4>(0hd), 3)
node _T_1705 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1704)
node _T_1706 = bits(_T_1705, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_1706
node _T_1707 = eq(UInt<3>(0h7), idx_13)
when _T_1707 :
node _T_1708 = shl(UInt<4>(0hd), 3)
node _T_1709 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1708)
node _T_1710 = bits(_T_1709, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_1710
node _T_1711 = eq(UInt<4>(0h8), idx_13)
when _T_1711 :
node _T_1712 = shl(UInt<4>(0hd), 3)
node _T_1713 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1712)
node _T_1714 = bits(_T_1713, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_1714
node _T_1715 = eq(UInt<4>(0h9), idx_13)
when _T_1715 :
node _T_1716 = shl(UInt<4>(0hd), 3)
node _T_1717 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1716)
node _T_1718 = bits(_T_1717, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_1718
node _T_1719 = eq(UInt<4>(0ha), idx_13)
when _T_1719 :
node _T_1720 = shl(UInt<4>(0hd), 3)
node _T_1721 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1720)
node _T_1722 = bits(_T_1721, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_1722
node _T_1723 = eq(UInt<4>(0hb), idx_13)
when _T_1723 :
node _T_1724 = shl(UInt<4>(0hd), 3)
node _T_1725 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1724)
node _T_1726 = bits(_T_1725, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_1726
node _T_1727 = eq(UInt<4>(0hc), idx_13)
when _T_1727 :
node _T_1728 = shl(UInt<4>(0hd), 3)
node _T_1729 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1728)
node _T_1730 = bits(_T_1729, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_1730
node _T_1731 = eq(UInt<4>(0hd), idx_13)
when _T_1731 :
node _T_1732 = shl(UInt<4>(0hd), 3)
node _T_1733 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1732)
node _T_1734 = bits(_T_1733, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_1734
node _T_1735 = eq(UInt<4>(0he), idx_13)
when _T_1735 :
node _T_1736 = shl(UInt<4>(0hd), 3)
node _T_1737 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1736)
node _T_1738 = bits(_T_1737, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_1738
node _T_1739 = eq(UInt<4>(0hf), idx_13)
when _T_1739 :
node _T_1740 = shl(UInt<4>(0hd), 3)
node _T_1741 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1740)
node _T_1742 = bits(_T_1741, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_1742
node _T_1743 = eq(UInt<5>(0h10), idx_13)
when _T_1743 :
node _T_1744 = shl(UInt<4>(0hd), 3)
node _T_1745 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1744)
node _T_1746 = bits(_T_1745, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_1746
node _T_1747 = eq(UInt<5>(0h11), idx_13)
when _T_1747 :
node _T_1748 = shl(UInt<4>(0hd), 3)
node _T_1749 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1748)
node _T_1750 = bits(_T_1749, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_1750
node _T_1751 = eq(UInt<5>(0h12), idx_13)
when _T_1751 :
node _T_1752 = shl(UInt<4>(0hd), 3)
node _T_1753 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1752)
node _T_1754 = bits(_T_1753, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_1754
node _T_1755 = eq(UInt<5>(0h13), idx_13)
when _T_1755 :
node _T_1756 = shl(UInt<4>(0hd), 3)
node _T_1757 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1756)
node _T_1758 = bits(_T_1757, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_1758
node _T_1759 = eq(UInt<5>(0h14), idx_13)
when _T_1759 :
node _T_1760 = shl(UInt<4>(0hd), 3)
node _T_1761 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1760)
node _T_1762 = bits(_T_1761, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_1762
node _T_1763 = eq(UInt<5>(0h15), idx_13)
when _T_1763 :
node _T_1764 = shl(UInt<4>(0hd), 3)
node _T_1765 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1764)
node _T_1766 = bits(_T_1765, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_1766
node _T_1767 = eq(UInt<5>(0h16), idx_13)
when _T_1767 :
node _T_1768 = shl(UInt<4>(0hd), 3)
node _T_1769 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1768)
node _T_1770 = bits(_T_1769, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_1770
node _T_1771 = eq(UInt<5>(0h17), idx_13)
when _T_1771 :
node _T_1772 = shl(UInt<4>(0hd), 3)
node _T_1773 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1772)
node _T_1774 = bits(_T_1773, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_1774
node _T_1775 = eq(UInt<5>(0h18), idx_13)
when _T_1775 :
node _T_1776 = shl(UInt<4>(0hd), 3)
node _T_1777 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1776)
node _T_1778 = bits(_T_1777, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_1778
node _T_1779 = eq(UInt<5>(0h19), idx_13)
when _T_1779 :
node _T_1780 = shl(UInt<4>(0hd), 3)
node _T_1781 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1780)
node _T_1782 = bits(_T_1781, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_1782
node _T_1783 = eq(UInt<5>(0h1a), idx_13)
when _T_1783 :
node _T_1784 = shl(UInt<4>(0hd), 3)
node _T_1785 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1784)
node _T_1786 = bits(_T_1785, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_1786
node _T_1787 = eq(UInt<5>(0h1b), idx_13)
when _T_1787 :
node _T_1788 = shl(UInt<4>(0hd), 3)
node _T_1789 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1788)
node _T_1790 = bits(_T_1789, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_1790
node _T_1791 = eq(UInt<5>(0h1c), idx_13)
when _T_1791 :
node _T_1792 = shl(UInt<4>(0hd), 3)
node _T_1793 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1792)
node _T_1794 = bits(_T_1793, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_1794
node _T_1795 = eq(UInt<5>(0h1d), idx_13)
when _T_1795 :
node _T_1796 = shl(UInt<4>(0hd), 3)
node _T_1797 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1796)
node _T_1798 = bits(_T_1797, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_1798
node _T_1799 = eq(UInt<5>(0h1e), idx_13)
when _T_1799 :
node _T_1800 = shl(UInt<4>(0hd), 3)
node _T_1801 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1800)
node _T_1802 = bits(_T_1801, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_1802
node _T_1803 = eq(UInt<5>(0h1f), idx_13)
when _T_1803 :
node _T_1804 = shl(UInt<4>(0hd), 3)
node _T_1805 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1804)
node _T_1806 = bits(_T_1805, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_1806
node _idx_T_14 = add(write_start_index, UInt<4>(0he))
node idx_14 = rem(_idx_T_14, UInt<6>(0h20))
node _T_1807 = eq(UInt<1>(0h0), idx_14)
when _T_1807 :
node _T_1808 = shl(UInt<4>(0he), 3)
node _T_1809 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1808)
node _T_1810 = bits(_T_1809, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_1810
node _T_1811 = eq(UInt<1>(0h1), idx_14)
when _T_1811 :
node _T_1812 = shl(UInt<4>(0he), 3)
node _T_1813 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1812)
node _T_1814 = bits(_T_1813, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_1814
node _T_1815 = eq(UInt<2>(0h2), idx_14)
when _T_1815 :
node _T_1816 = shl(UInt<4>(0he), 3)
node _T_1817 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1816)
node _T_1818 = bits(_T_1817, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_1818
node _T_1819 = eq(UInt<2>(0h3), idx_14)
when _T_1819 :
node _T_1820 = shl(UInt<4>(0he), 3)
node _T_1821 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1820)
node _T_1822 = bits(_T_1821, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_1822
node _T_1823 = eq(UInt<3>(0h4), idx_14)
when _T_1823 :
node _T_1824 = shl(UInt<4>(0he), 3)
node _T_1825 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1824)
node _T_1826 = bits(_T_1825, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_1826
node _T_1827 = eq(UInt<3>(0h5), idx_14)
when _T_1827 :
node _T_1828 = shl(UInt<4>(0he), 3)
node _T_1829 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1828)
node _T_1830 = bits(_T_1829, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_1830
node _T_1831 = eq(UInt<3>(0h6), idx_14)
when _T_1831 :
node _T_1832 = shl(UInt<4>(0he), 3)
node _T_1833 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1832)
node _T_1834 = bits(_T_1833, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_1834
node _T_1835 = eq(UInt<3>(0h7), idx_14)
when _T_1835 :
node _T_1836 = shl(UInt<4>(0he), 3)
node _T_1837 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1836)
node _T_1838 = bits(_T_1837, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_1838
node _T_1839 = eq(UInt<4>(0h8), idx_14)
when _T_1839 :
node _T_1840 = shl(UInt<4>(0he), 3)
node _T_1841 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1840)
node _T_1842 = bits(_T_1841, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_1842
node _T_1843 = eq(UInt<4>(0h9), idx_14)
when _T_1843 :
node _T_1844 = shl(UInt<4>(0he), 3)
node _T_1845 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1844)
node _T_1846 = bits(_T_1845, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_1846
node _T_1847 = eq(UInt<4>(0ha), idx_14)
when _T_1847 :
node _T_1848 = shl(UInt<4>(0he), 3)
node _T_1849 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1848)
node _T_1850 = bits(_T_1849, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_1850
node _T_1851 = eq(UInt<4>(0hb), idx_14)
when _T_1851 :
node _T_1852 = shl(UInt<4>(0he), 3)
node _T_1853 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1852)
node _T_1854 = bits(_T_1853, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_1854
node _T_1855 = eq(UInt<4>(0hc), idx_14)
when _T_1855 :
node _T_1856 = shl(UInt<4>(0he), 3)
node _T_1857 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1856)
node _T_1858 = bits(_T_1857, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_1858
node _T_1859 = eq(UInt<4>(0hd), idx_14)
when _T_1859 :
node _T_1860 = shl(UInt<4>(0he), 3)
node _T_1861 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1860)
node _T_1862 = bits(_T_1861, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_1862
node _T_1863 = eq(UInt<4>(0he), idx_14)
when _T_1863 :
node _T_1864 = shl(UInt<4>(0he), 3)
node _T_1865 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1864)
node _T_1866 = bits(_T_1865, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_1866
node _T_1867 = eq(UInt<4>(0hf), idx_14)
when _T_1867 :
node _T_1868 = shl(UInt<4>(0he), 3)
node _T_1869 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1868)
node _T_1870 = bits(_T_1869, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_1870
node _T_1871 = eq(UInt<5>(0h10), idx_14)
when _T_1871 :
node _T_1872 = shl(UInt<4>(0he), 3)
node _T_1873 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1872)
node _T_1874 = bits(_T_1873, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_1874
node _T_1875 = eq(UInt<5>(0h11), idx_14)
when _T_1875 :
node _T_1876 = shl(UInt<4>(0he), 3)
node _T_1877 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1876)
node _T_1878 = bits(_T_1877, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_1878
node _T_1879 = eq(UInt<5>(0h12), idx_14)
when _T_1879 :
node _T_1880 = shl(UInt<4>(0he), 3)
node _T_1881 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1880)
node _T_1882 = bits(_T_1881, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_1882
node _T_1883 = eq(UInt<5>(0h13), idx_14)
when _T_1883 :
node _T_1884 = shl(UInt<4>(0he), 3)
node _T_1885 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1884)
node _T_1886 = bits(_T_1885, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_1886
node _T_1887 = eq(UInt<5>(0h14), idx_14)
when _T_1887 :
node _T_1888 = shl(UInt<4>(0he), 3)
node _T_1889 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1888)
node _T_1890 = bits(_T_1889, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_1890
node _T_1891 = eq(UInt<5>(0h15), idx_14)
when _T_1891 :
node _T_1892 = shl(UInt<4>(0he), 3)
node _T_1893 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1892)
node _T_1894 = bits(_T_1893, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_1894
node _T_1895 = eq(UInt<5>(0h16), idx_14)
when _T_1895 :
node _T_1896 = shl(UInt<4>(0he), 3)
node _T_1897 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1896)
node _T_1898 = bits(_T_1897, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_1898
node _T_1899 = eq(UInt<5>(0h17), idx_14)
when _T_1899 :
node _T_1900 = shl(UInt<4>(0he), 3)
node _T_1901 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1900)
node _T_1902 = bits(_T_1901, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_1902
node _T_1903 = eq(UInt<5>(0h18), idx_14)
when _T_1903 :
node _T_1904 = shl(UInt<4>(0he), 3)
node _T_1905 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1904)
node _T_1906 = bits(_T_1905, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_1906
node _T_1907 = eq(UInt<5>(0h19), idx_14)
when _T_1907 :
node _T_1908 = shl(UInt<4>(0he), 3)
node _T_1909 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1908)
node _T_1910 = bits(_T_1909, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_1910
node _T_1911 = eq(UInt<5>(0h1a), idx_14)
when _T_1911 :
node _T_1912 = shl(UInt<4>(0he), 3)
node _T_1913 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1912)
node _T_1914 = bits(_T_1913, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_1914
node _T_1915 = eq(UInt<5>(0h1b), idx_14)
when _T_1915 :
node _T_1916 = shl(UInt<4>(0he), 3)
node _T_1917 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1916)
node _T_1918 = bits(_T_1917, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_1918
node _T_1919 = eq(UInt<5>(0h1c), idx_14)
when _T_1919 :
node _T_1920 = shl(UInt<4>(0he), 3)
node _T_1921 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1920)
node _T_1922 = bits(_T_1921, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_1922
node _T_1923 = eq(UInt<5>(0h1d), idx_14)
when _T_1923 :
node _T_1924 = shl(UInt<4>(0he), 3)
node _T_1925 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1924)
node _T_1926 = bits(_T_1925, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_1926
node _T_1927 = eq(UInt<5>(0h1e), idx_14)
when _T_1927 :
node _T_1928 = shl(UInt<4>(0he), 3)
node _T_1929 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1928)
node _T_1930 = bits(_T_1929, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_1930
node _T_1931 = eq(UInt<5>(0h1f), idx_14)
when _T_1931 :
node _T_1932 = shl(UInt<4>(0he), 3)
node _T_1933 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1932)
node _T_1934 = bits(_T_1933, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_1934
node _idx_T_15 = add(write_start_index, UInt<4>(0hf))
node idx_15 = rem(_idx_T_15, UInt<6>(0h20))
node _T_1935 = eq(UInt<1>(0h0), idx_15)
when _T_1935 :
node _T_1936 = shl(UInt<4>(0hf), 3)
node _T_1937 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1936)
node _T_1938 = bits(_T_1937, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_1938
node _T_1939 = eq(UInt<1>(0h1), idx_15)
when _T_1939 :
node _T_1940 = shl(UInt<4>(0hf), 3)
node _T_1941 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1940)
node _T_1942 = bits(_T_1941, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_1942
node _T_1943 = eq(UInt<2>(0h2), idx_15)
when _T_1943 :
node _T_1944 = shl(UInt<4>(0hf), 3)
node _T_1945 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1944)
node _T_1946 = bits(_T_1945, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_1946
node _T_1947 = eq(UInt<2>(0h3), idx_15)
when _T_1947 :
node _T_1948 = shl(UInt<4>(0hf), 3)
node _T_1949 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1948)
node _T_1950 = bits(_T_1949, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_1950
node _T_1951 = eq(UInt<3>(0h4), idx_15)
when _T_1951 :
node _T_1952 = shl(UInt<4>(0hf), 3)
node _T_1953 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1952)
node _T_1954 = bits(_T_1953, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_1954
node _T_1955 = eq(UInt<3>(0h5), idx_15)
when _T_1955 :
node _T_1956 = shl(UInt<4>(0hf), 3)
node _T_1957 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1956)
node _T_1958 = bits(_T_1957, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_1958
node _T_1959 = eq(UInt<3>(0h6), idx_15)
when _T_1959 :
node _T_1960 = shl(UInt<4>(0hf), 3)
node _T_1961 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1960)
node _T_1962 = bits(_T_1961, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_1962
node _T_1963 = eq(UInt<3>(0h7), idx_15)
when _T_1963 :
node _T_1964 = shl(UInt<4>(0hf), 3)
node _T_1965 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1964)
node _T_1966 = bits(_T_1965, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_1966
node _T_1967 = eq(UInt<4>(0h8), idx_15)
when _T_1967 :
node _T_1968 = shl(UInt<4>(0hf), 3)
node _T_1969 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1968)
node _T_1970 = bits(_T_1969, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_1970
node _T_1971 = eq(UInt<4>(0h9), idx_15)
when _T_1971 :
node _T_1972 = shl(UInt<4>(0hf), 3)
node _T_1973 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1972)
node _T_1974 = bits(_T_1973, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_1974
node _T_1975 = eq(UInt<4>(0ha), idx_15)
when _T_1975 :
node _T_1976 = shl(UInt<4>(0hf), 3)
node _T_1977 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1976)
node _T_1978 = bits(_T_1977, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_1978
node _T_1979 = eq(UInt<4>(0hb), idx_15)
when _T_1979 :
node _T_1980 = shl(UInt<4>(0hf), 3)
node _T_1981 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1980)
node _T_1982 = bits(_T_1981, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_1982
node _T_1983 = eq(UInt<4>(0hc), idx_15)
when _T_1983 :
node _T_1984 = shl(UInt<4>(0hf), 3)
node _T_1985 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1984)
node _T_1986 = bits(_T_1985, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_1986
node _T_1987 = eq(UInt<4>(0hd), idx_15)
when _T_1987 :
node _T_1988 = shl(UInt<4>(0hf), 3)
node _T_1989 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1988)
node _T_1990 = bits(_T_1989, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_1990
node _T_1991 = eq(UInt<4>(0he), idx_15)
when _T_1991 :
node _T_1992 = shl(UInt<4>(0hf), 3)
node _T_1993 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1992)
node _T_1994 = bits(_T_1993, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_1994
node _T_1995 = eq(UInt<4>(0hf), idx_15)
when _T_1995 :
node _T_1996 = shl(UInt<4>(0hf), 3)
node _T_1997 = dshr(incoming_writes_Q.io.deq.bits.data, _T_1996)
node _T_1998 = bits(_T_1997, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_1998
node _T_1999 = eq(UInt<5>(0h10), idx_15)
when _T_1999 :
node _T_2000 = shl(UInt<4>(0hf), 3)
node _T_2001 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2000)
node _T_2002 = bits(_T_2001, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_2002
node _T_2003 = eq(UInt<5>(0h11), idx_15)
when _T_2003 :
node _T_2004 = shl(UInt<4>(0hf), 3)
node _T_2005 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2004)
node _T_2006 = bits(_T_2005, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_2006
node _T_2007 = eq(UInt<5>(0h12), idx_15)
when _T_2007 :
node _T_2008 = shl(UInt<4>(0hf), 3)
node _T_2009 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2008)
node _T_2010 = bits(_T_2009, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_2010
node _T_2011 = eq(UInt<5>(0h13), idx_15)
when _T_2011 :
node _T_2012 = shl(UInt<4>(0hf), 3)
node _T_2013 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2012)
node _T_2014 = bits(_T_2013, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_2014
node _T_2015 = eq(UInt<5>(0h14), idx_15)
when _T_2015 :
node _T_2016 = shl(UInt<4>(0hf), 3)
node _T_2017 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2016)
node _T_2018 = bits(_T_2017, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_2018
node _T_2019 = eq(UInt<5>(0h15), idx_15)
when _T_2019 :
node _T_2020 = shl(UInt<4>(0hf), 3)
node _T_2021 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2020)
node _T_2022 = bits(_T_2021, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_2022
node _T_2023 = eq(UInt<5>(0h16), idx_15)
when _T_2023 :
node _T_2024 = shl(UInt<4>(0hf), 3)
node _T_2025 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2024)
node _T_2026 = bits(_T_2025, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_2026
node _T_2027 = eq(UInt<5>(0h17), idx_15)
when _T_2027 :
node _T_2028 = shl(UInt<4>(0hf), 3)
node _T_2029 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2028)
node _T_2030 = bits(_T_2029, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_2030
node _T_2031 = eq(UInt<5>(0h18), idx_15)
when _T_2031 :
node _T_2032 = shl(UInt<4>(0hf), 3)
node _T_2033 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2032)
node _T_2034 = bits(_T_2033, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_2034
node _T_2035 = eq(UInt<5>(0h19), idx_15)
when _T_2035 :
node _T_2036 = shl(UInt<4>(0hf), 3)
node _T_2037 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2036)
node _T_2038 = bits(_T_2037, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_2038
node _T_2039 = eq(UInt<5>(0h1a), idx_15)
when _T_2039 :
node _T_2040 = shl(UInt<4>(0hf), 3)
node _T_2041 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2040)
node _T_2042 = bits(_T_2041, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_2042
node _T_2043 = eq(UInt<5>(0h1b), idx_15)
when _T_2043 :
node _T_2044 = shl(UInt<4>(0hf), 3)
node _T_2045 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2044)
node _T_2046 = bits(_T_2045, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_2046
node _T_2047 = eq(UInt<5>(0h1c), idx_15)
when _T_2047 :
node _T_2048 = shl(UInt<4>(0hf), 3)
node _T_2049 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2048)
node _T_2050 = bits(_T_2049, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_2050
node _T_2051 = eq(UInt<5>(0h1d), idx_15)
when _T_2051 :
node _T_2052 = shl(UInt<4>(0hf), 3)
node _T_2053 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2052)
node _T_2054 = bits(_T_2053, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_2054
node _T_2055 = eq(UInt<5>(0h1e), idx_15)
when _T_2055 :
node _T_2056 = shl(UInt<4>(0hf), 3)
node _T_2057 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2056)
node _T_2058 = bits(_T_2057, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_2058
node _T_2059 = eq(UInt<5>(0h1f), idx_15)
when _T_2059 :
node _T_2060 = shl(UInt<4>(0hf), 3)
node _T_2061 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2060)
node _T_2062 = bits(_T_2061, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_2062
node _idx_T_16 = add(write_start_index, UInt<5>(0h10))
node idx_16 = rem(_idx_T_16, UInt<6>(0h20))
node _T_2063 = eq(UInt<1>(0h0), idx_16)
when _T_2063 :
node _T_2064 = shl(UInt<5>(0h10), 3)
node _T_2065 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2064)
node _T_2066 = bits(_T_2065, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_2066
node _T_2067 = eq(UInt<1>(0h1), idx_16)
when _T_2067 :
node _T_2068 = shl(UInt<5>(0h10), 3)
node _T_2069 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2068)
node _T_2070 = bits(_T_2069, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_2070
node _T_2071 = eq(UInt<2>(0h2), idx_16)
when _T_2071 :
node _T_2072 = shl(UInt<5>(0h10), 3)
node _T_2073 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2072)
node _T_2074 = bits(_T_2073, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_2074
node _T_2075 = eq(UInt<2>(0h3), idx_16)
when _T_2075 :
node _T_2076 = shl(UInt<5>(0h10), 3)
node _T_2077 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2076)
node _T_2078 = bits(_T_2077, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_2078
node _T_2079 = eq(UInt<3>(0h4), idx_16)
when _T_2079 :
node _T_2080 = shl(UInt<5>(0h10), 3)
node _T_2081 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2080)
node _T_2082 = bits(_T_2081, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_2082
node _T_2083 = eq(UInt<3>(0h5), idx_16)
when _T_2083 :
node _T_2084 = shl(UInt<5>(0h10), 3)
node _T_2085 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2084)
node _T_2086 = bits(_T_2085, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_2086
node _T_2087 = eq(UInt<3>(0h6), idx_16)
when _T_2087 :
node _T_2088 = shl(UInt<5>(0h10), 3)
node _T_2089 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2088)
node _T_2090 = bits(_T_2089, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_2090
node _T_2091 = eq(UInt<3>(0h7), idx_16)
when _T_2091 :
node _T_2092 = shl(UInt<5>(0h10), 3)
node _T_2093 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2092)
node _T_2094 = bits(_T_2093, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_2094
node _T_2095 = eq(UInt<4>(0h8), idx_16)
when _T_2095 :
node _T_2096 = shl(UInt<5>(0h10), 3)
node _T_2097 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2096)
node _T_2098 = bits(_T_2097, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_2098
node _T_2099 = eq(UInt<4>(0h9), idx_16)
when _T_2099 :
node _T_2100 = shl(UInt<5>(0h10), 3)
node _T_2101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2100)
node _T_2102 = bits(_T_2101, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_2102
node _T_2103 = eq(UInt<4>(0ha), idx_16)
when _T_2103 :
node _T_2104 = shl(UInt<5>(0h10), 3)
node _T_2105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2104)
node _T_2106 = bits(_T_2105, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_2106
node _T_2107 = eq(UInt<4>(0hb), idx_16)
when _T_2107 :
node _T_2108 = shl(UInt<5>(0h10), 3)
node _T_2109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2108)
node _T_2110 = bits(_T_2109, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_2110
node _T_2111 = eq(UInt<4>(0hc), idx_16)
when _T_2111 :
node _T_2112 = shl(UInt<5>(0h10), 3)
node _T_2113 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2112)
node _T_2114 = bits(_T_2113, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_2114
node _T_2115 = eq(UInt<4>(0hd), idx_16)
when _T_2115 :
node _T_2116 = shl(UInt<5>(0h10), 3)
node _T_2117 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2116)
node _T_2118 = bits(_T_2117, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_2118
node _T_2119 = eq(UInt<4>(0he), idx_16)
when _T_2119 :
node _T_2120 = shl(UInt<5>(0h10), 3)
node _T_2121 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2120)
node _T_2122 = bits(_T_2121, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_2122
node _T_2123 = eq(UInt<4>(0hf), idx_16)
when _T_2123 :
node _T_2124 = shl(UInt<5>(0h10), 3)
node _T_2125 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2124)
node _T_2126 = bits(_T_2125, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_2126
node _T_2127 = eq(UInt<5>(0h10), idx_16)
when _T_2127 :
node _T_2128 = shl(UInt<5>(0h10), 3)
node _T_2129 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2128)
node _T_2130 = bits(_T_2129, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_2130
node _T_2131 = eq(UInt<5>(0h11), idx_16)
when _T_2131 :
node _T_2132 = shl(UInt<5>(0h10), 3)
node _T_2133 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2132)
node _T_2134 = bits(_T_2133, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_2134
node _T_2135 = eq(UInt<5>(0h12), idx_16)
when _T_2135 :
node _T_2136 = shl(UInt<5>(0h10), 3)
node _T_2137 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2136)
node _T_2138 = bits(_T_2137, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_2138
node _T_2139 = eq(UInt<5>(0h13), idx_16)
when _T_2139 :
node _T_2140 = shl(UInt<5>(0h10), 3)
node _T_2141 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2140)
node _T_2142 = bits(_T_2141, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_2142
node _T_2143 = eq(UInt<5>(0h14), idx_16)
when _T_2143 :
node _T_2144 = shl(UInt<5>(0h10), 3)
node _T_2145 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2144)
node _T_2146 = bits(_T_2145, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_2146
node _T_2147 = eq(UInt<5>(0h15), idx_16)
when _T_2147 :
node _T_2148 = shl(UInt<5>(0h10), 3)
node _T_2149 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2148)
node _T_2150 = bits(_T_2149, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_2150
node _T_2151 = eq(UInt<5>(0h16), idx_16)
when _T_2151 :
node _T_2152 = shl(UInt<5>(0h10), 3)
node _T_2153 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2152)
node _T_2154 = bits(_T_2153, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_2154
node _T_2155 = eq(UInt<5>(0h17), idx_16)
when _T_2155 :
node _T_2156 = shl(UInt<5>(0h10), 3)
node _T_2157 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2156)
node _T_2158 = bits(_T_2157, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_2158
node _T_2159 = eq(UInt<5>(0h18), idx_16)
when _T_2159 :
node _T_2160 = shl(UInt<5>(0h10), 3)
node _T_2161 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2160)
node _T_2162 = bits(_T_2161, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_2162
node _T_2163 = eq(UInt<5>(0h19), idx_16)
when _T_2163 :
node _T_2164 = shl(UInt<5>(0h10), 3)
node _T_2165 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2164)
node _T_2166 = bits(_T_2165, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_2166
node _T_2167 = eq(UInt<5>(0h1a), idx_16)
when _T_2167 :
node _T_2168 = shl(UInt<5>(0h10), 3)
node _T_2169 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2168)
node _T_2170 = bits(_T_2169, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_2170
node _T_2171 = eq(UInt<5>(0h1b), idx_16)
when _T_2171 :
node _T_2172 = shl(UInt<5>(0h10), 3)
node _T_2173 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2172)
node _T_2174 = bits(_T_2173, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_2174
node _T_2175 = eq(UInt<5>(0h1c), idx_16)
when _T_2175 :
node _T_2176 = shl(UInt<5>(0h10), 3)
node _T_2177 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2176)
node _T_2178 = bits(_T_2177, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_2178
node _T_2179 = eq(UInt<5>(0h1d), idx_16)
when _T_2179 :
node _T_2180 = shl(UInt<5>(0h10), 3)
node _T_2181 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2180)
node _T_2182 = bits(_T_2181, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_2182
node _T_2183 = eq(UInt<5>(0h1e), idx_16)
when _T_2183 :
node _T_2184 = shl(UInt<5>(0h10), 3)
node _T_2185 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2184)
node _T_2186 = bits(_T_2185, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_2186
node _T_2187 = eq(UInt<5>(0h1f), idx_16)
when _T_2187 :
node _T_2188 = shl(UInt<5>(0h10), 3)
node _T_2189 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2188)
node _T_2190 = bits(_T_2189, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_2190
node _idx_T_17 = add(write_start_index, UInt<5>(0h11))
node idx_17 = rem(_idx_T_17, UInt<6>(0h20))
node _T_2191 = eq(UInt<1>(0h0), idx_17)
when _T_2191 :
node _T_2192 = shl(UInt<5>(0h11), 3)
node _T_2193 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2192)
node _T_2194 = bits(_T_2193, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_2194
node _T_2195 = eq(UInt<1>(0h1), idx_17)
when _T_2195 :
node _T_2196 = shl(UInt<5>(0h11), 3)
node _T_2197 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2196)
node _T_2198 = bits(_T_2197, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_2198
node _T_2199 = eq(UInt<2>(0h2), idx_17)
when _T_2199 :
node _T_2200 = shl(UInt<5>(0h11), 3)
node _T_2201 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2200)
node _T_2202 = bits(_T_2201, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_2202
node _T_2203 = eq(UInt<2>(0h3), idx_17)
when _T_2203 :
node _T_2204 = shl(UInt<5>(0h11), 3)
node _T_2205 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2204)
node _T_2206 = bits(_T_2205, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_2206
node _T_2207 = eq(UInt<3>(0h4), idx_17)
when _T_2207 :
node _T_2208 = shl(UInt<5>(0h11), 3)
node _T_2209 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2208)
node _T_2210 = bits(_T_2209, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_2210
node _T_2211 = eq(UInt<3>(0h5), idx_17)
when _T_2211 :
node _T_2212 = shl(UInt<5>(0h11), 3)
node _T_2213 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2212)
node _T_2214 = bits(_T_2213, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_2214
node _T_2215 = eq(UInt<3>(0h6), idx_17)
when _T_2215 :
node _T_2216 = shl(UInt<5>(0h11), 3)
node _T_2217 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2216)
node _T_2218 = bits(_T_2217, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_2218
node _T_2219 = eq(UInt<3>(0h7), idx_17)
when _T_2219 :
node _T_2220 = shl(UInt<5>(0h11), 3)
node _T_2221 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2220)
node _T_2222 = bits(_T_2221, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_2222
node _T_2223 = eq(UInt<4>(0h8), idx_17)
when _T_2223 :
node _T_2224 = shl(UInt<5>(0h11), 3)
node _T_2225 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2224)
node _T_2226 = bits(_T_2225, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_2226
node _T_2227 = eq(UInt<4>(0h9), idx_17)
when _T_2227 :
node _T_2228 = shl(UInt<5>(0h11), 3)
node _T_2229 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2228)
node _T_2230 = bits(_T_2229, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_2230
node _T_2231 = eq(UInt<4>(0ha), idx_17)
when _T_2231 :
node _T_2232 = shl(UInt<5>(0h11), 3)
node _T_2233 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2232)
node _T_2234 = bits(_T_2233, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_2234
node _T_2235 = eq(UInt<4>(0hb), idx_17)
when _T_2235 :
node _T_2236 = shl(UInt<5>(0h11), 3)
node _T_2237 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2236)
node _T_2238 = bits(_T_2237, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_2238
node _T_2239 = eq(UInt<4>(0hc), idx_17)
when _T_2239 :
node _T_2240 = shl(UInt<5>(0h11), 3)
node _T_2241 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2240)
node _T_2242 = bits(_T_2241, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_2242
node _T_2243 = eq(UInt<4>(0hd), idx_17)
when _T_2243 :
node _T_2244 = shl(UInt<5>(0h11), 3)
node _T_2245 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2244)
node _T_2246 = bits(_T_2245, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_2246
node _T_2247 = eq(UInt<4>(0he), idx_17)
when _T_2247 :
node _T_2248 = shl(UInt<5>(0h11), 3)
node _T_2249 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2248)
node _T_2250 = bits(_T_2249, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_2250
node _T_2251 = eq(UInt<4>(0hf), idx_17)
when _T_2251 :
node _T_2252 = shl(UInt<5>(0h11), 3)
node _T_2253 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2252)
node _T_2254 = bits(_T_2253, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_2254
node _T_2255 = eq(UInt<5>(0h10), idx_17)
when _T_2255 :
node _T_2256 = shl(UInt<5>(0h11), 3)
node _T_2257 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2256)
node _T_2258 = bits(_T_2257, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_2258
node _T_2259 = eq(UInt<5>(0h11), idx_17)
when _T_2259 :
node _T_2260 = shl(UInt<5>(0h11), 3)
node _T_2261 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2260)
node _T_2262 = bits(_T_2261, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_2262
node _T_2263 = eq(UInt<5>(0h12), idx_17)
when _T_2263 :
node _T_2264 = shl(UInt<5>(0h11), 3)
node _T_2265 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2264)
node _T_2266 = bits(_T_2265, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_2266
node _T_2267 = eq(UInt<5>(0h13), idx_17)
when _T_2267 :
node _T_2268 = shl(UInt<5>(0h11), 3)
node _T_2269 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2268)
node _T_2270 = bits(_T_2269, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_2270
node _T_2271 = eq(UInt<5>(0h14), idx_17)
when _T_2271 :
node _T_2272 = shl(UInt<5>(0h11), 3)
node _T_2273 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2272)
node _T_2274 = bits(_T_2273, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_2274
node _T_2275 = eq(UInt<5>(0h15), idx_17)
when _T_2275 :
node _T_2276 = shl(UInt<5>(0h11), 3)
node _T_2277 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2276)
node _T_2278 = bits(_T_2277, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_2278
node _T_2279 = eq(UInt<5>(0h16), idx_17)
when _T_2279 :
node _T_2280 = shl(UInt<5>(0h11), 3)
node _T_2281 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2280)
node _T_2282 = bits(_T_2281, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_2282
node _T_2283 = eq(UInt<5>(0h17), idx_17)
when _T_2283 :
node _T_2284 = shl(UInt<5>(0h11), 3)
node _T_2285 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2284)
node _T_2286 = bits(_T_2285, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_2286
node _T_2287 = eq(UInt<5>(0h18), idx_17)
when _T_2287 :
node _T_2288 = shl(UInt<5>(0h11), 3)
node _T_2289 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2288)
node _T_2290 = bits(_T_2289, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_2290
node _T_2291 = eq(UInt<5>(0h19), idx_17)
when _T_2291 :
node _T_2292 = shl(UInt<5>(0h11), 3)
node _T_2293 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2292)
node _T_2294 = bits(_T_2293, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_2294
node _T_2295 = eq(UInt<5>(0h1a), idx_17)
when _T_2295 :
node _T_2296 = shl(UInt<5>(0h11), 3)
node _T_2297 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2296)
node _T_2298 = bits(_T_2297, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_2298
node _T_2299 = eq(UInt<5>(0h1b), idx_17)
when _T_2299 :
node _T_2300 = shl(UInt<5>(0h11), 3)
node _T_2301 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2300)
node _T_2302 = bits(_T_2301, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_2302
node _T_2303 = eq(UInt<5>(0h1c), idx_17)
when _T_2303 :
node _T_2304 = shl(UInt<5>(0h11), 3)
node _T_2305 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2304)
node _T_2306 = bits(_T_2305, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_2306
node _T_2307 = eq(UInt<5>(0h1d), idx_17)
when _T_2307 :
node _T_2308 = shl(UInt<5>(0h11), 3)
node _T_2309 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2308)
node _T_2310 = bits(_T_2309, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_2310
node _T_2311 = eq(UInt<5>(0h1e), idx_17)
when _T_2311 :
node _T_2312 = shl(UInt<5>(0h11), 3)
node _T_2313 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2312)
node _T_2314 = bits(_T_2313, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_2314
node _T_2315 = eq(UInt<5>(0h1f), idx_17)
when _T_2315 :
node _T_2316 = shl(UInt<5>(0h11), 3)
node _T_2317 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2316)
node _T_2318 = bits(_T_2317, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_2318
node _idx_T_18 = add(write_start_index, UInt<5>(0h12))
node idx_18 = rem(_idx_T_18, UInt<6>(0h20))
node _T_2319 = eq(UInt<1>(0h0), idx_18)
when _T_2319 :
node _T_2320 = shl(UInt<5>(0h12), 3)
node _T_2321 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2320)
node _T_2322 = bits(_T_2321, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_2322
node _T_2323 = eq(UInt<1>(0h1), idx_18)
when _T_2323 :
node _T_2324 = shl(UInt<5>(0h12), 3)
node _T_2325 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2324)
node _T_2326 = bits(_T_2325, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_2326
node _T_2327 = eq(UInt<2>(0h2), idx_18)
when _T_2327 :
node _T_2328 = shl(UInt<5>(0h12), 3)
node _T_2329 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2328)
node _T_2330 = bits(_T_2329, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_2330
node _T_2331 = eq(UInt<2>(0h3), idx_18)
when _T_2331 :
node _T_2332 = shl(UInt<5>(0h12), 3)
node _T_2333 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2332)
node _T_2334 = bits(_T_2333, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_2334
node _T_2335 = eq(UInt<3>(0h4), idx_18)
when _T_2335 :
node _T_2336 = shl(UInt<5>(0h12), 3)
node _T_2337 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2336)
node _T_2338 = bits(_T_2337, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_2338
node _T_2339 = eq(UInt<3>(0h5), idx_18)
when _T_2339 :
node _T_2340 = shl(UInt<5>(0h12), 3)
node _T_2341 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2340)
node _T_2342 = bits(_T_2341, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_2342
node _T_2343 = eq(UInt<3>(0h6), idx_18)
when _T_2343 :
node _T_2344 = shl(UInt<5>(0h12), 3)
node _T_2345 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2344)
node _T_2346 = bits(_T_2345, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_2346
node _T_2347 = eq(UInt<3>(0h7), idx_18)
when _T_2347 :
node _T_2348 = shl(UInt<5>(0h12), 3)
node _T_2349 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2348)
node _T_2350 = bits(_T_2349, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_2350
node _T_2351 = eq(UInt<4>(0h8), idx_18)
when _T_2351 :
node _T_2352 = shl(UInt<5>(0h12), 3)
node _T_2353 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2352)
node _T_2354 = bits(_T_2353, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_2354
node _T_2355 = eq(UInt<4>(0h9), idx_18)
when _T_2355 :
node _T_2356 = shl(UInt<5>(0h12), 3)
node _T_2357 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2356)
node _T_2358 = bits(_T_2357, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_2358
node _T_2359 = eq(UInt<4>(0ha), idx_18)
when _T_2359 :
node _T_2360 = shl(UInt<5>(0h12), 3)
node _T_2361 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2360)
node _T_2362 = bits(_T_2361, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_2362
node _T_2363 = eq(UInt<4>(0hb), idx_18)
when _T_2363 :
node _T_2364 = shl(UInt<5>(0h12), 3)
node _T_2365 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2364)
node _T_2366 = bits(_T_2365, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_2366
node _T_2367 = eq(UInt<4>(0hc), idx_18)
when _T_2367 :
node _T_2368 = shl(UInt<5>(0h12), 3)
node _T_2369 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2368)
node _T_2370 = bits(_T_2369, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_2370
node _T_2371 = eq(UInt<4>(0hd), idx_18)
when _T_2371 :
node _T_2372 = shl(UInt<5>(0h12), 3)
node _T_2373 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2372)
node _T_2374 = bits(_T_2373, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_2374
node _T_2375 = eq(UInt<4>(0he), idx_18)
when _T_2375 :
node _T_2376 = shl(UInt<5>(0h12), 3)
node _T_2377 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2376)
node _T_2378 = bits(_T_2377, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_2378
node _T_2379 = eq(UInt<4>(0hf), idx_18)
when _T_2379 :
node _T_2380 = shl(UInt<5>(0h12), 3)
node _T_2381 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2380)
node _T_2382 = bits(_T_2381, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_2382
node _T_2383 = eq(UInt<5>(0h10), idx_18)
when _T_2383 :
node _T_2384 = shl(UInt<5>(0h12), 3)
node _T_2385 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2384)
node _T_2386 = bits(_T_2385, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_2386
node _T_2387 = eq(UInt<5>(0h11), idx_18)
when _T_2387 :
node _T_2388 = shl(UInt<5>(0h12), 3)
node _T_2389 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2388)
node _T_2390 = bits(_T_2389, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_2390
node _T_2391 = eq(UInt<5>(0h12), idx_18)
when _T_2391 :
node _T_2392 = shl(UInt<5>(0h12), 3)
node _T_2393 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2392)
node _T_2394 = bits(_T_2393, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_2394
node _T_2395 = eq(UInt<5>(0h13), idx_18)
when _T_2395 :
node _T_2396 = shl(UInt<5>(0h12), 3)
node _T_2397 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2396)
node _T_2398 = bits(_T_2397, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_2398
node _T_2399 = eq(UInt<5>(0h14), idx_18)
when _T_2399 :
node _T_2400 = shl(UInt<5>(0h12), 3)
node _T_2401 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2400)
node _T_2402 = bits(_T_2401, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_2402
node _T_2403 = eq(UInt<5>(0h15), idx_18)
when _T_2403 :
node _T_2404 = shl(UInt<5>(0h12), 3)
node _T_2405 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2404)
node _T_2406 = bits(_T_2405, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_2406
node _T_2407 = eq(UInt<5>(0h16), idx_18)
when _T_2407 :
node _T_2408 = shl(UInt<5>(0h12), 3)
node _T_2409 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2408)
node _T_2410 = bits(_T_2409, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_2410
node _T_2411 = eq(UInt<5>(0h17), idx_18)
when _T_2411 :
node _T_2412 = shl(UInt<5>(0h12), 3)
node _T_2413 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2412)
node _T_2414 = bits(_T_2413, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_2414
node _T_2415 = eq(UInt<5>(0h18), idx_18)
when _T_2415 :
node _T_2416 = shl(UInt<5>(0h12), 3)
node _T_2417 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2416)
node _T_2418 = bits(_T_2417, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_2418
node _T_2419 = eq(UInt<5>(0h19), idx_18)
when _T_2419 :
node _T_2420 = shl(UInt<5>(0h12), 3)
node _T_2421 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2420)
node _T_2422 = bits(_T_2421, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_2422
node _T_2423 = eq(UInt<5>(0h1a), idx_18)
when _T_2423 :
node _T_2424 = shl(UInt<5>(0h12), 3)
node _T_2425 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2424)
node _T_2426 = bits(_T_2425, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_2426
node _T_2427 = eq(UInt<5>(0h1b), idx_18)
when _T_2427 :
node _T_2428 = shl(UInt<5>(0h12), 3)
node _T_2429 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2428)
node _T_2430 = bits(_T_2429, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_2430
node _T_2431 = eq(UInt<5>(0h1c), idx_18)
when _T_2431 :
node _T_2432 = shl(UInt<5>(0h12), 3)
node _T_2433 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2432)
node _T_2434 = bits(_T_2433, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_2434
node _T_2435 = eq(UInt<5>(0h1d), idx_18)
when _T_2435 :
node _T_2436 = shl(UInt<5>(0h12), 3)
node _T_2437 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2436)
node _T_2438 = bits(_T_2437, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_2438
node _T_2439 = eq(UInt<5>(0h1e), idx_18)
when _T_2439 :
node _T_2440 = shl(UInt<5>(0h12), 3)
node _T_2441 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2440)
node _T_2442 = bits(_T_2441, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_2442
node _T_2443 = eq(UInt<5>(0h1f), idx_18)
when _T_2443 :
node _T_2444 = shl(UInt<5>(0h12), 3)
node _T_2445 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2444)
node _T_2446 = bits(_T_2445, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_2446
node _idx_T_19 = add(write_start_index, UInt<5>(0h13))
node idx_19 = rem(_idx_T_19, UInt<6>(0h20))
node _T_2447 = eq(UInt<1>(0h0), idx_19)
when _T_2447 :
node _T_2448 = shl(UInt<5>(0h13), 3)
node _T_2449 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2448)
node _T_2450 = bits(_T_2449, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_2450
node _T_2451 = eq(UInt<1>(0h1), idx_19)
when _T_2451 :
node _T_2452 = shl(UInt<5>(0h13), 3)
node _T_2453 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2452)
node _T_2454 = bits(_T_2453, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_2454
node _T_2455 = eq(UInt<2>(0h2), idx_19)
when _T_2455 :
node _T_2456 = shl(UInt<5>(0h13), 3)
node _T_2457 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2456)
node _T_2458 = bits(_T_2457, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_2458
node _T_2459 = eq(UInt<2>(0h3), idx_19)
when _T_2459 :
node _T_2460 = shl(UInt<5>(0h13), 3)
node _T_2461 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2460)
node _T_2462 = bits(_T_2461, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_2462
node _T_2463 = eq(UInt<3>(0h4), idx_19)
when _T_2463 :
node _T_2464 = shl(UInt<5>(0h13), 3)
node _T_2465 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2464)
node _T_2466 = bits(_T_2465, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_2466
node _T_2467 = eq(UInt<3>(0h5), idx_19)
when _T_2467 :
node _T_2468 = shl(UInt<5>(0h13), 3)
node _T_2469 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2468)
node _T_2470 = bits(_T_2469, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_2470
node _T_2471 = eq(UInt<3>(0h6), idx_19)
when _T_2471 :
node _T_2472 = shl(UInt<5>(0h13), 3)
node _T_2473 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2472)
node _T_2474 = bits(_T_2473, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_2474
node _T_2475 = eq(UInt<3>(0h7), idx_19)
when _T_2475 :
node _T_2476 = shl(UInt<5>(0h13), 3)
node _T_2477 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2476)
node _T_2478 = bits(_T_2477, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_2478
node _T_2479 = eq(UInt<4>(0h8), idx_19)
when _T_2479 :
node _T_2480 = shl(UInt<5>(0h13), 3)
node _T_2481 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2480)
node _T_2482 = bits(_T_2481, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_2482
node _T_2483 = eq(UInt<4>(0h9), idx_19)
when _T_2483 :
node _T_2484 = shl(UInt<5>(0h13), 3)
node _T_2485 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2484)
node _T_2486 = bits(_T_2485, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_2486
node _T_2487 = eq(UInt<4>(0ha), idx_19)
when _T_2487 :
node _T_2488 = shl(UInt<5>(0h13), 3)
node _T_2489 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2488)
node _T_2490 = bits(_T_2489, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_2490
node _T_2491 = eq(UInt<4>(0hb), idx_19)
when _T_2491 :
node _T_2492 = shl(UInt<5>(0h13), 3)
node _T_2493 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2492)
node _T_2494 = bits(_T_2493, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_2494
node _T_2495 = eq(UInt<4>(0hc), idx_19)
when _T_2495 :
node _T_2496 = shl(UInt<5>(0h13), 3)
node _T_2497 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2496)
node _T_2498 = bits(_T_2497, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_2498
node _T_2499 = eq(UInt<4>(0hd), idx_19)
when _T_2499 :
node _T_2500 = shl(UInt<5>(0h13), 3)
node _T_2501 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2500)
node _T_2502 = bits(_T_2501, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_2502
node _T_2503 = eq(UInt<4>(0he), idx_19)
when _T_2503 :
node _T_2504 = shl(UInt<5>(0h13), 3)
node _T_2505 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2504)
node _T_2506 = bits(_T_2505, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_2506
node _T_2507 = eq(UInt<4>(0hf), idx_19)
when _T_2507 :
node _T_2508 = shl(UInt<5>(0h13), 3)
node _T_2509 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2508)
node _T_2510 = bits(_T_2509, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_2510
node _T_2511 = eq(UInt<5>(0h10), idx_19)
when _T_2511 :
node _T_2512 = shl(UInt<5>(0h13), 3)
node _T_2513 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2512)
node _T_2514 = bits(_T_2513, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_2514
node _T_2515 = eq(UInt<5>(0h11), idx_19)
when _T_2515 :
node _T_2516 = shl(UInt<5>(0h13), 3)
node _T_2517 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2516)
node _T_2518 = bits(_T_2517, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_2518
node _T_2519 = eq(UInt<5>(0h12), idx_19)
when _T_2519 :
node _T_2520 = shl(UInt<5>(0h13), 3)
node _T_2521 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2520)
node _T_2522 = bits(_T_2521, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_2522
node _T_2523 = eq(UInt<5>(0h13), idx_19)
when _T_2523 :
node _T_2524 = shl(UInt<5>(0h13), 3)
node _T_2525 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2524)
node _T_2526 = bits(_T_2525, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_2526
node _T_2527 = eq(UInt<5>(0h14), idx_19)
when _T_2527 :
node _T_2528 = shl(UInt<5>(0h13), 3)
node _T_2529 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2528)
node _T_2530 = bits(_T_2529, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_2530
node _T_2531 = eq(UInt<5>(0h15), idx_19)
when _T_2531 :
node _T_2532 = shl(UInt<5>(0h13), 3)
node _T_2533 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2532)
node _T_2534 = bits(_T_2533, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_2534
node _T_2535 = eq(UInt<5>(0h16), idx_19)
when _T_2535 :
node _T_2536 = shl(UInt<5>(0h13), 3)
node _T_2537 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2536)
node _T_2538 = bits(_T_2537, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_2538
node _T_2539 = eq(UInt<5>(0h17), idx_19)
when _T_2539 :
node _T_2540 = shl(UInt<5>(0h13), 3)
node _T_2541 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2540)
node _T_2542 = bits(_T_2541, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_2542
node _T_2543 = eq(UInt<5>(0h18), idx_19)
when _T_2543 :
node _T_2544 = shl(UInt<5>(0h13), 3)
node _T_2545 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2544)
node _T_2546 = bits(_T_2545, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_2546
node _T_2547 = eq(UInt<5>(0h19), idx_19)
when _T_2547 :
node _T_2548 = shl(UInt<5>(0h13), 3)
node _T_2549 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2548)
node _T_2550 = bits(_T_2549, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_2550
node _T_2551 = eq(UInt<5>(0h1a), idx_19)
when _T_2551 :
node _T_2552 = shl(UInt<5>(0h13), 3)
node _T_2553 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2552)
node _T_2554 = bits(_T_2553, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_2554
node _T_2555 = eq(UInt<5>(0h1b), idx_19)
when _T_2555 :
node _T_2556 = shl(UInt<5>(0h13), 3)
node _T_2557 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2556)
node _T_2558 = bits(_T_2557, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_2558
node _T_2559 = eq(UInt<5>(0h1c), idx_19)
when _T_2559 :
node _T_2560 = shl(UInt<5>(0h13), 3)
node _T_2561 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2560)
node _T_2562 = bits(_T_2561, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_2562
node _T_2563 = eq(UInt<5>(0h1d), idx_19)
when _T_2563 :
node _T_2564 = shl(UInt<5>(0h13), 3)
node _T_2565 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2564)
node _T_2566 = bits(_T_2565, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_2566
node _T_2567 = eq(UInt<5>(0h1e), idx_19)
when _T_2567 :
node _T_2568 = shl(UInt<5>(0h13), 3)
node _T_2569 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2568)
node _T_2570 = bits(_T_2569, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_2570
node _T_2571 = eq(UInt<5>(0h1f), idx_19)
when _T_2571 :
node _T_2572 = shl(UInt<5>(0h13), 3)
node _T_2573 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2572)
node _T_2574 = bits(_T_2573, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_2574
node _idx_T_20 = add(write_start_index, UInt<5>(0h14))
node idx_20 = rem(_idx_T_20, UInt<6>(0h20))
node _T_2575 = eq(UInt<1>(0h0), idx_20)
when _T_2575 :
node _T_2576 = shl(UInt<5>(0h14), 3)
node _T_2577 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2576)
node _T_2578 = bits(_T_2577, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_2578
node _T_2579 = eq(UInt<1>(0h1), idx_20)
when _T_2579 :
node _T_2580 = shl(UInt<5>(0h14), 3)
node _T_2581 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2580)
node _T_2582 = bits(_T_2581, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_2582
node _T_2583 = eq(UInt<2>(0h2), idx_20)
when _T_2583 :
node _T_2584 = shl(UInt<5>(0h14), 3)
node _T_2585 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2584)
node _T_2586 = bits(_T_2585, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_2586
node _T_2587 = eq(UInt<2>(0h3), idx_20)
when _T_2587 :
node _T_2588 = shl(UInt<5>(0h14), 3)
node _T_2589 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2588)
node _T_2590 = bits(_T_2589, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_2590
node _T_2591 = eq(UInt<3>(0h4), idx_20)
when _T_2591 :
node _T_2592 = shl(UInt<5>(0h14), 3)
node _T_2593 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2592)
node _T_2594 = bits(_T_2593, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_2594
node _T_2595 = eq(UInt<3>(0h5), idx_20)
when _T_2595 :
node _T_2596 = shl(UInt<5>(0h14), 3)
node _T_2597 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2596)
node _T_2598 = bits(_T_2597, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_2598
node _T_2599 = eq(UInt<3>(0h6), idx_20)
when _T_2599 :
node _T_2600 = shl(UInt<5>(0h14), 3)
node _T_2601 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2600)
node _T_2602 = bits(_T_2601, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_2602
node _T_2603 = eq(UInt<3>(0h7), idx_20)
when _T_2603 :
node _T_2604 = shl(UInt<5>(0h14), 3)
node _T_2605 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2604)
node _T_2606 = bits(_T_2605, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_2606
node _T_2607 = eq(UInt<4>(0h8), idx_20)
when _T_2607 :
node _T_2608 = shl(UInt<5>(0h14), 3)
node _T_2609 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2608)
node _T_2610 = bits(_T_2609, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_2610
node _T_2611 = eq(UInt<4>(0h9), idx_20)
when _T_2611 :
node _T_2612 = shl(UInt<5>(0h14), 3)
node _T_2613 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2612)
node _T_2614 = bits(_T_2613, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_2614
node _T_2615 = eq(UInt<4>(0ha), idx_20)
when _T_2615 :
node _T_2616 = shl(UInt<5>(0h14), 3)
node _T_2617 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2616)
node _T_2618 = bits(_T_2617, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_2618
node _T_2619 = eq(UInt<4>(0hb), idx_20)
when _T_2619 :
node _T_2620 = shl(UInt<5>(0h14), 3)
node _T_2621 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2620)
node _T_2622 = bits(_T_2621, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_2622
node _T_2623 = eq(UInt<4>(0hc), idx_20)
when _T_2623 :
node _T_2624 = shl(UInt<5>(0h14), 3)
node _T_2625 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2624)
node _T_2626 = bits(_T_2625, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_2626
node _T_2627 = eq(UInt<4>(0hd), idx_20)
when _T_2627 :
node _T_2628 = shl(UInt<5>(0h14), 3)
node _T_2629 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2628)
node _T_2630 = bits(_T_2629, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_2630
node _T_2631 = eq(UInt<4>(0he), idx_20)
when _T_2631 :
node _T_2632 = shl(UInt<5>(0h14), 3)
node _T_2633 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2632)
node _T_2634 = bits(_T_2633, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_2634
node _T_2635 = eq(UInt<4>(0hf), idx_20)
when _T_2635 :
node _T_2636 = shl(UInt<5>(0h14), 3)
node _T_2637 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2636)
node _T_2638 = bits(_T_2637, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_2638
node _T_2639 = eq(UInt<5>(0h10), idx_20)
when _T_2639 :
node _T_2640 = shl(UInt<5>(0h14), 3)
node _T_2641 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2640)
node _T_2642 = bits(_T_2641, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_2642
node _T_2643 = eq(UInt<5>(0h11), idx_20)
when _T_2643 :
node _T_2644 = shl(UInt<5>(0h14), 3)
node _T_2645 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2644)
node _T_2646 = bits(_T_2645, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_2646
node _T_2647 = eq(UInt<5>(0h12), idx_20)
when _T_2647 :
node _T_2648 = shl(UInt<5>(0h14), 3)
node _T_2649 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2648)
node _T_2650 = bits(_T_2649, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_2650
node _T_2651 = eq(UInt<5>(0h13), idx_20)
when _T_2651 :
node _T_2652 = shl(UInt<5>(0h14), 3)
node _T_2653 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2652)
node _T_2654 = bits(_T_2653, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_2654
node _T_2655 = eq(UInt<5>(0h14), idx_20)
when _T_2655 :
node _T_2656 = shl(UInt<5>(0h14), 3)
node _T_2657 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2656)
node _T_2658 = bits(_T_2657, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_2658
node _T_2659 = eq(UInt<5>(0h15), idx_20)
when _T_2659 :
node _T_2660 = shl(UInt<5>(0h14), 3)
node _T_2661 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2660)
node _T_2662 = bits(_T_2661, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_2662
node _T_2663 = eq(UInt<5>(0h16), idx_20)
when _T_2663 :
node _T_2664 = shl(UInt<5>(0h14), 3)
node _T_2665 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2664)
node _T_2666 = bits(_T_2665, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_2666
node _T_2667 = eq(UInt<5>(0h17), idx_20)
when _T_2667 :
node _T_2668 = shl(UInt<5>(0h14), 3)
node _T_2669 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2668)
node _T_2670 = bits(_T_2669, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_2670
node _T_2671 = eq(UInt<5>(0h18), idx_20)
when _T_2671 :
node _T_2672 = shl(UInt<5>(0h14), 3)
node _T_2673 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2672)
node _T_2674 = bits(_T_2673, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_2674
node _T_2675 = eq(UInt<5>(0h19), idx_20)
when _T_2675 :
node _T_2676 = shl(UInt<5>(0h14), 3)
node _T_2677 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2676)
node _T_2678 = bits(_T_2677, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_2678
node _T_2679 = eq(UInt<5>(0h1a), idx_20)
when _T_2679 :
node _T_2680 = shl(UInt<5>(0h14), 3)
node _T_2681 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2680)
node _T_2682 = bits(_T_2681, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_2682
node _T_2683 = eq(UInt<5>(0h1b), idx_20)
when _T_2683 :
node _T_2684 = shl(UInt<5>(0h14), 3)
node _T_2685 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2684)
node _T_2686 = bits(_T_2685, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_2686
node _T_2687 = eq(UInt<5>(0h1c), idx_20)
when _T_2687 :
node _T_2688 = shl(UInt<5>(0h14), 3)
node _T_2689 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2688)
node _T_2690 = bits(_T_2689, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_2690
node _T_2691 = eq(UInt<5>(0h1d), idx_20)
when _T_2691 :
node _T_2692 = shl(UInt<5>(0h14), 3)
node _T_2693 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2692)
node _T_2694 = bits(_T_2693, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_2694
node _T_2695 = eq(UInt<5>(0h1e), idx_20)
when _T_2695 :
node _T_2696 = shl(UInt<5>(0h14), 3)
node _T_2697 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2696)
node _T_2698 = bits(_T_2697, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_2698
node _T_2699 = eq(UInt<5>(0h1f), idx_20)
when _T_2699 :
node _T_2700 = shl(UInt<5>(0h14), 3)
node _T_2701 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2700)
node _T_2702 = bits(_T_2701, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_2702
node _idx_T_21 = add(write_start_index, UInt<5>(0h15))
node idx_21 = rem(_idx_T_21, UInt<6>(0h20))
node _T_2703 = eq(UInt<1>(0h0), idx_21)
when _T_2703 :
node _T_2704 = shl(UInt<5>(0h15), 3)
node _T_2705 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2704)
node _T_2706 = bits(_T_2705, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_2706
node _T_2707 = eq(UInt<1>(0h1), idx_21)
when _T_2707 :
node _T_2708 = shl(UInt<5>(0h15), 3)
node _T_2709 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2708)
node _T_2710 = bits(_T_2709, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_2710
node _T_2711 = eq(UInt<2>(0h2), idx_21)
when _T_2711 :
node _T_2712 = shl(UInt<5>(0h15), 3)
node _T_2713 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2712)
node _T_2714 = bits(_T_2713, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_2714
node _T_2715 = eq(UInt<2>(0h3), idx_21)
when _T_2715 :
node _T_2716 = shl(UInt<5>(0h15), 3)
node _T_2717 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2716)
node _T_2718 = bits(_T_2717, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_2718
node _T_2719 = eq(UInt<3>(0h4), idx_21)
when _T_2719 :
node _T_2720 = shl(UInt<5>(0h15), 3)
node _T_2721 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2720)
node _T_2722 = bits(_T_2721, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_2722
node _T_2723 = eq(UInt<3>(0h5), idx_21)
when _T_2723 :
node _T_2724 = shl(UInt<5>(0h15), 3)
node _T_2725 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2724)
node _T_2726 = bits(_T_2725, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_2726
node _T_2727 = eq(UInt<3>(0h6), idx_21)
when _T_2727 :
node _T_2728 = shl(UInt<5>(0h15), 3)
node _T_2729 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2728)
node _T_2730 = bits(_T_2729, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_2730
node _T_2731 = eq(UInt<3>(0h7), idx_21)
when _T_2731 :
node _T_2732 = shl(UInt<5>(0h15), 3)
node _T_2733 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2732)
node _T_2734 = bits(_T_2733, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_2734
node _T_2735 = eq(UInt<4>(0h8), idx_21)
when _T_2735 :
node _T_2736 = shl(UInt<5>(0h15), 3)
node _T_2737 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2736)
node _T_2738 = bits(_T_2737, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_2738
node _T_2739 = eq(UInt<4>(0h9), idx_21)
when _T_2739 :
node _T_2740 = shl(UInt<5>(0h15), 3)
node _T_2741 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2740)
node _T_2742 = bits(_T_2741, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_2742
node _T_2743 = eq(UInt<4>(0ha), idx_21)
when _T_2743 :
node _T_2744 = shl(UInt<5>(0h15), 3)
node _T_2745 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2744)
node _T_2746 = bits(_T_2745, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_2746
node _T_2747 = eq(UInt<4>(0hb), idx_21)
when _T_2747 :
node _T_2748 = shl(UInt<5>(0h15), 3)
node _T_2749 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2748)
node _T_2750 = bits(_T_2749, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_2750
node _T_2751 = eq(UInt<4>(0hc), idx_21)
when _T_2751 :
node _T_2752 = shl(UInt<5>(0h15), 3)
node _T_2753 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2752)
node _T_2754 = bits(_T_2753, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_2754
node _T_2755 = eq(UInt<4>(0hd), idx_21)
when _T_2755 :
node _T_2756 = shl(UInt<5>(0h15), 3)
node _T_2757 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2756)
node _T_2758 = bits(_T_2757, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_2758
node _T_2759 = eq(UInt<4>(0he), idx_21)
when _T_2759 :
node _T_2760 = shl(UInt<5>(0h15), 3)
node _T_2761 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2760)
node _T_2762 = bits(_T_2761, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_2762
node _T_2763 = eq(UInt<4>(0hf), idx_21)
when _T_2763 :
node _T_2764 = shl(UInt<5>(0h15), 3)
node _T_2765 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2764)
node _T_2766 = bits(_T_2765, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_2766
node _T_2767 = eq(UInt<5>(0h10), idx_21)
when _T_2767 :
node _T_2768 = shl(UInt<5>(0h15), 3)
node _T_2769 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2768)
node _T_2770 = bits(_T_2769, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_2770
node _T_2771 = eq(UInt<5>(0h11), idx_21)
when _T_2771 :
node _T_2772 = shl(UInt<5>(0h15), 3)
node _T_2773 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2772)
node _T_2774 = bits(_T_2773, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_2774
node _T_2775 = eq(UInt<5>(0h12), idx_21)
when _T_2775 :
node _T_2776 = shl(UInt<5>(0h15), 3)
node _T_2777 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2776)
node _T_2778 = bits(_T_2777, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_2778
node _T_2779 = eq(UInt<5>(0h13), idx_21)
when _T_2779 :
node _T_2780 = shl(UInt<5>(0h15), 3)
node _T_2781 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2780)
node _T_2782 = bits(_T_2781, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_2782
node _T_2783 = eq(UInt<5>(0h14), idx_21)
when _T_2783 :
node _T_2784 = shl(UInt<5>(0h15), 3)
node _T_2785 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2784)
node _T_2786 = bits(_T_2785, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_2786
node _T_2787 = eq(UInt<5>(0h15), idx_21)
when _T_2787 :
node _T_2788 = shl(UInt<5>(0h15), 3)
node _T_2789 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2788)
node _T_2790 = bits(_T_2789, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_2790
node _T_2791 = eq(UInt<5>(0h16), idx_21)
when _T_2791 :
node _T_2792 = shl(UInt<5>(0h15), 3)
node _T_2793 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2792)
node _T_2794 = bits(_T_2793, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_2794
node _T_2795 = eq(UInt<5>(0h17), idx_21)
when _T_2795 :
node _T_2796 = shl(UInt<5>(0h15), 3)
node _T_2797 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2796)
node _T_2798 = bits(_T_2797, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_2798
node _T_2799 = eq(UInt<5>(0h18), idx_21)
when _T_2799 :
node _T_2800 = shl(UInt<5>(0h15), 3)
node _T_2801 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2800)
node _T_2802 = bits(_T_2801, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_2802
node _T_2803 = eq(UInt<5>(0h19), idx_21)
when _T_2803 :
node _T_2804 = shl(UInt<5>(0h15), 3)
node _T_2805 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2804)
node _T_2806 = bits(_T_2805, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_2806
node _T_2807 = eq(UInt<5>(0h1a), idx_21)
when _T_2807 :
node _T_2808 = shl(UInt<5>(0h15), 3)
node _T_2809 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2808)
node _T_2810 = bits(_T_2809, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_2810
node _T_2811 = eq(UInt<5>(0h1b), idx_21)
when _T_2811 :
node _T_2812 = shl(UInt<5>(0h15), 3)
node _T_2813 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2812)
node _T_2814 = bits(_T_2813, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_2814
node _T_2815 = eq(UInt<5>(0h1c), idx_21)
when _T_2815 :
node _T_2816 = shl(UInt<5>(0h15), 3)
node _T_2817 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2816)
node _T_2818 = bits(_T_2817, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_2818
node _T_2819 = eq(UInt<5>(0h1d), idx_21)
when _T_2819 :
node _T_2820 = shl(UInt<5>(0h15), 3)
node _T_2821 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2820)
node _T_2822 = bits(_T_2821, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_2822
node _T_2823 = eq(UInt<5>(0h1e), idx_21)
when _T_2823 :
node _T_2824 = shl(UInt<5>(0h15), 3)
node _T_2825 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2824)
node _T_2826 = bits(_T_2825, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_2826
node _T_2827 = eq(UInt<5>(0h1f), idx_21)
when _T_2827 :
node _T_2828 = shl(UInt<5>(0h15), 3)
node _T_2829 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2828)
node _T_2830 = bits(_T_2829, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_2830
node _idx_T_22 = add(write_start_index, UInt<5>(0h16))
node idx_22 = rem(_idx_T_22, UInt<6>(0h20))
node _T_2831 = eq(UInt<1>(0h0), idx_22)
when _T_2831 :
node _T_2832 = shl(UInt<5>(0h16), 3)
node _T_2833 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2832)
node _T_2834 = bits(_T_2833, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_2834
node _T_2835 = eq(UInt<1>(0h1), idx_22)
when _T_2835 :
node _T_2836 = shl(UInt<5>(0h16), 3)
node _T_2837 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2836)
node _T_2838 = bits(_T_2837, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_2838
node _T_2839 = eq(UInt<2>(0h2), idx_22)
when _T_2839 :
node _T_2840 = shl(UInt<5>(0h16), 3)
node _T_2841 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2840)
node _T_2842 = bits(_T_2841, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_2842
node _T_2843 = eq(UInt<2>(0h3), idx_22)
when _T_2843 :
node _T_2844 = shl(UInt<5>(0h16), 3)
node _T_2845 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2844)
node _T_2846 = bits(_T_2845, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_2846
node _T_2847 = eq(UInt<3>(0h4), idx_22)
when _T_2847 :
node _T_2848 = shl(UInt<5>(0h16), 3)
node _T_2849 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2848)
node _T_2850 = bits(_T_2849, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_2850
node _T_2851 = eq(UInt<3>(0h5), idx_22)
when _T_2851 :
node _T_2852 = shl(UInt<5>(0h16), 3)
node _T_2853 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2852)
node _T_2854 = bits(_T_2853, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_2854
node _T_2855 = eq(UInt<3>(0h6), idx_22)
when _T_2855 :
node _T_2856 = shl(UInt<5>(0h16), 3)
node _T_2857 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2856)
node _T_2858 = bits(_T_2857, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_2858
node _T_2859 = eq(UInt<3>(0h7), idx_22)
when _T_2859 :
node _T_2860 = shl(UInt<5>(0h16), 3)
node _T_2861 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2860)
node _T_2862 = bits(_T_2861, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_2862
node _T_2863 = eq(UInt<4>(0h8), idx_22)
when _T_2863 :
node _T_2864 = shl(UInt<5>(0h16), 3)
node _T_2865 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2864)
node _T_2866 = bits(_T_2865, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_2866
node _T_2867 = eq(UInt<4>(0h9), idx_22)
when _T_2867 :
node _T_2868 = shl(UInt<5>(0h16), 3)
node _T_2869 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2868)
node _T_2870 = bits(_T_2869, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_2870
node _T_2871 = eq(UInt<4>(0ha), idx_22)
when _T_2871 :
node _T_2872 = shl(UInt<5>(0h16), 3)
node _T_2873 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2872)
node _T_2874 = bits(_T_2873, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_2874
node _T_2875 = eq(UInt<4>(0hb), idx_22)
when _T_2875 :
node _T_2876 = shl(UInt<5>(0h16), 3)
node _T_2877 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2876)
node _T_2878 = bits(_T_2877, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_2878
node _T_2879 = eq(UInt<4>(0hc), idx_22)
when _T_2879 :
node _T_2880 = shl(UInt<5>(0h16), 3)
node _T_2881 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2880)
node _T_2882 = bits(_T_2881, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_2882
node _T_2883 = eq(UInt<4>(0hd), idx_22)
when _T_2883 :
node _T_2884 = shl(UInt<5>(0h16), 3)
node _T_2885 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2884)
node _T_2886 = bits(_T_2885, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_2886
node _T_2887 = eq(UInt<4>(0he), idx_22)
when _T_2887 :
node _T_2888 = shl(UInt<5>(0h16), 3)
node _T_2889 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2888)
node _T_2890 = bits(_T_2889, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_2890
node _T_2891 = eq(UInt<4>(0hf), idx_22)
when _T_2891 :
node _T_2892 = shl(UInt<5>(0h16), 3)
node _T_2893 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2892)
node _T_2894 = bits(_T_2893, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_2894
node _T_2895 = eq(UInt<5>(0h10), idx_22)
when _T_2895 :
node _T_2896 = shl(UInt<5>(0h16), 3)
node _T_2897 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2896)
node _T_2898 = bits(_T_2897, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_2898
node _T_2899 = eq(UInt<5>(0h11), idx_22)
when _T_2899 :
node _T_2900 = shl(UInt<5>(0h16), 3)
node _T_2901 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2900)
node _T_2902 = bits(_T_2901, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_2902
node _T_2903 = eq(UInt<5>(0h12), idx_22)
when _T_2903 :
node _T_2904 = shl(UInt<5>(0h16), 3)
node _T_2905 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2904)
node _T_2906 = bits(_T_2905, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_2906
node _T_2907 = eq(UInt<5>(0h13), idx_22)
when _T_2907 :
node _T_2908 = shl(UInt<5>(0h16), 3)
node _T_2909 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2908)
node _T_2910 = bits(_T_2909, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_2910
node _T_2911 = eq(UInt<5>(0h14), idx_22)
when _T_2911 :
node _T_2912 = shl(UInt<5>(0h16), 3)
node _T_2913 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2912)
node _T_2914 = bits(_T_2913, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_2914
node _T_2915 = eq(UInt<5>(0h15), idx_22)
when _T_2915 :
node _T_2916 = shl(UInt<5>(0h16), 3)
node _T_2917 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2916)
node _T_2918 = bits(_T_2917, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_2918
node _T_2919 = eq(UInt<5>(0h16), idx_22)
when _T_2919 :
node _T_2920 = shl(UInt<5>(0h16), 3)
node _T_2921 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2920)
node _T_2922 = bits(_T_2921, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_2922
node _T_2923 = eq(UInt<5>(0h17), idx_22)
when _T_2923 :
node _T_2924 = shl(UInt<5>(0h16), 3)
node _T_2925 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2924)
node _T_2926 = bits(_T_2925, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_2926
node _T_2927 = eq(UInt<5>(0h18), idx_22)
when _T_2927 :
node _T_2928 = shl(UInt<5>(0h16), 3)
node _T_2929 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2928)
node _T_2930 = bits(_T_2929, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_2930
node _T_2931 = eq(UInt<5>(0h19), idx_22)
when _T_2931 :
node _T_2932 = shl(UInt<5>(0h16), 3)
node _T_2933 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2932)
node _T_2934 = bits(_T_2933, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_2934
node _T_2935 = eq(UInt<5>(0h1a), idx_22)
when _T_2935 :
node _T_2936 = shl(UInt<5>(0h16), 3)
node _T_2937 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2936)
node _T_2938 = bits(_T_2937, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_2938
node _T_2939 = eq(UInt<5>(0h1b), idx_22)
when _T_2939 :
node _T_2940 = shl(UInt<5>(0h16), 3)
node _T_2941 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2940)
node _T_2942 = bits(_T_2941, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_2942
node _T_2943 = eq(UInt<5>(0h1c), idx_22)
when _T_2943 :
node _T_2944 = shl(UInt<5>(0h16), 3)
node _T_2945 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2944)
node _T_2946 = bits(_T_2945, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_2946
node _T_2947 = eq(UInt<5>(0h1d), idx_22)
when _T_2947 :
node _T_2948 = shl(UInt<5>(0h16), 3)
node _T_2949 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2948)
node _T_2950 = bits(_T_2949, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_2950
node _T_2951 = eq(UInt<5>(0h1e), idx_22)
when _T_2951 :
node _T_2952 = shl(UInt<5>(0h16), 3)
node _T_2953 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2952)
node _T_2954 = bits(_T_2953, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_2954
node _T_2955 = eq(UInt<5>(0h1f), idx_22)
when _T_2955 :
node _T_2956 = shl(UInt<5>(0h16), 3)
node _T_2957 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2956)
node _T_2958 = bits(_T_2957, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_2958
node _idx_T_23 = add(write_start_index, UInt<5>(0h17))
node idx_23 = rem(_idx_T_23, UInt<6>(0h20))
node _T_2959 = eq(UInt<1>(0h0), idx_23)
when _T_2959 :
node _T_2960 = shl(UInt<5>(0h17), 3)
node _T_2961 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2960)
node _T_2962 = bits(_T_2961, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_2962
node _T_2963 = eq(UInt<1>(0h1), idx_23)
when _T_2963 :
node _T_2964 = shl(UInt<5>(0h17), 3)
node _T_2965 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2964)
node _T_2966 = bits(_T_2965, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_2966
node _T_2967 = eq(UInt<2>(0h2), idx_23)
when _T_2967 :
node _T_2968 = shl(UInt<5>(0h17), 3)
node _T_2969 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2968)
node _T_2970 = bits(_T_2969, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_2970
node _T_2971 = eq(UInt<2>(0h3), idx_23)
when _T_2971 :
node _T_2972 = shl(UInt<5>(0h17), 3)
node _T_2973 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2972)
node _T_2974 = bits(_T_2973, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_2974
node _T_2975 = eq(UInt<3>(0h4), idx_23)
when _T_2975 :
node _T_2976 = shl(UInt<5>(0h17), 3)
node _T_2977 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2976)
node _T_2978 = bits(_T_2977, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_2978
node _T_2979 = eq(UInt<3>(0h5), idx_23)
when _T_2979 :
node _T_2980 = shl(UInt<5>(0h17), 3)
node _T_2981 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2980)
node _T_2982 = bits(_T_2981, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_2982
node _T_2983 = eq(UInt<3>(0h6), idx_23)
when _T_2983 :
node _T_2984 = shl(UInt<5>(0h17), 3)
node _T_2985 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2984)
node _T_2986 = bits(_T_2985, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_2986
node _T_2987 = eq(UInt<3>(0h7), idx_23)
when _T_2987 :
node _T_2988 = shl(UInt<5>(0h17), 3)
node _T_2989 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2988)
node _T_2990 = bits(_T_2989, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_2990
node _T_2991 = eq(UInt<4>(0h8), idx_23)
when _T_2991 :
node _T_2992 = shl(UInt<5>(0h17), 3)
node _T_2993 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2992)
node _T_2994 = bits(_T_2993, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_2994
node _T_2995 = eq(UInt<4>(0h9), idx_23)
when _T_2995 :
node _T_2996 = shl(UInt<5>(0h17), 3)
node _T_2997 = dshr(incoming_writes_Q.io.deq.bits.data, _T_2996)
node _T_2998 = bits(_T_2997, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_2998
node _T_2999 = eq(UInt<4>(0ha), idx_23)
when _T_2999 :
node _T_3000 = shl(UInt<5>(0h17), 3)
node _T_3001 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3000)
node _T_3002 = bits(_T_3001, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_3002
node _T_3003 = eq(UInt<4>(0hb), idx_23)
when _T_3003 :
node _T_3004 = shl(UInt<5>(0h17), 3)
node _T_3005 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3004)
node _T_3006 = bits(_T_3005, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_3006
node _T_3007 = eq(UInt<4>(0hc), idx_23)
when _T_3007 :
node _T_3008 = shl(UInt<5>(0h17), 3)
node _T_3009 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3008)
node _T_3010 = bits(_T_3009, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_3010
node _T_3011 = eq(UInt<4>(0hd), idx_23)
when _T_3011 :
node _T_3012 = shl(UInt<5>(0h17), 3)
node _T_3013 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3012)
node _T_3014 = bits(_T_3013, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_3014
node _T_3015 = eq(UInt<4>(0he), idx_23)
when _T_3015 :
node _T_3016 = shl(UInt<5>(0h17), 3)
node _T_3017 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3016)
node _T_3018 = bits(_T_3017, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_3018
node _T_3019 = eq(UInt<4>(0hf), idx_23)
when _T_3019 :
node _T_3020 = shl(UInt<5>(0h17), 3)
node _T_3021 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3020)
node _T_3022 = bits(_T_3021, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_3022
node _T_3023 = eq(UInt<5>(0h10), idx_23)
when _T_3023 :
node _T_3024 = shl(UInt<5>(0h17), 3)
node _T_3025 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3024)
node _T_3026 = bits(_T_3025, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_3026
node _T_3027 = eq(UInt<5>(0h11), idx_23)
when _T_3027 :
node _T_3028 = shl(UInt<5>(0h17), 3)
node _T_3029 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3028)
node _T_3030 = bits(_T_3029, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_3030
node _T_3031 = eq(UInt<5>(0h12), idx_23)
when _T_3031 :
node _T_3032 = shl(UInt<5>(0h17), 3)
node _T_3033 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3032)
node _T_3034 = bits(_T_3033, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_3034
node _T_3035 = eq(UInt<5>(0h13), idx_23)
when _T_3035 :
node _T_3036 = shl(UInt<5>(0h17), 3)
node _T_3037 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3036)
node _T_3038 = bits(_T_3037, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_3038
node _T_3039 = eq(UInt<5>(0h14), idx_23)
when _T_3039 :
node _T_3040 = shl(UInt<5>(0h17), 3)
node _T_3041 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3040)
node _T_3042 = bits(_T_3041, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_3042
node _T_3043 = eq(UInt<5>(0h15), idx_23)
when _T_3043 :
node _T_3044 = shl(UInt<5>(0h17), 3)
node _T_3045 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3044)
node _T_3046 = bits(_T_3045, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_3046
node _T_3047 = eq(UInt<5>(0h16), idx_23)
when _T_3047 :
node _T_3048 = shl(UInt<5>(0h17), 3)
node _T_3049 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3048)
node _T_3050 = bits(_T_3049, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_3050
node _T_3051 = eq(UInt<5>(0h17), idx_23)
when _T_3051 :
node _T_3052 = shl(UInt<5>(0h17), 3)
node _T_3053 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3052)
node _T_3054 = bits(_T_3053, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_3054
node _T_3055 = eq(UInt<5>(0h18), idx_23)
when _T_3055 :
node _T_3056 = shl(UInt<5>(0h17), 3)
node _T_3057 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3056)
node _T_3058 = bits(_T_3057, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_3058
node _T_3059 = eq(UInt<5>(0h19), idx_23)
when _T_3059 :
node _T_3060 = shl(UInt<5>(0h17), 3)
node _T_3061 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3060)
node _T_3062 = bits(_T_3061, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_3062
node _T_3063 = eq(UInt<5>(0h1a), idx_23)
when _T_3063 :
node _T_3064 = shl(UInt<5>(0h17), 3)
node _T_3065 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3064)
node _T_3066 = bits(_T_3065, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_3066
node _T_3067 = eq(UInt<5>(0h1b), idx_23)
when _T_3067 :
node _T_3068 = shl(UInt<5>(0h17), 3)
node _T_3069 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3068)
node _T_3070 = bits(_T_3069, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_3070
node _T_3071 = eq(UInt<5>(0h1c), idx_23)
when _T_3071 :
node _T_3072 = shl(UInt<5>(0h17), 3)
node _T_3073 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3072)
node _T_3074 = bits(_T_3073, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_3074
node _T_3075 = eq(UInt<5>(0h1d), idx_23)
when _T_3075 :
node _T_3076 = shl(UInt<5>(0h17), 3)
node _T_3077 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3076)
node _T_3078 = bits(_T_3077, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_3078
node _T_3079 = eq(UInt<5>(0h1e), idx_23)
when _T_3079 :
node _T_3080 = shl(UInt<5>(0h17), 3)
node _T_3081 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3080)
node _T_3082 = bits(_T_3081, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_3082
node _T_3083 = eq(UInt<5>(0h1f), idx_23)
when _T_3083 :
node _T_3084 = shl(UInt<5>(0h17), 3)
node _T_3085 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3084)
node _T_3086 = bits(_T_3085, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_3086
node _idx_T_24 = add(write_start_index, UInt<5>(0h18))
node idx_24 = rem(_idx_T_24, UInt<6>(0h20))
node _T_3087 = eq(UInt<1>(0h0), idx_24)
when _T_3087 :
node _T_3088 = shl(UInt<5>(0h18), 3)
node _T_3089 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3088)
node _T_3090 = bits(_T_3089, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_3090
node _T_3091 = eq(UInt<1>(0h1), idx_24)
when _T_3091 :
node _T_3092 = shl(UInt<5>(0h18), 3)
node _T_3093 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3092)
node _T_3094 = bits(_T_3093, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_3094
node _T_3095 = eq(UInt<2>(0h2), idx_24)
when _T_3095 :
node _T_3096 = shl(UInt<5>(0h18), 3)
node _T_3097 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3096)
node _T_3098 = bits(_T_3097, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_3098
node _T_3099 = eq(UInt<2>(0h3), idx_24)
when _T_3099 :
node _T_3100 = shl(UInt<5>(0h18), 3)
node _T_3101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3100)
node _T_3102 = bits(_T_3101, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_3102
node _T_3103 = eq(UInt<3>(0h4), idx_24)
when _T_3103 :
node _T_3104 = shl(UInt<5>(0h18), 3)
node _T_3105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3104)
node _T_3106 = bits(_T_3105, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_3106
node _T_3107 = eq(UInt<3>(0h5), idx_24)
when _T_3107 :
node _T_3108 = shl(UInt<5>(0h18), 3)
node _T_3109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3108)
node _T_3110 = bits(_T_3109, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_3110
node _T_3111 = eq(UInt<3>(0h6), idx_24)
when _T_3111 :
node _T_3112 = shl(UInt<5>(0h18), 3)
node _T_3113 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3112)
node _T_3114 = bits(_T_3113, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_3114
node _T_3115 = eq(UInt<3>(0h7), idx_24)
when _T_3115 :
node _T_3116 = shl(UInt<5>(0h18), 3)
node _T_3117 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3116)
node _T_3118 = bits(_T_3117, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_3118
node _T_3119 = eq(UInt<4>(0h8), idx_24)
when _T_3119 :
node _T_3120 = shl(UInt<5>(0h18), 3)
node _T_3121 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3120)
node _T_3122 = bits(_T_3121, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_3122
node _T_3123 = eq(UInt<4>(0h9), idx_24)
when _T_3123 :
node _T_3124 = shl(UInt<5>(0h18), 3)
node _T_3125 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3124)
node _T_3126 = bits(_T_3125, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_3126
node _T_3127 = eq(UInt<4>(0ha), idx_24)
when _T_3127 :
node _T_3128 = shl(UInt<5>(0h18), 3)
node _T_3129 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3128)
node _T_3130 = bits(_T_3129, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_3130
node _T_3131 = eq(UInt<4>(0hb), idx_24)
when _T_3131 :
node _T_3132 = shl(UInt<5>(0h18), 3)
node _T_3133 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3132)
node _T_3134 = bits(_T_3133, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_3134
node _T_3135 = eq(UInt<4>(0hc), idx_24)
when _T_3135 :
node _T_3136 = shl(UInt<5>(0h18), 3)
node _T_3137 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3136)
node _T_3138 = bits(_T_3137, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_3138
node _T_3139 = eq(UInt<4>(0hd), idx_24)
when _T_3139 :
node _T_3140 = shl(UInt<5>(0h18), 3)
node _T_3141 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3140)
node _T_3142 = bits(_T_3141, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_3142
node _T_3143 = eq(UInt<4>(0he), idx_24)
when _T_3143 :
node _T_3144 = shl(UInt<5>(0h18), 3)
node _T_3145 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3144)
node _T_3146 = bits(_T_3145, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_3146
node _T_3147 = eq(UInt<4>(0hf), idx_24)
when _T_3147 :
node _T_3148 = shl(UInt<5>(0h18), 3)
node _T_3149 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3148)
node _T_3150 = bits(_T_3149, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_3150
node _T_3151 = eq(UInt<5>(0h10), idx_24)
when _T_3151 :
node _T_3152 = shl(UInt<5>(0h18), 3)
node _T_3153 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3152)
node _T_3154 = bits(_T_3153, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_3154
node _T_3155 = eq(UInt<5>(0h11), idx_24)
when _T_3155 :
node _T_3156 = shl(UInt<5>(0h18), 3)
node _T_3157 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3156)
node _T_3158 = bits(_T_3157, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_3158
node _T_3159 = eq(UInt<5>(0h12), idx_24)
when _T_3159 :
node _T_3160 = shl(UInt<5>(0h18), 3)
node _T_3161 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3160)
node _T_3162 = bits(_T_3161, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_3162
node _T_3163 = eq(UInt<5>(0h13), idx_24)
when _T_3163 :
node _T_3164 = shl(UInt<5>(0h18), 3)
node _T_3165 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3164)
node _T_3166 = bits(_T_3165, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_3166
node _T_3167 = eq(UInt<5>(0h14), idx_24)
when _T_3167 :
node _T_3168 = shl(UInt<5>(0h18), 3)
node _T_3169 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3168)
node _T_3170 = bits(_T_3169, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_3170
node _T_3171 = eq(UInt<5>(0h15), idx_24)
when _T_3171 :
node _T_3172 = shl(UInt<5>(0h18), 3)
node _T_3173 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3172)
node _T_3174 = bits(_T_3173, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_3174
node _T_3175 = eq(UInt<5>(0h16), idx_24)
when _T_3175 :
node _T_3176 = shl(UInt<5>(0h18), 3)
node _T_3177 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3176)
node _T_3178 = bits(_T_3177, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_3178
node _T_3179 = eq(UInt<5>(0h17), idx_24)
when _T_3179 :
node _T_3180 = shl(UInt<5>(0h18), 3)
node _T_3181 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3180)
node _T_3182 = bits(_T_3181, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_3182
node _T_3183 = eq(UInt<5>(0h18), idx_24)
when _T_3183 :
node _T_3184 = shl(UInt<5>(0h18), 3)
node _T_3185 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3184)
node _T_3186 = bits(_T_3185, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_3186
node _T_3187 = eq(UInt<5>(0h19), idx_24)
when _T_3187 :
node _T_3188 = shl(UInt<5>(0h18), 3)
node _T_3189 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3188)
node _T_3190 = bits(_T_3189, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_3190
node _T_3191 = eq(UInt<5>(0h1a), idx_24)
when _T_3191 :
node _T_3192 = shl(UInt<5>(0h18), 3)
node _T_3193 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3192)
node _T_3194 = bits(_T_3193, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_3194
node _T_3195 = eq(UInt<5>(0h1b), idx_24)
when _T_3195 :
node _T_3196 = shl(UInt<5>(0h18), 3)
node _T_3197 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3196)
node _T_3198 = bits(_T_3197, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_3198
node _T_3199 = eq(UInt<5>(0h1c), idx_24)
when _T_3199 :
node _T_3200 = shl(UInt<5>(0h18), 3)
node _T_3201 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3200)
node _T_3202 = bits(_T_3201, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_3202
node _T_3203 = eq(UInt<5>(0h1d), idx_24)
when _T_3203 :
node _T_3204 = shl(UInt<5>(0h18), 3)
node _T_3205 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3204)
node _T_3206 = bits(_T_3205, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_3206
node _T_3207 = eq(UInt<5>(0h1e), idx_24)
when _T_3207 :
node _T_3208 = shl(UInt<5>(0h18), 3)
node _T_3209 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3208)
node _T_3210 = bits(_T_3209, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_3210
node _T_3211 = eq(UInt<5>(0h1f), idx_24)
when _T_3211 :
node _T_3212 = shl(UInt<5>(0h18), 3)
node _T_3213 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3212)
node _T_3214 = bits(_T_3213, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_3214
node _idx_T_25 = add(write_start_index, UInt<5>(0h19))
node idx_25 = rem(_idx_T_25, UInt<6>(0h20))
node _T_3215 = eq(UInt<1>(0h0), idx_25)
when _T_3215 :
node _T_3216 = shl(UInt<5>(0h19), 3)
node _T_3217 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3216)
node _T_3218 = bits(_T_3217, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_3218
node _T_3219 = eq(UInt<1>(0h1), idx_25)
when _T_3219 :
node _T_3220 = shl(UInt<5>(0h19), 3)
node _T_3221 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3220)
node _T_3222 = bits(_T_3221, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_3222
node _T_3223 = eq(UInt<2>(0h2), idx_25)
when _T_3223 :
node _T_3224 = shl(UInt<5>(0h19), 3)
node _T_3225 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3224)
node _T_3226 = bits(_T_3225, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_3226
node _T_3227 = eq(UInt<2>(0h3), idx_25)
when _T_3227 :
node _T_3228 = shl(UInt<5>(0h19), 3)
node _T_3229 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3228)
node _T_3230 = bits(_T_3229, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_3230
node _T_3231 = eq(UInt<3>(0h4), idx_25)
when _T_3231 :
node _T_3232 = shl(UInt<5>(0h19), 3)
node _T_3233 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3232)
node _T_3234 = bits(_T_3233, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_3234
node _T_3235 = eq(UInt<3>(0h5), idx_25)
when _T_3235 :
node _T_3236 = shl(UInt<5>(0h19), 3)
node _T_3237 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3236)
node _T_3238 = bits(_T_3237, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_3238
node _T_3239 = eq(UInt<3>(0h6), idx_25)
when _T_3239 :
node _T_3240 = shl(UInt<5>(0h19), 3)
node _T_3241 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3240)
node _T_3242 = bits(_T_3241, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_3242
node _T_3243 = eq(UInt<3>(0h7), idx_25)
when _T_3243 :
node _T_3244 = shl(UInt<5>(0h19), 3)
node _T_3245 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3244)
node _T_3246 = bits(_T_3245, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_3246
node _T_3247 = eq(UInt<4>(0h8), idx_25)
when _T_3247 :
node _T_3248 = shl(UInt<5>(0h19), 3)
node _T_3249 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3248)
node _T_3250 = bits(_T_3249, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_3250
node _T_3251 = eq(UInt<4>(0h9), idx_25)
when _T_3251 :
node _T_3252 = shl(UInt<5>(0h19), 3)
node _T_3253 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3252)
node _T_3254 = bits(_T_3253, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_3254
node _T_3255 = eq(UInt<4>(0ha), idx_25)
when _T_3255 :
node _T_3256 = shl(UInt<5>(0h19), 3)
node _T_3257 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3256)
node _T_3258 = bits(_T_3257, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_3258
node _T_3259 = eq(UInt<4>(0hb), idx_25)
when _T_3259 :
node _T_3260 = shl(UInt<5>(0h19), 3)
node _T_3261 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3260)
node _T_3262 = bits(_T_3261, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_3262
node _T_3263 = eq(UInt<4>(0hc), idx_25)
when _T_3263 :
node _T_3264 = shl(UInt<5>(0h19), 3)
node _T_3265 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3264)
node _T_3266 = bits(_T_3265, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_3266
node _T_3267 = eq(UInt<4>(0hd), idx_25)
when _T_3267 :
node _T_3268 = shl(UInt<5>(0h19), 3)
node _T_3269 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3268)
node _T_3270 = bits(_T_3269, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_3270
node _T_3271 = eq(UInt<4>(0he), idx_25)
when _T_3271 :
node _T_3272 = shl(UInt<5>(0h19), 3)
node _T_3273 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3272)
node _T_3274 = bits(_T_3273, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_3274
node _T_3275 = eq(UInt<4>(0hf), idx_25)
when _T_3275 :
node _T_3276 = shl(UInt<5>(0h19), 3)
node _T_3277 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3276)
node _T_3278 = bits(_T_3277, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_3278
node _T_3279 = eq(UInt<5>(0h10), idx_25)
when _T_3279 :
node _T_3280 = shl(UInt<5>(0h19), 3)
node _T_3281 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3280)
node _T_3282 = bits(_T_3281, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_3282
node _T_3283 = eq(UInt<5>(0h11), idx_25)
when _T_3283 :
node _T_3284 = shl(UInt<5>(0h19), 3)
node _T_3285 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3284)
node _T_3286 = bits(_T_3285, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_3286
node _T_3287 = eq(UInt<5>(0h12), idx_25)
when _T_3287 :
node _T_3288 = shl(UInt<5>(0h19), 3)
node _T_3289 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3288)
node _T_3290 = bits(_T_3289, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_3290
node _T_3291 = eq(UInt<5>(0h13), idx_25)
when _T_3291 :
node _T_3292 = shl(UInt<5>(0h19), 3)
node _T_3293 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3292)
node _T_3294 = bits(_T_3293, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_3294
node _T_3295 = eq(UInt<5>(0h14), idx_25)
when _T_3295 :
node _T_3296 = shl(UInt<5>(0h19), 3)
node _T_3297 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3296)
node _T_3298 = bits(_T_3297, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_3298
node _T_3299 = eq(UInt<5>(0h15), idx_25)
when _T_3299 :
node _T_3300 = shl(UInt<5>(0h19), 3)
node _T_3301 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3300)
node _T_3302 = bits(_T_3301, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_3302
node _T_3303 = eq(UInt<5>(0h16), idx_25)
when _T_3303 :
node _T_3304 = shl(UInt<5>(0h19), 3)
node _T_3305 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3304)
node _T_3306 = bits(_T_3305, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_3306
node _T_3307 = eq(UInt<5>(0h17), idx_25)
when _T_3307 :
node _T_3308 = shl(UInt<5>(0h19), 3)
node _T_3309 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3308)
node _T_3310 = bits(_T_3309, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_3310
node _T_3311 = eq(UInt<5>(0h18), idx_25)
when _T_3311 :
node _T_3312 = shl(UInt<5>(0h19), 3)
node _T_3313 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3312)
node _T_3314 = bits(_T_3313, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_3314
node _T_3315 = eq(UInt<5>(0h19), idx_25)
when _T_3315 :
node _T_3316 = shl(UInt<5>(0h19), 3)
node _T_3317 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3316)
node _T_3318 = bits(_T_3317, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_3318
node _T_3319 = eq(UInt<5>(0h1a), idx_25)
when _T_3319 :
node _T_3320 = shl(UInt<5>(0h19), 3)
node _T_3321 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3320)
node _T_3322 = bits(_T_3321, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_3322
node _T_3323 = eq(UInt<5>(0h1b), idx_25)
when _T_3323 :
node _T_3324 = shl(UInt<5>(0h19), 3)
node _T_3325 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3324)
node _T_3326 = bits(_T_3325, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_3326
node _T_3327 = eq(UInt<5>(0h1c), idx_25)
when _T_3327 :
node _T_3328 = shl(UInt<5>(0h19), 3)
node _T_3329 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3328)
node _T_3330 = bits(_T_3329, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_3330
node _T_3331 = eq(UInt<5>(0h1d), idx_25)
when _T_3331 :
node _T_3332 = shl(UInt<5>(0h19), 3)
node _T_3333 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3332)
node _T_3334 = bits(_T_3333, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_3334
node _T_3335 = eq(UInt<5>(0h1e), idx_25)
when _T_3335 :
node _T_3336 = shl(UInt<5>(0h19), 3)
node _T_3337 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3336)
node _T_3338 = bits(_T_3337, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_3338
node _T_3339 = eq(UInt<5>(0h1f), idx_25)
when _T_3339 :
node _T_3340 = shl(UInt<5>(0h19), 3)
node _T_3341 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3340)
node _T_3342 = bits(_T_3341, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_3342
node _idx_T_26 = add(write_start_index, UInt<5>(0h1a))
node idx_26 = rem(_idx_T_26, UInt<6>(0h20))
node _T_3343 = eq(UInt<1>(0h0), idx_26)
when _T_3343 :
node _T_3344 = shl(UInt<5>(0h1a), 3)
node _T_3345 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3344)
node _T_3346 = bits(_T_3345, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_3346
node _T_3347 = eq(UInt<1>(0h1), idx_26)
when _T_3347 :
node _T_3348 = shl(UInt<5>(0h1a), 3)
node _T_3349 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3348)
node _T_3350 = bits(_T_3349, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_3350
node _T_3351 = eq(UInt<2>(0h2), idx_26)
when _T_3351 :
node _T_3352 = shl(UInt<5>(0h1a), 3)
node _T_3353 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3352)
node _T_3354 = bits(_T_3353, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_3354
node _T_3355 = eq(UInt<2>(0h3), idx_26)
when _T_3355 :
node _T_3356 = shl(UInt<5>(0h1a), 3)
node _T_3357 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3356)
node _T_3358 = bits(_T_3357, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_3358
node _T_3359 = eq(UInt<3>(0h4), idx_26)
when _T_3359 :
node _T_3360 = shl(UInt<5>(0h1a), 3)
node _T_3361 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3360)
node _T_3362 = bits(_T_3361, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_3362
node _T_3363 = eq(UInt<3>(0h5), idx_26)
when _T_3363 :
node _T_3364 = shl(UInt<5>(0h1a), 3)
node _T_3365 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3364)
node _T_3366 = bits(_T_3365, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_3366
node _T_3367 = eq(UInt<3>(0h6), idx_26)
when _T_3367 :
node _T_3368 = shl(UInt<5>(0h1a), 3)
node _T_3369 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3368)
node _T_3370 = bits(_T_3369, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_3370
node _T_3371 = eq(UInt<3>(0h7), idx_26)
when _T_3371 :
node _T_3372 = shl(UInt<5>(0h1a), 3)
node _T_3373 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3372)
node _T_3374 = bits(_T_3373, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_3374
node _T_3375 = eq(UInt<4>(0h8), idx_26)
when _T_3375 :
node _T_3376 = shl(UInt<5>(0h1a), 3)
node _T_3377 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3376)
node _T_3378 = bits(_T_3377, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_3378
node _T_3379 = eq(UInt<4>(0h9), idx_26)
when _T_3379 :
node _T_3380 = shl(UInt<5>(0h1a), 3)
node _T_3381 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3380)
node _T_3382 = bits(_T_3381, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_3382
node _T_3383 = eq(UInt<4>(0ha), idx_26)
when _T_3383 :
node _T_3384 = shl(UInt<5>(0h1a), 3)
node _T_3385 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3384)
node _T_3386 = bits(_T_3385, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_3386
node _T_3387 = eq(UInt<4>(0hb), idx_26)
when _T_3387 :
node _T_3388 = shl(UInt<5>(0h1a), 3)
node _T_3389 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3388)
node _T_3390 = bits(_T_3389, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_3390
node _T_3391 = eq(UInt<4>(0hc), idx_26)
when _T_3391 :
node _T_3392 = shl(UInt<5>(0h1a), 3)
node _T_3393 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3392)
node _T_3394 = bits(_T_3393, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_3394
node _T_3395 = eq(UInt<4>(0hd), idx_26)
when _T_3395 :
node _T_3396 = shl(UInt<5>(0h1a), 3)
node _T_3397 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3396)
node _T_3398 = bits(_T_3397, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_3398
node _T_3399 = eq(UInt<4>(0he), idx_26)
when _T_3399 :
node _T_3400 = shl(UInt<5>(0h1a), 3)
node _T_3401 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3400)
node _T_3402 = bits(_T_3401, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_3402
node _T_3403 = eq(UInt<4>(0hf), idx_26)
when _T_3403 :
node _T_3404 = shl(UInt<5>(0h1a), 3)
node _T_3405 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3404)
node _T_3406 = bits(_T_3405, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_3406
node _T_3407 = eq(UInt<5>(0h10), idx_26)
when _T_3407 :
node _T_3408 = shl(UInt<5>(0h1a), 3)
node _T_3409 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3408)
node _T_3410 = bits(_T_3409, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_3410
node _T_3411 = eq(UInt<5>(0h11), idx_26)
when _T_3411 :
node _T_3412 = shl(UInt<5>(0h1a), 3)
node _T_3413 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3412)
node _T_3414 = bits(_T_3413, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_3414
node _T_3415 = eq(UInt<5>(0h12), idx_26)
when _T_3415 :
node _T_3416 = shl(UInt<5>(0h1a), 3)
node _T_3417 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3416)
node _T_3418 = bits(_T_3417, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_3418
node _T_3419 = eq(UInt<5>(0h13), idx_26)
when _T_3419 :
node _T_3420 = shl(UInt<5>(0h1a), 3)
node _T_3421 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3420)
node _T_3422 = bits(_T_3421, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_3422
node _T_3423 = eq(UInt<5>(0h14), idx_26)
when _T_3423 :
node _T_3424 = shl(UInt<5>(0h1a), 3)
node _T_3425 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3424)
node _T_3426 = bits(_T_3425, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_3426
node _T_3427 = eq(UInt<5>(0h15), idx_26)
when _T_3427 :
node _T_3428 = shl(UInt<5>(0h1a), 3)
node _T_3429 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3428)
node _T_3430 = bits(_T_3429, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_3430
node _T_3431 = eq(UInt<5>(0h16), idx_26)
when _T_3431 :
node _T_3432 = shl(UInt<5>(0h1a), 3)
node _T_3433 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3432)
node _T_3434 = bits(_T_3433, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_3434
node _T_3435 = eq(UInt<5>(0h17), idx_26)
when _T_3435 :
node _T_3436 = shl(UInt<5>(0h1a), 3)
node _T_3437 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3436)
node _T_3438 = bits(_T_3437, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_3438
node _T_3439 = eq(UInt<5>(0h18), idx_26)
when _T_3439 :
node _T_3440 = shl(UInt<5>(0h1a), 3)
node _T_3441 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3440)
node _T_3442 = bits(_T_3441, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_3442
node _T_3443 = eq(UInt<5>(0h19), idx_26)
when _T_3443 :
node _T_3444 = shl(UInt<5>(0h1a), 3)
node _T_3445 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3444)
node _T_3446 = bits(_T_3445, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_3446
node _T_3447 = eq(UInt<5>(0h1a), idx_26)
when _T_3447 :
node _T_3448 = shl(UInt<5>(0h1a), 3)
node _T_3449 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3448)
node _T_3450 = bits(_T_3449, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_3450
node _T_3451 = eq(UInt<5>(0h1b), idx_26)
when _T_3451 :
node _T_3452 = shl(UInt<5>(0h1a), 3)
node _T_3453 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3452)
node _T_3454 = bits(_T_3453, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_3454
node _T_3455 = eq(UInt<5>(0h1c), idx_26)
when _T_3455 :
node _T_3456 = shl(UInt<5>(0h1a), 3)
node _T_3457 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3456)
node _T_3458 = bits(_T_3457, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_3458
node _T_3459 = eq(UInt<5>(0h1d), idx_26)
when _T_3459 :
node _T_3460 = shl(UInt<5>(0h1a), 3)
node _T_3461 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3460)
node _T_3462 = bits(_T_3461, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_3462
node _T_3463 = eq(UInt<5>(0h1e), idx_26)
when _T_3463 :
node _T_3464 = shl(UInt<5>(0h1a), 3)
node _T_3465 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3464)
node _T_3466 = bits(_T_3465, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_3466
node _T_3467 = eq(UInt<5>(0h1f), idx_26)
when _T_3467 :
node _T_3468 = shl(UInt<5>(0h1a), 3)
node _T_3469 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3468)
node _T_3470 = bits(_T_3469, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_3470
node _idx_T_27 = add(write_start_index, UInt<5>(0h1b))
node idx_27 = rem(_idx_T_27, UInt<6>(0h20))
node _T_3471 = eq(UInt<1>(0h0), idx_27)
when _T_3471 :
node _T_3472 = shl(UInt<5>(0h1b), 3)
node _T_3473 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3472)
node _T_3474 = bits(_T_3473, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_3474
node _T_3475 = eq(UInt<1>(0h1), idx_27)
when _T_3475 :
node _T_3476 = shl(UInt<5>(0h1b), 3)
node _T_3477 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3476)
node _T_3478 = bits(_T_3477, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_3478
node _T_3479 = eq(UInt<2>(0h2), idx_27)
when _T_3479 :
node _T_3480 = shl(UInt<5>(0h1b), 3)
node _T_3481 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3480)
node _T_3482 = bits(_T_3481, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_3482
node _T_3483 = eq(UInt<2>(0h3), idx_27)
when _T_3483 :
node _T_3484 = shl(UInt<5>(0h1b), 3)
node _T_3485 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3484)
node _T_3486 = bits(_T_3485, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_3486
node _T_3487 = eq(UInt<3>(0h4), idx_27)
when _T_3487 :
node _T_3488 = shl(UInt<5>(0h1b), 3)
node _T_3489 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3488)
node _T_3490 = bits(_T_3489, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_3490
node _T_3491 = eq(UInt<3>(0h5), idx_27)
when _T_3491 :
node _T_3492 = shl(UInt<5>(0h1b), 3)
node _T_3493 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3492)
node _T_3494 = bits(_T_3493, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_3494
node _T_3495 = eq(UInt<3>(0h6), idx_27)
when _T_3495 :
node _T_3496 = shl(UInt<5>(0h1b), 3)
node _T_3497 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3496)
node _T_3498 = bits(_T_3497, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_3498
node _T_3499 = eq(UInt<3>(0h7), idx_27)
when _T_3499 :
node _T_3500 = shl(UInt<5>(0h1b), 3)
node _T_3501 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3500)
node _T_3502 = bits(_T_3501, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_3502
node _T_3503 = eq(UInt<4>(0h8), idx_27)
when _T_3503 :
node _T_3504 = shl(UInt<5>(0h1b), 3)
node _T_3505 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3504)
node _T_3506 = bits(_T_3505, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_3506
node _T_3507 = eq(UInt<4>(0h9), idx_27)
when _T_3507 :
node _T_3508 = shl(UInt<5>(0h1b), 3)
node _T_3509 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3508)
node _T_3510 = bits(_T_3509, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_3510
node _T_3511 = eq(UInt<4>(0ha), idx_27)
when _T_3511 :
node _T_3512 = shl(UInt<5>(0h1b), 3)
node _T_3513 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3512)
node _T_3514 = bits(_T_3513, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_3514
node _T_3515 = eq(UInt<4>(0hb), idx_27)
when _T_3515 :
node _T_3516 = shl(UInt<5>(0h1b), 3)
node _T_3517 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3516)
node _T_3518 = bits(_T_3517, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_3518
node _T_3519 = eq(UInt<4>(0hc), idx_27)
when _T_3519 :
node _T_3520 = shl(UInt<5>(0h1b), 3)
node _T_3521 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3520)
node _T_3522 = bits(_T_3521, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_3522
node _T_3523 = eq(UInt<4>(0hd), idx_27)
when _T_3523 :
node _T_3524 = shl(UInt<5>(0h1b), 3)
node _T_3525 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3524)
node _T_3526 = bits(_T_3525, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_3526
node _T_3527 = eq(UInt<4>(0he), idx_27)
when _T_3527 :
node _T_3528 = shl(UInt<5>(0h1b), 3)
node _T_3529 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3528)
node _T_3530 = bits(_T_3529, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_3530
node _T_3531 = eq(UInt<4>(0hf), idx_27)
when _T_3531 :
node _T_3532 = shl(UInt<5>(0h1b), 3)
node _T_3533 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3532)
node _T_3534 = bits(_T_3533, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_3534
node _T_3535 = eq(UInt<5>(0h10), idx_27)
when _T_3535 :
node _T_3536 = shl(UInt<5>(0h1b), 3)
node _T_3537 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3536)
node _T_3538 = bits(_T_3537, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_3538
node _T_3539 = eq(UInt<5>(0h11), idx_27)
when _T_3539 :
node _T_3540 = shl(UInt<5>(0h1b), 3)
node _T_3541 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3540)
node _T_3542 = bits(_T_3541, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_3542
node _T_3543 = eq(UInt<5>(0h12), idx_27)
when _T_3543 :
node _T_3544 = shl(UInt<5>(0h1b), 3)
node _T_3545 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3544)
node _T_3546 = bits(_T_3545, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_3546
node _T_3547 = eq(UInt<5>(0h13), idx_27)
when _T_3547 :
node _T_3548 = shl(UInt<5>(0h1b), 3)
node _T_3549 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3548)
node _T_3550 = bits(_T_3549, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_3550
node _T_3551 = eq(UInt<5>(0h14), idx_27)
when _T_3551 :
node _T_3552 = shl(UInt<5>(0h1b), 3)
node _T_3553 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3552)
node _T_3554 = bits(_T_3553, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_3554
node _T_3555 = eq(UInt<5>(0h15), idx_27)
when _T_3555 :
node _T_3556 = shl(UInt<5>(0h1b), 3)
node _T_3557 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3556)
node _T_3558 = bits(_T_3557, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_3558
node _T_3559 = eq(UInt<5>(0h16), idx_27)
when _T_3559 :
node _T_3560 = shl(UInt<5>(0h1b), 3)
node _T_3561 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3560)
node _T_3562 = bits(_T_3561, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_3562
node _T_3563 = eq(UInt<5>(0h17), idx_27)
when _T_3563 :
node _T_3564 = shl(UInt<5>(0h1b), 3)
node _T_3565 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3564)
node _T_3566 = bits(_T_3565, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_3566
node _T_3567 = eq(UInt<5>(0h18), idx_27)
when _T_3567 :
node _T_3568 = shl(UInt<5>(0h1b), 3)
node _T_3569 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3568)
node _T_3570 = bits(_T_3569, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_3570
node _T_3571 = eq(UInt<5>(0h19), idx_27)
when _T_3571 :
node _T_3572 = shl(UInt<5>(0h1b), 3)
node _T_3573 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3572)
node _T_3574 = bits(_T_3573, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_3574
node _T_3575 = eq(UInt<5>(0h1a), idx_27)
when _T_3575 :
node _T_3576 = shl(UInt<5>(0h1b), 3)
node _T_3577 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3576)
node _T_3578 = bits(_T_3577, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_3578
node _T_3579 = eq(UInt<5>(0h1b), idx_27)
when _T_3579 :
node _T_3580 = shl(UInt<5>(0h1b), 3)
node _T_3581 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3580)
node _T_3582 = bits(_T_3581, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_3582
node _T_3583 = eq(UInt<5>(0h1c), idx_27)
when _T_3583 :
node _T_3584 = shl(UInt<5>(0h1b), 3)
node _T_3585 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3584)
node _T_3586 = bits(_T_3585, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_3586
node _T_3587 = eq(UInt<5>(0h1d), idx_27)
when _T_3587 :
node _T_3588 = shl(UInt<5>(0h1b), 3)
node _T_3589 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3588)
node _T_3590 = bits(_T_3589, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_3590
node _T_3591 = eq(UInt<5>(0h1e), idx_27)
when _T_3591 :
node _T_3592 = shl(UInt<5>(0h1b), 3)
node _T_3593 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3592)
node _T_3594 = bits(_T_3593, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_3594
node _T_3595 = eq(UInt<5>(0h1f), idx_27)
when _T_3595 :
node _T_3596 = shl(UInt<5>(0h1b), 3)
node _T_3597 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3596)
node _T_3598 = bits(_T_3597, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_3598
node _idx_T_28 = add(write_start_index, UInt<5>(0h1c))
node idx_28 = rem(_idx_T_28, UInt<6>(0h20))
node _T_3599 = eq(UInt<1>(0h0), idx_28)
when _T_3599 :
node _T_3600 = shl(UInt<5>(0h1c), 3)
node _T_3601 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3600)
node _T_3602 = bits(_T_3601, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_3602
node _T_3603 = eq(UInt<1>(0h1), idx_28)
when _T_3603 :
node _T_3604 = shl(UInt<5>(0h1c), 3)
node _T_3605 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3604)
node _T_3606 = bits(_T_3605, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_3606
node _T_3607 = eq(UInt<2>(0h2), idx_28)
when _T_3607 :
node _T_3608 = shl(UInt<5>(0h1c), 3)
node _T_3609 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3608)
node _T_3610 = bits(_T_3609, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_3610
node _T_3611 = eq(UInt<2>(0h3), idx_28)
when _T_3611 :
node _T_3612 = shl(UInt<5>(0h1c), 3)
node _T_3613 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3612)
node _T_3614 = bits(_T_3613, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_3614
node _T_3615 = eq(UInt<3>(0h4), idx_28)
when _T_3615 :
node _T_3616 = shl(UInt<5>(0h1c), 3)
node _T_3617 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3616)
node _T_3618 = bits(_T_3617, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_3618
node _T_3619 = eq(UInt<3>(0h5), idx_28)
when _T_3619 :
node _T_3620 = shl(UInt<5>(0h1c), 3)
node _T_3621 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3620)
node _T_3622 = bits(_T_3621, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_3622
node _T_3623 = eq(UInt<3>(0h6), idx_28)
when _T_3623 :
node _T_3624 = shl(UInt<5>(0h1c), 3)
node _T_3625 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3624)
node _T_3626 = bits(_T_3625, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_3626
node _T_3627 = eq(UInt<3>(0h7), idx_28)
when _T_3627 :
node _T_3628 = shl(UInt<5>(0h1c), 3)
node _T_3629 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3628)
node _T_3630 = bits(_T_3629, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_3630
node _T_3631 = eq(UInt<4>(0h8), idx_28)
when _T_3631 :
node _T_3632 = shl(UInt<5>(0h1c), 3)
node _T_3633 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3632)
node _T_3634 = bits(_T_3633, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_3634
node _T_3635 = eq(UInt<4>(0h9), idx_28)
when _T_3635 :
node _T_3636 = shl(UInt<5>(0h1c), 3)
node _T_3637 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3636)
node _T_3638 = bits(_T_3637, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_3638
node _T_3639 = eq(UInt<4>(0ha), idx_28)
when _T_3639 :
node _T_3640 = shl(UInt<5>(0h1c), 3)
node _T_3641 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3640)
node _T_3642 = bits(_T_3641, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_3642
node _T_3643 = eq(UInt<4>(0hb), idx_28)
when _T_3643 :
node _T_3644 = shl(UInt<5>(0h1c), 3)
node _T_3645 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3644)
node _T_3646 = bits(_T_3645, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_3646
node _T_3647 = eq(UInt<4>(0hc), idx_28)
when _T_3647 :
node _T_3648 = shl(UInt<5>(0h1c), 3)
node _T_3649 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3648)
node _T_3650 = bits(_T_3649, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_3650
node _T_3651 = eq(UInt<4>(0hd), idx_28)
when _T_3651 :
node _T_3652 = shl(UInt<5>(0h1c), 3)
node _T_3653 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3652)
node _T_3654 = bits(_T_3653, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_3654
node _T_3655 = eq(UInt<4>(0he), idx_28)
when _T_3655 :
node _T_3656 = shl(UInt<5>(0h1c), 3)
node _T_3657 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3656)
node _T_3658 = bits(_T_3657, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_3658
node _T_3659 = eq(UInt<4>(0hf), idx_28)
when _T_3659 :
node _T_3660 = shl(UInt<5>(0h1c), 3)
node _T_3661 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3660)
node _T_3662 = bits(_T_3661, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_3662
node _T_3663 = eq(UInt<5>(0h10), idx_28)
when _T_3663 :
node _T_3664 = shl(UInt<5>(0h1c), 3)
node _T_3665 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3664)
node _T_3666 = bits(_T_3665, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_3666
node _T_3667 = eq(UInt<5>(0h11), idx_28)
when _T_3667 :
node _T_3668 = shl(UInt<5>(0h1c), 3)
node _T_3669 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3668)
node _T_3670 = bits(_T_3669, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_3670
node _T_3671 = eq(UInt<5>(0h12), idx_28)
when _T_3671 :
node _T_3672 = shl(UInt<5>(0h1c), 3)
node _T_3673 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3672)
node _T_3674 = bits(_T_3673, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_3674
node _T_3675 = eq(UInt<5>(0h13), idx_28)
when _T_3675 :
node _T_3676 = shl(UInt<5>(0h1c), 3)
node _T_3677 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3676)
node _T_3678 = bits(_T_3677, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_3678
node _T_3679 = eq(UInt<5>(0h14), idx_28)
when _T_3679 :
node _T_3680 = shl(UInt<5>(0h1c), 3)
node _T_3681 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3680)
node _T_3682 = bits(_T_3681, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_3682
node _T_3683 = eq(UInt<5>(0h15), idx_28)
when _T_3683 :
node _T_3684 = shl(UInt<5>(0h1c), 3)
node _T_3685 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3684)
node _T_3686 = bits(_T_3685, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_3686
node _T_3687 = eq(UInt<5>(0h16), idx_28)
when _T_3687 :
node _T_3688 = shl(UInt<5>(0h1c), 3)
node _T_3689 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3688)
node _T_3690 = bits(_T_3689, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_3690
node _T_3691 = eq(UInt<5>(0h17), idx_28)
when _T_3691 :
node _T_3692 = shl(UInt<5>(0h1c), 3)
node _T_3693 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3692)
node _T_3694 = bits(_T_3693, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_3694
node _T_3695 = eq(UInt<5>(0h18), idx_28)
when _T_3695 :
node _T_3696 = shl(UInt<5>(0h1c), 3)
node _T_3697 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3696)
node _T_3698 = bits(_T_3697, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_3698
node _T_3699 = eq(UInt<5>(0h19), idx_28)
when _T_3699 :
node _T_3700 = shl(UInt<5>(0h1c), 3)
node _T_3701 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3700)
node _T_3702 = bits(_T_3701, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_3702
node _T_3703 = eq(UInt<5>(0h1a), idx_28)
when _T_3703 :
node _T_3704 = shl(UInt<5>(0h1c), 3)
node _T_3705 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3704)
node _T_3706 = bits(_T_3705, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_3706
node _T_3707 = eq(UInt<5>(0h1b), idx_28)
when _T_3707 :
node _T_3708 = shl(UInt<5>(0h1c), 3)
node _T_3709 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3708)
node _T_3710 = bits(_T_3709, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_3710
node _T_3711 = eq(UInt<5>(0h1c), idx_28)
when _T_3711 :
node _T_3712 = shl(UInt<5>(0h1c), 3)
node _T_3713 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3712)
node _T_3714 = bits(_T_3713, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_3714
node _T_3715 = eq(UInt<5>(0h1d), idx_28)
when _T_3715 :
node _T_3716 = shl(UInt<5>(0h1c), 3)
node _T_3717 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3716)
node _T_3718 = bits(_T_3717, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_3718
node _T_3719 = eq(UInt<5>(0h1e), idx_28)
when _T_3719 :
node _T_3720 = shl(UInt<5>(0h1c), 3)
node _T_3721 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3720)
node _T_3722 = bits(_T_3721, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_3722
node _T_3723 = eq(UInt<5>(0h1f), idx_28)
when _T_3723 :
node _T_3724 = shl(UInt<5>(0h1c), 3)
node _T_3725 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3724)
node _T_3726 = bits(_T_3725, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_3726
node _idx_T_29 = add(write_start_index, UInt<5>(0h1d))
node idx_29 = rem(_idx_T_29, UInt<6>(0h20))
node _T_3727 = eq(UInt<1>(0h0), idx_29)
when _T_3727 :
node _T_3728 = shl(UInt<5>(0h1d), 3)
node _T_3729 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3728)
node _T_3730 = bits(_T_3729, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_3730
node _T_3731 = eq(UInt<1>(0h1), idx_29)
when _T_3731 :
node _T_3732 = shl(UInt<5>(0h1d), 3)
node _T_3733 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3732)
node _T_3734 = bits(_T_3733, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_3734
node _T_3735 = eq(UInt<2>(0h2), idx_29)
when _T_3735 :
node _T_3736 = shl(UInt<5>(0h1d), 3)
node _T_3737 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3736)
node _T_3738 = bits(_T_3737, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_3738
node _T_3739 = eq(UInt<2>(0h3), idx_29)
when _T_3739 :
node _T_3740 = shl(UInt<5>(0h1d), 3)
node _T_3741 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3740)
node _T_3742 = bits(_T_3741, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_3742
node _T_3743 = eq(UInt<3>(0h4), idx_29)
when _T_3743 :
node _T_3744 = shl(UInt<5>(0h1d), 3)
node _T_3745 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3744)
node _T_3746 = bits(_T_3745, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_3746
node _T_3747 = eq(UInt<3>(0h5), idx_29)
when _T_3747 :
node _T_3748 = shl(UInt<5>(0h1d), 3)
node _T_3749 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3748)
node _T_3750 = bits(_T_3749, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_3750
node _T_3751 = eq(UInt<3>(0h6), idx_29)
when _T_3751 :
node _T_3752 = shl(UInt<5>(0h1d), 3)
node _T_3753 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3752)
node _T_3754 = bits(_T_3753, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_3754
node _T_3755 = eq(UInt<3>(0h7), idx_29)
when _T_3755 :
node _T_3756 = shl(UInt<5>(0h1d), 3)
node _T_3757 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3756)
node _T_3758 = bits(_T_3757, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_3758
node _T_3759 = eq(UInt<4>(0h8), idx_29)
when _T_3759 :
node _T_3760 = shl(UInt<5>(0h1d), 3)
node _T_3761 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3760)
node _T_3762 = bits(_T_3761, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_3762
node _T_3763 = eq(UInt<4>(0h9), idx_29)
when _T_3763 :
node _T_3764 = shl(UInt<5>(0h1d), 3)
node _T_3765 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3764)
node _T_3766 = bits(_T_3765, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_3766
node _T_3767 = eq(UInt<4>(0ha), idx_29)
when _T_3767 :
node _T_3768 = shl(UInt<5>(0h1d), 3)
node _T_3769 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3768)
node _T_3770 = bits(_T_3769, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_3770
node _T_3771 = eq(UInt<4>(0hb), idx_29)
when _T_3771 :
node _T_3772 = shl(UInt<5>(0h1d), 3)
node _T_3773 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3772)
node _T_3774 = bits(_T_3773, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_3774
node _T_3775 = eq(UInt<4>(0hc), idx_29)
when _T_3775 :
node _T_3776 = shl(UInt<5>(0h1d), 3)
node _T_3777 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3776)
node _T_3778 = bits(_T_3777, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_3778
node _T_3779 = eq(UInt<4>(0hd), idx_29)
when _T_3779 :
node _T_3780 = shl(UInt<5>(0h1d), 3)
node _T_3781 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3780)
node _T_3782 = bits(_T_3781, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_3782
node _T_3783 = eq(UInt<4>(0he), idx_29)
when _T_3783 :
node _T_3784 = shl(UInt<5>(0h1d), 3)
node _T_3785 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3784)
node _T_3786 = bits(_T_3785, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_3786
node _T_3787 = eq(UInt<4>(0hf), idx_29)
when _T_3787 :
node _T_3788 = shl(UInt<5>(0h1d), 3)
node _T_3789 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3788)
node _T_3790 = bits(_T_3789, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_3790
node _T_3791 = eq(UInt<5>(0h10), idx_29)
when _T_3791 :
node _T_3792 = shl(UInt<5>(0h1d), 3)
node _T_3793 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3792)
node _T_3794 = bits(_T_3793, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_3794
node _T_3795 = eq(UInt<5>(0h11), idx_29)
when _T_3795 :
node _T_3796 = shl(UInt<5>(0h1d), 3)
node _T_3797 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3796)
node _T_3798 = bits(_T_3797, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_3798
node _T_3799 = eq(UInt<5>(0h12), idx_29)
when _T_3799 :
node _T_3800 = shl(UInt<5>(0h1d), 3)
node _T_3801 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3800)
node _T_3802 = bits(_T_3801, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_3802
node _T_3803 = eq(UInt<5>(0h13), idx_29)
when _T_3803 :
node _T_3804 = shl(UInt<5>(0h1d), 3)
node _T_3805 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3804)
node _T_3806 = bits(_T_3805, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_3806
node _T_3807 = eq(UInt<5>(0h14), idx_29)
when _T_3807 :
node _T_3808 = shl(UInt<5>(0h1d), 3)
node _T_3809 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3808)
node _T_3810 = bits(_T_3809, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_3810
node _T_3811 = eq(UInt<5>(0h15), idx_29)
when _T_3811 :
node _T_3812 = shl(UInt<5>(0h1d), 3)
node _T_3813 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3812)
node _T_3814 = bits(_T_3813, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_3814
node _T_3815 = eq(UInt<5>(0h16), idx_29)
when _T_3815 :
node _T_3816 = shl(UInt<5>(0h1d), 3)
node _T_3817 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3816)
node _T_3818 = bits(_T_3817, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_3818
node _T_3819 = eq(UInt<5>(0h17), idx_29)
when _T_3819 :
node _T_3820 = shl(UInt<5>(0h1d), 3)
node _T_3821 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3820)
node _T_3822 = bits(_T_3821, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_3822
node _T_3823 = eq(UInt<5>(0h18), idx_29)
when _T_3823 :
node _T_3824 = shl(UInt<5>(0h1d), 3)
node _T_3825 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3824)
node _T_3826 = bits(_T_3825, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_3826
node _T_3827 = eq(UInt<5>(0h19), idx_29)
when _T_3827 :
node _T_3828 = shl(UInt<5>(0h1d), 3)
node _T_3829 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3828)
node _T_3830 = bits(_T_3829, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_3830
node _T_3831 = eq(UInt<5>(0h1a), idx_29)
when _T_3831 :
node _T_3832 = shl(UInt<5>(0h1d), 3)
node _T_3833 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3832)
node _T_3834 = bits(_T_3833, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_3834
node _T_3835 = eq(UInt<5>(0h1b), idx_29)
when _T_3835 :
node _T_3836 = shl(UInt<5>(0h1d), 3)
node _T_3837 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3836)
node _T_3838 = bits(_T_3837, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_3838
node _T_3839 = eq(UInt<5>(0h1c), idx_29)
when _T_3839 :
node _T_3840 = shl(UInt<5>(0h1d), 3)
node _T_3841 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3840)
node _T_3842 = bits(_T_3841, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_3842
node _T_3843 = eq(UInt<5>(0h1d), idx_29)
when _T_3843 :
node _T_3844 = shl(UInt<5>(0h1d), 3)
node _T_3845 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3844)
node _T_3846 = bits(_T_3845, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_3846
node _T_3847 = eq(UInt<5>(0h1e), idx_29)
when _T_3847 :
node _T_3848 = shl(UInt<5>(0h1d), 3)
node _T_3849 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3848)
node _T_3850 = bits(_T_3849, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_3850
node _T_3851 = eq(UInt<5>(0h1f), idx_29)
when _T_3851 :
node _T_3852 = shl(UInt<5>(0h1d), 3)
node _T_3853 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3852)
node _T_3854 = bits(_T_3853, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_3854
node _idx_T_30 = add(write_start_index, UInt<5>(0h1e))
node idx_30 = rem(_idx_T_30, UInt<6>(0h20))
node _T_3855 = eq(UInt<1>(0h0), idx_30)
when _T_3855 :
node _T_3856 = shl(UInt<5>(0h1e), 3)
node _T_3857 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3856)
node _T_3858 = bits(_T_3857, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_3858
node _T_3859 = eq(UInt<1>(0h1), idx_30)
when _T_3859 :
node _T_3860 = shl(UInt<5>(0h1e), 3)
node _T_3861 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3860)
node _T_3862 = bits(_T_3861, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_3862
node _T_3863 = eq(UInt<2>(0h2), idx_30)
when _T_3863 :
node _T_3864 = shl(UInt<5>(0h1e), 3)
node _T_3865 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3864)
node _T_3866 = bits(_T_3865, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_3866
node _T_3867 = eq(UInt<2>(0h3), idx_30)
when _T_3867 :
node _T_3868 = shl(UInt<5>(0h1e), 3)
node _T_3869 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3868)
node _T_3870 = bits(_T_3869, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_3870
node _T_3871 = eq(UInt<3>(0h4), idx_30)
when _T_3871 :
node _T_3872 = shl(UInt<5>(0h1e), 3)
node _T_3873 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3872)
node _T_3874 = bits(_T_3873, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_3874
node _T_3875 = eq(UInt<3>(0h5), idx_30)
when _T_3875 :
node _T_3876 = shl(UInt<5>(0h1e), 3)
node _T_3877 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3876)
node _T_3878 = bits(_T_3877, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_3878
node _T_3879 = eq(UInt<3>(0h6), idx_30)
when _T_3879 :
node _T_3880 = shl(UInt<5>(0h1e), 3)
node _T_3881 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3880)
node _T_3882 = bits(_T_3881, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_3882
node _T_3883 = eq(UInt<3>(0h7), idx_30)
when _T_3883 :
node _T_3884 = shl(UInt<5>(0h1e), 3)
node _T_3885 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3884)
node _T_3886 = bits(_T_3885, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_3886
node _T_3887 = eq(UInt<4>(0h8), idx_30)
when _T_3887 :
node _T_3888 = shl(UInt<5>(0h1e), 3)
node _T_3889 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3888)
node _T_3890 = bits(_T_3889, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_3890
node _T_3891 = eq(UInt<4>(0h9), idx_30)
when _T_3891 :
node _T_3892 = shl(UInt<5>(0h1e), 3)
node _T_3893 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3892)
node _T_3894 = bits(_T_3893, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_3894
node _T_3895 = eq(UInt<4>(0ha), idx_30)
when _T_3895 :
node _T_3896 = shl(UInt<5>(0h1e), 3)
node _T_3897 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3896)
node _T_3898 = bits(_T_3897, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_3898
node _T_3899 = eq(UInt<4>(0hb), idx_30)
when _T_3899 :
node _T_3900 = shl(UInt<5>(0h1e), 3)
node _T_3901 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3900)
node _T_3902 = bits(_T_3901, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_3902
node _T_3903 = eq(UInt<4>(0hc), idx_30)
when _T_3903 :
node _T_3904 = shl(UInt<5>(0h1e), 3)
node _T_3905 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3904)
node _T_3906 = bits(_T_3905, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_3906
node _T_3907 = eq(UInt<4>(0hd), idx_30)
when _T_3907 :
node _T_3908 = shl(UInt<5>(0h1e), 3)
node _T_3909 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3908)
node _T_3910 = bits(_T_3909, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_3910
node _T_3911 = eq(UInt<4>(0he), idx_30)
when _T_3911 :
node _T_3912 = shl(UInt<5>(0h1e), 3)
node _T_3913 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3912)
node _T_3914 = bits(_T_3913, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_3914
node _T_3915 = eq(UInt<4>(0hf), idx_30)
when _T_3915 :
node _T_3916 = shl(UInt<5>(0h1e), 3)
node _T_3917 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3916)
node _T_3918 = bits(_T_3917, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_3918
node _T_3919 = eq(UInt<5>(0h10), idx_30)
when _T_3919 :
node _T_3920 = shl(UInt<5>(0h1e), 3)
node _T_3921 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3920)
node _T_3922 = bits(_T_3921, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_3922
node _T_3923 = eq(UInt<5>(0h11), idx_30)
when _T_3923 :
node _T_3924 = shl(UInt<5>(0h1e), 3)
node _T_3925 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3924)
node _T_3926 = bits(_T_3925, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_3926
node _T_3927 = eq(UInt<5>(0h12), idx_30)
when _T_3927 :
node _T_3928 = shl(UInt<5>(0h1e), 3)
node _T_3929 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3928)
node _T_3930 = bits(_T_3929, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_3930
node _T_3931 = eq(UInt<5>(0h13), idx_30)
when _T_3931 :
node _T_3932 = shl(UInt<5>(0h1e), 3)
node _T_3933 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3932)
node _T_3934 = bits(_T_3933, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_3934
node _T_3935 = eq(UInt<5>(0h14), idx_30)
when _T_3935 :
node _T_3936 = shl(UInt<5>(0h1e), 3)
node _T_3937 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3936)
node _T_3938 = bits(_T_3937, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_3938
node _T_3939 = eq(UInt<5>(0h15), idx_30)
when _T_3939 :
node _T_3940 = shl(UInt<5>(0h1e), 3)
node _T_3941 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3940)
node _T_3942 = bits(_T_3941, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_3942
node _T_3943 = eq(UInt<5>(0h16), idx_30)
when _T_3943 :
node _T_3944 = shl(UInt<5>(0h1e), 3)
node _T_3945 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3944)
node _T_3946 = bits(_T_3945, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_3946
node _T_3947 = eq(UInt<5>(0h17), idx_30)
when _T_3947 :
node _T_3948 = shl(UInt<5>(0h1e), 3)
node _T_3949 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3948)
node _T_3950 = bits(_T_3949, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_3950
node _T_3951 = eq(UInt<5>(0h18), idx_30)
when _T_3951 :
node _T_3952 = shl(UInt<5>(0h1e), 3)
node _T_3953 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3952)
node _T_3954 = bits(_T_3953, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_3954
node _T_3955 = eq(UInt<5>(0h19), idx_30)
when _T_3955 :
node _T_3956 = shl(UInt<5>(0h1e), 3)
node _T_3957 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3956)
node _T_3958 = bits(_T_3957, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_3958
node _T_3959 = eq(UInt<5>(0h1a), idx_30)
when _T_3959 :
node _T_3960 = shl(UInt<5>(0h1e), 3)
node _T_3961 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3960)
node _T_3962 = bits(_T_3961, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_3962
node _T_3963 = eq(UInt<5>(0h1b), idx_30)
when _T_3963 :
node _T_3964 = shl(UInt<5>(0h1e), 3)
node _T_3965 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3964)
node _T_3966 = bits(_T_3965, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_3966
node _T_3967 = eq(UInt<5>(0h1c), idx_30)
when _T_3967 :
node _T_3968 = shl(UInt<5>(0h1e), 3)
node _T_3969 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3968)
node _T_3970 = bits(_T_3969, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_3970
node _T_3971 = eq(UInt<5>(0h1d), idx_30)
when _T_3971 :
node _T_3972 = shl(UInt<5>(0h1e), 3)
node _T_3973 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3972)
node _T_3974 = bits(_T_3973, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_3974
node _T_3975 = eq(UInt<5>(0h1e), idx_30)
when _T_3975 :
node _T_3976 = shl(UInt<5>(0h1e), 3)
node _T_3977 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3976)
node _T_3978 = bits(_T_3977, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_3978
node _T_3979 = eq(UInt<5>(0h1f), idx_30)
when _T_3979 :
node _T_3980 = shl(UInt<5>(0h1e), 3)
node _T_3981 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3980)
node _T_3982 = bits(_T_3981, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_3982
node _idx_T_31 = add(write_start_index, UInt<5>(0h1f))
node idx_31 = rem(_idx_T_31, UInt<6>(0h20))
node _T_3983 = eq(UInt<1>(0h0), idx_31)
when _T_3983 :
node _T_3984 = shl(UInt<5>(0h1f), 3)
node _T_3985 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3984)
node _T_3986 = bits(_T_3985, 7, 0)
connect Queue2_UInt8.io.enq.bits, _T_3986
node _T_3987 = eq(UInt<1>(0h1), idx_31)
when _T_3987 :
node _T_3988 = shl(UInt<5>(0h1f), 3)
node _T_3989 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3988)
node _T_3990 = bits(_T_3989, 7, 0)
connect Queue2_UInt8_1.io.enq.bits, _T_3990
node _T_3991 = eq(UInt<2>(0h2), idx_31)
when _T_3991 :
node _T_3992 = shl(UInt<5>(0h1f), 3)
node _T_3993 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3992)
node _T_3994 = bits(_T_3993, 7, 0)
connect Queue2_UInt8_2.io.enq.bits, _T_3994
node _T_3995 = eq(UInt<2>(0h3), idx_31)
when _T_3995 :
node _T_3996 = shl(UInt<5>(0h1f), 3)
node _T_3997 = dshr(incoming_writes_Q.io.deq.bits.data, _T_3996)
node _T_3998 = bits(_T_3997, 7, 0)
connect Queue2_UInt8_3.io.enq.bits, _T_3998
node _T_3999 = eq(UInt<3>(0h4), idx_31)
when _T_3999 :
node _T_4000 = shl(UInt<5>(0h1f), 3)
node _T_4001 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4000)
node _T_4002 = bits(_T_4001, 7, 0)
connect Queue2_UInt8_4.io.enq.bits, _T_4002
node _T_4003 = eq(UInt<3>(0h5), idx_31)
when _T_4003 :
node _T_4004 = shl(UInt<5>(0h1f), 3)
node _T_4005 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4004)
node _T_4006 = bits(_T_4005, 7, 0)
connect Queue2_UInt8_5.io.enq.bits, _T_4006
node _T_4007 = eq(UInt<3>(0h6), idx_31)
when _T_4007 :
node _T_4008 = shl(UInt<5>(0h1f), 3)
node _T_4009 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4008)
node _T_4010 = bits(_T_4009, 7, 0)
connect Queue2_UInt8_6.io.enq.bits, _T_4010
node _T_4011 = eq(UInt<3>(0h7), idx_31)
when _T_4011 :
node _T_4012 = shl(UInt<5>(0h1f), 3)
node _T_4013 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4012)
node _T_4014 = bits(_T_4013, 7, 0)
connect Queue2_UInt8_7.io.enq.bits, _T_4014
node _T_4015 = eq(UInt<4>(0h8), idx_31)
when _T_4015 :
node _T_4016 = shl(UInt<5>(0h1f), 3)
node _T_4017 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4016)
node _T_4018 = bits(_T_4017, 7, 0)
connect Queue2_UInt8_8.io.enq.bits, _T_4018
node _T_4019 = eq(UInt<4>(0h9), idx_31)
when _T_4019 :
node _T_4020 = shl(UInt<5>(0h1f), 3)
node _T_4021 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4020)
node _T_4022 = bits(_T_4021, 7, 0)
connect Queue2_UInt8_9.io.enq.bits, _T_4022
node _T_4023 = eq(UInt<4>(0ha), idx_31)
when _T_4023 :
node _T_4024 = shl(UInt<5>(0h1f), 3)
node _T_4025 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4024)
node _T_4026 = bits(_T_4025, 7, 0)
connect Queue2_UInt8_10.io.enq.bits, _T_4026
node _T_4027 = eq(UInt<4>(0hb), idx_31)
when _T_4027 :
node _T_4028 = shl(UInt<5>(0h1f), 3)
node _T_4029 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4028)
node _T_4030 = bits(_T_4029, 7, 0)
connect Queue2_UInt8_11.io.enq.bits, _T_4030
node _T_4031 = eq(UInt<4>(0hc), idx_31)
when _T_4031 :
node _T_4032 = shl(UInt<5>(0h1f), 3)
node _T_4033 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4032)
node _T_4034 = bits(_T_4033, 7, 0)
connect Queue2_UInt8_12.io.enq.bits, _T_4034
node _T_4035 = eq(UInt<4>(0hd), idx_31)
when _T_4035 :
node _T_4036 = shl(UInt<5>(0h1f), 3)
node _T_4037 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4036)
node _T_4038 = bits(_T_4037, 7, 0)
connect Queue2_UInt8_13.io.enq.bits, _T_4038
node _T_4039 = eq(UInt<4>(0he), idx_31)
when _T_4039 :
node _T_4040 = shl(UInt<5>(0h1f), 3)
node _T_4041 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4040)
node _T_4042 = bits(_T_4041, 7, 0)
connect Queue2_UInt8_14.io.enq.bits, _T_4042
node _T_4043 = eq(UInt<4>(0hf), idx_31)
when _T_4043 :
node _T_4044 = shl(UInt<5>(0h1f), 3)
node _T_4045 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4044)
node _T_4046 = bits(_T_4045, 7, 0)
connect Queue2_UInt8_15.io.enq.bits, _T_4046
node _T_4047 = eq(UInt<5>(0h10), idx_31)
when _T_4047 :
node _T_4048 = shl(UInt<5>(0h1f), 3)
node _T_4049 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4048)
node _T_4050 = bits(_T_4049, 7, 0)
connect Queue2_UInt8_16.io.enq.bits, _T_4050
node _T_4051 = eq(UInt<5>(0h11), idx_31)
when _T_4051 :
node _T_4052 = shl(UInt<5>(0h1f), 3)
node _T_4053 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4052)
node _T_4054 = bits(_T_4053, 7, 0)
connect Queue2_UInt8_17.io.enq.bits, _T_4054
node _T_4055 = eq(UInt<5>(0h12), idx_31)
when _T_4055 :
node _T_4056 = shl(UInt<5>(0h1f), 3)
node _T_4057 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4056)
node _T_4058 = bits(_T_4057, 7, 0)
connect Queue2_UInt8_18.io.enq.bits, _T_4058
node _T_4059 = eq(UInt<5>(0h13), idx_31)
when _T_4059 :
node _T_4060 = shl(UInt<5>(0h1f), 3)
node _T_4061 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4060)
node _T_4062 = bits(_T_4061, 7, 0)
connect Queue2_UInt8_19.io.enq.bits, _T_4062
node _T_4063 = eq(UInt<5>(0h14), idx_31)
when _T_4063 :
node _T_4064 = shl(UInt<5>(0h1f), 3)
node _T_4065 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4064)
node _T_4066 = bits(_T_4065, 7, 0)
connect Queue2_UInt8_20.io.enq.bits, _T_4066
node _T_4067 = eq(UInt<5>(0h15), idx_31)
when _T_4067 :
node _T_4068 = shl(UInt<5>(0h1f), 3)
node _T_4069 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4068)
node _T_4070 = bits(_T_4069, 7, 0)
connect Queue2_UInt8_21.io.enq.bits, _T_4070
node _T_4071 = eq(UInt<5>(0h16), idx_31)
when _T_4071 :
node _T_4072 = shl(UInt<5>(0h1f), 3)
node _T_4073 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4072)
node _T_4074 = bits(_T_4073, 7, 0)
connect Queue2_UInt8_22.io.enq.bits, _T_4074
node _T_4075 = eq(UInt<5>(0h17), idx_31)
when _T_4075 :
node _T_4076 = shl(UInt<5>(0h1f), 3)
node _T_4077 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4076)
node _T_4078 = bits(_T_4077, 7, 0)
connect Queue2_UInt8_23.io.enq.bits, _T_4078
node _T_4079 = eq(UInt<5>(0h18), idx_31)
when _T_4079 :
node _T_4080 = shl(UInt<5>(0h1f), 3)
node _T_4081 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4080)
node _T_4082 = bits(_T_4081, 7, 0)
connect Queue2_UInt8_24.io.enq.bits, _T_4082
node _T_4083 = eq(UInt<5>(0h19), idx_31)
when _T_4083 :
node _T_4084 = shl(UInt<5>(0h1f), 3)
node _T_4085 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4084)
node _T_4086 = bits(_T_4085, 7, 0)
connect Queue2_UInt8_25.io.enq.bits, _T_4086
node _T_4087 = eq(UInt<5>(0h1a), idx_31)
when _T_4087 :
node _T_4088 = shl(UInt<5>(0h1f), 3)
node _T_4089 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4088)
node _T_4090 = bits(_T_4089, 7, 0)
connect Queue2_UInt8_26.io.enq.bits, _T_4090
node _T_4091 = eq(UInt<5>(0h1b), idx_31)
when _T_4091 :
node _T_4092 = shl(UInt<5>(0h1f), 3)
node _T_4093 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4092)
node _T_4094 = bits(_T_4093, 7, 0)
connect Queue2_UInt8_27.io.enq.bits, _T_4094
node _T_4095 = eq(UInt<5>(0h1c), idx_31)
when _T_4095 :
node _T_4096 = shl(UInt<5>(0h1f), 3)
node _T_4097 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4096)
node _T_4098 = bits(_T_4097, 7, 0)
connect Queue2_UInt8_28.io.enq.bits, _T_4098
node _T_4099 = eq(UInt<5>(0h1d), idx_31)
when _T_4099 :
node _T_4100 = shl(UInt<5>(0h1f), 3)
node _T_4101 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4100)
node _T_4102 = bits(_T_4101, 7, 0)
connect Queue2_UInt8_29.io.enq.bits, _T_4102
node _T_4103 = eq(UInt<5>(0h1e), idx_31)
when _T_4103 :
node _T_4104 = shl(UInt<5>(0h1f), 3)
node _T_4105 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4104)
node _T_4106 = bits(_T_4105, 7, 0)
connect Queue2_UInt8_30.io.enq.bits, _T_4106
node _T_4107 = eq(UInt<5>(0h1f), idx_31)
when _T_4107 :
node _T_4108 = shl(UInt<5>(0h1f), 3)
node _T_4109 = dshr(incoming_writes_Q.io.deq.bits.data, _T_4108)
node _T_4110 = bits(_T_4109, 7, 0)
connect Queue2_UInt8_31.io.enq.bits, _T_4110
node wrap_len_index_wide = add(write_start_index, incoming_writes_Q.io.deq.bits.validbytes)
node wrap_len_index_end = rem(wrap_len_index_wide, UInt<6>(0h20))
node wrapped = geq(wrap_len_index_wide, UInt<6>(0h20))
node _all_queues_ready_T = and(Queue2_UInt8.io.enq.ready, Queue2_UInt8_1.io.enq.ready)
node _all_queues_ready_T_1 = and(_all_queues_ready_T, Queue2_UInt8_2.io.enq.ready)
node _all_queues_ready_T_2 = and(_all_queues_ready_T_1, Queue2_UInt8_3.io.enq.ready)
node _all_queues_ready_T_3 = and(_all_queues_ready_T_2, Queue2_UInt8_4.io.enq.ready)
node _all_queues_ready_T_4 = and(_all_queues_ready_T_3, Queue2_UInt8_5.io.enq.ready)
node _all_queues_ready_T_5 = and(_all_queues_ready_T_4, Queue2_UInt8_6.io.enq.ready)
node _all_queues_ready_T_6 = and(_all_queues_ready_T_5, Queue2_UInt8_7.io.enq.ready)
node _all_queues_ready_T_7 = and(_all_queues_ready_T_6, Queue2_UInt8_8.io.enq.ready)
node _all_queues_ready_T_8 = and(_all_queues_ready_T_7, Queue2_UInt8_9.io.enq.ready)
node _all_queues_ready_T_9 = and(_all_queues_ready_T_8, Queue2_UInt8_10.io.enq.ready)
node _all_queues_ready_T_10 = and(_all_queues_ready_T_9, Queue2_UInt8_11.io.enq.ready)
node _all_queues_ready_T_11 = and(_all_queues_ready_T_10, Queue2_UInt8_12.io.enq.ready)
node _all_queues_ready_T_12 = and(_all_queues_ready_T_11, Queue2_UInt8_13.io.enq.ready)
node _all_queues_ready_T_13 = and(_all_queues_ready_T_12, Queue2_UInt8_14.io.enq.ready)
node _all_queues_ready_T_14 = and(_all_queues_ready_T_13, Queue2_UInt8_15.io.enq.ready)
node _all_queues_ready_T_15 = and(_all_queues_ready_T_14, Queue2_UInt8_16.io.enq.ready)
node _all_queues_ready_T_16 = and(_all_queues_ready_T_15, Queue2_UInt8_17.io.enq.ready)
node _all_queues_ready_T_17 = and(_all_queues_ready_T_16, Queue2_UInt8_18.io.enq.ready)
node _all_queues_ready_T_18 = and(_all_queues_ready_T_17, Queue2_UInt8_19.io.enq.ready)
node _all_queues_ready_T_19 = and(_all_queues_ready_T_18, Queue2_UInt8_20.io.enq.ready)
node _all_queues_ready_T_20 = and(_all_queues_ready_T_19, Queue2_UInt8_21.io.enq.ready)
node _all_queues_ready_T_21 = and(_all_queues_ready_T_20, Queue2_UInt8_22.io.enq.ready)
node _all_queues_ready_T_22 = and(_all_queues_ready_T_21, Queue2_UInt8_23.io.enq.ready)
node _all_queues_ready_T_23 = and(_all_queues_ready_T_22, Queue2_UInt8_24.io.enq.ready)
node _all_queues_ready_T_24 = and(_all_queues_ready_T_23, Queue2_UInt8_25.io.enq.ready)
node _all_queues_ready_T_25 = and(_all_queues_ready_T_24, Queue2_UInt8_26.io.enq.ready)
node _all_queues_ready_T_26 = and(_all_queues_ready_T_25, Queue2_UInt8_27.io.enq.ready)
node _all_queues_ready_T_27 = and(_all_queues_ready_T_26, Queue2_UInt8_28.io.enq.ready)
node _all_queues_ready_T_28 = and(_all_queues_ready_T_27, Queue2_UInt8_29.io.enq.ready)
node _all_queues_ready_T_29 = and(_all_queues_ready_T_28, Queue2_UInt8_30.io.enq.ready)
node all_queues_ready = and(_all_queues_ready_T_29, Queue2_UInt8_31.io.enq.ready)
node _account_for_buf_lens_Q_T = eq(incoming_writes_Q.io.deq.bits.end_of_message, UInt<1>(0h0))
node _account_for_buf_lens_Q_T_1 = and(incoming_writes_Q.io.deq.bits.end_of_message, buf_lens_Q.io.enq.ready)
node account_for_buf_lens_Q = or(_account_for_buf_lens_Q_T, _account_for_buf_lens_Q_T_1)
node _buf_lens_Q_io_enq_valid_T = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _buf_lens_Q_io_enq_valid_T_1 = and(_buf_lens_Q_io_enq_valid_T, incoming_writes_Q.io.deq.bits.end_of_message)
connect buf_lens_Q.io.enq.valid, _buf_lens_Q_io_enq_valid_T_1
node _buf_lens_Q_io_enq_bits_T = add(buf_len_tracker, incoming_writes_Q.io.deq.bits.validbytes)
connect buf_lens_Q.io.enq.bits, _buf_lens_Q_io_enq_bits_T
node _incoming_writes_Q_io_deq_ready_T = and(all_queues_ready, account_for_buf_lens_Q)
connect incoming_writes_Q.io.deq.ready, _incoming_writes_Q_io_deq_ready_T
node _T_4111 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4112 = and(_T_4111, account_for_buf_lens_Q)
when _T_4112 :
connect write_start_index, wrap_len_index_end
node _use_this_queue_T = geq(UInt<1>(0h0), write_start_index)
node _use_this_queue_T_1 = lt(UInt<1>(0h0), wrap_len_index_end)
node _use_this_queue_T_2 = or(_use_this_queue_T, _use_this_queue_T_1)
node _use_this_queue_T_3 = geq(UInt<1>(0h0), write_start_index)
node _use_this_queue_T_4 = lt(UInt<1>(0h0), wrap_len_index_end)
node _use_this_queue_T_5 = and(_use_this_queue_T_3, _use_this_queue_T_4)
node use_this_queue = mux(wrapped, _use_this_queue_T_2, _use_this_queue_T_5)
node _T_4113 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4114 = and(_T_4113, account_for_buf_lens_Q)
node _T_4115 = and(_T_4114, use_this_queue)
connect Queue2_UInt8.io.enq.valid, _T_4115
node _use_this_queue_T_6 = geq(UInt<1>(0h1), write_start_index)
node _use_this_queue_T_7 = lt(UInt<1>(0h1), wrap_len_index_end)
node _use_this_queue_T_8 = or(_use_this_queue_T_6, _use_this_queue_T_7)
node _use_this_queue_T_9 = geq(UInt<1>(0h1), write_start_index)
node _use_this_queue_T_10 = lt(UInt<1>(0h1), wrap_len_index_end)
node _use_this_queue_T_11 = and(_use_this_queue_T_9, _use_this_queue_T_10)
node use_this_queue_1 = mux(wrapped, _use_this_queue_T_8, _use_this_queue_T_11)
node _T_4116 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4117 = and(_T_4116, account_for_buf_lens_Q)
node _T_4118 = and(_T_4117, use_this_queue_1)
connect Queue2_UInt8_1.io.enq.valid, _T_4118
node _use_this_queue_T_12 = geq(UInt<2>(0h2), write_start_index)
node _use_this_queue_T_13 = lt(UInt<2>(0h2), wrap_len_index_end)
node _use_this_queue_T_14 = or(_use_this_queue_T_12, _use_this_queue_T_13)
node _use_this_queue_T_15 = geq(UInt<2>(0h2), write_start_index)
node _use_this_queue_T_16 = lt(UInt<2>(0h2), wrap_len_index_end)
node _use_this_queue_T_17 = and(_use_this_queue_T_15, _use_this_queue_T_16)
node use_this_queue_2 = mux(wrapped, _use_this_queue_T_14, _use_this_queue_T_17)
node _T_4119 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4120 = and(_T_4119, account_for_buf_lens_Q)
node _T_4121 = and(_T_4120, use_this_queue_2)
connect Queue2_UInt8_2.io.enq.valid, _T_4121
node _use_this_queue_T_18 = geq(UInt<2>(0h3), write_start_index)
node _use_this_queue_T_19 = lt(UInt<2>(0h3), wrap_len_index_end)
node _use_this_queue_T_20 = or(_use_this_queue_T_18, _use_this_queue_T_19)
node _use_this_queue_T_21 = geq(UInt<2>(0h3), write_start_index)
node _use_this_queue_T_22 = lt(UInt<2>(0h3), wrap_len_index_end)
node _use_this_queue_T_23 = and(_use_this_queue_T_21, _use_this_queue_T_22)
node use_this_queue_3 = mux(wrapped, _use_this_queue_T_20, _use_this_queue_T_23)
node _T_4122 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4123 = and(_T_4122, account_for_buf_lens_Q)
node _T_4124 = and(_T_4123, use_this_queue_3)
connect Queue2_UInt8_3.io.enq.valid, _T_4124
node _use_this_queue_T_24 = geq(UInt<3>(0h4), write_start_index)
node _use_this_queue_T_25 = lt(UInt<3>(0h4), wrap_len_index_end)
node _use_this_queue_T_26 = or(_use_this_queue_T_24, _use_this_queue_T_25)
node _use_this_queue_T_27 = geq(UInt<3>(0h4), write_start_index)
node _use_this_queue_T_28 = lt(UInt<3>(0h4), wrap_len_index_end)
node _use_this_queue_T_29 = and(_use_this_queue_T_27, _use_this_queue_T_28)
node use_this_queue_4 = mux(wrapped, _use_this_queue_T_26, _use_this_queue_T_29)
node _T_4125 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4126 = and(_T_4125, account_for_buf_lens_Q)
node _T_4127 = and(_T_4126, use_this_queue_4)
connect Queue2_UInt8_4.io.enq.valid, _T_4127
node _use_this_queue_T_30 = geq(UInt<3>(0h5), write_start_index)
node _use_this_queue_T_31 = lt(UInt<3>(0h5), wrap_len_index_end)
node _use_this_queue_T_32 = or(_use_this_queue_T_30, _use_this_queue_T_31)
node _use_this_queue_T_33 = geq(UInt<3>(0h5), write_start_index)
node _use_this_queue_T_34 = lt(UInt<3>(0h5), wrap_len_index_end)
node _use_this_queue_T_35 = and(_use_this_queue_T_33, _use_this_queue_T_34)
node use_this_queue_5 = mux(wrapped, _use_this_queue_T_32, _use_this_queue_T_35)
node _T_4128 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4129 = and(_T_4128, account_for_buf_lens_Q)
node _T_4130 = and(_T_4129, use_this_queue_5)
connect Queue2_UInt8_5.io.enq.valid, _T_4130
node _use_this_queue_T_36 = geq(UInt<3>(0h6), write_start_index)
node _use_this_queue_T_37 = lt(UInt<3>(0h6), wrap_len_index_end)
node _use_this_queue_T_38 = or(_use_this_queue_T_36, _use_this_queue_T_37)
node _use_this_queue_T_39 = geq(UInt<3>(0h6), write_start_index)
node _use_this_queue_T_40 = lt(UInt<3>(0h6), wrap_len_index_end)
node _use_this_queue_T_41 = and(_use_this_queue_T_39, _use_this_queue_T_40)
node use_this_queue_6 = mux(wrapped, _use_this_queue_T_38, _use_this_queue_T_41)
node _T_4131 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4132 = and(_T_4131, account_for_buf_lens_Q)
node _T_4133 = and(_T_4132, use_this_queue_6)
connect Queue2_UInt8_6.io.enq.valid, _T_4133
node _use_this_queue_T_42 = geq(UInt<3>(0h7), write_start_index)
node _use_this_queue_T_43 = lt(UInt<3>(0h7), wrap_len_index_end)
node _use_this_queue_T_44 = or(_use_this_queue_T_42, _use_this_queue_T_43)
node _use_this_queue_T_45 = geq(UInt<3>(0h7), write_start_index)
node _use_this_queue_T_46 = lt(UInt<3>(0h7), wrap_len_index_end)
node _use_this_queue_T_47 = and(_use_this_queue_T_45, _use_this_queue_T_46)
node use_this_queue_7 = mux(wrapped, _use_this_queue_T_44, _use_this_queue_T_47)
node _T_4134 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4135 = and(_T_4134, account_for_buf_lens_Q)
node _T_4136 = and(_T_4135, use_this_queue_7)
connect Queue2_UInt8_7.io.enq.valid, _T_4136
node _use_this_queue_T_48 = geq(UInt<4>(0h8), write_start_index)
node _use_this_queue_T_49 = lt(UInt<4>(0h8), wrap_len_index_end)
node _use_this_queue_T_50 = or(_use_this_queue_T_48, _use_this_queue_T_49)
node _use_this_queue_T_51 = geq(UInt<4>(0h8), write_start_index)
node _use_this_queue_T_52 = lt(UInt<4>(0h8), wrap_len_index_end)
node _use_this_queue_T_53 = and(_use_this_queue_T_51, _use_this_queue_T_52)
node use_this_queue_8 = mux(wrapped, _use_this_queue_T_50, _use_this_queue_T_53)
node _T_4137 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4138 = and(_T_4137, account_for_buf_lens_Q)
node _T_4139 = and(_T_4138, use_this_queue_8)
connect Queue2_UInt8_8.io.enq.valid, _T_4139
node _use_this_queue_T_54 = geq(UInt<4>(0h9), write_start_index)
node _use_this_queue_T_55 = lt(UInt<4>(0h9), wrap_len_index_end)
node _use_this_queue_T_56 = or(_use_this_queue_T_54, _use_this_queue_T_55)
node _use_this_queue_T_57 = geq(UInt<4>(0h9), write_start_index)
node _use_this_queue_T_58 = lt(UInt<4>(0h9), wrap_len_index_end)
node _use_this_queue_T_59 = and(_use_this_queue_T_57, _use_this_queue_T_58)
node use_this_queue_9 = mux(wrapped, _use_this_queue_T_56, _use_this_queue_T_59)
node _T_4140 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4141 = and(_T_4140, account_for_buf_lens_Q)
node _T_4142 = and(_T_4141, use_this_queue_9)
connect Queue2_UInt8_9.io.enq.valid, _T_4142
node _use_this_queue_T_60 = geq(UInt<4>(0ha), write_start_index)
node _use_this_queue_T_61 = lt(UInt<4>(0ha), wrap_len_index_end)
node _use_this_queue_T_62 = or(_use_this_queue_T_60, _use_this_queue_T_61)
node _use_this_queue_T_63 = geq(UInt<4>(0ha), write_start_index)
node _use_this_queue_T_64 = lt(UInt<4>(0ha), wrap_len_index_end)
node _use_this_queue_T_65 = and(_use_this_queue_T_63, _use_this_queue_T_64)
node use_this_queue_10 = mux(wrapped, _use_this_queue_T_62, _use_this_queue_T_65)
node _T_4143 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4144 = and(_T_4143, account_for_buf_lens_Q)
node _T_4145 = and(_T_4144, use_this_queue_10)
connect Queue2_UInt8_10.io.enq.valid, _T_4145
node _use_this_queue_T_66 = geq(UInt<4>(0hb), write_start_index)
node _use_this_queue_T_67 = lt(UInt<4>(0hb), wrap_len_index_end)
node _use_this_queue_T_68 = or(_use_this_queue_T_66, _use_this_queue_T_67)
node _use_this_queue_T_69 = geq(UInt<4>(0hb), write_start_index)
node _use_this_queue_T_70 = lt(UInt<4>(0hb), wrap_len_index_end)
node _use_this_queue_T_71 = and(_use_this_queue_T_69, _use_this_queue_T_70)
node use_this_queue_11 = mux(wrapped, _use_this_queue_T_68, _use_this_queue_T_71)
node _T_4146 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4147 = and(_T_4146, account_for_buf_lens_Q)
node _T_4148 = and(_T_4147, use_this_queue_11)
connect Queue2_UInt8_11.io.enq.valid, _T_4148
node _use_this_queue_T_72 = geq(UInt<4>(0hc), write_start_index)
node _use_this_queue_T_73 = lt(UInt<4>(0hc), wrap_len_index_end)
node _use_this_queue_T_74 = or(_use_this_queue_T_72, _use_this_queue_T_73)
node _use_this_queue_T_75 = geq(UInt<4>(0hc), write_start_index)
node _use_this_queue_T_76 = lt(UInt<4>(0hc), wrap_len_index_end)
node _use_this_queue_T_77 = and(_use_this_queue_T_75, _use_this_queue_T_76)
node use_this_queue_12 = mux(wrapped, _use_this_queue_T_74, _use_this_queue_T_77)
node _T_4149 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4150 = and(_T_4149, account_for_buf_lens_Q)
node _T_4151 = and(_T_4150, use_this_queue_12)
connect Queue2_UInt8_12.io.enq.valid, _T_4151
node _use_this_queue_T_78 = geq(UInt<4>(0hd), write_start_index)
node _use_this_queue_T_79 = lt(UInt<4>(0hd), wrap_len_index_end)
node _use_this_queue_T_80 = or(_use_this_queue_T_78, _use_this_queue_T_79)
node _use_this_queue_T_81 = geq(UInt<4>(0hd), write_start_index)
node _use_this_queue_T_82 = lt(UInt<4>(0hd), wrap_len_index_end)
node _use_this_queue_T_83 = and(_use_this_queue_T_81, _use_this_queue_T_82)
node use_this_queue_13 = mux(wrapped, _use_this_queue_T_80, _use_this_queue_T_83)
node _T_4152 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4153 = and(_T_4152, account_for_buf_lens_Q)
node _T_4154 = and(_T_4153, use_this_queue_13)
connect Queue2_UInt8_13.io.enq.valid, _T_4154
node _use_this_queue_T_84 = geq(UInt<4>(0he), write_start_index)
node _use_this_queue_T_85 = lt(UInt<4>(0he), wrap_len_index_end)
node _use_this_queue_T_86 = or(_use_this_queue_T_84, _use_this_queue_T_85)
node _use_this_queue_T_87 = geq(UInt<4>(0he), write_start_index)
node _use_this_queue_T_88 = lt(UInt<4>(0he), wrap_len_index_end)
node _use_this_queue_T_89 = and(_use_this_queue_T_87, _use_this_queue_T_88)
node use_this_queue_14 = mux(wrapped, _use_this_queue_T_86, _use_this_queue_T_89)
node _T_4155 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4156 = and(_T_4155, account_for_buf_lens_Q)
node _T_4157 = and(_T_4156, use_this_queue_14)
connect Queue2_UInt8_14.io.enq.valid, _T_4157
node _use_this_queue_T_90 = geq(UInt<4>(0hf), write_start_index)
node _use_this_queue_T_91 = lt(UInt<4>(0hf), wrap_len_index_end)
node _use_this_queue_T_92 = or(_use_this_queue_T_90, _use_this_queue_T_91)
node _use_this_queue_T_93 = geq(UInt<4>(0hf), write_start_index)
node _use_this_queue_T_94 = lt(UInt<4>(0hf), wrap_len_index_end)
node _use_this_queue_T_95 = and(_use_this_queue_T_93, _use_this_queue_T_94)
node use_this_queue_15 = mux(wrapped, _use_this_queue_T_92, _use_this_queue_T_95)
node _T_4158 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4159 = and(_T_4158, account_for_buf_lens_Q)
node _T_4160 = and(_T_4159, use_this_queue_15)
connect Queue2_UInt8_15.io.enq.valid, _T_4160
node _use_this_queue_T_96 = geq(UInt<5>(0h10), write_start_index)
node _use_this_queue_T_97 = lt(UInt<5>(0h10), wrap_len_index_end)
node _use_this_queue_T_98 = or(_use_this_queue_T_96, _use_this_queue_T_97)
node _use_this_queue_T_99 = geq(UInt<5>(0h10), write_start_index)
node _use_this_queue_T_100 = lt(UInt<5>(0h10), wrap_len_index_end)
node _use_this_queue_T_101 = and(_use_this_queue_T_99, _use_this_queue_T_100)
node use_this_queue_16 = mux(wrapped, _use_this_queue_T_98, _use_this_queue_T_101)
node _T_4161 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4162 = and(_T_4161, account_for_buf_lens_Q)
node _T_4163 = and(_T_4162, use_this_queue_16)
connect Queue2_UInt8_16.io.enq.valid, _T_4163
node _use_this_queue_T_102 = geq(UInt<5>(0h11), write_start_index)
node _use_this_queue_T_103 = lt(UInt<5>(0h11), wrap_len_index_end)
node _use_this_queue_T_104 = or(_use_this_queue_T_102, _use_this_queue_T_103)
node _use_this_queue_T_105 = geq(UInt<5>(0h11), write_start_index)
node _use_this_queue_T_106 = lt(UInt<5>(0h11), wrap_len_index_end)
node _use_this_queue_T_107 = and(_use_this_queue_T_105, _use_this_queue_T_106)
node use_this_queue_17 = mux(wrapped, _use_this_queue_T_104, _use_this_queue_T_107)
node _T_4164 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4165 = and(_T_4164, account_for_buf_lens_Q)
node _T_4166 = and(_T_4165, use_this_queue_17)
connect Queue2_UInt8_17.io.enq.valid, _T_4166
node _use_this_queue_T_108 = geq(UInt<5>(0h12), write_start_index)
node _use_this_queue_T_109 = lt(UInt<5>(0h12), wrap_len_index_end)
node _use_this_queue_T_110 = or(_use_this_queue_T_108, _use_this_queue_T_109)
node _use_this_queue_T_111 = geq(UInt<5>(0h12), write_start_index)
node _use_this_queue_T_112 = lt(UInt<5>(0h12), wrap_len_index_end)
node _use_this_queue_T_113 = and(_use_this_queue_T_111, _use_this_queue_T_112)
node use_this_queue_18 = mux(wrapped, _use_this_queue_T_110, _use_this_queue_T_113)
node _T_4167 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4168 = and(_T_4167, account_for_buf_lens_Q)
node _T_4169 = and(_T_4168, use_this_queue_18)
connect Queue2_UInt8_18.io.enq.valid, _T_4169
node _use_this_queue_T_114 = geq(UInt<5>(0h13), write_start_index)
node _use_this_queue_T_115 = lt(UInt<5>(0h13), wrap_len_index_end)
node _use_this_queue_T_116 = or(_use_this_queue_T_114, _use_this_queue_T_115)
node _use_this_queue_T_117 = geq(UInt<5>(0h13), write_start_index)
node _use_this_queue_T_118 = lt(UInt<5>(0h13), wrap_len_index_end)
node _use_this_queue_T_119 = and(_use_this_queue_T_117, _use_this_queue_T_118)
node use_this_queue_19 = mux(wrapped, _use_this_queue_T_116, _use_this_queue_T_119)
node _T_4170 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4171 = and(_T_4170, account_for_buf_lens_Q)
node _T_4172 = and(_T_4171, use_this_queue_19)
connect Queue2_UInt8_19.io.enq.valid, _T_4172
node _use_this_queue_T_120 = geq(UInt<5>(0h14), write_start_index)
node _use_this_queue_T_121 = lt(UInt<5>(0h14), wrap_len_index_end)
node _use_this_queue_T_122 = or(_use_this_queue_T_120, _use_this_queue_T_121)
node _use_this_queue_T_123 = geq(UInt<5>(0h14), write_start_index)
node _use_this_queue_T_124 = lt(UInt<5>(0h14), wrap_len_index_end)
node _use_this_queue_T_125 = and(_use_this_queue_T_123, _use_this_queue_T_124)
node use_this_queue_20 = mux(wrapped, _use_this_queue_T_122, _use_this_queue_T_125)
node _T_4173 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4174 = and(_T_4173, account_for_buf_lens_Q)
node _T_4175 = and(_T_4174, use_this_queue_20)
connect Queue2_UInt8_20.io.enq.valid, _T_4175
node _use_this_queue_T_126 = geq(UInt<5>(0h15), write_start_index)
node _use_this_queue_T_127 = lt(UInt<5>(0h15), wrap_len_index_end)
node _use_this_queue_T_128 = or(_use_this_queue_T_126, _use_this_queue_T_127)
node _use_this_queue_T_129 = geq(UInt<5>(0h15), write_start_index)
node _use_this_queue_T_130 = lt(UInt<5>(0h15), wrap_len_index_end)
node _use_this_queue_T_131 = and(_use_this_queue_T_129, _use_this_queue_T_130)
node use_this_queue_21 = mux(wrapped, _use_this_queue_T_128, _use_this_queue_T_131)
node _T_4176 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4177 = and(_T_4176, account_for_buf_lens_Q)
node _T_4178 = and(_T_4177, use_this_queue_21)
connect Queue2_UInt8_21.io.enq.valid, _T_4178
node _use_this_queue_T_132 = geq(UInt<5>(0h16), write_start_index)
node _use_this_queue_T_133 = lt(UInt<5>(0h16), wrap_len_index_end)
node _use_this_queue_T_134 = or(_use_this_queue_T_132, _use_this_queue_T_133)
node _use_this_queue_T_135 = geq(UInt<5>(0h16), write_start_index)
node _use_this_queue_T_136 = lt(UInt<5>(0h16), wrap_len_index_end)
node _use_this_queue_T_137 = and(_use_this_queue_T_135, _use_this_queue_T_136)
node use_this_queue_22 = mux(wrapped, _use_this_queue_T_134, _use_this_queue_T_137)
node _T_4179 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4180 = and(_T_4179, account_for_buf_lens_Q)
node _T_4181 = and(_T_4180, use_this_queue_22)
connect Queue2_UInt8_22.io.enq.valid, _T_4181
node _use_this_queue_T_138 = geq(UInt<5>(0h17), write_start_index)
node _use_this_queue_T_139 = lt(UInt<5>(0h17), wrap_len_index_end)
node _use_this_queue_T_140 = or(_use_this_queue_T_138, _use_this_queue_T_139)
node _use_this_queue_T_141 = geq(UInt<5>(0h17), write_start_index)
node _use_this_queue_T_142 = lt(UInt<5>(0h17), wrap_len_index_end)
node _use_this_queue_T_143 = and(_use_this_queue_T_141, _use_this_queue_T_142)
node use_this_queue_23 = mux(wrapped, _use_this_queue_T_140, _use_this_queue_T_143)
node _T_4182 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4183 = and(_T_4182, account_for_buf_lens_Q)
node _T_4184 = and(_T_4183, use_this_queue_23)
connect Queue2_UInt8_23.io.enq.valid, _T_4184
node _use_this_queue_T_144 = geq(UInt<5>(0h18), write_start_index)
node _use_this_queue_T_145 = lt(UInt<5>(0h18), wrap_len_index_end)
node _use_this_queue_T_146 = or(_use_this_queue_T_144, _use_this_queue_T_145)
node _use_this_queue_T_147 = geq(UInt<5>(0h18), write_start_index)
node _use_this_queue_T_148 = lt(UInt<5>(0h18), wrap_len_index_end)
node _use_this_queue_T_149 = and(_use_this_queue_T_147, _use_this_queue_T_148)
node use_this_queue_24 = mux(wrapped, _use_this_queue_T_146, _use_this_queue_T_149)
node _T_4185 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4186 = and(_T_4185, account_for_buf_lens_Q)
node _T_4187 = and(_T_4186, use_this_queue_24)
connect Queue2_UInt8_24.io.enq.valid, _T_4187
node _use_this_queue_T_150 = geq(UInt<5>(0h19), write_start_index)
node _use_this_queue_T_151 = lt(UInt<5>(0h19), wrap_len_index_end)
node _use_this_queue_T_152 = or(_use_this_queue_T_150, _use_this_queue_T_151)
node _use_this_queue_T_153 = geq(UInt<5>(0h19), write_start_index)
node _use_this_queue_T_154 = lt(UInt<5>(0h19), wrap_len_index_end)
node _use_this_queue_T_155 = and(_use_this_queue_T_153, _use_this_queue_T_154)
node use_this_queue_25 = mux(wrapped, _use_this_queue_T_152, _use_this_queue_T_155)
node _T_4188 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4189 = and(_T_4188, account_for_buf_lens_Q)
node _T_4190 = and(_T_4189, use_this_queue_25)
connect Queue2_UInt8_25.io.enq.valid, _T_4190
node _use_this_queue_T_156 = geq(UInt<5>(0h1a), write_start_index)
node _use_this_queue_T_157 = lt(UInt<5>(0h1a), wrap_len_index_end)
node _use_this_queue_T_158 = or(_use_this_queue_T_156, _use_this_queue_T_157)
node _use_this_queue_T_159 = geq(UInt<5>(0h1a), write_start_index)
node _use_this_queue_T_160 = lt(UInt<5>(0h1a), wrap_len_index_end)
node _use_this_queue_T_161 = and(_use_this_queue_T_159, _use_this_queue_T_160)
node use_this_queue_26 = mux(wrapped, _use_this_queue_T_158, _use_this_queue_T_161)
node _T_4191 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4192 = and(_T_4191, account_for_buf_lens_Q)
node _T_4193 = and(_T_4192, use_this_queue_26)
connect Queue2_UInt8_26.io.enq.valid, _T_4193
node _use_this_queue_T_162 = geq(UInt<5>(0h1b), write_start_index)
node _use_this_queue_T_163 = lt(UInt<5>(0h1b), wrap_len_index_end)
node _use_this_queue_T_164 = or(_use_this_queue_T_162, _use_this_queue_T_163)
node _use_this_queue_T_165 = geq(UInt<5>(0h1b), write_start_index)
node _use_this_queue_T_166 = lt(UInt<5>(0h1b), wrap_len_index_end)
node _use_this_queue_T_167 = and(_use_this_queue_T_165, _use_this_queue_T_166)
node use_this_queue_27 = mux(wrapped, _use_this_queue_T_164, _use_this_queue_T_167)
node _T_4194 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4195 = and(_T_4194, account_for_buf_lens_Q)
node _T_4196 = and(_T_4195, use_this_queue_27)
connect Queue2_UInt8_27.io.enq.valid, _T_4196
node _use_this_queue_T_168 = geq(UInt<5>(0h1c), write_start_index)
node _use_this_queue_T_169 = lt(UInt<5>(0h1c), wrap_len_index_end)
node _use_this_queue_T_170 = or(_use_this_queue_T_168, _use_this_queue_T_169)
node _use_this_queue_T_171 = geq(UInt<5>(0h1c), write_start_index)
node _use_this_queue_T_172 = lt(UInt<5>(0h1c), wrap_len_index_end)
node _use_this_queue_T_173 = and(_use_this_queue_T_171, _use_this_queue_T_172)
node use_this_queue_28 = mux(wrapped, _use_this_queue_T_170, _use_this_queue_T_173)
node _T_4197 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4198 = and(_T_4197, account_for_buf_lens_Q)
node _T_4199 = and(_T_4198, use_this_queue_28)
connect Queue2_UInt8_28.io.enq.valid, _T_4199
node _use_this_queue_T_174 = geq(UInt<5>(0h1d), write_start_index)
node _use_this_queue_T_175 = lt(UInt<5>(0h1d), wrap_len_index_end)
node _use_this_queue_T_176 = or(_use_this_queue_T_174, _use_this_queue_T_175)
node _use_this_queue_T_177 = geq(UInt<5>(0h1d), write_start_index)
node _use_this_queue_T_178 = lt(UInt<5>(0h1d), wrap_len_index_end)
node _use_this_queue_T_179 = and(_use_this_queue_T_177, _use_this_queue_T_178)
node use_this_queue_29 = mux(wrapped, _use_this_queue_T_176, _use_this_queue_T_179)
node _T_4200 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4201 = and(_T_4200, account_for_buf_lens_Q)
node _T_4202 = and(_T_4201, use_this_queue_29)
connect Queue2_UInt8_29.io.enq.valid, _T_4202
node _use_this_queue_T_180 = geq(UInt<5>(0h1e), write_start_index)
node _use_this_queue_T_181 = lt(UInt<5>(0h1e), wrap_len_index_end)
node _use_this_queue_T_182 = or(_use_this_queue_T_180, _use_this_queue_T_181)
node _use_this_queue_T_183 = geq(UInt<5>(0h1e), write_start_index)
node _use_this_queue_T_184 = lt(UInt<5>(0h1e), wrap_len_index_end)
node _use_this_queue_T_185 = and(_use_this_queue_T_183, _use_this_queue_T_184)
node use_this_queue_30 = mux(wrapped, _use_this_queue_T_182, _use_this_queue_T_185)
node _T_4203 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4204 = and(_T_4203, account_for_buf_lens_Q)
node _T_4205 = and(_T_4204, use_this_queue_30)
connect Queue2_UInt8_30.io.enq.valid, _T_4205
node _use_this_queue_T_186 = geq(UInt<5>(0h1f), write_start_index)
node _use_this_queue_T_187 = lt(UInt<5>(0h1f), wrap_len_index_end)
node _use_this_queue_T_188 = or(_use_this_queue_T_186, _use_this_queue_T_187)
node _use_this_queue_T_189 = geq(UInt<5>(0h1f), write_start_index)
node _use_this_queue_T_190 = lt(UInt<5>(0h1f), wrap_len_index_end)
node _use_this_queue_T_191 = and(_use_this_queue_T_189, _use_this_queue_T_190)
node use_this_queue_31 = mux(wrapped, _use_this_queue_T_188, _use_this_queue_T_191)
node _T_4206 = and(incoming_writes_Q.io.deq.valid, all_queues_ready)
node _T_4207 = and(_T_4206, account_for_buf_lens_Q)
node _T_4208 = and(_T_4207, use_this_queue_31)
connect Queue2_UInt8_31.io.enq.valid, _T_4208
when Queue2_UInt8.io.deq.valid :
regreset loginfo_cycles_3 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_6 = add(loginfo_cycles_3, UInt<1>(0h1))
node _loginfo_cycles_T_7 = tail(_loginfo_cycles_T_6, 1)
connect loginfo_cycles_3, _loginfo_cycles_T_7
node _T_4209 = asUInt(reset)
node _T_4210 = eq(_T_4209, UInt<1>(0h0))
when _T_4210 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_3) : printf_6
node _T_4211 = asUInt(reset)
node _T_4212 = eq(_T_4211, UInt<1>(0h0))
when _T_4212 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<1>(0h0), Queue2_UInt8.io.deq.bits) : printf_7
when Queue2_UInt8_1.io.deq.valid :
regreset loginfo_cycles_4 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_8 = add(loginfo_cycles_4, UInt<1>(0h1))
node _loginfo_cycles_T_9 = tail(_loginfo_cycles_T_8, 1)
connect loginfo_cycles_4, _loginfo_cycles_T_9
node _T_4213 = asUInt(reset)
node _T_4214 = eq(_T_4213, UInt<1>(0h0))
when _T_4214 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_4) : printf_8
node _T_4215 = asUInt(reset)
node _T_4216 = eq(_T_4215, UInt<1>(0h0))
when _T_4216 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<1>(0h1), Queue2_UInt8_1.io.deq.bits) : printf_9
when Queue2_UInt8_2.io.deq.valid :
regreset loginfo_cycles_5 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_10 = add(loginfo_cycles_5, UInt<1>(0h1))
node _loginfo_cycles_T_11 = tail(_loginfo_cycles_T_10, 1)
connect loginfo_cycles_5, _loginfo_cycles_T_11
node _T_4217 = asUInt(reset)
node _T_4218 = eq(_T_4217, UInt<1>(0h0))
when _T_4218 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_5) : printf_10
node _T_4219 = asUInt(reset)
node _T_4220 = eq(_T_4219, UInt<1>(0h0))
when _T_4220 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<2>(0h2), Queue2_UInt8_2.io.deq.bits) : printf_11
when Queue2_UInt8_3.io.deq.valid :
regreset loginfo_cycles_6 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_12 = add(loginfo_cycles_6, UInt<1>(0h1))
node _loginfo_cycles_T_13 = tail(_loginfo_cycles_T_12, 1)
connect loginfo_cycles_6, _loginfo_cycles_T_13
node _T_4221 = asUInt(reset)
node _T_4222 = eq(_T_4221, UInt<1>(0h0))
when _T_4222 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_6) : printf_12
node _T_4223 = asUInt(reset)
node _T_4224 = eq(_T_4223, UInt<1>(0h0))
when _T_4224 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<2>(0h3), Queue2_UInt8_3.io.deq.bits) : printf_13
when Queue2_UInt8_4.io.deq.valid :
regreset loginfo_cycles_7 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_14 = add(loginfo_cycles_7, UInt<1>(0h1))
node _loginfo_cycles_T_15 = tail(_loginfo_cycles_T_14, 1)
connect loginfo_cycles_7, _loginfo_cycles_T_15
node _T_4225 = asUInt(reset)
node _T_4226 = eq(_T_4225, UInt<1>(0h0))
when _T_4226 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_7) : printf_14
node _T_4227 = asUInt(reset)
node _T_4228 = eq(_T_4227, UInt<1>(0h0))
when _T_4228 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<3>(0h4), Queue2_UInt8_4.io.deq.bits) : printf_15
when Queue2_UInt8_5.io.deq.valid :
regreset loginfo_cycles_8 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_16 = add(loginfo_cycles_8, UInt<1>(0h1))
node _loginfo_cycles_T_17 = tail(_loginfo_cycles_T_16, 1)
connect loginfo_cycles_8, _loginfo_cycles_T_17
node _T_4229 = asUInt(reset)
node _T_4230 = eq(_T_4229, UInt<1>(0h0))
when _T_4230 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_8) : printf_16
node _T_4231 = asUInt(reset)
node _T_4232 = eq(_T_4231, UInt<1>(0h0))
when _T_4232 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<3>(0h5), Queue2_UInt8_5.io.deq.bits) : printf_17
when Queue2_UInt8_6.io.deq.valid :
regreset loginfo_cycles_9 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_18 = add(loginfo_cycles_9, UInt<1>(0h1))
node _loginfo_cycles_T_19 = tail(_loginfo_cycles_T_18, 1)
connect loginfo_cycles_9, _loginfo_cycles_T_19
node _T_4233 = asUInt(reset)
node _T_4234 = eq(_T_4233, UInt<1>(0h0))
when _T_4234 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_9) : printf_18
node _T_4235 = asUInt(reset)
node _T_4236 = eq(_T_4235, UInt<1>(0h0))
when _T_4236 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<3>(0h6), Queue2_UInt8_6.io.deq.bits) : printf_19
when Queue2_UInt8_7.io.deq.valid :
regreset loginfo_cycles_10 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_20 = add(loginfo_cycles_10, UInt<1>(0h1))
node _loginfo_cycles_T_21 = tail(_loginfo_cycles_T_20, 1)
connect loginfo_cycles_10, _loginfo_cycles_T_21
node _T_4237 = asUInt(reset)
node _T_4238 = eq(_T_4237, UInt<1>(0h0))
when _T_4238 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_10) : printf_20
node _T_4239 = asUInt(reset)
node _T_4240 = eq(_T_4239, UInt<1>(0h0))
when _T_4240 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<3>(0h7), Queue2_UInt8_7.io.deq.bits) : printf_21
when Queue2_UInt8_8.io.deq.valid :
regreset loginfo_cycles_11 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_22 = add(loginfo_cycles_11, UInt<1>(0h1))
node _loginfo_cycles_T_23 = tail(_loginfo_cycles_T_22, 1)
connect loginfo_cycles_11, _loginfo_cycles_T_23
node _T_4241 = asUInt(reset)
node _T_4242 = eq(_T_4241, UInt<1>(0h0))
when _T_4242 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_11) : printf_22
node _T_4243 = asUInt(reset)
node _T_4244 = eq(_T_4243, UInt<1>(0h0))
when _T_4244 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0h8), Queue2_UInt8_8.io.deq.bits) : printf_23
when Queue2_UInt8_9.io.deq.valid :
regreset loginfo_cycles_12 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_24 = add(loginfo_cycles_12, UInt<1>(0h1))
node _loginfo_cycles_T_25 = tail(_loginfo_cycles_T_24, 1)
connect loginfo_cycles_12, _loginfo_cycles_T_25
node _T_4245 = asUInt(reset)
node _T_4246 = eq(_T_4245, UInt<1>(0h0))
when _T_4246 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_12) : printf_24
node _T_4247 = asUInt(reset)
node _T_4248 = eq(_T_4247, UInt<1>(0h0))
when _T_4248 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0h9), Queue2_UInt8_9.io.deq.bits) : printf_25
when Queue2_UInt8_10.io.deq.valid :
regreset loginfo_cycles_13 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_26 = add(loginfo_cycles_13, UInt<1>(0h1))
node _loginfo_cycles_T_27 = tail(_loginfo_cycles_T_26, 1)
connect loginfo_cycles_13, _loginfo_cycles_T_27
node _T_4249 = asUInt(reset)
node _T_4250 = eq(_T_4249, UInt<1>(0h0))
when _T_4250 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_13) : printf_26
node _T_4251 = asUInt(reset)
node _T_4252 = eq(_T_4251, UInt<1>(0h0))
when _T_4252 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0ha), Queue2_UInt8_10.io.deq.bits) : printf_27
when Queue2_UInt8_11.io.deq.valid :
regreset loginfo_cycles_14 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_28 = add(loginfo_cycles_14, UInt<1>(0h1))
node _loginfo_cycles_T_29 = tail(_loginfo_cycles_T_28, 1)
connect loginfo_cycles_14, _loginfo_cycles_T_29
node _T_4253 = asUInt(reset)
node _T_4254 = eq(_T_4253, UInt<1>(0h0))
when _T_4254 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_14) : printf_28
node _T_4255 = asUInt(reset)
node _T_4256 = eq(_T_4255, UInt<1>(0h0))
when _T_4256 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0hb), Queue2_UInt8_11.io.deq.bits) : printf_29
when Queue2_UInt8_12.io.deq.valid :
regreset loginfo_cycles_15 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_30 = add(loginfo_cycles_15, UInt<1>(0h1))
node _loginfo_cycles_T_31 = tail(_loginfo_cycles_T_30, 1)
connect loginfo_cycles_15, _loginfo_cycles_T_31
node _T_4257 = asUInt(reset)
node _T_4258 = eq(_T_4257, UInt<1>(0h0))
when _T_4258 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_15) : printf_30
node _T_4259 = asUInt(reset)
node _T_4260 = eq(_T_4259, UInt<1>(0h0))
when _T_4260 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0hc), Queue2_UInt8_12.io.deq.bits) : printf_31
when Queue2_UInt8_13.io.deq.valid :
regreset loginfo_cycles_16 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_32 = add(loginfo_cycles_16, UInt<1>(0h1))
node _loginfo_cycles_T_33 = tail(_loginfo_cycles_T_32, 1)
connect loginfo_cycles_16, _loginfo_cycles_T_33
node _T_4261 = asUInt(reset)
node _T_4262 = eq(_T_4261, UInt<1>(0h0))
when _T_4262 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_16) : printf_32
node _T_4263 = asUInt(reset)
node _T_4264 = eq(_T_4263, UInt<1>(0h0))
when _T_4264 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0hd), Queue2_UInt8_13.io.deq.bits) : printf_33
when Queue2_UInt8_14.io.deq.valid :
regreset loginfo_cycles_17 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_34 = add(loginfo_cycles_17, UInt<1>(0h1))
node _loginfo_cycles_T_35 = tail(_loginfo_cycles_T_34, 1)
connect loginfo_cycles_17, _loginfo_cycles_T_35
node _T_4265 = asUInt(reset)
node _T_4266 = eq(_T_4265, UInt<1>(0h0))
when _T_4266 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_17) : printf_34
node _T_4267 = asUInt(reset)
node _T_4268 = eq(_T_4267, UInt<1>(0h0))
when _T_4268 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0he), Queue2_UInt8_14.io.deq.bits) : printf_35
when Queue2_UInt8_15.io.deq.valid :
regreset loginfo_cycles_18 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_36 = add(loginfo_cycles_18, UInt<1>(0h1))
node _loginfo_cycles_T_37 = tail(_loginfo_cycles_T_36, 1)
connect loginfo_cycles_18, _loginfo_cycles_T_37
node _T_4269 = asUInt(reset)
node _T_4270 = eq(_T_4269, UInt<1>(0h0))
when _T_4270 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_18) : printf_36
node _T_4271 = asUInt(reset)
node _T_4272 = eq(_T_4271, UInt<1>(0h0))
when _T_4272 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<4>(0hf), Queue2_UInt8_15.io.deq.bits) : printf_37
when Queue2_UInt8_16.io.deq.valid :
regreset loginfo_cycles_19 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_38 = add(loginfo_cycles_19, UInt<1>(0h1))
node _loginfo_cycles_T_39 = tail(_loginfo_cycles_T_38, 1)
connect loginfo_cycles_19, _loginfo_cycles_T_39
node _T_4273 = asUInt(reset)
node _T_4274 = eq(_T_4273, UInt<1>(0h0))
when _T_4274 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_19) : printf_38
node _T_4275 = asUInt(reset)
node _T_4276 = eq(_T_4275, UInt<1>(0h0))
when _T_4276 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h10), Queue2_UInt8_16.io.deq.bits) : printf_39
when Queue2_UInt8_17.io.deq.valid :
regreset loginfo_cycles_20 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_40 = add(loginfo_cycles_20, UInt<1>(0h1))
node _loginfo_cycles_T_41 = tail(_loginfo_cycles_T_40, 1)
connect loginfo_cycles_20, _loginfo_cycles_T_41
node _T_4277 = asUInt(reset)
node _T_4278 = eq(_T_4277, UInt<1>(0h0))
when _T_4278 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_20) : printf_40
node _T_4279 = asUInt(reset)
node _T_4280 = eq(_T_4279, UInt<1>(0h0))
when _T_4280 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h11), Queue2_UInt8_17.io.deq.bits) : printf_41
when Queue2_UInt8_18.io.deq.valid :
regreset loginfo_cycles_21 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_42 = add(loginfo_cycles_21, UInt<1>(0h1))
node _loginfo_cycles_T_43 = tail(_loginfo_cycles_T_42, 1)
connect loginfo_cycles_21, _loginfo_cycles_T_43
node _T_4281 = asUInt(reset)
node _T_4282 = eq(_T_4281, UInt<1>(0h0))
when _T_4282 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_21) : printf_42
node _T_4283 = asUInt(reset)
node _T_4284 = eq(_T_4283, UInt<1>(0h0))
when _T_4284 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h12), Queue2_UInt8_18.io.deq.bits) : printf_43
when Queue2_UInt8_19.io.deq.valid :
regreset loginfo_cycles_22 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_44 = add(loginfo_cycles_22, UInt<1>(0h1))
node _loginfo_cycles_T_45 = tail(_loginfo_cycles_T_44, 1)
connect loginfo_cycles_22, _loginfo_cycles_T_45
node _T_4285 = asUInt(reset)
node _T_4286 = eq(_T_4285, UInt<1>(0h0))
when _T_4286 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_22) : printf_44
node _T_4287 = asUInt(reset)
node _T_4288 = eq(_T_4287, UInt<1>(0h0))
when _T_4288 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h13), Queue2_UInt8_19.io.deq.bits) : printf_45
when Queue2_UInt8_20.io.deq.valid :
regreset loginfo_cycles_23 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_46 = add(loginfo_cycles_23, UInt<1>(0h1))
node _loginfo_cycles_T_47 = tail(_loginfo_cycles_T_46, 1)
connect loginfo_cycles_23, _loginfo_cycles_T_47
node _T_4289 = asUInt(reset)
node _T_4290 = eq(_T_4289, UInt<1>(0h0))
when _T_4290 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_23) : printf_46
node _T_4291 = asUInt(reset)
node _T_4292 = eq(_T_4291, UInt<1>(0h0))
when _T_4292 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h14), Queue2_UInt8_20.io.deq.bits) : printf_47
when Queue2_UInt8_21.io.deq.valid :
regreset loginfo_cycles_24 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_48 = add(loginfo_cycles_24, UInt<1>(0h1))
node _loginfo_cycles_T_49 = tail(_loginfo_cycles_T_48, 1)
connect loginfo_cycles_24, _loginfo_cycles_T_49
node _T_4293 = asUInt(reset)
node _T_4294 = eq(_T_4293, UInt<1>(0h0))
when _T_4294 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_24) : printf_48
node _T_4295 = asUInt(reset)
node _T_4296 = eq(_T_4295, UInt<1>(0h0))
when _T_4296 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h15), Queue2_UInt8_21.io.deq.bits) : printf_49
when Queue2_UInt8_22.io.deq.valid :
regreset loginfo_cycles_25 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_50 = add(loginfo_cycles_25, UInt<1>(0h1))
node _loginfo_cycles_T_51 = tail(_loginfo_cycles_T_50, 1)
connect loginfo_cycles_25, _loginfo_cycles_T_51
node _T_4297 = asUInt(reset)
node _T_4298 = eq(_T_4297, UInt<1>(0h0))
when _T_4298 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_25) : printf_50
node _T_4299 = asUInt(reset)
node _T_4300 = eq(_T_4299, UInt<1>(0h0))
when _T_4300 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h16), Queue2_UInt8_22.io.deq.bits) : printf_51
when Queue2_UInt8_23.io.deq.valid :
regreset loginfo_cycles_26 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_52 = add(loginfo_cycles_26, UInt<1>(0h1))
node _loginfo_cycles_T_53 = tail(_loginfo_cycles_T_52, 1)
connect loginfo_cycles_26, _loginfo_cycles_T_53
node _T_4301 = asUInt(reset)
node _T_4302 = eq(_T_4301, UInt<1>(0h0))
when _T_4302 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_26) : printf_52
node _T_4303 = asUInt(reset)
node _T_4304 = eq(_T_4303, UInt<1>(0h0))
when _T_4304 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h17), Queue2_UInt8_23.io.deq.bits) : printf_53
when Queue2_UInt8_24.io.deq.valid :
regreset loginfo_cycles_27 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_54 = add(loginfo_cycles_27, UInt<1>(0h1))
node _loginfo_cycles_T_55 = tail(_loginfo_cycles_T_54, 1)
connect loginfo_cycles_27, _loginfo_cycles_T_55
node _T_4305 = asUInt(reset)
node _T_4306 = eq(_T_4305, UInt<1>(0h0))
when _T_4306 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_27) : printf_54
node _T_4307 = asUInt(reset)
node _T_4308 = eq(_T_4307, UInt<1>(0h0))
when _T_4308 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h18), Queue2_UInt8_24.io.deq.bits) : printf_55
when Queue2_UInt8_25.io.deq.valid :
regreset loginfo_cycles_28 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_56 = add(loginfo_cycles_28, UInt<1>(0h1))
node _loginfo_cycles_T_57 = tail(_loginfo_cycles_T_56, 1)
connect loginfo_cycles_28, _loginfo_cycles_T_57
node _T_4309 = asUInt(reset)
node _T_4310 = eq(_T_4309, UInt<1>(0h0))
when _T_4310 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_28) : printf_56
node _T_4311 = asUInt(reset)
node _T_4312 = eq(_T_4311, UInt<1>(0h0))
when _T_4312 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h19), Queue2_UInt8_25.io.deq.bits) : printf_57
when Queue2_UInt8_26.io.deq.valid :
regreset loginfo_cycles_29 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_58 = add(loginfo_cycles_29, UInt<1>(0h1))
node _loginfo_cycles_T_59 = tail(_loginfo_cycles_T_58, 1)
connect loginfo_cycles_29, _loginfo_cycles_T_59
node _T_4313 = asUInt(reset)
node _T_4314 = eq(_T_4313, UInt<1>(0h0))
when _T_4314 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_29) : printf_58
node _T_4315 = asUInt(reset)
node _T_4316 = eq(_T_4315, UInt<1>(0h0))
when _T_4316 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1a), Queue2_UInt8_26.io.deq.bits) : printf_59
when Queue2_UInt8_27.io.deq.valid :
regreset loginfo_cycles_30 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_60 = add(loginfo_cycles_30, UInt<1>(0h1))
node _loginfo_cycles_T_61 = tail(_loginfo_cycles_T_60, 1)
connect loginfo_cycles_30, _loginfo_cycles_T_61
node _T_4317 = asUInt(reset)
node _T_4318 = eq(_T_4317, UInt<1>(0h0))
when _T_4318 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_30) : printf_60
node _T_4319 = asUInt(reset)
node _T_4320 = eq(_T_4319, UInt<1>(0h0))
when _T_4320 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1b), Queue2_UInt8_27.io.deq.bits) : printf_61
when Queue2_UInt8_28.io.deq.valid :
regreset loginfo_cycles_31 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_62 = add(loginfo_cycles_31, UInt<1>(0h1))
node _loginfo_cycles_T_63 = tail(_loginfo_cycles_T_62, 1)
connect loginfo_cycles_31, _loginfo_cycles_T_63
node _T_4321 = asUInt(reset)
node _T_4322 = eq(_T_4321, UInt<1>(0h0))
when _T_4322 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_31) : printf_62
node _T_4323 = asUInt(reset)
node _T_4324 = eq(_T_4323, UInt<1>(0h0))
when _T_4324 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1c), Queue2_UInt8_28.io.deq.bits) : printf_63
when Queue2_UInt8_29.io.deq.valid :
regreset loginfo_cycles_32 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_64 = add(loginfo_cycles_32, UInt<1>(0h1))
node _loginfo_cycles_T_65 = tail(_loginfo_cycles_T_64, 1)
connect loginfo_cycles_32, _loginfo_cycles_T_65
node _T_4325 = asUInt(reset)
node _T_4326 = eq(_T_4325, UInt<1>(0h0))
when _T_4326 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_32) : printf_64
node _T_4327 = asUInt(reset)
node _T_4328 = eq(_T_4327, UInt<1>(0h0))
when _T_4328 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1d), Queue2_UInt8_29.io.deq.bits) : printf_65
when Queue2_UInt8_30.io.deq.valid :
regreset loginfo_cycles_33 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_66 = add(loginfo_cycles_33, UInt<1>(0h1))
node _loginfo_cycles_T_67 = tail(_loginfo_cycles_T_66, 1)
connect loginfo_cycles_33, _loginfo_cycles_T_67
node _T_4329 = asUInt(reset)
node _T_4330 = eq(_T_4329, UInt<1>(0h0))
when _T_4330 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_33) : printf_66
node _T_4331 = asUInt(reset)
node _T_4332 = eq(_T_4331, UInt<1>(0h0))
when _T_4332 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1e), Queue2_UInt8_30.io.deq.bits) : printf_67
when Queue2_UInt8_31.io.deq.valid :
regreset loginfo_cycles_34 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_68 = add(loginfo_cycles_34, UInt<1>(0h1))
node _loginfo_cycles_T_69 = tail(_loginfo_cycles_T_68, 1)
connect loginfo_cycles_34, _loginfo_cycles_T_69
node _T_4333 = asUInt(reset)
node _T_4334 = eq(_T_4333, UInt<1>(0h0))
when _T_4334 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_34) : printf_68
node _T_4335 = asUInt(reset)
node _T_4336 = eq(_T_4335, UInt<1>(0h0))
when _T_4336 :
printf(clock, UInt<1>(0h1), "qi%d,0x%x\n", UInt<5>(0h1f), Queue2_UInt8_31.io.deq.bits) : printf_69
regreset read_start_index : UInt<6>, clock, reset, UInt<6>(0h0)
wire remapVecData : UInt<8>[32]
wire remapVecValids : UInt<1>[32]
wire remapVecReadys : UInt<1>[32]
connect remapVecData[0], UInt<1>(0h0)
connect remapVecValids[0], UInt<1>(0h0)
connect Queue2_UInt8.io.deq.ready, UInt<1>(0h0)
connect remapVecData[1], UInt<1>(0h0)
connect remapVecValids[1], UInt<1>(0h0)
connect Queue2_UInt8_1.io.deq.ready, UInt<1>(0h0)
connect remapVecData[2], UInt<1>(0h0)
connect remapVecValids[2], UInt<1>(0h0)
connect Queue2_UInt8_2.io.deq.ready, UInt<1>(0h0)
connect remapVecData[3], UInt<1>(0h0)
connect remapVecValids[3], UInt<1>(0h0)
connect Queue2_UInt8_3.io.deq.ready, UInt<1>(0h0)
connect remapVecData[4], UInt<1>(0h0)
connect remapVecValids[4], UInt<1>(0h0)
connect Queue2_UInt8_4.io.deq.ready, UInt<1>(0h0)
connect remapVecData[5], UInt<1>(0h0)
connect remapVecValids[5], UInt<1>(0h0)
connect Queue2_UInt8_5.io.deq.ready, UInt<1>(0h0)
connect remapVecData[6], UInt<1>(0h0)
connect remapVecValids[6], UInt<1>(0h0)
connect Queue2_UInt8_6.io.deq.ready, UInt<1>(0h0)
connect remapVecData[7], UInt<1>(0h0)
connect remapVecValids[7], UInt<1>(0h0)
connect Queue2_UInt8_7.io.deq.ready, UInt<1>(0h0)
connect remapVecData[8], UInt<1>(0h0)
connect remapVecValids[8], UInt<1>(0h0)
connect Queue2_UInt8_8.io.deq.ready, UInt<1>(0h0)
connect remapVecData[9], UInt<1>(0h0)
connect remapVecValids[9], UInt<1>(0h0)
connect Queue2_UInt8_9.io.deq.ready, UInt<1>(0h0)
connect remapVecData[10], UInt<1>(0h0)
connect remapVecValids[10], UInt<1>(0h0)
connect Queue2_UInt8_10.io.deq.ready, UInt<1>(0h0)
connect remapVecData[11], UInt<1>(0h0)
connect remapVecValids[11], UInt<1>(0h0)
connect Queue2_UInt8_11.io.deq.ready, UInt<1>(0h0)
connect remapVecData[12], UInt<1>(0h0)
connect remapVecValids[12], UInt<1>(0h0)
connect Queue2_UInt8_12.io.deq.ready, UInt<1>(0h0)
connect remapVecData[13], UInt<1>(0h0)
connect remapVecValids[13], UInt<1>(0h0)
connect Queue2_UInt8_13.io.deq.ready, UInt<1>(0h0)
connect remapVecData[14], UInt<1>(0h0)
connect remapVecValids[14], UInt<1>(0h0)
connect Queue2_UInt8_14.io.deq.ready, UInt<1>(0h0)
connect remapVecData[15], UInt<1>(0h0)
connect remapVecValids[15], UInt<1>(0h0)
connect Queue2_UInt8_15.io.deq.ready, UInt<1>(0h0)
connect remapVecData[16], UInt<1>(0h0)
connect remapVecValids[16], UInt<1>(0h0)
connect Queue2_UInt8_16.io.deq.ready, UInt<1>(0h0)
connect remapVecData[17], UInt<1>(0h0)
connect remapVecValids[17], UInt<1>(0h0)
connect Queue2_UInt8_17.io.deq.ready, UInt<1>(0h0)
connect remapVecData[18], UInt<1>(0h0)
connect remapVecValids[18], UInt<1>(0h0)
connect Queue2_UInt8_18.io.deq.ready, UInt<1>(0h0)
connect remapVecData[19], UInt<1>(0h0)
connect remapVecValids[19], UInt<1>(0h0)
connect Queue2_UInt8_19.io.deq.ready, UInt<1>(0h0)
connect remapVecData[20], UInt<1>(0h0)
connect remapVecValids[20], UInt<1>(0h0)
connect Queue2_UInt8_20.io.deq.ready, UInt<1>(0h0)
connect remapVecData[21], UInt<1>(0h0)
connect remapVecValids[21], UInt<1>(0h0)
connect Queue2_UInt8_21.io.deq.ready, UInt<1>(0h0)
connect remapVecData[22], UInt<1>(0h0)
connect remapVecValids[22], UInt<1>(0h0)
connect Queue2_UInt8_22.io.deq.ready, UInt<1>(0h0)
connect remapVecData[23], UInt<1>(0h0)
connect remapVecValids[23], UInt<1>(0h0)
connect Queue2_UInt8_23.io.deq.ready, UInt<1>(0h0)
connect remapVecData[24], UInt<1>(0h0)
connect remapVecValids[24], UInt<1>(0h0)
connect Queue2_UInt8_24.io.deq.ready, UInt<1>(0h0)
connect remapVecData[25], UInt<1>(0h0)
connect remapVecValids[25], UInt<1>(0h0)
connect Queue2_UInt8_25.io.deq.ready, UInt<1>(0h0)
connect remapVecData[26], UInt<1>(0h0)
connect remapVecValids[26], UInt<1>(0h0)
connect Queue2_UInt8_26.io.deq.ready, UInt<1>(0h0)
connect remapVecData[27], UInt<1>(0h0)
connect remapVecValids[27], UInt<1>(0h0)
connect Queue2_UInt8_27.io.deq.ready, UInt<1>(0h0)
connect remapVecData[28], UInt<1>(0h0)
connect remapVecValids[28], UInt<1>(0h0)
connect Queue2_UInt8_28.io.deq.ready, UInt<1>(0h0)
connect remapVecData[29], UInt<1>(0h0)
connect remapVecValids[29], UInt<1>(0h0)
connect Queue2_UInt8_29.io.deq.ready, UInt<1>(0h0)
connect remapVecData[30], UInt<1>(0h0)
connect remapVecValids[30], UInt<1>(0h0)
connect Queue2_UInt8_30.io.deq.ready, UInt<1>(0h0)
connect remapVecData[31], UInt<1>(0h0)
connect remapVecValids[31], UInt<1>(0h0)
connect Queue2_UInt8_31.io.deq.ready, UInt<1>(0h0)
node _remapindex_T = add(UInt<1>(0h0), read_start_index)
node remapindex = rem(_remapindex_T, UInt<6>(0h20))
node _T_4337 = eq(UInt<1>(0h0), remapindex)
when _T_4337 :
connect remapVecData[0], Queue2_UInt8.io.deq.bits
connect remapVecValids[0], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[0]
node _T_4338 = eq(UInt<1>(0h1), remapindex)
when _T_4338 :
connect remapVecData[0], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[0]
node _T_4339 = eq(UInt<2>(0h2), remapindex)
when _T_4339 :
connect remapVecData[0], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[0]
node _T_4340 = eq(UInt<2>(0h3), remapindex)
when _T_4340 :
connect remapVecData[0], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[0]
node _T_4341 = eq(UInt<3>(0h4), remapindex)
when _T_4341 :
connect remapVecData[0], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[0]
node _T_4342 = eq(UInt<3>(0h5), remapindex)
when _T_4342 :
connect remapVecData[0], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[0]
node _T_4343 = eq(UInt<3>(0h6), remapindex)
when _T_4343 :
connect remapVecData[0], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[0]
node _T_4344 = eq(UInt<3>(0h7), remapindex)
when _T_4344 :
connect remapVecData[0], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[0]
node _T_4345 = eq(UInt<4>(0h8), remapindex)
when _T_4345 :
connect remapVecData[0], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[0]
node _T_4346 = eq(UInt<4>(0h9), remapindex)
when _T_4346 :
connect remapVecData[0], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[0]
node _T_4347 = eq(UInt<4>(0ha), remapindex)
when _T_4347 :
connect remapVecData[0], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[0]
node _T_4348 = eq(UInt<4>(0hb), remapindex)
when _T_4348 :
connect remapVecData[0], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[0]
node _T_4349 = eq(UInt<4>(0hc), remapindex)
when _T_4349 :
connect remapVecData[0], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[0]
node _T_4350 = eq(UInt<4>(0hd), remapindex)
when _T_4350 :
connect remapVecData[0], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[0]
node _T_4351 = eq(UInt<4>(0he), remapindex)
when _T_4351 :
connect remapVecData[0], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[0]
node _T_4352 = eq(UInt<4>(0hf), remapindex)
when _T_4352 :
connect remapVecData[0], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[0]
node _T_4353 = eq(UInt<5>(0h10), remapindex)
when _T_4353 :
connect remapVecData[0], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[0]
node _T_4354 = eq(UInt<5>(0h11), remapindex)
when _T_4354 :
connect remapVecData[0], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[0]
node _T_4355 = eq(UInt<5>(0h12), remapindex)
when _T_4355 :
connect remapVecData[0], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[0]
node _T_4356 = eq(UInt<5>(0h13), remapindex)
when _T_4356 :
connect remapVecData[0], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[0]
node _T_4357 = eq(UInt<5>(0h14), remapindex)
when _T_4357 :
connect remapVecData[0], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[0]
node _T_4358 = eq(UInt<5>(0h15), remapindex)
when _T_4358 :
connect remapVecData[0], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[0]
node _T_4359 = eq(UInt<5>(0h16), remapindex)
when _T_4359 :
connect remapVecData[0], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[0]
node _T_4360 = eq(UInt<5>(0h17), remapindex)
when _T_4360 :
connect remapVecData[0], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[0]
node _T_4361 = eq(UInt<5>(0h18), remapindex)
when _T_4361 :
connect remapVecData[0], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[0]
node _T_4362 = eq(UInt<5>(0h19), remapindex)
when _T_4362 :
connect remapVecData[0], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[0]
node _T_4363 = eq(UInt<5>(0h1a), remapindex)
when _T_4363 :
connect remapVecData[0], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[0]
node _T_4364 = eq(UInt<5>(0h1b), remapindex)
when _T_4364 :
connect remapVecData[0], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[0]
node _T_4365 = eq(UInt<5>(0h1c), remapindex)
when _T_4365 :
connect remapVecData[0], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[0]
node _T_4366 = eq(UInt<5>(0h1d), remapindex)
when _T_4366 :
connect remapVecData[0], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[0]
node _T_4367 = eq(UInt<5>(0h1e), remapindex)
when _T_4367 :
connect remapVecData[0], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[0]
node _T_4368 = eq(UInt<5>(0h1f), remapindex)
when _T_4368 :
connect remapVecData[0], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[0], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[0]
node _remapindex_T_1 = add(UInt<1>(0h1), read_start_index)
node remapindex_1 = rem(_remapindex_T_1, UInt<6>(0h20))
node _T_4369 = eq(UInt<1>(0h0), remapindex_1)
when _T_4369 :
connect remapVecData[1], Queue2_UInt8.io.deq.bits
connect remapVecValids[1], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[1]
node _T_4370 = eq(UInt<1>(0h1), remapindex_1)
when _T_4370 :
connect remapVecData[1], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[1]
node _T_4371 = eq(UInt<2>(0h2), remapindex_1)
when _T_4371 :
connect remapVecData[1], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[1]
node _T_4372 = eq(UInt<2>(0h3), remapindex_1)
when _T_4372 :
connect remapVecData[1], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[1]
node _T_4373 = eq(UInt<3>(0h4), remapindex_1)
when _T_4373 :
connect remapVecData[1], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[1]
node _T_4374 = eq(UInt<3>(0h5), remapindex_1)
when _T_4374 :
connect remapVecData[1], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[1]
node _T_4375 = eq(UInt<3>(0h6), remapindex_1)
when _T_4375 :
connect remapVecData[1], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[1]
node _T_4376 = eq(UInt<3>(0h7), remapindex_1)
when _T_4376 :
connect remapVecData[1], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[1]
node _T_4377 = eq(UInt<4>(0h8), remapindex_1)
when _T_4377 :
connect remapVecData[1], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[1]
node _T_4378 = eq(UInt<4>(0h9), remapindex_1)
when _T_4378 :
connect remapVecData[1], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[1]
node _T_4379 = eq(UInt<4>(0ha), remapindex_1)
when _T_4379 :
connect remapVecData[1], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[1]
node _T_4380 = eq(UInt<4>(0hb), remapindex_1)
when _T_4380 :
connect remapVecData[1], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[1]
node _T_4381 = eq(UInt<4>(0hc), remapindex_1)
when _T_4381 :
connect remapVecData[1], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[1]
node _T_4382 = eq(UInt<4>(0hd), remapindex_1)
when _T_4382 :
connect remapVecData[1], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[1]
node _T_4383 = eq(UInt<4>(0he), remapindex_1)
when _T_4383 :
connect remapVecData[1], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[1]
node _T_4384 = eq(UInt<4>(0hf), remapindex_1)
when _T_4384 :
connect remapVecData[1], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[1]
node _T_4385 = eq(UInt<5>(0h10), remapindex_1)
when _T_4385 :
connect remapVecData[1], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[1]
node _T_4386 = eq(UInt<5>(0h11), remapindex_1)
when _T_4386 :
connect remapVecData[1], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[1]
node _T_4387 = eq(UInt<5>(0h12), remapindex_1)
when _T_4387 :
connect remapVecData[1], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[1]
node _T_4388 = eq(UInt<5>(0h13), remapindex_1)
when _T_4388 :
connect remapVecData[1], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[1]
node _T_4389 = eq(UInt<5>(0h14), remapindex_1)
when _T_4389 :
connect remapVecData[1], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[1]
node _T_4390 = eq(UInt<5>(0h15), remapindex_1)
when _T_4390 :
connect remapVecData[1], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[1]
node _T_4391 = eq(UInt<5>(0h16), remapindex_1)
when _T_4391 :
connect remapVecData[1], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[1]
node _T_4392 = eq(UInt<5>(0h17), remapindex_1)
when _T_4392 :
connect remapVecData[1], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[1]
node _T_4393 = eq(UInt<5>(0h18), remapindex_1)
when _T_4393 :
connect remapVecData[1], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[1]
node _T_4394 = eq(UInt<5>(0h19), remapindex_1)
when _T_4394 :
connect remapVecData[1], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[1]
node _T_4395 = eq(UInt<5>(0h1a), remapindex_1)
when _T_4395 :
connect remapVecData[1], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[1]
node _T_4396 = eq(UInt<5>(0h1b), remapindex_1)
when _T_4396 :
connect remapVecData[1], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[1]
node _T_4397 = eq(UInt<5>(0h1c), remapindex_1)
when _T_4397 :
connect remapVecData[1], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[1]
node _T_4398 = eq(UInt<5>(0h1d), remapindex_1)
when _T_4398 :
connect remapVecData[1], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[1]
node _T_4399 = eq(UInt<5>(0h1e), remapindex_1)
when _T_4399 :
connect remapVecData[1], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[1]
node _T_4400 = eq(UInt<5>(0h1f), remapindex_1)
when _T_4400 :
connect remapVecData[1], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[1], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[1]
node _remapindex_T_2 = add(UInt<2>(0h2), read_start_index)
node remapindex_2 = rem(_remapindex_T_2, UInt<6>(0h20))
node _T_4401 = eq(UInt<1>(0h0), remapindex_2)
when _T_4401 :
connect remapVecData[2], Queue2_UInt8.io.deq.bits
connect remapVecValids[2], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[2]
node _T_4402 = eq(UInt<1>(0h1), remapindex_2)
when _T_4402 :
connect remapVecData[2], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[2]
node _T_4403 = eq(UInt<2>(0h2), remapindex_2)
when _T_4403 :
connect remapVecData[2], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[2]
node _T_4404 = eq(UInt<2>(0h3), remapindex_2)
when _T_4404 :
connect remapVecData[2], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[2]
node _T_4405 = eq(UInt<3>(0h4), remapindex_2)
when _T_4405 :
connect remapVecData[2], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[2]
node _T_4406 = eq(UInt<3>(0h5), remapindex_2)
when _T_4406 :
connect remapVecData[2], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[2]
node _T_4407 = eq(UInt<3>(0h6), remapindex_2)
when _T_4407 :
connect remapVecData[2], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[2]
node _T_4408 = eq(UInt<3>(0h7), remapindex_2)
when _T_4408 :
connect remapVecData[2], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[2]
node _T_4409 = eq(UInt<4>(0h8), remapindex_2)
when _T_4409 :
connect remapVecData[2], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[2]
node _T_4410 = eq(UInt<4>(0h9), remapindex_2)
when _T_4410 :
connect remapVecData[2], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[2]
node _T_4411 = eq(UInt<4>(0ha), remapindex_2)
when _T_4411 :
connect remapVecData[2], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[2]
node _T_4412 = eq(UInt<4>(0hb), remapindex_2)
when _T_4412 :
connect remapVecData[2], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[2]
node _T_4413 = eq(UInt<4>(0hc), remapindex_2)
when _T_4413 :
connect remapVecData[2], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[2]
node _T_4414 = eq(UInt<4>(0hd), remapindex_2)
when _T_4414 :
connect remapVecData[2], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[2]
node _T_4415 = eq(UInt<4>(0he), remapindex_2)
when _T_4415 :
connect remapVecData[2], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[2]
node _T_4416 = eq(UInt<4>(0hf), remapindex_2)
when _T_4416 :
connect remapVecData[2], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[2]
node _T_4417 = eq(UInt<5>(0h10), remapindex_2)
when _T_4417 :
connect remapVecData[2], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[2]
node _T_4418 = eq(UInt<5>(0h11), remapindex_2)
when _T_4418 :
connect remapVecData[2], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[2]
node _T_4419 = eq(UInt<5>(0h12), remapindex_2)
when _T_4419 :
connect remapVecData[2], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[2]
node _T_4420 = eq(UInt<5>(0h13), remapindex_2)
when _T_4420 :
connect remapVecData[2], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[2]
node _T_4421 = eq(UInt<5>(0h14), remapindex_2)
when _T_4421 :
connect remapVecData[2], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[2]
node _T_4422 = eq(UInt<5>(0h15), remapindex_2)
when _T_4422 :
connect remapVecData[2], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[2]
node _T_4423 = eq(UInt<5>(0h16), remapindex_2)
when _T_4423 :
connect remapVecData[2], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[2]
node _T_4424 = eq(UInt<5>(0h17), remapindex_2)
when _T_4424 :
connect remapVecData[2], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[2]
node _T_4425 = eq(UInt<5>(0h18), remapindex_2)
when _T_4425 :
connect remapVecData[2], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[2]
node _T_4426 = eq(UInt<5>(0h19), remapindex_2)
when _T_4426 :
connect remapVecData[2], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[2]
node _T_4427 = eq(UInt<5>(0h1a), remapindex_2)
when _T_4427 :
connect remapVecData[2], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[2]
node _T_4428 = eq(UInt<5>(0h1b), remapindex_2)
when _T_4428 :
connect remapVecData[2], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[2]
node _T_4429 = eq(UInt<5>(0h1c), remapindex_2)
when _T_4429 :
connect remapVecData[2], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[2]
node _T_4430 = eq(UInt<5>(0h1d), remapindex_2)
when _T_4430 :
connect remapVecData[2], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[2]
node _T_4431 = eq(UInt<5>(0h1e), remapindex_2)
when _T_4431 :
connect remapVecData[2], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[2]
node _T_4432 = eq(UInt<5>(0h1f), remapindex_2)
when _T_4432 :
connect remapVecData[2], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[2], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[2]
node _remapindex_T_3 = add(UInt<2>(0h3), read_start_index)
node remapindex_3 = rem(_remapindex_T_3, UInt<6>(0h20))
node _T_4433 = eq(UInt<1>(0h0), remapindex_3)
when _T_4433 :
connect remapVecData[3], Queue2_UInt8.io.deq.bits
connect remapVecValids[3], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[3]
node _T_4434 = eq(UInt<1>(0h1), remapindex_3)
when _T_4434 :
connect remapVecData[3], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[3]
node _T_4435 = eq(UInt<2>(0h2), remapindex_3)
when _T_4435 :
connect remapVecData[3], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[3]
node _T_4436 = eq(UInt<2>(0h3), remapindex_3)
when _T_4436 :
connect remapVecData[3], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[3]
node _T_4437 = eq(UInt<3>(0h4), remapindex_3)
when _T_4437 :
connect remapVecData[3], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[3]
node _T_4438 = eq(UInt<3>(0h5), remapindex_3)
when _T_4438 :
connect remapVecData[3], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[3]
node _T_4439 = eq(UInt<3>(0h6), remapindex_3)
when _T_4439 :
connect remapVecData[3], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[3]
node _T_4440 = eq(UInt<3>(0h7), remapindex_3)
when _T_4440 :
connect remapVecData[3], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[3]
node _T_4441 = eq(UInt<4>(0h8), remapindex_3)
when _T_4441 :
connect remapVecData[3], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[3]
node _T_4442 = eq(UInt<4>(0h9), remapindex_3)
when _T_4442 :
connect remapVecData[3], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[3]
node _T_4443 = eq(UInt<4>(0ha), remapindex_3)
when _T_4443 :
connect remapVecData[3], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[3]
node _T_4444 = eq(UInt<4>(0hb), remapindex_3)
when _T_4444 :
connect remapVecData[3], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[3]
node _T_4445 = eq(UInt<4>(0hc), remapindex_3)
when _T_4445 :
connect remapVecData[3], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[3]
node _T_4446 = eq(UInt<4>(0hd), remapindex_3)
when _T_4446 :
connect remapVecData[3], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[3]
node _T_4447 = eq(UInt<4>(0he), remapindex_3)
when _T_4447 :
connect remapVecData[3], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[3]
node _T_4448 = eq(UInt<4>(0hf), remapindex_3)
when _T_4448 :
connect remapVecData[3], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[3]
node _T_4449 = eq(UInt<5>(0h10), remapindex_3)
when _T_4449 :
connect remapVecData[3], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[3]
node _T_4450 = eq(UInt<5>(0h11), remapindex_3)
when _T_4450 :
connect remapVecData[3], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[3]
node _T_4451 = eq(UInt<5>(0h12), remapindex_3)
when _T_4451 :
connect remapVecData[3], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[3]
node _T_4452 = eq(UInt<5>(0h13), remapindex_3)
when _T_4452 :
connect remapVecData[3], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[3]
node _T_4453 = eq(UInt<5>(0h14), remapindex_3)
when _T_4453 :
connect remapVecData[3], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[3]
node _T_4454 = eq(UInt<5>(0h15), remapindex_3)
when _T_4454 :
connect remapVecData[3], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[3]
node _T_4455 = eq(UInt<5>(0h16), remapindex_3)
when _T_4455 :
connect remapVecData[3], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[3]
node _T_4456 = eq(UInt<5>(0h17), remapindex_3)
when _T_4456 :
connect remapVecData[3], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[3]
node _T_4457 = eq(UInt<5>(0h18), remapindex_3)
when _T_4457 :
connect remapVecData[3], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[3]
node _T_4458 = eq(UInt<5>(0h19), remapindex_3)
when _T_4458 :
connect remapVecData[3], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[3]
node _T_4459 = eq(UInt<5>(0h1a), remapindex_3)
when _T_4459 :
connect remapVecData[3], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[3]
node _T_4460 = eq(UInt<5>(0h1b), remapindex_3)
when _T_4460 :
connect remapVecData[3], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[3]
node _T_4461 = eq(UInt<5>(0h1c), remapindex_3)
when _T_4461 :
connect remapVecData[3], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[3]
node _T_4462 = eq(UInt<5>(0h1d), remapindex_3)
when _T_4462 :
connect remapVecData[3], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[3]
node _T_4463 = eq(UInt<5>(0h1e), remapindex_3)
when _T_4463 :
connect remapVecData[3], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[3]
node _T_4464 = eq(UInt<5>(0h1f), remapindex_3)
when _T_4464 :
connect remapVecData[3], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[3], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[3]
node _remapindex_T_4 = add(UInt<3>(0h4), read_start_index)
node remapindex_4 = rem(_remapindex_T_4, UInt<6>(0h20))
node _T_4465 = eq(UInt<1>(0h0), remapindex_4)
when _T_4465 :
connect remapVecData[4], Queue2_UInt8.io.deq.bits
connect remapVecValids[4], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[4]
node _T_4466 = eq(UInt<1>(0h1), remapindex_4)
when _T_4466 :
connect remapVecData[4], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[4]
node _T_4467 = eq(UInt<2>(0h2), remapindex_4)
when _T_4467 :
connect remapVecData[4], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[4]
node _T_4468 = eq(UInt<2>(0h3), remapindex_4)
when _T_4468 :
connect remapVecData[4], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[4]
node _T_4469 = eq(UInt<3>(0h4), remapindex_4)
when _T_4469 :
connect remapVecData[4], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[4]
node _T_4470 = eq(UInt<3>(0h5), remapindex_4)
when _T_4470 :
connect remapVecData[4], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[4]
node _T_4471 = eq(UInt<3>(0h6), remapindex_4)
when _T_4471 :
connect remapVecData[4], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[4]
node _T_4472 = eq(UInt<3>(0h7), remapindex_4)
when _T_4472 :
connect remapVecData[4], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[4]
node _T_4473 = eq(UInt<4>(0h8), remapindex_4)
when _T_4473 :
connect remapVecData[4], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[4]
node _T_4474 = eq(UInt<4>(0h9), remapindex_4)
when _T_4474 :
connect remapVecData[4], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[4]
node _T_4475 = eq(UInt<4>(0ha), remapindex_4)
when _T_4475 :
connect remapVecData[4], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[4]
node _T_4476 = eq(UInt<4>(0hb), remapindex_4)
when _T_4476 :
connect remapVecData[4], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[4]
node _T_4477 = eq(UInt<4>(0hc), remapindex_4)
when _T_4477 :
connect remapVecData[4], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[4]
node _T_4478 = eq(UInt<4>(0hd), remapindex_4)
when _T_4478 :
connect remapVecData[4], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[4]
node _T_4479 = eq(UInt<4>(0he), remapindex_4)
when _T_4479 :
connect remapVecData[4], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[4]
node _T_4480 = eq(UInt<4>(0hf), remapindex_4)
when _T_4480 :
connect remapVecData[4], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[4]
node _T_4481 = eq(UInt<5>(0h10), remapindex_4)
when _T_4481 :
connect remapVecData[4], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[4]
node _T_4482 = eq(UInt<5>(0h11), remapindex_4)
when _T_4482 :
connect remapVecData[4], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[4]
node _T_4483 = eq(UInt<5>(0h12), remapindex_4)
when _T_4483 :
connect remapVecData[4], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[4]
node _T_4484 = eq(UInt<5>(0h13), remapindex_4)
when _T_4484 :
connect remapVecData[4], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[4]
node _T_4485 = eq(UInt<5>(0h14), remapindex_4)
when _T_4485 :
connect remapVecData[4], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[4]
node _T_4486 = eq(UInt<5>(0h15), remapindex_4)
when _T_4486 :
connect remapVecData[4], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[4]
node _T_4487 = eq(UInt<5>(0h16), remapindex_4)
when _T_4487 :
connect remapVecData[4], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[4]
node _T_4488 = eq(UInt<5>(0h17), remapindex_4)
when _T_4488 :
connect remapVecData[4], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[4]
node _T_4489 = eq(UInt<5>(0h18), remapindex_4)
when _T_4489 :
connect remapVecData[4], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[4]
node _T_4490 = eq(UInt<5>(0h19), remapindex_4)
when _T_4490 :
connect remapVecData[4], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[4]
node _T_4491 = eq(UInt<5>(0h1a), remapindex_4)
when _T_4491 :
connect remapVecData[4], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[4]
node _T_4492 = eq(UInt<5>(0h1b), remapindex_4)
when _T_4492 :
connect remapVecData[4], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[4]
node _T_4493 = eq(UInt<5>(0h1c), remapindex_4)
when _T_4493 :
connect remapVecData[4], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[4]
node _T_4494 = eq(UInt<5>(0h1d), remapindex_4)
when _T_4494 :
connect remapVecData[4], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[4]
node _T_4495 = eq(UInt<5>(0h1e), remapindex_4)
when _T_4495 :
connect remapVecData[4], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[4]
node _T_4496 = eq(UInt<5>(0h1f), remapindex_4)
when _T_4496 :
connect remapVecData[4], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[4], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[4]
node _remapindex_T_5 = add(UInt<3>(0h5), read_start_index)
node remapindex_5 = rem(_remapindex_T_5, UInt<6>(0h20))
node _T_4497 = eq(UInt<1>(0h0), remapindex_5)
when _T_4497 :
connect remapVecData[5], Queue2_UInt8.io.deq.bits
connect remapVecValids[5], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[5]
node _T_4498 = eq(UInt<1>(0h1), remapindex_5)
when _T_4498 :
connect remapVecData[5], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[5]
node _T_4499 = eq(UInt<2>(0h2), remapindex_5)
when _T_4499 :
connect remapVecData[5], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[5]
node _T_4500 = eq(UInt<2>(0h3), remapindex_5)
when _T_4500 :
connect remapVecData[5], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[5]
node _T_4501 = eq(UInt<3>(0h4), remapindex_5)
when _T_4501 :
connect remapVecData[5], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[5]
node _T_4502 = eq(UInt<3>(0h5), remapindex_5)
when _T_4502 :
connect remapVecData[5], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[5]
node _T_4503 = eq(UInt<3>(0h6), remapindex_5)
when _T_4503 :
connect remapVecData[5], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[5]
node _T_4504 = eq(UInt<3>(0h7), remapindex_5)
when _T_4504 :
connect remapVecData[5], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[5]
node _T_4505 = eq(UInt<4>(0h8), remapindex_5)
when _T_4505 :
connect remapVecData[5], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[5]
node _T_4506 = eq(UInt<4>(0h9), remapindex_5)
when _T_4506 :
connect remapVecData[5], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[5]
node _T_4507 = eq(UInt<4>(0ha), remapindex_5)
when _T_4507 :
connect remapVecData[5], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[5]
node _T_4508 = eq(UInt<4>(0hb), remapindex_5)
when _T_4508 :
connect remapVecData[5], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[5]
node _T_4509 = eq(UInt<4>(0hc), remapindex_5)
when _T_4509 :
connect remapVecData[5], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[5]
node _T_4510 = eq(UInt<4>(0hd), remapindex_5)
when _T_4510 :
connect remapVecData[5], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[5]
node _T_4511 = eq(UInt<4>(0he), remapindex_5)
when _T_4511 :
connect remapVecData[5], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[5]
node _T_4512 = eq(UInt<4>(0hf), remapindex_5)
when _T_4512 :
connect remapVecData[5], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[5]
node _T_4513 = eq(UInt<5>(0h10), remapindex_5)
when _T_4513 :
connect remapVecData[5], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[5]
node _T_4514 = eq(UInt<5>(0h11), remapindex_5)
when _T_4514 :
connect remapVecData[5], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[5]
node _T_4515 = eq(UInt<5>(0h12), remapindex_5)
when _T_4515 :
connect remapVecData[5], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[5]
node _T_4516 = eq(UInt<5>(0h13), remapindex_5)
when _T_4516 :
connect remapVecData[5], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[5]
node _T_4517 = eq(UInt<5>(0h14), remapindex_5)
when _T_4517 :
connect remapVecData[5], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[5]
node _T_4518 = eq(UInt<5>(0h15), remapindex_5)
when _T_4518 :
connect remapVecData[5], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[5]
node _T_4519 = eq(UInt<5>(0h16), remapindex_5)
when _T_4519 :
connect remapVecData[5], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[5]
node _T_4520 = eq(UInt<5>(0h17), remapindex_5)
when _T_4520 :
connect remapVecData[5], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[5]
node _T_4521 = eq(UInt<5>(0h18), remapindex_5)
when _T_4521 :
connect remapVecData[5], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[5]
node _T_4522 = eq(UInt<5>(0h19), remapindex_5)
when _T_4522 :
connect remapVecData[5], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[5]
node _T_4523 = eq(UInt<5>(0h1a), remapindex_5)
when _T_4523 :
connect remapVecData[5], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[5]
node _T_4524 = eq(UInt<5>(0h1b), remapindex_5)
when _T_4524 :
connect remapVecData[5], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[5]
node _T_4525 = eq(UInt<5>(0h1c), remapindex_5)
when _T_4525 :
connect remapVecData[5], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[5]
node _T_4526 = eq(UInt<5>(0h1d), remapindex_5)
when _T_4526 :
connect remapVecData[5], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[5]
node _T_4527 = eq(UInt<5>(0h1e), remapindex_5)
when _T_4527 :
connect remapVecData[5], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[5]
node _T_4528 = eq(UInt<5>(0h1f), remapindex_5)
when _T_4528 :
connect remapVecData[5], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[5], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[5]
node _remapindex_T_6 = add(UInt<3>(0h6), read_start_index)
node remapindex_6 = rem(_remapindex_T_6, UInt<6>(0h20))
node _T_4529 = eq(UInt<1>(0h0), remapindex_6)
when _T_4529 :
connect remapVecData[6], Queue2_UInt8.io.deq.bits
connect remapVecValids[6], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[6]
node _T_4530 = eq(UInt<1>(0h1), remapindex_6)
when _T_4530 :
connect remapVecData[6], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[6]
node _T_4531 = eq(UInt<2>(0h2), remapindex_6)
when _T_4531 :
connect remapVecData[6], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[6]
node _T_4532 = eq(UInt<2>(0h3), remapindex_6)
when _T_4532 :
connect remapVecData[6], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[6]
node _T_4533 = eq(UInt<3>(0h4), remapindex_6)
when _T_4533 :
connect remapVecData[6], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[6]
node _T_4534 = eq(UInt<3>(0h5), remapindex_6)
when _T_4534 :
connect remapVecData[6], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[6]
node _T_4535 = eq(UInt<3>(0h6), remapindex_6)
when _T_4535 :
connect remapVecData[6], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[6]
node _T_4536 = eq(UInt<3>(0h7), remapindex_6)
when _T_4536 :
connect remapVecData[6], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[6]
node _T_4537 = eq(UInt<4>(0h8), remapindex_6)
when _T_4537 :
connect remapVecData[6], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[6]
node _T_4538 = eq(UInt<4>(0h9), remapindex_6)
when _T_4538 :
connect remapVecData[6], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[6]
node _T_4539 = eq(UInt<4>(0ha), remapindex_6)
when _T_4539 :
connect remapVecData[6], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[6]
node _T_4540 = eq(UInt<4>(0hb), remapindex_6)
when _T_4540 :
connect remapVecData[6], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[6]
node _T_4541 = eq(UInt<4>(0hc), remapindex_6)
when _T_4541 :
connect remapVecData[6], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[6]
node _T_4542 = eq(UInt<4>(0hd), remapindex_6)
when _T_4542 :
connect remapVecData[6], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[6]
node _T_4543 = eq(UInt<4>(0he), remapindex_6)
when _T_4543 :
connect remapVecData[6], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[6]
node _T_4544 = eq(UInt<4>(0hf), remapindex_6)
when _T_4544 :
connect remapVecData[6], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[6]
node _T_4545 = eq(UInt<5>(0h10), remapindex_6)
when _T_4545 :
connect remapVecData[6], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[6]
node _T_4546 = eq(UInt<5>(0h11), remapindex_6)
when _T_4546 :
connect remapVecData[6], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[6]
node _T_4547 = eq(UInt<5>(0h12), remapindex_6)
when _T_4547 :
connect remapVecData[6], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[6]
node _T_4548 = eq(UInt<5>(0h13), remapindex_6)
when _T_4548 :
connect remapVecData[6], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[6]
node _T_4549 = eq(UInt<5>(0h14), remapindex_6)
when _T_4549 :
connect remapVecData[6], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[6]
node _T_4550 = eq(UInt<5>(0h15), remapindex_6)
when _T_4550 :
connect remapVecData[6], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[6]
node _T_4551 = eq(UInt<5>(0h16), remapindex_6)
when _T_4551 :
connect remapVecData[6], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[6]
node _T_4552 = eq(UInt<5>(0h17), remapindex_6)
when _T_4552 :
connect remapVecData[6], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[6]
node _T_4553 = eq(UInt<5>(0h18), remapindex_6)
when _T_4553 :
connect remapVecData[6], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[6]
node _T_4554 = eq(UInt<5>(0h19), remapindex_6)
when _T_4554 :
connect remapVecData[6], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[6]
node _T_4555 = eq(UInt<5>(0h1a), remapindex_6)
when _T_4555 :
connect remapVecData[6], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[6]
node _T_4556 = eq(UInt<5>(0h1b), remapindex_6)
when _T_4556 :
connect remapVecData[6], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[6]
node _T_4557 = eq(UInt<5>(0h1c), remapindex_6)
when _T_4557 :
connect remapVecData[6], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[6]
node _T_4558 = eq(UInt<5>(0h1d), remapindex_6)
when _T_4558 :
connect remapVecData[6], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[6]
node _T_4559 = eq(UInt<5>(0h1e), remapindex_6)
when _T_4559 :
connect remapVecData[6], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[6]
node _T_4560 = eq(UInt<5>(0h1f), remapindex_6)
when _T_4560 :
connect remapVecData[6], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[6], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[6]
node _remapindex_T_7 = add(UInt<3>(0h7), read_start_index)
node remapindex_7 = rem(_remapindex_T_7, UInt<6>(0h20))
node _T_4561 = eq(UInt<1>(0h0), remapindex_7)
when _T_4561 :
connect remapVecData[7], Queue2_UInt8.io.deq.bits
connect remapVecValids[7], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[7]
node _T_4562 = eq(UInt<1>(0h1), remapindex_7)
when _T_4562 :
connect remapVecData[7], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[7]
node _T_4563 = eq(UInt<2>(0h2), remapindex_7)
when _T_4563 :
connect remapVecData[7], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[7]
node _T_4564 = eq(UInt<2>(0h3), remapindex_7)
when _T_4564 :
connect remapVecData[7], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[7]
node _T_4565 = eq(UInt<3>(0h4), remapindex_7)
when _T_4565 :
connect remapVecData[7], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[7]
node _T_4566 = eq(UInt<3>(0h5), remapindex_7)
when _T_4566 :
connect remapVecData[7], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[7]
node _T_4567 = eq(UInt<3>(0h6), remapindex_7)
when _T_4567 :
connect remapVecData[7], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[7]
node _T_4568 = eq(UInt<3>(0h7), remapindex_7)
when _T_4568 :
connect remapVecData[7], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[7]
node _T_4569 = eq(UInt<4>(0h8), remapindex_7)
when _T_4569 :
connect remapVecData[7], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[7]
node _T_4570 = eq(UInt<4>(0h9), remapindex_7)
when _T_4570 :
connect remapVecData[7], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[7]
node _T_4571 = eq(UInt<4>(0ha), remapindex_7)
when _T_4571 :
connect remapVecData[7], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[7]
node _T_4572 = eq(UInt<4>(0hb), remapindex_7)
when _T_4572 :
connect remapVecData[7], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[7]
node _T_4573 = eq(UInt<4>(0hc), remapindex_7)
when _T_4573 :
connect remapVecData[7], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[7]
node _T_4574 = eq(UInt<4>(0hd), remapindex_7)
when _T_4574 :
connect remapVecData[7], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[7]
node _T_4575 = eq(UInt<4>(0he), remapindex_7)
when _T_4575 :
connect remapVecData[7], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[7]
node _T_4576 = eq(UInt<4>(0hf), remapindex_7)
when _T_4576 :
connect remapVecData[7], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[7]
node _T_4577 = eq(UInt<5>(0h10), remapindex_7)
when _T_4577 :
connect remapVecData[7], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[7]
node _T_4578 = eq(UInt<5>(0h11), remapindex_7)
when _T_4578 :
connect remapVecData[7], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[7]
node _T_4579 = eq(UInt<5>(0h12), remapindex_7)
when _T_4579 :
connect remapVecData[7], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[7]
node _T_4580 = eq(UInt<5>(0h13), remapindex_7)
when _T_4580 :
connect remapVecData[7], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[7]
node _T_4581 = eq(UInt<5>(0h14), remapindex_7)
when _T_4581 :
connect remapVecData[7], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[7]
node _T_4582 = eq(UInt<5>(0h15), remapindex_7)
when _T_4582 :
connect remapVecData[7], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[7]
node _T_4583 = eq(UInt<5>(0h16), remapindex_7)
when _T_4583 :
connect remapVecData[7], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[7]
node _T_4584 = eq(UInt<5>(0h17), remapindex_7)
when _T_4584 :
connect remapVecData[7], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[7]
node _T_4585 = eq(UInt<5>(0h18), remapindex_7)
when _T_4585 :
connect remapVecData[7], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[7]
node _T_4586 = eq(UInt<5>(0h19), remapindex_7)
when _T_4586 :
connect remapVecData[7], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[7]
node _T_4587 = eq(UInt<5>(0h1a), remapindex_7)
when _T_4587 :
connect remapVecData[7], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[7]
node _T_4588 = eq(UInt<5>(0h1b), remapindex_7)
when _T_4588 :
connect remapVecData[7], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[7]
node _T_4589 = eq(UInt<5>(0h1c), remapindex_7)
when _T_4589 :
connect remapVecData[7], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[7]
node _T_4590 = eq(UInt<5>(0h1d), remapindex_7)
when _T_4590 :
connect remapVecData[7], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[7]
node _T_4591 = eq(UInt<5>(0h1e), remapindex_7)
when _T_4591 :
connect remapVecData[7], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[7]
node _T_4592 = eq(UInt<5>(0h1f), remapindex_7)
when _T_4592 :
connect remapVecData[7], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[7], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[7]
node _remapindex_T_8 = add(UInt<4>(0h8), read_start_index)
node remapindex_8 = rem(_remapindex_T_8, UInt<6>(0h20))
node _T_4593 = eq(UInt<1>(0h0), remapindex_8)
when _T_4593 :
connect remapVecData[8], Queue2_UInt8.io.deq.bits
connect remapVecValids[8], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[8]
node _T_4594 = eq(UInt<1>(0h1), remapindex_8)
when _T_4594 :
connect remapVecData[8], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[8]
node _T_4595 = eq(UInt<2>(0h2), remapindex_8)
when _T_4595 :
connect remapVecData[8], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[8]
node _T_4596 = eq(UInt<2>(0h3), remapindex_8)
when _T_4596 :
connect remapVecData[8], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[8]
node _T_4597 = eq(UInt<3>(0h4), remapindex_8)
when _T_4597 :
connect remapVecData[8], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[8]
node _T_4598 = eq(UInt<3>(0h5), remapindex_8)
when _T_4598 :
connect remapVecData[8], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[8]
node _T_4599 = eq(UInt<3>(0h6), remapindex_8)
when _T_4599 :
connect remapVecData[8], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[8]
node _T_4600 = eq(UInt<3>(0h7), remapindex_8)
when _T_4600 :
connect remapVecData[8], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[8]
node _T_4601 = eq(UInt<4>(0h8), remapindex_8)
when _T_4601 :
connect remapVecData[8], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[8]
node _T_4602 = eq(UInt<4>(0h9), remapindex_8)
when _T_4602 :
connect remapVecData[8], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[8]
node _T_4603 = eq(UInt<4>(0ha), remapindex_8)
when _T_4603 :
connect remapVecData[8], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[8]
node _T_4604 = eq(UInt<4>(0hb), remapindex_8)
when _T_4604 :
connect remapVecData[8], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[8]
node _T_4605 = eq(UInt<4>(0hc), remapindex_8)
when _T_4605 :
connect remapVecData[8], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[8]
node _T_4606 = eq(UInt<4>(0hd), remapindex_8)
when _T_4606 :
connect remapVecData[8], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[8]
node _T_4607 = eq(UInt<4>(0he), remapindex_8)
when _T_4607 :
connect remapVecData[8], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[8]
node _T_4608 = eq(UInt<4>(0hf), remapindex_8)
when _T_4608 :
connect remapVecData[8], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[8]
node _T_4609 = eq(UInt<5>(0h10), remapindex_8)
when _T_4609 :
connect remapVecData[8], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[8]
node _T_4610 = eq(UInt<5>(0h11), remapindex_8)
when _T_4610 :
connect remapVecData[8], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[8]
node _T_4611 = eq(UInt<5>(0h12), remapindex_8)
when _T_4611 :
connect remapVecData[8], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[8]
node _T_4612 = eq(UInt<5>(0h13), remapindex_8)
when _T_4612 :
connect remapVecData[8], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[8]
node _T_4613 = eq(UInt<5>(0h14), remapindex_8)
when _T_4613 :
connect remapVecData[8], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[8]
node _T_4614 = eq(UInt<5>(0h15), remapindex_8)
when _T_4614 :
connect remapVecData[8], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[8]
node _T_4615 = eq(UInt<5>(0h16), remapindex_8)
when _T_4615 :
connect remapVecData[8], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[8]
node _T_4616 = eq(UInt<5>(0h17), remapindex_8)
when _T_4616 :
connect remapVecData[8], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[8]
node _T_4617 = eq(UInt<5>(0h18), remapindex_8)
when _T_4617 :
connect remapVecData[8], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[8]
node _T_4618 = eq(UInt<5>(0h19), remapindex_8)
when _T_4618 :
connect remapVecData[8], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[8]
node _T_4619 = eq(UInt<5>(0h1a), remapindex_8)
when _T_4619 :
connect remapVecData[8], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[8]
node _T_4620 = eq(UInt<5>(0h1b), remapindex_8)
when _T_4620 :
connect remapVecData[8], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[8]
node _T_4621 = eq(UInt<5>(0h1c), remapindex_8)
when _T_4621 :
connect remapVecData[8], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[8]
node _T_4622 = eq(UInt<5>(0h1d), remapindex_8)
when _T_4622 :
connect remapVecData[8], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[8]
node _T_4623 = eq(UInt<5>(0h1e), remapindex_8)
when _T_4623 :
connect remapVecData[8], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[8]
node _T_4624 = eq(UInt<5>(0h1f), remapindex_8)
when _T_4624 :
connect remapVecData[8], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[8], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[8]
node _remapindex_T_9 = add(UInt<4>(0h9), read_start_index)
node remapindex_9 = rem(_remapindex_T_9, UInt<6>(0h20))
node _T_4625 = eq(UInt<1>(0h0), remapindex_9)
when _T_4625 :
connect remapVecData[9], Queue2_UInt8.io.deq.bits
connect remapVecValids[9], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[9]
node _T_4626 = eq(UInt<1>(0h1), remapindex_9)
when _T_4626 :
connect remapVecData[9], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[9]
node _T_4627 = eq(UInt<2>(0h2), remapindex_9)
when _T_4627 :
connect remapVecData[9], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[9]
node _T_4628 = eq(UInt<2>(0h3), remapindex_9)
when _T_4628 :
connect remapVecData[9], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[9]
node _T_4629 = eq(UInt<3>(0h4), remapindex_9)
when _T_4629 :
connect remapVecData[9], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[9]
node _T_4630 = eq(UInt<3>(0h5), remapindex_9)
when _T_4630 :
connect remapVecData[9], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[9]
node _T_4631 = eq(UInt<3>(0h6), remapindex_9)
when _T_4631 :
connect remapVecData[9], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[9]
node _T_4632 = eq(UInt<3>(0h7), remapindex_9)
when _T_4632 :
connect remapVecData[9], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[9]
node _T_4633 = eq(UInt<4>(0h8), remapindex_9)
when _T_4633 :
connect remapVecData[9], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[9]
node _T_4634 = eq(UInt<4>(0h9), remapindex_9)
when _T_4634 :
connect remapVecData[9], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[9]
node _T_4635 = eq(UInt<4>(0ha), remapindex_9)
when _T_4635 :
connect remapVecData[9], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[9]
node _T_4636 = eq(UInt<4>(0hb), remapindex_9)
when _T_4636 :
connect remapVecData[9], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[9]
node _T_4637 = eq(UInt<4>(0hc), remapindex_9)
when _T_4637 :
connect remapVecData[9], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[9]
node _T_4638 = eq(UInt<4>(0hd), remapindex_9)
when _T_4638 :
connect remapVecData[9], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[9]
node _T_4639 = eq(UInt<4>(0he), remapindex_9)
when _T_4639 :
connect remapVecData[9], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[9]
node _T_4640 = eq(UInt<4>(0hf), remapindex_9)
when _T_4640 :
connect remapVecData[9], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[9]
node _T_4641 = eq(UInt<5>(0h10), remapindex_9)
when _T_4641 :
connect remapVecData[9], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[9]
node _T_4642 = eq(UInt<5>(0h11), remapindex_9)
when _T_4642 :
connect remapVecData[9], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[9]
node _T_4643 = eq(UInt<5>(0h12), remapindex_9)
when _T_4643 :
connect remapVecData[9], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[9]
node _T_4644 = eq(UInt<5>(0h13), remapindex_9)
when _T_4644 :
connect remapVecData[9], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[9]
node _T_4645 = eq(UInt<5>(0h14), remapindex_9)
when _T_4645 :
connect remapVecData[9], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[9]
node _T_4646 = eq(UInt<5>(0h15), remapindex_9)
when _T_4646 :
connect remapVecData[9], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[9]
node _T_4647 = eq(UInt<5>(0h16), remapindex_9)
when _T_4647 :
connect remapVecData[9], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[9]
node _T_4648 = eq(UInt<5>(0h17), remapindex_9)
when _T_4648 :
connect remapVecData[9], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[9]
node _T_4649 = eq(UInt<5>(0h18), remapindex_9)
when _T_4649 :
connect remapVecData[9], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[9]
node _T_4650 = eq(UInt<5>(0h19), remapindex_9)
when _T_4650 :
connect remapVecData[9], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[9]
node _T_4651 = eq(UInt<5>(0h1a), remapindex_9)
when _T_4651 :
connect remapVecData[9], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[9]
node _T_4652 = eq(UInt<5>(0h1b), remapindex_9)
when _T_4652 :
connect remapVecData[9], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[9]
node _T_4653 = eq(UInt<5>(0h1c), remapindex_9)
when _T_4653 :
connect remapVecData[9], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[9]
node _T_4654 = eq(UInt<5>(0h1d), remapindex_9)
when _T_4654 :
connect remapVecData[9], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[9]
node _T_4655 = eq(UInt<5>(0h1e), remapindex_9)
when _T_4655 :
connect remapVecData[9], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[9]
node _T_4656 = eq(UInt<5>(0h1f), remapindex_9)
when _T_4656 :
connect remapVecData[9], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[9], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[9]
node _remapindex_T_10 = add(UInt<4>(0ha), read_start_index)
node remapindex_10 = rem(_remapindex_T_10, UInt<6>(0h20))
node _T_4657 = eq(UInt<1>(0h0), remapindex_10)
when _T_4657 :
connect remapVecData[10], Queue2_UInt8.io.deq.bits
connect remapVecValids[10], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[10]
node _T_4658 = eq(UInt<1>(0h1), remapindex_10)
when _T_4658 :
connect remapVecData[10], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[10]
node _T_4659 = eq(UInt<2>(0h2), remapindex_10)
when _T_4659 :
connect remapVecData[10], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[10]
node _T_4660 = eq(UInt<2>(0h3), remapindex_10)
when _T_4660 :
connect remapVecData[10], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[10]
node _T_4661 = eq(UInt<3>(0h4), remapindex_10)
when _T_4661 :
connect remapVecData[10], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[10]
node _T_4662 = eq(UInt<3>(0h5), remapindex_10)
when _T_4662 :
connect remapVecData[10], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[10]
node _T_4663 = eq(UInt<3>(0h6), remapindex_10)
when _T_4663 :
connect remapVecData[10], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[10]
node _T_4664 = eq(UInt<3>(0h7), remapindex_10)
when _T_4664 :
connect remapVecData[10], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[10]
node _T_4665 = eq(UInt<4>(0h8), remapindex_10)
when _T_4665 :
connect remapVecData[10], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[10]
node _T_4666 = eq(UInt<4>(0h9), remapindex_10)
when _T_4666 :
connect remapVecData[10], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[10]
node _T_4667 = eq(UInt<4>(0ha), remapindex_10)
when _T_4667 :
connect remapVecData[10], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[10]
node _T_4668 = eq(UInt<4>(0hb), remapindex_10)
when _T_4668 :
connect remapVecData[10], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[10]
node _T_4669 = eq(UInt<4>(0hc), remapindex_10)
when _T_4669 :
connect remapVecData[10], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[10]
node _T_4670 = eq(UInt<4>(0hd), remapindex_10)
when _T_4670 :
connect remapVecData[10], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[10]
node _T_4671 = eq(UInt<4>(0he), remapindex_10)
when _T_4671 :
connect remapVecData[10], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[10]
node _T_4672 = eq(UInt<4>(0hf), remapindex_10)
when _T_4672 :
connect remapVecData[10], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[10]
node _T_4673 = eq(UInt<5>(0h10), remapindex_10)
when _T_4673 :
connect remapVecData[10], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[10]
node _T_4674 = eq(UInt<5>(0h11), remapindex_10)
when _T_4674 :
connect remapVecData[10], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[10]
node _T_4675 = eq(UInt<5>(0h12), remapindex_10)
when _T_4675 :
connect remapVecData[10], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[10]
node _T_4676 = eq(UInt<5>(0h13), remapindex_10)
when _T_4676 :
connect remapVecData[10], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[10]
node _T_4677 = eq(UInt<5>(0h14), remapindex_10)
when _T_4677 :
connect remapVecData[10], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[10]
node _T_4678 = eq(UInt<5>(0h15), remapindex_10)
when _T_4678 :
connect remapVecData[10], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[10]
node _T_4679 = eq(UInt<5>(0h16), remapindex_10)
when _T_4679 :
connect remapVecData[10], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[10]
node _T_4680 = eq(UInt<5>(0h17), remapindex_10)
when _T_4680 :
connect remapVecData[10], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[10]
node _T_4681 = eq(UInt<5>(0h18), remapindex_10)
when _T_4681 :
connect remapVecData[10], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[10]
node _T_4682 = eq(UInt<5>(0h19), remapindex_10)
when _T_4682 :
connect remapVecData[10], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[10]
node _T_4683 = eq(UInt<5>(0h1a), remapindex_10)
when _T_4683 :
connect remapVecData[10], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[10]
node _T_4684 = eq(UInt<5>(0h1b), remapindex_10)
when _T_4684 :
connect remapVecData[10], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[10]
node _T_4685 = eq(UInt<5>(0h1c), remapindex_10)
when _T_4685 :
connect remapVecData[10], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[10]
node _T_4686 = eq(UInt<5>(0h1d), remapindex_10)
when _T_4686 :
connect remapVecData[10], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[10]
node _T_4687 = eq(UInt<5>(0h1e), remapindex_10)
when _T_4687 :
connect remapVecData[10], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[10]
node _T_4688 = eq(UInt<5>(0h1f), remapindex_10)
when _T_4688 :
connect remapVecData[10], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[10], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[10]
node _remapindex_T_11 = add(UInt<4>(0hb), read_start_index)
node remapindex_11 = rem(_remapindex_T_11, UInt<6>(0h20))
node _T_4689 = eq(UInt<1>(0h0), remapindex_11)
when _T_4689 :
connect remapVecData[11], Queue2_UInt8.io.deq.bits
connect remapVecValids[11], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[11]
node _T_4690 = eq(UInt<1>(0h1), remapindex_11)
when _T_4690 :
connect remapVecData[11], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[11]
node _T_4691 = eq(UInt<2>(0h2), remapindex_11)
when _T_4691 :
connect remapVecData[11], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[11]
node _T_4692 = eq(UInt<2>(0h3), remapindex_11)
when _T_4692 :
connect remapVecData[11], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[11]
node _T_4693 = eq(UInt<3>(0h4), remapindex_11)
when _T_4693 :
connect remapVecData[11], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[11]
node _T_4694 = eq(UInt<3>(0h5), remapindex_11)
when _T_4694 :
connect remapVecData[11], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[11]
node _T_4695 = eq(UInt<3>(0h6), remapindex_11)
when _T_4695 :
connect remapVecData[11], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[11]
node _T_4696 = eq(UInt<3>(0h7), remapindex_11)
when _T_4696 :
connect remapVecData[11], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[11]
node _T_4697 = eq(UInt<4>(0h8), remapindex_11)
when _T_4697 :
connect remapVecData[11], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[11]
node _T_4698 = eq(UInt<4>(0h9), remapindex_11)
when _T_4698 :
connect remapVecData[11], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[11]
node _T_4699 = eq(UInt<4>(0ha), remapindex_11)
when _T_4699 :
connect remapVecData[11], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[11]
node _T_4700 = eq(UInt<4>(0hb), remapindex_11)
when _T_4700 :
connect remapVecData[11], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[11]
node _T_4701 = eq(UInt<4>(0hc), remapindex_11)
when _T_4701 :
connect remapVecData[11], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[11]
node _T_4702 = eq(UInt<4>(0hd), remapindex_11)
when _T_4702 :
connect remapVecData[11], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[11]
node _T_4703 = eq(UInt<4>(0he), remapindex_11)
when _T_4703 :
connect remapVecData[11], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[11]
node _T_4704 = eq(UInt<4>(0hf), remapindex_11)
when _T_4704 :
connect remapVecData[11], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[11]
node _T_4705 = eq(UInt<5>(0h10), remapindex_11)
when _T_4705 :
connect remapVecData[11], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[11]
node _T_4706 = eq(UInt<5>(0h11), remapindex_11)
when _T_4706 :
connect remapVecData[11], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[11]
node _T_4707 = eq(UInt<5>(0h12), remapindex_11)
when _T_4707 :
connect remapVecData[11], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[11]
node _T_4708 = eq(UInt<5>(0h13), remapindex_11)
when _T_4708 :
connect remapVecData[11], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[11]
node _T_4709 = eq(UInt<5>(0h14), remapindex_11)
when _T_4709 :
connect remapVecData[11], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[11]
node _T_4710 = eq(UInt<5>(0h15), remapindex_11)
when _T_4710 :
connect remapVecData[11], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[11]
node _T_4711 = eq(UInt<5>(0h16), remapindex_11)
when _T_4711 :
connect remapVecData[11], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[11]
node _T_4712 = eq(UInt<5>(0h17), remapindex_11)
when _T_4712 :
connect remapVecData[11], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[11]
node _T_4713 = eq(UInt<5>(0h18), remapindex_11)
when _T_4713 :
connect remapVecData[11], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[11]
node _T_4714 = eq(UInt<5>(0h19), remapindex_11)
when _T_4714 :
connect remapVecData[11], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[11]
node _T_4715 = eq(UInt<5>(0h1a), remapindex_11)
when _T_4715 :
connect remapVecData[11], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[11]
node _T_4716 = eq(UInt<5>(0h1b), remapindex_11)
when _T_4716 :
connect remapVecData[11], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[11]
node _T_4717 = eq(UInt<5>(0h1c), remapindex_11)
when _T_4717 :
connect remapVecData[11], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[11]
node _T_4718 = eq(UInt<5>(0h1d), remapindex_11)
when _T_4718 :
connect remapVecData[11], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[11]
node _T_4719 = eq(UInt<5>(0h1e), remapindex_11)
when _T_4719 :
connect remapVecData[11], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[11]
node _T_4720 = eq(UInt<5>(0h1f), remapindex_11)
when _T_4720 :
connect remapVecData[11], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[11], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[11]
node _remapindex_T_12 = add(UInt<4>(0hc), read_start_index)
node remapindex_12 = rem(_remapindex_T_12, UInt<6>(0h20))
node _T_4721 = eq(UInt<1>(0h0), remapindex_12)
when _T_4721 :
connect remapVecData[12], Queue2_UInt8.io.deq.bits
connect remapVecValids[12], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[12]
node _T_4722 = eq(UInt<1>(0h1), remapindex_12)
when _T_4722 :
connect remapVecData[12], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[12]
node _T_4723 = eq(UInt<2>(0h2), remapindex_12)
when _T_4723 :
connect remapVecData[12], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[12]
node _T_4724 = eq(UInt<2>(0h3), remapindex_12)
when _T_4724 :
connect remapVecData[12], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[12]
node _T_4725 = eq(UInt<3>(0h4), remapindex_12)
when _T_4725 :
connect remapVecData[12], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[12]
node _T_4726 = eq(UInt<3>(0h5), remapindex_12)
when _T_4726 :
connect remapVecData[12], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[12]
node _T_4727 = eq(UInt<3>(0h6), remapindex_12)
when _T_4727 :
connect remapVecData[12], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[12]
node _T_4728 = eq(UInt<3>(0h7), remapindex_12)
when _T_4728 :
connect remapVecData[12], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[12]
node _T_4729 = eq(UInt<4>(0h8), remapindex_12)
when _T_4729 :
connect remapVecData[12], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[12]
node _T_4730 = eq(UInt<4>(0h9), remapindex_12)
when _T_4730 :
connect remapVecData[12], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[12]
node _T_4731 = eq(UInt<4>(0ha), remapindex_12)
when _T_4731 :
connect remapVecData[12], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[12]
node _T_4732 = eq(UInt<4>(0hb), remapindex_12)
when _T_4732 :
connect remapVecData[12], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[12]
node _T_4733 = eq(UInt<4>(0hc), remapindex_12)
when _T_4733 :
connect remapVecData[12], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[12]
node _T_4734 = eq(UInt<4>(0hd), remapindex_12)
when _T_4734 :
connect remapVecData[12], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[12]
node _T_4735 = eq(UInt<4>(0he), remapindex_12)
when _T_4735 :
connect remapVecData[12], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[12]
node _T_4736 = eq(UInt<4>(0hf), remapindex_12)
when _T_4736 :
connect remapVecData[12], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[12]
node _T_4737 = eq(UInt<5>(0h10), remapindex_12)
when _T_4737 :
connect remapVecData[12], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[12]
node _T_4738 = eq(UInt<5>(0h11), remapindex_12)
when _T_4738 :
connect remapVecData[12], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[12]
node _T_4739 = eq(UInt<5>(0h12), remapindex_12)
when _T_4739 :
connect remapVecData[12], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[12]
node _T_4740 = eq(UInt<5>(0h13), remapindex_12)
when _T_4740 :
connect remapVecData[12], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[12]
node _T_4741 = eq(UInt<5>(0h14), remapindex_12)
when _T_4741 :
connect remapVecData[12], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[12]
node _T_4742 = eq(UInt<5>(0h15), remapindex_12)
when _T_4742 :
connect remapVecData[12], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[12]
node _T_4743 = eq(UInt<5>(0h16), remapindex_12)
when _T_4743 :
connect remapVecData[12], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[12]
node _T_4744 = eq(UInt<5>(0h17), remapindex_12)
when _T_4744 :
connect remapVecData[12], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[12]
node _T_4745 = eq(UInt<5>(0h18), remapindex_12)
when _T_4745 :
connect remapVecData[12], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[12]
node _T_4746 = eq(UInt<5>(0h19), remapindex_12)
when _T_4746 :
connect remapVecData[12], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[12]
node _T_4747 = eq(UInt<5>(0h1a), remapindex_12)
when _T_4747 :
connect remapVecData[12], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[12]
node _T_4748 = eq(UInt<5>(0h1b), remapindex_12)
when _T_4748 :
connect remapVecData[12], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[12]
node _T_4749 = eq(UInt<5>(0h1c), remapindex_12)
when _T_4749 :
connect remapVecData[12], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[12]
node _T_4750 = eq(UInt<5>(0h1d), remapindex_12)
when _T_4750 :
connect remapVecData[12], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[12]
node _T_4751 = eq(UInt<5>(0h1e), remapindex_12)
when _T_4751 :
connect remapVecData[12], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[12]
node _T_4752 = eq(UInt<5>(0h1f), remapindex_12)
when _T_4752 :
connect remapVecData[12], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[12], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[12]
node _remapindex_T_13 = add(UInt<4>(0hd), read_start_index)
node remapindex_13 = rem(_remapindex_T_13, UInt<6>(0h20))
node _T_4753 = eq(UInt<1>(0h0), remapindex_13)
when _T_4753 :
connect remapVecData[13], Queue2_UInt8.io.deq.bits
connect remapVecValids[13], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[13]
node _T_4754 = eq(UInt<1>(0h1), remapindex_13)
when _T_4754 :
connect remapVecData[13], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[13]
node _T_4755 = eq(UInt<2>(0h2), remapindex_13)
when _T_4755 :
connect remapVecData[13], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[13]
node _T_4756 = eq(UInt<2>(0h3), remapindex_13)
when _T_4756 :
connect remapVecData[13], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[13]
node _T_4757 = eq(UInt<3>(0h4), remapindex_13)
when _T_4757 :
connect remapVecData[13], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[13]
node _T_4758 = eq(UInt<3>(0h5), remapindex_13)
when _T_4758 :
connect remapVecData[13], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[13]
node _T_4759 = eq(UInt<3>(0h6), remapindex_13)
when _T_4759 :
connect remapVecData[13], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[13]
node _T_4760 = eq(UInt<3>(0h7), remapindex_13)
when _T_4760 :
connect remapVecData[13], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[13]
node _T_4761 = eq(UInt<4>(0h8), remapindex_13)
when _T_4761 :
connect remapVecData[13], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[13]
node _T_4762 = eq(UInt<4>(0h9), remapindex_13)
when _T_4762 :
connect remapVecData[13], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[13]
node _T_4763 = eq(UInt<4>(0ha), remapindex_13)
when _T_4763 :
connect remapVecData[13], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[13]
node _T_4764 = eq(UInt<4>(0hb), remapindex_13)
when _T_4764 :
connect remapVecData[13], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[13]
node _T_4765 = eq(UInt<4>(0hc), remapindex_13)
when _T_4765 :
connect remapVecData[13], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[13]
node _T_4766 = eq(UInt<4>(0hd), remapindex_13)
when _T_4766 :
connect remapVecData[13], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[13]
node _T_4767 = eq(UInt<4>(0he), remapindex_13)
when _T_4767 :
connect remapVecData[13], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[13]
node _T_4768 = eq(UInt<4>(0hf), remapindex_13)
when _T_4768 :
connect remapVecData[13], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[13]
node _T_4769 = eq(UInt<5>(0h10), remapindex_13)
when _T_4769 :
connect remapVecData[13], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[13]
node _T_4770 = eq(UInt<5>(0h11), remapindex_13)
when _T_4770 :
connect remapVecData[13], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[13]
node _T_4771 = eq(UInt<5>(0h12), remapindex_13)
when _T_4771 :
connect remapVecData[13], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[13]
node _T_4772 = eq(UInt<5>(0h13), remapindex_13)
when _T_4772 :
connect remapVecData[13], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[13]
node _T_4773 = eq(UInt<5>(0h14), remapindex_13)
when _T_4773 :
connect remapVecData[13], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[13]
node _T_4774 = eq(UInt<5>(0h15), remapindex_13)
when _T_4774 :
connect remapVecData[13], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[13]
node _T_4775 = eq(UInt<5>(0h16), remapindex_13)
when _T_4775 :
connect remapVecData[13], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[13]
node _T_4776 = eq(UInt<5>(0h17), remapindex_13)
when _T_4776 :
connect remapVecData[13], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[13]
node _T_4777 = eq(UInt<5>(0h18), remapindex_13)
when _T_4777 :
connect remapVecData[13], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[13]
node _T_4778 = eq(UInt<5>(0h19), remapindex_13)
when _T_4778 :
connect remapVecData[13], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[13]
node _T_4779 = eq(UInt<5>(0h1a), remapindex_13)
when _T_4779 :
connect remapVecData[13], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[13]
node _T_4780 = eq(UInt<5>(0h1b), remapindex_13)
when _T_4780 :
connect remapVecData[13], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[13]
node _T_4781 = eq(UInt<5>(0h1c), remapindex_13)
when _T_4781 :
connect remapVecData[13], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[13]
node _T_4782 = eq(UInt<5>(0h1d), remapindex_13)
when _T_4782 :
connect remapVecData[13], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[13]
node _T_4783 = eq(UInt<5>(0h1e), remapindex_13)
when _T_4783 :
connect remapVecData[13], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[13]
node _T_4784 = eq(UInt<5>(0h1f), remapindex_13)
when _T_4784 :
connect remapVecData[13], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[13], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[13]
node _remapindex_T_14 = add(UInt<4>(0he), read_start_index)
node remapindex_14 = rem(_remapindex_T_14, UInt<6>(0h20))
node _T_4785 = eq(UInt<1>(0h0), remapindex_14)
when _T_4785 :
connect remapVecData[14], Queue2_UInt8.io.deq.bits
connect remapVecValids[14], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[14]
node _T_4786 = eq(UInt<1>(0h1), remapindex_14)
when _T_4786 :
connect remapVecData[14], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[14]
node _T_4787 = eq(UInt<2>(0h2), remapindex_14)
when _T_4787 :
connect remapVecData[14], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[14]
node _T_4788 = eq(UInt<2>(0h3), remapindex_14)
when _T_4788 :
connect remapVecData[14], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[14]
node _T_4789 = eq(UInt<3>(0h4), remapindex_14)
when _T_4789 :
connect remapVecData[14], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[14]
node _T_4790 = eq(UInt<3>(0h5), remapindex_14)
when _T_4790 :
connect remapVecData[14], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[14]
node _T_4791 = eq(UInt<3>(0h6), remapindex_14)
when _T_4791 :
connect remapVecData[14], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[14]
node _T_4792 = eq(UInt<3>(0h7), remapindex_14)
when _T_4792 :
connect remapVecData[14], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[14]
node _T_4793 = eq(UInt<4>(0h8), remapindex_14)
when _T_4793 :
connect remapVecData[14], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[14]
node _T_4794 = eq(UInt<4>(0h9), remapindex_14)
when _T_4794 :
connect remapVecData[14], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[14]
node _T_4795 = eq(UInt<4>(0ha), remapindex_14)
when _T_4795 :
connect remapVecData[14], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[14]
node _T_4796 = eq(UInt<4>(0hb), remapindex_14)
when _T_4796 :
connect remapVecData[14], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[14]
node _T_4797 = eq(UInt<4>(0hc), remapindex_14)
when _T_4797 :
connect remapVecData[14], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[14]
node _T_4798 = eq(UInt<4>(0hd), remapindex_14)
when _T_4798 :
connect remapVecData[14], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[14]
node _T_4799 = eq(UInt<4>(0he), remapindex_14)
when _T_4799 :
connect remapVecData[14], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[14]
node _T_4800 = eq(UInt<4>(0hf), remapindex_14)
when _T_4800 :
connect remapVecData[14], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[14]
node _T_4801 = eq(UInt<5>(0h10), remapindex_14)
when _T_4801 :
connect remapVecData[14], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[14]
node _T_4802 = eq(UInt<5>(0h11), remapindex_14)
when _T_4802 :
connect remapVecData[14], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[14]
node _T_4803 = eq(UInt<5>(0h12), remapindex_14)
when _T_4803 :
connect remapVecData[14], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[14]
node _T_4804 = eq(UInt<5>(0h13), remapindex_14)
when _T_4804 :
connect remapVecData[14], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[14]
node _T_4805 = eq(UInt<5>(0h14), remapindex_14)
when _T_4805 :
connect remapVecData[14], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[14]
node _T_4806 = eq(UInt<5>(0h15), remapindex_14)
when _T_4806 :
connect remapVecData[14], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[14]
node _T_4807 = eq(UInt<5>(0h16), remapindex_14)
when _T_4807 :
connect remapVecData[14], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[14]
node _T_4808 = eq(UInt<5>(0h17), remapindex_14)
when _T_4808 :
connect remapVecData[14], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[14]
node _T_4809 = eq(UInt<5>(0h18), remapindex_14)
when _T_4809 :
connect remapVecData[14], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[14]
node _T_4810 = eq(UInt<5>(0h19), remapindex_14)
when _T_4810 :
connect remapVecData[14], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[14]
node _T_4811 = eq(UInt<5>(0h1a), remapindex_14)
when _T_4811 :
connect remapVecData[14], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[14]
node _T_4812 = eq(UInt<5>(0h1b), remapindex_14)
when _T_4812 :
connect remapVecData[14], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[14]
node _T_4813 = eq(UInt<5>(0h1c), remapindex_14)
when _T_4813 :
connect remapVecData[14], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[14]
node _T_4814 = eq(UInt<5>(0h1d), remapindex_14)
when _T_4814 :
connect remapVecData[14], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[14]
node _T_4815 = eq(UInt<5>(0h1e), remapindex_14)
when _T_4815 :
connect remapVecData[14], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[14]
node _T_4816 = eq(UInt<5>(0h1f), remapindex_14)
when _T_4816 :
connect remapVecData[14], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[14], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[14]
node _remapindex_T_15 = add(UInt<4>(0hf), read_start_index)
node remapindex_15 = rem(_remapindex_T_15, UInt<6>(0h20))
node _T_4817 = eq(UInt<1>(0h0), remapindex_15)
when _T_4817 :
connect remapVecData[15], Queue2_UInt8.io.deq.bits
connect remapVecValids[15], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[15]
node _T_4818 = eq(UInt<1>(0h1), remapindex_15)
when _T_4818 :
connect remapVecData[15], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[15]
node _T_4819 = eq(UInt<2>(0h2), remapindex_15)
when _T_4819 :
connect remapVecData[15], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[15]
node _T_4820 = eq(UInt<2>(0h3), remapindex_15)
when _T_4820 :
connect remapVecData[15], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[15]
node _T_4821 = eq(UInt<3>(0h4), remapindex_15)
when _T_4821 :
connect remapVecData[15], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[15]
node _T_4822 = eq(UInt<3>(0h5), remapindex_15)
when _T_4822 :
connect remapVecData[15], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[15]
node _T_4823 = eq(UInt<3>(0h6), remapindex_15)
when _T_4823 :
connect remapVecData[15], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[15]
node _T_4824 = eq(UInt<3>(0h7), remapindex_15)
when _T_4824 :
connect remapVecData[15], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[15]
node _T_4825 = eq(UInt<4>(0h8), remapindex_15)
when _T_4825 :
connect remapVecData[15], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[15]
node _T_4826 = eq(UInt<4>(0h9), remapindex_15)
when _T_4826 :
connect remapVecData[15], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[15]
node _T_4827 = eq(UInt<4>(0ha), remapindex_15)
when _T_4827 :
connect remapVecData[15], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[15]
node _T_4828 = eq(UInt<4>(0hb), remapindex_15)
when _T_4828 :
connect remapVecData[15], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[15]
node _T_4829 = eq(UInt<4>(0hc), remapindex_15)
when _T_4829 :
connect remapVecData[15], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[15]
node _T_4830 = eq(UInt<4>(0hd), remapindex_15)
when _T_4830 :
connect remapVecData[15], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[15]
node _T_4831 = eq(UInt<4>(0he), remapindex_15)
when _T_4831 :
connect remapVecData[15], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[15]
node _T_4832 = eq(UInt<4>(0hf), remapindex_15)
when _T_4832 :
connect remapVecData[15], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[15]
node _T_4833 = eq(UInt<5>(0h10), remapindex_15)
when _T_4833 :
connect remapVecData[15], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[15]
node _T_4834 = eq(UInt<5>(0h11), remapindex_15)
when _T_4834 :
connect remapVecData[15], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[15]
node _T_4835 = eq(UInt<5>(0h12), remapindex_15)
when _T_4835 :
connect remapVecData[15], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[15]
node _T_4836 = eq(UInt<5>(0h13), remapindex_15)
when _T_4836 :
connect remapVecData[15], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[15]
node _T_4837 = eq(UInt<5>(0h14), remapindex_15)
when _T_4837 :
connect remapVecData[15], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[15]
node _T_4838 = eq(UInt<5>(0h15), remapindex_15)
when _T_4838 :
connect remapVecData[15], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[15]
node _T_4839 = eq(UInt<5>(0h16), remapindex_15)
when _T_4839 :
connect remapVecData[15], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[15]
node _T_4840 = eq(UInt<5>(0h17), remapindex_15)
when _T_4840 :
connect remapVecData[15], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[15]
node _T_4841 = eq(UInt<5>(0h18), remapindex_15)
when _T_4841 :
connect remapVecData[15], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[15]
node _T_4842 = eq(UInt<5>(0h19), remapindex_15)
when _T_4842 :
connect remapVecData[15], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[15]
node _T_4843 = eq(UInt<5>(0h1a), remapindex_15)
when _T_4843 :
connect remapVecData[15], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[15]
node _T_4844 = eq(UInt<5>(0h1b), remapindex_15)
when _T_4844 :
connect remapVecData[15], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[15]
node _T_4845 = eq(UInt<5>(0h1c), remapindex_15)
when _T_4845 :
connect remapVecData[15], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[15]
node _T_4846 = eq(UInt<5>(0h1d), remapindex_15)
when _T_4846 :
connect remapVecData[15], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[15]
node _T_4847 = eq(UInt<5>(0h1e), remapindex_15)
when _T_4847 :
connect remapVecData[15], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[15]
node _T_4848 = eq(UInt<5>(0h1f), remapindex_15)
when _T_4848 :
connect remapVecData[15], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[15], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[15]
node _remapindex_T_16 = add(UInt<5>(0h10), read_start_index)
node remapindex_16 = rem(_remapindex_T_16, UInt<6>(0h20))
node _T_4849 = eq(UInt<1>(0h0), remapindex_16)
when _T_4849 :
connect remapVecData[16], Queue2_UInt8.io.deq.bits
connect remapVecValids[16], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[16]
node _T_4850 = eq(UInt<1>(0h1), remapindex_16)
when _T_4850 :
connect remapVecData[16], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[16]
node _T_4851 = eq(UInt<2>(0h2), remapindex_16)
when _T_4851 :
connect remapVecData[16], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[16]
node _T_4852 = eq(UInt<2>(0h3), remapindex_16)
when _T_4852 :
connect remapVecData[16], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[16]
node _T_4853 = eq(UInt<3>(0h4), remapindex_16)
when _T_4853 :
connect remapVecData[16], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[16]
node _T_4854 = eq(UInt<3>(0h5), remapindex_16)
when _T_4854 :
connect remapVecData[16], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[16]
node _T_4855 = eq(UInt<3>(0h6), remapindex_16)
when _T_4855 :
connect remapVecData[16], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[16]
node _T_4856 = eq(UInt<3>(0h7), remapindex_16)
when _T_4856 :
connect remapVecData[16], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[16]
node _T_4857 = eq(UInt<4>(0h8), remapindex_16)
when _T_4857 :
connect remapVecData[16], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[16]
node _T_4858 = eq(UInt<4>(0h9), remapindex_16)
when _T_4858 :
connect remapVecData[16], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[16]
node _T_4859 = eq(UInt<4>(0ha), remapindex_16)
when _T_4859 :
connect remapVecData[16], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[16]
node _T_4860 = eq(UInt<4>(0hb), remapindex_16)
when _T_4860 :
connect remapVecData[16], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[16]
node _T_4861 = eq(UInt<4>(0hc), remapindex_16)
when _T_4861 :
connect remapVecData[16], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[16]
node _T_4862 = eq(UInt<4>(0hd), remapindex_16)
when _T_4862 :
connect remapVecData[16], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[16]
node _T_4863 = eq(UInt<4>(0he), remapindex_16)
when _T_4863 :
connect remapVecData[16], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[16]
node _T_4864 = eq(UInt<4>(0hf), remapindex_16)
when _T_4864 :
connect remapVecData[16], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[16]
node _T_4865 = eq(UInt<5>(0h10), remapindex_16)
when _T_4865 :
connect remapVecData[16], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[16]
node _T_4866 = eq(UInt<5>(0h11), remapindex_16)
when _T_4866 :
connect remapVecData[16], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[16]
node _T_4867 = eq(UInt<5>(0h12), remapindex_16)
when _T_4867 :
connect remapVecData[16], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[16]
node _T_4868 = eq(UInt<5>(0h13), remapindex_16)
when _T_4868 :
connect remapVecData[16], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[16]
node _T_4869 = eq(UInt<5>(0h14), remapindex_16)
when _T_4869 :
connect remapVecData[16], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[16]
node _T_4870 = eq(UInt<5>(0h15), remapindex_16)
when _T_4870 :
connect remapVecData[16], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[16]
node _T_4871 = eq(UInt<5>(0h16), remapindex_16)
when _T_4871 :
connect remapVecData[16], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[16]
node _T_4872 = eq(UInt<5>(0h17), remapindex_16)
when _T_4872 :
connect remapVecData[16], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[16]
node _T_4873 = eq(UInt<5>(0h18), remapindex_16)
when _T_4873 :
connect remapVecData[16], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[16]
node _T_4874 = eq(UInt<5>(0h19), remapindex_16)
when _T_4874 :
connect remapVecData[16], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[16]
node _T_4875 = eq(UInt<5>(0h1a), remapindex_16)
when _T_4875 :
connect remapVecData[16], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[16]
node _T_4876 = eq(UInt<5>(0h1b), remapindex_16)
when _T_4876 :
connect remapVecData[16], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[16]
node _T_4877 = eq(UInt<5>(0h1c), remapindex_16)
when _T_4877 :
connect remapVecData[16], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[16]
node _T_4878 = eq(UInt<5>(0h1d), remapindex_16)
when _T_4878 :
connect remapVecData[16], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[16]
node _T_4879 = eq(UInt<5>(0h1e), remapindex_16)
when _T_4879 :
connect remapVecData[16], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[16]
node _T_4880 = eq(UInt<5>(0h1f), remapindex_16)
when _T_4880 :
connect remapVecData[16], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[16], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[16]
node _remapindex_T_17 = add(UInt<5>(0h11), read_start_index)
node remapindex_17 = rem(_remapindex_T_17, UInt<6>(0h20))
node _T_4881 = eq(UInt<1>(0h0), remapindex_17)
when _T_4881 :
connect remapVecData[17], Queue2_UInt8.io.deq.bits
connect remapVecValids[17], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[17]
node _T_4882 = eq(UInt<1>(0h1), remapindex_17)
when _T_4882 :
connect remapVecData[17], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[17]
node _T_4883 = eq(UInt<2>(0h2), remapindex_17)
when _T_4883 :
connect remapVecData[17], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[17]
node _T_4884 = eq(UInt<2>(0h3), remapindex_17)
when _T_4884 :
connect remapVecData[17], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[17]
node _T_4885 = eq(UInt<3>(0h4), remapindex_17)
when _T_4885 :
connect remapVecData[17], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[17]
node _T_4886 = eq(UInt<3>(0h5), remapindex_17)
when _T_4886 :
connect remapVecData[17], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[17]
node _T_4887 = eq(UInt<3>(0h6), remapindex_17)
when _T_4887 :
connect remapVecData[17], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[17]
node _T_4888 = eq(UInt<3>(0h7), remapindex_17)
when _T_4888 :
connect remapVecData[17], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[17]
node _T_4889 = eq(UInt<4>(0h8), remapindex_17)
when _T_4889 :
connect remapVecData[17], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[17]
node _T_4890 = eq(UInt<4>(0h9), remapindex_17)
when _T_4890 :
connect remapVecData[17], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[17]
node _T_4891 = eq(UInt<4>(0ha), remapindex_17)
when _T_4891 :
connect remapVecData[17], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[17]
node _T_4892 = eq(UInt<4>(0hb), remapindex_17)
when _T_4892 :
connect remapVecData[17], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[17]
node _T_4893 = eq(UInt<4>(0hc), remapindex_17)
when _T_4893 :
connect remapVecData[17], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[17]
node _T_4894 = eq(UInt<4>(0hd), remapindex_17)
when _T_4894 :
connect remapVecData[17], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[17]
node _T_4895 = eq(UInt<4>(0he), remapindex_17)
when _T_4895 :
connect remapVecData[17], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[17]
node _T_4896 = eq(UInt<4>(0hf), remapindex_17)
when _T_4896 :
connect remapVecData[17], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[17]
node _T_4897 = eq(UInt<5>(0h10), remapindex_17)
when _T_4897 :
connect remapVecData[17], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[17]
node _T_4898 = eq(UInt<5>(0h11), remapindex_17)
when _T_4898 :
connect remapVecData[17], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[17]
node _T_4899 = eq(UInt<5>(0h12), remapindex_17)
when _T_4899 :
connect remapVecData[17], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[17]
node _T_4900 = eq(UInt<5>(0h13), remapindex_17)
when _T_4900 :
connect remapVecData[17], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[17]
node _T_4901 = eq(UInt<5>(0h14), remapindex_17)
when _T_4901 :
connect remapVecData[17], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[17]
node _T_4902 = eq(UInt<5>(0h15), remapindex_17)
when _T_4902 :
connect remapVecData[17], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[17]
node _T_4903 = eq(UInt<5>(0h16), remapindex_17)
when _T_4903 :
connect remapVecData[17], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[17]
node _T_4904 = eq(UInt<5>(0h17), remapindex_17)
when _T_4904 :
connect remapVecData[17], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[17]
node _T_4905 = eq(UInt<5>(0h18), remapindex_17)
when _T_4905 :
connect remapVecData[17], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[17]
node _T_4906 = eq(UInt<5>(0h19), remapindex_17)
when _T_4906 :
connect remapVecData[17], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[17]
node _T_4907 = eq(UInt<5>(0h1a), remapindex_17)
when _T_4907 :
connect remapVecData[17], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[17]
node _T_4908 = eq(UInt<5>(0h1b), remapindex_17)
when _T_4908 :
connect remapVecData[17], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[17]
node _T_4909 = eq(UInt<5>(0h1c), remapindex_17)
when _T_4909 :
connect remapVecData[17], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[17]
node _T_4910 = eq(UInt<5>(0h1d), remapindex_17)
when _T_4910 :
connect remapVecData[17], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[17]
node _T_4911 = eq(UInt<5>(0h1e), remapindex_17)
when _T_4911 :
connect remapVecData[17], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[17]
node _T_4912 = eq(UInt<5>(0h1f), remapindex_17)
when _T_4912 :
connect remapVecData[17], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[17], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[17]
node _remapindex_T_18 = add(UInt<5>(0h12), read_start_index)
node remapindex_18 = rem(_remapindex_T_18, UInt<6>(0h20))
node _T_4913 = eq(UInt<1>(0h0), remapindex_18)
when _T_4913 :
connect remapVecData[18], Queue2_UInt8.io.deq.bits
connect remapVecValids[18], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[18]
node _T_4914 = eq(UInt<1>(0h1), remapindex_18)
when _T_4914 :
connect remapVecData[18], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[18]
node _T_4915 = eq(UInt<2>(0h2), remapindex_18)
when _T_4915 :
connect remapVecData[18], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[18]
node _T_4916 = eq(UInt<2>(0h3), remapindex_18)
when _T_4916 :
connect remapVecData[18], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[18]
node _T_4917 = eq(UInt<3>(0h4), remapindex_18)
when _T_4917 :
connect remapVecData[18], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[18]
node _T_4918 = eq(UInt<3>(0h5), remapindex_18)
when _T_4918 :
connect remapVecData[18], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[18]
node _T_4919 = eq(UInt<3>(0h6), remapindex_18)
when _T_4919 :
connect remapVecData[18], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[18]
node _T_4920 = eq(UInt<3>(0h7), remapindex_18)
when _T_4920 :
connect remapVecData[18], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[18]
node _T_4921 = eq(UInt<4>(0h8), remapindex_18)
when _T_4921 :
connect remapVecData[18], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[18]
node _T_4922 = eq(UInt<4>(0h9), remapindex_18)
when _T_4922 :
connect remapVecData[18], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[18]
node _T_4923 = eq(UInt<4>(0ha), remapindex_18)
when _T_4923 :
connect remapVecData[18], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[18]
node _T_4924 = eq(UInt<4>(0hb), remapindex_18)
when _T_4924 :
connect remapVecData[18], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[18]
node _T_4925 = eq(UInt<4>(0hc), remapindex_18)
when _T_4925 :
connect remapVecData[18], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[18]
node _T_4926 = eq(UInt<4>(0hd), remapindex_18)
when _T_4926 :
connect remapVecData[18], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[18]
node _T_4927 = eq(UInt<4>(0he), remapindex_18)
when _T_4927 :
connect remapVecData[18], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[18]
node _T_4928 = eq(UInt<4>(0hf), remapindex_18)
when _T_4928 :
connect remapVecData[18], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[18]
node _T_4929 = eq(UInt<5>(0h10), remapindex_18)
when _T_4929 :
connect remapVecData[18], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[18]
node _T_4930 = eq(UInt<5>(0h11), remapindex_18)
when _T_4930 :
connect remapVecData[18], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[18]
node _T_4931 = eq(UInt<5>(0h12), remapindex_18)
when _T_4931 :
connect remapVecData[18], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[18]
node _T_4932 = eq(UInt<5>(0h13), remapindex_18)
when _T_4932 :
connect remapVecData[18], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[18]
node _T_4933 = eq(UInt<5>(0h14), remapindex_18)
when _T_4933 :
connect remapVecData[18], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[18]
node _T_4934 = eq(UInt<5>(0h15), remapindex_18)
when _T_4934 :
connect remapVecData[18], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[18]
node _T_4935 = eq(UInt<5>(0h16), remapindex_18)
when _T_4935 :
connect remapVecData[18], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[18]
node _T_4936 = eq(UInt<5>(0h17), remapindex_18)
when _T_4936 :
connect remapVecData[18], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[18]
node _T_4937 = eq(UInt<5>(0h18), remapindex_18)
when _T_4937 :
connect remapVecData[18], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[18]
node _T_4938 = eq(UInt<5>(0h19), remapindex_18)
when _T_4938 :
connect remapVecData[18], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[18]
node _T_4939 = eq(UInt<5>(0h1a), remapindex_18)
when _T_4939 :
connect remapVecData[18], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[18]
node _T_4940 = eq(UInt<5>(0h1b), remapindex_18)
when _T_4940 :
connect remapVecData[18], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[18]
node _T_4941 = eq(UInt<5>(0h1c), remapindex_18)
when _T_4941 :
connect remapVecData[18], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[18]
node _T_4942 = eq(UInt<5>(0h1d), remapindex_18)
when _T_4942 :
connect remapVecData[18], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[18]
node _T_4943 = eq(UInt<5>(0h1e), remapindex_18)
when _T_4943 :
connect remapVecData[18], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[18]
node _T_4944 = eq(UInt<5>(0h1f), remapindex_18)
when _T_4944 :
connect remapVecData[18], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[18], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[18]
node _remapindex_T_19 = add(UInt<5>(0h13), read_start_index)
node remapindex_19 = rem(_remapindex_T_19, UInt<6>(0h20))
node _T_4945 = eq(UInt<1>(0h0), remapindex_19)
when _T_4945 :
connect remapVecData[19], Queue2_UInt8.io.deq.bits
connect remapVecValids[19], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[19]
node _T_4946 = eq(UInt<1>(0h1), remapindex_19)
when _T_4946 :
connect remapVecData[19], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[19]
node _T_4947 = eq(UInt<2>(0h2), remapindex_19)
when _T_4947 :
connect remapVecData[19], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[19]
node _T_4948 = eq(UInt<2>(0h3), remapindex_19)
when _T_4948 :
connect remapVecData[19], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[19]
node _T_4949 = eq(UInt<3>(0h4), remapindex_19)
when _T_4949 :
connect remapVecData[19], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[19]
node _T_4950 = eq(UInt<3>(0h5), remapindex_19)
when _T_4950 :
connect remapVecData[19], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[19]
node _T_4951 = eq(UInt<3>(0h6), remapindex_19)
when _T_4951 :
connect remapVecData[19], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[19]
node _T_4952 = eq(UInt<3>(0h7), remapindex_19)
when _T_4952 :
connect remapVecData[19], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[19]
node _T_4953 = eq(UInt<4>(0h8), remapindex_19)
when _T_4953 :
connect remapVecData[19], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[19]
node _T_4954 = eq(UInt<4>(0h9), remapindex_19)
when _T_4954 :
connect remapVecData[19], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[19]
node _T_4955 = eq(UInt<4>(0ha), remapindex_19)
when _T_4955 :
connect remapVecData[19], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[19]
node _T_4956 = eq(UInt<4>(0hb), remapindex_19)
when _T_4956 :
connect remapVecData[19], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[19]
node _T_4957 = eq(UInt<4>(0hc), remapindex_19)
when _T_4957 :
connect remapVecData[19], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[19]
node _T_4958 = eq(UInt<4>(0hd), remapindex_19)
when _T_4958 :
connect remapVecData[19], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[19]
node _T_4959 = eq(UInt<4>(0he), remapindex_19)
when _T_4959 :
connect remapVecData[19], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[19]
node _T_4960 = eq(UInt<4>(0hf), remapindex_19)
when _T_4960 :
connect remapVecData[19], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[19]
node _T_4961 = eq(UInt<5>(0h10), remapindex_19)
when _T_4961 :
connect remapVecData[19], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[19]
node _T_4962 = eq(UInt<5>(0h11), remapindex_19)
when _T_4962 :
connect remapVecData[19], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[19]
node _T_4963 = eq(UInt<5>(0h12), remapindex_19)
when _T_4963 :
connect remapVecData[19], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[19]
node _T_4964 = eq(UInt<5>(0h13), remapindex_19)
when _T_4964 :
connect remapVecData[19], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[19]
node _T_4965 = eq(UInt<5>(0h14), remapindex_19)
when _T_4965 :
connect remapVecData[19], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[19]
node _T_4966 = eq(UInt<5>(0h15), remapindex_19)
when _T_4966 :
connect remapVecData[19], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[19]
node _T_4967 = eq(UInt<5>(0h16), remapindex_19)
when _T_4967 :
connect remapVecData[19], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[19]
node _T_4968 = eq(UInt<5>(0h17), remapindex_19)
when _T_4968 :
connect remapVecData[19], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[19]
node _T_4969 = eq(UInt<5>(0h18), remapindex_19)
when _T_4969 :
connect remapVecData[19], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[19]
node _T_4970 = eq(UInt<5>(0h19), remapindex_19)
when _T_4970 :
connect remapVecData[19], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[19]
node _T_4971 = eq(UInt<5>(0h1a), remapindex_19)
when _T_4971 :
connect remapVecData[19], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[19]
node _T_4972 = eq(UInt<5>(0h1b), remapindex_19)
when _T_4972 :
connect remapVecData[19], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[19]
node _T_4973 = eq(UInt<5>(0h1c), remapindex_19)
when _T_4973 :
connect remapVecData[19], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[19]
node _T_4974 = eq(UInt<5>(0h1d), remapindex_19)
when _T_4974 :
connect remapVecData[19], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[19]
node _T_4975 = eq(UInt<5>(0h1e), remapindex_19)
when _T_4975 :
connect remapVecData[19], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[19]
node _T_4976 = eq(UInt<5>(0h1f), remapindex_19)
when _T_4976 :
connect remapVecData[19], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[19], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[19]
node _remapindex_T_20 = add(UInt<5>(0h14), read_start_index)
node remapindex_20 = rem(_remapindex_T_20, UInt<6>(0h20))
node _T_4977 = eq(UInt<1>(0h0), remapindex_20)
when _T_4977 :
connect remapVecData[20], Queue2_UInt8.io.deq.bits
connect remapVecValids[20], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[20]
node _T_4978 = eq(UInt<1>(0h1), remapindex_20)
when _T_4978 :
connect remapVecData[20], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[20]
node _T_4979 = eq(UInt<2>(0h2), remapindex_20)
when _T_4979 :
connect remapVecData[20], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[20]
node _T_4980 = eq(UInt<2>(0h3), remapindex_20)
when _T_4980 :
connect remapVecData[20], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[20]
node _T_4981 = eq(UInt<3>(0h4), remapindex_20)
when _T_4981 :
connect remapVecData[20], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[20]
node _T_4982 = eq(UInt<3>(0h5), remapindex_20)
when _T_4982 :
connect remapVecData[20], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[20]
node _T_4983 = eq(UInt<3>(0h6), remapindex_20)
when _T_4983 :
connect remapVecData[20], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[20]
node _T_4984 = eq(UInt<3>(0h7), remapindex_20)
when _T_4984 :
connect remapVecData[20], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[20]
node _T_4985 = eq(UInt<4>(0h8), remapindex_20)
when _T_4985 :
connect remapVecData[20], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[20]
node _T_4986 = eq(UInt<4>(0h9), remapindex_20)
when _T_4986 :
connect remapVecData[20], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[20]
node _T_4987 = eq(UInt<4>(0ha), remapindex_20)
when _T_4987 :
connect remapVecData[20], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[20]
node _T_4988 = eq(UInt<4>(0hb), remapindex_20)
when _T_4988 :
connect remapVecData[20], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[20]
node _T_4989 = eq(UInt<4>(0hc), remapindex_20)
when _T_4989 :
connect remapVecData[20], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[20]
node _T_4990 = eq(UInt<4>(0hd), remapindex_20)
when _T_4990 :
connect remapVecData[20], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[20]
node _T_4991 = eq(UInt<4>(0he), remapindex_20)
when _T_4991 :
connect remapVecData[20], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[20]
node _T_4992 = eq(UInt<4>(0hf), remapindex_20)
when _T_4992 :
connect remapVecData[20], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[20]
node _T_4993 = eq(UInt<5>(0h10), remapindex_20)
when _T_4993 :
connect remapVecData[20], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[20]
node _T_4994 = eq(UInt<5>(0h11), remapindex_20)
when _T_4994 :
connect remapVecData[20], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[20]
node _T_4995 = eq(UInt<5>(0h12), remapindex_20)
when _T_4995 :
connect remapVecData[20], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[20]
node _T_4996 = eq(UInt<5>(0h13), remapindex_20)
when _T_4996 :
connect remapVecData[20], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[20]
node _T_4997 = eq(UInt<5>(0h14), remapindex_20)
when _T_4997 :
connect remapVecData[20], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[20]
node _T_4998 = eq(UInt<5>(0h15), remapindex_20)
when _T_4998 :
connect remapVecData[20], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[20]
node _T_4999 = eq(UInt<5>(0h16), remapindex_20)
when _T_4999 :
connect remapVecData[20], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[20]
node _T_5000 = eq(UInt<5>(0h17), remapindex_20)
when _T_5000 :
connect remapVecData[20], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[20]
node _T_5001 = eq(UInt<5>(0h18), remapindex_20)
when _T_5001 :
connect remapVecData[20], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[20]
node _T_5002 = eq(UInt<5>(0h19), remapindex_20)
when _T_5002 :
connect remapVecData[20], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[20]
node _T_5003 = eq(UInt<5>(0h1a), remapindex_20)
when _T_5003 :
connect remapVecData[20], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[20]
node _T_5004 = eq(UInt<5>(0h1b), remapindex_20)
when _T_5004 :
connect remapVecData[20], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[20]
node _T_5005 = eq(UInt<5>(0h1c), remapindex_20)
when _T_5005 :
connect remapVecData[20], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[20]
node _T_5006 = eq(UInt<5>(0h1d), remapindex_20)
when _T_5006 :
connect remapVecData[20], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[20]
node _T_5007 = eq(UInt<5>(0h1e), remapindex_20)
when _T_5007 :
connect remapVecData[20], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[20]
node _T_5008 = eq(UInt<5>(0h1f), remapindex_20)
when _T_5008 :
connect remapVecData[20], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[20], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[20]
node _remapindex_T_21 = add(UInt<5>(0h15), read_start_index)
node remapindex_21 = rem(_remapindex_T_21, UInt<6>(0h20))
node _T_5009 = eq(UInt<1>(0h0), remapindex_21)
when _T_5009 :
connect remapVecData[21], Queue2_UInt8.io.deq.bits
connect remapVecValids[21], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[21]
node _T_5010 = eq(UInt<1>(0h1), remapindex_21)
when _T_5010 :
connect remapVecData[21], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[21]
node _T_5011 = eq(UInt<2>(0h2), remapindex_21)
when _T_5011 :
connect remapVecData[21], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[21]
node _T_5012 = eq(UInt<2>(0h3), remapindex_21)
when _T_5012 :
connect remapVecData[21], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[21]
node _T_5013 = eq(UInt<3>(0h4), remapindex_21)
when _T_5013 :
connect remapVecData[21], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[21]
node _T_5014 = eq(UInt<3>(0h5), remapindex_21)
when _T_5014 :
connect remapVecData[21], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[21]
node _T_5015 = eq(UInt<3>(0h6), remapindex_21)
when _T_5015 :
connect remapVecData[21], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[21]
node _T_5016 = eq(UInt<3>(0h7), remapindex_21)
when _T_5016 :
connect remapVecData[21], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[21]
node _T_5017 = eq(UInt<4>(0h8), remapindex_21)
when _T_5017 :
connect remapVecData[21], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[21]
node _T_5018 = eq(UInt<4>(0h9), remapindex_21)
when _T_5018 :
connect remapVecData[21], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[21]
node _T_5019 = eq(UInt<4>(0ha), remapindex_21)
when _T_5019 :
connect remapVecData[21], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[21]
node _T_5020 = eq(UInt<4>(0hb), remapindex_21)
when _T_5020 :
connect remapVecData[21], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[21]
node _T_5021 = eq(UInt<4>(0hc), remapindex_21)
when _T_5021 :
connect remapVecData[21], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[21]
node _T_5022 = eq(UInt<4>(0hd), remapindex_21)
when _T_5022 :
connect remapVecData[21], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[21]
node _T_5023 = eq(UInt<4>(0he), remapindex_21)
when _T_5023 :
connect remapVecData[21], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[21]
node _T_5024 = eq(UInt<4>(0hf), remapindex_21)
when _T_5024 :
connect remapVecData[21], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[21]
node _T_5025 = eq(UInt<5>(0h10), remapindex_21)
when _T_5025 :
connect remapVecData[21], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[21]
node _T_5026 = eq(UInt<5>(0h11), remapindex_21)
when _T_5026 :
connect remapVecData[21], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[21]
node _T_5027 = eq(UInt<5>(0h12), remapindex_21)
when _T_5027 :
connect remapVecData[21], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[21]
node _T_5028 = eq(UInt<5>(0h13), remapindex_21)
when _T_5028 :
connect remapVecData[21], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[21]
node _T_5029 = eq(UInt<5>(0h14), remapindex_21)
when _T_5029 :
connect remapVecData[21], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[21]
node _T_5030 = eq(UInt<5>(0h15), remapindex_21)
when _T_5030 :
connect remapVecData[21], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[21]
node _T_5031 = eq(UInt<5>(0h16), remapindex_21)
when _T_5031 :
connect remapVecData[21], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[21]
node _T_5032 = eq(UInt<5>(0h17), remapindex_21)
when _T_5032 :
connect remapVecData[21], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[21]
node _T_5033 = eq(UInt<5>(0h18), remapindex_21)
when _T_5033 :
connect remapVecData[21], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[21]
node _T_5034 = eq(UInt<5>(0h19), remapindex_21)
when _T_5034 :
connect remapVecData[21], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[21]
node _T_5035 = eq(UInt<5>(0h1a), remapindex_21)
when _T_5035 :
connect remapVecData[21], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[21]
node _T_5036 = eq(UInt<5>(0h1b), remapindex_21)
when _T_5036 :
connect remapVecData[21], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[21]
node _T_5037 = eq(UInt<5>(0h1c), remapindex_21)
when _T_5037 :
connect remapVecData[21], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[21]
node _T_5038 = eq(UInt<5>(0h1d), remapindex_21)
when _T_5038 :
connect remapVecData[21], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[21]
node _T_5039 = eq(UInt<5>(0h1e), remapindex_21)
when _T_5039 :
connect remapVecData[21], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[21]
node _T_5040 = eq(UInt<5>(0h1f), remapindex_21)
when _T_5040 :
connect remapVecData[21], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[21], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[21]
node _remapindex_T_22 = add(UInt<5>(0h16), read_start_index)
node remapindex_22 = rem(_remapindex_T_22, UInt<6>(0h20))
node _T_5041 = eq(UInt<1>(0h0), remapindex_22)
when _T_5041 :
connect remapVecData[22], Queue2_UInt8.io.deq.bits
connect remapVecValids[22], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[22]
node _T_5042 = eq(UInt<1>(0h1), remapindex_22)
when _T_5042 :
connect remapVecData[22], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[22]
node _T_5043 = eq(UInt<2>(0h2), remapindex_22)
when _T_5043 :
connect remapVecData[22], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[22]
node _T_5044 = eq(UInt<2>(0h3), remapindex_22)
when _T_5044 :
connect remapVecData[22], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[22]
node _T_5045 = eq(UInt<3>(0h4), remapindex_22)
when _T_5045 :
connect remapVecData[22], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[22]
node _T_5046 = eq(UInt<3>(0h5), remapindex_22)
when _T_5046 :
connect remapVecData[22], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[22]
node _T_5047 = eq(UInt<3>(0h6), remapindex_22)
when _T_5047 :
connect remapVecData[22], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[22]
node _T_5048 = eq(UInt<3>(0h7), remapindex_22)
when _T_5048 :
connect remapVecData[22], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[22]
node _T_5049 = eq(UInt<4>(0h8), remapindex_22)
when _T_5049 :
connect remapVecData[22], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[22]
node _T_5050 = eq(UInt<4>(0h9), remapindex_22)
when _T_5050 :
connect remapVecData[22], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[22]
node _T_5051 = eq(UInt<4>(0ha), remapindex_22)
when _T_5051 :
connect remapVecData[22], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[22]
node _T_5052 = eq(UInt<4>(0hb), remapindex_22)
when _T_5052 :
connect remapVecData[22], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[22]
node _T_5053 = eq(UInt<4>(0hc), remapindex_22)
when _T_5053 :
connect remapVecData[22], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[22]
node _T_5054 = eq(UInt<4>(0hd), remapindex_22)
when _T_5054 :
connect remapVecData[22], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[22]
node _T_5055 = eq(UInt<4>(0he), remapindex_22)
when _T_5055 :
connect remapVecData[22], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[22]
node _T_5056 = eq(UInt<4>(0hf), remapindex_22)
when _T_5056 :
connect remapVecData[22], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[22]
node _T_5057 = eq(UInt<5>(0h10), remapindex_22)
when _T_5057 :
connect remapVecData[22], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[22]
node _T_5058 = eq(UInt<5>(0h11), remapindex_22)
when _T_5058 :
connect remapVecData[22], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[22]
node _T_5059 = eq(UInt<5>(0h12), remapindex_22)
when _T_5059 :
connect remapVecData[22], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[22]
node _T_5060 = eq(UInt<5>(0h13), remapindex_22)
when _T_5060 :
connect remapVecData[22], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[22]
node _T_5061 = eq(UInt<5>(0h14), remapindex_22)
when _T_5061 :
connect remapVecData[22], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[22]
node _T_5062 = eq(UInt<5>(0h15), remapindex_22)
when _T_5062 :
connect remapVecData[22], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[22]
node _T_5063 = eq(UInt<5>(0h16), remapindex_22)
when _T_5063 :
connect remapVecData[22], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[22]
node _T_5064 = eq(UInt<5>(0h17), remapindex_22)
when _T_5064 :
connect remapVecData[22], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[22]
node _T_5065 = eq(UInt<5>(0h18), remapindex_22)
when _T_5065 :
connect remapVecData[22], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[22]
node _T_5066 = eq(UInt<5>(0h19), remapindex_22)
when _T_5066 :
connect remapVecData[22], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[22]
node _T_5067 = eq(UInt<5>(0h1a), remapindex_22)
when _T_5067 :
connect remapVecData[22], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[22]
node _T_5068 = eq(UInt<5>(0h1b), remapindex_22)
when _T_5068 :
connect remapVecData[22], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[22]
node _T_5069 = eq(UInt<5>(0h1c), remapindex_22)
when _T_5069 :
connect remapVecData[22], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[22]
node _T_5070 = eq(UInt<5>(0h1d), remapindex_22)
when _T_5070 :
connect remapVecData[22], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[22]
node _T_5071 = eq(UInt<5>(0h1e), remapindex_22)
when _T_5071 :
connect remapVecData[22], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[22]
node _T_5072 = eq(UInt<5>(0h1f), remapindex_22)
when _T_5072 :
connect remapVecData[22], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[22], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[22]
node _remapindex_T_23 = add(UInt<5>(0h17), read_start_index)
node remapindex_23 = rem(_remapindex_T_23, UInt<6>(0h20))
node _T_5073 = eq(UInt<1>(0h0), remapindex_23)
when _T_5073 :
connect remapVecData[23], Queue2_UInt8.io.deq.bits
connect remapVecValids[23], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[23]
node _T_5074 = eq(UInt<1>(0h1), remapindex_23)
when _T_5074 :
connect remapVecData[23], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[23]
node _T_5075 = eq(UInt<2>(0h2), remapindex_23)
when _T_5075 :
connect remapVecData[23], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[23]
node _T_5076 = eq(UInt<2>(0h3), remapindex_23)
when _T_5076 :
connect remapVecData[23], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[23]
node _T_5077 = eq(UInt<3>(0h4), remapindex_23)
when _T_5077 :
connect remapVecData[23], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[23]
node _T_5078 = eq(UInt<3>(0h5), remapindex_23)
when _T_5078 :
connect remapVecData[23], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[23]
node _T_5079 = eq(UInt<3>(0h6), remapindex_23)
when _T_5079 :
connect remapVecData[23], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[23]
node _T_5080 = eq(UInt<3>(0h7), remapindex_23)
when _T_5080 :
connect remapVecData[23], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[23]
node _T_5081 = eq(UInt<4>(0h8), remapindex_23)
when _T_5081 :
connect remapVecData[23], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[23]
node _T_5082 = eq(UInt<4>(0h9), remapindex_23)
when _T_5082 :
connect remapVecData[23], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[23]
node _T_5083 = eq(UInt<4>(0ha), remapindex_23)
when _T_5083 :
connect remapVecData[23], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[23]
node _T_5084 = eq(UInt<4>(0hb), remapindex_23)
when _T_5084 :
connect remapVecData[23], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[23]
node _T_5085 = eq(UInt<4>(0hc), remapindex_23)
when _T_5085 :
connect remapVecData[23], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[23]
node _T_5086 = eq(UInt<4>(0hd), remapindex_23)
when _T_5086 :
connect remapVecData[23], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[23]
node _T_5087 = eq(UInt<4>(0he), remapindex_23)
when _T_5087 :
connect remapVecData[23], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[23]
node _T_5088 = eq(UInt<4>(0hf), remapindex_23)
when _T_5088 :
connect remapVecData[23], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[23]
node _T_5089 = eq(UInt<5>(0h10), remapindex_23)
when _T_5089 :
connect remapVecData[23], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[23]
node _T_5090 = eq(UInt<5>(0h11), remapindex_23)
when _T_5090 :
connect remapVecData[23], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[23]
node _T_5091 = eq(UInt<5>(0h12), remapindex_23)
when _T_5091 :
connect remapVecData[23], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[23]
node _T_5092 = eq(UInt<5>(0h13), remapindex_23)
when _T_5092 :
connect remapVecData[23], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[23]
node _T_5093 = eq(UInt<5>(0h14), remapindex_23)
when _T_5093 :
connect remapVecData[23], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[23]
node _T_5094 = eq(UInt<5>(0h15), remapindex_23)
when _T_5094 :
connect remapVecData[23], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[23]
node _T_5095 = eq(UInt<5>(0h16), remapindex_23)
when _T_5095 :
connect remapVecData[23], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[23]
node _T_5096 = eq(UInt<5>(0h17), remapindex_23)
when _T_5096 :
connect remapVecData[23], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[23]
node _T_5097 = eq(UInt<5>(0h18), remapindex_23)
when _T_5097 :
connect remapVecData[23], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[23]
node _T_5098 = eq(UInt<5>(0h19), remapindex_23)
when _T_5098 :
connect remapVecData[23], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[23]
node _T_5099 = eq(UInt<5>(0h1a), remapindex_23)
when _T_5099 :
connect remapVecData[23], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[23]
node _T_5100 = eq(UInt<5>(0h1b), remapindex_23)
when _T_5100 :
connect remapVecData[23], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[23]
node _T_5101 = eq(UInt<5>(0h1c), remapindex_23)
when _T_5101 :
connect remapVecData[23], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[23]
node _T_5102 = eq(UInt<5>(0h1d), remapindex_23)
when _T_5102 :
connect remapVecData[23], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[23]
node _T_5103 = eq(UInt<5>(0h1e), remapindex_23)
when _T_5103 :
connect remapVecData[23], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[23]
node _T_5104 = eq(UInt<5>(0h1f), remapindex_23)
when _T_5104 :
connect remapVecData[23], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[23], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[23]
node _remapindex_T_24 = add(UInt<5>(0h18), read_start_index)
node remapindex_24 = rem(_remapindex_T_24, UInt<6>(0h20))
node _T_5105 = eq(UInt<1>(0h0), remapindex_24)
when _T_5105 :
connect remapVecData[24], Queue2_UInt8.io.deq.bits
connect remapVecValids[24], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[24]
node _T_5106 = eq(UInt<1>(0h1), remapindex_24)
when _T_5106 :
connect remapVecData[24], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[24]
node _T_5107 = eq(UInt<2>(0h2), remapindex_24)
when _T_5107 :
connect remapVecData[24], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[24]
node _T_5108 = eq(UInt<2>(0h3), remapindex_24)
when _T_5108 :
connect remapVecData[24], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[24]
node _T_5109 = eq(UInt<3>(0h4), remapindex_24)
when _T_5109 :
connect remapVecData[24], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[24]
node _T_5110 = eq(UInt<3>(0h5), remapindex_24)
when _T_5110 :
connect remapVecData[24], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[24]
node _T_5111 = eq(UInt<3>(0h6), remapindex_24)
when _T_5111 :
connect remapVecData[24], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[24]
node _T_5112 = eq(UInt<3>(0h7), remapindex_24)
when _T_5112 :
connect remapVecData[24], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[24]
node _T_5113 = eq(UInt<4>(0h8), remapindex_24)
when _T_5113 :
connect remapVecData[24], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[24]
node _T_5114 = eq(UInt<4>(0h9), remapindex_24)
when _T_5114 :
connect remapVecData[24], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[24]
node _T_5115 = eq(UInt<4>(0ha), remapindex_24)
when _T_5115 :
connect remapVecData[24], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[24]
node _T_5116 = eq(UInt<4>(0hb), remapindex_24)
when _T_5116 :
connect remapVecData[24], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[24]
node _T_5117 = eq(UInt<4>(0hc), remapindex_24)
when _T_5117 :
connect remapVecData[24], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[24]
node _T_5118 = eq(UInt<4>(0hd), remapindex_24)
when _T_5118 :
connect remapVecData[24], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[24]
node _T_5119 = eq(UInt<4>(0he), remapindex_24)
when _T_5119 :
connect remapVecData[24], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[24]
node _T_5120 = eq(UInt<4>(0hf), remapindex_24)
when _T_5120 :
connect remapVecData[24], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[24]
node _T_5121 = eq(UInt<5>(0h10), remapindex_24)
when _T_5121 :
connect remapVecData[24], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[24]
node _T_5122 = eq(UInt<5>(0h11), remapindex_24)
when _T_5122 :
connect remapVecData[24], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[24]
node _T_5123 = eq(UInt<5>(0h12), remapindex_24)
when _T_5123 :
connect remapVecData[24], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[24]
node _T_5124 = eq(UInt<5>(0h13), remapindex_24)
when _T_5124 :
connect remapVecData[24], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[24]
node _T_5125 = eq(UInt<5>(0h14), remapindex_24)
when _T_5125 :
connect remapVecData[24], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[24]
node _T_5126 = eq(UInt<5>(0h15), remapindex_24)
when _T_5126 :
connect remapVecData[24], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[24]
node _T_5127 = eq(UInt<5>(0h16), remapindex_24)
when _T_5127 :
connect remapVecData[24], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[24]
node _T_5128 = eq(UInt<5>(0h17), remapindex_24)
when _T_5128 :
connect remapVecData[24], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[24]
node _T_5129 = eq(UInt<5>(0h18), remapindex_24)
when _T_5129 :
connect remapVecData[24], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[24]
node _T_5130 = eq(UInt<5>(0h19), remapindex_24)
when _T_5130 :
connect remapVecData[24], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[24]
node _T_5131 = eq(UInt<5>(0h1a), remapindex_24)
when _T_5131 :
connect remapVecData[24], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[24]
node _T_5132 = eq(UInt<5>(0h1b), remapindex_24)
when _T_5132 :
connect remapVecData[24], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[24]
node _T_5133 = eq(UInt<5>(0h1c), remapindex_24)
when _T_5133 :
connect remapVecData[24], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[24]
node _T_5134 = eq(UInt<5>(0h1d), remapindex_24)
when _T_5134 :
connect remapVecData[24], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[24]
node _T_5135 = eq(UInt<5>(0h1e), remapindex_24)
when _T_5135 :
connect remapVecData[24], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[24]
node _T_5136 = eq(UInt<5>(0h1f), remapindex_24)
when _T_5136 :
connect remapVecData[24], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[24], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[24]
node _remapindex_T_25 = add(UInt<5>(0h19), read_start_index)
node remapindex_25 = rem(_remapindex_T_25, UInt<6>(0h20))
node _T_5137 = eq(UInt<1>(0h0), remapindex_25)
when _T_5137 :
connect remapVecData[25], Queue2_UInt8.io.deq.bits
connect remapVecValids[25], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[25]
node _T_5138 = eq(UInt<1>(0h1), remapindex_25)
when _T_5138 :
connect remapVecData[25], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[25]
node _T_5139 = eq(UInt<2>(0h2), remapindex_25)
when _T_5139 :
connect remapVecData[25], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[25]
node _T_5140 = eq(UInt<2>(0h3), remapindex_25)
when _T_5140 :
connect remapVecData[25], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[25]
node _T_5141 = eq(UInt<3>(0h4), remapindex_25)
when _T_5141 :
connect remapVecData[25], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[25]
node _T_5142 = eq(UInt<3>(0h5), remapindex_25)
when _T_5142 :
connect remapVecData[25], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[25]
node _T_5143 = eq(UInt<3>(0h6), remapindex_25)
when _T_5143 :
connect remapVecData[25], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[25]
node _T_5144 = eq(UInt<3>(0h7), remapindex_25)
when _T_5144 :
connect remapVecData[25], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[25]
node _T_5145 = eq(UInt<4>(0h8), remapindex_25)
when _T_5145 :
connect remapVecData[25], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[25]
node _T_5146 = eq(UInt<4>(0h9), remapindex_25)
when _T_5146 :
connect remapVecData[25], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[25]
node _T_5147 = eq(UInt<4>(0ha), remapindex_25)
when _T_5147 :
connect remapVecData[25], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[25]
node _T_5148 = eq(UInt<4>(0hb), remapindex_25)
when _T_5148 :
connect remapVecData[25], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[25]
node _T_5149 = eq(UInt<4>(0hc), remapindex_25)
when _T_5149 :
connect remapVecData[25], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[25]
node _T_5150 = eq(UInt<4>(0hd), remapindex_25)
when _T_5150 :
connect remapVecData[25], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[25]
node _T_5151 = eq(UInt<4>(0he), remapindex_25)
when _T_5151 :
connect remapVecData[25], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[25]
node _T_5152 = eq(UInt<4>(0hf), remapindex_25)
when _T_5152 :
connect remapVecData[25], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[25]
node _T_5153 = eq(UInt<5>(0h10), remapindex_25)
when _T_5153 :
connect remapVecData[25], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[25]
node _T_5154 = eq(UInt<5>(0h11), remapindex_25)
when _T_5154 :
connect remapVecData[25], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[25]
node _T_5155 = eq(UInt<5>(0h12), remapindex_25)
when _T_5155 :
connect remapVecData[25], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[25]
node _T_5156 = eq(UInt<5>(0h13), remapindex_25)
when _T_5156 :
connect remapVecData[25], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[25]
node _T_5157 = eq(UInt<5>(0h14), remapindex_25)
when _T_5157 :
connect remapVecData[25], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[25]
node _T_5158 = eq(UInt<5>(0h15), remapindex_25)
when _T_5158 :
connect remapVecData[25], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[25]
node _T_5159 = eq(UInt<5>(0h16), remapindex_25)
when _T_5159 :
connect remapVecData[25], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[25]
node _T_5160 = eq(UInt<5>(0h17), remapindex_25)
when _T_5160 :
connect remapVecData[25], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[25]
node _T_5161 = eq(UInt<5>(0h18), remapindex_25)
when _T_5161 :
connect remapVecData[25], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[25]
node _T_5162 = eq(UInt<5>(0h19), remapindex_25)
when _T_5162 :
connect remapVecData[25], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[25]
node _T_5163 = eq(UInt<5>(0h1a), remapindex_25)
when _T_5163 :
connect remapVecData[25], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[25]
node _T_5164 = eq(UInt<5>(0h1b), remapindex_25)
when _T_5164 :
connect remapVecData[25], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[25]
node _T_5165 = eq(UInt<5>(0h1c), remapindex_25)
when _T_5165 :
connect remapVecData[25], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[25]
node _T_5166 = eq(UInt<5>(0h1d), remapindex_25)
when _T_5166 :
connect remapVecData[25], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[25]
node _T_5167 = eq(UInt<5>(0h1e), remapindex_25)
when _T_5167 :
connect remapVecData[25], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[25]
node _T_5168 = eq(UInt<5>(0h1f), remapindex_25)
when _T_5168 :
connect remapVecData[25], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[25], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[25]
node _remapindex_T_26 = add(UInt<5>(0h1a), read_start_index)
node remapindex_26 = rem(_remapindex_T_26, UInt<6>(0h20))
node _T_5169 = eq(UInt<1>(0h0), remapindex_26)
when _T_5169 :
connect remapVecData[26], Queue2_UInt8.io.deq.bits
connect remapVecValids[26], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[26]
node _T_5170 = eq(UInt<1>(0h1), remapindex_26)
when _T_5170 :
connect remapVecData[26], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[26]
node _T_5171 = eq(UInt<2>(0h2), remapindex_26)
when _T_5171 :
connect remapVecData[26], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[26]
node _T_5172 = eq(UInt<2>(0h3), remapindex_26)
when _T_5172 :
connect remapVecData[26], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[26]
node _T_5173 = eq(UInt<3>(0h4), remapindex_26)
when _T_5173 :
connect remapVecData[26], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[26]
node _T_5174 = eq(UInt<3>(0h5), remapindex_26)
when _T_5174 :
connect remapVecData[26], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[26]
node _T_5175 = eq(UInt<3>(0h6), remapindex_26)
when _T_5175 :
connect remapVecData[26], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[26]
node _T_5176 = eq(UInt<3>(0h7), remapindex_26)
when _T_5176 :
connect remapVecData[26], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[26]
node _T_5177 = eq(UInt<4>(0h8), remapindex_26)
when _T_5177 :
connect remapVecData[26], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[26]
node _T_5178 = eq(UInt<4>(0h9), remapindex_26)
when _T_5178 :
connect remapVecData[26], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[26]
node _T_5179 = eq(UInt<4>(0ha), remapindex_26)
when _T_5179 :
connect remapVecData[26], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[26]
node _T_5180 = eq(UInt<4>(0hb), remapindex_26)
when _T_5180 :
connect remapVecData[26], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[26]
node _T_5181 = eq(UInt<4>(0hc), remapindex_26)
when _T_5181 :
connect remapVecData[26], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[26]
node _T_5182 = eq(UInt<4>(0hd), remapindex_26)
when _T_5182 :
connect remapVecData[26], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[26]
node _T_5183 = eq(UInt<4>(0he), remapindex_26)
when _T_5183 :
connect remapVecData[26], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[26]
node _T_5184 = eq(UInt<4>(0hf), remapindex_26)
when _T_5184 :
connect remapVecData[26], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[26]
node _T_5185 = eq(UInt<5>(0h10), remapindex_26)
when _T_5185 :
connect remapVecData[26], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[26]
node _T_5186 = eq(UInt<5>(0h11), remapindex_26)
when _T_5186 :
connect remapVecData[26], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[26]
node _T_5187 = eq(UInt<5>(0h12), remapindex_26)
when _T_5187 :
connect remapVecData[26], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[26]
node _T_5188 = eq(UInt<5>(0h13), remapindex_26)
when _T_5188 :
connect remapVecData[26], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[26]
node _T_5189 = eq(UInt<5>(0h14), remapindex_26)
when _T_5189 :
connect remapVecData[26], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[26]
node _T_5190 = eq(UInt<5>(0h15), remapindex_26)
when _T_5190 :
connect remapVecData[26], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[26]
node _T_5191 = eq(UInt<5>(0h16), remapindex_26)
when _T_5191 :
connect remapVecData[26], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[26]
node _T_5192 = eq(UInt<5>(0h17), remapindex_26)
when _T_5192 :
connect remapVecData[26], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[26]
node _T_5193 = eq(UInt<5>(0h18), remapindex_26)
when _T_5193 :
connect remapVecData[26], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[26]
node _T_5194 = eq(UInt<5>(0h19), remapindex_26)
when _T_5194 :
connect remapVecData[26], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[26]
node _T_5195 = eq(UInt<5>(0h1a), remapindex_26)
when _T_5195 :
connect remapVecData[26], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[26]
node _T_5196 = eq(UInt<5>(0h1b), remapindex_26)
when _T_5196 :
connect remapVecData[26], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[26]
node _T_5197 = eq(UInt<5>(0h1c), remapindex_26)
when _T_5197 :
connect remapVecData[26], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[26]
node _T_5198 = eq(UInt<5>(0h1d), remapindex_26)
when _T_5198 :
connect remapVecData[26], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[26]
node _T_5199 = eq(UInt<5>(0h1e), remapindex_26)
when _T_5199 :
connect remapVecData[26], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[26]
node _T_5200 = eq(UInt<5>(0h1f), remapindex_26)
when _T_5200 :
connect remapVecData[26], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[26], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[26]
node _remapindex_T_27 = add(UInt<5>(0h1b), read_start_index)
node remapindex_27 = rem(_remapindex_T_27, UInt<6>(0h20))
node _T_5201 = eq(UInt<1>(0h0), remapindex_27)
when _T_5201 :
connect remapVecData[27], Queue2_UInt8.io.deq.bits
connect remapVecValids[27], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[27]
node _T_5202 = eq(UInt<1>(0h1), remapindex_27)
when _T_5202 :
connect remapVecData[27], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[27]
node _T_5203 = eq(UInt<2>(0h2), remapindex_27)
when _T_5203 :
connect remapVecData[27], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[27]
node _T_5204 = eq(UInt<2>(0h3), remapindex_27)
when _T_5204 :
connect remapVecData[27], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[27]
node _T_5205 = eq(UInt<3>(0h4), remapindex_27)
when _T_5205 :
connect remapVecData[27], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[27]
node _T_5206 = eq(UInt<3>(0h5), remapindex_27)
when _T_5206 :
connect remapVecData[27], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[27]
node _T_5207 = eq(UInt<3>(0h6), remapindex_27)
when _T_5207 :
connect remapVecData[27], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[27]
node _T_5208 = eq(UInt<3>(0h7), remapindex_27)
when _T_5208 :
connect remapVecData[27], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[27]
node _T_5209 = eq(UInt<4>(0h8), remapindex_27)
when _T_5209 :
connect remapVecData[27], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[27]
node _T_5210 = eq(UInt<4>(0h9), remapindex_27)
when _T_5210 :
connect remapVecData[27], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[27]
node _T_5211 = eq(UInt<4>(0ha), remapindex_27)
when _T_5211 :
connect remapVecData[27], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[27]
node _T_5212 = eq(UInt<4>(0hb), remapindex_27)
when _T_5212 :
connect remapVecData[27], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[27]
node _T_5213 = eq(UInt<4>(0hc), remapindex_27)
when _T_5213 :
connect remapVecData[27], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[27]
node _T_5214 = eq(UInt<4>(0hd), remapindex_27)
when _T_5214 :
connect remapVecData[27], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[27]
node _T_5215 = eq(UInt<4>(0he), remapindex_27)
when _T_5215 :
connect remapVecData[27], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[27]
node _T_5216 = eq(UInt<4>(0hf), remapindex_27)
when _T_5216 :
connect remapVecData[27], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[27]
node _T_5217 = eq(UInt<5>(0h10), remapindex_27)
when _T_5217 :
connect remapVecData[27], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[27]
node _T_5218 = eq(UInt<5>(0h11), remapindex_27)
when _T_5218 :
connect remapVecData[27], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[27]
node _T_5219 = eq(UInt<5>(0h12), remapindex_27)
when _T_5219 :
connect remapVecData[27], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[27]
node _T_5220 = eq(UInt<5>(0h13), remapindex_27)
when _T_5220 :
connect remapVecData[27], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[27]
node _T_5221 = eq(UInt<5>(0h14), remapindex_27)
when _T_5221 :
connect remapVecData[27], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[27]
node _T_5222 = eq(UInt<5>(0h15), remapindex_27)
when _T_5222 :
connect remapVecData[27], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[27]
node _T_5223 = eq(UInt<5>(0h16), remapindex_27)
when _T_5223 :
connect remapVecData[27], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[27]
node _T_5224 = eq(UInt<5>(0h17), remapindex_27)
when _T_5224 :
connect remapVecData[27], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[27]
node _T_5225 = eq(UInt<5>(0h18), remapindex_27)
when _T_5225 :
connect remapVecData[27], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[27]
node _T_5226 = eq(UInt<5>(0h19), remapindex_27)
when _T_5226 :
connect remapVecData[27], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[27]
node _T_5227 = eq(UInt<5>(0h1a), remapindex_27)
when _T_5227 :
connect remapVecData[27], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[27]
node _T_5228 = eq(UInt<5>(0h1b), remapindex_27)
when _T_5228 :
connect remapVecData[27], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[27]
node _T_5229 = eq(UInt<5>(0h1c), remapindex_27)
when _T_5229 :
connect remapVecData[27], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[27]
node _T_5230 = eq(UInt<5>(0h1d), remapindex_27)
when _T_5230 :
connect remapVecData[27], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[27]
node _T_5231 = eq(UInt<5>(0h1e), remapindex_27)
when _T_5231 :
connect remapVecData[27], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[27]
node _T_5232 = eq(UInt<5>(0h1f), remapindex_27)
when _T_5232 :
connect remapVecData[27], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[27], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[27]
node _remapindex_T_28 = add(UInt<5>(0h1c), read_start_index)
node remapindex_28 = rem(_remapindex_T_28, UInt<6>(0h20))
node _T_5233 = eq(UInt<1>(0h0), remapindex_28)
when _T_5233 :
connect remapVecData[28], Queue2_UInt8.io.deq.bits
connect remapVecValids[28], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[28]
node _T_5234 = eq(UInt<1>(0h1), remapindex_28)
when _T_5234 :
connect remapVecData[28], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[28]
node _T_5235 = eq(UInt<2>(0h2), remapindex_28)
when _T_5235 :
connect remapVecData[28], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[28]
node _T_5236 = eq(UInt<2>(0h3), remapindex_28)
when _T_5236 :
connect remapVecData[28], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[28]
node _T_5237 = eq(UInt<3>(0h4), remapindex_28)
when _T_5237 :
connect remapVecData[28], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[28]
node _T_5238 = eq(UInt<3>(0h5), remapindex_28)
when _T_5238 :
connect remapVecData[28], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[28]
node _T_5239 = eq(UInt<3>(0h6), remapindex_28)
when _T_5239 :
connect remapVecData[28], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[28]
node _T_5240 = eq(UInt<3>(0h7), remapindex_28)
when _T_5240 :
connect remapVecData[28], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[28]
node _T_5241 = eq(UInt<4>(0h8), remapindex_28)
when _T_5241 :
connect remapVecData[28], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[28]
node _T_5242 = eq(UInt<4>(0h9), remapindex_28)
when _T_5242 :
connect remapVecData[28], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[28]
node _T_5243 = eq(UInt<4>(0ha), remapindex_28)
when _T_5243 :
connect remapVecData[28], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[28]
node _T_5244 = eq(UInt<4>(0hb), remapindex_28)
when _T_5244 :
connect remapVecData[28], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[28]
node _T_5245 = eq(UInt<4>(0hc), remapindex_28)
when _T_5245 :
connect remapVecData[28], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[28]
node _T_5246 = eq(UInt<4>(0hd), remapindex_28)
when _T_5246 :
connect remapVecData[28], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[28]
node _T_5247 = eq(UInt<4>(0he), remapindex_28)
when _T_5247 :
connect remapVecData[28], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[28]
node _T_5248 = eq(UInt<4>(0hf), remapindex_28)
when _T_5248 :
connect remapVecData[28], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[28]
node _T_5249 = eq(UInt<5>(0h10), remapindex_28)
when _T_5249 :
connect remapVecData[28], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[28]
node _T_5250 = eq(UInt<5>(0h11), remapindex_28)
when _T_5250 :
connect remapVecData[28], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[28]
node _T_5251 = eq(UInt<5>(0h12), remapindex_28)
when _T_5251 :
connect remapVecData[28], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[28]
node _T_5252 = eq(UInt<5>(0h13), remapindex_28)
when _T_5252 :
connect remapVecData[28], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[28]
node _T_5253 = eq(UInt<5>(0h14), remapindex_28)
when _T_5253 :
connect remapVecData[28], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[28]
node _T_5254 = eq(UInt<5>(0h15), remapindex_28)
when _T_5254 :
connect remapVecData[28], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[28]
node _T_5255 = eq(UInt<5>(0h16), remapindex_28)
when _T_5255 :
connect remapVecData[28], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[28]
node _T_5256 = eq(UInt<5>(0h17), remapindex_28)
when _T_5256 :
connect remapVecData[28], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[28]
node _T_5257 = eq(UInt<5>(0h18), remapindex_28)
when _T_5257 :
connect remapVecData[28], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[28]
node _T_5258 = eq(UInt<5>(0h19), remapindex_28)
when _T_5258 :
connect remapVecData[28], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[28]
node _T_5259 = eq(UInt<5>(0h1a), remapindex_28)
when _T_5259 :
connect remapVecData[28], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[28]
node _T_5260 = eq(UInt<5>(0h1b), remapindex_28)
when _T_5260 :
connect remapVecData[28], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[28]
node _T_5261 = eq(UInt<5>(0h1c), remapindex_28)
when _T_5261 :
connect remapVecData[28], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[28]
node _T_5262 = eq(UInt<5>(0h1d), remapindex_28)
when _T_5262 :
connect remapVecData[28], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[28]
node _T_5263 = eq(UInt<5>(0h1e), remapindex_28)
when _T_5263 :
connect remapVecData[28], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[28]
node _T_5264 = eq(UInt<5>(0h1f), remapindex_28)
when _T_5264 :
connect remapVecData[28], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[28], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[28]
node _remapindex_T_29 = add(UInt<5>(0h1d), read_start_index)
node remapindex_29 = rem(_remapindex_T_29, UInt<6>(0h20))
node _T_5265 = eq(UInt<1>(0h0), remapindex_29)
when _T_5265 :
connect remapVecData[29], Queue2_UInt8.io.deq.bits
connect remapVecValids[29], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[29]
node _T_5266 = eq(UInt<1>(0h1), remapindex_29)
when _T_5266 :
connect remapVecData[29], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[29]
node _T_5267 = eq(UInt<2>(0h2), remapindex_29)
when _T_5267 :
connect remapVecData[29], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[29]
node _T_5268 = eq(UInt<2>(0h3), remapindex_29)
when _T_5268 :
connect remapVecData[29], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[29]
node _T_5269 = eq(UInt<3>(0h4), remapindex_29)
when _T_5269 :
connect remapVecData[29], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[29]
node _T_5270 = eq(UInt<3>(0h5), remapindex_29)
when _T_5270 :
connect remapVecData[29], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[29]
node _T_5271 = eq(UInt<3>(0h6), remapindex_29)
when _T_5271 :
connect remapVecData[29], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[29]
node _T_5272 = eq(UInt<3>(0h7), remapindex_29)
when _T_5272 :
connect remapVecData[29], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[29]
node _T_5273 = eq(UInt<4>(0h8), remapindex_29)
when _T_5273 :
connect remapVecData[29], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[29]
node _T_5274 = eq(UInt<4>(0h9), remapindex_29)
when _T_5274 :
connect remapVecData[29], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[29]
node _T_5275 = eq(UInt<4>(0ha), remapindex_29)
when _T_5275 :
connect remapVecData[29], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[29]
node _T_5276 = eq(UInt<4>(0hb), remapindex_29)
when _T_5276 :
connect remapVecData[29], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[29]
node _T_5277 = eq(UInt<4>(0hc), remapindex_29)
when _T_5277 :
connect remapVecData[29], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[29]
node _T_5278 = eq(UInt<4>(0hd), remapindex_29)
when _T_5278 :
connect remapVecData[29], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[29]
node _T_5279 = eq(UInt<4>(0he), remapindex_29)
when _T_5279 :
connect remapVecData[29], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[29]
node _T_5280 = eq(UInt<4>(0hf), remapindex_29)
when _T_5280 :
connect remapVecData[29], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[29]
node _T_5281 = eq(UInt<5>(0h10), remapindex_29)
when _T_5281 :
connect remapVecData[29], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[29]
node _T_5282 = eq(UInt<5>(0h11), remapindex_29)
when _T_5282 :
connect remapVecData[29], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[29]
node _T_5283 = eq(UInt<5>(0h12), remapindex_29)
when _T_5283 :
connect remapVecData[29], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[29]
node _T_5284 = eq(UInt<5>(0h13), remapindex_29)
when _T_5284 :
connect remapVecData[29], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[29]
node _T_5285 = eq(UInt<5>(0h14), remapindex_29)
when _T_5285 :
connect remapVecData[29], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[29]
node _T_5286 = eq(UInt<5>(0h15), remapindex_29)
when _T_5286 :
connect remapVecData[29], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[29]
node _T_5287 = eq(UInt<5>(0h16), remapindex_29)
when _T_5287 :
connect remapVecData[29], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[29]
node _T_5288 = eq(UInt<5>(0h17), remapindex_29)
when _T_5288 :
connect remapVecData[29], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[29]
node _T_5289 = eq(UInt<5>(0h18), remapindex_29)
when _T_5289 :
connect remapVecData[29], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[29]
node _T_5290 = eq(UInt<5>(0h19), remapindex_29)
when _T_5290 :
connect remapVecData[29], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[29]
node _T_5291 = eq(UInt<5>(0h1a), remapindex_29)
when _T_5291 :
connect remapVecData[29], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[29]
node _T_5292 = eq(UInt<5>(0h1b), remapindex_29)
when _T_5292 :
connect remapVecData[29], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[29]
node _T_5293 = eq(UInt<5>(0h1c), remapindex_29)
when _T_5293 :
connect remapVecData[29], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[29]
node _T_5294 = eq(UInt<5>(0h1d), remapindex_29)
when _T_5294 :
connect remapVecData[29], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[29]
node _T_5295 = eq(UInt<5>(0h1e), remapindex_29)
when _T_5295 :
connect remapVecData[29], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[29]
node _T_5296 = eq(UInt<5>(0h1f), remapindex_29)
when _T_5296 :
connect remapVecData[29], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[29], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[29]
node _remapindex_T_30 = add(UInt<5>(0h1e), read_start_index)
node remapindex_30 = rem(_remapindex_T_30, UInt<6>(0h20))
node _T_5297 = eq(UInt<1>(0h0), remapindex_30)
when _T_5297 :
connect remapVecData[30], Queue2_UInt8.io.deq.bits
connect remapVecValids[30], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[30]
node _T_5298 = eq(UInt<1>(0h1), remapindex_30)
when _T_5298 :
connect remapVecData[30], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[30]
node _T_5299 = eq(UInt<2>(0h2), remapindex_30)
when _T_5299 :
connect remapVecData[30], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[30]
node _T_5300 = eq(UInt<2>(0h3), remapindex_30)
when _T_5300 :
connect remapVecData[30], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[30]
node _T_5301 = eq(UInt<3>(0h4), remapindex_30)
when _T_5301 :
connect remapVecData[30], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[30]
node _T_5302 = eq(UInt<3>(0h5), remapindex_30)
when _T_5302 :
connect remapVecData[30], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[30]
node _T_5303 = eq(UInt<3>(0h6), remapindex_30)
when _T_5303 :
connect remapVecData[30], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[30]
node _T_5304 = eq(UInt<3>(0h7), remapindex_30)
when _T_5304 :
connect remapVecData[30], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[30]
node _T_5305 = eq(UInt<4>(0h8), remapindex_30)
when _T_5305 :
connect remapVecData[30], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[30]
node _T_5306 = eq(UInt<4>(0h9), remapindex_30)
when _T_5306 :
connect remapVecData[30], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[30]
node _T_5307 = eq(UInt<4>(0ha), remapindex_30)
when _T_5307 :
connect remapVecData[30], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[30]
node _T_5308 = eq(UInt<4>(0hb), remapindex_30)
when _T_5308 :
connect remapVecData[30], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[30]
node _T_5309 = eq(UInt<4>(0hc), remapindex_30)
when _T_5309 :
connect remapVecData[30], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[30]
node _T_5310 = eq(UInt<4>(0hd), remapindex_30)
when _T_5310 :
connect remapVecData[30], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[30]
node _T_5311 = eq(UInt<4>(0he), remapindex_30)
when _T_5311 :
connect remapVecData[30], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[30]
node _T_5312 = eq(UInt<4>(0hf), remapindex_30)
when _T_5312 :
connect remapVecData[30], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[30]
node _T_5313 = eq(UInt<5>(0h10), remapindex_30)
when _T_5313 :
connect remapVecData[30], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[30]
node _T_5314 = eq(UInt<5>(0h11), remapindex_30)
when _T_5314 :
connect remapVecData[30], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[30]
node _T_5315 = eq(UInt<5>(0h12), remapindex_30)
when _T_5315 :
connect remapVecData[30], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[30]
node _T_5316 = eq(UInt<5>(0h13), remapindex_30)
when _T_5316 :
connect remapVecData[30], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[30]
node _T_5317 = eq(UInt<5>(0h14), remapindex_30)
when _T_5317 :
connect remapVecData[30], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[30]
node _T_5318 = eq(UInt<5>(0h15), remapindex_30)
when _T_5318 :
connect remapVecData[30], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[30]
node _T_5319 = eq(UInt<5>(0h16), remapindex_30)
when _T_5319 :
connect remapVecData[30], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[30]
node _T_5320 = eq(UInt<5>(0h17), remapindex_30)
when _T_5320 :
connect remapVecData[30], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[30]
node _T_5321 = eq(UInt<5>(0h18), remapindex_30)
when _T_5321 :
connect remapVecData[30], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[30]
node _T_5322 = eq(UInt<5>(0h19), remapindex_30)
when _T_5322 :
connect remapVecData[30], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[30]
node _T_5323 = eq(UInt<5>(0h1a), remapindex_30)
when _T_5323 :
connect remapVecData[30], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[30]
node _T_5324 = eq(UInt<5>(0h1b), remapindex_30)
when _T_5324 :
connect remapVecData[30], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[30]
node _T_5325 = eq(UInt<5>(0h1c), remapindex_30)
when _T_5325 :
connect remapVecData[30], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[30]
node _T_5326 = eq(UInt<5>(0h1d), remapindex_30)
when _T_5326 :
connect remapVecData[30], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[30]
node _T_5327 = eq(UInt<5>(0h1e), remapindex_30)
when _T_5327 :
connect remapVecData[30], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[30]
node _T_5328 = eq(UInt<5>(0h1f), remapindex_30)
when _T_5328 :
connect remapVecData[30], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[30], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[30]
node _remapindex_T_31 = add(UInt<5>(0h1f), read_start_index)
node remapindex_31 = rem(_remapindex_T_31, UInt<6>(0h20))
node _T_5329 = eq(UInt<1>(0h0), remapindex_31)
when _T_5329 :
connect remapVecData[31], Queue2_UInt8.io.deq.bits
connect remapVecValids[31], Queue2_UInt8.io.deq.valid
connect Queue2_UInt8.io.deq.ready, remapVecReadys[31]
node _T_5330 = eq(UInt<1>(0h1), remapindex_31)
when _T_5330 :
connect remapVecData[31], Queue2_UInt8_1.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_1.io.deq.valid
connect Queue2_UInt8_1.io.deq.ready, remapVecReadys[31]
node _T_5331 = eq(UInt<2>(0h2), remapindex_31)
when _T_5331 :
connect remapVecData[31], Queue2_UInt8_2.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_2.io.deq.valid
connect Queue2_UInt8_2.io.deq.ready, remapVecReadys[31]
node _T_5332 = eq(UInt<2>(0h3), remapindex_31)
when _T_5332 :
connect remapVecData[31], Queue2_UInt8_3.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_3.io.deq.valid
connect Queue2_UInt8_3.io.deq.ready, remapVecReadys[31]
node _T_5333 = eq(UInt<3>(0h4), remapindex_31)
when _T_5333 :
connect remapVecData[31], Queue2_UInt8_4.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_4.io.deq.valid
connect Queue2_UInt8_4.io.deq.ready, remapVecReadys[31]
node _T_5334 = eq(UInt<3>(0h5), remapindex_31)
when _T_5334 :
connect remapVecData[31], Queue2_UInt8_5.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_5.io.deq.valid
connect Queue2_UInt8_5.io.deq.ready, remapVecReadys[31]
node _T_5335 = eq(UInt<3>(0h6), remapindex_31)
when _T_5335 :
connect remapVecData[31], Queue2_UInt8_6.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_6.io.deq.valid
connect Queue2_UInt8_6.io.deq.ready, remapVecReadys[31]
node _T_5336 = eq(UInt<3>(0h7), remapindex_31)
when _T_5336 :
connect remapVecData[31], Queue2_UInt8_7.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_7.io.deq.valid
connect Queue2_UInt8_7.io.deq.ready, remapVecReadys[31]
node _T_5337 = eq(UInt<4>(0h8), remapindex_31)
when _T_5337 :
connect remapVecData[31], Queue2_UInt8_8.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_8.io.deq.valid
connect Queue2_UInt8_8.io.deq.ready, remapVecReadys[31]
node _T_5338 = eq(UInt<4>(0h9), remapindex_31)
when _T_5338 :
connect remapVecData[31], Queue2_UInt8_9.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_9.io.deq.valid
connect Queue2_UInt8_9.io.deq.ready, remapVecReadys[31]
node _T_5339 = eq(UInt<4>(0ha), remapindex_31)
when _T_5339 :
connect remapVecData[31], Queue2_UInt8_10.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_10.io.deq.valid
connect Queue2_UInt8_10.io.deq.ready, remapVecReadys[31]
node _T_5340 = eq(UInt<4>(0hb), remapindex_31)
when _T_5340 :
connect remapVecData[31], Queue2_UInt8_11.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_11.io.deq.valid
connect Queue2_UInt8_11.io.deq.ready, remapVecReadys[31]
node _T_5341 = eq(UInt<4>(0hc), remapindex_31)
when _T_5341 :
connect remapVecData[31], Queue2_UInt8_12.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_12.io.deq.valid
connect Queue2_UInt8_12.io.deq.ready, remapVecReadys[31]
node _T_5342 = eq(UInt<4>(0hd), remapindex_31)
when _T_5342 :
connect remapVecData[31], Queue2_UInt8_13.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_13.io.deq.valid
connect Queue2_UInt8_13.io.deq.ready, remapVecReadys[31]
node _T_5343 = eq(UInt<4>(0he), remapindex_31)
when _T_5343 :
connect remapVecData[31], Queue2_UInt8_14.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_14.io.deq.valid
connect Queue2_UInt8_14.io.deq.ready, remapVecReadys[31]
node _T_5344 = eq(UInt<4>(0hf), remapindex_31)
when _T_5344 :
connect remapVecData[31], Queue2_UInt8_15.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_15.io.deq.valid
connect Queue2_UInt8_15.io.deq.ready, remapVecReadys[31]
node _T_5345 = eq(UInt<5>(0h10), remapindex_31)
when _T_5345 :
connect remapVecData[31], Queue2_UInt8_16.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_16.io.deq.valid
connect Queue2_UInt8_16.io.deq.ready, remapVecReadys[31]
node _T_5346 = eq(UInt<5>(0h11), remapindex_31)
when _T_5346 :
connect remapVecData[31], Queue2_UInt8_17.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_17.io.deq.valid
connect Queue2_UInt8_17.io.deq.ready, remapVecReadys[31]
node _T_5347 = eq(UInt<5>(0h12), remapindex_31)
when _T_5347 :
connect remapVecData[31], Queue2_UInt8_18.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_18.io.deq.valid
connect Queue2_UInt8_18.io.deq.ready, remapVecReadys[31]
node _T_5348 = eq(UInt<5>(0h13), remapindex_31)
when _T_5348 :
connect remapVecData[31], Queue2_UInt8_19.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_19.io.deq.valid
connect Queue2_UInt8_19.io.deq.ready, remapVecReadys[31]
node _T_5349 = eq(UInt<5>(0h14), remapindex_31)
when _T_5349 :
connect remapVecData[31], Queue2_UInt8_20.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_20.io.deq.valid
connect Queue2_UInt8_20.io.deq.ready, remapVecReadys[31]
node _T_5350 = eq(UInt<5>(0h15), remapindex_31)
when _T_5350 :
connect remapVecData[31], Queue2_UInt8_21.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_21.io.deq.valid
connect Queue2_UInt8_21.io.deq.ready, remapVecReadys[31]
node _T_5351 = eq(UInt<5>(0h16), remapindex_31)
when _T_5351 :
connect remapVecData[31], Queue2_UInt8_22.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_22.io.deq.valid
connect Queue2_UInt8_22.io.deq.ready, remapVecReadys[31]
node _T_5352 = eq(UInt<5>(0h17), remapindex_31)
when _T_5352 :
connect remapVecData[31], Queue2_UInt8_23.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_23.io.deq.valid
connect Queue2_UInt8_23.io.deq.ready, remapVecReadys[31]
node _T_5353 = eq(UInt<5>(0h18), remapindex_31)
when _T_5353 :
connect remapVecData[31], Queue2_UInt8_24.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_24.io.deq.valid
connect Queue2_UInt8_24.io.deq.ready, remapVecReadys[31]
node _T_5354 = eq(UInt<5>(0h19), remapindex_31)
when _T_5354 :
connect remapVecData[31], Queue2_UInt8_25.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_25.io.deq.valid
connect Queue2_UInt8_25.io.deq.ready, remapVecReadys[31]
node _T_5355 = eq(UInt<5>(0h1a), remapindex_31)
when _T_5355 :
connect remapVecData[31], Queue2_UInt8_26.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_26.io.deq.valid
connect Queue2_UInt8_26.io.deq.ready, remapVecReadys[31]
node _T_5356 = eq(UInt<5>(0h1b), remapindex_31)
when _T_5356 :
connect remapVecData[31], Queue2_UInt8_27.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_27.io.deq.valid
connect Queue2_UInt8_27.io.deq.ready, remapVecReadys[31]
node _T_5357 = eq(UInt<5>(0h1c), remapindex_31)
when _T_5357 :
connect remapVecData[31], Queue2_UInt8_28.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_28.io.deq.valid
connect Queue2_UInt8_28.io.deq.ready, remapVecReadys[31]
node _T_5358 = eq(UInt<5>(0h1d), remapindex_31)
when _T_5358 :
connect remapVecData[31], Queue2_UInt8_29.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_29.io.deq.valid
connect Queue2_UInt8_29.io.deq.ready, remapVecReadys[31]
node _T_5359 = eq(UInt<5>(0h1e), remapindex_31)
when _T_5359 :
connect remapVecData[31], Queue2_UInt8_30.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_30.io.deq.valid
connect Queue2_UInt8_30.io.deq.ready, remapVecReadys[31]
node _T_5360 = eq(UInt<5>(0h1f), remapindex_31)
when _T_5360 :
connect remapVecData[31], Queue2_UInt8_31.io.deq.bits
connect remapVecValids[31], Queue2_UInt8_31.io.deq.valid
connect Queue2_UInt8_31.io.deq.ready, remapVecReadys[31]
node _count_valids_T = add(remapVecValids[0], remapVecValids[1])
node _count_valids_T_1 = add(_count_valids_T, remapVecValids[2])
node _count_valids_T_2 = add(_count_valids_T_1, remapVecValids[3])
node _count_valids_T_3 = add(_count_valids_T_2, remapVecValids[4])
node _count_valids_T_4 = add(_count_valids_T_3, remapVecValids[5])
node _count_valids_T_5 = add(_count_valids_T_4, remapVecValids[6])
node _count_valids_T_6 = add(_count_valids_T_5, remapVecValids[7])
node _count_valids_T_7 = add(_count_valids_T_6, remapVecValids[8])
node _count_valids_T_8 = add(_count_valids_T_7, remapVecValids[9])
node _count_valids_T_9 = add(_count_valids_T_8, remapVecValids[10])
node _count_valids_T_10 = add(_count_valids_T_9, remapVecValids[11])
node _count_valids_T_11 = add(_count_valids_T_10, remapVecValids[12])
node _count_valids_T_12 = add(_count_valids_T_11, remapVecValids[13])
node _count_valids_T_13 = add(_count_valids_T_12, remapVecValids[14])
node _count_valids_T_14 = add(_count_valids_T_13, remapVecValids[15])
node _count_valids_T_15 = add(_count_valids_T_14, remapVecValids[16])
node _count_valids_T_16 = add(_count_valids_T_15, remapVecValids[17])
node _count_valids_T_17 = add(_count_valids_T_16, remapVecValids[18])
node _count_valids_T_18 = add(_count_valids_T_17, remapVecValids[19])
node _count_valids_T_19 = add(_count_valids_T_18, remapVecValids[20])
node _count_valids_T_20 = add(_count_valids_T_19, remapVecValids[21])
node _count_valids_T_21 = add(_count_valids_T_20, remapVecValids[22])
node _count_valids_T_22 = add(_count_valids_T_21, remapVecValids[23])
node _count_valids_T_23 = add(_count_valids_T_22, remapVecValids[24])
node _count_valids_T_24 = add(_count_valids_T_23, remapVecValids[25])
node _count_valids_T_25 = add(_count_valids_T_24, remapVecValids[26])
node _count_valids_T_26 = add(_count_valids_T_25, remapVecValids[27])
node _count_valids_T_27 = add(_count_valids_T_26, remapVecValids[28])
node _count_valids_T_28 = add(_count_valids_T_27, remapVecValids[29])
node _count_valids_T_29 = add(_count_valids_T_28, remapVecValids[30])
node count_valids = add(_count_valids_T_29, remapVecValids[31])
regreset backend_bytes_written : UInt<64>, clock, reset, UInt<64>(0h0)
node _backend_next_write_addr_T = add(dest_info_Q.io.deq.bits.op, backend_bytes_written)
node backend_next_write_addr = tail(_backend_next_write_addr_T, 1)
node _throttle_end_T = sub(buf_lens_Q.io.deq.bits, backend_bytes_written)
node _throttle_end_T_1 = tail(_throttle_end_T, 1)
node throttle_end = mux(buf_lens_Q.io.deq.valid, _throttle_end_T_1, UInt<6>(0h20))
node _throttle_end_writeable_T = geq(throttle_end, UInt<6>(0h20))
node _throttle_end_writeable_T_1 = bits(throttle_end, 4, 4)
node _throttle_end_writeable_T_2 = bits(throttle_end, 3, 3)
node _throttle_end_writeable_T_3 = bits(throttle_end, 2, 2)
node _throttle_end_writeable_T_4 = bits(throttle_end, 1, 1)
node _throttle_end_writeable_T_5 = bits(throttle_end, 0, 0)
node _throttle_end_writeable_T_6 = mux(_throttle_end_writeable_T_5, UInt<1>(0h1), UInt<1>(0h0))
node _throttle_end_writeable_T_7 = mux(_throttle_end_writeable_T_4, UInt<2>(0h2), _throttle_end_writeable_T_6)
node _throttle_end_writeable_T_8 = mux(_throttle_end_writeable_T_3, UInt<3>(0h4), _throttle_end_writeable_T_7)
node _throttle_end_writeable_T_9 = mux(_throttle_end_writeable_T_2, UInt<4>(0h8), _throttle_end_writeable_T_8)
node _throttle_end_writeable_T_10 = mux(_throttle_end_writeable_T_1, UInt<5>(0h10), _throttle_end_writeable_T_9)
node throttle_end_writeable = mux(_throttle_end_writeable_T, UInt<6>(0h20), _throttle_end_writeable_T_10)
node _throttle_end_writeable_log2_T = geq(throttle_end, UInt<6>(0h20))
node _throttle_end_writeable_log2_T_1 = bits(throttle_end, 4, 4)
node _throttle_end_writeable_log2_T_2 = bits(throttle_end, 3, 3)
node _throttle_end_writeable_log2_T_3 = bits(throttle_end, 2, 2)
node _throttle_end_writeable_log2_T_4 = bits(throttle_end, 1, 1)
node _throttle_end_writeable_log2_T_5 = bits(throttle_end, 0, 0)
node _throttle_end_writeable_log2_T_6 = mux(_throttle_end_writeable_log2_T_5, UInt<1>(0h0), UInt<1>(0h0))
node _throttle_end_writeable_log2_T_7 = mux(_throttle_end_writeable_log2_T_4, UInt<1>(0h1), _throttle_end_writeable_log2_T_6)
node _throttle_end_writeable_log2_T_8 = mux(_throttle_end_writeable_log2_T_3, UInt<2>(0h2), _throttle_end_writeable_log2_T_7)
node _throttle_end_writeable_log2_T_9 = mux(_throttle_end_writeable_log2_T_2, UInt<2>(0h3), _throttle_end_writeable_log2_T_8)
node _throttle_end_writeable_log2_T_10 = mux(_throttle_end_writeable_log2_T_1, UInt<3>(0h4), _throttle_end_writeable_log2_T_9)
node throttle_end_writeable_log2 = mux(_throttle_end_writeable_log2_T, UInt<3>(0h5), _throttle_end_writeable_log2_T_10)
node _ptr_align_max_bytes_writeable_T = bits(backend_next_write_addr, 0, 0)
node _ptr_align_max_bytes_writeable_T_1 = bits(backend_next_write_addr, 1, 1)
node _ptr_align_max_bytes_writeable_T_2 = bits(backend_next_write_addr, 2, 2)
node _ptr_align_max_bytes_writeable_T_3 = bits(backend_next_write_addr, 3, 3)
node _ptr_align_max_bytes_writeable_T_4 = bits(backend_next_write_addr, 4, 4)
node _ptr_align_max_bytes_writeable_T_5 = mux(_ptr_align_max_bytes_writeable_T_4, UInt<5>(0h10), UInt<6>(0h20))
node _ptr_align_max_bytes_writeable_T_6 = mux(_ptr_align_max_bytes_writeable_T_3, UInt<4>(0h8), _ptr_align_max_bytes_writeable_T_5)
node _ptr_align_max_bytes_writeable_T_7 = mux(_ptr_align_max_bytes_writeable_T_2, UInt<3>(0h4), _ptr_align_max_bytes_writeable_T_6)
node _ptr_align_max_bytes_writeable_T_8 = mux(_ptr_align_max_bytes_writeable_T_1, UInt<2>(0h2), _ptr_align_max_bytes_writeable_T_7)
node ptr_align_max_bytes_writeable = mux(_ptr_align_max_bytes_writeable_T, UInt<1>(0h1), _ptr_align_max_bytes_writeable_T_8)
node _ptr_align_max_bytes_writeable_log2_T = bits(backend_next_write_addr, 0, 0)
node _ptr_align_max_bytes_writeable_log2_T_1 = bits(backend_next_write_addr, 1, 1)
node _ptr_align_max_bytes_writeable_log2_T_2 = bits(backend_next_write_addr, 2, 2)
node _ptr_align_max_bytes_writeable_log2_T_3 = bits(backend_next_write_addr, 3, 3)
node _ptr_align_max_bytes_writeable_log2_T_4 = bits(backend_next_write_addr, 4, 4)
node _ptr_align_max_bytes_writeable_log2_T_5 = mux(_ptr_align_max_bytes_writeable_log2_T_4, UInt<3>(0h4), UInt<3>(0h5))
node _ptr_align_max_bytes_writeable_log2_T_6 = mux(_ptr_align_max_bytes_writeable_log2_T_3, UInt<2>(0h3), _ptr_align_max_bytes_writeable_log2_T_5)
node _ptr_align_max_bytes_writeable_log2_T_7 = mux(_ptr_align_max_bytes_writeable_log2_T_2, UInt<2>(0h2), _ptr_align_max_bytes_writeable_log2_T_6)
node _ptr_align_max_bytes_writeable_log2_T_8 = mux(_ptr_align_max_bytes_writeable_log2_T_1, UInt<1>(0h1), _ptr_align_max_bytes_writeable_log2_T_7)
node ptr_align_max_bytes_writeable_log2 = mux(_ptr_align_max_bytes_writeable_log2_T, UInt<1>(0h0), _ptr_align_max_bytes_writeable_log2_T_8)
node _count_valids_largest_aligned_T = bits(count_valids, 5, 5)
node _count_valids_largest_aligned_T_1 = bits(count_valids, 4, 4)
node _count_valids_largest_aligned_T_2 = bits(count_valids, 3, 3)
node _count_valids_largest_aligned_T_3 = bits(count_valids, 2, 2)
node _count_valids_largest_aligned_T_4 = bits(count_valids, 1, 1)
node _count_valids_largest_aligned_T_5 = bits(count_valids, 0, 0)
node _count_valids_largest_aligned_T_6 = mux(_count_valids_largest_aligned_T_5, UInt<1>(0h1), UInt<1>(0h0))
node _count_valids_largest_aligned_T_7 = mux(_count_valids_largest_aligned_T_4, UInt<2>(0h2), _count_valids_largest_aligned_T_6)
node _count_valids_largest_aligned_T_8 = mux(_count_valids_largest_aligned_T_3, UInt<3>(0h4), _count_valids_largest_aligned_T_7)
node _count_valids_largest_aligned_T_9 = mux(_count_valids_largest_aligned_T_2, UInt<4>(0h8), _count_valids_largest_aligned_T_8)
node _count_valids_largest_aligned_T_10 = mux(_count_valids_largest_aligned_T_1, UInt<5>(0h10), _count_valids_largest_aligned_T_9)
node count_valids_largest_aligned = mux(_count_valids_largest_aligned_T, UInt<6>(0h20), _count_valids_largest_aligned_T_10)
node _count_valids_largest_aligned_log2_T = bits(count_valids, 5, 5)
node _count_valids_largest_aligned_log2_T_1 = bits(count_valids, 4, 4)
node _count_valids_largest_aligned_log2_T_2 = bits(count_valids, 3, 3)
node _count_valids_largest_aligned_log2_T_3 = bits(count_valids, 2, 2)
node _count_valids_largest_aligned_log2_T_4 = bits(count_valids, 1, 1)
node _count_valids_largest_aligned_log2_T_5 = bits(count_valids, 0, 0)
node _count_valids_largest_aligned_log2_T_6 = mux(_count_valids_largest_aligned_log2_T_5, UInt<1>(0h0), UInt<1>(0h0))
node _count_valids_largest_aligned_log2_T_7 = mux(_count_valids_largest_aligned_log2_T_4, UInt<1>(0h1), _count_valids_largest_aligned_log2_T_6)
node _count_valids_largest_aligned_log2_T_8 = mux(_count_valids_largest_aligned_log2_T_3, UInt<2>(0h2), _count_valids_largest_aligned_log2_T_7)
node _count_valids_largest_aligned_log2_T_9 = mux(_count_valids_largest_aligned_log2_T_2, UInt<2>(0h3), _count_valids_largest_aligned_log2_T_8)
node _count_valids_largest_aligned_log2_T_10 = mux(_count_valids_largest_aligned_log2_T_1, UInt<3>(0h4), _count_valids_largest_aligned_log2_T_9)
node count_valids_largest_aligned_log2 = mux(_count_valids_largest_aligned_log2_T, UInt<3>(0h5), _count_valids_largest_aligned_log2_T_10)
node _bytes_to_write_T = lt(ptr_align_max_bytes_writeable, count_valids_largest_aligned)
node _bytes_to_write_T_1 = lt(ptr_align_max_bytes_writeable, throttle_end_writeable)
node _bytes_to_write_T_2 = mux(_bytes_to_write_T_1, ptr_align_max_bytes_writeable, throttle_end_writeable)
node _bytes_to_write_T_3 = lt(count_valids_largest_aligned, throttle_end_writeable)
node _bytes_to_write_T_4 = mux(_bytes_to_write_T_3, count_valids_largest_aligned, throttle_end_writeable)
node bytes_to_write = mux(_bytes_to_write_T, _bytes_to_write_T_2, _bytes_to_write_T_4)
node remapped_write_data_lo_lo_lo_lo = cat(remapVecData[1], remapVecData[0])
node remapped_write_data_lo_lo_lo_hi = cat(remapVecData[3], remapVecData[2])
node remapped_write_data_lo_lo_lo = cat(remapped_write_data_lo_lo_lo_hi, remapped_write_data_lo_lo_lo_lo)
node remapped_write_data_lo_lo_hi_lo = cat(remapVecData[5], remapVecData[4])
node remapped_write_data_lo_lo_hi_hi = cat(remapVecData[7], remapVecData[6])
node remapped_write_data_lo_lo_hi = cat(remapped_write_data_lo_lo_hi_hi, remapped_write_data_lo_lo_hi_lo)
node remapped_write_data_lo_lo = cat(remapped_write_data_lo_lo_hi, remapped_write_data_lo_lo_lo)
node remapped_write_data_lo_hi_lo_lo = cat(remapVecData[9], remapVecData[8])
node remapped_write_data_lo_hi_lo_hi = cat(remapVecData[11], remapVecData[10])
node remapped_write_data_lo_hi_lo = cat(remapped_write_data_lo_hi_lo_hi, remapped_write_data_lo_hi_lo_lo)
node remapped_write_data_lo_hi_hi_lo = cat(remapVecData[13], remapVecData[12])
node remapped_write_data_lo_hi_hi_hi = cat(remapVecData[15], remapVecData[14])
node remapped_write_data_lo_hi_hi = cat(remapped_write_data_lo_hi_hi_hi, remapped_write_data_lo_hi_hi_lo)
node remapped_write_data_lo_hi = cat(remapped_write_data_lo_hi_hi, remapped_write_data_lo_hi_lo)
node remapped_write_data_lo = cat(remapped_write_data_lo_hi, remapped_write_data_lo_lo)
node remapped_write_data_hi_lo_lo_lo = cat(remapVecData[17], remapVecData[16])
node remapped_write_data_hi_lo_lo_hi = cat(remapVecData[19], remapVecData[18])
node remapped_write_data_hi_lo_lo = cat(remapped_write_data_hi_lo_lo_hi, remapped_write_data_hi_lo_lo_lo)
node remapped_write_data_hi_lo_hi_lo = cat(remapVecData[21], remapVecData[20])
node remapped_write_data_hi_lo_hi_hi = cat(remapVecData[23], remapVecData[22])
node remapped_write_data_hi_lo_hi = cat(remapped_write_data_hi_lo_hi_hi, remapped_write_data_hi_lo_hi_lo)
node remapped_write_data_hi_lo = cat(remapped_write_data_hi_lo_hi, remapped_write_data_hi_lo_lo)
node remapped_write_data_hi_hi_lo_lo = cat(remapVecData[25], remapVecData[24])
node remapped_write_data_hi_hi_lo_hi = cat(remapVecData[27], remapVecData[26])
node remapped_write_data_hi_hi_lo = cat(remapped_write_data_hi_hi_lo_hi, remapped_write_data_hi_hi_lo_lo)
node remapped_write_data_hi_hi_hi_lo = cat(remapVecData[29], remapVecData[28])
node remapped_write_data_hi_hi_hi_hi = cat(remapVecData[31], remapVecData[30])
node remapped_write_data_hi_hi_hi = cat(remapped_write_data_hi_hi_hi_hi, remapped_write_data_hi_hi_hi_lo)
node remapped_write_data_hi_hi = cat(remapped_write_data_hi_hi_hi, remapped_write_data_hi_hi_lo)
node remapped_write_data_hi = cat(remapped_write_data_hi_hi, remapped_write_data_hi_lo)
node remapped_write_data = cat(remapped_write_data_hi, remapped_write_data_lo)
node enough_data = neq(bytes_to_write, UInt<1>(0h0))
node _bytes_to_write_log2_T = lt(ptr_align_max_bytes_writeable_log2, count_valids_largest_aligned_log2)
node _bytes_to_write_log2_T_1 = lt(ptr_align_max_bytes_writeable_log2, throttle_end_writeable_log2)
node _bytes_to_write_log2_T_2 = mux(_bytes_to_write_log2_T_1, ptr_align_max_bytes_writeable_log2, throttle_end_writeable_log2)
node _bytes_to_write_log2_T_3 = lt(count_valids_largest_aligned_log2, throttle_end_writeable_log2)
node _bytes_to_write_log2_T_4 = mux(_bytes_to_write_log2_T_3, count_valids_largest_aligned_log2, throttle_end_writeable_log2)
node bytes_to_write_log2 = mux(_bytes_to_write_log2_T, _bytes_to_write_log2_T_2, _bytes_to_write_log2_T_4)
node _write_ptr_override_T = eq(buf_lens_Q.io.deq.bits, backend_bytes_written)
node write_ptr_override = and(buf_lens_Q.io.deq.valid, _write_ptr_override_T)
node _T_5361 = eq(write_ptr_override, UInt<1>(0h0))
node _T_5362 = eq(buf_lens_Q.io.deq.bits, backend_bytes_written)
node _remapVecReadys_0_T = lt(UInt<1>(0h0), bytes_to_write)
node _remapVecReadys_0_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_0_T_2 = and(_remapVecReadys_0_T_1, _T_5361)
node _remapVecReadys_0_T_3 = and(_remapVecReadys_0_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_0_T_4 = and(_remapVecReadys_0_T, _remapVecReadys_0_T_3)
connect remapVecReadys[0], _remapVecReadys_0_T_4
node _remapVecReadys_1_T = lt(UInt<1>(0h1), bytes_to_write)
node _remapVecReadys_1_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_1_T_2 = and(_remapVecReadys_1_T_1, _T_5361)
node _remapVecReadys_1_T_3 = and(_remapVecReadys_1_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_1_T_4 = and(_remapVecReadys_1_T, _remapVecReadys_1_T_3)
connect remapVecReadys[1], _remapVecReadys_1_T_4
node _remapVecReadys_2_T = lt(UInt<2>(0h2), bytes_to_write)
node _remapVecReadys_2_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_2_T_2 = and(_remapVecReadys_2_T_1, _T_5361)
node _remapVecReadys_2_T_3 = and(_remapVecReadys_2_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_2_T_4 = and(_remapVecReadys_2_T, _remapVecReadys_2_T_3)
connect remapVecReadys[2], _remapVecReadys_2_T_4
node _remapVecReadys_3_T = lt(UInt<2>(0h3), bytes_to_write)
node _remapVecReadys_3_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_3_T_2 = and(_remapVecReadys_3_T_1, _T_5361)
node _remapVecReadys_3_T_3 = and(_remapVecReadys_3_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_3_T_4 = and(_remapVecReadys_3_T, _remapVecReadys_3_T_3)
connect remapVecReadys[3], _remapVecReadys_3_T_4
node _remapVecReadys_4_T = lt(UInt<3>(0h4), bytes_to_write)
node _remapVecReadys_4_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_4_T_2 = and(_remapVecReadys_4_T_1, _T_5361)
node _remapVecReadys_4_T_3 = and(_remapVecReadys_4_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_4_T_4 = and(_remapVecReadys_4_T, _remapVecReadys_4_T_3)
connect remapVecReadys[4], _remapVecReadys_4_T_4
node _remapVecReadys_5_T = lt(UInt<3>(0h5), bytes_to_write)
node _remapVecReadys_5_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_5_T_2 = and(_remapVecReadys_5_T_1, _T_5361)
node _remapVecReadys_5_T_3 = and(_remapVecReadys_5_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_5_T_4 = and(_remapVecReadys_5_T, _remapVecReadys_5_T_3)
connect remapVecReadys[5], _remapVecReadys_5_T_4
node _remapVecReadys_6_T = lt(UInt<3>(0h6), bytes_to_write)
node _remapVecReadys_6_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_6_T_2 = and(_remapVecReadys_6_T_1, _T_5361)
node _remapVecReadys_6_T_3 = and(_remapVecReadys_6_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_6_T_4 = and(_remapVecReadys_6_T, _remapVecReadys_6_T_3)
connect remapVecReadys[6], _remapVecReadys_6_T_4
node _remapVecReadys_7_T = lt(UInt<3>(0h7), bytes_to_write)
node _remapVecReadys_7_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_7_T_2 = and(_remapVecReadys_7_T_1, _T_5361)
node _remapVecReadys_7_T_3 = and(_remapVecReadys_7_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_7_T_4 = and(_remapVecReadys_7_T, _remapVecReadys_7_T_3)
connect remapVecReadys[7], _remapVecReadys_7_T_4
node _remapVecReadys_8_T = lt(UInt<4>(0h8), bytes_to_write)
node _remapVecReadys_8_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_8_T_2 = and(_remapVecReadys_8_T_1, _T_5361)
node _remapVecReadys_8_T_3 = and(_remapVecReadys_8_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_8_T_4 = and(_remapVecReadys_8_T, _remapVecReadys_8_T_3)
connect remapVecReadys[8], _remapVecReadys_8_T_4
node _remapVecReadys_9_T = lt(UInt<4>(0h9), bytes_to_write)
node _remapVecReadys_9_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_9_T_2 = and(_remapVecReadys_9_T_1, _T_5361)
node _remapVecReadys_9_T_3 = and(_remapVecReadys_9_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_9_T_4 = and(_remapVecReadys_9_T, _remapVecReadys_9_T_3)
connect remapVecReadys[9], _remapVecReadys_9_T_4
node _remapVecReadys_10_T = lt(UInt<4>(0ha), bytes_to_write)
node _remapVecReadys_10_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_10_T_2 = and(_remapVecReadys_10_T_1, _T_5361)
node _remapVecReadys_10_T_3 = and(_remapVecReadys_10_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_10_T_4 = and(_remapVecReadys_10_T, _remapVecReadys_10_T_3)
connect remapVecReadys[10], _remapVecReadys_10_T_4
node _remapVecReadys_11_T = lt(UInt<4>(0hb), bytes_to_write)
node _remapVecReadys_11_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_11_T_2 = and(_remapVecReadys_11_T_1, _T_5361)
node _remapVecReadys_11_T_3 = and(_remapVecReadys_11_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_11_T_4 = and(_remapVecReadys_11_T, _remapVecReadys_11_T_3)
connect remapVecReadys[11], _remapVecReadys_11_T_4
node _remapVecReadys_12_T = lt(UInt<4>(0hc), bytes_to_write)
node _remapVecReadys_12_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_12_T_2 = and(_remapVecReadys_12_T_1, _T_5361)
node _remapVecReadys_12_T_3 = and(_remapVecReadys_12_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_12_T_4 = and(_remapVecReadys_12_T, _remapVecReadys_12_T_3)
connect remapVecReadys[12], _remapVecReadys_12_T_4
node _remapVecReadys_13_T = lt(UInt<4>(0hd), bytes_to_write)
node _remapVecReadys_13_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_13_T_2 = and(_remapVecReadys_13_T_1, _T_5361)
node _remapVecReadys_13_T_3 = and(_remapVecReadys_13_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_13_T_4 = and(_remapVecReadys_13_T, _remapVecReadys_13_T_3)
connect remapVecReadys[13], _remapVecReadys_13_T_4
node _remapVecReadys_14_T = lt(UInt<4>(0he), bytes_to_write)
node _remapVecReadys_14_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_14_T_2 = and(_remapVecReadys_14_T_1, _T_5361)
node _remapVecReadys_14_T_3 = and(_remapVecReadys_14_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_14_T_4 = and(_remapVecReadys_14_T, _remapVecReadys_14_T_3)
connect remapVecReadys[14], _remapVecReadys_14_T_4
node _remapVecReadys_15_T = lt(UInt<4>(0hf), bytes_to_write)
node _remapVecReadys_15_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_15_T_2 = and(_remapVecReadys_15_T_1, _T_5361)
node _remapVecReadys_15_T_3 = and(_remapVecReadys_15_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_15_T_4 = and(_remapVecReadys_15_T, _remapVecReadys_15_T_3)
connect remapVecReadys[15], _remapVecReadys_15_T_4
node _remapVecReadys_16_T = lt(UInt<5>(0h10), bytes_to_write)
node _remapVecReadys_16_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_16_T_2 = and(_remapVecReadys_16_T_1, _T_5361)
node _remapVecReadys_16_T_3 = and(_remapVecReadys_16_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_16_T_4 = and(_remapVecReadys_16_T, _remapVecReadys_16_T_3)
connect remapVecReadys[16], _remapVecReadys_16_T_4
node _remapVecReadys_17_T = lt(UInt<5>(0h11), bytes_to_write)
node _remapVecReadys_17_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_17_T_2 = and(_remapVecReadys_17_T_1, _T_5361)
node _remapVecReadys_17_T_3 = and(_remapVecReadys_17_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_17_T_4 = and(_remapVecReadys_17_T, _remapVecReadys_17_T_3)
connect remapVecReadys[17], _remapVecReadys_17_T_4
node _remapVecReadys_18_T = lt(UInt<5>(0h12), bytes_to_write)
node _remapVecReadys_18_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_18_T_2 = and(_remapVecReadys_18_T_1, _T_5361)
node _remapVecReadys_18_T_3 = and(_remapVecReadys_18_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_18_T_4 = and(_remapVecReadys_18_T, _remapVecReadys_18_T_3)
connect remapVecReadys[18], _remapVecReadys_18_T_4
node _remapVecReadys_19_T = lt(UInt<5>(0h13), bytes_to_write)
node _remapVecReadys_19_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_19_T_2 = and(_remapVecReadys_19_T_1, _T_5361)
node _remapVecReadys_19_T_3 = and(_remapVecReadys_19_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_19_T_4 = and(_remapVecReadys_19_T, _remapVecReadys_19_T_3)
connect remapVecReadys[19], _remapVecReadys_19_T_4
node _remapVecReadys_20_T = lt(UInt<5>(0h14), bytes_to_write)
node _remapVecReadys_20_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_20_T_2 = and(_remapVecReadys_20_T_1, _T_5361)
node _remapVecReadys_20_T_3 = and(_remapVecReadys_20_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_20_T_4 = and(_remapVecReadys_20_T, _remapVecReadys_20_T_3)
connect remapVecReadys[20], _remapVecReadys_20_T_4
node _remapVecReadys_21_T = lt(UInt<5>(0h15), bytes_to_write)
node _remapVecReadys_21_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_21_T_2 = and(_remapVecReadys_21_T_1, _T_5361)
node _remapVecReadys_21_T_3 = and(_remapVecReadys_21_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_21_T_4 = and(_remapVecReadys_21_T, _remapVecReadys_21_T_3)
connect remapVecReadys[21], _remapVecReadys_21_T_4
node _remapVecReadys_22_T = lt(UInt<5>(0h16), bytes_to_write)
node _remapVecReadys_22_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_22_T_2 = and(_remapVecReadys_22_T_1, _T_5361)
node _remapVecReadys_22_T_3 = and(_remapVecReadys_22_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_22_T_4 = and(_remapVecReadys_22_T, _remapVecReadys_22_T_3)
connect remapVecReadys[22], _remapVecReadys_22_T_4
node _remapVecReadys_23_T = lt(UInt<5>(0h17), bytes_to_write)
node _remapVecReadys_23_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_23_T_2 = and(_remapVecReadys_23_T_1, _T_5361)
node _remapVecReadys_23_T_3 = and(_remapVecReadys_23_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_23_T_4 = and(_remapVecReadys_23_T, _remapVecReadys_23_T_3)
connect remapVecReadys[23], _remapVecReadys_23_T_4
node _remapVecReadys_24_T = lt(UInt<5>(0h18), bytes_to_write)
node _remapVecReadys_24_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_24_T_2 = and(_remapVecReadys_24_T_1, _T_5361)
node _remapVecReadys_24_T_3 = and(_remapVecReadys_24_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_24_T_4 = and(_remapVecReadys_24_T, _remapVecReadys_24_T_3)
connect remapVecReadys[24], _remapVecReadys_24_T_4
node _remapVecReadys_25_T = lt(UInt<5>(0h19), bytes_to_write)
node _remapVecReadys_25_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_25_T_2 = and(_remapVecReadys_25_T_1, _T_5361)
node _remapVecReadys_25_T_3 = and(_remapVecReadys_25_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_25_T_4 = and(_remapVecReadys_25_T, _remapVecReadys_25_T_3)
connect remapVecReadys[25], _remapVecReadys_25_T_4
node _remapVecReadys_26_T = lt(UInt<5>(0h1a), bytes_to_write)
node _remapVecReadys_26_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_26_T_2 = and(_remapVecReadys_26_T_1, _T_5361)
node _remapVecReadys_26_T_3 = and(_remapVecReadys_26_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_26_T_4 = and(_remapVecReadys_26_T, _remapVecReadys_26_T_3)
connect remapVecReadys[26], _remapVecReadys_26_T_4
node _remapVecReadys_27_T = lt(UInt<5>(0h1b), bytes_to_write)
node _remapVecReadys_27_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_27_T_2 = and(_remapVecReadys_27_T_1, _T_5361)
node _remapVecReadys_27_T_3 = and(_remapVecReadys_27_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_27_T_4 = and(_remapVecReadys_27_T, _remapVecReadys_27_T_3)
connect remapVecReadys[27], _remapVecReadys_27_T_4
node _remapVecReadys_28_T = lt(UInt<5>(0h1c), bytes_to_write)
node _remapVecReadys_28_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_28_T_2 = and(_remapVecReadys_28_T_1, _T_5361)
node _remapVecReadys_28_T_3 = and(_remapVecReadys_28_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_28_T_4 = and(_remapVecReadys_28_T, _remapVecReadys_28_T_3)
connect remapVecReadys[28], _remapVecReadys_28_T_4
node _remapVecReadys_29_T = lt(UInt<5>(0h1d), bytes_to_write)
node _remapVecReadys_29_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_29_T_2 = and(_remapVecReadys_29_T_1, _T_5361)
node _remapVecReadys_29_T_3 = and(_remapVecReadys_29_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_29_T_4 = and(_remapVecReadys_29_T, _remapVecReadys_29_T_3)
connect remapVecReadys[29], _remapVecReadys_29_T_4
node _remapVecReadys_30_T = lt(UInt<5>(0h1e), bytes_to_write)
node _remapVecReadys_30_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_30_T_2 = and(_remapVecReadys_30_T_1, _T_5361)
node _remapVecReadys_30_T_3 = and(_remapVecReadys_30_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_30_T_4 = and(_remapVecReadys_30_T, _remapVecReadys_30_T_3)
connect remapVecReadys[30], _remapVecReadys_30_T_4
node _remapVecReadys_31_T = lt(UInt<5>(0h1f), bytes_to_write)
node _remapVecReadys_31_T_1 = and(io.l2io.req.ready, enough_data)
node _remapVecReadys_31_T_2 = and(_remapVecReadys_31_T_1, _T_5361)
node _remapVecReadys_31_T_3 = and(_remapVecReadys_31_T_2, dest_info_Q.io.deq.valid)
node _remapVecReadys_31_T_4 = and(_remapVecReadys_31_T, _remapVecReadys_31_T_3)
connect remapVecReadys[31], _remapVecReadys_31_T_4
node _T_5363 = and(io.l2io.req.ready, enough_data)
node _T_5364 = and(_T_5363, _T_5361)
node _T_5365 = and(_T_5364, dest_info_Q.io.deq.valid)
when _T_5365 :
node _read_start_index_T = add(read_start_index, bytes_to_write)
node _read_start_index_T_1 = rem(_read_start_index_T, UInt<6>(0h20))
connect read_start_index, _read_start_index_T_1
node _backend_bytes_written_T = add(backend_bytes_written, bytes_to_write)
node _backend_bytes_written_T_1 = tail(_backend_bytes_written_T, 1)
connect backend_bytes_written, _backend_bytes_written_T_1
regreset loginfo_cycles_35 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_70 = add(loginfo_cycles_35, UInt<1>(0h1))
node _loginfo_cycles_T_71 = tail(_loginfo_cycles_T_70, 1)
connect loginfo_cycles_35, _loginfo_cycles_T_71
node _T_5366 = asUInt(reset)
node _T_5367 = eq(_T_5366, UInt<1>(0h0))
when _T_5367 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_35) : printf_70
node _T_5368 = asUInt(reset)
node _T_5369 = eq(_T_5368, UInt<1>(0h0))
when _T_5369 :
printf(clock, UInt<1>(0h1), "[fhdr_memwriter] writefire: addr: 0x%x, data 0x%x, size %d\n", io.l2io.req.bits.addr, io.l2io.req.bits.data, io.l2io.req.bits.size) : printf_71
node _io_l2io_req_valid_T = and(enough_data, _T_5361)
node _io_l2io_req_valid_T_1 = and(_io_l2io_req_valid_T, dest_info_Q.io.deq.valid)
connect io.l2io.req.valid, _io_l2io_req_valid_T_1
node _io_l2io_req_bits_size_T = mux(write_ptr_override, UInt<2>(0h2), bytes_to_write_log2)
connect io.l2io.req.bits.size, _io_l2io_req_bits_size_T
node _io_l2io_req_bits_addr_T = mux(write_ptr_override, dest_info_Q.io.deq.bits.cmpflag, backend_next_write_addr)
connect io.l2io.req.bits.addr, _io_l2io_req_bits_addr_T
node _io_l2io_req_bits_data_T = mux(write_ptr_override, dest_info_Q.io.deq.bits.cmpval, remapped_write_data)
connect io.l2io.req.bits.data, _io_l2io_req_bits_data_T
connect io.l2io.req.bits.cmd, UInt<1>(0h1)
node _buf_lens_Q_io_deq_ready_T = and(io.l2io.req.ready, _T_5362)
node _buf_lens_Q_io_deq_ready_T_1 = and(_buf_lens_Q_io_deq_ready_T, dest_info_Q.io.deq.valid)
connect buf_lens_Q.io.deq.ready, _buf_lens_Q_io_deq_ready_T_1
node _dest_info_Q_io_deq_ready_T = and(io.l2io.req.ready, buf_lens_Q.io.deq.valid)
node _dest_info_Q_io_deq_ready_T_1 = and(_dest_info_Q_io_deq_ready_T, _T_5362)
connect dest_info_Q.io.deq.ready, _dest_info_Q_io_deq_ready_T_1
regreset bufs_completed : UInt<64>, clock, reset, UInt<64>(0h0)
connect io.bufs_completed, bufs_completed
connect io.l2io.resp.ready, UInt<1>(0h1)
connect io.no_writes_inflight, io.l2io.no_memops_inflight
node _T_5370 = and(io.l2io.req.ready, buf_lens_Q.io.deq.valid)
node _T_5371 = and(_T_5370, _T_5362)
node _T_5372 = and(_T_5371, dest_info_Q.io.deq.valid)
when _T_5372 :
node _bufs_completed_T = add(bufs_completed, UInt<1>(0h1))
node _bufs_completed_T_1 = tail(_bufs_completed_T, 1)
connect bufs_completed, _bufs_completed_T_1
connect backend_bytes_written, UInt<1>(0h0)
regreset loginfo_cycles_36 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_72 = add(loginfo_cycles_36, UInt<1>(0h1))
node _loginfo_cycles_T_73 = tail(_loginfo_cycles_T_72, 1)
connect loginfo_cycles_36, _loginfo_cycles_T_73
node _T_5373 = asUInt(reset)
node _T_5374 = eq(_T_5373, UInt<1>(0h0))
when _T_5374 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_36) : printf_72
node _T_5375 = asUInt(reset)
node _T_5376 = eq(_T_5375, UInt<1>(0h0))
when _T_5376 :
printf(clock, UInt<1>(0h1), "[fhdr_memwriter] write cmpflag addr: 0x%x, write ptr val 0x%x\n", dest_info_Q.io.deq.bits.cmpflag, dest_info_Q.io.deq.bits.cmpval) : printf_73
node _T_5377 = neq(count_valids, UInt<1>(0h0))
when _T_5377 :
regreset loginfo_cycles_37 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_74 = add(loginfo_cycles_37, UInt<1>(0h1))
node _loginfo_cycles_T_75 = tail(_loginfo_cycles_T_74, 1)
connect loginfo_cycles_37, _loginfo_cycles_T_75
node _T_5378 = asUInt(reset)
node _T_5379 = eq(_T_5378, UInt<1>(0h0))
when _T_5379 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_37) : printf_74
node _T_5380 = asUInt(reset)
node _T_5381 = eq(_T_5380, UInt<1>(0h0))
when _T_5381 :
printf(clock, UInt<1>(0h1), "[fhdr_memwriter] write_start_index %d, backend_bytes_written %d, count_valids %d, ptr_align_max_bytes_writeable %d, bytes_to_write %d, bytes_to_write_log2 %d\n", read_start_index, backend_bytes_written, count_valids, ptr_align_max_bytes_writeable, bytes_to_write, bytes_to_write_log2) : printf_75 | module ZstdCompressorMemWriter( // @[ZstdCompressorMemWriter.scala:23:7]
input clock, // @[ZstdCompressorMemWriter.scala:23:7]
input reset, // @[ZstdCompressorMemWriter.scala:23:7]
output io_memwrites_in_ready, // @[ZstdCompressorMemWriter.scala:26:14]
input io_memwrites_in_valid, // @[ZstdCompressorMemWriter.scala:26:14]
input [255:0] io_memwrites_in_bits_data, // @[ZstdCompressorMemWriter.scala:26:14]
input [5:0] io_memwrites_in_bits_validbytes, // @[ZstdCompressorMemWriter.scala:26:14]
input io_l2io_req_ready, // @[ZstdCompressorMemWriter.scala:26:14]
output io_l2io_req_valid, // @[ZstdCompressorMemWriter.scala:26:14]
output [63:0] io_l2io_req_bits_addr, // @[ZstdCompressorMemWriter.scala:26:14]
output [2:0] io_l2io_req_bits_size, // @[ZstdCompressorMemWriter.scala:26:14]
output [255:0] io_l2io_req_bits_data, // @[ZstdCompressorMemWriter.scala:26:14]
input io_l2io_resp_valid, // @[ZstdCompressorMemWriter.scala:26:14]
input [255:0] io_l2io_resp_bits_data, // @[ZstdCompressorMemWriter.scala:26:14]
input io_l2io_no_memops_inflight, // @[ZstdCompressorMemWriter.scala:26:14]
output io_dest_info_ready, // @[ZstdCompressorMemWriter.scala:26:14]
input io_dest_info_valid, // @[ZstdCompressorMemWriter.scala:26:14]
input [63:0] io_dest_info_bits_op // @[ZstdCompressorMemWriter.scala:26:14]
);
wire _Queue2_UInt8_31_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_31_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_31_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_30_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_30_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_30_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_29_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_29_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_29_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_28_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_28_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_28_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_27_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_27_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_27_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_26_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_26_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_26_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_25_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_25_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_25_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_24_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_24_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_24_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_23_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_23_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_23_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_22_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_22_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_22_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_21_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_21_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_21_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_20_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_20_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_20_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_19_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_19_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_19_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_18_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_18_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_18_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_17_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_17_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_17_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_16_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_16_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_16_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_15_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_15_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_15_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_14_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_14_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_14_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_13_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_13_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_13_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_12_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_12_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_12_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_11_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_11_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_11_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_10_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_10_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_10_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_9_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_9_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_9_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_8_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_8_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_7_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_7_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_7_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_6_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_6_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_6_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_5_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_5_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_5_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_4_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_4_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_4_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_3_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_3_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_3_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_2_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_2_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_2_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_1_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_1_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_1_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52]
wire _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52]
wire [7:0] _Queue2_UInt8_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52]
wire _buf_lens_Q_io_enq_ready; // @[ZstdCompressorMemWriter.scala:52:26]
wire _buf_lens_Q_io_deq_valid; // @[ZstdCompressorMemWriter.scala:52:26]
wire [63:0] _buf_lens_Q_io_deq_bits; // @[ZstdCompressorMemWriter.scala:52:26]
wire _dest_info_Q_io_deq_valid; // @[ZstdCompressorMemWriter.scala:39:27]
wire [63:0] _dest_info_Q_io_deq_bits_op; // @[ZstdCompressorMemWriter.scala:39:27]
wire [63:0] _dest_info_Q_io_deq_bits_cmpflag; // @[ZstdCompressorMemWriter.scala:39:27]
wire [63:0] _dest_info_Q_io_deq_bits_cmpval; // @[ZstdCompressorMemWriter.scala:39:27]
wire _incoming_writes_Q_io_deq_valid; // @[ZstdCompressorMemWriter.scala:35:33]
wire [255:0] _incoming_writes_Q_io_deq_bits_data; // @[ZstdCompressorMemWriter.scala:35:33]
wire [5:0] _incoming_writes_Q_io_deq_bits_validbytes; // @[ZstdCompressorMemWriter.scala:35:33]
wire _incoming_writes_Q_io_deq_bits_end_of_message; // @[ZstdCompressorMemWriter.scala:35:33]
wire io_memwrites_in_valid_0 = io_memwrites_in_valid; // @[ZstdCompressorMemWriter.scala:23:7]
wire [255:0] io_memwrites_in_bits_data_0 = io_memwrites_in_bits_data; // @[ZstdCompressorMemWriter.scala:23:7]
wire [5:0] io_memwrites_in_bits_validbytes_0 = io_memwrites_in_bits_validbytes; // @[ZstdCompressorMemWriter.scala:23:7]
wire io_l2io_req_ready_0 = io_l2io_req_ready; // @[ZstdCompressorMemWriter.scala:23:7]
wire io_l2io_resp_valid_0 = io_l2io_resp_valid; // @[ZstdCompressorMemWriter.scala:23:7]
wire [255:0] io_l2io_resp_bits_data_0 = io_l2io_resp_bits_data; // @[ZstdCompressorMemWriter.scala:23:7]
wire io_l2io_no_memops_inflight_0 = io_l2io_no_memops_inflight; // @[ZstdCompressorMemWriter.scala:23:7]
wire io_dest_info_valid_0 = io_dest_info_valid; // @[ZstdCompressorMemWriter.scala:23:7]
wire [63:0] io_dest_info_bits_op_0 = io_dest_info_bits_op; // @[ZstdCompressorMemWriter.scala:23:7]
wire io_memwrites_in_bits_end_of_message = 1'h1; // @[ZstdCompressorMemWriter.scala:23:7]
wire io_l2io_req_bits_cmd = 1'h1; // @[ZstdCompressorMemWriter.scala:23:7]
wire io_l2io_resp_ready = 1'h1; // @[ZstdCompressorMemWriter.scala:23:7]
wire [63:0] io_dest_info_bits_cmpflag = 64'h0; // @[ZstdCompressorMemWriter.scala:23:7]
wire [63:0] io_dest_info_bits_cmpval = 64'h0; // @[ZstdCompressorMemWriter.scala:23:7]
wire _throttle_end_writeable_log2_T_6 = 1'h0; // @[ZstdCompressorMemWriter.scala:187:50]
wire _count_valids_largest_aligned_log2_T_6 = 1'h0; // @[ZstdCompressorMemWriter.scala:218:56]
wire _io_l2io_req_valid_T_1; // @[Misc.scala:26:53]
wire [63:0] _io_l2io_req_bits_addr_T; // @[ZstdCompressorMemWriter.scala:283:31]
wire [2:0] _io_l2io_req_bits_size_T; // @[ZstdCompressorMemWriter.scala:282:31]
wire [255:0] _io_l2io_req_bits_data_T; // @[ZstdCompressorMemWriter.scala:284:31]
wire io_no_writes_inflight = io_l2io_no_memops_inflight_0; // @[ZstdCompressorMemWriter.scala:23:7]
wire io_memwrites_in_ready_0; // @[ZstdCompressorMemWriter.scala:23:7]
wire [63:0] io_l2io_req_bits_addr_0; // @[ZstdCompressorMemWriter.scala:23:7]
wire [2:0] io_l2io_req_bits_size_0; // @[ZstdCompressorMemWriter.scala:23:7]
wire [255:0] io_l2io_req_bits_data_0; // @[ZstdCompressorMemWriter.scala:23:7]
wire io_l2io_req_valid_0; // @[ZstdCompressorMemWriter.scala:23:7]
wire io_dest_info_ready_0; // @[ZstdCompressorMemWriter.scala:23:7]
wire [63:0] io_bufs_completed; // @[ZstdCompressorMemWriter.scala:23:7]
wire _dest_info_Q_io_deq_ready_T_1; // @[Misc.scala:26:53]
wire _decompress_dest_last_fire_T = _dest_info_Q_io_deq_ready_T_1 & _dest_info_Q_io_deq_valid; // @[Decoupled.scala:51:35]
reg decompress_dest_last_fire; // @[ZstdCompressorMemWriter.scala:42:42]
reg decompress_dest_last_valid; // @[ZstdCompressorMemWriter.scala:43:43]
wire _decompress_dest_printhelp_T = ~decompress_dest_last_valid; // @[ZstdCompressorMemWriter.scala:43:43, :44:94]
wire _decompress_dest_printhelp_T_1 = decompress_dest_last_fire | _decompress_dest_printhelp_T; // @[ZstdCompressorMemWriter.scala:42:42, :44:{90,94}]
wire decompress_dest_printhelp = _dest_info_Q_io_deq_valid & _decompress_dest_printhelp_T_1; // @[ZstdCompressorMemWriter.scala:39:27, :44:{60,90}]
reg [63:0] loginfo_cycles; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38]
reg [63:0] buf_len_tracker; // @[ZstdCompressorMemWriter.scala:57:32]
wire _incoming_writes_Q_io_deq_ready_T; // @[Misc.scala:26:53]
wire _T_10 = _incoming_writes_Q_io_deq_ready_T & _incoming_writes_Q_io_deq_valid; // @[Decoupled.scala:51:35]
wire [64:0] _GEN = {1'h0, buf_len_tracker} + {59'h0, _incoming_writes_Q_io_deq_bits_validbytes}; // @[ZstdCompressorMemWriter.scala:35:33, :57:32, :62:42]
wire [64:0] _buf_len_tracker_T; // @[ZstdCompressorMemWriter.scala:62:42]
assign _buf_len_tracker_T = _GEN; // @[ZstdCompressorMemWriter.scala:62:42]
wire [64:0] _buf_lens_Q_io_enq_bits_T; // @[ZstdCompressorMemWriter.scala:112:45]
assign _buf_lens_Q_io_enq_bits_T = _GEN; // @[ZstdCompressorMemWriter.scala:62:42, :112:45]
reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38]
reg [5:0] write_start_index; // @[ZstdCompressorMemWriter.scala:76:34]
wire [6:0] _idx_T = {1'h0, write_start_index}; // @[ZstdCompressorMemWriter.scala:76:34, :86:34]
wire [6:0] _GEN_0 = _idx_T % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx = _GEN_0[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_1 = _idx_T + 7'h1; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_1 = _idx_T_1 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_1 = _GEN_1[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_2 = _idx_T + 7'h2; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_2 = _idx_T_2 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_2 = _GEN_2[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_3 = _idx_T + 7'h3; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_3 = _idx_T_3 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_3 = _GEN_3[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_4 = _idx_T + 7'h4; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_4 = _idx_T_4 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_4 = _GEN_4[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_5 = _idx_T + 7'h5; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_5 = _idx_T_5 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_5 = _GEN_5[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_6 = _idx_T + 7'h6; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_6 = _idx_T_6 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_6 = _GEN_6[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_7 = _idx_T + 7'h7; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_7 = _idx_T_7 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_7 = _GEN_7[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_8 = _idx_T + 7'h8; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_8 = _idx_T_8 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_8 = _GEN_8[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_9 = _idx_T + 7'h9; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_9 = _idx_T_9 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_9 = _GEN_9[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_10 = _idx_T + 7'hA; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_10 = _idx_T_10 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_10 = _GEN_10[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_11 = _idx_T + 7'hB; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_11 = _idx_T_11 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_11 = _GEN_11[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_12 = _idx_T + 7'hC; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_12 = _idx_T_12 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_12 = _GEN_12[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_13 = _idx_T + 7'hD; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_13 = _idx_T_13 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_13 = _GEN_13[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_14 = _idx_T + 7'hE; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_14 = _idx_T_14 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_14 = _GEN_14[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_15 = _idx_T + 7'hF; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_15 = _idx_T_15 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_15 = _GEN_15[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_16 = _idx_T + 7'h10; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_16 = _idx_T_16 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_16 = _GEN_16[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_17 = _idx_T + 7'h11; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_17 = _idx_T_17 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_17 = _GEN_17[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_18 = _idx_T + 7'h12; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_18 = _idx_T_18 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_18 = _GEN_18[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_19 = _idx_T + 7'h13; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_19 = _idx_T_19 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_19 = _GEN_19[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_20 = _idx_T + 7'h14; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_20 = _idx_T_20 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_20 = _GEN_20[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_21 = _idx_T + 7'h15; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_21 = _idx_T_21 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_21 = _GEN_21[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_22 = _idx_T + 7'h16; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_22 = _idx_T_22 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_22 = _GEN_22[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_23 = _idx_T + 7'h17; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_23 = _idx_T_23 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_23 = _GEN_23[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_24 = _idx_T + 7'h18; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_24 = _idx_T_24 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_24 = _GEN_24[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_25 = _idx_T + 7'h19; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_25 = _idx_T_25 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_25 = _GEN_25[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_26 = _idx_T + 7'h1A; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_26 = _idx_T_26 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_26 = _GEN_26[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_27 = _idx_T + 7'h1B; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_27 = _idx_T_27 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_27 = _GEN_27[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_28 = _idx_T + 7'h1C; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_28 = _idx_T_28 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_28 = _GEN_28[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_29 = _idx_T + 7'h1D; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_29 = _idx_T_29 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_29 = _GEN_29[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_30 = _idx_T + 7'h1E; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_30 = _idx_T_30 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_30 = _GEN_30[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] _idx_T_31 = _idx_T + 7'h1F; // @[ZstdCompressorMemWriter.scala:86:34]
wire [6:0] _GEN_31 = _idx_T_31 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}]
wire [5:0] idx_31 = _GEN_31[5:0]; // @[ZstdCompressorMemWriter.scala:86:48]
wire [6:0] wrap_len_index_wide = _idx_T + {1'h0, _incoming_writes_Q_io_deq_bits_validbytes}; // @[ZstdCompressorMemWriter.scala:35:33, :86:34, :95:47]
wire [6:0] _GEN_32 = wrap_len_index_wide % 7'h20; // @[ZstdCompressorMemWriter.scala:95:47, :96:48]
wire [5:0] wrap_len_index_end = _GEN_32[5:0]; // @[ZstdCompressorMemWriter.scala:96:48]
wire wrapped = |(wrap_len_index_wide[6:5]); // @[ZstdCompressorMemWriter.scala:95:47, :97:37]
wire _all_queues_ready_T = _Queue2_UInt8_io_enq_ready & _Queue2_UInt8_1_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_1 = _all_queues_ready_T & _Queue2_UInt8_2_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_2 = _all_queues_ready_T_1 & _Queue2_UInt8_3_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_3 = _all_queues_ready_T_2 & _Queue2_UInt8_4_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_4 = _all_queues_ready_T_3 & _Queue2_UInt8_5_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_5 = _all_queues_ready_T_4 & _Queue2_UInt8_6_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_6 = _all_queues_ready_T_5 & _Queue2_UInt8_7_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_7 = _all_queues_ready_T_6 & _Queue2_UInt8_8_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_8 = _all_queues_ready_T_7 & _Queue2_UInt8_9_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_9 = _all_queues_ready_T_8 & _Queue2_UInt8_10_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_10 = _all_queues_ready_T_9 & _Queue2_UInt8_11_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_11 = _all_queues_ready_T_10 & _Queue2_UInt8_12_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_12 = _all_queues_ready_T_11 & _Queue2_UInt8_13_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_13 = _all_queues_ready_T_12 & _Queue2_UInt8_14_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_14 = _all_queues_ready_T_13 & _Queue2_UInt8_15_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_15 = _all_queues_ready_T_14 & _Queue2_UInt8_16_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_16 = _all_queues_ready_T_15 & _Queue2_UInt8_17_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_17 = _all_queues_ready_T_16 & _Queue2_UInt8_18_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_18 = _all_queues_ready_T_17 & _Queue2_UInt8_19_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_19 = _all_queues_ready_T_18 & _Queue2_UInt8_20_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_20 = _all_queues_ready_T_19 & _Queue2_UInt8_21_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_21 = _all_queues_ready_T_20 & _Queue2_UInt8_22_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_22 = _all_queues_ready_T_21 & _Queue2_UInt8_23_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_23 = _all_queues_ready_T_22 & _Queue2_UInt8_24_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_24 = _all_queues_ready_T_23 & _Queue2_UInt8_25_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_25 = _all_queues_ready_T_24 & _Queue2_UInt8_26_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_26 = _all_queues_ready_T_25 & _Queue2_UInt8_27_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_27 = _all_queues_ready_T_26 & _Queue2_UInt8_28_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_28 = _all_queues_ready_T_27 & _Queue2_UInt8_29_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _all_queues_ready_T_29 = _all_queues_ready_T_28 & _Queue2_UInt8_30_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire all_queues_ready = _all_queues_ready_T_29 & _Queue2_UInt8_31_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68]
wire _account_for_buf_lens_Q_T = ~_incoming_writes_Q_io_deq_bits_end_of_message; // @[ZstdCompressorMemWriter.scala:35:33, :103:33]
wire _account_for_buf_lens_Q_T_1 = _incoming_writes_Q_io_deq_bits_end_of_message & _buf_lens_Q_io_enq_ready; // @[ZstdCompressorMemWriter.scala:35:33, :52:26, :103:61]
wire account_for_buf_lens_Q = _account_for_buf_lens_Q_T | _account_for_buf_lens_Q_T_1; // @[ZstdCompressorMemWriter.scala:103:{33,46,61}]
wire _buf_lens_Q_io_enq_valid_T = _incoming_writes_Q_io_deq_valid & all_queues_ready; // @[Misc.scala:26:53]
wire _buf_lens_Q_io_enq_valid_T_1 = _buf_lens_Q_io_enq_valid_T & _incoming_writes_Q_io_deq_bits_end_of_message; // @[Misc.scala:26:53]
assign _incoming_writes_Q_io_deq_ready_T = all_queues_ready & account_for_buf_lens_Q; // @[Misc.scala:26:53]
wire _GEN_33 = write_start_index == 6'h0; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T = _GEN_33; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_3; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_3 = _GEN_33; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _use_this_queue_T_1 = |wrap_len_index_end; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_2 = _use_this_queue_T | _use_this_queue_T_1; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_4 = |wrap_len_index_end; // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77]
wire _use_this_queue_T_5 = _use_this_queue_T_3 & _use_this_queue_T_4; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue = wrapped ? _use_this_queue_T_2 : _use_this_queue_T_5; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_34 = write_start_index < 6'h2; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_6; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_6 = _GEN_34; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_9; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_9 = _GEN_34; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _use_this_queue_T_7 = |(wrap_len_index_end[5:1]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_8 = _use_this_queue_T_6 | _use_this_queue_T_7; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_10 = |(wrap_len_index_end[5:1]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77]
wire _use_this_queue_T_11 = _use_this_queue_T_9 & _use_this_queue_T_10; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_1 = wrapped ? _use_this_queue_T_8 : _use_this_queue_T_11; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_35 = write_start_index < 6'h3; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_12; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_12 = _GEN_35; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_15; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_15 = _GEN_35; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _GEN_36 = wrap_len_index_end > 6'h2; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_13; // @[ZstdCompressorMemWriter.scala:124:77]
assign _use_this_queue_T_13 = _GEN_36; // @[ZstdCompressorMemWriter.scala:124:77]
wire _use_this_queue_T_16; // @[ZstdCompressorMemWriter.scala:125:77]
assign _use_this_queue_T_16 = _GEN_36; // @[ZstdCompressorMemWriter.scala:124:77, :125:77]
wire _use_this_queue_T_14 = _use_this_queue_T_12 | _use_this_queue_T_13; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_17 = _use_this_queue_T_15 & _use_this_queue_T_16; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_2 = wrapped ? _use_this_queue_T_14 : _use_this_queue_T_17; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_37 = write_start_index < 6'h4; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_18; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_18 = _GEN_37; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_21; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_21 = _GEN_37; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _use_this_queue_T_19 = |(wrap_len_index_end[5:2]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_20 = _use_this_queue_T_18 | _use_this_queue_T_19; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_22 = |(wrap_len_index_end[5:2]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77]
wire _use_this_queue_T_23 = _use_this_queue_T_21 & _use_this_queue_T_22; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_3 = wrapped ? _use_this_queue_T_20 : _use_this_queue_T_23; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_38 = write_start_index < 6'h5; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_24; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_24 = _GEN_38; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_27; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_27 = _GEN_38; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _GEN_39 = wrap_len_index_end > 6'h4; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_25; // @[ZstdCompressorMemWriter.scala:124:77]
assign _use_this_queue_T_25 = _GEN_39; // @[ZstdCompressorMemWriter.scala:124:77]
wire _use_this_queue_T_28; // @[ZstdCompressorMemWriter.scala:125:77]
assign _use_this_queue_T_28 = _GEN_39; // @[ZstdCompressorMemWriter.scala:124:77, :125:77]
wire _use_this_queue_T_26 = _use_this_queue_T_24 | _use_this_queue_T_25; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_29 = _use_this_queue_T_27 & _use_this_queue_T_28; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_4 = wrapped ? _use_this_queue_T_26 : _use_this_queue_T_29; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_40 = write_start_index < 6'h6; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_30; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_30 = _GEN_40; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_33; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_33 = _GEN_40; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _GEN_41 = wrap_len_index_end > 6'h5; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_31; // @[ZstdCompressorMemWriter.scala:124:77]
assign _use_this_queue_T_31 = _GEN_41; // @[ZstdCompressorMemWriter.scala:124:77]
wire _use_this_queue_T_34; // @[ZstdCompressorMemWriter.scala:125:77]
assign _use_this_queue_T_34 = _GEN_41; // @[ZstdCompressorMemWriter.scala:124:77, :125:77]
wire _use_this_queue_T_32 = _use_this_queue_T_30 | _use_this_queue_T_31; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_35 = _use_this_queue_T_33 & _use_this_queue_T_34; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_5 = wrapped ? _use_this_queue_T_32 : _use_this_queue_T_35; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_42 = write_start_index < 6'h7; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_36; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_36 = _GEN_42; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_39; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_39 = _GEN_42; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _GEN_43 = wrap_len_index_end > 6'h6; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_37; // @[ZstdCompressorMemWriter.scala:124:77]
assign _use_this_queue_T_37 = _GEN_43; // @[ZstdCompressorMemWriter.scala:124:77]
wire _use_this_queue_T_40; // @[ZstdCompressorMemWriter.scala:125:77]
assign _use_this_queue_T_40 = _GEN_43; // @[ZstdCompressorMemWriter.scala:124:77, :125:77]
wire _use_this_queue_T_38 = _use_this_queue_T_36 | _use_this_queue_T_37; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_41 = _use_this_queue_T_39 & _use_this_queue_T_40; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_6 = wrapped ? _use_this_queue_T_38 : _use_this_queue_T_41; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_44 = write_start_index < 6'h8; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_42; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_42 = _GEN_44; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_45; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_45 = _GEN_44; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _use_this_queue_T_43 = |(wrap_len_index_end[5:3]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_44 = _use_this_queue_T_42 | _use_this_queue_T_43; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_46 = |(wrap_len_index_end[5:3]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77]
wire _use_this_queue_T_47 = _use_this_queue_T_45 & _use_this_queue_T_46; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_7 = wrapped ? _use_this_queue_T_44 : _use_this_queue_T_47; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_45 = write_start_index < 6'h9; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_48; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_48 = _GEN_45; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_51; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_51 = _GEN_45; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _GEN_46 = wrap_len_index_end > 6'h8; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_49; // @[ZstdCompressorMemWriter.scala:124:77]
assign _use_this_queue_T_49 = _GEN_46; // @[ZstdCompressorMemWriter.scala:124:77]
wire _use_this_queue_T_52; // @[ZstdCompressorMemWriter.scala:125:77]
assign _use_this_queue_T_52 = _GEN_46; // @[ZstdCompressorMemWriter.scala:124:77, :125:77]
wire _use_this_queue_T_50 = _use_this_queue_T_48 | _use_this_queue_T_49; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_53 = _use_this_queue_T_51 & _use_this_queue_T_52; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_8 = wrapped ? _use_this_queue_T_50 : _use_this_queue_T_53; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_47 = write_start_index < 6'hA; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_54; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_54 = _GEN_47; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_57; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_57 = _GEN_47; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _GEN_48 = wrap_len_index_end > 6'h9; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_55; // @[ZstdCompressorMemWriter.scala:124:77]
assign _use_this_queue_T_55 = _GEN_48; // @[ZstdCompressorMemWriter.scala:124:77]
wire _use_this_queue_T_58; // @[ZstdCompressorMemWriter.scala:125:77]
assign _use_this_queue_T_58 = _GEN_48; // @[ZstdCompressorMemWriter.scala:124:77, :125:77]
wire _use_this_queue_T_56 = _use_this_queue_T_54 | _use_this_queue_T_55; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_59 = _use_this_queue_T_57 & _use_this_queue_T_58; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_9 = wrapped ? _use_this_queue_T_56 : _use_this_queue_T_59; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_49 = write_start_index < 6'hB; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_60; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_60 = _GEN_49; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_63; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_63 = _GEN_49; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _GEN_50 = wrap_len_index_end > 6'hA; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_61; // @[ZstdCompressorMemWriter.scala:124:77]
assign _use_this_queue_T_61 = _GEN_50; // @[ZstdCompressorMemWriter.scala:124:77]
wire _use_this_queue_T_64; // @[ZstdCompressorMemWriter.scala:125:77]
assign _use_this_queue_T_64 = _GEN_50; // @[ZstdCompressorMemWriter.scala:124:77, :125:77]
wire _use_this_queue_T_62 = _use_this_queue_T_60 | _use_this_queue_T_61; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_65 = _use_this_queue_T_63 & _use_this_queue_T_64; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_10 = wrapped ? _use_this_queue_T_62 : _use_this_queue_T_65; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_51 = write_start_index < 6'hC; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_66; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_66 = _GEN_51; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_69; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_69 = _GEN_51; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _GEN_52 = wrap_len_index_end > 6'hB; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_67; // @[ZstdCompressorMemWriter.scala:124:77]
assign _use_this_queue_T_67 = _GEN_52; // @[ZstdCompressorMemWriter.scala:124:77]
wire _use_this_queue_T_70; // @[ZstdCompressorMemWriter.scala:125:77]
assign _use_this_queue_T_70 = _GEN_52; // @[ZstdCompressorMemWriter.scala:124:77, :125:77]
wire _use_this_queue_T_68 = _use_this_queue_T_66 | _use_this_queue_T_67; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_71 = _use_this_queue_T_69 & _use_this_queue_T_70; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_11 = wrapped ? _use_this_queue_T_68 : _use_this_queue_T_71; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_53 = write_start_index < 6'hD; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_72; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_72 = _GEN_53; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_75; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_75 = _GEN_53; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _GEN_54 = wrap_len_index_end > 6'hC; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_73; // @[ZstdCompressorMemWriter.scala:124:77]
assign _use_this_queue_T_73 = _GEN_54; // @[ZstdCompressorMemWriter.scala:124:77]
wire _use_this_queue_T_76; // @[ZstdCompressorMemWriter.scala:125:77]
assign _use_this_queue_T_76 = _GEN_54; // @[ZstdCompressorMemWriter.scala:124:77, :125:77]
wire _use_this_queue_T_74 = _use_this_queue_T_72 | _use_this_queue_T_73; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_77 = _use_this_queue_T_75 & _use_this_queue_T_76; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_12 = wrapped ? _use_this_queue_T_74 : _use_this_queue_T_77; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_55 = write_start_index < 6'hE; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_78; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_78 = _GEN_55; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_81; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_81 = _GEN_55; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _GEN_56 = wrap_len_index_end > 6'hD; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_79; // @[ZstdCompressorMemWriter.scala:124:77]
assign _use_this_queue_T_79 = _GEN_56; // @[ZstdCompressorMemWriter.scala:124:77]
wire _use_this_queue_T_82; // @[ZstdCompressorMemWriter.scala:125:77]
assign _use_this_queue_T_82 = _GEN_56; // @[ZstdCompressorMemWriter.scala:124:77, :125:77]
wire _use_this_queue_T_80 = _use_this_queue_T_78 | _use_this_queue_T_79; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_83 = _use_this_queue_T_81 & _use_this_queue_T_82; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_13 = wrapped ? _use_this_queue_T_80 : _use_this_queue_T_83; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_57 = write_start_index < 6'hF; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_84; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_84 = _GEN_57; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_87; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_87 = _GEN_57; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _GEN_58 = wrap_len_index_end > 6'hE; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_85; // @[ZstdCompressorMemWriter.scala:124:77]
assign _use_this_queue_T_85 = _GEN_58; // @[ZstdCompressorMemWriter.scala:124:77]
wire _use_this_queue_T_88; // @[ZstdCompressorMemWriter.scala:125:77]
assign _use_this_queue_T_88 = _GEN_58; // @[ZstdCompressorMemWriter.scala:124:77, :125:77]
wire _use_this_queue_T_86 = _use_this_queue_T_84 | _use_this_queue_T_85; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_89 = _use_this_queue_T_87 & _use_this_queue_T_88; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_14 = wrapped ? _use_this_queue_T_86 : _use_this_queue_T_89; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_59 = write_start_index < 6'h10; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_90; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_90 = _GEN_59; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_93; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_93 = _GEN_59; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _use_this_queue_T_91 = |(wrap_len_index_end[5:4]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_92 = _use_this_queue_T_90 | _use_this_queue_T_91; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_94 = |(wrap_len_index_end[5:4]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77]
wire _use_this_queue_T_95 = _use_this_queue_T_93 & _use_this_queue_T_94; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_15 = wrapped ? _use_this_queue_T_92 : _use_this_queue_T_95; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_60 = write_start_index < 6'h11; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_96; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_96 = _GEN_60; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_99; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_99 = _GEN_60; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _GEN_61 = wrap_len_index_end > 6'h10; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_97; // @[ZstdCompressorMemWriter.scala:124:77]
assign _use_this_queue_T_97 = _GEN_61; // @[ZstdCompressorMemWriter.scala:124:77]
wire _use_this_queue_T_100; // @[ZstdCompressorMemWriter.scala:125:77]
assign _use_this_queue_T_100 = _GEN_61; // @[ZstdCompressorMemWriter.scala:124:77, :125:77]
wire _use_this_queue_T_98 = _use_this_queue_T_96 | _use_this_queue_T_97; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_101 = _use_this_queue_T_99 & _use_this_queue_T_100; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_16 = wrapped ? _use_this_queue_T_98 : _use_this_queue_T_101; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_62 = write_start_index < 6'h12; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_102; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_102 = _GEN_62; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_105; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_105 = _GEN_62; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _GEN_63 = wrap_len_index_end > 6'h11; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_103; // @[ZstdCompressorMemWriter.scala:124:77]
assign _use_this_queue_T_103 = _GEN_63; // @[ZstdCompressorMemWriter.scala:124:77]
wire _use_this_queue_T_106; // @[ZstdCompressorMemWriter.scala:125:77]
assign _use_this_queue_T_106 = _GEN_63; // @[ZstdCompressorMemWriter.scala:124:77, :125:77]
wire _use_this_queue_T_104 = _use_this_queue_T_102 | _use_this_queue_T_103; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_107 = _use_this_queue_T_105 & _use_this_queue_T_106; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_17 = wrapped ? _use_this_queue_T_104 : _use_this_queue_T_107; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_64 = write_start_index < 6'h13; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_108; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_108 = _GEN_64; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_111; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_111 = _GEN_64; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _GEN_65 = wrap_len_index_end > 6'h12; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_109; // @[ZstdCompressorMemWriter.scala:124:77]
assign _use_this_queue_T_109 = _GEN_65; // @[ZstdCompressorMemWriter.scala:124:77]
wire _use_this_queue_T_112; // @[ZstdCompressorMemWriter.scala:125:77]
assign _use_this_queue_T_112 = _GEN_65; // @[ZstdCompressorMemWriter.scala:124:77, :125:77]
wire _use_this_queue_T_110 = _use_this_queue_T_108 | _use_this_queue_T_109; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_113 = _use_this_queue_T_111 & _use_this_queue_T_112; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_18 = wrapped ? _use_this_queue_T_110 : _use_this_queue_T_113; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_66 = write_start_index < 6'h14; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_114; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_114 = _GEN_66; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_117; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_117 = _GEN_66; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _GEN_67 = wrap_len_index_end > 6'h13; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_115; // @[ZstdCompressorMemWriter.scala:124:77]
assign _use_this_queue_T_115 = _GEN_67; // @[ZstdCompressorMemWriter.scala:124:77]
wire _use_this_queue_T_118; // @[ZstdCompressorMemWriter.scala:125:77]
assign _use_this_queue_T_118 = _GEN_67; // @[ZstdCompressorMemWriter.scala:124:77, :125:77]
wire _use_this_queue_T_116 = _use_this_queue_T_114 | _use_this_queue_T_115; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_119 = _use_this_queue_T_117 & _use_this_queue_T_118; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_19 = wrapped ? _use_this_queue_T_116 : _use_this_queue_T_119; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_68 = write_start_index < 6'h15; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_120; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_120 = _GEN_68; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_123; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_123 = _GEN_68; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _GEN_69 = wrap_len_index_end > 6'h14; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_121; // @[ZstdCompressorMemWriter.scala:124:77]
assign _use_this_queue_T_121 = _GEN_69; // @[ZstdCompressorMemWriter.scala:124:77]
wire _use_this_queue_T_124; // @[ZstdCompressorMemWriter.scala:125:77]
assign _use_this_queue_T_124 = _GEN_69; // @[ZstdCompressorMemWriter.scala:124:77, :125:77]
wire _use_this_queue_T_122 = _use_this_queue_T_120 | _use_this_queue_T_121; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_125 = _use_this_queue_T_123 & _use_this_queue_T_124; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_20 = wrapped ? _use_this_queue_T_122 : _use_this_queue_T_125; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_70 = write_start_index < 6'h16; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_126; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_126 = _GEN_70; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_129; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_129 = _GEN_70; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _GEN_71 = wrap_len_index_end > 6'h15; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_127; // @[ZstdCompressorMemWriter.scala:124:77]
assign _use_this_queue_T_127 = _GEN_71; // @[ZstdCompressorMemWriter.scala:124:77]
wire _use_this_queue_T_130; // @[ZstdCompressorMemWriter.scala:125:77]
assign _use_this_queue_T_130 = _GEN_71; // @[ZstdCompressorMemWriter.scala:124:77, :125:77]
wire _use_this_queue_T_128 = _use_this_queue_T_126 | _use_this_queue_T_127; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_131 = _use_this_queue_T_129 & _use_this_queue_T_130; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_21 = wrapped ? _use_this_queue_T_128 : _use_this_queue_T_131; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_72 = write_start_index < 6'h17; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_132; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_132 = _GEN_72; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_135; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_135 = _GEN_72; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _GEN_73 = wrap_len_index_end > 6'h16; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_133; // @[ZstdCompressorMemWriter.scala:124:77]
assign _use_this_queue_T_133 = _GEN_73; // @[ZstdCompressorMemWriter.scala:124:77]
wire _use_this_queue_T_136; // @[ZstdCompressorMemWriter.scala:125:77]
assign _use_this_queue_T_136 = _GEN_73; // @[ZstdCompressorMemWriter.scala:124:77, :125:77]
wire _use_this_queue_T_134 = _use_this_queue_T_132 | _use_this_queue_T_133; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_137 = _use_this_queue_T_135 & _use_this_queue_T_136; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_22 = wrapped ? _use_this_queue_T_134 : _use_this_queue_T_137; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_74 = write_start_index < 6'h18; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_138; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_138 = _GEN_74; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_141; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_141 = _GEN_74; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _GEN_75 = wrap_len_index_end > 6'h17; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_139; // @[ZstdCompressorMemWriter.scala:124:77]
assign _use_this_queue_T_139 = _GEN_75; // @[ZstdCompressorMemWriter.scala:124:77]
wire _use_this_queue_T_142; // @[ZstdCompressorMemWriter.scala:125:77]
assign _use_this_queue_T_142 = _GEN_75; // @[ZstdCompressorMemWriter.scala:124:77, :125:77]
wire _use_this_queue_T_140 = _use_this_queue_T_138 | _use_this_queue_T_139; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_143 = _use_this_queue_T_141 & _use_this_queue_T_142; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_23 = wrapped ? _use_this_queue_T_140 : _use_this_queue_T_143; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_76 = write_start_index < 6'h19; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_144; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_144 = _GEN_76; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_147; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_147 = _GEN_76; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _GEN_77 = wrap_len_index_end > 6'h18; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_145; // @[ZstdCompressorMemWriter.scala:124:77]
assign _use_this_queue_T_145 = _GEN_77; // @[ZstdCompressorMemWriter.scala:124:77]
wire _use_this_queue_T_148; // @[ZstdCompressorMemWriter.scala:125:77]
assign _use_this_queue_T_148 = _GEN_77; // @[ZstdCompressorMemWriter.scala:124:77, :125:77]
wire _use_this_queue_T_146 = _use_this_queue_T_144 | _use_this_queue_T_145; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_149 = _use_this_queue_T_147 & _use_this_queue_T_148; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_24 = wrapped ? _use_this_queue_T_146 : _use_this_queue_T_149; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_78 = write_start_index < 6'h1A; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_150; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_150 = _GEN_78; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_153; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_153 = _GEN_78; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _GEN_79 = wrap_len_index_end > 6'h19; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_151; // @[ZstdCompressorMemWriter.scala:124:77]
assign _use_this_queue_T_151 = _GEN_79; // @[ZstdCompressorMemWriter.scala:124:77]
wire _use_this_queue_T_154; // @[ZstdCompressorMemWriter.scala:125:77]
assign _use_this_queue_T_154 = _GEN_79; // @[ZstdCompressorMemWriter.scala:124:77, :125:77]
wire _use_this_queue_T_152 = _use_this_queue_T_150 | _use_this_queue_T_151; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_155 = _use_this_queue_T_153 & _use_this_queue_T_154; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_25 = wrapped ? _use_this_queue_T_152 : _use_this_queue_T_155; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_80 = write_start_index < 6'h1B; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_156; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_156 = _GEN_80; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_159; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_159 = _GEN_80; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _GEN_81 = wrap_len_index_end > 6'h1A; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_157; // @[ZstdCompressorMemWriter.scala:124:77]
assign _use_this_queue_T_157 = _GEN_81; // @[ZstdCompressorMemWriter.scala:124:77]
wire _use_this_queue_T_160; // @[ZstdCompressorMemWriter.scala:125:77]
assign _use_this_queue_T_160 = _GEN_81; // @[ZstdCompressorMemWriter.scala:124:77, :125:77]
wire _use_this_queue_T_158 = _use_this_queue_T_156 | _use_this_queue_T_157; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_161 = _use_this_queue_T_159 & _use_this_queue_T_160; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_26 = wrapped ? _use_this_queue_T_158 : _use_this_queue_T_161; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_82 = write_start_index < 6'h1C; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_162; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_162 = _GEN_82; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_165; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_165 = _GEN_82; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _GEN_83 = wrap_len_index_end > 6'h1B; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_163; // @[ZstdCompressorMemWriter.scala:124:77]
assign _use_this_queue_T_163 = _GEN_83; // @[ZstdCompressorMemWriter.scala:124:77]
wire _use_this_queue_T_166; // @[ZstdCompressorMemWriter.scala:125:77]
assign _use_this_queue_T_166 = _GEN_83; // @[ZstdCompressorMemWriter.scala:124:77, :125:77]
wire _use_this_queue_T_164 = _use_this_queue_T_162 | _use_this_queue_T_163; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_167 = _use_this_queue_T_165 & _use_this_queue_T_166; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_27 = wrapped ? _use_this_queue_T_164 : _use_this_queue_T_167; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_84 = write_start_index < 6'h1D; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_168; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_168 = _GEN_84; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_171; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_171 = _GEN_84; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _GEN_85 = wrap_len_index_end > 6'h1C; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_169; // @[ZstdCompressorMemWriter.scala:124:77]
assign _use_this_queue_T_169 = _GEN_85; // @[ZstdCompressorMemWriter.scala:124:77]
wire _use_this_queue_T_172; // @[ZstdCompressorMemWriter.scala:125:77]
assign _use_this_queue_T_172 = _GEN_85; // @[ZstdCompressorMemWriter.scala:124:77, :125:77]
wire _use_this_queue_T_170 = _use_this_queue_T_168 | _use_this_queue_T_169; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_173 = _use_this_queue_T_171 & _use_this_queue_T_172; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_28 = wrapped ? _use_this_queue_T_170 : _use_this_queue_T_173; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_86 = write_start_index < 6'h1E; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_174; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_174 = _GEN_86; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_177; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_177 = _GEN_86; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _GEN_87 = wrap_len_index_end > 6'h1D; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_175; // @[ZstdCompressorMemWriter.scala:124:77]
assign _use_this_queue_T_175 = _GEN_87; // @[ZstdCompressorMemWriter.scala:124:77]
wire _use_this_queue_T_178; // @[ZstdCompressorMemWriter.scala:125:77]
assign _use_this_queue_T_178 = _GEN_87; // @[ZstdCompressorMemWriter.scala:124:77, :125:77]
wire _use_this_queue_T_176 = _use_this_queue_T_174 | _use_this_queue_T_175; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_179 = _use_this_queue_T_177 & _use_this_queue_T_178; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_29 = wrapped ? _use_this_queue_T_176 : _use_this_queue_T_179; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _GEN_88 = write_start_index < 6'h1F; // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_180; // @[ZstdCompressorMemWriter.scala:124:41]
assign _use_this_queue_T_180 = _GEN_88; // @[ZstdCompressorMemWriter.scala:124:41]
wire _use_this_queue_T_183; // @[ZstdCompressorMemWriter.scala:125:41]
assign _use_this_queue_T_183 = _GEN_88; // @[ZstdCompressorMemWriter.scala:124:41, :125:41]
wire _GEN_89 = wrap_len_index_end > 6'h1E; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_181; // @[ZstdCompressorMemWriter.scala:124:77]
assign _use_this_queue_T_181 = _GEN_89; // @[ZstdCompressorMemWriter.scala:124:77]
wire _use_this_queue_T_184; // @[ZstdCompressorMemWriter.scala:125:77]
assign _use_this_queue_T_184 = _GEN_89; // @[ZstdCompressorMemWriter.scala:124:77, :125:77]
wire _use_this_queue_T_182 = _use_this_queue_T_180 | _use_this_queue_T_181; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_185 = _use_this_queue_T_183 & _use_this_queue_T_184; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_30 = wrapped ? _use_this_queue_T_182 : _use_this_queue_T_185; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
wire _use_this_queue_T_186 = ~(write_start_index[5]); // @[ZstdCompressorMemWriter.scala:76:34, :124:41]
wire _use_this_queue_T_187 = wrap_len_index_end[5]; // @[ZstdCompressorMemWriter.scala:96:48, :124:77]
wire _use_this_queue_T_190 = wrap_len_index_end[5]; // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77]
wire _use_this_queue_T_188 = _use_this_queue_T_186 | _use_this_queue_T_187; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}]
wire _use_this_queue_T_189 = ~(write_start_index[5]); // @[ZstdCompressorMemWriter.scala:76:34, :124:41, :125:41]
wire _use_this_queue_T_191 = _use_this_queue_T_189 & _use_this_queue_T_190; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}]
wire use_this_queue_31 = wrapped ? _use_this_queue_T_188 : _use_this_queue_T_191; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63]
reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38]
reg [5:0] read_start_index; // @[ZstdCompressorMemWriter.scala:139:33]
wire [7:0] remapVecData_0; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_1; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_2; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_3; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_4; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_5; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_6; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_7; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_8; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_9; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_10; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_11; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_12; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_13; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_14; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_15; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_16; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_17; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_18; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_19; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_20; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_21; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_22; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_23; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_24; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_25; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_26; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_27; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_28; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_29; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_30; // @[ZstdCompressorMemWriter.scala:141:26]
wire [7:0] remapVecData_31; // @[ZstdCompressorMemWriter.scala:141:26]
wire remapVecValids_0; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_1; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_2; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_3; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_4; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_5; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_6; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_7; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_8; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_9; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_10; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_11; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_12; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_13; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_14; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_15; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_16; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_17; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_18; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_19; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_20; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_21; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_22; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_23; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_24; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_25; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_26; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_27; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_28; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_29; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_30; // @[ZstdCompressorMemWriter.scala:142:28]
wire remapVecValids_31; // @[ZstdCompressorMemWriter.scala:142:28]
wire _remapVecReadys_0_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_1_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_2_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_3_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_4_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_5_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_6_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_7_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_8_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_9_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_10_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_11_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_12_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_13_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_14_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_15_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_16_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_17_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_18_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_19_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_20_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_21_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_22_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_23_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_24_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_25_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_26_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_27_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_28_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_29_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_30_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire _remapVecReadys_31_T_4; // @[ZstdCompressorMemWriter.scala:264:61]
wire remapVecReadys_0; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_1; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_2; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_3; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_4; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_5; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_6; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_7; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_8; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_9; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_10; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_11; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_12; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_13; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_14; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_15; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_16; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_17; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_18; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_19; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_20; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_21; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_22; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_23; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_24; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_25; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_26; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_27; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_28; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_29; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_30; // @[ZstdCompressorMemWriter.scala:143:28]
wire remapVecReadys_31; // @[ZstdCompressorMemWriter.scala:143:28]
wire [6:0] _remapindex_T = {1'h0, read_start_index}; // @[ZstdCompressorMemWriter.scala:139:33, :153:33]
wire [6:0] _GEN_90 = _remapindex_T % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex = _GEN_90[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_4337 = remapindex == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4338 = remapindex == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4339 = remapindex == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4340 = remapindex == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4341 = remapindex == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4342 = remapindex == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4343 = remapindex == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4344 = remapindex == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4345 = remapindex == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4346 = remapindex == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4347 = remapindex == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4348 = remapindex == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4349 = remapindex == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4350 = remapindex == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4351 = remapindex == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4352 = remapindex == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4353 = remapindex == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4354 = remapindex == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4355 = remapindex == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4356 = remapindex == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4357 = remapindex == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4358 = remapindex == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4359 = remapindex == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4360 = remapindex == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4361 = remapindex == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4362 = remapindex == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4363 = remapindex == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4364 = remapindex == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4365 = remapindex == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4366 = remapindex == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4367 = remapindex == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4368 = remapindex == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_0 = _T_4368 ? _Queue2_UInt8_31_io_deq_bits : _T_4367 ? _Queue2_UInt8_30_io_deq_bits : _T_4366 ? _Queue2_UInt8_29_io_deq_bits : _T_4365 ? _Queue2_UInt8_28_io_deq_bits : _T_4364 ? _Queue2_UInt8_27_io_deq_bits : _T_4363 ? _Queue2_UInt8_26_io_deq_bits : _T_4362 ? _Queue2_UInt8_25_io_deq_bits : _T_4361 ? _Queue2_UInt8_24_io_deq_bits : _T_4360 ? _Queue2_UInt8_23_io_deq_bits : _T_4359 ? _Queue2_UInt8_22_io_deq_bits : _T_4358 ? _Queue2_UInt8_21_io_deq_bits : _T_4357 ? _Queue2_UInt8_20_io_deq_bits : _T_4356 ? _Queue2_UInt8_19_io_deq_bits : _T_4355 ? _Queue2_UInt8_18_io_deq_bits : _T_4354 ? _Queue2_UInt8_17_io_deq_bits : _T_4353 ? _Queue2_UInt8_16_io_deq_bits : _T_4352 ? _Queue2_UInt8_15_io_deq_bits : _T_4351 ? _Queue2_UInt8_14_io_deq_bits : _T_4350 ? _Queue2_UInt8_13_io_deq_bits : _T_4349 ? _Queue2_UInt8_12_io_deq_bits : _T_4348 ? _Queue2_UInt8_11_io_deq_bits : _T_4347 ? _Queue2_UInt8_10_io_deq_bits : _T_4346 ? _Queue2_UInt8_9_io_deq_bits : _T_4345 ? _Queue2_UInt8_8_io_deq_bits : _T_4344 ? _Queue2_UInt8_7_io_deq_bits : _T_4343 ? _Queue2_UInt8_6_io_deq_bits : _T_4342 ? _Queue2_UInt8_5_io_deq_bits : _T_4341 ? _Queue2_UInt8_4_io_deq_bits : _T_4340 ? _Queue2_UInt8_3_io_deq_bits : _T_4339 ? _Queue2_UInt8_2_io_deq_bits : _T_4338 ? _Queue2_UInt8_1_io_deq_bits : _T_4337 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_0 = _T_4368 ? _Queue2_UInt8_31_io_deq_valid : _T_4367 ? _Queue2_UInt8_30_io_deq_valid : _T_4366 ? _Queue2_UInt8_29_io_deq_valid : _T_4365 ? _Queue2_UInt8_28_io_deq_valid : _T_4364 ? _Queue2_UInt8_27_io_deq_valid : _T_4363 ? _Queue2_UInt8_26_io_deq_valid : _T_4362 ? _Queue2_UInt8_25_io_deq_valid : _T_4361 ? _Queue2_UInt8_24_io_deq_valid : _T_4360 ? _Queue2_UInt8_23_io_deq_valid : _T_4359 ? _Queue2_UInt8_22_io_deq_valid : _T_4358 ? _Queue2_UInt8_21_io_deq_valid : _T_4357 ? _Queue2_UInt8_20_io_deq_valid : _T_4356 ? _Queue2_UInt8_19_io_deq_valid : _T_4355 ? _Queue2_UInt8_18_io_deq_valid : _T_4354 ? _Queue2_UInt8_17_io_deq_valid : _T_4353 ? _Queue2_UInt8_16_io_deq_valid : _T_4352 ? _Queue2_UInt8_15_io_deq_valid : _T_4351 ? _Queue2_UInt8_14_io_deq_valid : _T_4350 ? _Queue2_UInt8_13_io_deq_valid : _T_4349 ? _Queue2_UInt8_12_io_deq_valid : _T_4348 ? _Queue2_UInt8_11_io_deq_valid : _T_4347 ? _Queue2_UInt8_10_io_deq_valid : _T_4346 ? _Queue2_UInt8_9_io_deq_valid : _T_4345 ? _Queue2_UInt8_8_io_deq_valid : _T_4344 ? _Queue2_UInt8_7_io_deq_valid : _T_4343 ? _Queue2_UInt8_6_io_deq_valid : _T_4342 ? _Queue2_UInt8_5_io_deq_valid : _T_4341 ? _Queue2_UInt8_4_io_deq_valid : _T_4340 ? _Queue2_UInt8_3_io_deq_valid : _T_4339 ? _Queue2_UInt8_2_io_deq_valid : _T_4338 ? _Queue2_UInt8_1_io_deq_valid : _T_4337 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_1 = _remapindex_T + 7'h1; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_91 = _remapindex_T_1 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_1 = _GEN_91[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_4369 = remapindex_1 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4370 = remapindex_1 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4371 = remapindex_1 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4372 = remapindex_1 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4373 = remapindex_1 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4374 = remapindex_1 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4375 = remapindex_1 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4376 = remapindex_1 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4377 = remapindex_1 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4378 = remapindex_1 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4379 = remapindex_1 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4380 = remapindex_1 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4381 = remapindex_1 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4382 = remapindex_1 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4383 = remapindex_1 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4384 = remapindex_1 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4385 = remapindex_1 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4386 = remapindex_1 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4387 = remapindex_1 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4388 = remapindex_1 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4389 = remapindex_1 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4390 = remapindex_1 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4391 = remapindex_1 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4392 = remapindex_1 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4393 = remapindex_1 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4394 = remapindex_1 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4395 = remapindex_1 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4396 = remapindex_1 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4397 = remapindex_1 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4398 = remapindex_1 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4399 = remapindex_1 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4400 = remapindex_1 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_1 = _T_4400 ? _Queue2_UInt8_31_io_deq_bits : _T_4399 ? _Queue2_UInt8_30_io_deq_bits : _T_4398 ? _Queue2_UInt8_29_io_deq_bits : _T_4397 ? _Queue2_UInt8_28_io_deq_bits : _T_4396 ? _Queue2_UInt8_27_io_deq_bits : _T_4395 ? _Queue2_UInt8_26_io_deq_bits : _T_4394 ? _Queue2_UInt8_25_io_deq_bits : _T_4393 ? _Queue2_UInt8_24_io_deq_bits : _T_4392 ? _Queue2_UInt8_23_io_deq_bits : _T_4391 ? _Queue2_UInt8_22_io_deq_bits : _T_4390 ? _Queue2_UInt8_21_io_deq_bits : _T_4389 ? _Queue2_UInt8_20_io_deq_bits : _T_4388 ? _Queue2_UInt8_19_io_deq_bits : _T_4387 ? _Queue2_UInt8_18_io_deq_bits : _T_4386 ? _Queue2_UInt8_17_io_deq_bits : _T_4385 ? _Queue2_UInt8_16_io_deq_bits : _T_4384 ? _Queue2_UInt8_15_io_deq_bits : _T_4383 ? _Queue2_UInt8_14_io_deq_bits : _T_4382 ? _Queue2_UInt8_13_io_deq_bits : _T_4381 ? _Queue2_UInt8_12_io_deq_bits : _T_4380 ? _Queue2_UInt8_11_io_deq_bits : _T_4379 ? _Queue2_UInt8_10_io_deq_bits : _T_4378 ? _Queue2_UInt8_9_io_deq_bits : _T_4377 ? _Queue2_UInt8_8_io_deq_bits : _T_4376 ? _Queue2_UInt8_7_io_deq_bits : _T_4375 ? _Queue2_UInt8_6_io_deq_bits : _T_4374 ? _Queue2_UInt8_5_io_deq_bits : _T_4373 ? _Queue2_UInt8_4_io_deq_bits : _T_4372 ? _Queue2_UInt8_3_io_deq_bits : _T_4371 ? _Queue2_UInt8_2_io_deq_bits : _T_4370 ? _Queue2_UInt8_1_io_deq_bits : _T_4369 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_1 = _T_4400 ? _Queue2_UInt8_31_io_deq_valid : _T_4399 ? _Queue2_UInt8_30_io_deq_valid : _T_4398 ? _Queue2_UInt8_29_io_deq_valid : _T_4397 ? _Queue2_UInt8_28_io_deq_valid : _T_4396 ? _Queue2_UInt8_27_io_deq_valid : _T_4395 ? _Queue2_UInt8_26_io_deq_valid : _T_4394 ? _Queue2_UInt8_25_io_deq_valid : _T_4393 ? _Queue2_UInt8_24_io_deq_valid : _T_4392 ? _Queue2_UInt8_23_io_deq_valid : _T_4391 ? _Queue2_UInt8_22_io_deq_valid : _T_4390 ? _Queue2_UInt8_21_io_deq_valid : _T_4389 ? _Queue2_UInt8_20_io_deq_valid : _T_4388 ? _Queue2_UInt8_19_io_deq_valid : _T_4387 ? _Queue2_UInt8_18_io_deq_valid : _T_4386 ? _Queue2_UInt8_17_io_deq_valid : _T_4385 ? _Queue2_UInt8_16_io_deq_valid : _T_4384 ? _Queue2_UInt8_15_io_deq_valid : _T_4383 ? _Queue2_UInt8_14_io_deq_valid : _T_4382 ? _Queue2_UInt8_13_io_deq_valid : _T_4381 ? _Queue2_UInt8_12_io_deq_valid : _T_4380 ? _Queue2_UInt8_11_io_deq_valid : _T_4379 ? _Queue2_UInt8_10_io_deq_valid : _T_4378 ? _Queue2_UInt8_9_io_deq_valid : _T_4377 ? _Queue2_UInt8_8_io_deq_valid : _T_4376 ? _Queue2_UInt8_7_io_deq_valid : _T_4375 ? _Queue2_UInt8_6_io_deq_valid : _T_4374 ? _Queue2_UInt8_5_io_deq_valid : _T_4373 ? _Queue2_UInt8_4_io_deq_valid : _T_4372 ? _Queue2_UInt8_3_io_deq_valid : _T_4371 ? _Queue2_UInt8_2_io_deq_valid : _T_4370 ? _Queue2_UInt8_1_io_deq_valid : _T_4369 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_2 = _remapindex_T + 7'h2; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_92 = _remapindex_T_2 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_2 = _GEN_92[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_4401 = remapindex_2 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4402 = remapindex_2 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4403 = remapindex_2 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4404 = remapindex_2 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4405 = remapindex_2 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4406 = remapindex_2 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4407 = remapindex_2 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4408 = remapindex_2 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4409 = remapindex_2 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4410 = remapindex_2 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4411 = remapindex_2 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4412 = remapindex_2 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4413 = remapindex_2 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4414 = remapindex_2 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4415 = remapindex_2 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4416 = remapindex_2 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4417 = remapindex_2 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4418 = remapindex_2 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4419 = remapindex_2 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4420 = remapindex_2 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4421 = remapindex_2 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4422 = remapindex_2 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4423 = remapindex_2 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4424 = remapindex_2 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4425 = remapindex_2 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4426 = remapindex_2 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4427 = remapindex_2 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4428 = remapindex_2 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4429 = remapindex_2 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4430 = remapindex_2 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4431 = remapindex_2 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4432 = remapindex_2 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_2 = _T_4432 ? _Queue2_UInt8_31_io_deq_bits : _T_4431 ? _Queue2_UInt8_30_io_deq_bits : _T_4430 ? _Queue2_UInt8_29_io_deq_bits : _T_4429 ? _Queue2_UInt8_28_io_deq_bits : _T_4428 ? _Queue2_UInt8_27_io_deq_bits : _T_4427 ? _Queue2_UInt8_26_io_deq_bits : _T_4426 ? _Queue2_UInt8_25_io_deq_bits : _T_4425 ? _Queue2_UInt8_24_io_deq_bits : _T_4424 ? _Queue2_UInt8_23_io_deq_bits : _T_4423 ? _Queue2_UInt8_22_io_deq_bits : _T_4422 ? _Queue2_UInt8_21_io_deq_bits : _T_4421 ? _Queue2_UInt8_20_io_deq_bits : _T_4420 ? _Queue2_UInt8_19_io_deq_bits : _T_4419 ? _Queue2_UInt8_18_io_deq_bits : _T_4418 ? _Queue2_UInt8_17_io_deq_bits : _T_4417 ? _Queue2_UInt8_16_io_deq_bits : _T_4416 ? _Queue2_UInt8_15_io_deq_bits : _T_4415 ? _Queue2_UInt8_14_io_deq_bits : _T_4414 ? _Queue2_UInt8_13_io_deq_bits : _T_4413 ? _Queue2_UInt8_12_io_deq_bits : _T_4412 ? _Queue2_UInt8_11_io_deq_bits : _T_4411 ? _Queue2_UInt8_10_io_deq_bits : _T_4410 ? _Queue2_UInt8_9_io_deq_bits : _T_4409 ? _Queue2_UInt8_8_io_deq_bits : _T_4408 ? _Queue2_UInt8_7_io_deq_bits : _T_4407 ? _Queue2_UInt8_6_io_deq_bits : _T_4406 ? _Queue2_UInt8_5_io_deq_bits : _T_4405 ? _Queue2_UInt8_4_io_deq_bits : _T_4404 ? _Queue2_UInt8_3_io_deq_bits : _T_4403 ? _Queue2_UInt8_2_io_deq_bits : _T_4402 ? _Queue2_UInt8_1_io_deq_bits : _T_4401 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_2 = _T_4432 ? _Queue2_UInt8_31_io_deq_valid : _T_4431 ? _Queue2_UInt8_30_io_deq_valid : _T_4430 ? _Queue2_UInt8_29_io_deq_valid : _T_4429 ? _Queue2_UInt8_28_io_deq_valid : _T_4428 ? _Queue2_UInt8_27_io_deq_valid : _T_4427 ? _Queue2_UInt8_26_io_deq_valid : _T_4426 ? _Queue2_UInt8_25_io_deq_valid : _T_4425 ? _Queue2_UInt8_24_io_deq_valid : _T_4424 ? _Queue2_UInt8_23_io_deq_valid : _T_4423 ? _Queue2_UInt8_22_io_deq_valid : _T_4422 ? _Queue2_UInt8_21_io_deq_valid : _T_4421 ? _Queue2_UInt8_20_io_deq_valid : _T_4420 ? _Queue2_UInt8_19_io_deq_valid : _T_4419 ? _Queue2_UInt8_18_io_deq_valid : _T_4418 ? _Queue2_UInt8_17_io_deq_valid : _T_4417 ? _Queue2_UInt8_16_io_deq_valid : _T_4416 ? _Queue2_UInt8_15_io_deq_valid : _T_4415 ? _Queue2_UInt8_14_io_deq_valid : _T_4414 ? _Queue2_UInt8_13_io_deq_valid : _T_4413 ? _Queue2_UInt8_12_io_deq_valid : _T_4412 ? _Queue2_UInt8_11_io_deq_valid : _T_4411 ? _Queue2_UInt8_10_io_deq_valid : _T_4410 ? _Queue2_UInt8_9_io_deq_valid : _T_4409 ? _Queue2_UInt8_8_io_deq_valid : _T_4408 ? _Queue2_UInt8_7_io_deq_valid : _T_4407 ? _Queue2_UInt8_6_io_deq_valid : _T_4406 ? _Queue2_UInt8_5_io_deq_valid : _T_4405 ? _Queue2_UInt8_4_io_deq_valid : _T_4404 ? _Queue2_UInt8_3_io_deq_valid : _T_4403 ? _Queue2_UInt8_2_io_deq_valid : _T_4402 ? _Queue2_UInt8_1_io_deq_valid : _T_4401 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_3 = _remapindex_T + 7'h3; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_93 = _remapindex_T_3 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_3 = _GEN_93[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_4433 = remapindex_3 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4434 = remapindex_3 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4435 = remapindex_3 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4436 = remapindex_3 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4437 = remapindex_3 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4438 = remapindex_3 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4439 = remapindex_3 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4440 = remapindex_3 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4441 = remapindex_3 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4442 = remapindex_3 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4443 = remapindex_3 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4444 = remapindex_3 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4445 = remapindex_3 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4446 = remapindex_3 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4447 = remapindex_3 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4448 = remapindex_3 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4449 = remapindex_3 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4450 = remapindex_3 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4451 = remapindex_3 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4452 = remapindex_3 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4453 = remapindex_3 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4454 = remapindex_3 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4455 = remapindex_3 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4456 = remapindex_3 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4457 = remapindex_3 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4458 = remapindex_3 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4459 = remapindex_3 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4460 = remapindex_3 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4461 = remapindex_3 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4462 = remapindex_3 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4463 = remapindex_3 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4464 = remapindex_3 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_3 = _T_4464 ? _Queue2_UInt8_31_io_deq_bits : _T_4463 ? _Queue2_UInt8_30_io_deq_bits : _T_4462 ? _Queue2_UInt8_29_io_deq_bits : _T_4461 ? _Queue2_UInt8_28_io_deq_bits : _T_4460 ? _Queue2_UInt8_27_io_deq_bits : _T_4459 ? _Queue2_UInt8_26_io_deq_bits : _T_4458 ? _Queue2_UInt8_25_io_deq_bits : _T_4457 ? _Queue2_UInt8_24_io_deq_bits : _T_4456 ? _Queue2_UInt8_23_io_deq_bits : _T_4455 ? _Queue2_UInt8_22_io_deq_bits : _T_4454 ? _Queue2_UInt8_21_io_deq_bits : _T_4453 ? _Queue2_UInt8_20_io_deq_bits : _T_4452 ? _Queue2_UInt8_19_io_deq_bits : _T_4451 ? _Queue2_UInt8_18_io_deq_bits : _T_4450 ? _Queue2_UInt8_17_io_deq_bits : _T_4449 ? _Queue2_UInt8_16_io_deq_bits : _T_4448 ? _Queue2_UInt8_15_io_deq_bits : _T_4447 ? _Queue2_UInt8_14_io_deq_bits : _T_4446 ? _Queue2_UInt8_13_io_deq_bits : _T_4445 ? _Queue2_UInt8_12_io_deq_bits : _T_4444 ? _Queue2_UInt8_11_io_deq_bits : _T_4443 ? _Queue2_UInt8_10_io_deq_bits : _T_4442 ? _Queue2_UInt8_9_io_deq_bits : _T_4441 ? _Queue2_UInt8_8_io_deq_bits : _T_4440 ? _Queue2_UInt8_7_io_deq_bits : _T_4439 ? _Queue2_UInt8_6_io_deq_bits : _T_4438 ? _Queue2_UInt8_5_io_deq_bits : _T_4437 ? _Queue2_UInt8_4_io_deq_bits : _T_4436 ? _Queue2_UInt8_3_io_deq_bits : _T_4435 ? _Queue2_UInt8_2_io_deq_bits : _T_4434 ? _Queue2_UInt8_1_io_deq_bits : _T_4433 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_3 = _T_4464 ? _Queue2_UInt8_31_io_deq_valid : _T_4463 ? _Queue2_UInt8_30_io_deq_valid : _T_4462 ? _Queue2_UInt8_29_io_deq_valid : _T_4461 ? _Queue2_UInt8_28_io_deq_valid : _T_4460 ? _Queue2_UInt8_27_io_deq_valid : _T_4459 ? _Queue2_UInt8_26_io_deq_valid : _T_4458 ? _Queue2_UInt8_25_io_deq_valid : _T_4457 ? _Queue2_UInt8_24_io_deq_valid : _T_4456 ? _Queue2_UInt8_23_io_deq_valid : _T_4455 ? _Queue2_UInt8_22_io_deq_valid : _T_4454 ? _Queue2_UInt8_21_io_deq_valid : _T_4453 ? _Queue2_UInt8_20_io_deq_valid : _T_4452 ? _Queue2_UInt8_19_io_deq_valid : _T_4451 ? _Queue2_UInt8_18_io_deq_valid : _T_4450 ? _Queue2_UInt8_17_io_deq_valid : _T_4449 ? _Queue2_UInt8_16_io_deq_valid : _T_4448 ? _Queue2_UInt8_15_io_deq_valid : _T_4447 ? _Queue2_UInt8_14_io_deq_valid : _T_4446 ? _Queue2_UInt8_13_io_deq_valid : _T_4445 ? _Queue2_UInt8_12_io_deq_valid : _T_4444 ? _Queue2_UInt8_11_io_deq_valid : _T_4443 ? _Queue2_UInt8_10_io_deq_valid : _T_4442 ? _Queue2_UInt8_9_io_deq_valid : _T_4441 ? _Queue2_UInt8_8_io_deq_valid : _T_4440 ? _Queue2_UInt8_7_io_deq_valid : _T_4439 ? _Queue2_UInt8_6_io_deq_valid : _T_4438 ? _Queue2_UInt8_5_io_deq_valid : _T_4437 ? _Queue2_UInt8_4_io_deq_valid : _T_4436 ? _Queue2_UInt8_3_io_deq_valid : _T_4435 ? _Queue2_UInt8_2_io_deq_valid : _T_4434 ? _Queue2_UInt8_1_io_deq_valid : _T_4433 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_4 = _remapindex_T + 7'h4; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_94 = _remapindex_T_4 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_4 = _GEN_94[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_4465 = remapindex_4 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4466 = remapindex_4 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4467 = remapindex_4 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4468 = remapindex_4 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4469 = remapindex_4 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4470 = remapindex_4 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4471 = remapindex_4 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4472 = remapindex_4 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4473 = remapindex_4 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4474 = remapindex_4 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4475 = remapindex_4 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4476 = remapindex_4 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4477 = remapindex_4 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4478 = remapindex_4 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4479 = remapindex_4 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4480 = remapindex_4 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4481 = remapindex_4 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4482 = remapindex_4 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4483 = remapindex_4 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4484 = remapindex_4 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4485 = remapindex_4 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4486 = remapindex_4 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4487 = remapindex_4 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4488 = remapindex_4 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4489 = remapindex_4 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4490 = remapindex_4 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4491 = remapindex_4 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4492 = remapindex_4 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4493 = remapindex_4 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4494 = remapindex_4 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4495 = remapindex_4 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4496 = remapindex_4 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_4 = _T_4496 ? _Queue2_UInt8_31_io_deq_bits : _T_4495 ? _Queue2_UInt8_30_io_deq_bits : _T_4494 ? _Queue2_UInt8_29_io_deq_bits : _T_4493 ? _Queue2_UInt8_28_io_deq_bits : _T_4492 ? _Queue2_UInt8_27_io_deq_bits : _T_4491 ? _Queue2_UInt8_26_io_deq_bits : _T_4490 ? _Queue2_UInt8_25_io_deq_bits : _T_4489 ? _Queue2_UInt8_24_io_deq_bits : _T_4488 ? _Queue2_UInt8_23_io_deq_bits : _T_4487 ? _Queue2_UInt8_22_io_deq_bits : _T_4486 ? _Queue2_UInt8_21_io_deq_bits : _T_4485 ? _Queue2_UInt8_20_io_deq_bits : _T_4484 ? _Queue2_UInt8_19_io_deq_bits : _T_4483 ? _Queue2_UInt8_18_io_deq_bits : _T_4482 ? _Queue2_UInt8_17_io_deq_bits : _T_4481 ? _Queue2_UInt8_16_io_deq_bits : _T_4480 ? _Queue2_UInt8_15_io_deq_bits : _T_4479 ? _Queue2_UInt8_14_io_deq_bits : _T_4478 ? _Queue2_UInt8_13_io_deq_bits : _T_4477 ? _Queue2_UInt8_12_io_deq_bits : _T_4476 ? _Queue2_UInt8_11_io_deq_bits : _T_4475 ? _Queue2_UInt8_10_io_deq_bits : _T_4474 ? _Queue2_UInt8_9_io_deq_bits : _T_4473 ? _Queue2_UInt8_8_io_deq_bits : _T_4472 ? _Queue2_UInt8_7_io_deq_bits : _T_4471 ? _Queue2_UInt8_6_io_deq_bits : _T_4470 ? _Queue2_UInt8_5_io_deq_bits : _T_4469 ? _Queue2_UInt8_4_io_deq_bits : _T_4468 ? _Queue2_UInt8_3_io_deq_bits : _T_4467 ? _Queue2_UInt8_2_io_deq_bits : _T_4466 ? _Queue2_UInt8_1_io_deq_bits : _T_4465 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_4 = _T_4496 ? _Queue2_UInt8_31_io_deq_valid : _T_4495 ? _Queue2_UInt8_30_io_deq_valid : _T_4494 ? _Queue2_UInt8_29_io_deq_valid : _T_4493 ? _Queue2_UInt8_28_io_deq_valid : _T_4492 ? _Queue2_UInt8_27_io_deq_valid : _T_4491 ? _Queue2_UInt8_26_io_deq_valid : _T_4490 ? _Queue2_UInt8_25_io_deq_valid : _T_4489 ? _Queue2_UInt8_24_io_deq_valid : _T_4488 ? _Queue2_UInt8_23_io_deq_valid : _T_4487 ? _Queue2_UInt8_22_io_deq_valid : _T_4486 ? _Queue2_UInt8_21_io_deq_valid : _T_4485 ? _Queue2_UInt8_20_io_deq_valid : _T_4484 ? _Queue2_UInt8_19_io_deq_valid : _T_4483 ? _Queue2_UInt8_18_io_deq_valid : _T_4482 ? _Queue2_UInt8_17_io_deq_valid : _T_4481 ? _Queue2_UInt8_16_io_deq_valid : _T_4480 ? _Queue2_UInt8_15_io_deq_valid : _T_4479 ? _Queue2_UInt8_14_io_deq_valid : _T_4478 ? _Queue2_UInt8_13_io_deq_valid : _T_4477 ? _Queue2_UInt8_12_io_deq_valid : _T_4476 ? _Queue2_UInt8_11_io_deq_valid : _T_4475 ? _Queue2_UInt8_10_io_deq_valid : _T_4474 ? _Queue2_UInt8_9_io_deq_valid : _T_4473 ? _Queue2_UInt8_8_io_deq_valid : _T_4472 ? _Queue2_UInt8_7_io_deq_valid : _T_4471 ? _Queue2_UInt8_6_io_deq_valid : _T_4470 ? _Queue2_UInt8_5_io_deq_valid : _T_4469 ? _Queue2_UInt8_4_io_deq_valid : _T_4468 ? _Queue2_UInt8_3_io_deq_valid : _T_4467 ? _Queue2_UInt8_2_io_deq_valid : _T_4466 ? _Queue2_UInt8_1_io_deq_valid : _T_4465 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_5 = _remapindex_T + 7'h5; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_95 = _remapindex_T_5 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_5 = _GEN_95[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_4497 = remapindex_5 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4498 = remapindex_5 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4499 = remapindex_5 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4500 = remapindex_5 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4501 = remapindex_5 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4502 = remapindex_5 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4503 = remapindex_5 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4504 = remapindex_5 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4505 = remapindex_5 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4506 = remapindex_5 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4507 = remapindex_5 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4508 = remapindex_5 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4509 = remapindex_5 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4510 = remapindex_5 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4511 = remapindex_5 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4512 = remapindex_5 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4513 = remapindex_5 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4514 = remapindex_5 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4515 = remapindex_5 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4516 = remapindex_5 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4517 = remapindex_5 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4518 = remapindex_5 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4519 = remapindex_5 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4520 = remapindex_5 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4521 = remapindex_5 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4522 = remapindex_5 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4523 = remapindex_5 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4524 = remapindex_5 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4525 = remapindex_5 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4526 = remapindex_5 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4527 = remapindex_5 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4528 = remapindex_5 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_5 = _T_4528 ? _Queue2_UInt8_31_io_deq_bits : _T_4527 ? _Queue2_UInt8_30_io_deq_bits : _T_4526 ? _Queue2_UInt8_29_io_deq_bits : _T_4525 ? _Queue2_UInt8_28_io_deq_bits : _T_4524 ? _Queue2_UInt8_27_io_deq_bits : _T_4523 ? _Queue2_UInt8_26_io_deq_bits : _T_4522 ? _Queue2_UInt8_25_io_deq_bits : _T_4521 ? _Queue2_UInt8_24_io_deq_bits : _T_4520 ? _Queue2_UInt8_23_io_deq_bits : _T_4519 ? _Queue2_UInt8_22_io_deq_bits : _T_4518 ? _Queue2_UInt8_21_io_deq_bits : _T_4517 ? _Queue2_UInt8_20_io_deq_bits : _T_4516 ? _Queue2_UInt8_19_io_deq_bits : _T_4515 ? _Queue2_UInt8_18_io_deq_bits : _T_4514 ? _Queue2_UInt8_17_io_deq_bits : _T_4513 ? _Queue2_UInt8_16_io_deq_bits : _T_4512 ? _Queue2_UInt8_15_io_deq_bits : _T_4511 ? _Queue2_UInt8_14_io_deq_bits : _T_4510 ? _Queue2_UInt8_13_io_deq_bits : _T_4509 ? _Queue2_UInt8_12_io_deq_bits : _T_4508 ? _Queue2_UInt8_11_io_deq_bits : _T_4507 ? _Queue2_UInt8_10_io_deq_bits : _T_4506 ? _Queue2_UInt8_9_io_deq_bits : _T_4505 ? _Queue2_UInt8_8_io_deq_bits : _T_4504 ? _Queue2_UInt8_7_io_deq_bits : _T_4503 ? _Queue2_UInt8_6_io_deq_bits : _T_4502 ? _Queue2_UInt8_5_io_deq_bits : _T_4501 ? _Queue2_UInt8_4_io_deq_bits : _T_4500 ? _Queue2_UInt8_3_io_deq_bits : _T_4499 ? _Queue2_UInt8_2_io_deq_bits : _T_4498 ? _Queue2_UInt8_1_io_deq_bits : _T_4497 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_5 = _T_4528 ? _Queue2_UInt8_31_io_deq_valid : _T_4527 ? _Queue2_UInt8_30_io_deq_valid : _T_4526 ? _Queue2_UInt8_29_io_deq_valid : _T_4525 ? _Queue2_UInt8_28_io_deq_valid : _T_4524 ? _Queue2_UInt8_27_io_deq_valid : _T_4523 ? _Queue2_UInt8_26_io_deq_valid : _T_4522 ? _Queue2_UInt8_25_io_deq_valid : _T_4521 ? _Queue2_UInt8_24_io_deq_valid : _T_4520 ? _Queue2_UInt8_23_io_deq_valid : _T_4519 ? _Queue2_UInt8_22_io_deq_valid : _T_4518 ? _Queue2_UInt8_21_io_deq_valid : _T_4517 ? _Queue2_UInt8_20_io_deq_valid : _T_4516 ? _Queue2_UInt8_19_io_deq_valid : _T_4515 ? _Queue2_UInt8_18_io_deq_valid : _T_4514 ? _Queue2_UInt8_17_io_deq_valid : _T_4513 ? _Queue2_UInt8_16_io_deq_valid : _T_4512 ? _Queue2_UInt8_15_io_deq_valid : _T_4511 ? _Queue2_UInt8_14_io_deq_valid : _T_4510 ? _Queue2_UInt8_13_io_deq_valid : _T_4509 ? _Queue2_UInt8_12_io_deq_valid : _T_4508 ? _Queue2_UInt8_11_io_deq_valid : _T_4507 ? _Queue2_UInt8_10_io_deq_valid : _T_4506 ? _Queue2_UInt8_9_io_deq_valid : _T_4505 ? _Queue2_UInt8_8_io_deq_valid : _T_4504 ? _Queue2_UInt8_7_io_deq_valid : _T_4503 ? _Queue2_UInt8_6_io_deq_valid : _T_4502 ? _Queue2_UInt8_5_io_deq_valid : _T_4501 ? _Queue2_UInt8_4_io_deq_valid : _T_4500 ? _Queue2_UInt8_3_io_deq_valid : _T_4499 ? _Queue2_UInt8_2_io_deq_valid : _T_4498 ? _Queue2_UInt8_1_io_deq_valid : _T_4497 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_6 = _remapindex_T + 7'h6; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_96 = _remapindex_T_6 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_6 = _GEN_96[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_4529 = remapindex_6 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4530 = remapindex_6 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4531 = remapindex_6 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4532 = remapindex_6 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4533 = remapindex_6 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4534 = remapindex_6 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4535 = remapindex_6 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4536 = remapindex_6 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4537 = remapindex_6 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4538 = remapindex_6 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4539 = remapindex_6 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4540 = remapindex_6 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4541 = remapindex_6 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4542 = remapindex_6 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4543 = remapindex_6 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4544 = remapindex_6 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4545 = remapindex_6 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4546 = remapindex_6 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4547 = remapindex_6 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4548 = remapindex_6 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4549 = remapindex_6 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4550 = remapindex_6 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4551 = remapindex_6 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4552 = remapindex_6 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4553 = remapindex_6 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4554 = remapindex_6 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4555 = remapindex_6 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4556 = remapindex_6 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4557 = remapindex_6 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4558 = remapindex_6 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4559 = remapindex_6 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4560 = remapindex_6 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_6 = _T_4560 ? _Queue2_UInt8_31_io_deq_bits : _T_4559 ? _Queue2_UInt8_30_io_deq_bits : _T_4558 ? _Queue2_UInt8_29_io_deq_bits : _T_4557 ? _Queue2_UInt8_28_io_deq_bits : _T_4556 ? _Queue2_UInt8_27_io_deq_bits : _T_4555 ? _Queue2_UInt8_26_io_deq_bits : _T_4554 ? _Queue2_UInt8_25_io_deq_bits : _T_4553 ? _Queue2_UInt8_24_io_deq_bits : _T_4552 ? _Queue2_UInt8_23_io_deq_bits : _T_4551 ? _Queue2_UInt8_22_io_deq_bits : _T_4550 ? _Queue2_UInt8_21_io_deq_bits : _T_4549 ? _Queue2_UInt8_20_io_deq_bits : _T_4548 ? _Queue2_UInt8_19_io_deq_bits : _T_4547 ? _Queue2_UInt8_18_io_deq_bits : _T_4546 ? _Queue2_UInt8_17_io_deq_bits : _T_4545 ? _Queue2_UInt8_16_io_deq_bits : _T_4544 ? _Queue2_UInt8_15_io_deq_bits : _T_4543 ? _Queue2_UInt8_14_io_deq_bits : _T_4542 ? _Queue2_UInt8_13_io_deq_bits : _T_4541 ? _Queue2_UInt8_12_io_deq_bits : _T_4540 ? _Queue2_UInt8_11_io_deq_bits : _T_4539 ? _Queue2_UInt8_10_io_deq_bits : _T_4538 ? _Queue2_UInt8_9_io_deq_bits : _T_4537 ? _Queue2_UInt8_8_io_deq_bits : _T_4536 ? _Queue2_UInt8_7_io_deq_bits : _T_4535 ? _Queue2_UInt8_6_io_deq_bits : _T_4534 ? _Queue2_UInt8_5_io_deq_bits : _T_4533 ? _Queue2_UInt8_4_io_deq_bits : _T_4532 ? _Queue2_UInt8_3_io_deq_bits : _T_4531 ? _Queue2_UInt8_2_io_deq_bits : _T_4530 ? _Queue2_UInt8_1_io_deq_bits : _T_4529 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_6 = _T_4560 ? _Queue2_UInt8_31_io_deq_valid : _T_4559 ? _Queue2_UInt8_30_io_deq_valid : _T_4558 ? _Queue2_UInt8_29_io_deq_valid : _T_4557 ? _Queue2_UInt8_28_io_deq_valid : _T_4556 ? _Queue2_UInt8_27_io_deq_valid : _T_4555 ? _Queue2_UInt8_26_io_deq_valid : _T_4554 ? _Queue2_UInt8_25_io_deq_valid : _T_4553 ? _Queue2_UInt8_24_io_deq_valid : _T_4552 ? _Queue2_UInt8_23_io_deq_valid : _T_4551 ? _Queue2_UInt8_22_io_deq_valid : _T_4550 ? _Queue2_UInt8_21_io_deq_valid : _T_4549 ? _Queue2_UInt8_20_io_deq_valid : _T_4548 ? _Queue2_UInt8_19_io_deq_valid : _T_4547 ? _Queue2_UInt8_18_io_deq_valid : _T_4546 ? _Queue2_UInt8_17_io_deq_valid : _T_4545 ? _Queue2_UInt8_16_io_deq_valid : _T_4544 ? _Queue2_UInt8_15_io_deq_valid : _T_4543 ? _Queue2_UInt8_14_io_deq_valid : _T_4542 ? _Queue2_UInt8_13_io_deq_valid : _T_4541 ? _Queue2_UInt8_12_io_deq_valid : _T_4540 ? _Queue2_UInt8_11_io_deq_valid : _T_4539 ? _Queue2_UInt8_10_io_deq_valid : _T_4538 ? _Queue2_UInt8_9_io_deq_valid : _T_4537 ? _Queue2_UInt8_8_io_deq_valid : _T_4536 ? _Queue2_UInt8_7_io_deq_valid : _T_4535 ? _Queue2_UInt8_6_io_deq_valid : _T_4534 ? _Queue2_UInt8_5_io_deq_valid : _T_4533 ? _Queue2_UInt8_4_io_deq_valid : _T_4532 ? _Queue2_UInt8_3_io_deq_valid : _T_4531 ? _Queue2_UInt8_2_io_deq_valid : _T_4530 ? _Queue2_UInt8_1_io_deq_valid : _T_4529 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_7 = _remapindex_T + 7'h7; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_97 = _remapindex_T_7 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_7 = _GEN_97[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_4561 = remapindex_7 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4562 = remapindex_7 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4563 = remapindex_7 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4564 = remapindex_7 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4565 = remapindex_7 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4566 = remapindex_7 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4567 = remapindex_7 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4568 = remapindex_7 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4569 = remapindex_7 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4570 = remapindex_7 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4571 = remapindex_7 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4572 = remapindex_7 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4573 = remapindex_7 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4574 = remapindex_7 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4575 = remapindex_7 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4576 = remapindex_7 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4577 = remapindex_7 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4578 = remapindex_7 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4579 = remapindex_7 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4580 = remapindex_7 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4581 = remapindex_7 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4582 = remapindex_7 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4583 = remapindex_7 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4584 = remapindex_7 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4585 = remapindex_7 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4586 = remapindex_7 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4587 = remapindex_7 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4588 = remapindex_7 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4589 = remapindex_7 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4590 = remapindex_7 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4591 = remapindex_7 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4592 = remapindex_7 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_7 = _T_4592 ? _Queue2_UInt8_31_io_deq_bits : _T_4591 ? _Queue2_UInt8_30_io_deq_bits : _T_4590 ? _Queue2_UInt8_29_io_deq_bits : _T_4589 ? _Queue2_UInt8_28_io_deq_bits : _T_4588 ? _Queue2_UInt8_27_io_deq_bits : _T_4587 ? _Queue2_UInt8_26_io_deq_bits : _T_4586 ? _Queue2_UInt8_25_io_deq_bits : _T_4585 ? _Queue2_UInt8_24_io_deq_bits : _T_4584 ? _Queue2_UInt8_23_io_deq_bits : _T_4583 ? _Queue2_UInt8_22_io_deq_bits : _T_4582 ? _Queue2_UInt8_21_io_deq_bits : _T_4581 ? _Queue2_UInt8_20_io_deq_bits : _T_4580 ? _Queue2_UInt8_19_io_deq_bits : _T_4579 ? _Queue2_UInt8_18_io_deq_bits : _T_4578 ? _Queue2_UInt8_17_io_deq_bits : _T_4577 ? _Queue2_UInt8_16_io_deq_bits : _T_4576 ? _Queue2_UInt8_15_io_deq_bits : _T_4575 ? _Queue2_UInt8_14_io_deq_bits : _T_4574 ? _Queue2_UInt8_13_io_deq_bits : _T_4573 ? _Queue2_UInt8_12_io_deq_bits : _T_4572 ? _Queue2_UInt8_11_io_deq_bits : _T_4571 ? _Queue2_UInt8_10_io_deq_bits : _T_4570 ? _Queue2_UInt8_9_io_deq_bits : _T_4569 ? _Queue2_UInt8_8_io_deq_bits : _T_4568 ? _Queue2_UInt8_7_io_deq_bits : _T_4567 ? _Queue2_UInt8_6_io_deq_bits : _T_4566 ? _Queue2_UInt8_5_io_deq_bits : _T_4565 ? _Queue2_UInt8_4_io_deq_bits : _T_4564 ? _Queue2_UInt8_3_io_deq_bits : _T_4563 ? _Queue2_UInt8_2_io_deq_bits : _T_4562 ? _Queue2_UInt8_1_io_deq_bits : _T_4561 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_7 = _T_4592 ? _Queue2_UInt8_31_io_deq_valid : _T_4591 ? _Queue2_UInt8_30_io_deq_valid : _T_4590 ? _Queue2_UInt8_29_io_deq_valid : _T_4589 ? _Queue2_UInt8_28_io_deq_valid : _T_4588 ? _Queue2_UInt8_27_io_deq_valid : _T_4587 ? _Queue2_UInt8_26_io_deq_valid : _T_4586 ? _Queue2_UInt8_25_io_deq_valid : _T_4585 ? _Queue2_UInt8_24_io_deq_valid : _T_4584 ? _Queue2_UInt8_23_io_deq_valid : _T_4583 ? _Queue2_UInt8_22_io_deq_valid : _T_4582 ? _Queue2_UInt8_21_io_deq_valid : _T_4581 ? _Queue2_UInt8_20_io_deq_valid : _T_4580 ? _Queue2_UInt8_19_io_deq_valid : _T_4579 ? _Queue2_UInt8_18_io_deq_valid : _T_4578 ? _Queue2_UInt8_17_io_deq_valid : _T_4577 ? _Queue2_UInt8_16_io_deq_valid : _T_4576 ? _Queue2_UInt8_15_io_deq_valid : _T_4575 ? _Queue2_UInt8_14_io_deq_valid : _T_4574 ? _Queue2_UInt8_13_io_deq_valid : _T_4573 ? _Queue2_UInt8_12_io_deq_valid : _T_4572 ? _Queue2_UInt8_11_io_deq_valid : _T_4571 ? _Queue2_UInt8_10_io_deq_valid : _T_4570 ? _Queue2_UInt8_9_io_deq_valid : _T_4569 ? _Queue2_UInt8_8_io_deq_valid : _T_4568 ? _Queue2_UInt8_7_io_deq_valid : _T_4567 ? _Queue2_UInt8_6_io_deq_valid : _T_4566 ? _Queue2_UInt8_5_io_deq_valid : _T_4565 ? _Queue2_UInt8_4_io_deq_valid : _T_4564 ? _Queue2_UInt8_3_io_deq_valid : _T_4563 ? _Queue2_UInt8_2_io_deq_valid : _T_4562 ? _Queue2_UInt8_1_io_deq_valid : _T_4561 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_8 = _remapindex_T + 7'h8; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_98 = _remapindex_T_8 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_8 = _GEN_98[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_4593 = remapindex_8 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4594 = remapindex_8 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4595 = remapindex_8 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4596 = remapindex_8 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4597 = remapindex_8 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4598 = remapindex_8 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4599 = remapindex_8 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4600 = remapindex_8 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4601 = remapindex_8 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4602 = remapindex_8 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4603 = remapindex_8 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4604 = remapindex_8 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4605 = remapindex_8 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4606 = remapindex_8 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4607 = remapindex_8 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4608 = remapindex_8 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4609 = remapindex_8 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4610 = remapindex_8 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4611 = remapindex_8 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4612 = remapindex_8 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4613 = remapindex_8 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4614 = remapindex_8 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4615 = remapindex_8 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4616 = remapindex_8 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4617 = remapindex_8 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4618 = remapindex_8 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4619 = remapindex_8 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4620 = remapindex_8 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4621 = remapindex_8 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4622 = remapindex_8 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4623 = remapindex_8 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4624 = remapindex_8 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_8 = _T_4624 ? _Queue2_UInt8_31_io_deq_bits : _T_4623 ? _Queue2_UInt8_30_io_deq_bits : _T_4622 ? _Queue2_UInt8_29_io_deq_bits : _T_4621 ? _Queue2_UInt8_28_io_deq_bits : _T_4620 ? _Queue2_UInt8_27_io_deq_bits : _T_4619 ? _Queue2_UInt8_26_io_deq_bits : _T_4618 ? _Queue2_UInt8_25_io_deq_bits : _T_4617 ? _Queue2_UInt8_24_io_deq_bits : _T_4616 ? _Queue2_UInt8_23_io_deq_bits : _T_4615 ? _Queue2_UInt8_22_io_deq_bits : _T_4614 ? _Queue2_UInt8_21_io_deq_bits : _T_4613 ? _Queue2_UInt8_20_io_deq_bits : _T_4612 ? _Queue2_UInt8_19_io_deq_bits : _T_4611 ? _Queue2_UInt8_18_io_deq_bits : _T_4610 ? _Queue2_UInt8_17_io_deq_bits : _T_4609 ? _Queue2_UInt8_16_io_deq_bits : _T_4608 ? _Queue2_UInt8_15_io_deq_bits : _T_4607 ? _Queue2_UInt8_14_io_deq_bits : _T_4606 ? _Queue2_UInt8_13_io_deq_bits : _T_4605 ? _Queue2_UInt8_12_io_deq_bits : _T_4604 ? _Queue2_UInt8_11_io_deq_bits : _T_4603 ? _Queue2_UInt8_10_io_deq_bits : _T_4602 ? _Queue2_UInt8_9_io_deq_bits : _T_4601 ? _Queue2_UInt8_8_io_deq_bits : _T_4600 ? _Queue2_UInt8_7_io_deq_bits : _T_4599 ? _Queue2_UInt8_6_io_deq_bits : _T_4598 ? _Queue2_UInt8_5_io_deq_bits : _T_4597 ? _Queue2_UInt8_4_io_deq_bits : _T_4596 ? _Queue2_UInt8_3_io_deq_bits : _T_4595 ? _Queue2_UInt8_2_io_deq_bits : _T_4594 ? _Queue2_UInt8_1_io_deq_bits : _T_4593 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_8 = _T_4624 ? _Queue2_UInt8_31_io_deq_valid : _T_4623 ? _Queue2_UInt8_30_io_deq_valid : _T_4622 ? _Queue2_UInt8_29_io_deq_valid : _T_4621 ? _Queue2_UInt8_28_io_deq_valid : _T_4620 ? _Queue2_UInt8_27_io_deq_valid : _T_4619 ? _Queue2_UInt8_26_io_deq_valid : _T_4618 ? _Queue2_UInt8_25_io_deq_valid : _T_4617 ? _Queue2_UInt8_24_io_deq_valid : _T_4616 ? _Queue2_UInt8_23_io_deq_valid : _T_4615 ? _Queue2_UInt8_22_io_deq_valid : _T_4614 ? _Queue2_UInt8_21_io_deq_valid : _T_4613 ? _Queue2_UInt8_20_io_deq_valid : _T_4612 ? _Queue2_UInt8_19_io_deq_valid : _T_4611 ? _Queue2_UInt8_18_io_deq_valid : _T_4610 ? _Queue2_UInt8_17_io_deq_valid : _T_4609 ? _Queue2_UInt8_16_io_deq_valid : _T_4608 ? _Queue2_UInt8_15_io_deq_valid : _T_4607 ? _Queue2_UInt8_14_io_deq_valid : _T_4606 ? _Queue2_UInt8_13_io_deq_valid : _T_4605 ? _Queue2_UInt8_12_io_deq_valid : _T_4604 ? _Queue2_UInt8_11_io_deq_valid : _T_4603 ? _Queue2_UInt8_10_io_deq_valid : _T_4602 ? _Queue2_UInt8_9_io_deq_valid : _T_4601 ? _Queue2_UInt8_8_io_deq_valid : _T_4600 ? _Queue2_UInt8_7_io_deq_valid : _T_4599 ? _Queue2_UInt8_6_io_deq_valid : _T_4598 ? _Queue2_UInt8_5_io_deq_valid : _T_4597 ? _Queue2_UInt8_4_io_deq_valid : _T_4596 ? _Queue2_UInt8_3_io_deq_valid : _T_4595 ? _Queue2_UInt8_2_io_deq_valid : _T_4594 ? _Queue2_UInt8_1_io_deq_valid : _T_4593 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_9 = _remapindex_T + 7'h9; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_99 = _remapindex_T_9 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_9 = _GEN_99[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_4625 = remapindex_9 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4626 = remapindex_9 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4627 = remapindex_9 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4628 = remapindex_9 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4629 = remapindex_9 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4630 = remapindex_9 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4631 = remapindex_9 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4632 = remapindex_9 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4633 = remapindex_9 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4634 = remapindex_9 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4635 = remapindex_9 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4636 = remapindex_9 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4637 = remapindex_9 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4638 = remapindex_9 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4639 = remapindex_9 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4640 = remapindex_9 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4641 = remapindex_9 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4642 = remapindex_9 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4643 = remapindex_9 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4644 = remapindex_9 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4645 = remapindex_9 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4646 = remapindex_9 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4647 = remapindex_9 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4648 = remapindex_9 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4649 = remapindex_9 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4650 = remapindex_9 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4651 = remapindex_9 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4652 = remapindex_9 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4653 = remapindex_9 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4654 = remapindex_9 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4655 = remapindex_9 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4656 = remapindex_9 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_9 = _T_4656 ? _Queue2_UInt8_31_io_deq_bits : _T_4655 ? _Queue2_UInt8_30_io_deq_bits : _T_4654 ? _Queue2_UInt8_29_io_deq_bits : _T_4653 ? _Queue2_UInt8_28_io_deq_bits : _T_4652 ? _Queue2_UInt8_27_io_deq_bits : _T_4651 ? _Queue2_UInt8_26_io_deq_bits : _T_4650 ? _Queue2_UInt8_25_io_deq_bits : _T_4649 ? _Queue2_UInt8_24_io_deq_bits : _T_4648 ? _Queue2_UInt8_23_io_deq_bits : _T_4647 ? _Queue2_UInt8_22_io_deq_bits : _T_4646 ? _Queue2_UInt8_21_io_deq_bits : _T_4645 ? _Queue2_UInt8_20_io_deq_bits : _T_4644 ? _Queue2_UInt8_19_io_deq_bits : _T_4643 ? _Queue2_UInt8_18_io_deq_bits : _T_4642 ? _Queue2_UInt8_17_io_deq_bits : _T_4641 ? _Queue2_UInt8_16_io_deq_bits : _T_4640 ? _Queue2_UInt8_15_io_deq_bits : _T_4639 ? _Queue2_UInt8_14_io_deq_bits : _T_4638 ? _Queue2_UInt8_13_io_deq_bits : _T_4637 ? _Queue2_UInt8_12_io_deq_bits : _T_4636 ? _Queue2_UInt8_11_io_deq_bits : _T_4635 ? _Queue2_UInt8_10_io_deq_bits : _T_4634 ? _Queue2_UInt8_9_io_deq_bits : _T_4633 ? _Queue2_UInt8_8_io_deq_bits : _T_4632 ? _Queue2_UInt8_7_io_deq_bits : _T_4631 ? _Queue2_UInt8_6_io_deq_bits : _T_4630 ? _Queue2_UInt8_5_io_deq_bits : _T_4629 ? _Queue2_UInt8_4_io_deq_bits : _T_4628 ? _Queue2_UInt8_3_io_deq_bits : _T_4627 ? _Queue2_UInt8_2_io_deq_bits : _T_4626 ? _Queue2_UInt8_1_io_deq_bits : _T_4625 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_9 = _T_4656 ? _Queue2_UInt8_31_io_deq_valid : _T_4655 ? _Queue2_UInt8_30_io_deq_valid : _T_4654 ? _Queue2_UInt8_29_io_deq_valid : _T_4653 ? _Queue2_UInt8_28_io_deq_valid : _T_4652 ? _Queue2_UInt8_27_io_deq_valid : _T_4651 ? _Queue2_UInt8_26_io_deq_valid : _T_4650 ? _Queue2_UInt8_25_io_deq_valid : _T_4649 ? _Queue2_UInt8_24_io_deq_valid : _T_4648 ? _Queue2_UInt8_23_io_deq_valid : _T_4647 ? _Queue2_UInt8_22_io_deq_valid : _T_4646 ? _Queue2_UInt8_21_io_deq_valid : _T_4645 ? _Queue2_UInt8_20_io_deq_valid : _T_4644 ? _Queue2_UInt8_19_io_deq_valid : _T_4643 ? _Queue2_UInt8_18_io_deq_valid : _T_4642 ? _Queue2_UInt8_17_io_deq_valid : _T_4641 ? _Queue2_UInt8_16_io_deq_valid : _T_4640 ? _Queue2_UInt8_15_io_deq_valid : _T_4639 ? _Queue2_UInt8_14_io_deq_valid : _T_4638 ? _Queue2_UInt8_13_io_deq_valid : _T_4637 ? _Queue2_UInt8_12_io_deq_valid : _T_4636 ? _Queue2_UInt8_11_io_deq_valid : _T_4635 ? _Queue2_UInt8_10_io_deq_valid : _T_4634 ? _Queue2_UInt8_9_io_deq_valid : _T_4633 ? _Queue2_UInt8_8_io_deq_valid : _T_4632 ? _Queue2_UInt8_7_io_deq_valid : _T_4631 ? _Queue2_UInt8_6_io_deq_valid : _T_4630 ? _Queue2_UInt8_5_io_deq_valid : _T_4629 ? _Queue2_UInt8_4_io_deq_valid : _T_4628 ? _Queue2_UInt8_3_io_deq_valid : _T_4627 ? _Queue2_UInt8_2_io_deq_valid : _T_4626 ? _Queue2_UInt8_1_io_deq_valid : _T_4625 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_10 = _remapindex_T + 7'hA; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_100 = _remapindex_T_10 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_10 = _GEN_100[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_4657 = remapindex_10 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4658 = remapindex_10 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4659 = remapindex_10 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4660 = remapindex_10 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4661 = remapindex_10 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4662 = remapindex_10 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4663 = remapindex_10 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4664 = remapindex_10 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4665 = remapindex_10 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4666 = remapindex_10 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4667 = remapindex_10 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4668 = remapindex_10 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4669 = remapindex_10 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4670 = remapindex_10 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4671 = remapindex_10 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4672 = remapindex_10 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4673 = remapindex_10 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4674 = remapindex_10 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4675 = remapindex_10 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4676 = remapindex_10 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4677 = remapindex_10 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4678 = remapindex_10 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4679 = remapindex_10 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4680 = remapindex_10 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4681 = remapindex_10 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4682 = remapindex_10 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4683 = remapindex_10 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4684 = remapindex_10 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4685 = remapindex_10 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4686 = remapindex_10 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4687 = remapindex_10 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4688 = remapindex_10 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_10 = _T_4688 ? _Queue2_UInt8_31_io_deq_bits : _T_4687 ? _Queue2_UInt8_30_io_deq_bits : _T_4686 ? _Queue2_UInt8_29_io_deq_bits : _T_4685 ? _Queue2_UInt8_28_io_deq_bits : _T_4684 ? _Queue2_UInt8_27_io_deq_bits : _T_4683 ? _Queue2_UInt8_26_io_deq_bits : _T_4682 ? _Queue2_UInt8_25_io_deq_bits : _T_4681 ? _Queue2_UInt8_24_io_deq_bits : _T_4680 ? _Queue2_UInt8_23_io_deq_bits : _T_4679 ? _Queue2_UInt8_22_io_deq_bits : _T_4678 ? _Queue2_UInt8_21_io_deq_bits : _T_4677 ? _Queue2_UInt8_20_io_deq_bits : _T_4676 ? _Queue2_UInt8_19_io_deq_bits : _T_4675 ? _Queue2_UInt8_18_io_deq_bits : _T_4674 ? _Queue2_UInt8_17_io_deq_bits : _T_4673 ? _Queue2_UInt8_16_io_deq_bits : _T_4672 ? _Queue2_UInt8_15_io_deq_bits : _T_4671 ? _Queue2_UInt8_14_io_deq_bits : _T_4670 ? _Queue2_UInt8_13_io_deq_bits : _T_4669 ? _Queue2_UInt8_12_io_deq_bits : _T_4668 ? _Queue2_UInt8_11_io_deq_bits : _T_4667 ? _Queue2_UInt8_10_io_deq_bits : _T_4666 ? _Queue2_UInt8_9_io_deq_bits : _T_4665 ? _Queue2_UInt8_8_io_deq_bits : _T_4664 ? _Queue2_UInt8_7_io_deq_bits : _T_4663 ? _Queue2_UInt8_6_io_deq_bits : _T_4662 ? _Queue2_UInt8_5_io_deq_bits : _T_4661 ? _Queue2_UInt8_4_io_deq_bits : _T_4660 ? _Queue2_UInt8_3_io_deq_bits : _T_4659 ? _Queue2_UInt8_2_io_deq_bits : _T_4658 ? _Queue2_UInt8_1_io_deq_bits : _T_4657 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_10 = _T_4688 ? _Queue2_UInt8_31_io_deq_valid : _T_4687 ? _Queue2_UInt8_30_io_deq_valid : _T_4686 ? _Queue2_UInt8_29_io_deq_valid : _T_4685 ? _Queue2_UInt8_28_io_deq_valid : _T_4684 ? _Queue2_UInt8_27_io_deq_valid : _T_4683 ? _Queue2_UInt8_26_io_deq_valid : _T_4682 ? _Queue2_UInt8_25_io_deq_valid : _T_4681 ? _Queue2_UInt8_24_io_deq_valid : _T_4680 ? _Queue2_UInt8_23_io_deq_valid : _T_4679 ? _Queue2_UInt8_22_io_deq_valid : _T_4678 ? _Queue2_UInt8_21_io_deq_valid : _T_4677 ? _Queue2_UInt8_20_io_deq_valid : _T_4676 ? _Queue2_UInt8_19_io_deq_valid : _T_4675 ? _Queue2_UInt8_18_io_deq_valid : _T_4674 ? _Queue2_UInt8_17_io_deq_valid : _T_4673 ? _Queue2_UInt8_16_io_deq_valid : _T_4672 ? _Queue2_UInt8_15_io_deq_valid : _T_4671 ? _Queue2_UInt8_14_io_deq_valid : _T_4670 ? _Queue2_UInt8_13_io_deq_valid : _T_4669 ? _Queue2_UInt8_12_io_deq_valid : _T_4668 ? _Queue2_UInt8_11_io_deq_valid : _T_4667 ? _Queue2_UInt8_10_io_deq_valid : _T_4666 ? _Queue2_UInt8_9_io_deq_valid : _T_4665 ? _Queue2_UInt8_8_io_deq_valid : _T_4664 ? _Queue2_UInt8_7_io_deq_valid : _T_4663 ? _Queue2_UInt8_6_io_deq_valid : _T_4662 ? _Queue2_UInt8_5_io_deq_valid : _T_4661 ? _Queue2_UInt8_4_io_deq_valid : _T_4660 ? _Queue2_UInt8_3_io_deq_valid : _T_4659 ? _Queue2_UInt8_2_io_deq_valid : _T_4658 ? _Queue2_UInt8_1_io_deq_valid : _T_4657 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_11 = _remapindex_T + 7'hB; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_101 = _remapindex_T_11 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_11 = _GEN_101[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_4689 = remapindex_11 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4690 = remapindex_11 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4691 = remapindex_11 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4692 = remapindex_11 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4693 = remapindex_11 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4694 = remapindex_11 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4695 = remapindex_11 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4696 = remapindex_11 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4697 = remapindex_11 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4698 = remapindex_11 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4699 = remapindex_11 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4700 = remapindex_11 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4701 = remapindex_11 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4702 = remapindex_11 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4703 = remapindex_11 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4704 = remapindex_11 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4705 = remapindex_11 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4706 = remapindex_11 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4707 = remapindex_11 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4708 = remapindex_11 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4709 = remapindex_11 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4710 = remapindex_11 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4711 = remapindex_11 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4712 = remapindex_11 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4713 = remapindex_11 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4714 = remapindex_11 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4715 = remapindex_11 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4716 = remapindex_11 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4717 = remapindex_11 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4718 = remapindex_11 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4719 = remapindex_11 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4720 = remapindex_11 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_11 = _T_4720 ? _Queue2_UInt8_31_io_deq_bits : _T_4719 ? _Queue2_UInt8_30_io_deq_bits : _T_4718 ? _Queue2_UInt8_29_io_deq_bits : _T_4717 ? _Queue2_UInt8_28_io_deq_bits : _T_4716 ? _Queue2_UInt8_27_io_deq_bits : _T_4715 ? _Queue2_UInt8_26_io_deq_bits : _T_4714 ? _Queue2_UInt8_25_io_deq_bits : _T_4713 ? _Queue2_UInt8_24_io_deq_bits : _T_4712 ? _Queue2_UInt8_23_io_deq_bits : _T_4711 ? _Queue2_UInt8_22_io_deq_bits : _T_4710 ? _Queue2_UInt8_21_io_deq_bits : _T_4709 ? _Queue2_UInt8_20_io_deq_bits : _T_4708 ? _Queue2_UInt8_19_io_deq_bits : _T_4707 ? _Queue2_UInt8_18_io_deq_bits : _T_4706 ? _Queue2_UInt8_17_io_deq_bits : _T_4705 ? _Queue2_UInt8_16_io_deq_bits : _T_4704 ? _Queue2_UInt8_15_io_deq_bits : _T_4703 ? _Queue2_UInt8_14_io_deq_bits : _T_4702 ? _Queue2_UInt8_13_io_deq_bits : _T_4701 ? _Queue2_UInt8_12_io_deq_bits : _T_4700 ? _Queue2_UInt8_11_io_deq_bits : _T_4699 ? _Queue2_UInt8_10_io_deq_bits : _T_4698 ? _Queue2_UInt8_9_io_deq_bits : _T_4697 ? _Queue2_UInt8_8_io_deq_bits : _T_4696 ? _Queue2_UInt8_7_io_deq_bits : _T_4695 ? _Queue2_UInt8_6_io_deq_bits : _T_4694 ? _Queue2_UInt8_5_io_deq_bits : _T_4693 ? _Queue2_UInt8_4_io_deq_bits : _T_4692 ? _Queue2_UInt8_3_io_deq_bits : _T_4691 ? _Queue2_UInt8_2_io_deq_bits : _T_4690 ? _Queue2_UInt8_1_io_deq_bits : _T_4689 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_11 = _T_4720 ? _Queue2_UInt8_31_io_deq_valid : _T_4719 ? _Queue2_UInt8_30_io_deq_valid : _T_4718 ? _Queue2_UInt8_29_io_deq_valid : _T_4717 ? _Queue2_UInt8_28_io_deq_valid : _T_4716 ? _Queue2_UInt8_27_io_deq_valid : _T_4715 ? _Queue2_UInt8_26_io_deq_valid : _T_4714 ? _Queue2_UInt8_25_io_deq_valid : _T_4713 ? _Queue2_UInt8_24_io_deq_valid : _T_4712 ? _Queue2_UInt8_23_io_deq_valid : _T_4711 ? _Queue2_UInt8_22_io_deq_valid : _T_4710 ? _Queue2_UInt8_21_io_deq_valid : _T_4709 ? _Queue2_UInt8_20_io_deq_valid : _T_4708 ? _Queue2_UInt8_19_io_deq_valid : _T_4707 ? _Queue2_UInt8_18_io_deq_valid : _T_4706 ? _Queue2_UInt8_17_io_deq_valid : _T_4705 ? _Queue2_UInt8_16_io_deq_valid : _T_4704 ? _Queue2_UInt8_15_io_deq_valid : _T_4703 ? _Queue2_UInt8_14_io_deq_valid : _T_4702 ? _Queue2_UInt8_13_io_deq_valid : _T_4701 ? _Queue2_UInt8_12_io_deq_valid : _T_4700 ? _Queue2_UInt8_11_io_deq_valid : _T_4699 ? _Queue2_UInt8_10_io_deq_valid : _T_4698 ? _Queue2_UInt8_9_io_deq_valid : _T_4697 ? _Queue2_UInt8_8_io_deq_valid : _T_4696 ? _Queue2_UInt8_7_io_deq_valid : _T_4695 ? _Queue2_UInt8_6_io_deq_valid : _T_4694 ? _Queue2_UInt8_5_io_deq_valid : _T_4693 ? _Queue2_UInt8_4_io_deq_valid : _T_4692 ? _Queue2_UInt8_3_io_deq_valid : _T_4691 ? _Queue2_UInt8_2_io_deq_valid : _T_4690 ? _Queue2_UInt8_1_io_deq_valid : _T_4689 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_12 = _remapindex_T + 7'hC; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_102 = _remapindex_T_12 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_12 = _GEN_102[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_4721 = remapindex_12 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4722 = remapindex_12 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4723 = remapindex_12 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4724 = remapindex_12 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4725 = remapindex_12 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4726 = remapindex_12 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4727 = remapindex_12 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4728 = remapindex_12 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4729 = remapindex_12 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4730 = remapindex_12 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4731 = remapindex_12 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4732 = remapindex_12 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4733 = remapindex_12 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4734 = remapindex_12 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4735 = remapindex_12 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4736 = remapindex_12 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4737 = remapindex_12 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4738 = remapindex_12 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4739 = remapindex_12 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4740 = remapindex_12 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4741 = remapindex_12 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4742 = remapindex_12 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4743 = remapindex_12 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4744 = remapindex_12 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4745 = remapindex_12 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4746 = remapindex_12 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4747 = remapindex_12 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4748 = remapindex_12 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4749 = remapindex_12 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4750 = remapindex_12 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4751 = remapindex_12 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4752 = remapindex_12 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_12 = _T_4752 ? _Queue2_UInt8_31_io_deq_bits : _T_4751 ? _Queue2_UInt8_30_io_deq_bits : _T_4750 ? _Queue2_UInt8_29_io_deq_bits : _T_4749 ? _Queue2_UInt8_28_io_deq_bits : _T_4748 ? _Queue2_UInt8_27_io_deq_bits : _T_4747 ? _Queue2_UInt8_26_io_deq_bits : _T_4746 ? _Queue2_UInt8_25_io_deq_bits : _T_4745 ? _Queue2_UInt8_24_io_deq_bits : _T_4744 ? _Queue2_UInt8_23_io_deq_bits : _T_4743 ? _Queue2_UInt8_22_io_deq_bits : _T_4742 ? _Queue2_UInt8_21_io_deq_bits : _T_4741 ? _Queue2_UInt8_20_io_deq_bits : _T_4740 ? _Queue2_UInt8_19_io_deq_bits : _T_4739 ? _Queue2_UInt8_18_io_deq_bits : _T_4738 ? _Queue2_UInt8_17_io_deq_bits : _T_4737 ? _Queue2_UInt8_16_io_deq_bits : _T_4736 ? _Queue2_UInt8_15_io_deq_bits : _T_4735 ? _Queue2_UInt8_14_io_deq_bits : _T_4734 ? _Queue2_UInt8_13_io_deq_bits : _T_4733 ? _Queue2_UInt8_12_io_deq_bits : _T_4732 ? _Queue2_UInt8_11_io_deq_bits : _T_4731 ? _Queue2_UInt8_10_io_deq_bits : _T_4730 ? _Queue2_UInt8_9_io_deq_bits : _T_4729 ? _Queue2_UInt8_8_io_deq_bits : _T_4728 ? _Queue2_UInt8_7_io_deq_bits : _T_4727 ? _Queue2_UInt8_6_io_deq_bits : _T_4726 ? _Queue2_UInt8_5_io_deq_bits : _T_4725 ? _Queue2_UInt8_4_io_deq_bits : _T_4724 ? _Queue2_UInt8_3_io_deq_bits : _T_4723 ? _Queue2_UInt8_2_io_deq_bits : _T_4722 ? _Queue2_UInt8_1_io_deq_bits : _T_4721 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_12 = _T_4752 ? _Queue2_UInt8_31_io_deq_valid : _T_4751 ? _Queue2_UInt8_30_io_deq_valid : _T_4750 ? _Queue2_UInt8_29_io_deq_valid : _T_4749 ? _Queue2_UInt8_28_io_deq_valid : _T_4748 ? _Queue2_UInt8_27_io_deq_valid : _T_4747 ? _Queue2_UInt8_26_io_deq_valid : _T_4746 ? _Queue2_UInt8_25_io_deq_valid : _T_4745 ? _Queue2_UInt8_24_io_deq_valid : _T_4744 ? _Queue2_UInt8_23_io_deq_valid : _T_4743 ? _Queue2_UInt8_22_io_deq_valid : _T_4742 ? _Queue2_UInt8_21_io_deq_valid : _T_4741 ? _Queue2_UInt8_20_io_deq_valid : _T_4740 ? _Queue2_UInt8_19_io_deq_valid : _T_4739 ? _Queue2_UInt8_18_io_deq_valid : _T_4738 ? _Queue2_UInt8_17_io_deq_valid : _T_4737 ? _Queue2_UInt8_16_io_deq_valid : _T_4736 ? _Queue2_UInt8_15_io_deq_valid : _T_4735 ? _Queue2_UInt8_14_io_deq_valid : _T_4734 ? _Queue2_UInt8_13_io_deq_valid : _T_4733 ? _Queue2_UInt8_12_io_deq_valid : _T_4732 ? _Queue2_UInt8_11_io_deq_valid : _T_4731 ? _Queue2_UInt8_10_io_deq_valid : _T_4730 ? _Queue2_UInt8_9_io_deq_valid : _T_4729 ? _Queue2_UInt8_8_io_deq_valid : _T_4728 ? _Queue2_UInt8_7_io_deq_valid : _T_4727 ? _Queue2_UInt8_6_io_deq_valid : _T_4726 ? _Queue2_UInt8_5_io_deq_valid : _T_4725 ? _Queue2_UInt8_4_io_deq_valid : _T_4724 ? _Queue2_UInt8_3_io_deq_valid : _T_4723 ? _Queue2_UInt8_2_io_deq_valid : _T_4722 ? _Queue2_UInt8_1_io_deq_valid : _T_4721 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_13 = _remapindex_T + 7'hD; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_103 = _remapindex_T_13 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_13 = _GEN_103[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_4753 = remapindex_13 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4754 = remapindex_13 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4755 = remapindex_13 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4756 = remapindex_13 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4757 = remapindex_13 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4758 = remapindex_13 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4759 = remapindex_13 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4760 = remapindex_13 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4761 = remapindex_13 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4762 = remapindex_13 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4763 = remapindex_13 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4764 = remapindex_13 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4765 = remapindex_13 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4766 = remapindex_13 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4767 = remapindex_13 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4768 = remapindex_13 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4769 = remapindex_13 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4770 = remapindex_13 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4771 = remapindex_13 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4772 = remapindex_13 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4773 = remapindex_13 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4774 = remapindex_13 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4775 = remapindex_13 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4776 = remapindex_13 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4777 = remapindex_13 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4778 = remapindex_13 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4779 = remapindex_13 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4780 = remapindex_13 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4781 = remapindex_13 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4782 = remapindex_13 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4783 = remapindex_13 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4784 = remapindex_13 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_13 = _T_4784 ? _Queue2_UInt8_31_io_deq_bits : _T_4783 ? _Queue2_UInt8_30_io_deq_bits : _T_4782 ? _Queue2_UInt8_29_io_deq_bits : _T_4781 ? _Queue2_UInt8_28_io_deq_bits : _T_4780 ? _Queue2_UInt8_27_io_deq_bits : _T_4779 ? _Queue2_UInt8_26_io_deq_bits : _T_4778 ? _Queue2_UInt8_25_io_deq_bits : _T_4777 ? _Queue2_UInt8_24_io_deq_bits : _T_4776 ? _Queue2_UInt8_23_io_deq_bits : _T_4775 ? _Queue2_UInt8_22_io_deq_bits : _T_4774 ? _Queue2_UInt8_21_io_deq_bits : _T_4773 ? _Queue2_UInt8_20_io_deq_bits : _T_4772 ? _Queue2_UInt8_19_io_deq_bits : _T_4771 ? _Queue2_UInt8_18_io_deq_bits : _T_4770 ? _Queue2_UInt8_17_io_deq_bits : _T_4769 ? _Queue2_UInt8_16_io_deq_bits : _T_4768 ? _Queue2_UInt8_15_io_deq_bits : _T_4767 ? _Queue2_UInt8_14_io_deq_bits : _T_4766 ? _Queue2_UInt8_13_io_deq_bits : _T_4765 ? _Queue2_UInt8_12_io_deq_bits : _T_4764 ? _Queue2_UInt8_11_io_deq_bits : _T_4763 ? _Queue2_UInt8_10_io_deq_bits : _T_4762 ? _Queue2_UInt8_9_io_deq_bits : _T_4761 ? _Queue2_UInt8_8_io_deq_bits : _T_4760 ? _Queue2_UInt8_7_io_deq_bits : _T_4759 ? _Queue2_UInt8_6_io_deq_bits : _T_4758 ? _Queue2_UInt8_5_io_deq_bits : _T_4757 ? _Queue2_UInt8_4_io_deq_bits : _T_4756 ? _Queue2_UInt8_3_io_deq_bits : _T_4755 ? _Queue2_UInt8_2_io_deq_bits : _T_4754 ? _Queue2_UInt8_1_io_deq_bits : _T_4753 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_13 = _T_4784 ? _Queue2_UInt8_31_io_deq_valid : _T_4783 ? _Queue2_UInt8_30_io_deq_valid : _T_4782 ? _Queue2_UInt8_29_io_deq_valid : _T_4781 ? _Queue2_UInt8_28_io_deq_valid : _T_4780 ? _Queue2_UInt8_27_io_deq_valid : _T_4779 ? _Queue2_UInt8_26_io_deq_valid : _T_4778 ? _Queue2_UInt8_25_io_deq_valid : _T_4777 ? _Queue2_UInt8_24_io_deq_valid : _T_4776 ? _Queue2_UInt8_23_io_deq_valid : _T_4775 ? _Queue2_UInt8_22_io_deq_valid : _T_4774 ? _Queue2_UInt8_21_io_deq_valid : _T_4773 ? _Queue2_UInt8_20_io_deq_valid : _T_4772 ? _Queue2_UInt8_19_io_deq_valid : _T_4771 ? _Queue2_UInt8_18_io_deq_valid : _T_4770 ? _Queue2_UInt8_17_io_deq_valid : _T_4769 ? _Queue2_UInt8_16_io_deq_valid : _T_4768 ? _Queue2_UInt8_15_io_deq_valid : _T_4767 ? _Queue2_UInt8_14_io_deq_valid : _T_4766 ? _Queue2_UInt8_13_io_deq_valid : _T_4765 ? _Queue2_UInt8_12_io_deq_valid : _T_4764 ? _Queue2_UInt8_11_io_deq_valid : _T_4763 ? _Queue2_UInt8_10_io_deq_valid : _T_4762 ? _Queue2_UInt8_9_io_deq_valid : _T_4761 ? _Queue2_UInt8_8_io_deq_valid : _T_4760 ? _Queue2_UInt8_7_io_deq_valid : _T_4759 ? _Queue2_UInt8_6_io_deq_valid : _T_4758 ? _Queue2_UInt8_5_io_deq_valid : _T_4757 ? _Queue2_UInt8_4_io_deq_valid : _T_4756 ? _Queue2_UInt8_3_io_deq_valid : _T_4755 ? _Queue2_UInt8_2_io_deq_valid : _T_4754 ? _Queue2_UInt8_1_io_deq_valid : _T_4753 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_14 = _remapindex_T + 7'hE; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_104 = _remapindex_T_14 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_14 = _GEN_104[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_4785 = remapindex_14 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4786 = remapindex_14 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4787 = remapindex_14 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4788 = remapindex_14 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4789 = remapindex_14 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4790 = remapindex_14 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4791 = remapindex_14 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4792 = remapindex_14 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4793 = remapindex_14 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4794 = remapindex_14 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4795 = remapindex_14 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4796 = remapindex_14 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4797 = remapindex_14 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4798 = remapindex_14 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4799 = remapindex_14 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4800 = remapindex_14 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4801 = remapindex_14 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4802 = remapindex_14 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4803 = remapindex_14 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4804 = remapindex_14 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4805 = remapindex_14 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4806 = remapindex_14 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4807 = remapindex_14 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4808 = remapindex_14 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4809 = remapindex_14 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4810 = remapindex_14 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4811 = remapindex_14 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4812 = remapindex_14 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4813 = remapindex_14 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4814 = remapindex_14 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4815 = remapindex_14 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4816 = remapindex_14 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_14 = _T_4816 ? _Queue2_UInt8_31_io_deq_bits : _T_4815 ? _Queue2_UInt8_30_io_deq_bits : _T_4814 ? _Queue2_UInt8_29_io_deq_bits : _T_4813 ? _Queue2_UInt8_28_io_deq_bits : _T_4812 ? _Queue2_UInt8_27_io_deq_bits : _T_4811 ? _Queue2_UInt8_26_io_deq_bits : _T_4810 ? _Queue2_UInt8_25_io_deq_bits : _T_4809 ? _Queue2_UInt8_24_io_deq_bits : _T_4808 ? _Queue2_UInt8_23_io_deq_bits : _T_4807 ? _Queue2_UInt8_22_io_deq_bits : _T_4806 ? _Queue2_UInt8_21_io_deq_bits : _T_4805 ? _Queue2_UInt8_20_io_deq_bits : _T_4804 ? _Queue2_UInt8_19_io_deq_bits : _T_4803 ? _Queue2_UInt8_18_io_deq_bits : _T_4802 ? _Queue2_UInt8_17_io_deq_bits : _T_4801 ? _Queue2_UInt8_16_io_deq_bits : _T_4800 ? _Queue2_UInt8_15_io_deq_bits : _T_4799 ? _Queue2_UInt8_14_io_deq_bits : _T_4798 ? _Queue2_UInt8_13_io_deq_bits : _T_4797 ? _Queue2_UInt8_12_io_deq_bits : _T_4796 ? _Queue2_UInt8_11_io_deq_bits : _T_4795 ? _Queue2_UInt8_10_io_deq_bits : _T_4794 ? _Queue2_UInt8_9_io_deq_bits : _T_4793 ? _Queue2_UInt8_8_io_deq_bits : _T_4792 ? _Queue2_UInt8_7_io_deq_bits : _T_4791 ? _Queue2_UInt8_6_io_deq_bits : _T_4790 ? _Queue2_UInt8_5_io_deq_bits : _T_4789 ? _Queue2_UInt8_4_io_deq_bits : _T_4788 ? _Queue2_UInt8_3_io_deq_bits : _T_4787 ? _Queue2_UInt8_2_io_deq_bits : _T_4786 ? _Queue2_UInt8_1_io_deq_bits : _T_4785 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_14 = _T_4816 ? _Queue2_UInt8_31_io_deq_valid : _T_4815 ? _Queue2_UInt8_30_io_deq_valid : _T_4814 ? _Queue2_UInt8_29_io_deq_valid : _T_4813 ? _Queue2_UInt8_28_io_deq_valid : _T_4812 ? _Queue2_UInt8_27_io_deq_valid : _T_4811 ? _Queue2_UInt8_26_io_deq_valid : _T_4810 ? _Queue2_UInt8_25_io_deq_valid : _T_4809 ? _Queue2_UInt8_24_io_deq_valid : _T_4808 ? _Queue2_UInt8_23_io_deq_valid : _T_4807 ? _Queue2_UInt8_22_io_deq_valid : _T_4806 ? _Queue2_UInt8_21_io_deq_valid : _T_4805 ? _Queue2_UInt8_20_io_deq_valid : _T_4804 ? _Queue2_UInt8_19_io_deq_valid : _T_4803 ? _Queue2_UInt8_18_io_deq_valid : _T_4802 ? _Queue2_UInt8_17_io_deq_valid : _T_4801 ? _Queue2_UInt8_16_io_deq_valid : _T_4800 ? _Queue2_UInt8_15_io_deq_valid : _T_4799 ? _Queue2_UInt8_14_io_deq_valid : _T_4798 ? _Queue2_UInt8_13_io_deq_valid : _T_4797 ? _Queue2_UInt8_12_io_deq_valid : _T_4796 ? _Queue2_UInt8_11_io_deq_valid : _T_4795 ? _Queue2_UInt8_10_io_deq_valid : _T_4794 ? _Queue2_UInt8_9_io_deq_valid : _T_4793 ? _Queue2_UInt8_8_io_deq_valid : _T_4792 ? _Queue2_UInt8_7_io_deq_valid : _T_4791 ? _Queue2_UInt8_6_io_deq_valid : _T_4790 ? _Queue2_UInt8_5_io_deq_valid : _T_4789 ? _Queue2_UInt8_4_io_deq_valid : _T_4788 ? _Queue2_UInt8_3_io_deq_valid : _T_4787 ? _Queue2_UInt8_2_io_deq_valid : _T_4786 ? _Queue2_UInt8_1_io_deq_valid : _T_4785 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_15 = _remapindex_T + 7'hF; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_105 = _remapindex_T_15 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_15 = _GEN_105[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_4817 = remapindex_15 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4818 = remapindex_15 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4819 = remapindex_15 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4820 = remapindex_15 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4821 = remapindex_15 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4822 = remapindex_15 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4823 = remapindex_15 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4824 = remapindex_15 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4825 = remapindex_15 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4826 = remapindex_15 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4827 = remapindex_15 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4828 = remapindex_15 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4829 = remapindex_15 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4830 = remapindex_15 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4831 = remapindex_15 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4832 = remapindex_15 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4833 = remapindex_15 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4834 = remapindex_15 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4835 = remapindex_15 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4836 = remapindex_15 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4837 = remapindex_15 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4838 = remapindex_15 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4839 = remapindex_15 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4840 = remapindex_15 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4841 = remapindex_15 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4842 = remapindex_15 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4843 = remapindex_15 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4844 = remapindex_15 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4845 = remapindex_15 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4846 = remapindex_15 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4847 = remapindex_15 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4848 = remapindex_15 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_15 = _T_4848 ? _Queue2_UInt8_31_io_deq_bits : _T_4847 ? _Queue2_UInt8_30_io_deq_bits : _T_4846 ? _Queue2_UInt8_29_io_deq_bits : _T_4845 ? _Queue2_UInt8_28_io_deq_bits : _T_4844 ? _Queue2_UInt8_27_io_deq_bits : _T_4843 ? _Queue2_UInt8_26_io_deq_bits : _T_4842 ? _Queue2_UInt8_25_io_deq_bits : _T_4841 ? _Queue2_UInt8_24_io_deq_bits : _T_4840 ? _Queue2_UInt8_23_io_deq_bits : _T_4839 ? _Queue2_UInt8_22_io_deq_bits : _T_4838 ? _Queue2_UInt8_21_io_deq_bits : _T_4837 ? _Queue2_UInt8_20_io_deq_bits : _T_4836 ? _Queue2_UInt8_19_io_deq_bits : _T_4835 ? _Queue2_UInt8_18_io_deq_bits : _T_4834 ? _Queue2_UInt8_17_io_deq_bits : _T_4833 ? _Queue2_UInt8_16_io_deq_bits : _T_4832 ? _Queue2_UInt8_15_io_deq_bits : _T_4831 ? _Queue2_UInt8_14_io_deq_bits : _T_4830 ? _Queue2_UInt8_13_io_deq_bits : _T_4829 ? _Queue2_UInt8_12_io_deq_bits : _T_4828 ? _Queue2_UInt8_11_io_deq_bits : _T_4827 ? _Queue2_UInt8_10_io_deq_bits : _T_4826 ? _Queue2_UInt8_9_io_deq_bits : _T_4825 ? _Queue2_UInt8_8_io_deq_bits : _T_4824 ? _Queue2_UInt8_7_io_deq_bits : _T_4823 ? _Queue2_UInt8_6_io_deq_bits : _T_4822 ? _Queue2_UInt8_5_io_deq_bits : _T_4821 ? _Queue2_UInt8_4_io_deq_bits : _T_4820 ? _Queue2_UInt8_3_io_deq_bits : _T_4819 ? _Queue2_UInt8_2_io_deq_bits : _T_4818 ? _Queue2_UInt8_1_io_deq_bits : _T_4817 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_15 = _T_4848 ? _Queue2_UInt8_31_io_deq_valid : _T_4847 ? _Queue2_UInt8_30_io_deq_valid : _T_4846 ? _Queue2_UInt8_29_io_deq_valid : _T_4845 ? _Queue2_UInt8_28_io_deq_valid : _T_4844 ? _Queue2_UInt8_27_io_deq_valid : _T_4843 ? _Queue2_UInt8_26_io_deq_valid : _T_4842 ? _Queue2_UInt8_25_io_deq_valid : _T_4841 ? _Queue2_UInt8_24_io_deq_valid : _T_4840 ? _Queue2_UInt8_23_io_deq_valid : _T_4839 ? _Queue2_UInt8_22_io_deq_valid : _T_4838 ? _Queue2_UInt8_21_io_deq_valid : _T_4837 ? _Queue2_UInt8_20_io_deq_valid : _T_4836 ? _Queue2_UInt8_19_io_deq_valid : _T_4835 ? _Queue2_UInt8_18_io_deq_valid : _T_4834 ? _Queue2_UInt8_17_io_deq_valid : _T_4833 ? _Queue2_UInt8_16_io_deq_valid : _T_4832 ? _Queue2_UInt8_15_io_deq_valid : _T_4831 ? _Queue2_UInt8_14_io_deq_valid : _T_4830 ? _Queue2_UInt8_13_io_deq_valid : _T_4829 ? _Queue2_UInt8_12_io_deq_valid : _T_4828 ? _Queue2_UInt8_11_io_deq_valid : _T_4827 ? _Queue2_UInt8_10_io_deq_valid : _T_4826 ? _Queue2_UInt8_9_io_deq_valid : _T_4825 ? _Queue2_UInt8_8_io_deq_valid : _T_4824 ? _Queue2_UInt8_7_io_deq_valid : _T_4823 ? _Queue2_UInt8_6_io_deq_valid : _T_4822 ? _Queue2_UInt8_5_io_deq_valid : _T_4821 ? _Queue2_UInt8_4_io_deq_valid : _T_4820 ? _Queue2_UInt8_3_io_deq_valid : _T_4819 ? _Queue2_UInt8_2_io_deq_valid : _T_4818 ? _Queue2_UInt8_1_io_deq_valid : _T_4817 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_16 = _remapindex_T + 7'h10; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_106 = _remapindex_T_16 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_16 = _GEN_106[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_4849 = remapindex_16 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4850 = remapindex_16 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4851 = remapindex_16 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4852 = remapindex_16 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4853 = remapindex_16 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4854 = remapindex_16 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4855 = remapindex_16 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4856 = remapindex_16 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4857 = remapindex_16 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4858 = remapindex_16 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4859 = remapindex_16 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4860 = remapindex_16 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4861 = remapindex_16 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4862 = remapindex_16 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4863 = remapindex_16 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4864 = remapindex_16 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4865 = remapindex_16 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4866 = remapindex_16 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4867 = remapindex_16 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4868 = remapindex_16 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4869 = remapindex_16 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4870 = remapindex_16 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4871 = remapindex_16 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4872 = remapindex_16 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4873 = remapindex_16 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4874 = remapindex_16 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4875 = remapindex_16 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4876 = remapindex_16 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4877 = remapindex_16 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4878 = remapindex_16 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4879 = remapindex_16 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4880 = remapindex_16 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_16 = _T_4880 ? _Queue2_UInt8_31_io_deq_bits : _T_4879 ? _Queue2_UInt8_30_io_deq_bits : _T_4878 ? _Queue2_UInt8_29_io_deq_bits : _T_4877 ? _Queue2_UInt8_28_io_deq_bits : _T_4876 ? _Queue2_UInt8_27_io_deq_bits : _T_4875 ? _Queue2_UInt8_26_io_deq_bits : _T_4874 ? _Queue2_UInt8_25_io_deq_bits : _T_4873 ? _Queue2_UInt8_24_io_deq_bits : _T_4872 ? _Queue2_UInt8_23_io_deq_bits : _T_4871 ? _Queue2_UInt8_22_io_deq_bits : _T_4870 ? _Queue2_UInt8_21_io_deq_bits : _T_4869 ? _Queue2_UInt8_20_io_deq_bits : _T_4868 ? _Queue2_UInt8_19_io_deq_bits : _T_4867 ? _Queue2_UInt8_18_io_deq_bits : _T_4866 ? _Queue2_UInt8_17_io_deq_bits : _T_4865 ? _Queue2_UInt8_16_io_deq_bits : _T_4864 ? _Queue2_UInt8_15_io_deq_bits : _T_4863 ? _Queue2_UInt8_14_io_deq_bits : _T_4862 ? _Queue2_UInt8_13_io_deq_bits : _T_4861 ? _Queue2_UInt8_12_io_deq_bits : _T_4860 ? _Queue2_UInt8_11_io_deq_bits : _T_4859 ? _Queue2_UInt8_10_io_deq_bits : _T_4858 ? _Queue2_UInt8_9_io_deq_bits : _T_4857 ? _Queue2_UInt8_8_io_deq_bits : _T_4856 ? _Queue2_UInt8_7_io_deq_bits : _T_4855 ? _Queue2_UInt8_6_io_deq_bits : _T_4854 ? _Queue2_UInt8_5_io_deq_bits : _T_4853 ? _Queue2_UInt8_4_io_deq_bits : _T_4852 ? _Queue2_UInt8_3_io_deq_bits : _T_4851 ? _Queue2_UInt8_2_io_deq_bits : _T_4850 ? _Queue2_UInt8_1_io_deq_bits : _T_4849 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_16 = _T_4880 ? _Queue2_UInt8_31_io_deq_valid : _T_4879 ? _Queue2_UInt8_30_io_deq_valid : _T_4878 ? _Queue2_UInt8_29_io_deq_valid : _T_4877 ? _Queue2_UInt8_28_io_deq_valid : _T_4876 ? _Queue2_UInt8_27_io_deq_valid : _T_4875 ? _Queue2_UInt8_26_io_deq_valid : _T_4874 ? _Queue2_UInt8_25_io_deq_valid : _T_4873 ? _Queue2_UInt8_24_io_deq_valid : _T_4872 ? _Queue2_UInt8_23_io_deq_valid : _T_4871 ? _Queue2_UInt8_22_io_deq_valid : _T_4870 ? _Queue2_UInt8_21_io_deq_valid : _T_4869 ? _Queue2_UInt8_20_io_deq_valid : _T_4868 ? _Queue2_UInt8_19_io_deq_valid : _T_4867 ? _Queue2_UInt8_18_io_deq_valid : _T_4866 ? _Queue2_UInt8_17_io_deq_valid : _T_4865 ? _Queue2_UInt8_16_io_deq_valid : _T_4864 ? _Queue2_UInt8_15_io_deq_valid : _T_4863 ? _Queue2_UInt8_14_io_deq_valid : _T_4862 ? _Queue2_UInt8_13_io_deq_valid : _T_4861 ? _Queue2_UInt8_12_io_deq_valid : _T_4860 ? _Queue2_UInt8_11_io_deq_valid : _T_4859 ? _Queue2_UInt8_10_io_deq_valid : _T_4858 ? _Queue2_UInt8_9_io_deq_valid : _T_4857 ? _Queue2_UInt8_8_io_deq_valid : _T_4856 ? _Queue2_UInt8_7_io_deq_valid : _T_4855 ? _Queue2_UInt8_6_io_deq_valid : _T_4854 ? _Queue2_UInt8_5_io_deq_valid : _T_4853 ? _Queue2_UInt8_4_io_deq_valid : _T_4852 ? _Queue2_UInt8_3_io_deq_valid : _T_4851 ? _Queue2_UInt8_2_io_deq_valid : _T_4850 ? _Queue2_UInt8_1_io_deq_valid : _T_4849 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_17 = _remapindex_T + 7'h11; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_107 = _remapindex_T_17 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_17 = _GEN_107[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_4881 = remapindex_17 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4882 = remapindex_17 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4883 = remapindex_17 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4884 = remapindex_17 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4885 = remapindex_17 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4886 = remapindex_17 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4887 = remapindex_17 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4888 = remapindex_17 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4889 = remapindex_17 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4890 = remapindex_17 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4891 = remapindex_17 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4892 = remapindex_17 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4893 = remapindex_17 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4894 = remapindex_17 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4895 = remapindex_17 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4896 = remapindex_17 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4897 = remapindex_17 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4898 = remapindex_17 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4899 = remapindex_17 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4900 = remapindex_17 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4901 = remapindex_17 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4902 = remapindex_17 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4903 = remapindex_17 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4904 = remapindex_17 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4905 = remapindex_17 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4906 = remapindex_17 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4907 = remapindex_17 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4908 = remapindex_17 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4909 = remapindex_17 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4910 = remapindex_17 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4911 = remapindex_17 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4912 = remapindex_17 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_17 = _T_4912 ? _Queue2_UInt8_31_io_deq_bits : _T_4911 ? _Queue2_UInt8_30_io_deq_bits : _T_4910 ? _Queue2_UInt8_29_io_deq_bits : _T_4909 ? _Queue2_UInt8_28_io_deq_bits : _T_4908 ? _Queue2_UInt8_27_io_deq_bits : _T_4907 ? _Queue2_UInt8_26_io_deq_bits : _T_4906 ? _Queue2_UInt8_25_io_deq_bits : _T_4905 ? _Queue2_UInt8_24_io_deq_bits : _T_4904 ? _Queue2_UInt8_23_io_deq_bits : _T_4903 ? _Queue2_UInt8_22_io_deq_bits : _T_4902 ? _Queue2_UInt8_21_io_deq_bits : _T_4901 ? _Queue2_UInt8_20_io_deq_bits : _T_4900 ? _Queue2_UInt8_19_io_deq_bits : _T_4899 ? _Queue2_UInt8_18_io_deq_bits : _T_4898 ? _Queue2_UInt8_17_io_deq_bits : _T_4897 ? _Queue2_UInt8_16_io_deq_bits : _T_4896 ? _Queue2_UInt8_15_io_deq_bits : _T_4895 ? _Queue2_UInt8_14_io_deq_bits : _T_4894 ? _Queue2_UInt8_13_io_deq_bits : _T_4893 ? _Queue2_UInt8_12_io_deq_bits : _T_4892 ? _Queue2_UInt8_11_io_deq_bits : _T_4891 ? _Queue2_UInt8_10_io_deq_bits : _T_4890 ? _Queue2_UInt8_9_io_deq_bits : _T_4889 ? _Queue2_UInt8_8_io_deq_bits : _T_4888 ? _Queue2_UInt8_7_io_deq_bits : _T_4887 ? _Queue2_UInt8_6_io_deq_bits : _T_4886 ? _Queue2_UInt8_5_io_deq_bits : _T_4885 ? _Queue2_UInt8_4_io_deq_bits : _T_4884 ? _Queue2_UInt8_3_io_deq_bits : _T_4883 ? _Queue2_UInt8_2_io_deq_bits : _T_4882 ? _Queue2_UInt8_1_io_deq_bits : _T_4881 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_17 = _T_4912 ? _Queue2_UInt8_31_io_deq_valid : _T_4911 ? _Queue2_UInt8_30_io_deq_valid : _T_4910 ? _Queue2_UInt8_29_io_deq_valid : _T_4909 ? _Queue2_UInt8_28_io_deq_valid : _T_4908 ? _Queue2_UInt8_27_io_deq_valid : _T_4907 ? _Queue2_UInt8_26_io_deq_valid : _T_4906 ? _Queue2_UInt8_25_io_deq_valid : _T_4905 ? _Queue2_UInt8_24_io_deq_valid : _T_4904 ? _Queue2_UInt8_23_io_deq_valid : _T_4903 ? _Queue2_UInt8_22_io_deq_valid : _T_4902 ? _Queue2_UInt8_21_io_deq_valid : _T_4901 ? _Queue2_UInt8_20_io_deq_valid : _T_4900 ? _Queue2_UInt8_19_io_deq_valid : _T_4899 ? _Queue2_UInt8_18_io_deq_valid : _T_4898 ? _Queue2_UInt8_17_io_deq_valid : _T_4897 ? _Queue2_UInt8_16_io_deq_valid : _T_4896 ? _Queue2_UInt8_15_io_deq_valid : _T_4895 ? _Queue2_UInt8_14_io_deq_valid : _T_4894 ? _Queue2_UInt8_13_io_deq_valid : _T_4893 ? _Queue2_UInt8_12_io_deq_valid : _T_4892 ? _Queue2_UInt8_11_io_deq_valid : _T_4891 ? _Queue2_UInt8_10_io_deq_valid : _T_4890 ? _Queue2_UInt8_9_io_deq_valid : _T_4889 ? _Queue2_UInt8_8_io_deq_valid : _T_4888 ? _Queue2_UInt8_7_io_deq_valid : _T_4887 ? _Queue2_UInt8_6_io_deq_valid : _T_4886 ? _Queue2_UInt8_5_io_deq_valid : _T_4885 ? _Queue2_UInt8_4_io_deq_valid : _T_4884 ? _Queue2_UInt8_3_io_deq_valid : _T_4883 ? _Queue2_UInt8_2_io_deq_valid : _T_4882 ? _Queue2_UInt8_1_io_deq_valid : _T_4881 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_18 = _remapindex_T + 7'h12; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_108 = _remapindex_T_18 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_18 = _GEN_108[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_4913 = remapindex_18 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4914 = remapindex_18 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4915 = remapindex_18 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4916 = remapindex_18 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4917 = remapindex_18 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4918 = remapindex_18 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4919 = remapindex_18 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4920 = remapindex_18 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4921 = remapindex_18 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4922 = remapindex_18 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4923 = remapindex_18 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4924 = remapindex_18 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4925 = remapindex_18 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4926 = remapindex_18 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4927 = remapindex_18 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4928 = remapindex_18 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4929 = remapindex_18 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4930 = remapindex_18 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4931 = remapindex_18 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4932 = remapindex_18 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4933 = remapindex_18 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4934 = remapindex_18 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4935 = remapindex_18 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4936 = remapindex_18 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4937 = remapindex_18 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4938 = remapindex_18 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4939 = remapindex_18 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4940 = remapindex_18 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4941 = remapindex_18 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4942 = remapindex_18 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4943 = remapindex_18 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4944 = remapindex_18 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_18 = _T_4944 ? _Queue2_UInt8_31_io_deq_bits : _T_4943 ? _Queue2_UInt8_30_io_deq_bits : _T_4942 ? _Queue2_UInt8_29_io_deq_bits : _T_4941 ? _Queue2_UInt8_28_io_deq_bits : _T_4940 ? _Queue2_UInt8_27_io_deq_bits : _T_4939 ? _Queue2_UInt8_26_io_deq_bits : _T_4938 ? _Queue2_UInt8_25_io_deq_bits : _T_4937 ? _Queue2_UInt8_24_io_deq_bits : _T_4936 ? _Queue2_UInt8_23_io_deq_bits : _T_4935 ? _Queue2_UInt8_22_io_deq_bits : _T_4934 ? _Queue2_UInt8_21_io_deq_bits : _T_4933 ? _Queue2_UInt8_20_io_deq_bits : _T_4932 ? _Queue2_UInt8_19_io_deq_bits : _T_4931 ? _Queue2_UInt8_18_io_deq_bits : _T_4930 ? _Queue2_UInt8_17_io_deq_bits : _T_4929 ? _Queue2_UInt8_16_io_deq_bits : _T_4928 ? _Queue2_UInt8_15_io_deq_bits : _T_4927 ? _Queue2_UInt8_14_io_deq_bits : _T_4926 ? _Queue2_UInt8_13_io_deq_bits : _T_4925 ? _Queue2_UInt8_12_io_deq_bits : _T_4924 ? _Queue2_UInt8_11_io_deq_bits : _T_4923 ? _Queue2_UInt8_10_io_deq_bits : _T_4922 ? _Queue2_UInt8_9_io_deq_bits : _T_4921 ? _Queue2_UInt8_8_io_deq_bits : _T_4920 ? _Queue2_UInt8_7_io_deq_bits : _T_4919 ? _Queue2_UInt8_6_io_deq_bits : _T_4918 ? _Queue2_UInt8_5_io_deq_bits : _T_4917 ? _Queue2_UInt8_4_io_deq_bits : _T_4916 ? _Queue2_UInt8_3_io_deq_bits : _T_4915 ? _Queue2_UInt8_2_io_deq_bits : _T_4914 ? _Queue2_UInt8_1_io_deq_bits : _T_4913 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_18 = _T_4944 ? _Queue2_UInt8_31_io_deq_valid : _T_4943 ? _Queue2_UInt8_30_io_deq_valid : _T_4942 ? _Queue2_UInt8_29_io_deq_valid : _T_4941 ? _Queue2_UInt8_28_io_deq_valid : _T_4940 ? _Queue2_UInt8_27_io_deq_valid : _T_4939 ? _Queue2_UInt8_26_io_deq_valid : _T_4938 ? _Queue2_UInt8_25_io_deq_valid : _T_4937 ? _Queue2_UInt8_24_io_deq_valid : _T_4936 ? _Queue2_UInt8_23_io_deq_valid : _T_4935 ? _Queue2_UInt8_22_io_deq_valid : _T_4934 ? _Queue2_UInt8_21_io_deq_valid : _T_4933 ? _Queue2_UInt8_20_io_deq_valid : _T_4932 ? _Queue2_UInt8_19_io_deq_valid : _T_4931 ? _Queue2_UInt8_18_io_deq_valid : _T_4930 ? _Queue2_UInt8_17_io_deq_valid : _T_4929 ? _Queue2_UInt8_16_io_deq_valid : _T_4928 ? _Queue2_UInt8_15_io_deq_valid : _T_4927 ? _Queue2_UInt8_14_io_deq_valid : _T_4926 ? _Queue2_UInt8_13_io_deq_valid : _T_4925 ? _Queue2_UInt8_12_io_deq_valid : _T_4924 ? _Queue2_UInt8_11_io_deq_valid : _T_4923 ? _Queue2_UInt8_10_io_deq_valid : _T_4922 ? _Queue2_UInt8_9_io_deq_valid : _T_4921 ? _Queue2_UInt8_8_io_deq_valid : _T_4920 ? _Queue2_UInt8_7_io_deq_valid : _T_4919 ? _Queue2_UInt8_6_io_deq_valid : _T_4918 ? _Queue2_UInt8_5_io_deq_valid : _T_4917 ? _Queue2_UInt8_4_io_deq_valid : _T_4916 ? _Queue2_UInt8_3_io_deq_valid : _T_4915 ? _Queue2_UInt8_2_io_deq_valid : _T_4914 ? _Queue2_UInt8_1_io_deq_valid : _T_4913 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_19 = _remapindex_T + 7'h13; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_109 = _remapindex_T_19 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_19 = _GEN_109[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_4945 = remapindex_19 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4946 = remapindex_19 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4947 = remapindex_19 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4948 = remapindex_19 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4949 = remapindex_19 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4950 = remapindex_19 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4951 = remapindex_19 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4952 = remapindex_19 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4953 = remapindex_19 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4954 = remapindex_19 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4955 = remapindex_19 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4956 = remapindex_19 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4957 = remapindex_19 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4958 = remapindex_19 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4959 = remapindex_19 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4960 = remapindex_19 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4961 = remapindex_19 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4962 = remapindex_19 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4963 = remapindex_19 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4964 = remapindex_19 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4965 = remapindex_19 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4966 = remapindex_19 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4967 = remapindex_19 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4968 = remapindex_19 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4969 = remapindex_19 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4970 = remapindex_19 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4971 = remapindex_19 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4972 = remapindex_19 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4973 = remapindex_19 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4974 = remapindex_19 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4975 = remapindex_19 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4976 = remapindex_19 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_19 = _T_4976 ? _Queue2_UInt8_31_io_deq_bits : _T_4975 ? _Queue2_UInt8_30_io_deq_bits : _T_4974 ? _Queue2_UInt8_29_io_deq_bits : _T_4973 ? _Queue2_UInt8_28_io_deq_bits : _T_4972 ? _Queue2_UInt8_27_io_deq_bits : _T_4971 ? _Queue2_UInt8_26_io_deq_bits : _T_4970 ? _Queue2_UInt8_25_io_deq_bits : _T_4969 ? _Queue2_UInt8_24_io_deq_bits : _T_4968 ? _Queue2_UInt8_23_io_deq_bits : _T_4967 ? _Queue2_UInt8_22_io_deq_bits : _T_4966 ? _Queue2_UInt8_21_io_deq_bits : _T_4965 ? _Queue2_UInt8_20_io_deq_bits : _T_4964 ? _Queue2_UInt8_19_io_deq_bits : _T_4963 ? _Queue2_UInt8_18_io_deq_bits : _T_4962 ? _Queue2_UInt8_17_io_deq_bits : _T_4961 ? _Queue2_UInt8_16_io_deq_bits : _T_4960 ? _Queue2_UInt8_15_io_deq_bits : _T_4959 ? _Queue2_UInt8_14_io_deq_bits : _T_4958 ? _Queue2_UInt8_13_io_deq_bits : _T_4957 ? _Queue2_UInt8_12_io_deq_bits : _T_4956 ? _Queue2_UInt8_11_io_deq_bits : _T_4955 ? _Queue2_UInt8_10_io_deq_bits : _T_4954 ? _Queue2_UInt8_9_io_deq_bits : _T_4953 ? _Queue2_UInt8_8_io_deq_bits : _T_4952 ? _Queue2_UInt8_7_io_deq_bits : _T_4951 ? _Queue2_UInt8_6_io_deq_bits : _T_4950 ? _Queue2_UInt8_5_io_deq_bits : _T_4949 ? _Queue2_UInt8_4_io_deq_bits : _T_4948 ? _Queue2_UInt8_3_io_deq_bits : _T_4947 ? _Queue2_UInt8_2_io_deq_bits : _T_4946 ? _Queue2_UInt8_1_io_deq_bits : _T_4945 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_19 = _T_4976 ? _Queue2_UInt8_31_io_deq_valid : _T_4975 ? _Queue2_UInt8_30_io_deq_valid : _T_4974 ? _Queue2_UInt8_29_io_deq_valid : _T_4973 ? _Queue2_UInt8_28_io_deq_valid : _T_4972 ? _Queue2_UInt8_27_io_deq_valid : _T_4971 ? _Queue2_UInt8_26_io_deq_valid : _T_4970 ? _Queue2_UInt8_25_io_deq_valid : _T_4969 ? _Queue2_UInt8_24_io_deq_valid : _T_4968 ? _Queue2_UInt8_23_io_deq_valid : _T_4967 ? _Queue2_UInt8_22_io_deq_valid : _T_4966 ? _Queue2_UInt8_21_io_deq_valid : _T_4965 ? _Queue2_UInt8_20_io_deq_valid : _T_4964 ? _Queue2_UInt8_19_io_deq_valid : _T_4963 ? _Queue2_UInt8_18_io_deq_valid : _T_4962 ? _Queue2_UInt8_17_io_deq_valid : _T_4961 ? _Queue2_UInt8_16_io_deq_valid : _T_4960 ? _Queue2_UInt8_15_io_deq_valid : _T_4959 ? _Queue2_UInt8_14_io_deq_valid : _T_4958 ? _Queue2_UInt8_13_io_deq_valid : _T_4957 ? _Queue2_UInt8_12_io_deq_valid : _T_4956 ? _Queue2_UInt8_11_io_deq_valid : _T_4955 ? _Queue2_UInt8_10_io_deq_valid : _T_4954 ? _Queue2_UInt8_9_io_deq_valid : _T_4953 ? _Queue2_UInt8_8_io_deq_valid : _T_4952 ? _Queue2_UInt8_7_io_deq_valid : _T_4951 ? _Queue2_UInt8_6_io_deq_valid : _T_4950 ? _Queue2_UInt8_5_io_deq_valid : _T_4949 ? _Queue2_UInt8_4_io_deq_valid : _T_4948 ? _Queue2_UInt8_3_io_deq_valid : _T_4947 ? _Queue2_UInt8_2_io_deq_valid : _T_4946 ? _Queue2_UInt8_1_io_deq_valid : _T_4945 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_20 = _remapindex_T + 7'h14; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_110 = _remapindex_T_20 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_20 = _GEN_110[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_4977 = remapindex_20 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4978 = remapindex_20 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4979 = remapindex_20 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4980 = remapindex_20 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4981 = remapindex_20 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4982 = remapindex_20 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4983 = remapindex_20 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4984 = remapindex_20 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4985 = remapindex_20 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4986 = remapindex_20 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4987 = remapindex_20 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4988 = remapindex_20 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4989 = remapindex_20 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4990 = remapindex_20 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4991 = remapindex_20 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4992 = remapindex_20 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4993 = remapindex_20 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4994 = remapindex_20 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4995 = remapindex_20 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4996 = remapindex_20 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4997 = remapindex_20 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4998 = remapindex_20 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_4999 = remapindex_20 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5000 = remapindex_20 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5001 = remapindex_20 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5002 = remapindex_20 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5003 = remapindex_20 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5004 = remapindex_20 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5005 = remapindex_20 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5006 = remapindex_20 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5007 = remapindex_20 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5008 = remapindex_20 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_20 = _T_5008 ? _Queue2_UInt8_31_io_deq_bits : _T_5007 ? _Queue2_UInt8_30_io_deq_bits : _T_5006 ? _Queue2_UInt8_29_io_deq_bits : _T_5005 ? _Queue2_UInt8_28_io_deq_bits : _T_5004 ? _Queue2_UInt8_27_io_deq_bits : _T_5003 ? _Queue2_UInt8_26_io_deq_bits : _T_5002 ? _Queue2_UInt8_25_io_deq_bits : _T_5001 ? _Queue2_UInt8_24_io_deq_bits : _T_5000 ? _Queue2_UInt8_23_io_deq_bits : _T_4999 ? _Queue2_UInt8_22_io_deq_bits : _T_4998 ? _Queue2_UInt8_21_io_deq_bits : _T_4997 ? _Queue2_UInt8_20_io_deq_bits : _T_4996 ? _Queue2_UInt8_19_io_deq_bits : _T_4995 ? _Queue2_UInt8_18_io_deq_bits : _T_4994 ? _Queue2_UInt8_17_io_deq_bits : _T_4993 ? _Queue2_UInt8_16_io_deq_bits : _T_4992 ? _Queue2_UInt8_15_io_deq_bits : _T_4991 ? _Queue2_UInt8_14_io_deq_bits : _T_4990 ? _Queue2_UInt8_13_io_deq_bits : _T_4989 ? _Queue2_UInt8_12_io_deq_bits : _T_4988 ? _Queue2_UInt8_11_io_deq_bits : _T_4987 ? _Queue2_UInt8_10_io_deq_bits : _T_4986 ? _Queue2_UInt8_9_io_deq_bits : _T_4985 ? _Queue2_UInt8_8_io_deq_bits : _T_4984 ? _Queue2_UInt8_7_io_deq_bits : _T_4983 ? _Queue2_UInt8_6_io_deq_bits : _T_4982 ? _Queue2_UInt8_5_io_deq_bits : _T_4981 ? _Queue2_UInt8_4_io_deq_bits : _T_4980 ? _Queue2_UInt8_3_io_deq_bits : _T_4979 ? _Queue2_UInt8_2_io_deq_bits : _T_4978 ? _Queue2_UInt8_1_io_deq_bits : _T_4977 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_20 = _T_5008 ? _Queue2_UInt8_31_io_deq_valid : _T_5007 ? _Queue2_UInt8_30_io_deq_valid : _T_5006 ? _Queue2_UInt8_29_io_deq_valid : _T_5005 ? _Queue2_UInt8_28_io_deq_valid : _T_5004 ? _Queue2_UInt8_27_io_deq_valid : _T_5003 ? _Queue2_UInt8_26_io_deq_valid : _T_5002 ? _Queue2_UInt8_25_io_deq_valid : _T_5001 ? _Queue2_UInt8_24_io_deq_valid : _T_5000 ? _Queue2_UInt8_23_io_deq_valid : _T_4999 ? _Queue2_UInt8_22_io_deq_valid : _T_4998 ? _Queue2_UInt8_21_io_deq_valid : _T_4997 ? _Queue2_UInt8_20_io_deq_valid : _T_4996 ? _Queue2_UInt8_19_io_deq_valid : _T_4995 ? _Queue2_UInt8_18_io_deq_valid : _T_4994 ? _Queue2_UInt8_17_io_deq_valid : _T_4993 ? _Queue2_UInt8_16_io_deq_valid : _T_4992 ? _Queue2_UInt8_15_io_deq_valid : _T_4991 ? _Queue2_UInt8_14_io_deq_valid : _T_4990 ? _Queue2_UInt8_13_io_deq_valid : _T_4989 ? _Queue2_UInt8_12_io_deq_valid : _T_4988 ? _Queue2_UInt8_11_io_deq_valid : _T_4987 ? _Queue2_UInt8_10_io_deq_valid : _T_4986 ? _Queue2_UInt8_9_io_deq_valid : _T_4985 ? _Queue2_UInt8_8_io_deq_valid : _T_4984 ? _Queue2_UInt8_7_io_deq_valid : _T_4983 ? _Queue2_UInt8_6_io_deq_valid : _T_4982 ? _Queue2_UInt8_5_io_deq_valid : _T_4981 ? _Queue2_UInt8_4_io_deq_valid : _T_4980 ? _Queue2_UInt8_3_io_deq_valid : _T_4979 ? _Queue2_UInt8_2_io_deq_valid : _T_4978 ? _Queue2_UInt8_1_io_deq_valid : _T_4977 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_21 = _remapindex_T + 7'h15; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_111 = _remapindex_T_21 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_21 = _GEN_111[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_5009 = remapindex_21 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5010 = remapindex_21 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5011 = remapindex_21 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5012 = remapindex_21 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5013 = remapindex_21 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5014 = remapindex_21 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5015 = remapindex_21 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5016 = remapindex_21 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5017 = remapindex_21 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5018 = remapindex_21 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5019 = remapindex_21 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5020 = remapindex_21 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5021 = remapindex_21 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5022 = remapindex_21 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5023 = remapindex_21 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5024 = remapindex_21 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5025 = remapindex_21 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5026 = remapindex_21 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5027 = remapindex_21 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5028 = remapindex_21 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5029 = remapindex_21 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5030 = remapindex_21 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5031 = remapindex_21 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5032 = remapindex_21 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5033 = remapindex_21 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5034 = remapindex_21 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5035 = remapindex_21 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5036 = remapindex_21 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5037 = remapindex_21 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5038 = remapindex_21 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5039 = remapindex_21 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5040 = remapindex_21 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_21 = _T_5040 ? _Queue2_UInt8_31_io_deq_bits : _T_5039 ? _Queue2_UInt8_30_io_deq_bits : _T_5038 ? _Queue2_UInt8_29_io_deq_bits : _T_5037 ? _Queue2_UInt8_28_io_deq_bits : _T_5036 ? _Queue2_UInt8_27_io_deq_bits : _T_5035 ? _Queue2_UInt8_26_io_deq_bits : _T_5034 ? _Queue2_UInt8_25_io_deq_bits : _T_5033 ? _Queue2_UInt8_24_io_deq_bits : _T_5032 ? _Queue2_UInt8_23_io_deq_bits : _T_5031 ? _Queue2_UInt8_22_io_deq_bits : _T_5030 ? _Queue2_UInt8_21_io_deq_bits : _T_5029 ? _Queue2_UInt8_20_io_deq_bits : _T_5028 ? _Queue2_UInt8_19_io_deq_bits : _T_5027 ? _Queue2_UInt8_18_io_deq_bits : _T_5026 ? _Queue2_UInt8_17_io_deq_bits : _T_5025 ? _Queue2_UInt8_16_io_deq_bits : _T_5024 ? _Queue2_UInt8_15_io_deq_bits : _T_5023 ? _Queue2_UInt8_14_io_deq_bits : _T_5022 ? _Queue2_UInt8_13_io_deq_bits : _T_5021 ? _Queue2_UInt8_12_io_deq_bits : _T_5020 ? _Queue2_UInt8_11_io_deq_bits : _T_5019 ? _Queue2_UInt8_10_io_deq_bits : _T_5018 ? _Queue2_UInt8_9_io_deq_bits : _T_5017 ? _Queue2_UInt8_8_io_deq_bits : _T_5016 ? _Queue2_UInt8_7_io_deq_bits : _T_5015 ? _Queue2_UInt8_6_io_deq_bits : _T_5014 ? _Queue2_UInt8_5_io_deq_bits : _T_5013 ? _Queue2_UInt8_4_io_deq_bits : _T_5012 ? _Queue2_UInt8_3_io_deq_bits : _T_5011 ? _Queue2_UInt8_2_io_deq_bits : _T_5010 ? _Queue2_UInt8_1_io_deq_bits : _T_5009 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_21 = _T_5040 ? _Queue2_UInt8_31_io_deq_valid : _T_5039 ? _Queue2_UInt8_30_io_deq_valid : _T_5038 ? _Queue2_UInt8_29_io_deq_valid : _T_5037 ? _Queue2_UInt8_28_io_deq_valid : _T_5036 ? _Queue2_UInt8_27_io_deq_valid : _T_5035 ? _Queue2_UInt8_26_io_deq_valid : _T_5034 ? _Queue2_UInt8_25_io_deq_valid : _T_5033 ? _Queue2_UInt8_24_io_deq_valid : _T_5032 ? _Queue2_UInt8_23_io_deq_valid : _T_5031 ? _Queue2_UInt8_22_io_deq_valid : _T_5030 ? _Queue2_UInt8_21_io_deq_valid : _T_5029 ? _Queue2_UInt8_20_io_deq_valid : _T_5028 ? _Queue2_UInt8_19_io_deq_valid : _T_5027 ? _Queue2_UInt8_18_io_deq_valid : _T_5026 ? _Queue2_UInt8_17_io_deq_valid : _T_5025 ? _Queue2_UInt8_16_io_deq_valid : _T_5024 ? _Queue2_UInt8_15_io_deq_valid : _T_5023 ? _Queue2_UInt8_14_io_deq_valid : _T_5022 ? _Queue2_UInt8_13_io_deq_valid : _T_5021 ? _Queue2_UInt8_12_io_deq_valid : _T_5020 ? _Queue2_UInt8_11_io_deq_valid : _T_5019 ? _Queue2_UInt8_10_io_deq_valid : _T_5018 ? _Queue2_UInt8_9_io_deq_valid : _T_5017 ? _Queue2_UInt8_8_io_deq_valid : _T_5016 ? _Queue2_UInt8_7_io_deq_valid : _T_5015 ? _Queue2_UInt8_6_io_deq_valid : _T_5014 ? _Queue2_UInt8_5_io_deq_valid : _T_5013 ? _Queue2_UInt8_4_io_deq_valid : _T_5012 ? _Queue2_UInt8_3_io_deq_valid : _T_5011 ? _Queue2_UInt8_2_io_deq_valid : _T_5010 ? _Queue2_UInt8_1_io_deq_valid : _T_5009 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_22 = _remapindex_T + 7'h16; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_112 = _remapindex_T_22 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_22 = _GEN_112[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_5041 = remapindex_22 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5042 = remapindex_22 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5043 = remapindex_22 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5044 = remapindex_22 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5045 = remapindex_22 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5046 = remapindex_22 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5047 = remapindex_22 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5048 = remapindex_22 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5049 = remapindex_22 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5050 = remapindex_22 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5051 = remapindex_22 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5052 = remapindex_22 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5053 = remapindex_22 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5054 = remapindex_22 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5055 = remapindex_22 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5056 = remapindex_22 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5057 = remapindex_22 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5058 = remapindex_22 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5059 = remapindex_22 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5060 = remapindex_22 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5061 = remapindex_22 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5062 = remapindex_22 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5063 = remapindex_22 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5064 = remapindex_22 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5065 = remapindex_22 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5066 = remapindex_22 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5067 = remapindex_22 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5068 = remapindex_22 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5069 = remapindex_22 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5070 = remapindex_22 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5071 = remapindex_22 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5072 = remapindex_22 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_22 = _T_5072 ? _Queue2_UInt8_31_io_deq_bits : _T_5071 ? _Queue2_UInt8_30_io_deq_bits : _T_5070 ? _Queue2_UInt8_29_io_deq_bits : _T_5069 ? _Queue2_UInt8_28_io_deq_bits : _T_5068 ? _Queue2_UInt8_27_io_deq_bits : _T_5067 ? _Queue2_UInt8_26_io_deq_bits : _T_5066 ? _Queue2_UInt8_25_io_deq_bits : _T_5065 ? _Queue2_UInt8_24_io_deq_bits : _T_5064 ? _Queue2_UInt8_23_io_deq_bits : _T_5063 ? _Queue2_UInt8_22_io_deq_bits : _T_5062 ? _Queue2_UInt8_21_io_deq_bits : _T_5061 ? _Queue2_UInt8_20_io_deq_bits : _T_5060 ? _Queue2_UInt8_19_io_deq_bits : _T_5059 ? _Queue2_UInt8_18_io_deq_bits : _T_5058 ? _Queue2_UInt8_17_io_deq_bits : _T_5057 ? _Queue2_UInt8_16_io_deq_bits : _T_5056 ? _Queue2_UInt8_15_io_deq_bits : _T_5055 ? _Queue2_UInt8_14_io_deq_bits : _T_5054 ? _Queue2_UInt8_13_io_deq_bits : _T_5053 ? _Queue2_UInt8_12_io_deq_bits : _T_5052 ? _Queue2_UInt8_11_io_deq_bits : _T_5051 ? _Queue2_UInt8_10_io_deq_bits : _T_5050 ? _Queue2_UInt8_9_io_deq_bits : _T_5049 ? _Queue2_UInt8_8_io_deq_bits : _T_5048 ? _Queue2_UInt8_7_io_deq_bits : _T_5047 ? _Queue2_UInt8_6_io_deq_bits : _T_5046 ? _Queue2_UInt8_5_io_deq_bits : _T_5045 ? _Queue2_UInt8_4_io_deq_bits : _T_5044 ? _Queue2_UInt8_3_io_deq_bits : _T_5043 ? _Queue2_UInt8_2_io_deq_bits : _T_5042 ? _Queue2_UInt8_1_io_deq_bits : _T_5041 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_22 = _T_5072 ? _Queue2_UInt8_31_io_deq_valid : _T_5071 ? _Queue2_UInt8_30_io_deq_valid : _T_5070 ? _Queue2_UInt8_29_io_deq_valid : _T_5069 ? _Queue2_UInt8_28_io_deq_valid : _T_5068 ? _Queue2_UInt8_27_io_deq_valid : _T_5067 ? _Queue2_UInt8_26_io_deq_valid : _T_5066 ? _Queue2_UInt8_25_io_deq_valid : _T_5065 ? _Queue2_UInt8_24_io_deq_valid : _T_5064 ? _Queue2_UInt8_23_io_deq_valid : _T_5063 ? _Queue2_UInt8_22_io_deq_valid : _T_5062 ? _Queue2_UInt8_21_io_deq_valid : _T_5061 ? _Queue2_UInt8_20_io_deq_valid : _T_5060 ? _Queue2_UInt8_19_io_deq_valid : _T_5059 ? _Queue2_UInt8_18_io_deq_valid : _T_5058 ? _Queue2_UInt8_17_io_deq_valid : _T_5057 ? _Queue2_UInt8_16_io_deq_valid : _T_5056 ? _Queue2_UInt8_15_io_deq_valid : _T_5055 ? _Queue2_UInt8_14_io_deq_valid : _T_5054 ? _Queue2_UInt8_13_io_deq_valid : _T_5053 ? _Queue2_UInt8_12_io_deq_valid : _T_5052 ? _Queue2_UInt8_11_io_deq_valid : _T_5051 ? _Queue2_UInt8_10_io_deq_valid : _T_5050 ? _Queue2_UInt8_9_io_deq_valid : _T_5049 ? _Queue2_UInt8_8_io_deq_valid : _T_5048 ? _Queue2_UInt8_7_io_deq_valid : _T_5047 ? _Queue2_UInt8_6_io_deq_valid : _T_5046 ? _Queue2_UInt8_5_io_deq_valid : _T_5045 ? _Queue2_UInt8_4_io_deq_valid : _T_5044 ? _Queue2_UInt8_3_io_deq_valid : _T_5043 ? _Queue2_UInt8_2_io_deq_valid : _T_5042 ? _Queue2_UInt8_1_io_deq_valid : _T_5041 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_23 = _remapindex_T + 7'h17; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_113 = _remapindex_T_23 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_23 = _GEN_113[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_5073 = remapindex_23 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5074 = remapindex_23 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5075 = remapindex_23 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5076 = remapindex_23 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5077 = remapindex_23 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5078 = remapindex_23 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5079 = remapindex_23 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5080 = remapindex_23 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5081 = remapindex_23 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5082 = remapindex_23 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5083 = remapindex_23 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5084 = remapindex_23 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5085 = remapindex_23 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5086 = remapindex_23 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5087 = remapindex_23 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5088 = remapindex_23 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5089 = remapindex_23 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5090 = remapindex_23 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5091 = remapindex_23 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5092 = remapindex_23 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5093 = remapindex_23 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5094 = remapindex_23 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5095 = remapindex_23 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5096 = remapindex_23 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5097 = remapindex_23 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5098 = remapindex_23 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5099 = remapindex_23 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5100 = remapindex_23 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5101 = remapindex_23 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5102 = remapindex_23 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5103 = remapindex_23 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5104 = remapindex_23 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_23 = _T_5104 ? _Queue2_UInt8_31_io_deq_bits : _T_5103 ? _Queue2_UInt8_30_io_deq_bits : _T_5102 ? _Queue2_UInt8_29_io_deq_bits : _T_5101 ? _Queue2_UInt8_28_io_deq_bits : _T_5100 ? _Queue2_UInt8_27_io_deq_bits : _T_5099 ? _Queue2_UInt8_26_io_deq_bits : _T_5098 ? _Queue2_UInt8_25_io_deq_bits : _T_5097 ? _Queue2_UInt8_24_io_deq_bits : _T_5096 ? _Queue2_UInt8_23_io_deq_bits : _T_5095 ? _Queue2_UInt8_22_io_deq_bits : _T_5094 ? _Queue2_UInt8_21_io_deq_bits : _T_5093 ? _Queue2_UInt8_20_io_deq_bits : _T_5092 ? _Queue2_UInt8_19_io_deq_bits : _T_5091 ? _Queue2_UInt8_18_io_deq_bits : _T_5090 ? _Queue2_UInt8_17_io_deq_bits : _T_5089 ? _Queue2_UInt8_16_io_deq_bits : _T_5088 ? _Queue2_UInt8_15_io_deq_bits : _T_5087 ? _Queue2_UInt8_14_io_deq_bits : _T_5086 ? _Queue2_UInt8_13_io_deq_bits : _T_5085 ? _Queue2_UInt8_12_io_deq_bits : _T_5084 ? _Queue2_UInt8_11_io_deq_bits : _T_5083 ? _Queue2_UInt8_10_io_deq_bits : _T_5082 ? _Queue2_UInt8_9_io_deq_bits : _T_5081 ? _Queue2_UInt8_8_io_deq_bits : _T_5080 ? _Queue2_UInt8_7_io_deq_bits : _T_5079 ? _Queue2_UInt8_6_io_deq_bits : _T_5078 ? _Queue2_UInt8_5_io_deq_bits : _T_5077 ? _Queue2_UInt8_4_io_deq_bits : _T_5076 ? _Queue2_UInt8_3_io_deq_bits : _T_5075 ? _Queue2_UInt8_2_io_deq_bits : _T_5074 ? _Queue2_UInt8_1_io_deq_bits : _T_5073 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_23 = _T_5104 ? _Queue2_UInt8_31_io_deq_valid : _T_5103 ? _Queue2_UInt8_30_io_deq_valid : _T_5102 ? _Queue2_UInt8_29_io_deq_valid : _T_5101 ? _Queue2_UInt8_28_io_deq_valid : _T_5100 ? _Queue2_UInt8_27_io_deq_valid : _T_5099 ? _Queue2_UInt8_26_io_deq_valid : _T_5098 ? _Queue2_UInt8_25_io_deq_valid : _T_5097 ? _Queue2_UInt8_24_io_deq_valid : _T_5096 ? _Queue2_UInt8_23_io_deq_valid : _T_5095 ? _Queue2_UInt8_22_io_deq_valid : _T_5094 ? _Queue2_UInt8_21_io_deq_valid : _T_5093 ? _Queue2_UInt8_20_io_deq_valid : _T_5092 ? _Queue2_UInt8_19_io_deq_valid : _T_5091 ? _Queue2_UInt8_18_io_deq_valid : _T_5090 ? _Queue2_UInt8_17_io_deq_valid : _T_5089 ? _Queue2_UInt8_16_io_deq_valid : _T_5088 ? _Queue2_UInt8_15_io_deq_valid : _T_5087 ? _Queue2_UInt8_14_io_deq_valid : _T_5086 ? _Queue2_UInt8_13_io_deq_valid : _T_5085 ? _Queue2_UInt8_12_io_deq_valid : _T_5084 ? _Queue2_UInt8_11_io_deq_valid : _T_5083 ? _Queue2_UInt8_10_io_deq_valid : _T_5082 ? _Queue2_UInt8_9_io_deq_valid : _T_5081 ? _Queue2_UInt8_8_io_deq_valid : _T_5080 ? _Queue2_UInt8_7_io_deq_valid : _T_5079 ? _Queue2_UInt8_6_io_deq_valid : _T_5078 ? _Queue2_UInt8_5_io_deq_valid : _T_5077 ? _Queue2_UInt8_4_io_deq_valid : _T_5076 ? _Queue2_UInt8_3_io_deq_valid : _T_5075 ? _Queue2_UInt8_2_io_deq_valid : _T_5074 ? _Queue2_UInt8_1_io_deq_valid : _T_5073 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_24 = _remapindex_T + 7'h18; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_114 = _remapindex_T_24 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_24 = _GEN_114[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_5105 = remapindex_24 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5106 = remapindex_24 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5107 = remapindex_24 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5108 = remapindex_24 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5109 = remapindex_24 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5110 = remapindex_24 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5111 = remapindex_24 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5112 = remapindex_24 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5113 = remapindex_24 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5114 = remapindex_24 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5115 = remapindex_24 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5116 = remapindex_24 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5117 = remapindex_24 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5118 = remapindex_24 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5119 = remapindex_24 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5120 = remapindex_24 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5121 = remapindex_24 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5122 = remapindex_24 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5123 = remapindex_24 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5124 = remapindex_24 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5125 = remapindex_24 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5126 = remapindex_24 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5127 = remapindex_24 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5128 = remapindex_24 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5129 = remapindex_24 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5130 = remapindex_24 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5131 = remapindex_24 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5132 = remapindex_24 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5133 = remapindex_24 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5134 = remapindex_24 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5135 = remapindex_24 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5136 = remapindex_24 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_24 = _T_5136 ? _Queue2_UInt8_31_io_deq_bits : _T_5135 ? _Queue2_UInt8_30_io_deq_bits : _T_5134 ? _Queue2_UInt8_29_io_deq_bits : _T_5133 ? _Queue2_UInt8_28_io_deq_bits : _T_5132 ? _Queue2_UInt8_27_io_deq_bits : _T_5131 ? _Queue2_UInt8_26_io_deq_bits : _T_5130 ? _Queue2_UInt8_25_io_deq_bits : _T_5129 ? _Queue2_UInt8_24_io_deq_bits : _T_5128 ? _Queue2_UInt8_23_io_deq_bits : _T_5127 ? _Queue2_UInt8_22_io_deq_bits : _T_5126 ? _Queue2_UInt8_21_io_deq_bits : _T_5125 ? _Queue2_UInt8_20_io_deq_bits : _T_5124 ? _Queue2_UInt8_19_io_deq_bits : _T_5123 ? _Queue2_UInt8_18_io_deq_bits : _T_5122 ? _Queue2_UInt8_17_io_deq_bits : _T_5121 ? _Queue2_UInt8_16_io_deq_bits : _T_5120 ? _Queue2_UInt8_15_io_deq_bits : _T_5119 ? _Queue2_UInt8_14_io_deq_bits : _T_5118 ? _Queue2_UInt8_13_io_deq_bits : _T_5117 ? _Queue2_UInt8_12_io_deq_bits : _T_5116 ? _Queue2_UInt8_11_io_deq_bits : _T_5115 ? _Queue2_UInt8_10_io_deq_bits : _T_5114 ? _Queue2_UInt8_9_io_deq_bits : _T_5113 ? _Queue2_UInt8_8_io_deq_bits : _T_5112 ? _Queue2_UInt8_7_io_deq_bits : _T_5111 ? _Queue2_UInt8_6_io_deq_bits : _T_5110 ? _Queue2_UInt8_5_io_deq_bits : _T_5109 ? _Queue2_UInt8_4_io_deq_bits : _T_5108 ? _Queue2_UInt8_3_io_deq_bits : _T_5107 ? _Queue2_UInt8_2_io_deq_bits : _T_5106 ? _Queue2_UInt8_1_io_deq_bits : _T_5105 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_24 = _T_5136 ? _Queue2_UInt8_31_io_deq_valid : _T_5135 ? _Queue2_UInt8_30_io_deq_valid : _T_5134 ? _Queue2_UInt8_29_io_deq_valid : _T_5133 ? _Queue2_UInt8_28_io_deq_valid : _T_5132 ? _Queue2_UInt8_27_io_deq_valid : _T_5131 ? _Queue2_UInt8_26_io_deq_valid : _T_5130 ? _Queue2_UInt8_25_io_deq_valid : _T_5129 ? _Queue2_UInt8_24_io_deq_valid : _T_5128 ? _Queue2_UInt8_23_io_deq_valid : _T_5127 ? _Queue2_UInt8_22_io_deq_valid : _T_5126 ? _Queue2_UInt8_21_io_deq_valid : _T_5125 ? _Queue2_UInt8_20_io_deq_valid : _T_5124 ? _Queue2_UInt8_19_io_deq_valid : _T_5123 ? _Queue2_UInt8_18_io_deq_valid : _T_5122 ? _Queue2_UInt8_17_io_deq_valid : _T_5121 ? _Queue2_UInt8_16_io_deq_valid : _T_5120 ? _Queue2_UInt8_15_io_deq_valid : _T_5119 ? _Queue2_UInt8_14_io_deq_valid : _T_5118 ? _Queue2_UInt8_13_io_deq_valid : _T_5117 ? _Queue2_UInt8_12_io_deq_valid : _T_5116 ? _Queue2_UInt8_11_io_deq_valid : _T_5115 ? _Queue2_UInt8_10_io_deq_valid : _T_5114 ? _Queue2_UInt8_9_io_deq_valid : _T_5113 ? _Queue2_UInt8_8_io_deq_valid : _T_5112 ? _Queue2_UInt8_7_io_deq_valid : _T_5111 ? _Queue2_UInt8_6_io_deq_valid : _T_5110 ? _Queue2_UInt8_5_io_deq_valid : _T_5109 ? _Queue2_UInt8_4_io_deq_valid : _T_5108 ? _Queue2_UInt8_3_io_deq_valid : _T_5107 ? _Queue2_UInt8_2_io_deq_valid : _T_5106 ? _Queue2_UInt8_1_io_deq_valid : _T_5105 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_25 = _remapindex_T + 7'h19; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_115 = _remapindex_T_25 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_25 = _GEN_115[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_5137 = remapindex_25 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5138 = remapindex_25 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5139 = remapindex_25 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5140 = remapindex_25 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5141 = remapindex_25 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5142 = remapindex_25 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5143 = remapindex_25 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5144 = remapindex_25 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5145 = remapindex_25 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5146 = remapindex_25 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5147 = remapindex_25 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5148 = remapindex_25 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5149 = remapindex_25 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5150 = remapindex_25 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5151 = remapindex_25 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5152 = remapindex_25 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5153 = remapindex_25 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5154 = remapindex_25 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5155 = remapindex_25 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5156 = remapindex_25 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5157 = remapindex_25 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5158 = remapindex_25 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5159 = remapindex_25 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5160 = remapindex_25 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5161 = remapindex_25 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5162 = remapindex_25 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5163 = remapindex_25 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5164 = remapindex_25 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5165 = remapindex_25 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5166 = remapindex_25 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5167 = remapindex_25 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5168 = remapindex_25 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_25 = _T_5168 ? _Queue2_UInt8_31_io_deq_bits : _T_5167 ? _Queue2_UInt8_30_io_deq_bits : _T_5166 ? _Queue2_UInt8_29_io_deq_bits : _T_5165 ? _Queue2_UInt8_28_io_deq_bits : _T_5164 ? _Queue2_UInt8_27_io_deq_bits : _T_5163 ? _Queue2_UInt8_26_io_deq_bits : _T_5162 ? _Queue2_UInt8_25_io_deq_bits : _T_5161 ? _Queue2_UInt8_24_io_deq_bits : _T_5160 ? _Queue2_UInt8_23_io_deq_bits : _T_5159 ? _Queue2_UInt8_22_io_deq_bits : _T_5158 ? _Queue2_UInt8_21_io_deq_bits : _T_5157 ? _Queue2_UInt8_20_io_deq_bits : _T_5156 ? _Queue2_UInt8_19_io_deq_bits : _T_5155 ? _Queue2_UInt8_18_io_deq_bits : _T_5154 ? _Queue2_UInt8_17_io_deq_bits : _T_5153 ? _Queue2_UInt8_16_io_deq_bits : _T_5152 ? _Queue2_UInt8_15_io_deq_bits : _T_5151 ? _Queue2_UInt8_14_io_deq_bits : _T_5150 ? _Queue2_UInt8_13_io_deq_bits : _T_5149 ? _Queue2_UInt8_12_io_deq_bits : _T_5148 ? _Queue2_UInt8_11_io_deq_bits : _T_5147 ? _Queue2_UInt8_10_io_deq_bits : _T_5146 ? _Queue2_UInt8_9_io_deq_bits : _T_5145 ? _Queue2_UInt8_8_io_deq_bits : _T_5144 ? _Queue2_UInt8_7_io_deq_bits : _T_5143 ? _Queue2_UInt8_6_io_deq_bits : _T_5142 ? _Queue2_UInt8_5_io_deq_bits : _T_5141 ? _Queue2_UInt8_4_io_deq_bits : _T_5140 ? _Queue2_UInt8_3_io_deq_bits : _T_5139 ? _Queue2_UInt8_2_io_deq_bits : _T_5138 ? _Queue2_UInt8_1_io_deq_bits : _T_5137 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_25 = _T_5168 ? _Queue2_UInt8_31_io_deq_valid : _T_5167 ? _Queue2_UInt8_30_io_deq_valid : _T_5166 ? _Queue2_UInt8_29_io_deq_valid : _T_5165 ? _Queue2_UInt8_28_io_deq_valid : _T_5164 ? _Queue2_UInt8_27_io_deq_valid : _T_5163 ? _Queue2_UInt8_26_io_deq_valid : _T_5162 ? _Queue2_UInt8_25_io_deq_valid : _T_5161 ? _Queue2_UInt8_24_io_deq_valid : _T_5160 ? _Queue2_UInt8_23_io_deq_valid : _T_5159 ? _Queue2_UInt8_22_io_deq_valid : _T_5158 ? _Queue2_UInt8_21_io_deq_valid : _T_5157 ? _Queue2_UInt8_20_io_deq_valid : _T_5156 ? _Queue2_UInt8_19_io_deq_valid : _T_5155 ? _Queue2_UInt8_18_io_deq_valid : _T_5154 ? _Queue2_UInt8_17_io_deq_valid : _T_5153 ? _Queue2_UInt8_16_io_deq_valid : _T_5152 ? _Queue2_UInt8_15_io_deq_valid : _T_5151 ? _Queue2_UInt8_14_io_deq_valid : _T_5150 ? _Queue2_UInt8_13_io_deq_valid : _T_5149 ? _Queue2_UInt8_12_io_deq_valid : _T_5148 ? _Queue2_UInt8_11_io_deq_valid : _T_5147 ? _Queue2_UInt8_10_io_deq_valid : _T_5146 ? _Queue2_UInt8_9_io_deq_valid : _T_5145 ? _Queue2_UInt8_8_io_deq_valid : _T_5144 ? _Queue2_UInt8_7_io_deq_valid : _T_5143 ? _Queue2_UInt8_6_io_deq_valid : _T_5142 ? _Queue2_UInt8_5_io_deq_valid : _T_5141 ? _Queue2_UInt8_4_io_deq_valid : _T_5140 ? _Queue2_UInt8_3_io_deq_valid : _T_5139 ? _Queue2_UInt8_2_io_deq_valid : _T_5138 ? _Queue2_UInt8_1_io_deq_valid : _T_5137 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_26 = _remapindex_T + 7'h1A; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_116 = _remapindex_T_26 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_26 = _GEN_116[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_5169 = remapindex_26 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5170 = remapindex_26 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5171 = remapindex_26 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5172 = remapindex_26 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5173 = remapindex_26 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5174 = remapindex_26 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5175 = remapindex_26 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5176 = remapindex_26 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5177 = remapindex_26 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5178 = remapindex_26 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5179 = remapindex_26 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5180 = remapindex_26 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5181 = remapindex_26 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5182 = remapindex_26 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5183 = remapindex_26 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5184 = remapindex_26 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5185 = remapindex_26 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5186 = remapindex_26 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5187 = remapindex_26 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5188 = remapindex_26 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5189 = remapindex_26 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5190 = remapindex_26 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5191 = remapindex_26 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5192 = remapindex_26 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5193 = remapindex_26 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5194 = remapindex_26 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5195 = remapindex_26 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5196 = remapindex_26 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5197 = remapindex_26 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5198 = remapindex_26 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5199 = remapindex_26 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5200 = remapindex_26 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_26 = _T_5200 ? _Queue2_UInt8_31_io_deq_bits : _T_5199 ? _Queue2_UInt8_30_io_deq_bits : _T_5198 ? _Queue2_UInt8_29_io_deq_bits : _T_5197 ? _Queue2_UInt8_28_io_deq_bits : _T_5196 ? _Queue2_UInt8_27_io_deq_bits : _T_5195 ? _Queue2_UInt8_26_io_deq_bits : _T_5194 ? _Queue2_UInt8_25_io_deq_bits : _T_5193 ? _Queue2_UInt8_24_io_deq_bits : _T_5192 ? _Queue2_UInt8_23_io_deq_bits : _T_5191 ? _Queue2_UInt8_22_io_deq_bits : _T_5190 ? _Queue2_UInt8_21_io_deq_bits : _T_5189 ? _Queue2_UInt8_20_io_deq_bits : _T_5188 ? _Queue2_UInt8_19_io_deq_bits : _T_5187 ? _Queue2_UInt8_18_io_deq_bits : _T_5186 ? _Queue2_UInt8_17_io_deq_bits : _T_5185 ? _Queue2_UInt8_16_io_deq_bits : _T_5184 ? _Queue2_UInt8_15_io_deq_bits : _T_5183 ? _Queue2_UInt8_14_io_deq_bits : _T_5182 ? _Queue2_UInt8_13_io_deq_bits : _T_5181 ? _Queue2_UInt8_12_io_deq_bits : _T_5180 ? _Queue2_UInt8_11_io_deq_bits : _T_5179 ? _Queue2_UInt8_10_io_deq_bits : _T_5178 ? _Queue2_UInt8_9_io_deq_bits : _T_5177 ? _Queue2_UInt8_8_io_deq_bits : _T_5176 ? _Queue2_UInt8_7_io_deq_bits : _T_5175 ? _Queue2_UInt8_6_io_deq_bits : _T_5174 ? _Queue2_UInt8_5_io_deq_bits : _T_5173 ? _Queue2_UInt8_4_io_deq_bits : _T_5172 ? _Queue2_UInt8_3_io_deq_bits : _T_5171 ? _Queue2_UInt8_2_io_deq_bits : _T_5170 ? _Queue2_UInt8_1_io_deq_bits : _T_5169 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_26 = _T_5200 ? _Queue2_UInt8_31_io_deq_valid : _T_5199 ? _Queue2_UInt8_30_io_deq_valid : _T_5198 ? _Queue2_UInt8_29_io_deq_valid : _T_5197 ? _Queue2_UInt8_28_io_deq_valid : _T_5196 ? _Queue2_UInt8_27_io_deq_valid : _T_5195 ? _Queue2_UInt8_26_io_deq_valid : _T_5194 ? _Queue2_UInt8_25_io_deq_valid : _T_5193 ? _Queue2_UInt8_24_io_deq_valid : _T_5192 ? _Queue2_UInt8_23_io_deq_valid : _T_5191 ? _Queue2_UInt8_22_io_deq_valid : _T_5190 ? _Queue2_UInt8_21_io_deq_valid : _T_5189 ? _Queue2_UInt8_20_io_deq_valid : _T_5188 ? _Queue2_UInt8_19_io_deq_valid : _T_5187 ? _Queue2_UInt8_18_io_deq_valid : _T_5186 ? _Queue2_UInt8_17_io_deq_valid : _T_5185 ? _Queue2_UInt8_16_io_deq_valid : _T_5184 ? _Queue2_UInt8_15_io_deq_valid : _T_5183 ? _Queue2_UInt8_14_io_deq_valid : _T_5182 ? _Queue2_UInt8_13_io_deq_valid : _T_5181 ? _Queue2_UInt8_12_io_deq_valid : _T_5180 ? _Queue2_UInt8_11_io_deq_valid : _T_5179 ? _Queue2_UInt8_10_io_deq_valid : _T_5178 ? _Queue2_UInt8_9_io_deq_valid : _T_5177 ? _Queue2_UInt8_8_io_deq_valid : _T_5176 ? _Queue2_UInt8_7_io_deq_valid : _T_5175 ? _Queue2_UInt8_6_io_deq_valid : _T_5174 ? _Queue2_UInt8_5_io_deq_valid : _T_5173 ? _Queue2_UInt8_4_io_deq_valid : _T_5172 ? _Queue2_UInt8_3_io_deq_valid : _T_5171 ? _Queue2_UInt8_2_io_deq_valid : _T_5170 ? _Queue2_UInt8_1_io_deq_valid : _T_5169 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_27 = _remapindex_T + 7'h1B; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_117 = _remapindex_T_27 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_27 = _GEN_117[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_5201 = remapindex_27 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5202 = remapindex_27 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5203 = remapindex_27 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5204 = remapindex_27 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5205 = remapindex_27 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5206 = remapindex_27 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5207 = remapindex_27 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5208 = remapindex_27 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5209 = remapindex_27 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5210 = remapindex_27 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5211 = remapindex_27 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5212 = remapindex_27 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5213 = remapindex_27 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5214 = remapindex_27 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5215 = remapindex_27 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5216 = remapindex_27 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5217 = remapindex_27 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5218 = remapindex_27 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5219 = remapindex_27 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5220 = remapindex_27 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5221 = remapindex_27 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5222 = remapindex_27 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5223 = remapindex_27 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5224 = remapindex_27 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5225 = remapindex_27 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5226 = remapindex_27 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5227 = remapindex_27 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5228 = remapindex_27 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5229 = remapindex_27 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5230 = remapindex_27 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5231 = remapindex_27 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5232 = remapindex_27 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_27 = _T_5232 ? _Queue2_UInt8_31_io_deq_bits : _T_5231 ? _Queue2_UInt8_30_io_deq_bits : _T_5230 ? _Queue2_UInt8_29_io_deq_bits : _T_5229 ? _Queue2_UInt8_28_io_deq_bits : _T_5228 ? _Queue2_UInt8_27_io_deq_bits : _T_5227 ? _Queue2_UInt8_26_io_deq_bits : _T_5226 ? _Queue2_UInt8_25_io_deq_bits : _T_5225 ? _Queue2_UInt8_24_io_deq_bits : _T_5224 ? _Queue2_UInt8_23_io_deq_bits : _T_5223 ? _Queue2_UInt8_22_io_deq_bits : _T_5222 ? _Queue2_UInt8_21_io_deq_bits : _T_5221 ? _Queue2_UInt8_20_io_deq_bits : _T_5220 ? _Queue2_UInt8_19_io_deq_bits : _T_5219 ? _Queue2_UInt8_18_io_deq_bits : _T_5218 ? _Queue2_UInt8_17_io_deq_bits : _T_5217 ? _Queue2_UInt8_16_io_deq_bits : _T_5216 ? _Queue2_UInt8_15_io_deq_bits : _T_5215 ? _Queue2_UInt8_14_io_deq_bits : _T_5214 ? _Queue2_UInt8_13_io_deq_bits : _T_5213 ? _Queue2_UInt8_12_io_deq_bits : _T_5212 ? _Queue2_UInt8_11_io_deq_bits : _T_5211 ? _Queue2_UInt8_10_io_deq_bits : _T_5210 ? _Queue2_UInt8_9_io_deq_bits : _T_5209 ? _Queue2_UInt8_8_io_deq_bits : _T_5208 ? _Queue2_UInt8_7_io_deq_bits : _T_5207 ? _Queue2_UInt8_6_io_deq_bits : _T_5206 ? _Queue2_UInt8_5_io_deq_bits : _T_5205 ? _Queue2_UInt8_4_io_deq_bits : _T_5204 ? _Queue2_UInt8_3_io_deq_bits : _T_5203 ? _Queue2_UInt8_2_io_deq_bits : _T_5202 ? _Queue2_UInt8_1_io_deq_bits : _T_5201 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_27 = _T_5232 ? _Queue2_UInt8_31_io_deq_valid : _T_5231 ? _Queue2_UInt8_30_io_deq_valid : _T_5230 ? _Queue2_UInt8_29_io_deq_valid : _T_5229 ? _Queue2_UInt8_28_io_deq_valid : _T_5228 ? _Queue2_UInt8_27_io_deq_valid : _T_5227 ? _Queue2_UInt8_26_io_deq_valid : _T_5226 ? _Queue2_UInt8_25_io_deq_valid : _T_5225 ? _Queue2_UInt8_24_io_deq_valid : _T_5224 ? _Queue2_UInt8_23_io_deq_valid : _T_5223 ? _Queue2_UInt8_22_io_deq_valid : _T_5222 ? _Queue2_UInt8_21_io_deq_valid : _T_5221 ? _Queue2_UInt8_20_io_deq_valid : _T_5220 ? _Queue2_UInt8_19_io_deq_valid : _T_5219 ? _Queue2_UInt8_18_io_deq_valid : _T_5218 ? _Queue2_UInt8_17_io_deq_valid : _T_5217 ? _Queue2_UInt8_16_io_deq_valid : _T_5216 ? _Queue2_UInt8_15_io_deq_valid : _T_5215 ? _Queue2_UInt8_14_io_deq_valid : _T_5214 ? _Queue2_UInt8_13_io_deq_valid : _T_5213 ? _Queue2_UInt8_12_io_deq_valid : _T_5212 ? _Queue2_UInt8_11_io_deq_valid : _T_5211 ? _Queue2_UInt8_10_io_deq_valid : _T_5210 ? _Queue2_UInt8_9_io_deq_valid : _T_5209 ? _Queue2_UInt8_8_io_deq_valid : _T_5208 ? _Queue2_UInt8_7_io_deq_valid : _T_5207 ? _Queue2_UInt8_6_io_deq_valid : _T_5206 ? _Queue2_UInt8_5_io_deq_valid : _T_5205 ? _Queue2_UInt8_4_io_deq_valid : _T_5204 ? _Queue2_UInt8_3_io_deq_valid : _T_5203 ? _Queue2_UInt8_2_io_deq_valid : _T_5202 ? _Queue2_UInt8_1_io_deq_valid : _T_5201 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_28 = _remapindex_T + 7'h1C; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_118 = _remapindex_T_28 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_28 = _GEN_118[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_5233 = remapindex_28 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5234 = remapindex_28 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5235 = remapindex_28 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5236 = remapindex_28 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5237 = remapindex_28 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5238 = remapindex_28 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5239 = remapindex_28 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5240 = remapindex_28 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5241 = remapindex_28 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5242 = remapindex_28 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5243 = remapindex_28 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5244 = remapindex_28 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5245 = remapindex_28 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5246 = remapindex_28 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5247 = remapindex_28 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5248 = remapindex_28 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5249 = remapindex_28 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5250 = remapindex_28 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5251 = remapindex_28 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5252 = remapindex_28 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5253 = remapindex_28 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5254 = remapindex_28 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5255 = remapindex_28 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5256 = remapindex_28 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5257 = remapindex_28 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5258 = remapindex_28 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5259 = remapindex_28 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5260 = remapindex_28 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5261 = remapindex_28 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5262 = remapindex_28 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5263 = remapindex_28 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5264 = remapindex_28 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_28 = _T_5264 ? _Queue2_UInt8_31_io_deq_bits : _T_5263 ? _Queue2_UInt8_30_io_deq_bits : _T_5262 ? _Queue2_UInt8_29_io_deq_bits : _T_5261 ? _Queue2_UInt8_28_io_deq_bits : _T_5260 ? _Queue2_UInt8_27_io_deq_bits : _T_5259 ? _Queue2_UInt8_26_io_deq_bits : _T_5258 ? _Queue2_UInt8_25_io_deq_bits : _T_5257 ? _Queue2_UInt8_24_io_deq_bits : _T_5256 ? _Queue2_UInt8_23_io_deq_bits : _T_5255 ? _Queue2_UInt8_22_io_deq_bits : _T_5254 ? _Queue2_UInt8_21_io_deq_bits : _T_5253 ? _Queue2_UInt8_20_io_deq_bits : _T_5252 ? _Queue2_UInt8_19_io_deq_bits : _T_5251 ? _Queue2_UInt8_18_io_deq_bits : _T_5250 ? _Queue2_UInt8_17_io_deq_bits : _T_5249 ? _Queue2_UInt8_16_io_deq_bits : _T_5248 ? _Queue2_UInt8_15_io_deq_bits : _T_5247 ? _Queue2_UInt8_14_io_deq_bits : _T_5246 ? _Queue2_UInt8_13_io_deq_bits : _T_5245 ? _Queue2_UInt8_12_io_deq_bits : _T_5244 ? _Queue2_UInt8_11_io_deq_bits : _T_5243 ? _Queue2_UInt8_10_io_deq_bits : _T_5242 ? _Queue2_UInt8_9_io_deq_bits : _T_5241 ? _Queue2_UInt8_8_io_deq_bits : _T_5240 ? _Queue2_UInt8_7_io_deq_bits : _T_5239 ? _Queue2_UInt8_6_io_deq_bits : _T_5238 ? _Queue2_UInt8_5_io_deq_bits : _T_5237 ? _Queue2_UInt8_4_io_deq_bits : _T_5236 ? _Queue2_UInt8_3_io_deq_bits : _T_5235 ? _Queue2_UInt8_2_io_deq_bits : _T_5234 ? _Queue2_UInt8_1_io_deq_bits : _T_5233 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_28 = _T_5264 ? _Queue2_UInt8_31_io_deq_valid : _T_5263 ? _Queue2_UInt8_30_io_deq_valid : _T_5262 ? _Queue2_UInt8_29_io_deq_valid : _T_5261 ? _Queue2_UInt8_28_io_deq_valid : _T_5260 ? _Queue2_UInt8_27_io_deq_valid : _T_5259 ? _Queue2_UInt8_26_io_deq_valid : _T_5258 ? _Queue2_UInt8_25_io_deq_valid : _T_5257 ? _Queue2_UInt8_24_io_deq_valid : _T_5256 ? _Queue2_UInt8_23_io_deq_valid : _T_5255 ? _Queue2_UInt8_22_io_deq_valid : _T_5254 ? _Queue2_UInt8_21_io_deq_valid : _T_5253 ? _Queue2_UInt8_20_io_deq_valid : _T_5252 ? _Queue2_UInt8_19_io_deq_valid : _T_5251 ? _Queue2_UInt8_18_io_deq_valid : _T_5250 ? _Queue2_UInt8_17_io_deq_valid : _T_5249 ? _Queue2_UInt8_16_io_deq_valid : _T_5248 ? _Queue2_UInt8_15_io_deq_valid : _T_5247 ? _Queue2_UInt8_14_io_deq_valid : _T_5246 ? _Queue2_UInt8_13_io_deq_valid : _T_5245 ? _Queue2_UInt8_12_io_deq_valid : _T_5244 ? _Queue2_UInt8_11_io_deq_valid : _T_5243 ? _Queue2_UInt8_10_io_deq_valid : _T_5242 ? _Queue2_UInt8_9_io_deq_valid : _T_5241 ? _Queue2_UInt8_8_io_deq_valid : _T_5240 ? _Queue2_UInt8_7_io_deq_valid : _T_5239 ? _Queue2_UInt8_6_io_deq_valid : _T_5238 ? _Queue2_UInt8_5_io_deq_valid : _T_5237 ? _Queue2_UInt8_4_io_deq_valid : _T_5236 ? _Queue2_UInt8_3_io_deq_valid : _T_5235 ? _Queue2_UInt8_2_io_deq_valid : _T_5234 ? _Queue2_UInt8_1_io_deq_valid : _T_5233 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_29 = _remapindex_T + 7'h1D; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_119 = _remapindex_T_29 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_29 = _GEN_119[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_5265 = remapindex_29 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5266 = remapindex_29 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5267 = remapindex_29 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5268 = remapindex_29 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5269 = remapindex_29 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5270 = remapindex_29 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5271 = remapindex_29 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5272 = remapindex_29 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5273 = remapindex_29 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5274 = remapindex_29 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5275 = remapindex_29 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5276 = remapindex_29 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5277 = remapindex_29 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5278 = remapindex_29 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5279 = remapindex_29 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5280 = remapindex_29 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5281 = remapindex_29 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5282 = remapindex_29 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5283 = remapindex_29 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5284 = remapindex_29 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5285 = remapindex_29 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5286 = remapindex_29 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5287 = remapindex_29 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5288 = remapindex_29 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5289 = remapindex_29 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5290 = remapindex_29 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5291 = remapindex_29 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5292 = remapindex_29 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5293 = remapindex_29 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5294 = remapindex_29 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5295 = remapindex_29 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5296 = remapindex_29 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_29 = _T_5296 ? _Queue2_UInt8_31_io_deq_bits : _T_5295 ? _Queue2_UInt8_30_io_deq_bits : _T_5294 ? _Queue2_UInt8_29_io_deq_bits : _T_5293 ? _Queue2_UInt8_28_io_deq_bits : _T_5292 ? _Queue2_UInt8_27_io_deq_bits : _T_5291 ? _Queue2_UInt8_26_io_deq_bits : _T_5290 ? _Queue2_UInt8_25_io_deq_bits : _T_5289 ? _Queue2_UInt8_24_io_deq_bits : _T_5288 ? _Queue2_UInt8_23_io_deq_bits : _T_5287 ? _Queue2_UInt8_22_io_deq_bits : _T_5286 ? _Queue2_UInt8_21_io_deq_bits : _T_5285 ? _Queue2_UInt8_20_io_deq_bits : _T_5284 ? _Queue2_UInt8_19_io_deq_bits : _T_5283 ? _Queue2_UInt8_18_io_deq_bits : _T_5282 ? _Queue2_UInt8_17_io_deq_bits : _T_5281 ? _Queue2_UInt8_16_io_deq_bits : _T_5280 ? _Queue2_UInt8_15_io_deq_bits : _T_5279 ? _Queue2_UInt8_14_io_deq_bits : _T_5278 ? _Queue2_UInt8_13_io_deq_bits : _T_5277 ? _Queue2_UInt8_12_io_deq_bits : _T_5276 ? _Queue2_UInt8_11_io_deq_bits : _T_5275 ? _Queue2_UInt8_10_io_deq_bits : _T_5274 ? _Queue2_UInt8_9_io_deq_bits : _T_5273 ? _Queue2_UInt8_8_io_deq_bits : _T_5272 ? _Queue2_UInt8_7_io_deq_bits : _T_5271 ? _Queue2_UInt8_6_io_deq_bits : _T_5270 ? _Queue2_UInt8_5_io_deq_bits : _T_5269 ? _Queue2_UInt8_4_io_deq_bits : _T_5268 ? _Queue2_UInt8_3_io_deq_bits : _T_5267 ? _Queue2_UInt8_2_io_deq_bits : _T_5266 ? _Queue2_UInt8_1_io_deq_bits : _T_5265 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_29 = _T_5296 ? _Queue2_UInt8_31_io_deq_valid : _T_5295 ? _Queue2_UInt8_30_io_deq_valid : _T_5294 ? _Queue2_UInt8_29_io_deq_valid : _T_5293 ? _Queue2_UInt8_28_io_deq_valid : _T_5292 ? _Queue2_UInt8_27_io_deq_valid : _T_5291 ? _Queue2_UInt8_26_io_deq_valid : _T_5290 ? _Queue2_UInt8_25_io_deq_valid : _T_5289 ? _Queue2_UInt8_24_io_deq_valid : _T_5288 ? _Queue2_UInt8_23_io_deq_valid : _T_5287 ? _Queue2_UInt8_22_io_deq_valid : _T_5286 ? _Queue2_UInt8_21_io_deq_valid : _T_5285 ? _Queue2_UInt8_20_io_deq_valid : _T_5284 ? _Queue2_UInt8_19_io_deq_valid : _T_5283 ? _Queue2_UInt8_18_io_deq_valid : _T_5282 ? _Queue2_UInt8_17_io_deq_valid : _T_5281 ? _Queue2_UInt8_16_io_deq_valid : _T_5280 ? _Queue2_UInt8_15_io_deq_valid : _T_5279 ? _Queue2_UInt8_14_io_deq_valid : _T_5278 ? _Queue2_UInt8_13_io_deq_valid : _T_5277 ? _Queue2_UInt8_12_io_deq_valid : _T_5276 ? _Queue2_UInt8_11_io_deq_valid : _T_5275 ? _Queue2_UInt8_10_io_deq_valid : _T_5274 ? _Queue2_UInt8_9_io_deq_valid : _T_5273 ? _Queue2_UInt8_8_io_deq_valid : _T_5272 ? _Queue2_UInt8_7_io_deq_valid : _T_5271 ? _Queue2_UInt8_6_io_deq_valid : _T_5270 ? _Queue2_UInt8_5_io_deq_valid : _T_5269 ? _Queue2_UInt8_4_io_deq_valid : _T_5268 ? _Queue2_UInt8_3_io_deq_valid : _T_5267 ? _Queue2_UInt8_2_io_deq_valid : _T_5266 ? _Queue2_UInt8_1_io_deq_valid : _T_5265 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_30 = _remapindex_T + 7'h1E; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_120 = _remapindex_T_30 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_30 = _GEN_120[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_5297 = remapindex_30 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5298 = remapindex_30 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5299 = remapindex_30 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5300 = remapindex_30 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5301 = remapindex_30 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5302 = remapindex_30 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5303 = remapindex_30 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5304 = remapindex_30 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5305 = remapindex_30 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5306 = remapindex_30 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5307 = remapindex_30 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5308 = remapindex_30 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5309 = remapindex_30 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5310 = remapindex_30 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5311 = remapindex_30 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5312 = remapindex_30 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5313 = remapindex_30 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5314 = remapindex_30 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5315 = remapindex_30 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5316 = remapindex_30 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5317 = remapindex_30 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5318 = remapindex_30 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5319 = remapindex_30 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5320 = remapindex_30 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5321 = remapindex_30 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5322 = remapindex_30 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5323 = remapindex_30 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5324 = remapindex_30 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5325 = remapindex_30 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5326 = remapindex_30 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5327 = remapindex_30 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5328 = remapindex_30 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_30 = _T_5328 ? _Queue2_UInt8_31_io_deq_bits : _T_5327 ? _Queue2_UInt8_30_io_deq_bits : _T_5326 ? _Queue2_UInt8_29_io_deq_bits : _T_5325 ? _Queue2_UInt8_28_io_deq_bits : _T_5324 ? _Queue2_UInt8_27_io_deq_bits : _T_5323 ? _Queue2_UInt8_26_io_deq_bits : _T_5322 ? _Queue2_UInt8_25_io_deq_bits : _T_5321 ? _Queue2_UInt8_24_io_deq_bits : _T_5320 ? _Queue2_UInt8_23_io_deq_bits : _T_5319 ? _Queue2_UInt8_22_io_deq_bits : _T_5318 ? _Queue2_UInt8_21_io_deq_bits : _T_5317 ? _Queue2_UInt8_20_io_deq_bits : _T_5316 ? _Queue2_UInt8_19_io_deq_bits : _T_5315 ? _Queue2_UInt8_18_io_deq_bits : _T_5314 ? _Queue2_UInt8_17_io_deq_bits : _T_5313 ? _Queue2_UInt8_16_io_deq_bits : _T_5312 ? _Queue2_UInt8_15_io_deq_bits : _T_5311 ? _Queue2_UInt8_14_io_deq_bits : _T_5310 ? _Queue2_UInt8_13_io_deq_bits : _T_5309 ? _Queue2_UInt8_12_io_deq_bits : _T_5308 ? _Queue2_UInt8_11_io_deq_bits : _T_5307 ? _Queue2_UInt8_10_io_deq_bits : _T_5306 ? _Queue2_UInt8_9_io_deq_bits : _T_5305 ? _Queue2_UInt8_8_io_deq_bits : _T_5304 ? _Queue2_UInt8_7_io_deq_bits : _T_5303 ? _Queue2_UInt8_6_io_deq_bits : _T_5302 ? _Queue2_UInt8_5_io_deq_bits : _T_5301 ? _Queue2_UInt8_4_io_deq_bits : _T_5300 ? _Queue2_UInt8_3_io_deq_bits : _T_5299 ? _Queue2_UInt8_2_io_deq_bits : _T_5298 ? _Queue2_UInt8_1_io_deq_bits : _T_5297 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_30 = _T_5328 ? _Queue2_UInt8_31_io_deq_valid : _T_5327 ? _Queue2_UInt8_30_io_deq_valid : _T_5326 ? _Queue2_UInt8_29_io_deq_valid : _T_5325 ? _Queue2_UInt8_28_io_deq_valid : _T_5324 ? _Queue2_UInt8_27_io_deq_valid : _T_5323 ? _Queue2_UInt8_26_io_deq_valid : _T_5322 ? _Queue2_UInt8_25_io_deq_valid : _T_5321 ? _Queue2_UInt8_24_io_deq_valid : _T_5320 ? _Queue2_UInt8_23_io_deq_valid : _T_5319 ? _Queue2_UInt8_22_io_deq_valid : _T_5318 ? _Queue2_UInt8_21_io_deq_valid : _T_5317 ? _Queue2_UInt8_20_io_deq_valid : _T_5316 ? _Queue2_UInt8_19_io_deq_valid : _T_5315 ? _Queue2_UInt8_18_io_deq_valid : _T_5314 ? _Queue2_UInt8_17_io_deq_valid : _T_5313 ? _Queue2_UInt8_16_io_deq_valid : _T_5312 ? _Queue2_UInt8_15_io_deq_valid : _T_5311 ? _Queue2_UInt8_14_io_deq_valid : _T_5310 ? _Queue2_UInt8_13_io_deq_valid : _T_5309 ? _Queue2_UInt8_12_io_deq_valid : _T_5308 ? _Queue2_UInt8_11_io_deq_valid : _T_5307 ? _Queue2_UInt8_10_io_deq_valid : _T_5306 ? _Queue2_UInt8_9_io_deq_valid : _T_5305 ? _Queue2_UInt8_8_io_deq_valid : _T_5304 ? _Queue2_UInt8_7_io_deq_valid : _T_5303 ? _Queue2_UInt8_6_io_deq_valid : _T_5302 ? _Queue2_UInt8_5_io_deq_valid : _T_5301 ? _Queue2_UInt8_4_io_deq_valid : _T_5300 ? _Queue2_UInt8_3_io_deq_valid : _T_5299 ? _Queue2_UInt8_2_io_deq_valid : _T_5298 ? _Queue2_UInt8_1_io_deq_valid : _T_5297 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [6:0] _remapindex_T_31 = _remapindex_T + 7'h1F; // @[ZstdCompressorMemWriter.scala:153:33]
wire [6:0] _GEN_121 = _remapindex_T_31 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}]
wire [5:0] remapindex_31 = _GEN_121[5:0]; // @[ZstdCompressorMemWriter.scala:153:54]
wire _T_5329 = remapindex_31 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5330 = remapindex_31 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5331 = remapindex_31 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5332 = remapindex_31 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5333 = remapindex_31 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5334 = remapindex_31 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5335 = remapindex_31 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5336 = remapindex_31 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5337 = remapindex_31 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5338 = remapindex_31 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5339 = remapindex_31 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5340 = remapindex_31 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5341 = remapindex_31 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5342 = remapindex_31 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5343 = remapindex_31 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5344 = remapindex_31 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5345 = remapindex_31 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5346 = remapindex_31 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5347 = remapindex_31 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5348 = remapindex_31 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5349 = remapindex_31 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5350 = remapindex_31 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5351 = remapindex_31 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5352 = remapindex_31 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5353 = remapindex_31 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5354 = remapindex_31 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5355 = remapindex_31 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5356 = remapindex_31 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5357 = remapindex_31 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5358 = remapindex_31 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5359 = remapindex_31 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
wire _T_5360 = remapindex_31 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17]
assign remapVecData_31 = _T_5360 ? _Queue2_UInt8_31_io_deq_bits : _T_5359 ? _Queue2_UInt8_30_io_deq_bits : _T_5358 ? _Queue2_UInt8_29_io_deq_bits : _T_5357 ? _Queue2_UInt8_28_io_deq_bits : _T_5356 ? _Queue2_UInt8_27_io_deq_bits : _T_5355 ? _Queue2_UInt8_26_io_deq_bits : _T_5354 ? _Queue2_UInt8_25_io_deq_bits : _T_5353 ? _Queue2_UInt8_24_io_deq_bits : _T_5352 ? _Queue2_UInt8_23_io_deq_bits : _T_5351 ? _Queue2_UInt8_22_io_deq_bits : _T_5350 ? _Queue2_UInt8_21_io_deq_bits : _T_5349 ? _Queue2_UInt8_20_io_deq_bits : _T_5348 ? _Queue2_UInt8_19_io_deq_bits : _T_5347 ? _Queue2_UInt8_18_io_deq_bits : _T_5346 ? _Queue2_UInt8_17_io_deq_bits : _T_5345 ? _Queue2_UInt8_16_io_deq_bits : _T_5344 ? _Queue2_UInt8_15_io_deq_bits : _T_5343 ? _Queue2_UInt8_14_io_deq_bits : _T_5342 ? _Queue2_UInt8_13_io_deq_bits : _T_5341 ? _Queue2_UInt8_12_io_deq_bits : _T_5340 ? _Queue2_UInt8_11_io_deq_bits : _T_5339 ? _Queue2_UInt8_10_io_deq_bits : _T_5338 ? _Queue2_UInt8_9_io_deq_bits : _T_5337 ? _Queue2_UInt8_8_io_deq_bits : _T_5336 ? _Queue2_UInt8_7_io_deq_bits : _T_5335 ? _Queue2_UInt8_6_io_deq_bits : _T_5334 ? _Queue2_UInt8_5_io_deq_bits : _T_5333 ? _Queue2_UInt8_4_io_deq_bits : _T_5332 ? _Queue2_UInt8_3_io_deq_bits : _T_5331 ? _Queue2_UInt8_2_io_deq_bits : _T_5330 ? _Queue2_UInt8_1_io_deq_bits : _T_5329 ? _Queue2_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31]
assign remapVecValids_31 = _T_5360 ? _Queue2_UInt8_31_io_deq_valid : _T_5359 ? _Queue2_UInt8_30_io_deq_valid : _T_5358 ? _Queue2_UInt8_29_io_deq_valid : _T_5357 ? _Queue2_UInt8_28_io_deq_valid : _T_5356 ? _Queue2_UInt8_27_io_deq_valid : _T_5355 ? _Queue2_UInt8_26_io_deq_valid : _T_5354 ? _Queue2_UInt8_25_io_deq_valid : _T_5353 ? _Queue2_UInt8_24_io_deq_valid : _T_5352 ? _Queue2_UInt8_23_io_deq_valid : _T_5351 ? _Queue2_UInt8_22_io_deq_valid : _T_5350 ? _Queue2_UInt8_21_io_deq_valid : _T_5349 ? _Queue2_UInt8_20_io_deq_valid : _T_5348 ? _Queue2_UInt8_19_io_deq_valid : _T_5347 ? _Queue2_UInt8_18_io_deq_valid : _T_5346 ? _Queue2_UInt8_17_io_deq_valid : _T_5345 ? _Queue2_UInt8_16_io_deq_valid : _T_5344 ? _Queue2_UInt8_15_io_deq_valid : _T_5343 ? _Queue2_UInt8_14_io_deq_valid : _T_5342 ? _Queue2_UInt8_13_io_deq_valid : _T_5341 ? _Queue2_UInt8_12_io_deq_valid : _T_5340 ? _Queue2_UInt8_11_io_deq_valid : _T_5339 ? _Queue2_UInt8_10_io_deq_valid : _T_5338 ? _Queue2_UInt8_9_io_deq_valid : _T_5337 ? _Queue2_UInt8_8_io_deq_valid : _T_5336 ? _Queue2_UInt8_7_io_deq_valid : _T_5335 ? _Queue2_UInt8_6_io_deq_valid : _T_5334 ? _Queue2_UInt8_5_io_deq_valid : _T_5333 ? _Queue2_UInt8_4_io_deq_valid : _T_5332 ? _Queue2_UInt8_3_io_deq_valid : _T_5331 ? _Queue2_UInt8_2_io_deq_valid : _T_5330 ? _Queue2_UInt8_1_io_deq_valid : _T_5329 & _Queue2_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33]
wire [1:0] _count_valids_T = {1'h0, remapVecValids_0} + {1'h0, remapVecValids_1}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [2:0] _count_valids_T_1 = {1'h0, _count_valids_T} + {2'h0, remapVecValids_2}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [3:0] _count_valids_T_2 = {1'h0, _count_valids_T_1} + {3'h0, remapVecValids_3}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [4:0] _count_valids_T_3 = {1'h0, _count_valids_T_2} + {4'h0, remapVecValids_4}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [5:0] _count_valids_T_4 = {1'h0, _count_valids_T_3} + {5'h0, remapVecValids_5}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [6:0] _count_valids_T_5 = {1'h0, _count_valids_T_4} + {6'h0, remapVecValids_6}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [7:0] _count_valids_T_6 = {1'h0, _count_valids_T_5} + {7'h0, remapVecValids_7}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [8:0] _count_valids_T_7 = {1'h0, _count_valids_T_6} + {8'h0, remapVecValids_8}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [9:0] _count_valids_T_8 = {1'h0, _count_valids_T_7} + {9'h0, remapVecValids_9}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [10:0] _count_valids_T_9 = {1'h0, _count_valids_T_8} + {10'h0, remapVecValids_10}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [11:0] _count_valids_T_10 = {1'h0, _count_valids_T_9} + {11'h0, remapVecValids_11}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [12:0] _count_valids_T_11 = {1'h0, _count_valids_T_10} + {12'h0, remapVecValids_12}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [13:0] _count_valids_T_12 = {1'h0, _count_valids_T_11} + {13'h0, remapVecValids_13}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [14:0] _count_valids_T_13 = {1'h0, _count_valids_T_12} + {14'h0, remapVecValids_14}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [15:0] _count_valids_T_14 = {1'h0, _count_valids_T_13} + {15'h0, remapVecValids_15}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [16:0] _count_valids_T_15 = {1'h0, _count_valids_T_14} + {16'h0, remapVecValids_16}; // @[ZstdCompressorMemWriter.scala:89:{76,90}, :142:28, :163:60]
wire [17:0] _count_valids_T_16 = {1'h0, _count_valids_T_15} + {17'h0, remapVecValids_17}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [18:0] _count_valids_T_17 = {1'h0, _count_valids_T_16} + {18'h0, remapVecValids_18}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [19:0] _count_valids_T_18 = {1'h0, _count_valids_T_17} + {19'h0, remapVecValids_19}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [20:0] _count_valids_T_19 = {1'h0, _count_valids_T_18} + {20'h0, remapVecValids_20}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [21:0] _count_valids_T_20 = {1'h0, _count_valids_T_19} + {21'h0, remapVecValids_21}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [22:0] _count_valids_T_21 = {1'h0, _count_valids_T_20} + {22'h0, remapVecValids_22}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [23:0] _count_valids_T_22 = {1'h0, _count_valids_T_21} + {23'h0, remapVecValids_23}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [24:0] _count_valids_T_23 = {1'h0, _count_valids_T_22} + {24'h0, remapVecValids_24}; // @[ZstdCompressorMemWriter.scala:89:{76,90}, :142:28, :163:60]
wire [25:0] _count_valids_T_24 = {1'h0, _count_valids_T_23} + {25'h0, remapVecValids_25}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [26:0] _count_valids_T_25 = {1'h0, _count_valids_T_24} + {26'h0, remapVecValids_26}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [27:0] _count_valids_T_26 = {1'h0, _count_valids_T_25} + {27'h0, remapVecValids_27}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [28:0] _count_valids_T_27 = {1'h0, _count_valids_T_26} + {28'h0, remapVecValids_28}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [29:0] _count_valids_T_28 = {1'h0, _count_valids_T_27} + {29'h0, remapVecValids_29}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [30:0] _count_valids_T_29 = {1'h0, _count_valids_T_28} + {30'h0, remapVecValids_30}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
wire [31:0] count_valids = {1'h0, _count_valids_T_29} + {31'h0, remapVecValids_31}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60]
reg [63:0] backend_bytes_written; // @[ZstdCompressorMemWriter.scala:167:38]
wire [64:0] _GEN_122 = {1'h0, backend_bytes_written}; // @[ZstdCompressorMemWriter.scala:167:38, :168:60]
wire [64:0] _backend_next_write_addr_T = {1'h0, _dest_info_Q_io_deq_bits_op} + _GEN_122; // @[ZstdCompressorMemWriter.scala:39:27, :168:60]
wire [63:0] backend_next_write_addr = _backend_next_write_addr_T[63:0]; // @[ZstdCompressorMemWriter.scala:168:60]
wire [64:0] _throttle_end_T = {1'h0, _buf_lens_Q_io_deq_bits} - _GEN_122; // @[ZstdCompressorMemWriter.scala:52:26, :168:60, :171:28]
wire [63:0] _throttle_end_T_1 = _throttle_end_T[63:0]; // @[ZstdCompressorMemWriter.scala:171:28]
wire [63:0] throttle_end = _buf_lens_Q_io_deq_valid ? _throttle_end_T_1 : 64'h20; // @[ZstdCompressorMemWriter.scala:52:26, :170:25, :171:28]
wire _throttle_end_writeable_T = |(throttle_end[63:5]); // @[ZstdCompressorMemWriter.scala:170:25, :174:49]
wire _throttle_end_writeable_T_1 = throttle_end[4]; // @[ZstdCompressorMemWriter.scala:170:25, :175:53]
wire _throttle_end_writeable_log2_T_1 = throttle_end[4]; // @[ZstdCompressorMemWriter.scala:170:25, :175:53, :183:55]
wire _throttle_end_writeable_T_2 = throttle_end[3]; // @[ZstdCompressorMemWriter.scala:170:25, :176:55]
wire _throttle_end_writeable_log2_T_2 = throttle_end[3]; // @[ZstdCompressorMemWriter.scala:170:25, :176:55, :184:57]
wire _throttle_end_writeable_T_3 = throttle_end[2]; // @[ZstdCompressorMemWriter.scala:170:25, :177:57]
wire _throttle_end_writeable_log2_T_3 = throttle_end[2]; // @[ZstdCompressorMemWriter.scala:170:25, :177:57, :185:59]
wire _throttle_end_writeable_T_4 = throttle_end[1]; // @[ZstdCompressorMemWriter.scala:170:25, :178:59]
wire _throttle_end_writeable_log2_T_4 = throttle_end[1]; // @[ZstdCompressorMemWriter.scala:170:25, :178:59, :186:61]
wire _throttle_end_writeable_T_5 = throttle_end[0]; // @[ZstdCompressorMemWriter.scala:170:25, :179:61]
wire _throttle_end_writeable_log2_T_5 = throttle_end[0]; // @[ZstdCompressorMemWriter.scala:170:25, :179:61, :187:63]
wire _throttle_end_writeable_T_6 = _throttle_end_writeable_T_5; // @[ZstdCompressorMemWriter.scala:179:{48,61}]
wire [1:0] _throttle_end_writeable_T_7 = _throttle_end_writeable_T_4 ? 2'h2 : {1'h0, _throttle_end_writeable_T_6}; // @[ZstdCompressorMemWriter.scala:178:{46,59}, :179:48]
wire [2:0] _throttle_end_writeable_T_8 = _throttle_end_writeable_T_3 ? 3'h4 : {1'h0, _throttle_end_writeable_T_7}; // @[ZstdCompressorMemWriter.scala:177:{44,57}, :178:46]
wire [3:0] _throttle_end_writeable_T_9 = _throttle_end_writeable_T_2 ? 4'h8 : {1'h0, _throttle_end_writeable_T_8}; // @[ZstdCompressorMemWriter.scala:176:{42,55}, :177:44]
wire [4:0] _throttle_end_writeable_T_10 = _throttle_end_writeable_T_1 ? 5'h10 : {1'h0, _throttle_end_writeable_T_9}; // @[ZstdCompressorMemWriter.scala:175:{40,53}, :176:42]
wire [5:0] throttle_end_writeable = _throttle_end_writeable_T ? 6'h20 : {1'h0, _throttle_end_writeable_T_10}; // @[ZstdCompressorMemWriter.scala:174:{35,49}, :175:40]
wire _throttle_end_writeable_log2_T = |(throttle_end[63:5]); // @[ZstdCompressorMemWriter.scala:170:25, :174:49, :182:54]
wire _throttle_end_writeable_log2_T_7 = _throttle_end_writeable_log2_T_4; // @[ZstdCompressorMemWriter.scala:186:{48,61}]
wire [1:0] _throttle_end_writeable_log2_T_8 = _throttle_end_writeable_log2_T_3 ? 2'h2 : {1'h0, _throttle_end_writeable_log2_T_7}; // @[ZstdCompressorMemWriter.scala:185:{46,59}, :186:48]
wire [1:0] _throttle_end_writeable_log2_T_9 = _throttle_end_writeable_log2_T_2 ? 2'h3 : _throttle_end_writeable_log2_T_8; // @[ZstdCompressorMemWriter.scala:184:{44,57}, :185:46]
wire [2:0] _throttle_end_writeable_log2_T_10 = _throttle_end_writeable_log2_T_1 ? 3'h4 : {1'h0, _throttle_end_writeable_log2_T_9}; // @[ZstdCompressorMemWriter.scala:183:{42,55}, :184:44]
wire [2:0] throttle_end_writeable_log2 = _throttle_end_writeable_log2_T ? 3'h5 : _throttle_end_writeable_log2_T_10; // @[ZstdCompressorMemWriter.scala:182:{40,54}, :183:42]
wire _ptr_align_max_bytes_writeable_T = backend_next_write_addr[0]; // @[ZstdCompressorMemWriter.scala:168:60, :191:66]
wire _ptr_align_max_bytes_writeable_log2_T = backend_next_write_addr[0]; // @[ZstdCompressorMemWriter.scala:168:60, :191:66, :198:71]
wire _ptr_align_max_bytes_writeable_T_1 = backend_next_write_addr[1]; // @[ZstdCompressorMemWriter.scala:168:60, :192:68]
wire _ptr_align_max_bytes_writeable_log2_T_1 = backend_next_write_addr[1]; // @[ZstdCompressorMemWriter.scala:168:60, :192:68, :199:72]
wire _ptr_align_max_bytes_writeable_T_2 = backend_next_write_addr[2]; // @[ZstdCompressorMemWriter.scala:168:60, :193:70]
wire _ptr_align_max_bytes_writeable_log2_T_2 = backend_next_write_addr[2]; // @[ZstdCompressorMemWriter.scala:168:60, :193:70, :200:74]
wire _ptr_align_max_bytes_writeable_T_3 = backend_next_write_addr[3]; // @[ZstdCompressorMemWriter.scala:168:60, :194:72]
wire _ptr_align_max_bytes_writeable_log2_T_3 = backend_next_write_addr[3]; // @[ZstdCompressorMemWriter.scala:168:60, :194:72, :201:76]
wire _ptr_align_max_bytes_writeable_T_4 = backend_next_write_addr[4]; // @[ZstdCompressorMemWriter.scala:168:60, :195:74]
wire _ptr_align_max_bytes_writeable_log2_T_4 = backend_next_write_addr[4]; // @[ZstdCompressorMemWriter.scala:168:60, :195:74, :202:78]
wire [5:0] _ptr_align_max_bytes_writeable_T_5 = _ptr_align_max_bytes_writeable_T_4 ? 6'h10 : 6'h20; // @[ZstdCompressorMemWriter.scala:195:{50,74}]
wire [5:0] _ptr_align_max_bytes_writeable_T_6 = _ptr_align_max_bytes_writeable_T_3 ? 6'h8 : _ptr_align_max_bytes_writeable_T_5; // @[ZstdCompressorMemWriter.scala:194:{48,72}, :195:50]
wire [5:0] _ptr_align_max_bytes_writeable_T_7 = _ptr_align_max_bytes_writeable_T_2 ? 6'h4 : _ptr_align_max_bytes_writeable_T_6; // @[ZstdCompressorMemWriter.scala:193:{46,70}, :194:48]
wire [5:0] _ptr_align_max_bytes_writeable_T_8 = _ptr_align_max_bytes_writeable_T_1 ? 6'h2 : _ptr_align_max_bytes_writeable_T_7; // @[ZstdCompressorMemWriter.scala:192:{44,68}, :193:46]
wire [5:0] ptr_align_max_bytes_writeable = _ptr_align_max_bytes_writeable_T ? 6'h1 : _ptr_align_max_bytes_writeable_T_8; // @[ZstdCompressorMemWriter.scala:191:{42,66}, :192:44]
wire [2:0] _ptr_align_max_bytes_writeable_log2_T_5 = {2'h2, ~_ptr_align_max_bytes_writeable_log2_T_4}; // @[ZstdCompressorMemWriter.scala:202:{54,78}]
wire [2:0] _ptr_align_max_bytes_writeable_log2_T_6 = _ptr_align_max_bytes_writeable_log2_T_3 ? 3'h3 : _ptr_align_max_bytes_writeable_log2_T_5; // @[ZstdCompressorMemWriter.scala:201:{52,76}, :202:54]
wire [2:0] _ptr_align_max_bytes_writeable_log2_T_7 = _ptr_align_max_bytes_writeable_log2_T_2 ? 3'h2 : _ptr_align_max_bytes_writeable_log2_T_6; // @[ZstdCompressorMemWriter.scala:200:{50,74}, :201:52]
wire [2:0] _ptr_align_max_bytes_writeable_log2_T_8 = _ptr_align_max_bytes_writeable_log2_T_1 ? 3'h1 : _ptr_align_max_bytes_writeable_log2_T_7; // @[ZstdCompressorMemWriter.scala:199:{48,72}, :200:50]
wire [2:0] ptr_align_max_bytes_writeable_log2 = _ptr_align_max_bytes_writeable_log2_T ? 3'h0 : _ptr_align_max_bytes_writeable_log2_T_8; // @[ZstdCompressorMemWriter.scala:198:{47,71}, :199:48]
wire _count_valids_largest_aligned_T = count_valids[5]; // @[ZstdCompressorMemWriter.scala:163:60, :205:54]
wire _count_valids_largest_aligned_log2_T = count_valids[5]; // @[ZstdCompressorMemWriter.scala:163:60, :205:54, :213:59]
wire _count_valids_largest_aligned_T_1 = count_valids[4]; // @[ZstdCompressorMemWriter.scala:163:60, :206:55]
wire _count_valids_largest_aligned_log2_T_1 = count_valids[4]; // @[ZstdCompressorMemWriter.scala:163:60, :206:55, :214:61]
wire _count_valids_largest_aligned_T_2 = count_valids[3]; // @[ZstdCompressorMemWriter.scala:163:60, :207:57]
wire _count_valids_largest_aligned_log2_T_2 = count_valids[3]; // @[ZstdCompressorMemWriter.scala:163:60, :207:57, :215:63]
wire _count_valids_largest_aligned_T_3 = count_valids[2]; // @[ZstdCompressorMemWriter.scala:163:60, :208:59]
wire _count_valids_largest_aligned_log2_T_3 = count_valids[2]; // @[ZstdCompressorMemWriter.scala:163:60, :208:59, :216:65]
wire _count_valids_largest_aligned_T_4 = count_valids[1]; // @[ZstdCompressorMemWriter.scala:163:60, :209:61]
wire _count_valids_largest_aligned_log2_T_4 = count_valids[1]; // @[ZstdCompressorMemWriter.scala:163:60, :209:61, :217:67]
wire _count_valids_largest_aligned_T_5 = count_valids[0]; // @[ZstdCompressorMemWriter.scala:163:60, :210:63]
wire _count_valids_largest_aligned_log2_T_5 = count_valids[0]; // @[ZstdCompressorMemWriter.scala:163:60, :210:63, :218:69]
wire _count_valids_largest_aligned_T_6 = _count_valids_largest_aligned_T_5; // @[ZstdCompressorMemWriter.scala:210:{50,63}]
wire [1:0] _count_valids_largest_aligned_T_7 = _count_valids_largest_aligned_T_4 ? 2'h2 : {1'h0, _count_valids_largest_aligned_T_6}; // @[ZstdCompressorMemWriter.scala:209:{48,61}, :210:50]
wire [2:0] _count_valids_largest_aligned_T_8 = _count_valids_largest_aligned_T_3 ? 3'h4 : {1'h0, _count_valids_largest_aligned_T_7}; // @[ZstdCompressorMemWriter.scala:208:{46,59}, :209:48]
wire [3:0] _count_valids_largest_aligned_T_9 = _count_valids_largest_aligned_T_2 ? 4'h8 : {1'h0, _count_valids_largest_aligned_T_8}; // @[ZstdCompressorMemWriter.scala:207:{44,57}, :208:46]
wire [4:0] _count_valids_largest_aligned_T_10 = _count_valids_largest_aligned_T_1 ? 5'h10 : {1'h0, _count_valids_largest_aligned_T_9}; // @[ZstdCompressorMemWriter.scala:206:{42,55}, :207:44]
wire [5:0] count_valids_largest_aligned = _count_valids_largest_aligned_T ? 6'h20 : {1'h0, _count_valids_largest_aligned_T_10}; // @[ZstdCompressorMemWriter.scala:205:{41,54}, :206:42]
wire _count_valids_largest_aligned_log2_T_7 = _count_valids_largest_aligned_log2_T_4; // @[ZstdCompressorMemWriter.scala:217:{54,67}]
wire [1:0] _count_valids_largest_aligned_log2_T_8 = _count_valids_largest_aligned_log2_T_3 ? 2'h2 : {1'h0, _count_valids_largest_aligned_log2_T_7}; // @[ZstdCompressorMemWriter.scala:216:{52,65}, :217:54]
wire [1:0] _count_valids_largest_aligned_log2_T_9 = _count_valids_largest_aligned_log2_T_2 ? 2'h3 : _count_valids_largest_aligned_log2_T_8; // @[ZstdCompressorMemWriter.scala:215:{50,63}, :216:52]
wire [2:0] _count_valids_largest_aligned_log2_T_10 = _count_valids_largest_aligned_log2_T_1 ? 3'h4 : {1'h0, _count_valids_largest_aligned_log2_T_9}; // @[ZstdCompressorMemWriter.scala:214:{48,61}, :215:50]
wire [2:0] count_valids_largest_aligned_log2 = _count_valids_largest_aligned_log2_T ? 3'h5 : _count_valids_largest_aligned_log2_T_10; // @[ZstdCompressorMemWriter.scala:213:{46,59}, :214:48]
wire _bytes_to_write_T = ptr_align_max_bytes_writeable < count_valids_largest_aligned; // @[ZstdCompressorMemWriter.scala:191:42, :205:41, :225:35]
wire _bytes_to_write_T_1 = ptr_align_max_bytes_writeable < throttle_end_writeable; // @[ZstdCompressorMemWriter.scala:174:35, :191:42, :226:39]
wire [5:0] _bytes_to_write_T_2 = _bytes_to_write_T_1 ? ptr_align_max_bytes_writeable : throttle_end_writeable; // @[ZstdCompressorMemWriter.scala:174:35, :191:42, :226:{8,39}]
wire _bytes_to_write_T_3 = count_valids_largest_aligned < throttle_end_writeable; // @[ZstdCompressorMemWriter.scala:174:35, :205:41, :229:38]
wire [5:0] _bytes_to_write_T_4 = _bytes_to_write_T_3 ? count_valids_largest_aligned : throttle_end_writeable; // @[ZstdCompressorMemWriter.scala:174:35, :205:41, :229:{8,38}]
wire [5:0] bytes_to_write = _bytes_to_write_T ? _bytes_to_write_T_2 : _bytes_to_write_T_4; // @[ZstdCompressorMemWriter.scala:224:27, :225:35, :226:8, :229:8]
wire [15:0] remapped_write_data_lo_lo_lo_lo = {remapVecData_1, remapVecData_0}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32]
wire [15:0] remapped_write_data_lo_lo_lo_hi = {remapVecData_3, remapVecData_2}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32]
wire [31:0] remapped_write_data_lo_lo_lo = {remapped_write_data_lo_lo_lo_hi, remapped_write_data_lo_lo_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32]
wire [15:0] remapped_write_data_lo_lo_hi_lo = {remapVecData_5, remapVecData_4}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32]
wire [15:0] remapped_write_data_lo_lo_hi_hi = {remapVecData_7, remapVecData_6}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32]
wire [31:0] remapped_write_data_lo_lo_hi = {remapped_write_data_lo_lo_hi_hi, remapped_write_data_lo_lo_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32]
wire [63:0] remapped_write_data_lo_lo = {remapped_write_data_lo_lo_hi, remapped_write_data_lo_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32]
wire [15:0] remapped_write_data_lo_hi_lo_lo = {remapVecData_9, remapVecData_8}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32]
wire [15:0] remapped_write_data_lo_hi_lo_hi = {remapVecData_11, remapVecData_10}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32]
wire [31:0] remapped_write_data_lo_hi_lo = {remapped_write_data_lo_hi_lo_hi, remapped_write_data_lo_hi_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32]
wire [15:0] remapped_write_data_lo_hi_hi_lo = {remapVecData_13, remapVecData_12}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32]
wire [15:0] remapped_write_data_lo_hi_hi_hi = {remapVecData_15, remapVecData_14}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32]
wire [31:0] remapped_write_data_lo_hi_hi = {remapped_write_data_lo_hi_hi_hi, remapped_write_data_lo_hi_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32]
wire [63:0] remapped_write_data_lo_hi = {remapped_write_data_lo_hi_hi, remapped_write_data_lo_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32]
wire [127:0] remapped_write_data_lo = {remapped_write_data_lo_hi, remapped_write_data_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32]
wire [15:0] remapped_write_data_hi_lo_lo_lo = {remapVecData_17, remapVecData_16}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32]
wire [15:0] remapped_write_data_hi_lo_lo_hi = {remapVecData_19, remapVecData_18}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32]
wire [31:0] remapped_write_data_hi_lo_lo = {remapped_write_data_hi_lo_lo_hi, remapped_write_data_hi_lo_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32]
wire [15:0] remapped_write_data_hi_lo_hi_lo = {remapVecData_21, remapVecData_20}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32]
wire [15:0] remapped_write_data_hi_lo_hi_hi = {remapVecData_23, remapVecData_22}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32]
wire [31:0] remapped_write_data_hi_lo_hi = {remapped_write_data_hi_lo_hi_hi, remapped_write_data_hi_lo_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32]
wire [63:0] remapped_write_data_hi_lo = {remapped_write_data_hi_lo_hi, remapped_write_data_hi_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32]
wire [15:0] remapped_write_data_hi_hi_lo_lo = {remapVecData_25, remapVecData_24}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32]
wire [15:0] remapped_write_data_hi_hi_lo_hi = {remapVecData_27, remapVecData_26}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32]
wire [31:0] remapped_write_data_hi_hi_lo = {remapped_write_data_hi_hi_lo_hi, remapped_write_data_hi_hi_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32]
wire [15:0] remapped_write_data_hi_hi_hi_lo = {remapVecData_29, remapVecData_28}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32]
wire [15:0] remapped_write_data_hi_hi_hi_hi = {remapVecData_31, remapVecData_30}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32]
wire [31:0] remapped_write_data_hi_hi_hi = {remapped_write_data_hi_hi_hi_hi, remapped_write_data_hi_hi_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32]
wire [63:0] remapped_write_data_hi_hi = {remapped_write_data_hi_hi_hi, remapped_write_data_hi_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32]
wire [127:0] remapped_write_data_hi = {remapped_write_data_hi_hi, remapped_write_data_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32]
wire [255:0] remapped_write_data = {remapped_write_data_hi, remapped_write_data_lo}; // @[ZstdCompressorMemWriter.scala:233:32]
wire enough_data = |bytes_to_write; // @[ZstdCompressorMemWriter.scala:224:27, :235:36]
wire _bytes_to_write_log2_T = ptr_align_max_bytes_writeable_log2 < count_valids_largest_aligned_log2; // @[ZstdCompressorMemWriter.scala:198:47, :213:46, :238:40]
wire _bytes_to_write_log2_T_1 = ptr_align_max_bytes_writeable_log2 < throttle_end_writeable_log2; // @[ZstdCompressorMemWriter.scala:182:40, :198:47, :239:44]
wire [2:0] _bytes_to_write_log2_T_2 = _bytes_to_write_log2_T_1 ? ptr_align_max_bytes_writeable_log2 : throttle_end_writeable_log2; // @[ZstdCompressorMemWriter.scala:182:40, :198:47, :239:{8,44}]
wire _bytes_to_write_log2_T_3 = count_valids_largest_aligned_log2 < throttle_end_writeable_log2; // @[ZstdCompressorMemWriter.scala:182:40, :213:46, :242:43]
wire [2:0] _bytes_to_write_log2_T_4 = _bytes_to_write_log2_T_3 ? count_valids_largest_aligned_log2 : throttle_end_writeable_log2; // @[ZstdCompressorMemWriter.scala:182:40, :213:46, :242:{8,43}]
wire [2:0] bytes_to_write_log2 = _bytes_to_write_log2_T ? _bytes_to_write_log2_T_2 : _bytes_to_write_log2_T_4; // @[ZstdCompressorMemWriter.scala:237:32, :238:40, :239:8, :242:8]
wire _write_ptr_override_T = _buf_lens_Q_io_deq_bits == backend_bytes_written; // @[ZstdCompressorMemWriter.scala:52:26, :167:38, :247:79]
wire write_ptr_override = _buf_lens_Q_io_deq_valid & _write_ptr_override_T; // @[ZstdCompressorMemWriter.scala:52:26, :247:{52,79}]
wire _remapVecReadys_0_T = |bytes_to_write; // @[ZstdCompressorMemWriter.scala:224:27, :235:36, :264:43]
wire _T_5363 = io_l2io_req_ready_0 & enough_data; // @[Misc.scala:29:18]
wire _remapVecReadys_0_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_0_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_1_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_1_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_2_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_2_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_3_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_3_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_4_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_4_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_5_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_5_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_6_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_6_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_7_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_7_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_8_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_8_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_9_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_9_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_10_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_10_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_11_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_11_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_12_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_12_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_13_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_13_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_14_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_14_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_15_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_15_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_16_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_16_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_17_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_17_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_18_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_18_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_19_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_19_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_20_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_20_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_21_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_21_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_22_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_22_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_23_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_23_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_24_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_24_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_25_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_25_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_26_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_26_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_27_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_27_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_28_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_28_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_29_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_29_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_30_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_30_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_31_T_1; // @[Misc.scala:29:18]
assign _remapVecReadys_31_T_1 = _T_5363; // @[Misc.scala:29:18]
wire _remapVecReadys_0_T_2 = _remapVecReadys_0_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_0_T_3 = _remapVecReadys_0_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_0_T_4 = _remapVecReadys_0_T & _remapVecReadys_0_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_0 = _remapVecReadys_0_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_1_T = |(bytes_to_write[5:1]); // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_1_T_2 = _remapVecReadys_1_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_1_T_3 = _remapVecReadys_1_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_1_T_4 = _remapVecReadys_1_T & _remapVecReadys_1_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_1 = _remapVecReadys_1_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_2_T = bytes_to_write > 6'h2; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_2_T_2 = _remapVecReadys_2_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_2_T_3 = _remapVecReadys_2_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_2_T_4 = _remapVecReadys_2_T & _remapVecReadys_2_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_2 = _remapVecReadys_2_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_3_T = |(bytes_to_write[5:2]); // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_3_T_2 = _remapVecReadys_3_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_3_T_3 = _remapVecReadys_3_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_3_T_4 = _remapVecReadys_3_T & _remapVecReadys_3_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_3 = _remapVecReadys_3_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_4_T = bytes_to_write > 6'h4; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_4_T_2 = _remapVecReadys_4_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_4_T_3 = _remapVecReadys_4_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_4_T_4 = _remapVecReadys_4_T & _remapVecReadys_4_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_4 = _remapVecReadys_4_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_5_T = bytes_to_write > 6'h5; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_5_T_2 = _remapVecReadys_5_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_5_T_3 = _remapVecReadys_5_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_5_T_4 = _remapVecReadys_5_T & _remapVecReadys_5_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_5 = _remapVecReadys_5_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_6_T = bytes_to_write > 6'h6; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_6_T_2 = _remapVecReadys_6_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_6_T_3 = _remapVecReadys_6_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_6_T_4 = _remapVecReadys_6_T & _remapVecReadys_6_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_6 = _remapVecReadys_6_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_7_T = |(bytes_to_write[5:3]); // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_7_T_2 = _remapVecReadys_7_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_7_T_3 = _remapVecReadys_7_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_7_T_4 = _remapVecReadys_7_T & _remapVecReadys_7_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_7 = _remapVecReadys_7_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_8_T = bytes_to_write > 6'h8; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_8_T_2 = _remapVecReadys_8_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_8_T_3 = _remapVecReadys_8_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_8_T_4 = _remapVecReadys_8_T & _remapVecReadys_8_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_8 = _remapVecReadys_8_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_9_T = bytes_to_write > 6'h9; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_9_T_2 = _remapVecReadys_9_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_9_T_3 = _remapVecReadys_9_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_9_T_4 = _remapVecReadys_9_T & _remapVecReadys_9_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_9 = _remapVecReadys_9_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_10_T = bytes_to_write > 6'hA; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_10_T_2 = _remapVecReadys_10_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_10_T_3 = _remapVecReadys_10_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_10_T_4 = _remapVecReadys_10_T & _remapVecReadys_10_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_10 = _remapVecReadys_10_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_11_T = bytes_to_write > 6'hB; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_11_T_2 = _remapVecReadys_11_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_11_T_3 = _remapVecReadys_11_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_11_T_4 = _remapVecReadys_11_T & _remapVecReadys_11_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_11 = _remapVecReadys_11_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_12_T = bytes_to_write > 6'hC; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_12_T_2 = _remapVecReadys_12_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_12_T_3 = _remapVecReadys_12_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_12_T_4 = _remapVecReadys_12_T & _remapVecReadys_12_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_12 = _remapVecReadys_12_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_13_T = bytes_to_write > 6'hD; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_13_T_2 = _remapVecReadys_13_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_13_T_3 = _remapVecReadys_13_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_13_T_4 = _remapVecReadys_13_T & _remapVecReadys_13_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_13 = _remapVecReadys_13_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_14_T = bytes_to_write > 6'hE; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_14_T_2 = _remapVecReadys_14_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_14_T_3 = _remapVecReadys_14_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_14_T_4 = _remapVecReadys_14_T & _remapVecReadys_14_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_14 = _remapVecReadys_14_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_15_T = |(bytes_to_write[5:4]); // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_15_T_2 = _remapVecReadys_15_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_15_T_3 = _remapVecReadys_15_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_15_T_4 = _remapVecReadys_15_T & _remapVecReadys_15_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_15 = _remapVecReadys_15_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_16_T = bytes_to_write > 6'h10; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_16_T_2 = _remapVecReadys_16_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_16_T_3 = _remapVecReadys_16_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_16_T_4 = _remapVecReadys_16_T & _remapVecReadys_16_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_16 = _remapVecReadys_16_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_17_T = bytes_to_write > 6'h11; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_17_T_2 = _remapVecReadys_17_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_17_T_3 = _remapVecReadys_17_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_17_T_4 = _remapVecReadys_17_T & _remapVecReadys_17_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_17 = _remapVecReadys_17_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_18_T = bytes_to_write > 6'h12; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_18_T_2 = _remapVecReadys_18_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_18_T_3 = _remapVecReadys_18_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_18_T_4 = _remapVecReadys_18_T & _remapVecReadys_18_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_18 = _remapVecReadys_18_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_19_T = bytes_to_write > 6'h13; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_19_T_2 = _remapVecReadys_19_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_19_T_3 = _remapVecReadys_19_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_19_T_4 = _remapVecReadys_19_T & _remapVecReadys_19_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_19 = _remapVecReadys_19_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_20_T = bytes_to_write > 6'h14; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_20_T_2 = _remapVecReadys_20_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_20_T_3 = _remapVecReadys_20_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_20_T_4 = _remapVecReadys_20_T & _remapVecReadys_20_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_20 = _remapVecReadys_20_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_21_T = bytes_to_write > 6'h15; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_21_T_2 = _remapVecReadys_21_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_21_T_3 = _remapVecReadys_21_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_21_T_4 = _remapVecReadys_21_T & _remapVecReadys_21_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_21 = _remapVecReadys_21_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_22_T = bytes_to_write > 6'h16; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_22_T_2 = _remapVecReadys_22_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_22_T_3 = _remapVecReadys_22_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_22_T_4 = _remapVecReadys_22_T & _remapVecReadys_22_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_22 = _remapVecReadys_22_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_23_T = bytes_to_write > 6'h17; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_23_T_2 = _remapVecReadys_23_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_23_T_3 = _remapVecReadys_23_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_23_T_4 = _remapVecReadys_23_T & _remapVecReadys_23_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_23 = _remapVecReadys_23_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_24_T = bytes_to_write > 6'h18; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_24_T_2 = _remapVecReadys_24_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_24_T_3 = _remapVecReadys_24_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_24_T_4 = _remapVecReadys_24_T & _remapVecReadys_24_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_24 = _remapVecReadys_24_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_25_T = bytes_to_write > 6'h19; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_25_T_2 = _remapVecReadys_25_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_25_T_3 = _remapVecReadys_25_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_25_T_4 = _remapVecReadys_25_T & _remapVecReadys_25_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_25 = _remapVecReadys_25_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_26_T = bytes_to_write > 6'h1A; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_26_T_2 = _remapVecReadys_26_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_26_T_3 = _remapVecReadys_26_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_26_T_4 = _remapVecReadys_26_T & _remapVecReadys_26_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_26 = _remapVecReadys_26_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_27_T = bytes_to_write > 6'h1B; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_27_T_2 = _remapVecReadys_27_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_27_T_3 = _remapVecReadys_27_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_27_T_4 = _remapVecReadys_27_T & _remapVecReadys_27_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_27 = _remapVecReadys_27_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_28_T = bytes_to_write > 6'h1C; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_28_T_2 = _remapVecReadys_28_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_28_T_3 = _remapVecReadys_28_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_28_T_4 = _remapVecReadys_28_T & _remapVecReadys_28_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_28 = _remapVecReadys_28_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_29_T = bytes_to_write > 6'h1D; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_29_T_2 = _remapVecReadys_29_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_29_T_3 = _remapVecReadys_29_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_29_T_4 = _remapVecReadys_29_T & _remapVecReadys_29_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_29 = _remapVecReadys_29_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_30_T = bytes_to_write > 6'h1E; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_30_T_2 = _remapVecReadys_30_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_30_T_3 = _remapVecReadys_30_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_30_T_4 = _remapVecReadys_30_T & _remapVecReadys_30_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_30 = _remapVecReadys_30_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _remapVecReadys_31_T = bytes_to_write[5]; // @[ZstdCompressorMemWriter.scala:224:27, :264:43]
wire _remapVecReadys_31_T_2 = _remapVecReadys_31_T_1 & ~write_ptr_override; // @[Misc.scala:29:18]
wire _remapVecReadys_31_T_3 = _remapVecReadys_31_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
assign _remapVecReadys_31_T_4 = _remapVecReadys_31_T & _remapVecReadys_31_T_3; // @[Misc.scala:29:18]
assign remapVecReadys_31 = _remapVecReadys_31_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61]
wire _T_5365 = _T_5363 & ~write_ptr_override & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18]
wire [6:0] _read_start_index_T = _remapindex_T + {1'h0, bytes_to_write}; // @[ZstdCompressorMemWriter.scala:153:33, :224:27, :268:43]
wire [6:0] _GEN_123 = _read_start_index_T % 7'h20; // @[ZstdCompressorMemWriter.scala:268:{43,62}]
wire [5:0] _read_start_index_T_1 = _GEN_123[5:0]; // @[ZstdCompressorMemWriter.scala:268:62]
wire [64:0] _backend_bytes_written_T = _GEN_122 + {59'h0, bytes_to_write}; // @[ZstdCompressorMemWriter.scala:168:60, :224:27, :269:52]
wire [63:0] _backend_bytes_written_T_1 = _backend_bytes_written_T[63:0]; // @[ZstdCompressorMemWriter.scala:269:52]
reg [63:0] loginfo_cycles_35; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_70 = {1'h0, loginfo_cycles_35} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_71 = _loginfo_cycles_T_70[63:0]; // @[Util.scala:19:38]
wire _io_l2io_req_valid_T = enough_data & ~write_ptr_override; // @[Misc.scala:26:53]
assign _io_l2io_req_valid_T_1 = _io_l2io_req_valid_T & _dest_info_Q_io_deq_valid; // @[Misc.scala:26:53]
assign io_l2io_req_valid_0 = _io_l2io_req_valid_T_1; // @[Misc.scala:26:53]
assign _io_l2io_req_bits_size_T = write_ptr_override ? 3'h2 : bytes_to_write_log2; // @[ZstdCompressorMemWriter.scala:237:32, :247:52, :282:31]
assign io_l2io_req_bits_size_0 = _io_l2io_req_bits_size_T; // @[ZstdCompressorMemWriter.scala:23:7, :282:31]
assign _io_l2io_req_bits_addr_T = write_ptr_override ? _dest_info_Q_io_deq_bits_cmpflag : backend_next_write_addr; // @[ZstdCompressorMemWriter.scala:39:27, :168:60, :247:52, :283:31]
assign io_l2io_req_bits_addr_0 = _io_l2io_req_bits_addr_T; // @[ZstdCompressorMemWriter.scala:23:7, :283:31]
assign _io_l2io_req_bits_data_T = write_ptr_override ? {192'h0, _dest_info_Q_io_deq_bits_cmpval} : remapped_write_data; // @[ZstdCompressorMemWriter.scala:39:27, :89:{76,90}, :233:32, :247:52, :284:31]
assign io_l2io_req_bits_data_0 = _io_l2io_req_bits_data_T; // @[ZstdCompressorMemWriter.scala:23:7, :284:31]
wire _buf_lens_Q_io_deq_ready_T = io_l2io_req_ready_0 & _write_ptr_override_T; // @[Misc.scala:26:53]
wire _buf_lens_Q_io_deq_ready_T_1 = _buf_lens_Q_io_deq_ready_T & _dest_info_Q_io_deq_valid; // @[Misc.scala:26:53]
wire _dest_info_Q_io_deq_ready_T = io_l2io_req_ready_0 & _buf_lens_Q_io_deq_valid; // @[Misc.scala:26:53]
assign _dest_info_Q_io_deq_ready_T_1 = _dest_info_Q_io_deq_ready_T & _write_ptr_override_T; // @[Misc.scala:26:53]
reg [63:0] bufs_completed; // @[ZstdCompressorMemWriter.scala:290:31]
assign io_bufs_completed = bufs_completed; // @[ZstdCompressorMemWriter.scala:23:7, :290:31]
wire _T_5372 = _dest_info_Q_io_deq_ready_T & _write_ptr_override_T & _dest_info_Q_io_deq_valid; // @[Misc.scala:26:53, :29:18]
wire [64:0] _bufs_completed_T = {1'h0, bufs_completed} + 65'h1; // @[ZstdCompressorMemWriter.scala:290:31, :298:38]
wire [63:0] _bufs_completed_T_1 = _bufs_completed_T[63:0]; // @[ZstdCompressorMemWriter.scala:298:38]
reg [63:0] loginfo_cycles_36; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_72 = {1'h0, loginfo_cycles_36} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_73 = _loginfo_cycles_T_72[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_37; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_74 = {1'h0, loginfo_cycles_37} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_75 = _loginfo_cycles_T_74[63:0]; // @[Util.scala:19:38] |
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_1 :
input clock : Clock
input reset : Reset
output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1)
reg flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, clock
inst q of Queue3_EgressFlit_1
connect q.clock, clock
connect q.reset, reset
connect q.io.enq.valid, io.in[0].valid
connect q.io.enq.bits.head, io.in[0].bits.head
connect q.io.enq.bits.tail, io.in[0].bits.tail
node _q_io_enq_bits_ingress_id_T = eq(UInt<2>(0h3), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1)
node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<4>(0h9), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4)
node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<3>(0h6), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7)
node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<3>(0h5), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10)
node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<4>(0ha), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13)
node _q_io_enq_bits_ingress_id_T_15 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<6>(0h1c), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_16 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<6>(0h22), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_17 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<6>(0h20), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_18 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<6>(0h1e), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_19 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<6>(0h24), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_20 = or(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16)
node _q_io_enq_bits_ingress_id_T_21 = or(_q_io_enq_bits_ingress_id_T_20, _q_io_enq_bits_ingress_id_T_17)
node _q_io_enq_bits_ingress_id_T_22 = or(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_18)
node _q_io_enq_bits_ingress_id_T_23 = or(_q_io_enq_bits_ingress_id_T_22, _q_io_enq_bits_ingress_id_T_19)
wire _q_io_enq_bits_ingress_id_WIRE : UInt<6>
connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_23
connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE
connect q.io.enq.bits.payload, io.in[0].bits.payload
connect io.out.bits, q.io.deq.bits
connect io.out.valid, q.io.deq.valid
connect q.io.deq.ready, io.out.ready
node _T = eq(q.io.enq.ready, UInt<1>(0h0))
node _T_1 = and(q.io.enq.valid, _T)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0))
connect io.credit_available[0], _io_credit_available_0_T
node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0))
connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T
connect io.channel_status[0].flow, flow
node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail)
when _T_6 :
connect channel_empty, UInt<1>(0h1)
when io.allocs[0].alloc :
connect channel_empty, UInt<1>(0h0)
connect flow, io.allocs[0].flow | module EgressUnit_1( // @[EgressUnit.scala:12:7]
input clock, // @[EgressUnit.scala:12:7]
input reset, // @[EgressUnit.scala:12:7]
input io_in_0_valid, // @[EgressUnit.scala:18:14]
input io_in_0_bits_head, // @[EgressUnit.scala:18:14]
input io_in_0_bits_tail, // @[EgressUnit.scala:18:14]
input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14]
input [4:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14]
input [1:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14]
output io_credit_available_0, // @[EgressUnit.scala:18:14]
output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14]
input io_allocs_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14]
input io_out_ready, // @[EgressUnit.scala:18:14]
output io_out_valid, // @[EgressUnit.scala:18:14]
output io_out_bits_head, // @[EgressUnit.scala:18:14]
output io_out_bits_tail, // @[EgressUnit.scala:18:14]
output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14]
);
wire _q_io_enq_ready; // @[EgressUnit.scala:22:17]
wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17]
reg channel_empty; // @[EgressUnit.scala:20:30]
wire _q_io_enq_bits_ingress_id_T_13 = io_in_0_bits_flow_ingress_node_id == 2'h1; // @[EgressUnit.scala:32:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_359 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_359( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module PE_205 :
input clock : Clock
input reset : Reset
output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>}
node _reg_T = eq(io.dir, UInt<1>(0h0))
node _reg_T_1 = mux(_reg_T, io.inR, io.inD)
reg reg : SInt<8>, clock
when io.en :
connect reg, _reg_T_1
connect io.outU, reg
connect io.outL, reg | module PE_205( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IntSyncSyncCrossingSink_n1x1_5 :
output auto : { flip in : { sync : UInt<1>[1]}, out : UInt<1>[1]}
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
wire nodeIn : { sync : UInt<1>[1]}
invalidate nodeIn.sync[0]
wire nodeOut : UInt<1>[1]
invalidate nodeOut[0]
connect auto.out, nodeOut
connect nodeIn, auto.in
connect nodeOut, nodeIn.sync
extmodule plusarg_reader_127 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_128 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module IntSyncSyncCrossingSink_n1x1_5( // @[Crossing.scala:96:9]
input auto_in_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_out_0 // @[LazyModuleImp.scala:107:25]
);
wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9]
wire nodeOut_0; // @[MixedNode.scala:542:17]
wire auto_out_0_0; // @[Crossing.scala:96:9]
assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9]
assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RouteComputer_25 :
input clock : Clock
input reset : Reset
output io : { req : { flip `4` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `3` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}}, resp : { `4` : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `3` : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `2` : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `1` : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `0` : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}}
connect io.req.`0`.ready, UInt<1>(0h1)
node addr_lo = cat(io.req.`0`.bits.flow.egress_node, io.req.`0`.bits.flow.egress_node_id)
node addr_hi_hi = cat(io.req.`0`.bits.flow.vnet_id, io.req.`0`.bits.flow.ingress_node)
node addr_hi = cat(addr_hi_hi, io.req.`0`.bits.flow.ingress_node_id)
node _addr_T = cat(addr_hi, addr_lo)
node addr = cat(io.req.`0`.bits.src_virt_id, _addr_T)
wire decoded_plaInput : UInt<14>
node decoded_invInputs = not(decoded_plaInput)
wire decoded_plaOutput : UInt<8>
node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_plaInput, 12, 12)
node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1)
node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T)
node _decoded_orMatrixOutputs_T = orr(decoded_andMatrixOutputs_0_2)
node decoded_orMatrixOutputs_lo_lo = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T)
node decoded_orMatrixOutputs_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_lo = cat(decoded_orMatrixOutputs_lo_hi, decoded_orMatrixOutputs_lo_lo)
node decoded_orMatrixOutputs_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_hi = cat(decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo)
node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo)
node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0)
node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1)
node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2)
node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3)
node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs, 4, 4)
node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs, 5, 5)
node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs, 6, 6)
node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs, 7, 7)
node decoded_invMatrixOutputs_lo_lo = cat(_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T)
node decoded_invMatrixOutputs_lo_hi = cat(_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2)
node decoded_invMatrixOutputs_lo = cat(decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo)
node decoded_invMatrixOutputs_hi_lo = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4)
node decoded_invMatrixOutputs_hi_hi = cat(_decoded_invMatrixOutputs_T_7, _decoded_invMatrixOutputs_T_6)
node decoded_invMatrixOutputs_hi = cat(decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo)
node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo)
connect decoded_plaOutput, decoded_invMatrixOutputs
connect decoded_plaInput, addr
node _decoded_T = shl(UInt<4>(0hf), 4)
node _decoded_T_1 = xor(UInt<8>(0hff), _decoded_T)
node _decoded_T_2 = shr(decoded_plaOutput, 4)
node _decoded_T_3 = and(_decoded_T_2, _decoded_T_1)
node _decoded_T_4 = bits(decoded_plaOutput, 3, 0)
node _decoded_T_5 = shl(_decoded_T_4, 4)
node _decoded_T_6 = not(_decoded_T_1)
node _decoded_T_7 = and(_decoded_T_5, _decoded_T_6)
node _decoded_T_8 = or(_decoded_T_3, _decoded_T_7)
node _decoded_T_9 = bits(_decoded_T_1, 5, 0)
node _decoded_T_10 = shl(_decoded_T_9, 2)
node _decoded_T_11 = xor(_decoded_T_1, _decoded_T_10)
node _decoded_T_12 = shr(_decoded_T_8, 2)
node _decoded_T_13 = and(_decoded_T_12, _decoded_T_11)
node _decoded_T_14 = bits(_decoded_T_8, 5, 0)
node _decoded_T_15 = shl(_decoded_T_14, 2)
node _decoded_T_16 = not(_decoded_T_11)
node _decoded_T_17 = and(_decoded_T_15, _decoded_T_16)
node _decoded_T_18 = or(_decoded_T_13, _decoded_T_17)
node _decoded_T_19 = bits(_decoded_T_11, 6, 0)
node _decoded_T_20 = shl(_decoded_T_19, 1)
node _decoded_T_21 = xor(_decoded_T_11, _decoded_T_20)
node _decoded_T_22 = shr(_decoded_T_18, 1)
node _decoded_T_23 = and(_decoded_T_22, _decoded_T_21)
node _decoded_T_24 = bits(_decoded_T_18, 6, 0)
node _decoded_T_25 = shl(_decoded_T_24, 1)
node _decoded_T_26 = not(_decoded_T_21)
node _decoded_T_27 = and(_decoded_T_25, _decoded_T_26)
node decoded = or(_decoded_T_23, _decoded_T_27)
node _io_resp_0_vc_sel_0_0_T = bits(decoded, 0, 0)
connect io.resp.`0`.vc_sel.`0`[0], _io_resp_0_vc_sel_0_0_T
node _io_resp_0_vc_sel_0_1_T = bits(decoded, 1, 1)
connect io.resp.`0`.vc_sel.`0`[1], _io_resp_0_vc_sel_0_1_T
node _io_resp_0_vc_sel_1_0_T = bits(decoded, 2, 2)
connect io.resp.`0`.vc_sel.`1`[0], _io_resp_0_vc_sel_1_0_T
node _io_resp_0_vc_sel_1_1_T = bits(decoded, 3, 3)
connect io.resp.`0`.vc_sel.`1`[1], _io_resp_0_vc_sel_1_1_T
node _io_resp_0_vc_sel_2_0_T = bits(decoded, 4, 4)
connect io.resp.`0`.vc_sel.`2`[0], _io_resp_0_vc_sel_2_0_T
node _io_resp_0_vc_sel_2_1_T = bits(decoded, 5, 5)
connect io.resp.`0`.vc_sel.`2`[1], _io_resp_0_vc_sel_2_1_T
node _io_resp_0_vc_sel_3_0_T = bits(decoded, 6, 6)
connect io.resp.`0`.vc_sel.`3`[0], _io_resp_0_vc_sel_3_0_T
node _io_resp_0_vc_sel_3_1_T = bits(decoded, 7, 7)
connect io.resp.`0`.vc_sel.`3`[1], _io_resp_0_vc_sel_3_1_T
connect io.resp.`0`.vc_sel.`4`[0], UInt<1>(0h0)
connect io.req.`1`.ready, UInt<1>(0h1)
node addr_lo_1 = cat(io.req.`1`.bits.flow.egress_node, io.req.`1`.bits.flow.egress_node_id)
node addr_hi_hi_1 = cat(io.req.`1`.bits.flow.vnet_id, io.req.`1`.bits.flow.ingress_node)
node addr_hi_1 = cat(addr_hi_hi_1, io.req.`1`.bits.flow.ingress_node_id)
node _addr_T_1 = cat(addr_hi_1, addr_lo_1)
node addr_1 = cat(io.req.`1`.bits.src_virt_id, _addr_T_1)
wire decoded_plaInput_1 : UInt<14>
node decoded_invInputs_1 = not(decoded_plaInput_1)
wire decoded_plaOutput_1 : UInt<8>
node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_plaInput_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_invInputs_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_invInputs_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_plaInput_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_9, decoded_andMatrixOutputs_andMatrixInput_10)
node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7)
node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_8)
node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo)
node decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4)
node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5)
node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1)
node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2)
node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo)
node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo)
node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_1)
node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_plaInput_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_plaInput_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_invInputs_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_plaInput_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10_1)
node decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1)
node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_8_1)
node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1)
node decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1)
node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_1)
node decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2)
node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1)
node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1)
node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1)
node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_2)
node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_plaInput_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_invInputs_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_invInputs_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_plaInput_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_9_2, decoded_andMatrixOutputs_andMatrixInput_10_2)
node decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_andMatrixOutputs_andMatrixInput_7_2)
node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_8_2)
node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2)
node decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_andMatrixOutputs_andMatrixInput_4_2)
node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_andMatrixInput_5_2)
node decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3)
node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_2)
node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2)
node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2)
node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_3)
node _decoded_orMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_1_2, decoded_andMatrixOutputs_2_2)
node _decoded_orMatrixOutputs_T_2 = orr(_decoded_orMatrixOutputs_T_1)
node _decoded_orMatrixOutputs_T_3 = orr(decoded_andMatrixOutputs_0_2_1)
node decoded_orMatrixOutputs_lo_lo_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_hi_1 = cat(_decoded_orMatrixOutputs_T_2, UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_1 = cat(decoded_orMatrixOutputs_lo_hi_1, decoded_orMatrixOutputs_lo_lo_1)
node decoded_orMatrixOutputs_hi_lo_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_3, UInt<1>(0h0))
node decoded_orMatrixOutputs_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1)
node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1)
node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs_1, 0, 0)
node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs_1, 1, 1)
node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs_1, 2, 2)
node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs_1, 3, 3)
node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs_1, 4, 4)
node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs_1, 5, 5)
node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs_1, 6, 6)
node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs_1, 7, 7)
node decoded_invMatrixOutputs_lo_lo_1 = cat(_decoded_invMatrixOutputs_T_9, _decoded_invMatrixOutputs_T_8)
node decoded_invMatrixOutputs_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_11, _decoded_invMatrixOutputs_T_10)
node decoded_invMatrixOutputs_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1)
node decoded_invMatrixOutputs_hi_lo_1 = cat(_decoded_invMatrixOutputs_T_13, _decoded_invMatrixOutputs_T_12)
node decoded_invMatrixOutputs_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_15, _decoded_invMatrixOutputs_T_14)
node decoded_invMatrixOutputs_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1)
node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1)
connect decoded_plaOutput_1, decoded_invMatrixOutputs_1
connect decoded_plaInput_1, addr_1
node _decoded_T_28 = shl(UInt<4>(0hf), 4)
node _decoded_T_29 = xor(UInt<8>(0hff), _decoded_T_28)
node _decoded_T_30 = shr(decoded_plaOutput_1, 4)
node _decoded_T_31 = and(_decoded_T_30, _decoded_T_29)
node _decoded_T_32 = bits(decoded_plaOutput_1, 3, 0)
node _decoded_T_33 = shl(_decoded_T_32, 4)
node _decoded_T_34 = not(_decoded_T_29)
node _decoded_T_35 = and(_decoded_T_33, _decoded_T_34)
node _decoded_T_36 = or(_decoded_T_31, _decoded_T_35)
node _decoded_T_37 = bits(_decoded_T_29, 5, 0)
node _decoded_T_38 = shl(_decoded_T_37, 2)
node _decoded_T_39 = xor(_decoded_T_29, _decoded_T_38)
node _decoded_T_40 = shr(_decoded_T_36, 2)
node _decoded_T_41 = and(_decoded_T_40, _decoded_T_39)
node _decoded_T_42 = bits(_decoded_T_36, 5, 0)
node _decoded_T_43 = shl(_decoded_T_42, 2)
node _decoded_T_44 = not(_decoded_T_39)
node _decoded_T_45 = and(_decoded_T_43, _decoded_T_44)
node _decoded_T_46 = or(_decoded_T_41, _decoded_T_45)
node _decoded_T_47 = bits(_decoded_T_39, 6, 0)
node _decoded_T_48 = shl(_decoded_T_47, 1)
node _decoded_T_49 = xor(_decoded_T_39, _decoded_T_48)
node _decoded_T_50 = shr(_decoded_T_46, 1)
node _decoded_T_51 = and(_decoded_T_50, _decoded_T_49)
node _decoded_T_52 = bits(_decoded_T_46, 6, 0)
node _decoded_T_53 = shl(_decoded_T_52, 1)
node _decoded_T_54 = not(_decoded_T_49)
node _decoded_T_55 = and(_decoded_T_53, _decoded_T_54)
node decoded_1 = or(_decoded_T_51, _decoded_T_55)
node _io_resp_1_vc_sel_0_0_T = bits(decoded_1, 0, 0)
connect io.resp.`1`.vc_sel.`0`[0], _io_resp_1_vc_sel_0_0_T
node _io_resp_1_vc_sel_0_1_T = bits(decoded_1, 1, 1)
connect io.resp.`1`.vc_sel.`0`[1], _io_resp_1_vc_sel_0_1_T
node _io_resp_1_vc_sel_1_0_T = bits(decoded_1, 2, 2)
connect io.resp.`1`.vc_sel.`1`[0], _io_resp_1_vc_sel_1_0_T
node _io_resp_1_vc_sel_1_1_T = bits(decoded_1, 3, 3)
connect io.resp.`1`.vc_sel.`1`[1], _io_resp_1_vc_sel_1_1_T
node _io_resp_1_vc_sel_2_0_T = bits(decoded_1, 4, 4)
connect io.resp.`1`.vc_sel.`2`[0], _io_resp_1_vc_sel_2_0_T
node _io_resp_1_vc_sel_2_1_T = bits(decoded_1, 5, 5)
connect io.resp.`1`.vc_sel.`2`[1], _io_resp_1_vc_sel_2_1_T
node _io_resp_1_vc_sel_3_0_T = bits(decoded_1, 6, 6)
connect io.resp.`1`.vc_sel.`3`[0], _io_resp_1_vc_sel_3_0_T
node _io_resp_1_vc_sel_3_1_T = bits(decoded_1, 7, 7)
connect io.resp.`1`.vc_sel.`3`[1], _io_resp_1_vc_sel_3_1_T
connect io.resp.`1`.vc_sel.`4`[0], UInt<1>(0h0)
connect io.req.`2`.ready, UInt<1>(0h1)
node addr_lo_2 = cat(io.req.`2`.bits.flow.egress_node, io.req.`2`.bits.flow.egress_node_id)
node addr_hi_hi_2 = cat(io.req.`2`.bits.flow.vnet_id, io.req.`2`.bits.flow.ingress_node)
node addr_hi_2 = cat(addr_hi_hi_2, io.req.`2`.bits.flow.ingress_node_id)
node _addr_T_2 = cat(addr_hi_2, addr_lo_2)
node addr_2 = cat(io.req.`2`.bits.src_virt_id, _addr_T_2)
wire decoded_plaInput_2 : UInt<14>
node decoded_invInputs_2 = not(decoded_plaInput_2)
wire decoded_plaOutput_2 : UInt<8>
node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_1_2_1 = andr(decoded_andMatrixOutputs_andMatrixInput_0_4)
node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_plaInput_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_7_3, decoded_andMatrixOutputs_andMatrixInput_8_3)
node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3)
node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3)
node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3)
node decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_4)
node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_3)
node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3)
node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3)
node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_4)
node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_invInputs_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_plaInput_2, 12, 12)
node decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_8_4, decoded_andMatrixOutputs_andMatrixInput_9_3)
node decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_5_4, decoded_andMatrixOutputs_andMatrixInput_6_4)
node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_7_4)
node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4)
node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_4)
node decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_5)
node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_andMatrixInput_2_4)
node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4)
node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4)
node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_5)
node decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_invInputs_2, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_invInputs_2, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_plaInput_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_plaInput_2, 12, 12)
node decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_3)
node decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_11)
node decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_andMatrixOutputs_andMatrixInput_7_5)
node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_andMatrixInput_8_5)
node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5)
node decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5)
node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_5_5)
node decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_6)
node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_5)
node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5)
node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5)
node decoded_andMatrixOutputs_2_2_1 = andr(_decoded_andMatrixOutputs_T_6)
node decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_invInputs_2, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_invInputs_2, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_plaInput_2, 12, 12)
node decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_andMatrixOutputs_andMatrixInput_10_4)
node decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_11_1)
node decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6)
node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_8_6)
node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6)
node decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_6)
node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_5_6)
node decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_7)
node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_6)
node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6)
node _decoded_andMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6)
node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_7)
node decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_plaInput_2, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_invInputs_2, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_plaInput_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_plaInput_2, 12, 12)
node decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_andMatrixOutputs_andMatrixInput_10_5)
node decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_andMatrixInput_11_2)
node decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7)
node decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_8_7)
node decoded_andMatrixOutputs_lo_7 = cat(decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7)
node decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_andMatrixOutputs_andMatrixInput_4_7)
node decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_andMatrixInput_5_7)
node decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_8)
node decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_7)
node decoded_andMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7)
node _decoded_andMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7)
node decoded_andMatrixOutputs_0_2_2 = andr(_decoded_andMatrixOutputs_T_8)
node _decoded_orMatrixOutputs_T_4 = orr(decoded_andMatrixOutputs_0_2_2)
node decoded_orMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_1_2_1, decoded_andMatrixOutputs_2_2_1)
node _decoded_orMatrixOutputs_T_5 = cat(decoded_orMatrixOutputs_hi_2, decoded_andMatrixOutputs_3_2)
node _decoded_orMatrixOutputs_T_6 = orr(_decoded_orMatrixOutputs_T_5)
node _decoded_orMatrixOutputs_T_7 = orr(decoded_andMatrixOutputs_5_2)
node _decoded_orMatrixOutputs_T_8 = orr(decoded_andMatrixOutputs_4_2)
node decoded_orMatrixOutputs_lo_lo_2 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_4)
node decoded_orMatrixOutputs_lo_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_2 = cat(decoded_orMatrixOutputs_lo_hi_2, decoded_orMatrixOutputs_lo_lo_2)
node decoded_orMatrixOutputs_hi_lo_2 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_6)
node decoded_orMatrixOutputs_hi_hi_2 = cat(_decoded_orMatrixOutputs_T_8, _decoded_orMatrixOutputs_T_7)
node decoded_orMatrixOutputs_hi_3 = cat(decoded_orMatrixOutputs_hi_hi_2, decoded_orMatrixOutputs_hi_lo_2)
node decoded_orMatrixOutputs_2 = cat(decoded_orMatrixOutputs_hi_3, decoded_orMatrixOutputs_lo_2)
node _decoded_invMatrixOutputs_T_16 = bits(decoded_orMatrixOutputs_2, 0, 0)
node _decoded_invMatrixOutputs_T_17 = bits(decoded_orMatrixOutputs_2, 1, 1)
node _decoded_invMatrixOutputs_T_18 = bits(decoded_orMatrixOutputs_2, 2, 2)
node _decoded_invMatrixOutputs_T_19 = bits(decoded_orMatrixOutputs_2, 3, 3)
node _decoded_invMatrixOutputs_T_20 = bits(decoded_orMatrixOutputs_2, 4, 4)
node _decoded_invMatrixOutputs_T_21 = bits(decoded_orMatrixOutputs_2, 5, 5)
node _decoded_invMatrixOutputs_T_22 = bits(decoded_orMatrixOutputs_2, 6, 6)
node _decoded_invMatrixOutputs_T_23 = bits(decoded_orMatrixOutputs_2, 7, 7)
node decoded_invMatrixOutputs_lo_lo_2 = cat(_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16)
node decoded_invMatrixOutputs_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_19, _decoded_invMatrixOutputs_T_18)
node decoded_invMatrixOutputs_lo_2 = cat(decoded_invMatrixOutputs_lo_hi_2, decoded_invMatrixOutputs_lo_lo_2)
node decoded_invMatrixOutputs_hi_lo_2 = cat(_decoded_invMatrixOutputs_T_21, _decoded_invMatrixOutputs_T_20)
node decoded_invMatrixOutputs_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_23, _decoded_invMatrixOutputs_T_22)
node decoded_invMatrixOutputs_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_2, decoded_invMatrixOutputs_hi_lo_2)
node decoded_invMatrixOutputs_2 = cat(decoded_invMatrixOutputs_hi_2, decoded_invMatrixOutputs_lo_2)
connect decoded_plaOutput_2, decoded_invMatrixOutputs_2
connect decoded_plaInput_2, addr_2
node _decoded_T_56 = shl(UInt<4>(0hf), 4)
node _decoded_T_57 = xor(UInt<8>(0hff), _decoded_T_56)
node _decoded_T_58 = shr(decoded_plaOutput_2, 4)
node _decoded_T_59 = and(_decoded_T_58, _decoded_T_57)
node _decoded_T_60 = bits(decoded_plaOutput_2, 3, 0)
node _decoded_T_61 = shl(_decoded_T_60, 4)
node _decoded_T_62 = not(_decoded_T_57)
node _decoded_T_63 = and(_decoded_T_61, _decoded_T_62)
node _decoded_T_64 = or(_decoded_T_59, _decoded_T_63)
node _decoded_T_65 = bits(_decoded_T_57, 5, 0)
node _decoded_T_66 = shl(_decoded_T_65, 2)
node _decoded_T_67 = xor(_decoded_T_57, _decoded_T_66)
node _decoded_T_68 = shr(_decoded_T_64, 2)
node _decoded_T_69 = and(_decoded_T_68, _decoded_T_67)
node _decoded_T_70 = bits(_decoded_T_64, 5, 0)
node _decoded_T_71 = shl(_decoded_T_70, 2)
node _decoded_T_72 = not(_decoded_T_67)
node _decoded_T_73 = and(_decoded_T_71, _decoded_T_72)
node _decoded_T_74 = or(_decoded_T_69, _decoded_T_73)
node _decoded_T_75 = bits(_decoded_T_67, 6, 0)
node _decoded_T_76 = shl(_decoded_T_75, 1)
node _decoded_T_77 = xor(_decoded_T_67, _decoded_T_76)
node _decoded_T_78 = shr(_decoded_T_74, 1)
node _decoded_T_79 = and(_decoded_T_78, _decoded_T_77)
node _decoded_T_80 = bits(_decoded_T_74, 6, 0)
node _decoded_T_81 = shl(_decoded_T_80, 1)
node _decoded_T_82 = not(_decoded_T_77)
node _decoded_T_83 = and(_decoded_T_81, _decoded_T_82)
node decoded_2 = or(_decoded_T_79, _decoded_T_83)
node _io_resp_2_vc_sel_0_0_T = bits(decoded_2, 0, 0)
connect io.resp.`2`.vc_sel.`0`[0], _io_resp_2_vc_sel_0_0_T
node _io_resp_2_vc_sel_0_1_T = bits(decoded_2, 1, 1)
connect io.resp.`2`.vc_sel.`0`[1], _io_resp_2_vc_sel_0_1_T
node _io_resp_2_vc_sel_1_0_T = bits(decoded_2, 2, 2)
connect io.resp.`2`.vc_sel.`1`[0], _io_resp_2_vc_sel_1_0_T
node _io_resp_2_vc_sel_1_1_T = bits(decoded_2, 3, 3)
connect io.resp.`2`.vc_sel.`1`[1], _io_resp_2_vc_sel_1_1_T
node _io_resp_2_vc_sel_2_0_T = bits(decoded_2, 4, 4)
connect io.resp.`2`.vc_sel.`2`[0], _io_resp_2_vc_sel_2_0_T
node _io_resp_2_vc_sel_2_1_T = bits(decoded_2, 5, 5)
connect io.resp.`2`.vc_sel.`2`[1], _io_resp_2_vc_sel_2_1_T
node _io_resp_2_vc_sel_3_0_T = bits(decoded_2, 6, 6)
connect io.resp.`2`.vc_sel.`3`[0], _io_resp_2_vc_sel_3_0_T
node _io_resp_2_vc_sel_3_1_T = bits(decoded_2, 7, 7)
connect io.resp.`2`.vc_sel.`3`[1], _io_resp_2_vc_sel_3_1_T
connect io.resp.`2`.vc_sel.`4`[0], UInt<1>(0h0)
connect io.req.`3`.ready, UInt<1>(0h1)
node addr_lo_3 = cat(io.req.`3`.bits.flow.egress_node, io.req.`3`.bits.flow.egress_node_id)
node addr_hi_hi_3 = cat(io.req.`3`.bits.flow.vnet_id, io.req.`3`.bits.flow.ingress_node)
node addr_hi_3 = cat(addr_hi_hi_3, io.req.`3`.bits.flow.ingress_node_id)
node _addr_T_3 = cat(addr_hi_3, addr_lo_3)
node addr_3 = cat(io.req.`3`.bits.src_virt_id, _addr_T_3)
wire decoded_plaInput_3 : UInt<14>
node decoded_invInputs_3 = not(decoded_plaInput_3)
wire decoded_plaOutput_3 : UInt<8>
node decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_plaInput_3, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_invInputs_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_7_8, decoded_andMatrixOutputs_andMatrixInput_8_8)
node decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_5_8, decoded_andMatrixOutputs_andMatrixInput_6_8)
node decoded_andMatrixOutputs_lo_8 = cat(decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8)
node decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_8)
node decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_9)
node decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_2_8)
node decoded_andMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8)
node _decoded_andMatrixOutputs_T_9 = cat(decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8)
node decoded_andMatrixOutputs_0_2_3 = andr(_decoded_andMatrixOutputs_T_9)
node _decoded_orMatrixOutputs_T_9 = orr(decoded_andMatrixOutputs_0_2_3)
node decoded_orMatrixOutputs_lo_lo_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_hi_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_3 = cat(decoded_orMatrixOutputs_lo_hi_3, decoded_orMatrixOutputs_lo_lo_3)
node decoded_orMatrixOutputs_hi_lo_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_hi_hi_3 = cat(_decoded_orMatrixOutputs_T_9, UInt<1>(0h0))
node decoded_orMatrixOutputs_hi_4 = cat(decoded_orMatrixOutputs_hi_hi_3, decoded_orMatrixOutputs_hi_lo_3)
node decoded_orMatrixOutputs_3 = cat(decoded_orMatrixOutputs_hi_4, decoded_orMatrixOutputs_lo_3)
node _decoded_invMatrixOutputs_T_24 = bits(decoded_orMatrixOutputs_3, 0, 0)
node _decoded_invMatrixOutputs_T_25 = bits(decoded_orMatrixOutputs_3, 1, 1)
node _decoded_invMatrixOutputs_T_26 = bits(decoded_orMatrixOutputs_3, 2, 2)
node _decoded_invMatrixOutputs_T_27 = bits(decoded_orMatrixOutputs_3, 3, 3)
node _decoded_invMatrixOutputs_T_28 = bits(decoded_orMatrixOutputs_3, 4, 4)
node _decoded_invMatrixOutputs_T_29 = bits(decoded_orMatrixOutputs_3, 5, 5)
node _decoded_invMatrixOutputs_T_30 = bits(decoded_orMatrixOutputs_3, 6, 6)
node _decoded_invMatrixOutputs_T_31 = bits(decoded_orMatrixOutputs_3, 7, 7)
node decoded_invMatrixOutputs_lo_lo_3 = cat(_decoded_invMatrixOutputs_T_25, _decoded_invMatrixOutputs_T_24)
node decoded_invMatrixOutputs_lo_hi_3 = cat(_decoded_invMatrixOutputs_T_27, _decoded_invMatrixOutputs_T_26)
node decoded_invMatrixOutputs_lo_3 = cat(decoded_invMatrixOutputs_lo_hi_3, decoded_invMatrixOutputs_lo_lo_3)
node decoded_invMatrixOutputs_hi_lo_3 = cat(_decoded_invMatrixOutputs_T_29, _decoded_invMatrixOutputs_T_28)
node decoded_invMatrixOutputs_hi_hi_3 = cat(_decoded_invMatrixOutputs_T_31, _decoded_invMatrixOutputs_T_30)
node decoded_invMatrixOutputs_hi_3 = cat(decoded_invMatrixOutputs_hi_hi_3, decoded_invMatrixOutputs_hi_lo_3)
node decoded_invMatrixOutputs_3 = cat(decoded_invMatrixOutputs_hi_3, decoded_invMatrixOutputs_lo_3)
connect decoded_plaOutput_3, decoded_invMatrixOutputs_3
connect decoded_plaInput_3, addr_3
node _decoded_T_84 = shl(UInt<4>(0hf), 4)
node _decoded_T_85 = xor(UInt<8>(0hff), _decoded_T_84)
node _decoded_T_86 = shr(decoded_plaOutput_3, 4)
node _decoded_T_87 = and(_decoded_T_86, _decoded_T_85)
node _decoded_T_88 = bits(decoded_plaOutput_3, 3, 0)
node _decoded_T_89 = shl(_decoded_T_88, 4)
node _decoded_T_90 = not(_decoded_T_85)
node _decoded_T_91 = and(_decoded_T_89, _decoded_T_90)
node _decoded_T_92 = or(_decoded_T_87, _decoded_T_91)
node _decoded_T_93 = bits(_decoded_T_85, 5, 0)
node _decoded_T_94 = shl(_decoded_T_93, 2)
node _decoded_T_95 = xor(_decoded_T_85, _decoded_T_94)
node _decoded_T_96 = shr(_decoded_T_92, 2)
node _decoded_T_97 = and(_decoded_T_96, _decoded_T_95)
node _decoded_T_98 = bits(_decoded_T_92, 5, 0)
node _decoded_T_99 = shl(_decoded_T_98, 2)
node _decoded_T_100 = not(_decoded_T_95)
node _decoded_T_101 = and(_decoded_T_99, _decoded_T_100)
node _decoded_T_102 = or(_decoded_T_97, _decoded_T_101)
node _decoded_T_103 = bits(_decoded_T_95, 6, 0)
node _decoded_T_104 = shl(_decoded_T_103, 1)
node _decoded_T_105 = xor(_decoded_T_95, _decoded_T_104)
node _decoded_T_106 = shr(_decoded_T_102, 1)
node _decoded_T_107 = and(_decoded_T_106, _decoded_T_105)
node _decoded_T_108 = bits(_decoded_T_102, 6, 0)
node _decoded_T_109 = shl(_decoded_T_108, 1)
node _decoded_T_110 = not(_decoded_T_105)
node _decoded_T_111 = and(_decoded_T_109, _decoded_T_110)
node decoded_3 = or(_decoded_T_107, _decoded_T_111)
node _io_resp_3_vc_sel_0_0_T = bits(decoded_3, 0, 0)
connect io.resp.`3`.vc_sel.`0`[0], _io_resp_3_vc_sel_0_0_T
node _io_resp_3_vc_sel_0_1_T = bits(decoded_3, 1, 1)
connect io.resp.`3`.vc_sel.`0`[1], _io_resp_3_vc_sel_0_1_T
node _io_resp_3_vc_sel_1_0_T = bits(decoded_3, 2, 2)
connect io.resp.`3`.vc_sel.`1`[0], _io_resp_3_vc_sel_1_0_T
node _io_resp_3_vc_sel_1_1_T = bits(decoded_3, 3, 3)
connect io.resp.`3`.vc_sel.`1`[1], _io_resp_3_vc_sel_1_1_T
node _io_resp_3_vc_sel_2_0_T = bits(decoded_3, 4, 4)
connect io.resp.`3`.vc_sel.`2`[0], _io_resp_3_vc_sel_2_0_T
node _io_resp_3_vc_sel_2_1_T = bits(decoded_3, 5, 5)
connect io.resp.`3`.vc_sel.`2`[1], _io_resp_3_vc_sel_2_1_T
node _io_resp_3_vc_sel_3_0_T = bits(decoded_3, 6, 6)
connect io.resp.`3`.vc_sel.`3`[0], _io_resp_3_vc_sel_3_0_T
node _io_resp_3_vc_sel_3_1_T = bits(decoded_3, 7, 7)
connect io.resp.`3`.vc_sel.`3`[1], _io_resp_3_vc_sel_3_1_T
connect io.resp.`3`.vc_sel.`4`[0], UInt<1>(0h0)
connect io.req.`4`.ready, UInt<1>(0h1)
node addr_lo_4 = cat(io.req.`4`.bits.flow.egress_node, io.req.`4`.bits.flow.egress_node_id)
node addr_hi_hi_4 = cat(io.req.`4`.bits.flow.vnet_id, io.req.`4`.bits.flow.ingress_node)
node addr_hi_4 = cat(addr_hi_hi_4, io.req.`4`.bits.flow.ingress_node_id)
node _addr_T_4 = cat(addr_hi_4, addr_lo_4)
node addr_4 = cat(io.req.`4`.bits.src_virt_id, _addr_T_4)
wire decoded_plaInput_4 : UInt<14>
node decoded_invInputs_4 = not(decoded_plaInput_4)
wire decoded_plaOutput_4 : UInt<8>
node decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_invInputs_4, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_plaInput_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_invInputs_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_plaInput_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_andMatrixOutputs_andMatrixInput_10_6)
node decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_11_3)
node decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_andMatrixOutputs_andMatrixInput_7_9)
node decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_8_9)
node decoded_andMatrixOutputs_lo_9 = cat(decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9)
node decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_andMatrixOutputs_andMatrixInput_4_9)
node decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_andMatrixOutputs_hi_lo_hi_6, decoded_andMatrixOutputs_andMatrixInput_5_9)
node decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_10)
node decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_9)
node decoded_andMatrixOutputs_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9)
node _decoded_andMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9)
node decoded_andMatrixOutputs_3_2_1 = andr(_decoded_andMatrixOutputs_T_10)
node decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_plaInput_4, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_plaInput_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_invInputs_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_plaInput_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_andMatrixOutputs_andMatrixInput_10_7)
node decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_11_4)
node decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_andMatrixOutputs_andMatrixInput_7_10)
node decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_8_10)
node decoded_andMatrixOutputs_lo_10 = cat(decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10)
node decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10)
node decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_andMatrixOutputs_hi_lo_hi_7, decoded_andMatrixOutputs_andMatrixInput_5_10)
node decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_11)
node decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_andMatrixInput_2_10)
node decoded_andMatrixOutputs_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10)
node _decoded_andMatrixOutputs_T_11 = cat(decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10)
node decoded_andMatrixOutputs_0_2_4 = andr(_decoded_andMatrixOutputs_T_11)
node decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_plaInput_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_plaInput_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_invInputs_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_plaInput_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_andMatrixOutputs_andMatrixInput_10_8)
node decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_andMatrixOutputs_andMatrixInput_7_11)
node decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_8_11)
node decoded_andMatrixOutputs_lo_11 = cat(decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11)
node decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_andMatrixOutputs_andMatrixInput_4_11)
node decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_andMatrixOutputs_hi_lo_hi_8, decoded_andMatrixOutputs_andMatrixInput_5_11)
node decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_12)
node decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_2_11)
node decoded_andMatrixOutputs_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11)
node _decoded_andMatrixOutputs_T_12 = cat(decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11)
node decoded_andMatrixOutputs_2_2_2 = andr(_decoded_andMatrixOutputs_T_12)
node decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_invInputs_4, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoded_plaInput_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoded_invInputs_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_plaInput_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_9)
node decoded_andMatrixOutputs_lo_lo_12 = cat(decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_andMatrixInput_11_5)
node decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_6_12, decoded_andMatrixOutputs_andMatrixInput_7_12)
node decoded_andMatrixOutputs_lo_hi_12 = cat(decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_andMatrixInput_8_12)
node decoded_andMatrixOutputs_lo_12 = cat(decoded_andMatrixOutputs_lo_hi_12, decoded_andMatrixOutputs_lo_lo_12)
node decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_andMatrixOutputs_andMatrixInput_4_12)
node decoded_andMatrixOutputs_hi_lo_12 = cat(decoded_andMatrixOutputs_hi_lo_hi_9, decoded_andMatrixOutputs_andMatrixInput_5_12)
node decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_andMatrixOutputs_andMatrixInput_1_13)
node decoded_andMatrixOutputs_hi_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_hi_12, decoded_andMatrixOutputs_andMatrixInput_2_12)
node decoded_andMatrixOutputs_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_12, decoded_andMatrixOutputs_hi_lo_12)
node _decoded_andMatrixOutputs_T_13 = cat(decoded_andMatrixOutputs_hi_12, decoded_andMatrixOutputs_lo_12)
node decoded_andMatrixOutputs_1_2_2 = andr(_decoded_andMatrixOutputs_T_13)
node decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoded_invInputs_4, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoded_plaInput_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoded_plaInput_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(decoded_invInputs_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_plaInput_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_lo_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_9_11, decoded_andMatrixOutputs_andMatrixInput_10_10)
node decoded_andMatrixOutputs_lo_lo_13 = cat(decoded_andMatrixOutputs_lo_lo_hi_6, decoded_andMatrixOutputs_andMatrixInput_11_6)
node decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_andMatrixOutputs_andMatrixInput_7_13)
node decoded_andMatrixOutputs_lo_hi_13 = cat(decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_8_13)
node decoded_andMatrixOutputs_lo_13 = cat(decoded_andMatrixOutputs_lo_hi_13, decoded_andMatrixOutputs_lo_lo_13)
node decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_andMatrixOutputs_andMatrixInput_4_13)
node decoded_andMatrixOutputs_hi_lo_13 = cat(decoded_andMatrixOutputs_hi_lo_hi_10, decoded_andMatrixOutputs_andMatrixInput_5_13)
node decoded_andMatrixOutputs_hi_hi_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_andMatrixOutputs_andMatrixInput_1_14)
node decoded_andMatrixOutputs_hi_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_hi_13, decoded_andMatrixOutputs_andMatrixInput_2_13)
node decoded_andMatrixOutputs_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_13, decoded_andMatrixOutputs_hi_lo_13)
node _decoded_andMatrixOutputs_T_14 = cat(decoded_andMatrixOutputs_hi_13, decoded_andMatrixOutputs_lo_13)
node decoded_andMatrixOutputs_5_2_1 = andr(_decoded_andMatrixOutputs_T_14)
node decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoded_plaInput_4, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoded_plaInput_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoded_plaInput_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(decoded_invInputs_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(decoded_plaInput_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_lo_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_andMatrixOutputs_andMatrixInput_10_11)
node decoded_andMatrixOutputs_lo_lo_14 = cat(decoded_andMatrixOutputs_lo_lo_hi_7, decoded_andMatrixOutputs_andMatrixInput_11_7)
node decoded_andMatrixOutputs_lo_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_andMatrixOutputs_andMatrixInput_7_14)
node decoded_andMatrixOutputs_lo_hi_14 = cat(decoded_andMatrixOutputs_lo_hi_hi_12, decoded_andMatrixOutputs_andMatrixInput_8_14)
node decoded_andMatrixOutputs_lo_14 = cat(decoded_andMatrixOutputs_lo_hi_14, decoded_andMatrixOutputs_lo_lo_14)
node decoded_andMatrixOutputs_hi_lo_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_andMatrixOutputs_andMatrixInput_4_14)
node decoded_andMatrixOutputs_hi_lo_14 = cat(decoded_andMatrixOutputs_hi_lo_hi_11, decoded_andMatrixOutputs_andMatrixInput_5_14)
node decoded_andMatrixOutputs_hi_hi_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_andMatrixOutputs_andMatrixInput_1_15)
node decoded_andMatrixOutputs_hi_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_hi_14, decoded_andMatrixOutputs_andMatrixInput_2_14)
node decoded_andMatrixOutputs_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_14, decoded_andMatrixOutputs_hi_lo_14)
node _decoded_andMatrixOutputs_T_15 = cat(decoded_andMatrixOutputs_hi_14, decoded_andMatrixOutputs_lo_14)
node decoded_andMatrixOutputs_4_2_1 = andr(_decoded_andMatrixOutputs_T_15)
node _decoded_orMatrixOutputs_T_10 = orr(decoded_andMatrixOutputs_4_2_1)
node _decoded_orMatrixOutputs_T_11 = orr(decoded_andMatrixOutputs_2_2_2)
node decoded_orMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_3_2_1, decoded_andMatrixOutputs_1_2_2)
node _decoded_orMatrixOutputs_T_12 = cat(decoded_orMatrixOutputs_hi_5, decoded_andMatrixOutputs_5_2_1)
node _decoded_orMatrixOutputs_T_13 = orr(_decoded_orMatrixOutputs_T_12)
node _decoded_orMatrixOutputs_T_14 = orr(decoded_andMatrixOutputs_0_2_4)
node decoded_orMatrixOutputs_lo_lo_4 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_10)
node decoded_orMatrixOutputs_lo_hi_4 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_11)
node decoded_orMatrixOutputs_lo_4 = cat(decoded_orMatrixOutputs_lo_hi_4, decoded_orMatrixOutputs_lo_lo_4)
node decoded_orMatrixOutputs_hi_lo_4 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_13)
node decoded_orMatrixOutputs_hi_hi_4 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_14)
node decoded_orMatrixOutputs_hi_6 = cat(decoded_orMatrixOutputs_hi_hi_4, decoded_orMatrixOutputs_hi_lo_4)
node decoded_orMatrixOutputs_4 = cat(decoded_orMatrixOutputs_hi_6, decoded_orMatrixOutputs_lo_4)
node _decoded_invMatrixOutputs_T_32 = bits(decoded_orMatrixOutputs_4, 0, 0)
node _decoded_invMatrixOutputs_T_33 = bits(decoded_orMatrixOutputs_4, 1, 1)
node _decoded_invMatrixOutputs_T_34 = bits(decoded_orMatrixOutputs_4, 2, 2)
node _decoded_invMatrixOutputs_T_35 = bits(decoded_orMatrixOutputs_4, 3, 3)
node _decoded_invMatrixOutputs_T_36 = bits(decoded_orMatrixOutputs_4, 4, 4)
node _decoded_invMatrixOutputs_T_37 = bits(decoded_orMatrixOutputs_4, 5, 5)
node _decoded_invMatrixOutputs_T_38 = bits(decoded_orMatrixOutputs_4, 6, 6)
node _decoded_invMatrixOutputs_T_39 = bits(decoded_orMatrixOutputs_4, 7, 7)
node decoded_invMatrixOutputs_lo_lo_4 = cat(_decoded_invMatrixOutputs_T_33, _decoded_invMatrixOutputs_T_32)
node decoded_invMatrixOutputs_lo_hi_4 = cat(_decoded_invMatrixOutputs_T_35, _decoded_invMatrixOutputs_T_34)
node decoded_invMatrixOutputs_lo_4 = cat(decoded_invMatrixOutputs_lo_hi_4, decoded_invMatrixOutputs_lo_lo_4)
node decoded_invMatrixOutputs_hi_lo_4 = cat(_decoded_invMatrixOutputs_T_37, _decoded_invMatrixOutputs_T_36)
node decoded_invMatrixOutputs_hi_hi_4 = cat(_decoded_invMatrixOutputs_T_39, _decoded_invMatrixOutputs_T_38)
node decoded_invMatrixOutputs_hi_4 = cat(decoded_invMatrixOutputs_hi_hi_4, decoded_invMatrixOutputs_hi_lo_4)
node decoded_invMatrixOutputs_4 = cat(decoded_invMatrixOutputs_hi_4, decoded_invMatrixOutputs_lo_4)
connect decoded_plaOutput_4, decoded_invMatrixOutputs_4
connect decoded_plaInput_4, addr_4
node _decoded_T_112 = shl(UInt<4>(0hf), 4)
node _decoded_T_113 = xor(UInt<8>(0hff), _decoded_T_112)
node _decoded_T_114 = shr(decoded_plaOutput_4, 4)
node _decoded_T_115 = and(_decoded_T_114, _decoded_T_113)
node _decoded_T_116 = bits(decoded_plaOutput_4, 3, 0)
node _decoded_T_117 = shl(_decoded_T_116, 4)
node _decoded_T_118 = not(_decoded_T_113)
node _decoded_T_119 = and(_decoded_T_117, _decoded_T_118)
node _decoded_T_120 = or(_decoded_T_115, _decoded_T_119)
node _decoded_T_121 = bits(_decoded_T_113, 5, 0)
node _decoded_T_122 = shl(_decoded_T_121, 2)
node _decoded_T_123 = xor(_decoded_T_113, _decoded_T_122)
node _decoded_T_124 = shr(_decoded_T_120, 2)
node _decoded_T_125 = and(_decoded_T_124, _decoded_T_123)
node _decoded_T_126 = bits(_decoded_T_120, 5, 0)
node _decoded_T_127 = shl(_decoded_T_126, 2)
node _decoded_T_128 = not(_decoded_T_123)
node _decoded_T_129 = and(_decoded_T_127, _decoded_T_128)
node _decoded_T_130 = or(_decoded_T_125, _decoded_T_129)
node _decoded_T_131 = bits(_decoded_T_123, 6, 0)
node _decoded_T_132 = shl(_decoded_T_131, 1)
node _decoded_T_133 = xor(_decoded_T_123, _decoded_T_132)
node _decoded_T_134 = shr(_decoded_T_130, 1)
node _decoded_T_135 = and(_decoded_T_134, _decoded_T_133)
node _decoded_T_136 = bits(_decoded_T_130, 6, 0)
node _decoded_T_137 = shl(_decoded_T_136, 1)
node _decoded_T_138 = not(_decoded_T_133)
node _decoded_T_139 = and(_decoded_T_137, _decoded_T_138)
node decoded_4 = or(_decoded_T_135, _decoded_T_139)
node _io_resp_4_vc_sel_0_0_T = bits(decoded_4, 0, 0)
connect io.resp.`4`.vc_sel.`0`[0], _io_resp_4_vc_sel_0_0_T
node _io_resp_4_vc_sel_0_1_T = bits(decoded_4, 1, 1)
connect io.resp.`4`.vc_sel.`0`[1], _io_resp_4_vc_sel_0_1_T
node _io_resp_4_vc_sel_1_0_T = bits(decoded_4, 2, 2)
connect io.resp.`4`.vc_sel.`1`[0], _io_resp_4_vc_sel_1_0_T
node _io_resp_4_vc_sel_1_1_T = bits(decoded_4, 3, 3)
connect io.resp.`4`.vc_sel.`1`[1], _io_resp_4_vc_sel_1_1_T
node _io_resp_4_vc_sel_2_0_T = bits(decoded_4, 4, 4)
connect io.resp.`4`.vc_sel.`2`[0], _io_resp_4_vc_sel_2_0_T
node _io_resp_4_vc_sel_2_1_T = bits(decoded_4, 5, 5)
connect io.resp.`4`.vc_sel.`2`[1], _io_resp_4_vc_sel_2_1_T
node _io_resp_4_vc_sel_3_0_T = bits(decoded_4, 6, 6)
connect io.resp.`4`.vc_sel.`3`[0], _io_resp_4_vc_sel_3_0_T
node _io_resp_4_vc_sel_3_1_T = bits(decoded_4, 7, 7)
connect io.resp.`4`.vc_sel.`3`[1], _io_resp_4_vc_sel_3_1_T
connect io.resp.`4`.vc_sel.`4`[0], UInt<1>(0h0)
extmodule plusarg_reader_51 :
output out : UInt<20>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "noc_util_sample_rate=%d"
parameter WIDTH = 20 | module RouteComputer_25( // @[RouteComputer.scala:29:7]
input [3:0] io_req_4_bits_flow_egress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_4_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14]
input io_req_3_bits_src_virt_id, // @[RouteComputer.scala:40:14]
input io_req_3_bits_flow_vnet_id, // @[RouteComputer.scala:40:14]
input [3:0] io_req_3_bits_flow_ingress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_3_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14]
input [3:0] io_req_3_bits_flow_egress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_3_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14]
input io_req_2_bits_src_virt_id, // @[RouteComputer.scala:40:14]
input io_req_2_bits_flow_vnet_id, // @[RouteComputer.scala:40:14]
input [3:0] io_req_2_bits_flow_ingress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_2_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14]
input [3:0] io_req_2_bits_flow_egress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_2_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14]
input io_req_1_bits_src_virt_id, // @[RouteComputer.scala:40:14]
input io_req_1_bits_flow_vnet_id, // @[RouteComputer.scala:40:14]
input [3:0] io_req_1_bits_flow_ingress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_1_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14]
input [3:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_1_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14]
input io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14]
input io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14]
input [3:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14]
input [3:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_3_0, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_3_1, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_2_0, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_2_1, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_1_0, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_1_1, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_0_0, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_0_1, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_3_0, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_3_1, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_2_0, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_2_1, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_1_0, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_1_1, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_0_0, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_0_1, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_3_0, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_3_1, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_2_0, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_2_1, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_1_0, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_1_1, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_0, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_1, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_3_0, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_3_1, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_2_0, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_2_1, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_1_0, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_1_1, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_0, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_1, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_3_0, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_3_1, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_2_0, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_2_1, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_1_0, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_1_1, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_0_0, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_0_1 // @[RouteComputer.scala:40:14]
);
wire [12:0] decoded_invInputs_1 = ~{io_req_1_bits_flow_vnet_id, io_req_1_bits_flow_ingress_node, io_req_1_bits_flow_ingress_node_id, io_req_1_bits_flow_egress_node, io_req_1_bits_flow_egress_node_id}; // @[pla.scala:78:21]
wire [12:0] decoded_invInputs_2 = ~{io_req_2_bits_flow_vnet_id, io_req_2_bits_flow_ingress_node, io_req_2_bits_flow_ingress_node_id, io_req_2_bits_flow_egress_node, io_req_2_bits_flow_egress_node_id}; // @[pla.scala:78:21]
wire [12:0] decoded_invInputs_3 = ~{io_req_3_bits_flow_vnet_id, io_req_3_bits_flow_ingress_node, io_req_3_bits_flow_ingress_node_id, io_req_3_bits_flow_egress_node, io_req_3_bits_flow_egress_node_id}; // @[pla.scala:78:21]
wire [3:0] _GEN = ~io_req_4_bits_flow_egress_node; // @[pla.scala:78:21]
wire [1:0] _GEN_0 = ~io_req_4_bits_flow_egress_node_id; // @[pla.scala:78:21]
assign io_resp_4_vc_sel_3_0 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_4_vc_sel_3_1 = &{io_req_4_bits_flow_egress_node[0], _GEN[1], io_req_4_bits_flow_egress_node[2], io_req_4_bits_flow_egress_node[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}]
assign io_resp_4_vc_sel_2_0 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_4_vc_sel_2_1 = &{_GEN_0[0], _GEN_0[1], io_req_4_bits_flow_egress_node[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}]
assign io_resp_4_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_4_vc_sel_1_1 = |{&{_GEN[0], _GEN[1], _GEN[2], _GEN[3]}, &{_GEN_0[0], _GEN[0], _GEN[1], io_req_4_bits_flow_egress_node[2]}, &{_GEN_0[0], _GEN[0], _GEN[1], io_req_4_bits_flow_egress_node[3]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_4_vc_sel_0_1 = &{io_req_4_bits_flow_egress_node[0], _GEN[1], _GEN[2], _GEN[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}]
assign io_resp_3_vc_sel_3_0 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_3_vc_sel_3_1 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_3_vc_sel_2_0 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_3_vc_sel_2_1 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_3_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_3_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_3_vc_sel_0_0 = &{decoded_invInputs_3[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[0], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node[2], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}]
assign io_resp_3_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_2_vc_sel_3_0 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_2_vc_sel_3_1 = &{decoded_invInputs_2[0], io_req_2_bits_flow_egress_node[0], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[3], io_req_2_bits_flow_vnet_id}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}]
assign io_resp_2_vc_sel_2_0 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_2_vc_sel_2_1 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_2_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_2_vc_sel_1_1 = |{io_req_2_bits_flow_egress_node_id[0], &{decoded_invInputs_2[0], decoded_invInputs_2[1], decoded_invInputs_2[2], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[3], io_req_2_bits_flow_vnet_id}, &{decoded_invInputs_2[0], decoded_invInputs_2[1], decoded_invInputs_2[2], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[3], io_req_2_bits_flow_vnet_id}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_0_0 = &{decoded_invInputs_2[0], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}]
assign io_resp_2_vc_sel_0_1 = &{decoded_invInputs_2[0], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[1], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[3], io_req_2_bits_flow_vnet_id}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}]
assign io_resp_1_vc_sel_3_0 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_1_vc_sel_3_1 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_1_vc_sel_2_0 = |{&{decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], io_req_1_bits_flow_ingress_node[3], decoded_invInputs_1[12]}, &{decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], io_req_1_bits_flow_ingress_node[3], decoded_invInputs_1[12]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_2_1 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_1_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_1_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_1_vc_sel_0_0 = &{decoded_invInputs_1[0], decoded_invInputs_1[3], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], io_req_1_bits_flow_ingress_node[3], decoded_invInputs_1[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}]
assign io_resp_1_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_0_vc_sel_3_0 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_0_vc_sel_3_1 = &{~(io_req_0_bits_flow_egress_node_id[0]), io_req_0_bits_flow_vnet_id}; // @[pla.scala:78:21, :98:{53,70}]
assign io_resp_0_vc_sel_2_0 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_0_vc_sel_2_1 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_0_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_0_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_0_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_0_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_MasterXbar_RocketTile_i3_o1_a32d128s6k4z4c :
input clock : Clock
input reset : Reset
output auto : { flip anon_in_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}, flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}
invalidate anonIn.e.bits.sink
invalidate anonIn.e.valid
invalidate anonIn.e.ready
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.c.bits.corrupt
invalidate anonIn.c.bits.data
invalidate anonIn.c.bits.address
invalidate anonIn.c.bits.source
invalidate anonIn.c.bits.size
invalidate anonIn.c.bits.param
invalidate anonIn.c.bits.opcode
invalidate anonIn.c.valid
invalidate anonIn.c.ready
invalidate anonIn.b.bits.corrupt
invalidate anonIn.b.bits.data
invalidate anonIn.b.bits.mask
invalidate anonIn.b.bits.address
invalidate anonIn.b.bits.source
invalidate anonIn.b.bits.size
invalidate anonIn.b.bits.param
invalidate anonIn.b.bits.opcode
invalidate anonIn.b.valid
invalidate anonIn.b.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}
invalidate anonIn_1.d.bits.corrupt
invalidate anonIn_1.d.bits.data
invalidate anonIn_1.d.bits.denied
invalidate anonIn_1.d.bits.sink
invalidate anonIn_1.d.bits.source
invalidate anonIn_1.d.bits.size
invalidate anonIn_1.d.bits.param
invalidate anonIn_1.d.bits.opcode
invalidate anonIn_1.d.valid
invalidate anonIn_1.d.ready
invalidate anonIn_1.a.bits.corrupt
invalidate anonIn_1.a.bits.data
invalidate anonIn_1.a.bits.mask
invalidate anonIn_1.a.bits.address
invalidate anonIn_1.a.bits.source
invalidate anonIn_1.a.bits.size
invalidate anonIn_1.a.bits.param
invalidate anonIn_1.a.bits.opcode
invalidate anonIn_1.a.valid
invalidate anonIn_1.a.ready
wire anonIn_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}
invalidate anonIn_2.d.bits.corrupt
invalidate anonIn_2.d.bits.data
invalidate anonIn_2.d.bits.denied
invalidate anonIn_2.d.bits.sink
invalidate anonIn_2.d.bits.source
invalidate anonIn_2.d.bits.size
invalidate anonIn_2.d.bits.param
invalidate anonIn_2.d.bits.opcode
invalidate anonIn_2.d.valid
invalidate anonIn_2.d.ready
invalidate anonIn_2.a.bits.corrupt
invalidate anonIn_2.a.bits.data
invalidate anonIn_2.a.bits.mask
invalidate anonIn_2.a.bits.address
invalidate anonIn_2.a.bits.source
invalidate anonIn_2.a.bits.size
invalidate anonIn_2.a.bits.param
invalidate anonIn_2.a.bits.opcode
invalidate anonIn_2.a.valid
invalidate anonIn_2.a.ready
inst monitor of TLMonitor_40
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.e.bits.sink, anonIn.e.bits.sink
connect monitor.io.in.e.valid, anonIn.e.valid
connect monitor.io.in.e.ready, anonIn.e.ready
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.c.bits.corrupt, anonIn.c.bits.corrupt
connect monitor.io.in.c.bits.data, anonIn.c.bits.data
connect monitor.io.in.c.bits.address, anonIn.c.bits.address
connect monitor.io.in.c.bits.source, anonIn.c.bits.source
connect monitor.io.in.c.bits.size, anonIn.c.bits.size
connect monitor.io.in.c.bits.param, anonIn.c.bits.param
connect monitor.io.in.c.bits.opcode, anonIn.c.bits.opcode
connect monitor.io.in.c.valid, anonIn.c.valid
connect monitor.io.in.c.ready, anonIn.c.ready
connect monitor.io.in.b.bits.corrupt, anonIn.b.bits.corrupt
connect monitor.io.in.b.bits.data, anonIn.b.bits.data
connect monitor.io.in.b.bits.mask, anonIn.b.bits.mask
connect monitor.io.in.b.bits.address, anonIn.b.bits.address
connect monitor.io.in.b.bits.source, anonIn.b.bits.source
connect monitor.io.in.b.bits.size, anonIn.b.bits.size
connect monitor.io.in.b.bits.param, anonIn.b.bits.param
connect monitor.io.in.b.bits.opcode, anonIn.b.bits.opcode
connect monitor.io.in.b.valid, anonIn.b.valid
connect monitor.io.in.b.ready, anonIn.b.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
inst monitor_1 of TLMonitor_41
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt
connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data
connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied
connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink
connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source
connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size
connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param
connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode
connect monitor_1.io.in.d.valid, anonIn_1.d.valid
connect monitor_1.io.in.d.ready, anonIn_1.d.ready
connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt
connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data
connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask
connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address
connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source
connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size
connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param
connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode
connect monitor_1.io.in.a.valid, anonIn_1.a.valid
connect monitor_1.io.in.a.ready, anonIn_1.a.ready
inst monitor_2 of TLMonitor_42
connect monitor_2.clock, clock
connect monitor_2.reset, reset
connect monitor_2.io.in.d.bits.corrupt, anonIn_2.d.bits.corrupt
connect monitor_2.io.in.d.bits.data, anonIn_2.d.bits.data
connect monitor_2.io.in.d.bits.denied, anonIn_2.d.bits.denied
connect monitor_2.io.in.d.bits.sink, anonIn_2.d.bits.sink
connect monitor_2.io.in.d.bits.source, anonIn_2.d.bits.source
connect monitor_2.io.in.d.bits.size, anonIn_2.d.bits.size
connect monitor_2.io.in.d.bits.param, anonIn_2.d.bits.param
connect monitor_2.io.in.d.bits.opcode, anonIn_2.d.bits.opcode
connect monitor_2.io.in.d.valid, anonIn_2.d.valid
connect monitor_2.io.in.d.ready, anonIn_2.d.ready
connect monitor_2.io.in.a.bits.corrupt, anonIn_2.a.bits.corrupt
connect monitor_2.io.in.a.bits.data, anonIn_2.a.bits.data
connect monitor_2.io.in.a.bits.mask, anonIn_2.a.bits.mask
connect monitor_2.io.in.a.bits.address, anonIn_2.a.bits.address
connect monitor_2.io.in.a.bits.source, anonIn_2.a.bits.source
connect monitor_2.io.in.a.bits.size, anonIn_2.a.bits.size
connect monitor_2.io.in.a.bits.param, anonIn_2.a.bits.param
connect monitor_2.io.in.a.bits.opcode, anonIn_2.a.bits.opcode
connect monitor_2.io.in.a.valid, anonIn_2.a.valid
connect monitor_2.io.in.a.ready, anonIn_2.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}
invalidate anonOut.e.bits.sink
invalidate anonOut.e.valid
invalidate anonOut.e.ready
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.c.bits.corrupt
invalidate anonOut.c.bits.data
invalidate anonOut.c.bits.address
invalidate anonOut.c.bits.source
invalidate anonOut.c.bits.size
invalidate anonOut.c.bits.param
invalidate anonOut.c.bits.opcode
invalidate anonOut.c.valid
invalidate anonOut.c.ready
invalidate anonOut.b.bits.corrupt
invalidate anonOut.b.bits.data
invalidate anonOut.b.bits.mask
invalidate anonOut.b.bits.address
invalidate anonOut.b.bits.source
invalidate anonOut.b.bits.size
invalidate anonOut.b.bits.param
invalidate anonOut.b.bits.opcode
invalidate anonOut.b.valid
invalidate anonOut.b.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in_0
connect anonIn_1, auto.anon_in_1
connect anonIn_2, auto.anon_in_2
wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}[3]
connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt
connect in[0].a.bits.data, anonIn.a.bits.data
connect in[0].a.bits.mask, anonIn.a.bits.mask
connect in[0].a.bits.address, anonIn.a.bits.address
connect in[0].a.bits.source, anonIn.a.bits.source
connect in[0].a.bits.size, anonIn.a.bits.size
connect in[0].a.bits.param, anonIn.a.bits.param
connect in[0].a.bits.opcode, anonIn.a.bits.opcode
connect in[0].a.valid, anonIn.a.valid
connect anonIn.a.ready, in[0].a.ready
node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<6>(0h20))
connect in[0].a.bits.source, _in_0_a_bits_source_T
connect anonIn.b.bits.corrupt, in[0].b.bits.corrupt
connect anonIn.b.bits.data, in[0].b.bits.data
connect anonIn.b.bits.mask, in[0].b.bits.mask
connect anonIn.b.bits.address, in[0].b.bits.address
connect anonIn.b.bits.source, in[0].b.bits.source
connect anonIn.b.bits.size, in[0].b.bits.size
connect anonIn.b.bits.param, in[0].b.bits.param
connect anonIn.b.bits.opcode, in[0].b.bits.opcode
connect anonIn.b.valid, in[0].b.valid
connect in[0].b.ready, anonIn.b.ready
node _anonIn_b_bits_source_T = bits(in[0].b.bits.source, 0, 0)
connect anonIn.b.bits.source, _anonIn_b_bits_source_T
connect in[0].c.bits.corrupt, anonIn.c.bits.corrupt
connect in[0].c.bits.data, anonIn.c.bits.data
connect in[0].c.bits.address, anonIn.c.bits.address
connect in[0].c.bits.source, anonIn.c.bits.source
connect in[0].c.bits.size, anonIn.c.bits.size
connect in[0].c.bits.param, anonIn.c.bits.param
connect in[0].c.bits.opcode, anonIn.c.bits.opcode
connect in[0].c.valid, anonIn.c.valid
connect anonIn.c.ready, in[0].c.ready
node _in_0_c_bits_source_T = or(anonIn.c.bits.source, UInt<6>(0h20))
connect in[0].c.bits.source, _in_0_c_bits_source_T
connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt
connect anonIn.d.bits.data, in[0].d.bits.data
connect anonIn.d.bits.denied, in[0].d.bits.denied
connect anonIn.d.bits.sink, in[0].d.bits.sink
connect anonIn.d.bits.source, in[0].d.bits.source
connect anonIn.d.bits.size, in[0].d.bits.size
connect anonIn.d.bits.param, in[0].d.bits.param
connect anonIn.d.bits.opcode, in[0].d.bits.opcode
connect anonIn.d.valid, in[0].d.valid
connect in[0].d.ready, anonIn.d.ready
node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 0, 0)
connect anonIn.d.bits.source, _anonIn_d_bits_source_T
connect in[0].e.bits.sink, anonIn.e.bits.sink
connect in[0].e.valid, anonIn.e.valid
connect anonIn.e.ready, in[0].e.ready
connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt
connect in[1].a.bits.data, anonIn_1.a.bits.data
connect in[1].a.bits.mask, anonIn_1.a.bits.mask
connect in[1].a.bits.address, anonIn_1.a.bits.address
connect in[1].a.bits.source, anonIn_1.a.bits.source
connect in[1].a.bits.size, anonIn_1.a.bits.size
connect in[1].a.bits.param, anonIn_1.a.bits.param
connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode
connect in[1].a.valid, anonIn_1.a.valid
connect anonIn_1.a.ready, in[1].a.ready
node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<1>(0h0))
connect in[1].a.bits.source, _in_1_a_bits_source_T
invalidate in[1].b.bits.corrupt
invalidate in[1].b.bits.data
invalidate in[1].b.bits.mask
invalidate in[1].b.bits.address
invalidate in[1].b.bits.source
invalidate in[1].b.bits.size
invalidate in[1].b.bits.param
invalidate in[1].b.bits.opcode
invalidate in[1].b.valid
invalidate in[1].b.ready
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<128>(0h0)
connect _WIRE.bits.mask, UInt<16>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
invalidate _WIRE_1.bits.corrupt
invalidate _WIRE_1.bits.data
invalidate _WIRE_1.bits.mask
invalidate _WIRE_1.bits.address
invalidate _WIRE_1.bits.source
invalidate _WIRE_1.bits.size
invalidate _WIRE_1.bits.param
invalidate _WIRE_1.bits.opcode
invalidate _WIRE_1.valid
invalidate _WIRE_1.ready
connect in[1].b.ready, UInt<1>(0h1)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<128>(0h0)
connect _WIRE_2.bits.mask, UInt<16>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<2>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.valid, UInt<1>(0h0)
invalidate in[1].c.bits.corrupt
invalidate in[1].c.bits.data
invalidate in[1].c.bits.address
invalidate in[1].c.bits.source
invalidate in[1].c.bits.size
invalidate in[1].c.bits.param
invalidate in[1].c.bits.opcode
invalidate in[1].c.valid
invalidate in[1].c.ready
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<128>(0h0)
connect _WIRE_4.bits.address, UInt<32>(0h0)
connect _WIRE_4.bits.source, UInt<5>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<3>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
invalidate _WIRE_5.bits.corrupt
invalidate _WIRE_5.bits.data
invalidate _WIRE_5.bits.address
invalidate _WIRE_5.bits.source
invalidate _WIRE_5.bits.size
invalidate _WIRE_5.bits.param
invalidate _WIRE_5.bits.opcode
invalidate _WIRE_5.valid
invalidate _WIRE_5.ready
connect in[1].c.valid, UInt<1>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<128>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt
connect anonIn_1.d.bits.data, in[1].d.bits.data
connect anonIn_1.d.bits.denied, in[1].d.bits.denied
connect anonIn_1.d.bits.sink, in[1].d.bits.sink
connect anonIn_1.d.bits.source, in[1].d.bits.source
connect anonIn_1.d.bits.size, in[1].d.bits.size
connect anonIn_1.d.bits.param, in[1].d.bits.param
connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode
connect anonIn_1.d.valid, in[1].d.valid
connect in[1].d.ready, anonIn_1.d.ready
node _anonIn_d_bits_source_T_1 = bits(in[1].d.bits.source, 4, 0)
connect anonIn_1.d.bits.source, _anonIn_d_bits_source_T_1
invalidate in[1].e.bits.sink
invalidate in[1].e.valid
invalidate in[1].e.ready
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_8.bits.sink, UInt<4>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
invalidate _WIRE_9.bits.sink
invalidate _WIRE_9.valid
invalidate _WIRE_9.ready
connect in[1].e.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_10.bits.sink, UInt<4>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.ready, UInt<1>(0h1)
connect in[2].a.bits.corrupt, anonIn_2.a.bits.corrupt
connect in[2].a.bits.data, anonIn_2.a.bits.data
connect in[2].a.bits.mask, anonIn_2.a.bits.mask
connect in[2].a.bits.address, anonIn_2.a.bits.address
connect in[2].a.bits.source, anonIn_2.a.bits.source
connect in[2].a.bits.size, anonIn_2.a.bits.size
connect in[2].a.bits.param, anonIn_2.a.bits.param
connect in[2].a.bits.opcode, anonIn_2.a.bits.opcode
connect in[2].a.valid, anonIn_2.a.valid
connect anonIn_2.a.ready, in[2].a.ready
node _in_2_a_bits_source_T = or(anonIn_2.a.bits.source, UInt<6>(0h22))
connect in[2].a.bits.source, _in_2_a_bits_source_T
invalidate in[2].b.bits.corrupt
invalidate in[2].b.bits.data
invalidate in[2].b.bits.mask
invalidate in[2].b.bits.address
invalidate in[2].b.bits.source
invalidate in[2].b.bits.size
invalidate in[2].b.bits.param
invalidate in[2].b.bits.opcode
invalidate in[2].b.valid
invalidate in[2].b.ready
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<128>(0h0)
connect _WIRE_12.bits.mask, UInt<16>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<2>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
invalidate _WIRE_13.bits.corrupt
invalidate _WIRE_13.bits.data
invalidate _WIRE_13.bits.mask
invalidate _WIRE_13.bits.address
invalidate _WIRE_13.bits.source
invalidate _WIRE_13.bits.size
invalidate _WIRE_13.bits.param
invalidate _WIRE_13.bits.opcode
invalidate _WIRE_13.valid
invalidate _WIRE_13.ready
connect in[2].b.ready, UInt<1>(0h1)
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<128>(0h0)
connect _WIRE_14.bits.mask, UInt<16>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<2>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
connect _WIRE_15.valid, UInt<1>(0h0)
invalidate in[2].c.bits.corrupt
invalidate in[2].c.bits.data
invalidate in[2].c.bits.address
invalidate in[2].c.bits.source
invalidate in[2].c.bits.size
invalidate in[2].c.bits.param
invalidate in[2].c.bits.opcode
invalidate in[2].c.valid
invalidate in[2].c.ready
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<128>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
invalidate _WIRE_17.bits.corrupt
invalidate _WIRE_17.bits.data
invalidate _WIRE_17.bits.address
invalidate _WIRE_17.bits.source
invalidate _WIRE_17.bits.size
invalidate _WIRE_17.bits.param
invalidate _WIRE_17.bits.opcode
invalidate _WIRE_17.valid
invalidate _WIRE_17.ready
connect in[2].c.valid, UInt<1>(0h0)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<128>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
connect _WIRE_19.ready, UInt<1>(0h1)
connect anonIn_2.d.bits.corrupt, in[2].d.bits.corrupt
connect anonIn_2.d.bits.data, in[2].d.bits.data
connect anonIn_2.d.bits.denied, in[2].d.bits.denied
connect anonIn_2.d.bits.sink, in[2].d.bits.sink
connect anonIn_2.d.bits.source, in[2].d.bits.source
connect anonIn_2.d.bits.size, in[2].d.bits.size
connect anonIn_2.d.bits.param, in[2].d.bits.param
connect anonIn_2.d.bits.opcode, in[2].d.bits.opcode
connect anonIn_2.d.valid, in[2].d.valid
connect in[2].d.ready, anonIn_2.d.ready
connect anonIn_2.d.bits.source, UInt<1>(0h0)
invalidate in[2].e.bits.sink
invalidate in[2].e.valid
invalidate in[2].e.ready
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_20.bits.sink, UInt<4>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
invalidate _WIRE_21.bits.sink
invalidate _WIRE_21.valid
invalidate _WIRE_21.ready
connect in[2].e.valid, UInt<1>(0h0)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_22.bits.sink, UInt<4>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
connect _WIRE_23.ready, UInt<1>(0h1)
wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}[1]
connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt
connect anonOut.a.bits.data, out[0].a.bits.data
connect anonOut.a.bits.mask, out[0].a.bits.mask
connect anonOut.a.bits.address, out[0].a.bits.address
connect anonOut.a.bits.source, out[0].a.bits.source
connect anonOut.a.bits.size, out[0].a.bits.size
connect anonOut.a.bits.param, out[0].a.bits.param
connect anonOut.a.bits.opcode, out[0].a.bits.opcode
connect anonOut.a.valid, out[0].a.valid
connect out[0].a.ready, anonOut.a.ready
connect out[0].b.bits.corrupt, anonOut.b.bits.corrupt
connect out[0].b.bits.data, anonOut.b.bits.data
connect out[0].b.bits.mask, anonOut.b.bits.mask
connect out[0].b.bits.address, anonOut.b.bits.address
connect out[0].b.bits.source, anonOut.b.bits.source
connect out[0].b.bits.size, anonOut.b.bits.size
connect out[0].b.bits.param, anonOut.b.bits.param
connect out[0].b.bits.opcode, anonOut.b.bits.opcode
connect out[0].b.valid, anonOut.b.valid
connect anonOut.b.ready, out[0].b.ready
connect anonOut.c.bits.corrupt, out[0].c.bits.corrupt
connect anonOut.c.bits.data, out[0].c.bits.data
connect anonOut.c.bits.address, out[0].c.bits.address
connect anonOut.c.bits.source, out[0].c.bits.source
connect anonOut.c.bits.size, out[0].c.bits.size
connect anonOut.c.bits.param, out[0].c.bits.param
connect anonOut.c.bits.opcode, out[0].c.bits.opcode
connect anonOut.c.valid, out[0].c.valid
connect out[0].c.ready, anonOut.c.ready
connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt
connect out[0].d.bits.data, anonOut.d.bits.data
connect out[0].d.bits.denied, anonOut.d.bits.denied
connect out[0].d.bits.sink, anonOut.d.bits.sink
connect out[0].d.bits.source, anonOut.d.bits.source
connect out[0].d.bits.size, anonOut.d.bits.size
connect out[0].d.bits.param, anonOut.d.bits.param
connect out[0].d.bits.opcode, anonOut.d.bits.opcode
connect out[0].d.valid, anonOut.d.valid
connect anonOut.d.ready, out[0].d.ready
node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0))
connect out[0].d.bits.sink, _out_0_d_bits_sink_T
connect anonOut.e.bits.sink, out[0].e.bits.sink
connect anonOut.e.valid, out[0].e.valid
connect out[0].e.ready, anonOut.e.ready
node _anonOut_e_bits_sink_T = bits(out[0].e.bits.sink, 3, 0)
connect anonOut.e.bits.sink, _anonOut_e_bits_sink_T
node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_1 = cvt(_requestAIO_T)
node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<1>(0h0)))
node _requestAIO_T_3 = asSInt(_requestAIO_T_2)
node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0)))
node requestAIO_0_0 = or(UInt<1>(0h1), _requestAIO_T_4)
node _requestAIO_T_5 = xor(in[1].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_6 = cvt(_requestAIO_T_5)
node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<1>(0h0)))
node _requestAIO_T_8 = asSInt(_requestAIO_T_7)
node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0)))
node requestAIO_1_0 = or(UInt<1>(0h1), _requestAIO_T_9)
node _requestAIO_T_10 = xor(in[2].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_11 = cvt(_requestAIO_T_10)
node _requestAIO_T_12 = and(_requestAIO_T_11, asSInt(UInt<1>(0h0)))
node _requestAIO_T_13 = asSInt(_requestAIO_T_12)
node _requestAIO_T_14 = eq(_requestAIO_T_13, asSInt(UInt<1>(0h0)))
node requestAIO_2_0 = or(UInt<1>(0h1), _requestAIO_T_14)
node _requestCIO_T = xor(in[0].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_1 = cvt(_requestCIO_T)
node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0)))
node _requestCIO_T_3 = asSInt(_requestCIO_T_2)
node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0)))
node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4)
node _requestCIO_T_5 = xor(in[1].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_6 = cvt(_requestCIO_T_5)
node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0)))
node _requestCIO_T_8 = asSInt(_requestCIO_T_7)
node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0)))
node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_9)
node _requestCIO_T_10 = xor(in[2].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_11 = cvt(_requestCIO_T_10)
node _requestCIO_T_12 = and(_requestCIO_T_11, asSInt(UInt<1>(0h0)))
node _requestCIO_T_13 = asSInt(_requestCIO_T_12)
node _requestCIO_T_14 = eq(_requestCIO_T_13, asSInt(UInt<1>(0h0)))
node requestCIO_2_0 = or(UInt<1>(0h1), _requestCIO_T_14)
node _requestBOI_uncommonBits_T = or(out[0].b.bits.source, UInt<1>(0h0))
node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 0, 0)
node _requestBOI_T = shr(out[0].b.bits.source, 1)
node _requestBOI_T_1 = eq(_requestBOI_T, UInt<5>(0h10))
node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits)
node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2)
node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<1>(0h1))
node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4)
node _requestBOI_uncommonBits_T_1 = or(out[0].b.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 4, 0)
node _requestBOI_T_5 = shr(out[0].b.bits.source, 5)
node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<1>(0h0))
node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1)
node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7)
node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<5>(0h1f))
node requestBOI_0_1 = and(_requestBOI_T_8, _requestBOI_T_9)
node requestBOI_0_2 = eq(out[0].b.bits.source, UInt<6>(0h22))
node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<1>(0h0))
node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 0, 0)
node _requestDOI_T = shr(out[0].d.bits.source, 1)
node _requestDOI_T_1 = eq(_requestDOI_T, UInt<5>(0h10))
node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits)
node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2)
node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<1>(0h1))
node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4)
node _requestDOI_uncommonBits_T_1 = or(out[0].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 4, 0)
node _requestDOI_T_5 = shr(out[0].d.bits.source, 5)
node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<1>(0h0))
node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1)
node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7)
node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<5>(0h1f))
node requestDOI_0_1 = and(_requestDOI_T_8, _requestDOI_T_9)
node requestDOI_0_2 = eq(out[0].d.bits.source, UInt<6>(0h22))
node _requestEIO_uncommonBits_T = or(in[0].e.bits.sink, UInt<4>(0h0))
node requestEIO_uncommonBits = bits(_requestEIO_uncommonBits_T, 3, 0)
node _requestEIO_T = shr(in[0].e.bits.sink, 4)
node _requestEIO_T_1 = eq(_requestEIO_T, UInt<1>(0h0))
node _requestEIO_T_2 = leq(UInt<1>(0h0), requestEIO_uncommonBits)
node _requestEIO_T_3 = and(_requestEIO_T_1, _requestEIO_T_2)
node _requestEIO_T_4 = leq(requestEIO_uncommonBits, UInt<4>(0hf))
node requestEIO_0_0 = and(_requestEIO_T_3, _requestEIO_T_4)
node _requestEIO_uncommonBits_T_1 = or(in[1].e.bits.sink, UInt<4>(0h0))
node requestEIO_uncommonBits_1 = bits(_requestEIO_uncommonBits_T_1, 3, 0)
node _requestEIO_T_5 = shr(in[1].e.bits.sink, 4)
node _requestEIO_T_6 = eq(_requestEIO_T_5, UInt<1>(0h0))
node _requestEIO_T_7 = leq(UInt<1>(0h0), requestEIO_uncommonBits_1)
node _requestEIO_T_8 = and(_requestEIO_T_6, _requestEIO_T_7)
node _requestEIO_T_9 = leq(requestEIO_uncommonBits_1, UInt<4>(0hf))
node requestEIO_1_0 = and(_requestEIO_T_8, _requestEIO_T_9)
node _requestEIO_uncommonBits_T_2 = or(in[2].e.bits.sink, UInt<4>(0h0))
node requestEIO_uncommonBits_2 = bits(_requestEIO_uncommonBits_T_2, 3, 0)
node _requestEIO_T_10 = shr(in[2].e.bits.sink, 4)
node _requestEIO_T_11 = eq(_requestEIO_T_10, UInt<1>(0h0))
node _requestEIO_T_12 = leq(UInt<1>(0h0), requestEIO_uncommonBits_2)
node _requestEIO_T_13 = and(_requestEIO_T_11, _requestEIO_T_12)
node _requestEIO_T_14 = leq(requestEIO_uncommonBits_2, UInt<4>(0hf))
node requestEIO_2_0 = and(_requestEIO_T_13, _requestEIO_T_14)
node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size)
node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0)
node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1)
node beatsAI_decode = shr(_beatsAI_decode_T_2, 4)
node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2)
node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0))
node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0))
node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size)
node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0)
node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4)
node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 4)
node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2)
node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0))
node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0))
node _beatsAI_decode_T_6 = dshl(UInt<12>(0hfff), in[2].a.bits.size)
node _beatsAI_decode_T_7 = bits(_beatsAI_decode_T_6, 11, 0)
node _beatsAI_decode_T_8 = not(_beatsAI_decode_T_7)
node beatsAI_decode_2 = shr(_beatsAI_decode_T_8, 4)
node _beatsAI_opdata_T_2 = bits(in[2].a.bits.opcode, 2, 2)
node beatsAI_opdata_2 = eq(_beatsAI_opdata_T_2, UInt<1>(0h0))
node beatsAI_2 = mux(beatsAI_opdata_2, beatsAI_decode_2, UInt<1>(0h0))
node _beatsBO_decode_T = dshl(UInt<12>(0hfff), out[0].b.bits.size)
node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0)
node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1)
node beatsBO_decode = shr(_beatsBO_decode_T_2, 4)
node _beatsBO_opdata_T = bits(out[0].b.bits.opcode, 2, 2)
node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0))
node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0))
node _beatsCI_decode_T = dshl(UInt<12>(0hfff), in[0].c.bits.size)
node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0)
node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1)
node beatsCI_decode = shr(_beatsCI_decode_T_2, 4)
node beatsCI_opdata = bits(in[0].c.bits.opcode, 0, 0)
node beatsCI_0 = mux(beatsCI_opdata, beatsCI_decode, UInt<1>(0h0))
node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].c.bits.size)
node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0)
node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4)
node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 4)
node beatsCI_opdata_1 = bits(in[1].c.bits.opcode, 0, 0)
node beatsCI_1 = mux(UInt<1>(0h0), beatsCI_decode_1, UInt<1>(0h0))
node _beatsCI_decode_T_6 = dshl(UInt<12>(0hfff), in[2].c.bits.size)
node _beatsCI_decode_T_7 = bits(_beatsCI_decode_T_6, 11, 0)
node _beatsCI_decode_T_8 = not(_beatsCI_decode_T_7)
node beatsCI_decode_2 = shr(_beatsCI_decode_T_8, 4)
node beatsCI_opdata_2 = bits(in[2].c.bits.opcode, 0, 0)
node beatsCI_2 = mux(UInt<1>(0h0), beatsCI_decode_2, UInt<1>(0h0))
node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size)
node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0)
node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1)
node beatsDO_decode = shr(_beatsDO_decode_T_2, 4)
node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0)
node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0))
wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}[1]
connect portsAOI_filtered[0].bits, in[0].a.bits
node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h1))
node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T)
connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1
connect in[0].a.ready, portsAOI_filtered[0].ready
wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}[1]
connect portsAOI_filtered_1[0].bits, in[1].a.bits
node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h1))
node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2)
connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3
connect in[1].a.ready, portsAOI_filtered_1[0].ready
wire portsAOI_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}[1]
connect portsAOI_filtered_2[0].bits, in[2].a.bits
node _portsAOI_filtered_0_valid_T_4 = or(requestAIO_2_0, UInt<1>(0h1))
node _portsAOI_filtered_0_valid_T_5 = and(in[2].a.valid, _portsAOI_filtered_0_valid_T_4)
connect portsAOI_filtered_2[0].valid, _portsAOI_filtered_0_valid_T_5
connect in[2].a.ready, portsAOI_filtered_2[0].ready
wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}[3]
connect portsBIO_filtered[0].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[0].bits.data, out[0].b.bits.data
connect portsBIO_filtered[0].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[0].bits.address, out[0].b.bits.address
connect portsBIO_filtered[0].bits.source, out[0].b.bits.source
connect portsBIO_filtered[0].bits.size, out[0].b.bits.size
connect portsBIO_filtered[0].bits.param, out[0].b.bits.param
connect portsBIO_filtered[0].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0))
node _portsBIO_filtered_0_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_0_valid_T)
connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1
connect portsBIO_filtered[1].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[1].bits.data, out[0].b.bits.data
connect portsBIO_filtered[1].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[1].bits.address, out[0].b.bits.address
connect portsBIO_filtered[1].bits.source, out[0].b.bits.source
connect portsBIO_filtered[1].bits.size, out[0].b.bits.size
connect portsBIO_filtered[1].bits.param, out[0].b.bits.param
connect portsBIO_filtered[1].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0))
node _portsBIO_filtered_1_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_1_valid_T)
connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1
connect portsBIO_filtered[2].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[2].bits.data, out[0].b.bits.data
connect portsBIO_filtered[2].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[2].bits.address, out[0].b.bits.address
connect portsBIO_filtered[2].bits.source, out[0].b.bits.source
connect portsBIO_filtered[2].bits.size, out[0].b.bits.size
connect portsBIO_filtered[2].bits.param, out[0].b.bits.param
connect portsBIO_filtered[2].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_2_valid_T = or(requestBOI_0_2, UInt<1>(0h0))
node _portsBIO_filtered_2_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_2_valid_T)
connect portsBIO_filtered[2].valid, _portsBIO_filtered_2_valid_T_1
node _portsBIO_out_0_b_ready_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_2 = mux(requestBOI_0_2, portsBIO_filtered[2].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_3 = or(_portsBIO_out_0_b_ready_T, _portsBIO_out_0_b_ready_T_1)
node _portsBIO_out_0_b_ready_T_4 = or(_portsBIO_out_0_b_ready_T_3, _portsBIO_out_0_b_ready_T_2)
wire _portsBIO_out_0_b_ready_WIRE : UInt<1>
connect _portsBIO_out_0_b_ready_WIRE, _portsBIO_out_0_b_ready_T_4
connect out[0].b.ready, _portsBIO_out_0_b_ready_WIRE
wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}[1]
connect portsCOI_filtered[0].bits, in[0].c.bits
node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h1))
node _portsCOI_filtered_0_valid_T_1 = and(in[0].c.valid, _portsCOI_filtered_0_valid_T)
connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1
connect in[0].c.ready, portsCOI_filtered[0].ready
wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}[1]
connect portsCOI_filtered_1[0].bits, in[1].c.bits
node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h1))
node _portsCOI_filtered_0_valid_T_3 = and(in[1].c.valid, _portsCOI_filtered_0_valid_T_2)
connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3
connect in[1].c.ready, portsCOI_filtered_1[0].ready
wire portsCOI_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}[1]
connect portsCOI_filtered_2[0].bits, in[2].c.bits
node _portsCOI_filtered_0_valid_T_4 = or(requestCIO_2_0, UInt<1>(0h1))
node _portsCOI_filtered_0_valid_T_5 = and(in[2].c.valid, _portsCOI_filtered_0_valid_T_4)
connect portsCOI_filtered_2[0].valid, _portsCOI_filtered_0_valid_T_5
connect in[2].c.ready, portsCOI_filtered_2[0].ready
wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}[3]
connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[0].bits.data, out[0].d.bits.data
connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[0].bits.source, out[0].d.bits.source
connect portsDIO_filtered[0].bits.size, out[0].d.bits.size
connect portsDIO_filtered[0].bits.param, out[0].d.bits.param
connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0))
node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T)
connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1
connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[1].bits.data, out[0].d.bits.data
connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[1].bits.source, out[0].d.bits.source
connect portsDIO_filtered[1].bits.size, out[0].d.bits.size
connect portsDIO_filtered[1].bits.param, out[0].d.bits.param
connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0))
node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T)
connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1
connect portsDIO_filtered[2].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[2].bits.data, out[0].d.bits.data
connect portsDIO_filtered[2].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[2].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[2].bits.source, out[0].d.bits.source
connect portsDIO_filtered[2].bits.size, out[0].d.bits.size
connect portsDIO_filtered[2].bits.param, out[0].d.bits.param
connect portsDIO_filtered[2].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_2_valid_T = or(requestDOI_0_2, UInt<1>(0h0))
node _portsDIO_filtered_2_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_2_valid_T)
connect portsDIO_filtered[2].valid, _portsDIO_filtered_2_valid_T_1
node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_2 = mux(requestDOI_0_2, portsDIO_filtered[2].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_3 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1)
node _portsDIO_out_0_d_ready_T_4 = or(_portsDIO_out_0_d_ready_T_3, _portsDIO_out_0_d_ready_T_2)
wire _portsDIO_out_0_d_ready_WIRE : UInt<1>
connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_4
connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE
wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}[1]
connect portsEOI_filtered[0].bits, in[0].e.bits
node _portsEOI_filtered_0_valid_T = or(requestEIO_0_0, UInt<1>(0h1))
node _portsEOI_filtered_0_valid_T_1 = and(in[0].e.valid, _portsEOI_filtered_0_valid_T)
connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1
connect in[0].e.ready, portsEOI_filtered[0].ready
wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}[1]
connect portsEOI_filtered_1[0].bits, in[1].e.bits
node _portsEOI_filtered_0_valid_T_2 = or(requestEIO_1_0, UInt<1>(0h1))
node _portsEOI_filtered_0_valid_T_3 = and(in[1].e.valid, _portsEOI_filtered_0_valid_T_2)
connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3
connect in[1].e.ready, portsEOI_filtered_1[0].ready
wire portsEOI_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}[1]
connect portsEOI_filtered_2[0].bits, in[2].e.bits
node _portsEOI_filtered_0_valid_T_4 = or(requestEIO_2_0, UInt<1>(0h1))
node _portsEOI_filtered_0_valid_T_5 = and(in[2].e.valid, _portsEOI_filtered_0_valid_T_4)
connect portsEOI_filtered_2[0].valid, _portsEOI_filtered_0_valid_T_5
connect in[2].e.ready, portsEOI_filtered_2[0].ready
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, out[0].a.ready)
node readys_hi = cat(portsAOI_filtered_2[0].valid, portsAOI_filtered_1[0].valid)
node _readys_T = cat(readys_hi, portsAOI_filtered[0].valid)
node readys_valid = bits(_readys_T, 2, 0)
node _readys_T_1 = eq(readys_valid, _readys_T)
node _readys_T_2 = asUInt(reset)
node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0))
when _readys_T_3 :
node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0))
when _readys_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf
assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert
regreset readys_mask : UInt<3>, clock, reset, UInt<3>(0h7)
node _readys_filter_T = not(readys_mask)
node _readys_filter_T_1 = and(readys_valid, _readys_filter_T)
node readys_filter = cat(_readys_filter_T_1, readys_valid)
node _readys_unready_T = shr(readys_filter, 1)
node _readys_unready_T_1 = or(readys_filter, _readys_unready_T)
node _readys_unready_T_2 = shr(_readys_unready_T_1, 2)
node _readys_unready_T_3 = or(_readys_unready_T_1, _readys_unready_T_2)
node _readys_unready_T_4 = bits(_readys_unready_T_3, 5, 0)
node _readys_unready_T_5 = shr(_readys_unready_T_4, 1)
node _readys_unready_T_6 = shl(readys_mask, 3)
node readys_unready = or(_readys_unready_T_5, _readys_unready_T_6)
node _readys_readys_T = shr(readys_unready, 3)
node _readys_readys_T_1 = bits(readys_unready, 2, 0)
node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1)
node readys_readys = not(_readys_readys_T_2)
node _readys_T_5 = orr(readys_valid)
node _readys_T_6 = and(latch, _readys_T_5)
when _readys_T_6 :
node _readys_mask_T = and(readys_readys, readys_valid)
node _readys_mask_T_1 = shl(_readys_mask_T, 1)
node _readys_mask_T_2 = bits(_readys_mask_T_1, 2, 0)
node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2)
node _readys_mask_T_4 = shl(_readys_mask_T_3, 2)
node _readys_mask_T_5 = bits(_readys_mask_T_4, 2, 0)
node _readys_mask_T_6 = or(_readys_mask_T_3, _readys_mask_T_5)
node _readys_mask_T_7 = bits(_readys_mask_T_6, 2, 0)
connect readys_mask, _readys_mask_T_7
node _readys_T_7 = bits(readys_readys, 2, 0)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
node _readys_T_10 = bits(_readys_T_7, 2, 2)
wire readys : UInt<1>[3]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
connect readys[2], _readys_T_10
node _winner_T = and(readys[0], portsAOI_filtered[0].valid)
node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid)
node _winner_T_2 = and(readys[2], portsAOI_filtered_2[0].valid)
wire winner : UInt<1>[3]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
connect winner[2], _winner_T_2
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node prefixOR_2 = or(prefixOR_1, winner[1])
node _prefixOR_T = or(prefixOR_2, winner[2])
node _T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_1 = eq(winner[0], UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = eq(prefixOR_1, UInt<1>(0h0))
node _T_4 = eq(winner[1], UInt<1>(0h0))
node _T_5 = or(_T_3, _T_4)
node _T_6 = eq(prefixOR_2, UInt<1>(0h0))
node _T_7 = eq(winner[2], UInt<1>(0h0))
node _T_8 = or(_T_6, _T_7)
node _T_9 = and(_T_2, _T_5)
node _T_10 = and(_T_9, _T_8)
node _T_11 = asUInt(reset)
node _T_12 = eq(_T_11, UInt<1>(0h0))
when _T_12 :
node _T_13 = eq(_T_10, UInt<1>(0h0))
when _T_13 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf
assert(clock, _T_10, UInt<1>(0h1), "") : assert
node _T_14 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _T_15 = or(_T_14, portsAOI_filtered_2[0].valid)
node _T_16 = eq(_T_15, UInt<1>(0h0))
node _T_17 = or(winner[0], winner[1])
node _T_18 = or(_T_17, winner[2])
node _T_19 = or(_T_16, _T_18)
node _T_20 = asUInt(reset)
node _T_21 = eq(_T_20, UInt<1>(0h0))
when _T_21 :
node _T_22 = eq(_T_19, UInt<1>(0h0))
when _T_22 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1
assert(clock, _T_19, UInt<1>(0h1), "") : assert_1
node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0))
node maskedBeats_2 = mux(winner[2], beatsAI_2, UInt<1>(0h0))
node _initBeats_T = or(maskedBeats_0, maskedBeats_1)
node initBeats = or(_initBeats_T, maskedBeats_2)
node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[3]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
connect _state_WIRE[2], UInt<1>(0h0)
regreset state : UInt<1>[3], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _filtered_0_ready_T = and(out[0].a.ready, allowed[0])
connect portsAOI_filtered[0].ready, _filtered_0_ready_T
node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1])
connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1
node _filtered_0_ready_T_2 = and(out[0].a.ready, allowed[2])
connect portsAOI_filtered_2[0].ready, _filtered_0_ready_T_2
node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _out_0_a_valid_T_1 = or(_out_0_a_valid_T, portsAOI_filtered_2[0].valid)
node _out_0_a_valid_T_2 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_3 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_4 = mux(state[2], portsAOI_filtered_2[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_5 = or(_out_0_a_valid_T_2, _out_0_a_valid_T_3)
node _out_0_a_valid_T_6 = or(_out_0_a_valid_T_5, _out_0_a_valid_T_4)
wire _out_0_a_valid_WIRE : UInt<1>
connect _out_0_a_valid_WIRE, _out_0_a_valid_T_6
node _out_0_a_valid_T_7 = mux(idle, _out_0_a_valid_T_1, _out_0_a_valid_WIRE)
connect out[0].a.valid, _out_0_a_valid_T_7
wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}
node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_2 = mux(muxState[2], portsAOI_filtered_2[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_3 = or(_out_0_a_bits_T, _out_0_a_bits_T_1)
node _out_0_a_bits_T_4 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_2)
wire _out_0_a_bits_WIRE_1 : UInt<1>
connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_4
connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1
node _out_0_a_bits_T_5 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_6 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_7 = mux(muxState[2], portsAOI_filtered_2[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_5, _out_0_a_bits_T_6)
node _out_0_a_bits_T_9 = or(_out_0_a_bits_T_8, _out_0_a_bits_T_7)
wire _out_0_a_bits_WIRE_2 : UInt<128>
connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_9
connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2
node _out_0_a_bits_T_10 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_11 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_12 = mux(muxState[2], portsAOI_filtered_2[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_13 = or(_out_0_a_bits_T_10, _out_0_a_bits_T_11)
node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_13, _out_0_a_bits_T_12)
wire _out_0_a_bits_WIRE_3 : UInt<16>
connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_14
connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3
wire _out_0_a_bits_WIRE_4 : { }
connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4
wire _out_0_a_bits_WIRE_5 : { }
connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5
node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_17 = mux(muxState[2], portsAOI_filtered_2[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_18 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16)
node _out_0_a_bits_T_19 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_17)
wire _out_0_a_bits_WIRE_6 : UInt<32>
connect _out_0_a_bits_WIRE_6, _out_0_a_bits_T_19
connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_6
node _out_0_a_bits_T_20 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_21 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_22 = mux(muxState[2], portsAOI_filtered_2[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_20, _out_0_a_bits_T_21)
node _out_0_a_bits_T_24 = or(_out_0_a_bits_T_23, _out_0_a_bits_T_22)
wire _out_0_a_bits_WIRE_7 : UInt<6>
connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_24
connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_7
node _out_0_a_bits_T_25 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_26 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_27 = mux(muxState[2], portsAOI_filtered_2[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_28 = or(_out_0_a_bits_T_25, _out_0_a_bits_T_26)
node _out_0_a_bits_T_29 = or(_out_0_a_bits_T_28, _out_0_a_bits_T_27)
wire _out_0_a_bits_WIRE_8 : UInt<4>
connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_29
connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_8
node _out_0_a_bits_T_30 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_31 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_32 = mux(muxState[2], portsAOI_filtered_2[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_33 = or(_out_0_a_bits_T_30, _out_0_a_bits_T_31)
node _out_0_a_bits_T_34 = or(_out_0_a_bits_T_33, _out_0_a_bits_T_32)
wire _out_0_a_bits_WIRE_9 : UInt<3>
connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_34
connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_9
node _out_0_a_bits_T_35 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_36 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_37 = mux(muxState[2], portsAOI_filtered_2[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_38 = or(_out_0_a_bits_T_35, _out_0_a_bits_T_36)
node _out_0_a_bits_T_39 = or(_out_0_a_bits_T_38, _out_0_a_bits_T_37)
wire _out_0_a_bits_WIRE_10 : UInt<3>
connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_39
connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_10
connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt
connect out[0].a.bits.data, _out_0_a_bits_WIRE.data
connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask
connect out[0].a.bits.address, _out_0_a_bits_WIRE.address
connect out[0].a.bits.source, _out_0_a_bits_WIRE.source
connect out[0].a.bits.size, _out_0_a_bits_WIRE.size
connect out[0].a.bits.param, _out_0_a_bits_WIRE.param
connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode
connect out[0].c, portsCOI_filtered[0]
connect out[0].e, portsEOI_filtered[0]
connect portsCOI_filtered_1[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_2[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_1[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_2[0].ready, UInt<1>(0h0)
connect in[0].b, portsBIO_filtered[0]
connect in[0].d, portsDIO_filtered[0]
invalidate in[1].b.bits.corrupt
invalidate in[1].b.bits.data
invalidate in[1].b.bits.mask
invalidate in[1].b.bits.address
invalidate in[1].b.bits.source
invalidate in[1].b.bits.size
invalidate in[1].b.bits.param
invalidate in[1].b.bits.opcode
connect in[1].d, portsDIO_filtered[1]
connect portsBIO_filtered[1].ready, UInt<1>(0h0)
invalidate in[2].b.bits.corrupt
invalidate in[2].b.bits.data
invalidate in[2].b.bits.mask
invalidate in[2].b.bits.address
invalidate in[2].b.bits.source
invalidate in[2].b.bits.size
invalidate in[2].b.bits.param
invalidate in[2].b.bits.opcode
connect in[2].d, portsDIO_filtered[2]
connect portsBIO_filtered[2].ready, UInt<1>(0h0) | module TLXbar_MasterXbar_RocketTile_i3_o1_a32d128s6k4z4c( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset, // @[Xbar.scala:74:9]
output auto_anon_in_2_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_2_a_valid, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_2_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_2_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_2_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_anon_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_0_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_0_b_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_in_0_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_anon_in_0_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_anon_in_0_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_0_c_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_0_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_anon_in_0_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_e_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_0_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_b_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_anon_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_anon_out_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_anon_out_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_anon_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_anon_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire [3:0] out_0_e_bits_sink; // @[Xbar.scala:216:19]
wire [3:0] out_0_d_bits_sink; // @[Xbar.scala:216:19]
wire [5:0] in_1_a_bits_source; // @[Xbar.scala:159:18]
wire [5:0] in_0_c_bits_source; // @[Xbar.scala:159:18]
wire [5:0] in_0_a_bits_source; // @[Xbar.scala:159:18]
wire auto_anon_in_2_a_valid_0 = auto_anon_in_2_a_valid; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_2_a_bits_address_0 = auto_anon_in_2_a_bits_address; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_a_bits_opcode_0 = auto_anon_in_1_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_a_bits_param_0 = auto_anon_in_1_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_a_bits_size_0 = auto_anon_in_1_a_bits_size; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_1_a_bits_source_0 = auto_anon_in_1_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9]
wire [15:0] auto_anon_in_1_a_bits_mask_0 = auto_anon_in_1_a_bits_mask; // @[Xbar.scala:74:9]
wire [127:0] auto_anon_in_1_a_bits_data_0 = auto_anon_in_1_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_bits_corrupt_0 = auto_anon_in_1_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_ready_0 = auto_anon_in_1_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9]
wire [15:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9]
wire [127:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_0_b_ready_0 = auto_anon_in_0_b_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_0_c_valid_0 = auto_anon_in_0_c_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_c_bits_opcode_0 = auto_anon_in_0_c_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_c_bits_param_0 = auto_anon_in_0_c_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_c_bits_size_0 = auto_anon_in_0_c_bits_size; // @[Xbar.scala:74:9]
wire auto_anon_in_0_c_bits_source_0 = auto_anon_in_0_c_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_0_c_bits_address_0 = auto_anon_in_0_c_bits_address; // @[Xbar.scala:74:9]
wire [127:0] auto_anon_in_0_c_bits_data_0 = auto_anon_in_0_c_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_0_e_valid_0 = auto_anon_in_0_e_valid; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_e_bits_sink_0 = auto_anon_in_0_e_bits_sink; // @[Xbar.scala:74:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_b_valid_0 = auto_anon_out_b_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_b_bits_opcode_0 = auto_anon_out_b_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_b_bits_param_0 = auto_anon_out_b_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_b_bits_size_0 = auto_anon_out_b_bits_size; // @[Xbar.scala:74:9]
wire [5:0] auto_anon_out_b_bits_source_0 = auto_anon_out_b_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_out_b_bits_address_0 = auto_anon_out_b_bits_address; // @[Xbar.scala:74:9]
wire [15:0] auto_anon_out_b_bits_mask_0 = auto_anon_out_b_bits_mask; // @[Xbar.scala:74:9]
wire [127:0] auto_anon_out_b_bits_data_0 = auto_anon_out_b_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_b_bits_corrupt_0 = auto_anon_out_b_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_out_c_ready_0 = auto_anon_out_c_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Xbar.scala:74:9]
wire [5:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9]
wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9]
wire [127:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_out_e_ready_0 = auto_anon_out_e_ready; // @[Xbar.scala:74:9]
wire _readys_T_2 = reset; // @[Arbiter.scala:22:12]
wire auto_anon_in_2_d_ready = 1'h1; // @[Xbar.scala:74:9]
wire anonIn_2_d_ready = 1'h1; // @[MixedNode.scala:551:17]
wire in_1_b_ready = 1'h1; // @[Xbar.scala:159:18]
wire in_2_b_ready = 1'h1; // @[Xbar.scala:159:18]
wire in_2_d_ready = 1'h1; // @[Xbar.scala:159:18]
wire _requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107]
wire _requestAIO_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire requestAIO_1_0 = 1'h1; // @[Xbar.scala:307:107]
wire _requestAIO_T_14 = 1'h1; // @[Parameters.scala:137:59]
wire requestAIO_2_0 = 1'h1; // @[Xbar.scala:307:107]
wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_14 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_2_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire _requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_6 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_8 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_1_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_11 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_12 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_13 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_14 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_2_0 = 1'h1; // @[Parameters.scala:56:48]
wire _beatsAI_opdata_T_2 = 1'h1; // @[Edges.scala:92:37]
wire _portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsAOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsAOI_filtered_0_valid_T_4 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_4 = 1'h1; // @[Xbar.scala:355:54]
wire portsDIO_filtered_2_ready = 1'h1; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_4 = 1'h1; // @[Xbar.scala:355:54]
wire [2:0] auto_anon_in_2_a_bits_opcode = 3'h4; // @[Xbar.scala:74:9]
wire [2:0] anonIn_2_a_bits_opcode = 3'h4; // @[MixedNode.scala:551:17]
wire [2:0] in_2_a_bits_opcode = 3'h4; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_2_0_bits_opcode = 3'h4; // @[Xbar.scala:352:24]
wire [2:0] auto_anon_in_2_a_bits_param = 3'h0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_2_a_bits_param = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] in_1_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_1_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_1_c_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_2_a_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_2_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_2_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_2_c_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] portsAOI_filtered_2_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_2_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_2_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _out_0_a_bits_T_32 = 3'h0; // @[Mux.scala:30:73]
wire [3:0] auto_anon_in_2_a_bits_size = 4'h6; // @[Xbar.scala:74:9]
wire [3:0] anonIn_2_a_bits_size = 4'h6; // @[MixedNode.scala:551:17]
wire [3:0] in_2_a_bits_size = 4'h6; // @[Xbar.scala:159:18]
wire [3:0] portsAOI_filtered_2_0_bits_size = 4'h6; // @[Xbar.scala:352:24]
wire auto_anon_in_2_a_bits_source = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_2_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_2_d_bits_source = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_out_c_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_2_a_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_2_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_2_d_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire in_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_1_b_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_1_c_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_1_c_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_1_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_1_e_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_1_e_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_2_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_2_b_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_2_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_2_c_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_2_c_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_2_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_2_e_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_2_e_valid = 1'h0; // @[Xbar.scala:159:18]
wire out_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:216:19]
wire _requestEIO_T = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_T_5 = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_T_10 = 1'h0; // @[Parameters.scala:54:10]
wire beatsAI_opdata_2 = 1'h0; // @[Edges.scala:92:28]
wire beatsCI_opdata_1 = 1'h0; // @[Edges.scala:102:36]
wire beatsCI_opdata_2 = 1'h0; // @[Edges.scala:102:36]
wire portsAOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsAOI_filtered_2_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_2_ready = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_out_0_b_ready_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_2 = 1'h0; // @[Mux.scala:30:73]
wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire portsCOI_filtered_2_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_2_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_2_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_5 = 1'h0; // @[Xbar.scala:355:40]
wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire portsEOI_filtered_2_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_2_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_5 = 1'h0; // @[Xbar.scala:355:40]
wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_2 = 1'h0; // @[Arbiter.scala:88:34]
wire _out_0_a_bits_T = 1'h0; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_2 = 1'h0; // @[Mux.scala:30:73]
wire [15:0] auto_anon_in_2_a_bits_mask = 16'hFFFF; // @[Xbar.scala:74:9]
wire [15:0] anonIn_2_a_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17]
wire [15:0] in_2_a_bits_mask = 16'hFFFF; // @[Xbar.scala:159:18]
wire [15:0] portsAOI_filtered_2_0_bits_mask = 16'hFFFF; // @[Xbar.scala:352:24]
wire [127:0] auto_anon_in_2_a_bits_data = 128'h0; // @[Xbar.scala:74:9]
wire [127:0] anonIn_2_a_bits_data = 128'h0; // @[MixedNode.scala:551:17]
wire [127:0] in_1_b_bits_data = 128'h0; // @[Xbar.scala:159:18]
wire [127:0] in_1_c_bits_data = 128'h0; // @[Xbar.scala:159:18]
wire [127:0] in_2_a_bits_data = 128'h0; // @[Xbar.scala:159:18]
wire [127:0] in_2_b_bits_data = 128'h0; // @[Xbar.scala:159:18]
wire [127:0] in_2_c_bits_data = 128'h0; // @[Xbar.scala:159:18]
wire [127:0] portsAOI_filtered_2_0_bits_data = 128'h0; // @[Xbar.scala:352:24]
wire [127:0] portsCOI_filtered_1_0_bits_data = 128'h0; // @[Xbar.scala:352:24]
wire [127:0] portsCOI_filtered_2_0_bits_data = 128'h0; // @[Xbar.scala:352:24]
wire [127:0] _out_0_a_bits_T_7 = 128'h0; // @[Mux.scala:30:73]
wire [7:0] beatsAI_2 = 8'h0; // @[Edges.scala:221:14]
wire [7:0] beatsBO_0 = 8'h0; // @[Edges.scala:221:14]
wire [7:0] beatsCI_decode_1 = 8'h0; // @[Edges.scala:220:59]
wire [7:0] beatsCI_1 = 8'h0; // @[Edges.scala:221:14]
wire [7:0] beatsCI_decode_2 = 8'h0; // @[Edges.scala:220:59]
wire [7:0] beatsCI_2 = 8'h0; // @[Edges.scala:221:14]
wire [7:0] maskedBeats_2 = 8'h0; // @[Arbiter.scala:82:69]
wire [3:0] in_1_b_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_1_c_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_1_e_bits_sink = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_2_b_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_2_c_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_2_e_bits_sink = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] _requestEIO_uncommonBits_T_1 = 4'h0; // @[Parameters.scala:52:29]
wire [3:0] requestEIO_uncommonBits_1 = 4'h0; // @[Parameters.scala:52:56]
wire [3:0] _requestEIO_uncommonBits_T_2 = 4'h0; // @[Parameters.scala:52:29]
wire [3:0] requestEIO_uncommonBits_2 = 4'h0; // @[Parameters.scala:52:56]
wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_2_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsEOI_filtered_1_0_bits_sink = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsEOI_filtered_2_0_bits_sink = 4'h0; // @[Xbar.scala:352:24]
wire [31:0] in_1_b_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_1_c_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_2_b_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_2_c_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_10 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] portsCOI_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_2_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [5:0] in_1_b_bits_source = 6'h0; // @[Xbar.scala:159:18]
wire [5:0] in_1_c_bits_source = 6'h0; // @[Xbar.scala:159:18]
wire [5:0] in_2_b_bits_source = 6'h0; // @[Xbar.scala:159:18]
wire [5:0] in_2_c_bits_source = 6'h0; // @[Xbar.scala:159:18]
wire [5:0] portsCOI_filtered_1_0_bits_source = 6'h0; // @[Xbar.scala:352:24]
wire [5:0] portsCOI_filtered_2_0_bits_source = 6'h0; // @[Xbar.scala:352:24]
wire [5:0] in_2_a_bits_source = 6'h22; // @[Xbar.scala:159:18]
wire [5:0] _in_2_a_bits_source_T = 6'h22; // @[Xbar.scala:166:55]
wire [5:0] portsAOI_filtered_2_0_bits_source = 6'h22; // @[Xbar.scala:352:24]
wire [11:0] _beatsCI_decode_T_5 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_8 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_4 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_7 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _beatsCI_decode_T_3 = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T_6 = 27'hFFF; // @[package.scala:243:71]
wire [7:0] beatsAI_decode_2 = 8'h3; // @[Edges.scala:220:59]
wire [11:0] _beatsAI_decode_T_8 = 12'h3F; // @[package.scala:243:46]
wire [11:0] _beatsAI_decode_T_7 = 12'hFC0; // @[package.scala:243:76]
wire [26:0] _beatsAI_decode_T_6 = 27'h3FFC0; // @[package.scala:243:71]
wire [32:0] _requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_12 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_13 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_11 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_12 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_13 = 33'h0; // @[Parameters.scala:137:46]
wire [15:0] in_1_b_bits_mask = 16'h0; // @[Xbar.scala:159:18]
wire [15:0] in_2_b_bits_mask = 16'h0; // @[Xbar.scala:159:18]
wire [1:0] in_1_b_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire [1:0] in_2_b_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire anonIn_2_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_2_a_valid = auto_anon_in_2_a_valid_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_2_a_bits_address = auto_anon_in_2_a_bits_address_0; // @[Xbar.scala:74:9]
wire anonIn_2_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_2_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_2_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_2_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_2_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_2_d_bits_denied; // @[MixedNode.scala:551:17]
wire [127:0] anonIn_2_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_2_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_1_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_a_bits_opcode = auto_anon_in_1_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_a_bits_param = auto_anon_in_1_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_1_a_bits_size = auto_anon_in_1_a_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] anonIn_1_a_bits_source = auto_anon_in_1_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9]
wire [15:0] anonIn_1_a_bits_mask = auto_anon_in_1_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [127:0] anonIn_1_a_bits_data = auto_anon_in_1_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_1_a_bits_corrupt = auto_anon_in_1_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_1_d_ready = auto_anon_in_1_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_1_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] anonIn_1_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17]
wire [127:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9]
wire anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9]
wire [15:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [127:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_b_ready = auto_anon_in_0_b_ready_0; // @[Xbar.scala:74:9]
wire anonIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_b_bits_size; // @[MixedNode.scala:551:17]
wire anonIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] anonIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [15:0] anonIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [127:0] anonIn_b_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_c_ready; // @[MixedNode.scala:551:17]
wire anonIn_c_valid = auto_anon_in_0_c_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_c_bits_opcode = auto_anon_in_0_c_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_c_bits_param = auto_anon_in_0_c_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_c_bits_size = auto_anon_in_0_c_bits_size_0; // @[Xbar.scala:74:9]
wire anonIn_c_bits_source = auto_anon_in_0_c_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_c_bits_address = auto_anon_in_0_c_bits_address_0; // @[Xbar.scala:74:9]
wire [127:0] anonIn_c_bits_data = auto_anon_in_0_c_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [127:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_e_ready; // @[MixedNode.scala:551:17]
wire anonIn_e_valid = auto_anon_in_0_e_valid_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_e_bits_sink = auto_anon_in_0_e_bits_sink_0; // @[Xbar.scala:74:9]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Xbar.scala:74:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [5:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [15:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [127:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_b_ready; // @[MixedNode.scala:542:17]
wire anonOut_b_valid = auto_anon_out_b_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonOut_b_bits_opcode = auto_anon_out_b_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] anonOut_b_bits_param = auto_anon_out_b_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonOut_b_bits_size = auto_anon_out_b_bits_size_0; // @[Xbar.scala:74:9]
wire [5:0] anonOut_b_bits_source = auto_anon_out_b_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonOut_b_bits_address = auto_anon_out_b_bits_address_0; // @[Xbar.scala:74:9]
wire [15:0] anonOut_b_bits_mask = auto_anon_out_b_bits_mask_0; // @[Xbar.scala:74:9]
wire [127:0] anonOut_b_bits_data = auto_anon_out_b_bits_data_0; // @[Xbar.scala:74:9]
wire anonOut_b_bits_corrupt = auto_anon_out_b_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonOut_c_ready = auto_anon_out_c_ready_0; // @[Xbar.scala:74:9]
wire anonOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [5:0] anonOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [127:0] anonOut_c_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Xbar.scala:74:9]
wire [5:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Xbar.scala:74:9]
wire [3:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [127:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonOut_e_ready = auto_anon_out_e_ready_0; // @[Xbar.scala:74:9]
wire anonOut_e_valid; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire auto_anon_in_2_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_2_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_2_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_2_d_bits_size_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_2_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_2_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [127:0] auto_anon_in_2_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_2_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_2_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_1_d_bits_source_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [127:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_b_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_0_b_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_b_bits_size_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_b_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_0_b_bits_address_0; // @[Xbar.scala:74:9]
wire [15:0] auto_anon_in_0_b_bits_mask_0; // @[Xbar.scala:74:9]
wire [127:0] auto_anon_in_0_b_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_b_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_b_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_c_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_source_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [127:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_e_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_a_bits_size_0; // @[Xbar.scala:74:9]
wire [5:0] auto_anon_out_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_out_a_bits_address_0; // @[Xbar.scala:74:9]
wire [15:0] auto_anon_out_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [127:0] auto_anon_out_a_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_b_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_c_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_c_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_c_bits_size_0; // @[Xbar.scala:74:9]
wire [5:0] auto_anon_out_c_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_out_c_bits_address_0; // @[Xbar.scala:74:9]
wire [127:0] auto_anon_out_c_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_c_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_d_ready_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_e_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_out_e_valid_0; // @[Xbar.scala:74:9]
wire in_0_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9]
wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18]
wire [15:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18]
wire [127:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18]
wire in_0_b_ready = anonIn_b_ready; // @[Xbar.scala:159:18]
wire in_0_b_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_0_b_valid_0 = anonIn_b_valid; // @[Xbar.scala:74:9]
wire [2:0] in_0_b_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_0_b_bits_opcode_0 = anonIn_b_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_0_b_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_0_b_bits_param_0 = anonIn_b_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_0_b_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_0_b_bits_size_0 = anonIn_b_bits_size; // @[Xbar.scala:74:9]
wire _anonIn_b_bits_source_T; // @[Xbar.scala:156:69]
assign auto_anon_in_0_b_bits_source_0 = anonIn_b_bits_source; // @[Xbar.scala:74:9]
wire [31:0] in_0_b_bits_address; // @[Xbar.scala:159:18]
assign auto_anon_in_0_b_bits_address_0 = anonIn_b_bits_address; // @[Xbar.scala:74:9]
wire [15:0] in_0_b_bits_mask; // @[Xbar.scala:159:18]
assign auto_anon_in_0_b_bits_mask_0 = anonIn_b_bits_mask; // @[Xbar.scala:74:9]
wire [127:0] in_0_b_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_0_b_bits_data_0 = anonIn_b_bits_data; // @[Xbar.scala:74:9]
wire in_0_b_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_0_b_bits_corrupt_0 = anonIn_b_bits_corrupt; // @[Xbar.scala:74:9]
wire in_0_c_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_0_c_ready_0 = anonIn_c_ready; // @[Xbar.scala:74:9]
wire in_0_c_valid = anonIn_c_valid; // @[Xbar.scala:159:18]
wire [2:0] in_0_c_bits_opcode = anonIn_c_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_0_c_bits_param = anonIn_c_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_0_c_bits_size = anonIn_c_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_0_c_bits_address = anonIn_c_bits_address; // @[Xbar.scala:159:18]
wire [127:0] in_0_c_bits_data = anonIn_c_bits_data; // @[Xbar.scala:159:18]
wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18]
wire in_0_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9]
wire _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9]
wire [3:0] in_0_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9]
wire in_0_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9]
wire [127:0] in_0_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9]
wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_0_e_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_0_e_ready_0 = anonIn_e_ready; // @[Xbar.scala:74:9]
wire in_0_e_valid = anonIn_e_valid; // @[Xbar.scala:159:18]
wire [3:0] in_0_e_bits_sink = anonIn_e_bits_sink; // @[Xbar.scala:159:18]
wire in_1_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9]
wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_1_a_bits_opcode = anonIn_1_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_1_a_bits_param = anonIn_1_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_1_a_bits_size = anonIn_1_a_bits_size; // @[Xbar.scala:159:18]
wire [4:0] _in_1_a_bits_source_T = anonIn_1_a_bits_source; // @[Xbar.scala:166:55]
wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18]
wire [15:0] in_1_a_bits_mask = anonIn_1_a_bits_mask; // @[Xbar.scala:159:18]
wire [127:0] in_1_a_bits_data = anonIn_1_a_bits_data; // @[Xbar.scala:159:18]
wire in_1_a_bits_corrupt = anonIn_1_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_1_d_ready = anonIn_1_d_ready; // @[Xbar.scala:159:18]
wire in_1_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9]
wire [4:0] _anonIn_d_bits_source_T_1; // @[Xbar.scala:156:69]
assign auto_anon_in_1_d_bits_source_0 = anonIn_1_d_bits_source; // @[Xbar.scala:74:9]
wire [3:0] in_1_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9]
wire in_1_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9]
wire [127:0] in_1_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9]
wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_2_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_2_a_ready_0 = anonIn_2_a_ready; // @[Xbar.scala:74:9]
wire in_2_a_valid = anonIn_2_a_valid; // @[Xbar.scala:159:18]
wire [31:0] in_2_a_bits_address = anonIn_2_a_bits_address; // @[Xbar.scala:159:18]
wire in_2_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_2_d_valid_0 = anonIn_2_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_2_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_2_d_bits_opcode_0 = anonIn_2_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_2_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_2_d_bits_param_0 = anonIn_2_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_2_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_2_d_bits_size_0 = anonIn_2_d_bits_size; // @[Xbar.scala:74:9]
wire [3:0] in_2_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_2_d_bits_sink_0 = anonIn_2_d_bits_sink; // @[Xbar.scala:74:9]
wire in_2_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_2_d_bits_denied_0 = anonIn_2_d_bits_denied; // @[Xbar.scala:74:9]
wire [127:0] in_2_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_2_d_bits_data_0 = anonIn_2_d_bits_data; // @[Xbar.scala:74:9]
wire in_2_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_2_d_bits_corrupt_0 = anonIn_2_d_bits_corrupt; // @[Xbar.scala:74:9]
wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19]
wire out_0_a_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire [5:0] out_0_a_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire [15:0] out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [127:0] out_0_a_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9]
wire out_0_b_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_b_ready_0 = anonOut_b_ready; // @[Xbar.scala:74:9]
wire out_0_b_valid = anonOut_b_valid; // @[Xbar.scala:216:19]
wire [2:0] out_0_b_bits_opcode = anonOut_b_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] out_0_b_bits_param = anonOut_b_bits_param; // @[Xbar.scala:216:19]
wire [3:0] out_0_b_bits_size = anonOut_b_bits_size; // @[Xbar.scala:216:19]
wire [5:0] out_0_b_bits_source = anonOut_b_bits_source; // @[Xbar.scala:216:19]
wire [31:0] out_0_b_bits_address = anonOut_b_bits_address; // @[Xbar.scala:216:19]
wire [15:0] out_0_b_bits_mask = anonOut_b_bits_mask; // @[Xbar.scala:216:19]
wire [127:0] out_0_b_bits_data = anonOut_b_bits_data; // @[Xbar.scala:216:19]
wire out_0_b_bits_corrupt = anonOut_b_bits_corrupt; // @[Xbar.scala:216:19]
wire out_0_c_ready = anonOut_c_ready; // @[Xbar.scala:216:19]
wire out_0_c_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_c_valid_0 = anonOut_c_valid; // @[Xbar.scala:74:9]
wire [2:0] out_0_c_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_c_bits_opcode_0 = anonOut_c_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_0_c_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_c_bits_param_0 = anonOut_c_bits_param; // @[Xbar.scala:74:9]
wire [3:0] out_0_c_bits_size; // @[Xbar.scala:216:19]
assign auto_anon_out_c_bits_size_0 = anonOut_c_bits_size; // @[Xbar.scala:74:9]
wire [5:0] out_0_c_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_c_bits_source_0 = anonOut_c_bits_source; // @[Xbar.scala:74:9]
wire [31:0] out_0_c_bits_address; // @[Xbar.scala:216:19]
assign auto_anon_out_c_bits_address_0 = anonOut_c_bits_address; // @[Xbar.scala:74:9]
wire [127:0] out_0_c_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_c_bits_data_0 = anonOut_c_bits_data; // @[Xbar.scala:74:9]
wire out_0_d_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9]
wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [5:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire [3:0] _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [127:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire out_0_e_ready = anonOut_e_ready; // @[Xbar.scala:216:19]
wire out_0_e_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_e_valid_0 = anonOut_e_valid; // @[Xbar.scala:74:9]
wire [3:0] _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69]
assign auto_anon_out_e_bits_sink_0 = anonOut_e_bits_sink; // @[Xbar.scala:74:9]
wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18]
wire _portsAOI_filtered_0_valid_T_1 = in_0_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [5:0] _in_0_a_bits_source_T; // @[Xbar.scala:166:55]
wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [5:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [15:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [127:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsBIO_filtered_0_ready = in_0_b_ready; // @[Xbar.scala:159:18, :352:24]
wire portsBIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign anonIn_b_valid = in_0_b_valid; // @[Xbar.scala:159:18]
wire [2:0] portsBIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24]
assign anonIn_b_bits_opcode = in_0_b_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] portsBIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign anonIn_b_bits_param = in_0_b_bits_param; // @[Xbar.scala:159:18]
wire [3:0] portsBIO_filtered_0_bits_size; // @[Xbar.scala:352:24]
assign anonIn_b_bits_size = in_0_b_bits_size; // @[Xbar.scala:159:18]
wire [5:0] portsBIO_filtered_0_bits_source; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_0_bits_address; // @[Xbar.scala:352:24]
assign anonIn_b_bits_address = in_0_b_bits_address; // @[Xbar.scala:159:18]
wire [15:0] portsBIO_filtered_0_bits_mask; // @[Xbar.scala:352:24]
assign anonIn_b_bits_mask = in_0_b_bits_mask; // @[Xbar.scala:159:18]
wire [127:0] portsBIO_filtered_0_bits_data; // @[Xbar.scala:352:24]
assign anonIn_b_bits_data = in_0_b_bits_data; // @[Xbar.scala:159:18]
wire portsBIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24]
assign anonIn_b_bits_corrupt = in_0_b_bits_corrupt; // @[Xbar.scala:159:18]
wire portsCOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign anonIn_c_ready = in_0_c_ready; // @[Xbar.scala:159:18]
wire _portsCOI_filtered_0_valid_T_1 = in_0_c_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] portsCOI_filtered_0_bits_opcode = in_0_c_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsCOI_filtered_0_bits_param = in_0_c_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [5:0] _in_0_c_bits_source_T; // @[Xbar.scala:187:55]
wire [3:0] portsCOI_filtered_0_bits_size = in_0_c_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [5:0] portsCOI_filtered_0_bits_source = in_0_c_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestCIO_T = in_0_c_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsCOI_filtered_0_bits_address = in_0_c_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [127:0] portsCOI_filtered_0_bits_data = in_0_c_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_0_ready = in_0_d_ready; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18]
wire [2:0] portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24]
assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24]
assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18]
wire [5:0] portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24]
wire [3:0] portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24]
assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18]
wire portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24]
assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18]
wire [127:0] portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24]
assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18]
wire portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24]
assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
wire portsEOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign anonIn_e_ready = in_0_e_ready; // @[Xbar.scala:159:18]
wire _portsEOI_filtered_0_valid_T_1 = in_0_e_valid; // @[Xbar.scala:159:18, :355:40]
wire [3:0] _requestEIO_uncommonBits_T = in_0_e_bits_sink; // @[Xbar.scala:159:18]
wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24]
wire [3:0] portsEOI_filtered_0_bits_sink = in_0_e_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18]
wire _portsAOI_filtered_0_valid_T_3 = in_1_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] portsAOI_filtered_1_0_bits_opcode = in_1_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_1_0_bits_param = in_1_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_1_0_bits_size = in_1_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [5:0] portsAOI_filtered_1_0_bits_source = in_1_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_5 = in_1_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [15:0] portsAOI_filtered_1_0_bits_mask = in_1_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [127:0] portsAOI_filtered_1_0_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_0_bits_corrupt = in_1_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_1_ready = in_1_d_ready; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24]
assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18]
wire [2:0] portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] portsDIO_filtered_1_bits_param; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] portsDIO_filtered_1_bits_size; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18]
wire [5:0] portsDIO_filtered_1_bits_source; // @[Xbar.scala:352:24]
wire [3:0] portsDIO_filtered_1_bits_sink; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18]
wire portsDIO_filtered_1_bits_denied; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18]
wire [127:0] portsDIO_filtered_1_bits_data; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18]
wire portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18]
wire portsAOI_filtered_2_0_ready; // @[Xbar.scala:352:24]
assign anonIn_2_a_ready = in_2_a_ready; // @[Xbar.scala:159:18]
wire _portsAOI_filtered_0_valid_T_5 = in_2_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [31:0] _requestAIO_T_10 = in_2_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_2_0_bits_address = in_2_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_2_valid; // @[Xbar.scala:352:24]
assign anonIn_2_d_valid = in_2_d_valid; // @[Xbar.scala:159:18]
wire [2:0] portsDIO_filtered_2_bits_opcode; // @[Xbar.scala:352:24]
assign anonIn_2_d_bits_opcode = in_2_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] portsDIO_filtered_2_bits_param; // @[Xbar.scala:352:24]
assign anonIn_2_d_bits_param = in_2_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] portsDIO_filtered_2_bits_size; // @[Xbar.scala:352:24]
assign anonIn_2_d_bits_size = in_2_d_bits_size; // @[Xbar.scala:159:18]
wire [5:0] portsDIO_filtered_2_bits_source; // @[Xbar.scala:352:24]
wire [3:0] portsDIO_filtered_2_bits_sink; // @[Xbar.scala:352:24]
assign anonIn_2_d_bits_sink = in_2_d_bits_sink; // @[Xbar.scala:159:18]
wire portsDIO_filtered_2_bits_denied; // @[Xbar.scala:352:24]
assign anonIn_2_d_bits_denied = in_2_d_bits_denied; // @[Xbar.scala:159:18]
wire [127:0] portsDIO_filtered_2_bits_data; // @[Xbar.scala:352:24]
assign anonIn_2_d_bits_data = in_2_d_bits_data; // @[Xbar.scala:159:18]
wire portsDIO_filtered_2_bits_corrupt; // @[Xbar.scala:352:24]
assign anonIn_2_d_bits_corrupt = in_2_d_bits_corrupt; // @[Xbar.scala:159:18]
wire [5:0] in_0_b_bits_source; // @[Xbar.scala:159:18]
wire [5:0] in_0_d_bits_source; // @[Xbar.scala:159:18]
wire [5:0] in_1_d_bits_source; // @[Xbar.scala:159:18]
wire [5:0] in_2_d_bits_source; // @[Xbar.scala:159:18]
assign _in_0_a_bits_source_T = {5'h10, anonIn_a_bits_source}; // @[Xbar.scala:166:55]
assign in_0_a_bits_source = _in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign _anonIn_b_bits_source_T = in_0_b_bits_source[0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_b_bits_source = _anonIn_b_bits_source_T; // @[Xbar.scala:156:69]
assign _in_0_c_bits_source_T = {5'h10, anonIn_c_bits_source}; // @[Xbar.scala:187:55]
assign in_0_c_bits_source = _in_0_c_bits_source_T; // @[Xbar.scala:159:18, :187:55]
assign _anonIn_d_bits_source_T = in_0_d_bits_source[0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign in_1_a_bits_source = {1'h0, _in_1_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}]
assign _anonIn_d_bits_source_T_1 = in_1_d_bits_source[4:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_1_d_bits_source = _anonIn_d_bits_source_T_1; // @[Xbar.scala:156:69]
wire _out_0_a_valid_T_7; // @[Arbiter.scala:96:24]
assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19]
wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19]
wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19]
wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19]
wire [5:0] _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73]
assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19]
wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73]
assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19]
wire [15:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73]
assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19]
wire [127:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19]
wire _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
wire _portsBIO_out_0_b_ready_WIRE; // @[Mux.scala:30:73]
assign anonOut_b_ready = out_0_b_ready; // @[Xbar.scala:216:19]
assign portsBIO_filtered_0_bits_opcode = out_0_b_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsBIO_filtered_1_bits_opcode = out_0_b_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [2:0] portsBIO_filtered_2_bits_opcode = out_0_b_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_0_bits_param = out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsBIO_filtered_1_bits_param = out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsBIO_filtered_2_bits_param = out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_0_bits_size = out_0_b_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsBIO_filtered_1_bits_size = out_0_b_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsBIO_filtered_2_bits_size = out_0_b_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [5:0] _requestBOI_uncommonBits_T = out_0_b_bits_source; // @[Xbar.scala:216:19]
wire [5:0] _requestBOI_uncommonBits_T_1 = out_0_b_bits_source; // @[Xbar.scala:216:19]
assign portsBIO_filtered_0_bits_source = out_0_b_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [5:0] portsBIO_filtered_1_bits_source = out_0_b_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [5:0] portsBIO_filtered_2_bits_source = out_0_b_bits_source; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_0_bits_address = out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24]
wire [31:0] portsBIO_filtered_1_bits_address = out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24]
wire [31:0] portsBIO_filtered_2_bits_address = out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_0_bits_mask = out_0_b_bits_mask; // @[Xbar.scala:216:19, :352:24]
wire [15:0] portsBIO_filtered_1_bits_mask = out_0_b_bits_mask; // @[Xbar.scala:216:19, :352:24]
wire [15:0] portsBIO_filtered_2_bits_mask = out_0_b_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_0_bits_data = out_0_b_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [127:0] portsBIO_filtered_1_bits_data = out_0_b_bits_data; // @[Xbar.scala:216:19, :352:24]
wire [127:0] portsBIO_filtered_2_bits_data = out_0_b_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_0_bits_corrupt = out_0_b_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsBIO_filtered_1_bits_corrupt = out_0_b_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire portsBIO_filtered_2_bits_corrupt = out_0_b_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign portsCOI_filtered_0_ready = out_0_c_ready; // @[Xbar.scala:216:19, :352:24]
wire portsCOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign anonOut_c_valid = out_0_c_valid; // @[Xbar.scala:216:19]
assign anonOut_c_bits_opcode = out_0_c_bits_opcode; // @[Xbar.scala:216:19]
assign anonOut_c_bits_param = out_0_c_bits_param; // @[Xbar.scala:216:19]
assign anonOut_c_bits_size = out_0_c_bits_size; // @[Xbar.scala:216:19]
assign anonOut_c_bits_source = out_0_c_bits_source; // @[Xbar.scala:216:19]
assign anonOut_c_bits_address = out_0_c_bits_address; // @[Xbar.scala:216:19]
assign anonOut_c_bits_data = out_0_c_bits_data; // @[Xbar.scala:216:19]
wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73]
assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19]
assign portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_2_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_2_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_2_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [5:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [5:0] _requestDOI_uncommonBits_T_1 = out_0_d_bits_source; // @[Xbar.scala:216:19]
assign portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_2_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_2_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_2_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_2_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_2_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign portsEOI_filtered_0_ready = out_0_e_ready; // @[Xbar.scala:216:19, :352:24]
wire portsEOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign anonOut_e_valid = out_0_e_valid; // @[Xbar.scala:216:19]
assign _anonOut_e_bits_sink_T = out_0_e_bits_sink; // @[Xbar.scala:156:69, :216:19]
assign out_0_d_bits_sink = _out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
assign anonOut_e_bits_sink = _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69]
wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_11 = {1'h0, _requestAIO_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestCIO_T_1 = {1'h0, _requestCIO_T}; // @[Parameters.scala:137:{31,41}]
wire requestBOI_uncommonBits = _requestBOI_uncommonBits_T[0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _requestBOI_T = out_0_b_bits_source[5:1]; // @[Xbar.scala:216:19]
wire _requestBOI_T_1 = _requestBOI_T == 5'h10; // @[Parameters.scala:54:{10,32}]
wire _requestBOI_T_3 = _requestBOI_T_1; // @[Parameters.scala:54:{32,67}]
wire requestBOI_0_0 = _requestBOI_T_3; // @[Parameters.scala:54:67, :56:48]
wire _portsBIO_filtered_0_valid_T = requestBOI_0_0; // @[Xbar.scala:355:54]
wire [4:0] requestBOI_uncommonBits_1 = _requestBOI_uncommonBits_T_1[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestBOI_T_5 = out_0_b_bits_source[5]; // @[Xbar.scala:216:19]
wire _requestBOI_T_6 = ~_requestBOI_T_5; // @[Parameters.scala:54:{10,32}]
wire _requestBOI_T_8 = _requestBOI_T_6; // @[Parameters.scala:54:{32,67}]
wire requestBOI_0_1 = _requestBOI_T_8; // @[Parameters.scala:54:67, :56:48]
wire _portsBIO_filtered_1_valid_T = requestBOI_0_1; // @[Xbar.scala:355:54]
wire requestBOI_0_2 = out_0_b_bits_source == 6'h22; // @[Xbar.scala:216:19]
wire _portsBIO_filtered_2_valid_T = requestBOI_0_2; // @[Xbar.scala:355:54]
wire requestDOI_uncommonBits = _requestDOI_uncommonBits_T[0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _requestDOI_T = out_0_d_bits_source[5:1]; // @[Xbar.scala:216:19]
wire _requestDOI_T_1 = _requestDOI_T == 5'h10; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_3 = _requestDOI_T_1; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_0 = _requestDOI_T_3; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54]
wire [4:0] requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_5 = out_0_d_bits_source[5]; // @[Xbar.scala:216:19]
wire _requestDOI_T_6 = ~_requestDOI_T_5; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_8 = _requestDOI_T_6; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_1 = _requestDOI_T_8; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54]
wire requestDOI_0_2 = out_0_d_bits_source == 6'h22; // @[Xbar.scala:216:19]
wire _portsDIO_filtered_2_valid_T = requestDOI_0_2; // @[Xbar.scala:355:54]
wire _portsDIO_out_0_d_ready_T_2 = requestDOI_0_2; // @[Mux.scala:30:73]
wire [3:0] requestEIO_uncommonBits = _requestEIO_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] beatsAI_decode = _beatsAI_decode_T_2[11:4]; // @[package.scala:243:46]
wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}]
wire [7:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_3 = 27'hFFF << in_1_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_4 = _beatsAI_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_5 = ~_beatsAI_decode_T_4; // @[package.scala:243:{46,76}]
wire [7:0] beatsAI_decode_1 = _beatsAI_decode_T_5[11:4]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_1 = in_1_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_1 = ~_beatsAI_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [7:0] beatsAI_1 = beatsAI_opdata_1 ? beatsAI_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsBO_decode_T = 27'hFFF << out_0_b_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsBO_decode_T_1 = _beatsBO_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsBO_decode_T_2 = ~_beatsBO_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] beatsBO_decode = _beatsBO_decode_T_2[11:4]; // @[package.scala:243:46]
wire _beatsBO_opdata_T = out_0_b_bits_opcode[2]; // @[Xbar.scala:216:19]
wire beatsBO_opdata = ~_beatsBO_opdata_T; // @[Edges.scala:97:{28,37}]
wire [26:0] _beatsCI_decode_T = 27'hFFF << in_0_c_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsCI_decode_T_1 = _beatsCI_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsCI_decode_T_2 = ~_beatsCI_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] beatsCI_decode = _beatsCI_decode_T_2[11:4]; // @[package.scala:243:46]
wire beatsCI_opdata = in_0_c_bits_opcode[0]; // @[Xbar.scala:159:18]
wire [7:0] beatsCI_0 = beatsCI_opdata ? beatsCI_decode : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14]
wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] beatsDO_decode = _beatsDO_decode_T_2[11:4]; // @[package.scala:243:46]
wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [7:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire _filtered_0_ready_T; // @[Arbiter.scala:94:31]
assign in_0_a_ready = portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31]
assign in_1_a_ready = portsAOI_filtered_1_0_ready; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40]
wire _filtered_0_ready_T_2; // @[Arbiter.scala:94:31]
assign in_2_a_ready = portsAOI_filtered_2_0_ready; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_2_0_valid; // @[Xbar.scala:352:24]
assign portsAOI_filtered_2_0_valid = _portsAOI_filtered_0_valid_T_5; // @[Xbar.scala:352:24, :355:40]
wire _portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40]
assign in_0_b_valid = portsBIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign in_0_b_bits_opcode = portsBIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_0_b_bits_param = portsBIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_0_b_bits_size = portsBIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_0_b_bits_source = portsBIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_0_b_bits_address = portsBIO_filtered_0_bits_address; // @[Xbar.scala:159:18, :352:24]
assign in_0_b_bits_mask = portsBIO_filtered_0_bits_mask; // @[Xbar.scala:159:18, :352:24]
assign in_0_b_bits_data = portsBIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_0_b_bits_corrupt = portsBIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _portsBIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_2_valid_T_1; // @[Xbar.scala:355:40]
wire portsBIO_filtered_1_valid; // @[Xbar.scala:352:24]
wire portsBIO_filtered_2_valid; // @[Xbar.scala:352:24]
assign _portsBIO_filtered_0_valid_T_1 = out_0_b_valid & _portsBIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsBIO_filtered_0_valid = _portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsBIO_filtered_1_valid_T_1 = out_0_b_valid & _portsBIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsBIO_filtered_1_valid = _portsBIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsBIO_filtered_2_valid_T_1 = out_0_b_valid & _portsBIO_filtered_2_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsBIO_filtered_2_valid = _portsBIO_filtered_2_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _portsBIO_out_0_b_ready_T = requestBOI_0_0 & portsBIO_filtered_0_ready; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_3 = _portsBIO_out_0_b_ready_T; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_4 = _portsBIO_out_0_b_ready_T_3; // @[Mux.scala:30:73]
assign _portsBIO_out_0_b_ready_WIRE = _portsBIO_out_0_b_ready_T_4; // @[Mux.scala:30:73]
assign out_0_b_ready = _portsBIO_out_0_b_ready_WIRE; // @[Mux.scala:30:73]
assign in_0_c_ready = portsCOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
assign out_0_c_valid = portsCOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign out_0_c_bits_opcode = portsCOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign out_0_c_bits_param = portsCOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24]
assign out_0_c_bits_size = portsCOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24]
assign out_0_c_bits_source = portsCOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24]
assign out_0_c_bits_address = portsCOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24]
assign out_0_c_bits_data = portsCOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsCOI_filtered_0_valid = _portsCOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40]
assign in_0_d_valid = portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_opcode = portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_param = portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_size = portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_source = portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_sink = portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_denied = portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_data = portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_corrupt = portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40]
assign in_1_d_valid = portsDIO_filtered_1_valid; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_opcode = portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_param = portsDIO_filtered_1_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_size = portsDIO_filtered_1_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_source = portsDIO_filtered_1_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_sink = portsDIO_filtered_1_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_denied = portsDIO_filtered_1_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_data = portsDIO_filtered_1_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_corrupt = portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _portsDIO_filtered_2_valid_T_1; // @[Xbar.scala:355:40]
assign in_2_d_valid = portsDIO_filtered_2_valid; // @[Xbar.scala:159:18, :352:24]
assign in_2_d_bits_opcode = portsDIO_filtered_2_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_2_d_bits_param = portsDIO_filtered_2_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_2_d_bits_size = portsDIO_filtered_2_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_2_d_bits_source = portsDIO_filtered_2_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_2_d_bits_sink = portsDIO_filtered_2_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign in_2_d_bits_denied = portsDIO_filtered_2_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign in_2_d_bits_data = portsDIO_filtered_2_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_2_d_bits_corrupt = portsDIO_filtered_2_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_2_valid_T_1 = out_0_d_valid & _portsDIO_filtered_2_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_2_valid = _portsDIO_filtered_2_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1 & portsDIO_filtered_1_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_3 = _portsDIO_out_0_d_ready_T | _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_4 = _portsDIO_out_0_d_ready_T_3 | _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73]
assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_4; // @[Mux.scala:30:73]
assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73]
assign in_0_e_ready = portsEOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
assign out_0_e_valid = portsEOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign out_0_e_bits_sink = portsEOI_filtered_0_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsEOI_filtered_0_valid = _portsEOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
reg [7:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 8'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19]
wire [1:0] readys_hi = {portsAOI_filtered_2_0_valid, portsAOI_filtered_1_0_valid}; // @[Xbar.scala:352:24]
wire [2:0] _readys_T = {readys_hi, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24]
wire [2:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12]
wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}]
reg [2:0] readys_mask; // @[Arbiter.scala:23:23]
wire [2:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30]
wire [2:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [5:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [4:0] _readys_unready_T = readys_filter[5:1]; // @[package.scala:262:48]
wire [5:0] _readys_unready_T_1 = {readys_filter[5], readys_filter[4:0] | _readys_unready_T}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_2 = _readys_unready_T_1[5:2]; // @[package.scala:262:{43,48}]
wire [5:0] _readys_unready_T_3 = {_readys_unready_T_1[5:4], _readys_unready_T_1[3:0] | _readys_unready_T_2}; // @[package.scala:262:{43,48}]
wire [5:0] _readys_unready_T_4 = _readys_unready_T_3; // @[package.scala:262:43, :263:17]
wire [4:0] _readys_unready_T_5 = _readys_unready_T_4[5:1]; // @[package.scala:263:17]
wire [5:0] _readys_unready_T_6 = {readys_mask, 3'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [5:0] readys_unready = {1'h0, _readys_unready_T_5} | _readys_unready_T_6; // @[Arbiter.scala:25:{52,58,66}]
wire [2:0] _readys_readys_T = readys_unready[5:3]; // @[Arbiter.scala:25:58, :26:29]
wire [2:0] _readys_readys_T_1 = readys_unready[2:0]; // @[Arbiter.scala:25:58, :26:48]
wire [2:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}]
wire [2:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}]
wire [2:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [2:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [3:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48]
wire [2:0] _readys_mask_T_2 = _readys_mask_T_1[2:0]; // @[package.scala:253:{48,53}]
wire [2:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}]
wire [4:0] _readys_mask_T_4 = {_readys_mask_T_3, 2'h0}; // @[package.scala:253:{43,48}]
wire [2:0] _readys_mask_T_5 = _readys_mask_T_4[2:0]; // @[package.scala:253:{48,53}]
wire [2:0] _readys_mask_T_6 = _readys_mask_T_3 | _readys_mask_T_5; // @[package.scala:253:{43,53}]
wire [2:0] _readys_mask_T_7 = _readys_mask_T_6; // @[package.scala:253:43, :254:17]
wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_10 = _readys_T_7[2]; // @[Arbiter.scala:30:11, :68:76]
wire readys_2 = _readys_T_10; // @[Arbiter.scala:68:{27,76}]
wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_2 = readys_2 & portsAOI_filtered_2_0_valid; // @[Xbar.scala:352:24]
wire winner_2 = _winner_T_2; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_2 = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T = prefixOR_2 | winner_2; // @[Arbiter.scala:71:27, :76:48]
wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_47 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}}[4], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<2>}
regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock
wire next_valid : UInt<1>
connect next_valid, slot_valid
wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop_out, slot_uop
node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T)
connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1
wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop, next_uop_out
node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _killed_T_1 = neq(_killed_T, UInt<1>(0h0))
node killed = or(_killed_T_1, io.kill)
connect io.valid, slot_valid
connect io.out_uop, next_uop
node _io_will_be_valid_T = eq(killed, UInt<1>(0h0))
node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T)
connect io.will_be_valid, _io_will_be_valid_T_1
when io.kill :
connect slot_valid, UInt<1>(0h0)
else :
when io.in_uop.valid :
connect slot_valid, UInt<1>(0h1)
else :
when io.clear :
connect slot_valid, UInt<1>(0h0)
else :
node _slot_valid_T = eq(killed, UInt<1>(0h0))
node _slot_valid_T_1 = and(next_valid, _slot_valid_T)
connect slot_valid, _slot_valid_T_1
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T = eq(slot_valid, UInt<1>(0h0))
node _T_1 = or(_T, io.clear)
node _T_2 = or(_T_1, io.kill)
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid || io.clear || io.kill)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
else :
connect slot_uop, next_uop
connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p1_speculative_child, UInt<1>(0h0)
connect next_uop.iw_p2_speculative_child, UInt<1>(0h0)
wire rebusied_prs1 : UInt<1>
connect rebusied_prs1, UInt<1>(0h0)
wire rebusied_prs2 : UInt<1>
connect rebusied_prs2, UInt<1>(0h0)
node rebusied = or(rebusied_prs1, rebusied_prs2)
node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs1)
node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs2)
node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs3)
node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0)
node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1)
node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2)
node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3)
node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0)
node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1)
node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2)
node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3)
node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0)
node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1)
node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2)
node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3)
node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0)
node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1)
node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2)
node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3)
node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0)
node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1)
node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2)
node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3)
node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1)
node _T_7 = or(_T_6, prs1_wakeups_2)
node _T_8 = or(_T_7, prs1_wakeups_3)
when _T_8 :
connect next_uop.prs1_busy, UInt<1>(0h0)
node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_4 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1)
node _next_uop_iw_p1_speculative_child_T_5 = or(_next_uop_iw_p1_speculative_child_T_4, _next_uop_iw_p1_speculative_child_T_2)
node _next_uop_iw_p1_speculative_child_T_6 = or(_next_uop_iw_p1_speculative_child_T_5, _next_uop_iw_p1_speculative_child_T_3)
wire _next_uop_iw_p1_speculative_child_WIRE : UInt<2>
connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_6
connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE
node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_4 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1)
node _next_uop_iw_p1_bypass_hint_T_5 = or(_next_uop_iw_p1_bypass_hint_T_4, _next_uop_iw_p1_bypass_hint_T_2)
node _next_uop_iw_p1_bypass_hint_T_6 = or(_next_uop_iw_p1_bypass_hint_T_5, _next_uop_iw_p1_bypass_hint_T_3)
wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_6
connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE
node _T_9 = or(prs1_rebusys_0, prs1_rebusys_1)
node _T_10 = or(_T_9, prs1_rebusys_2)
node _T_11 = or(_T_10, prs1_rebusys_3)
node _T_12 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child)
node _T_13 = neq(_T_12, UInt<1>(0h0))
node _T_14 = or(_T_11, _T_13)
node _T_15 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0))
node _T_16 = and(_T_14, _T_15)
when _T_16 :
connect next_uop.prs1_busy, UInt<1>(0h1)
connect rebusied_prs1, UInt<1>(0h1)
node _T_17 = or(prs2_wakeups_0, prs2_wakeups_1)
node _T_18 = or(_T_17, prs2_wakeups_2)
node _T_19 = or(_T_18, prs2_wakeups_3)
when _T_19 :
connect next_uop.prs2_busy, UInt<1>(0h0)
node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_4 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1)
node _next_uop_iw_p2_speculative_child_T_5 = or(_next_uop_iw_p2_speculative_child_T_4, _next_uop_iw_p2_speculative_child_T_2)
node _next_uop_iw_p2_speculative_child_T_6 = or(_next_uop_iw_p2_speculative_child_T_5, _next_uop_iw_p2_speculative_child_T_3)
wire _next_uop_iw_p2_speculative_child_WIRE : UInt<2>
connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_6
connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE
node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_4 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1)
node _next_uop_iw_p2_bypass_hint_T_5 = or(_next_uop_iw_p2_bypass_hint_T_4, _next_uop_iw_p2_bypass_hint_T_2)
node _next_uop_iw_p2_bypass_hint_T_6 = or(_next_uop_iw_p2_bypass_hint_T_5, _next_uop_iw_p2_bypass_hint_T_3)
wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_6
connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE
node _T_20 = or(prs2_rebusys_0, prs2_rebusys_1)
node _T_21 = or(_T_20, prs2_rebusys_2)
node _T_22 = or(_T_21, prs2_rebusys_3)
node _T_23 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child)
node _T_24 = neq(_T_23, UInt<1>(0h0))
node _T_25 = or(_T_22, _T_24)
node _T_26 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0))
node _T_27 = and(_T_25, _T_26)
when _T_27 :
connect next_uop.prs2_busy, UInt<1>(0h1)
connect rebusied_prs2, UInt<1>(0h1)
node _T_28 = or(prs3_wakeups_0, prs3_wakeups_1)
node _T_29 = or(_T_28, prs3_wakeups_2)
node _T_30 = or(_T_29, prs3_wakeups_3)
when _T_30 :
connect next_uop.prs3_busy, UInt<1>(0h0)
node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_2 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_3 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_4 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1)
node _next_uop_iw_p3_bypass_hint_T_5 = or(_next_uop_iw_p3_bypass_hint_T_4, _next_uop_iw_p3_bypass_hint_T_2)
node _next_uop_iw_p3_bypass_hint_T_6 = or(_next_uop_iw_p3_bypass_hint_T_5, _next_uop_iw_p3_bypass_hint_T_3)
wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_6
connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE
node _T_31 = eq(io.pred_wakeup_port.bits, slot_uop.ppred)
node _T_32 = and(io.pred_wakeup_port.valid, _T_31)
when _T_32 :
connect next_uop.ppred_busy, UInt<1>(0h0)
node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1)
node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0))
node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4)
node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h0))
node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0))
node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7)
node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T)
node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0))
node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3)
node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0))
node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T)
node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0))
node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3)
node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0))
node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0))
node _io_request_T_1 = and(slot_valid, _io_request_T)
node _io_request_T_2 = or(iss_ready, agen_ready)
node _io_request_T_3 = or(_io_request_T_2, dgen_ready)
node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3)
connect io.request, _io_request_T_4
connect io.iss_uop, slot_uop
connect next_uop.iw_issued, UInt<1>(0h0)
connect next_uop.iw_issued_partial_agen, UInt<1>(0h0)
connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0)
node _T_33 = eq(io.squash_grant, UInt<1>(0h0))
node _T_34 = and(io.grant, _T_33)
when _T_34 :
connect next_uop.iw_issued, UInt<1>(0h1)
node _T_35 = and(slot_valid, slot_uop.iw_issued)
when _T_35 :
connect next_valid, rebusied | module IssueSlot_47( // @[issue-slot.scala:49:7]
input clock, // @[issue-slot.scala:49:7]
input reset, // @[issue-slot.scala:49:7]
output io_valid, // @[issue-slot.scala:52:14]
output io_will_be_valid, // @[issue-slot.scala:52:14]
output io_request, // @[issue-slot.scala:52:14]
input io_grant, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [11:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_amo, // @[issue-slot.scala:52:14]
output io_iss_uop_is_eret, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_iss_uop_taken, // @[issue-slot.scala:52:14]
output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14]
output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_iss_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14]
output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_iss_uop_is_unique, // @[issue-slot.scala:52:14]
output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_in_uop_valid, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:52:14]
input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:52:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [11:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_out_uop_is_fence, // @[issue-slot.scala:52:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_out_uop_is_amo, // @[issue-slot.scala:52:14]
output io_out_uop_is_eret, // @[issue-slot.scala:52:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_out_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_out_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_out_uop_taken, // @[issue-slot.scala:52:14]
output io_out_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_out_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_out_uop_is_unique, // @[issue-slot.scala:52:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_out_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14]
input io_kill, // @[issue-slot.scala:52:14]
input io_clear, // @[issue-slot.scala:52:14]
input io_squash_grant, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14]
input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14]
input [1:0] io_child_rebusys // @[issue-slot.scala:52:14]
);
wire [11:0] next_uop_out_br_mask; // @[util.scala:104:23]
wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7]
wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7]
wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7]
wire [1:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23]
wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23]
wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28]
wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91]
wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91]
wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131]
wire agen_ready = 1'h0; // @[issue-slot.scala:137:114]
wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114]
wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7]
wire [1:0] _next_uop_iw_p1_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p2_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73]
wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110]
wire [1:0] io_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-slot.scala:49:7]
wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34]
wire _io_request_T_4; // @[issue-slot.scala:140:51]
wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28]
wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28]
wire next_uop_is_rvc; // @[issue-slot.scala:59:28]
wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_0; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_1; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_2; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_0; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_1; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_2; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_4; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_5; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_6; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_7; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_8; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_9; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28]
wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28]
wire [11:0] next_uop_br_mask; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28]
wire next_uop_is_sfb; // @[issue-slot.scala:59:28]
wire next_uop_is_fence; // @[issue-slot.scala:59:28]
wire next_uop_is_fencei; // @[issue-slot.scala:59:28]
wire next_uop_is_sfence; // @[issue-slot.scala:59:28]
wire next_uop_is_amo; // @[issue-slot.scala:59:28]
wire next_uop_is_eret; // @[issue-slot.scala:59:28]
wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28]
wire next_uop_is_rocc; // @[issue-slot.scala:59:28]
wire next_uop_is_mov; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28]
wire next_uop_edge_inst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28]
wire next_uop_taken; // @[issue-slot.scala:59:28]
wire next_uop_imm_rename; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28]
wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_rob_idx; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_stq_idx; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28]
wire next_uop_prs1_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs2_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs3_busy; // @[issue-slot.scala:59:28]
wire next_uop_ppred_busy; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28]
wire next_uop_exception; // @[issue-slot.scala:59:28]
wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28]
wire next_uop_mem_signed; // @[issue-slot.scala:59:28]
wire next_uop_uses_ldq; // @[issue-slot.scala:59:28]
wire next_uop_uses_stq; // @[issue-slot.scala:59:28]
wire next_uop_is_unique; // @[issue-slot.scala:59:28]
wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28]
wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28]
wire next_uop_frs3_en; // @[issue-slot.scala:59:28]
wire next_uop_fcn_dw; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28]
wire next_uop_fp_val; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28]
wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [11:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [11:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_valid_0; // @[issue-slot.scala:49:7]
wire io_will_be_valid_0; // @[issue-slot.scala:49:7]
wire io_request_0; // @[issue-slot.scala:49:7]
reg slot_valid; // @[issue-slot.scala:55:27]
assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23]
reg slot_uop_is_rvc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21]
wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23]
reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23]
reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23]
reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23]
reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23]
reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23]
reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23]
reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23]
reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23]
reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23]
reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23]
reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23]
reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23]
reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23]
reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23]
reg slot_uop_iw_issued; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23]
reg [1:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23]
reg [1:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23]
reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [1:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23]
reg [11:0] slot_uop_br_mask; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23]
reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23]
reg slot_uop_is_sfb; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23]
reg slot_uop_is_fence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23]
reg slot_uop_is_fencei; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23]
reg slot_uop_is_sfence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23]
reg slot_uop_is_amo; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23]
reg slot_uop_is_eret; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23]
reg slot_uop_is_rocc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23]
reg slot_uop_is_mov; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23]
reg slot_uop_edge_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21]
assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23]
reg slot_uop_taken; // @[issue-slot.scala:56:21]
assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23]
reg slot_uop_imm_rename; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23]
reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23]
reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21]
assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21]
wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23]
reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23]
reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23]
reg [5:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23]
reg [3:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23]
reg [3:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23]
reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23]
reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23]
reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23]
reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23]
wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88]
wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95]
wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23]
reg slot_uop_exception; // @[issue-slot.scala:56:21]
assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21]
assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21]
wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23]
reg slot_uop_mem_signed; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23]
reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23]
reg slot_uop_uses_stq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23]
reg slot_uop_is_unique; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21]
assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23]
reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23]
reg slot_uop_frs3_en; // @[issue-slot.scala:56:21]
assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23]
reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23]
reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23]
reg slot_uop_fp_val; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23]
reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23]
wire next_valid; // @[issue-slot.scala:58:28]
assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23]
assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23]
assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23]
assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23]
assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23]
assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23]
assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23]
assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23]
assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23]
assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23]
assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23]
assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23]
assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23]
assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23]
assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23]
assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23]
assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23]
assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23]
wire [11:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25]
assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23]
assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23]
assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23]
assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23]
assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23]
assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23]
assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23]
assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23]
assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23]
assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23]
assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23]
assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23]
assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23]
assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23]
assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23]
assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23]
assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23]
assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23]
assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23]
assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23]
assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23]
assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23]
assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23]
assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23]
assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23]
assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23]
assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23]
assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23]
assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23]
assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23]
assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23]
assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23]
assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23]
assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23]
assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23]
assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23]
assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23]
assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23]
assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23]
assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23]
assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23]
assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23]
assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23]
assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23]
assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23]
assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23]
assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23]
assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23]
assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23]
assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23]
assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23]
assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23]
assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23]
assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23]
assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23]
assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23]
assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23]
assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23]
assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23]
assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23]
assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23]
assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23]
assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23]
assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23]
assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23]
assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23]
assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23]
wire [11:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}]
assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28]
wire [11:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51]
wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}]
wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61]
assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}]
assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34]
wire _slot_valid_T = ~killed; // @[util.scala:61:61]
wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}] |
Generate the Verilog code corresponding to this FIRRTL code module BreakpointUnit :
input clock : Clock
input reset : Reset
output io : { flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[0], flip pc : UInt<39>, flip ea : UInt<39>, flip mcontext : UInt<0>, flip scontext : UInt<0>, xcpt_if : UInt<1>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, debug_if : UInt<1>, debug_ld : UInt<1>, debug_st : UInt<1>, bpwatch : { valid : UInt<1>[1], rvalid : UInt<1>[1], wvalid : UInt<1>[1], ivalid : UInt<1>[1], action : UInt<3>}[0]}
connect io.xcpt_if, UInt<1>(0h0)
connect io.xcpt_ld, UInt<1>(0h0)
connect io.xcpt_st, UInt<1>(0h0)
connect io.debug_if, UInt<1>(0h0)
connect io.debug_ld, UInt<1>(0h0)
connect io.debug_st, UInt<1>(0h0) | module BreakpointUnit( // @[Breakpoint.scala:79:7]
input clock, // @[Breakpoint.scala:79:7]
input reset, // @[Breakpoint.scala:79:7]
input io_status_debug, // @[Breakpoint.scala:80:14]
input io_status_cease, // @[Breakpoint.scala:80:14]
input io_status_wfi, // @[Breakpoint.scala:80:14]
input [1:0] io_status_dprv, // @[Breakpoint.scala:80:14]
input io_status_dv, // @[Breakpoint.scala:80:14]
input [1:0] io_status_prv, // @[Breakpoint.scala:80:14]
input io_status_v, // @[Breakpoint.scala:80:14]
input io_status_sd, // @[Breakpoint.scala:80:14]
input io_status_mpv, // @[Breakpoint.scala:80:14]
input io_status_gva, // @[Breakpoint.scala:80:14]
input io_status_tsr, // @[Breakpoint.scala:80:14]
input io_status_tw, // @[Breakpoint.scala:80:14]
input io_status_tvm, // @[Breakpoint.scala:80:14]
input io_status_mxr, // @[Breakpoint.scala:80:14]
input io_status_sum, // @[Breakpoint.scala:80:14]
input io_status_mprv, // @[Breakpoint.scala:80:14]
input [1:0] io_status_fs, // @[Breakpoint.scala:80:14]
input [1:0] io_status_mpp, // @[Breakpoint.scala:80:14]
input io_status_spp, // @[Breakpoint.scala:80:14]
input io_status_mpie, // @[Breakpoint.scala:80:14]
input io_status_spie, // @[Breakpoint.scala:80:14]
input io_status_mie, // @[Breakpoint.scala:80:14]
input io_status_sie, // @[Breakpoint.scala:80:14]
input [38:0] io_pc // @[Breakpoint.scala:80:14]
);
wire io_status_debug_0 = io_status_debug; // @[Breakpoint.scala:79:7]
wire io_status_cease_0 = io_status_cease; // @[Breakpoint.scala:79:7]
wire io_status_wfi_0 = io_status_wfi; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_dprv_0 = io_status_dprv; // @[Breakpoint.scala:79:7]
wire io_status_dv_0 = io_status_dv; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_prv_0 = io_status_prv; // @[Breakpoint.scala:79:7]
wire io_status_v_0 = io_status_v; // @[Breakpoint.scala:79:7]
wire io_status_sd_0 = io_status_sd; // @[Breakpoint.scala:79:7]
wire io_status_mpv_0 = io_status_mpv; // @[Breakpoint.scala:79:7]
wire io_status_gva_0 = io_status_gva; // @[Breakpoint.scala:79:7]
wire io_status_tsr_0 = io_status_tsr; // @[Breakpoint.scala:79:7]
wire io_status_tw_0 = io_status_tw; // @[Breakpoint.scala:79:7]
wire io_status_tvm_0 = io_status_tvm; // @[Breakpoint.scala:79:7]
wire io_status_mxr_0 = io_status_mxr; // @[Breakpoint.scala:79:7]
wire io_status_sum_0 = io_status_sum; // @[Breakpoint.scala:79:7]
wire io_status_mprv_0 = io_status_mprv; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_fs_0 = io_status_fs; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_mpp_0 = io_status_mpp; // @[Breakpoint.scala:79:7]
wire io_status_spp_0 = io_status_spp; // @[Breakpoint.scala:79:7]
wire io_status_mpie_0 = io_status_mpie; // @[Breakpoint.scala:79:7]
wire io_status_spie_0 = io_status_spie; // @[Breakpoint.scala:79:7]
wire io_status_mie_0 = io_status_mie; // @[Breakpoint.scala:79:7]
wire io_status_sie_0 = io_status_sie; // @[Breakpoint.scala:79:7]
wire [38:0] io_pc_0 = io_pc; // @[Breakpoint.scala:79:7]
wire [38:0] io_ea = 39'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_sxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_uxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_xs = 2'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_vs = 2'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [7:0] io_status_zero1 = 8'h0; // @[Breakpoint.scala:79:7, :80:14]
wire io_status_mbe = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_sbe = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_sd_rv32 = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_ube = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_upie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_hie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_uie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_if = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_ld = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_st = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_if = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_ld = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_st = 1'h0; // @[Breakpoint.scala:79:7]
wire [22:0] io_status_zero2 = 23'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [31:0] io_status_isa = 32'h14112D; // @[Breakpoint.scala:79:7, :80:14]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_11 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0)
node _source_ok_T = shr(io.in.a.bits.source, 5)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h1f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits = bits(_uncommonBits_T, 4, 0)
node _T_4 = shr(io.in.a.bits.source, 5)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<5>(0h1f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0)
node _T_24 = shr(io.in.a.bits.source, 5)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<5>(0h1f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<14>(0h2000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<13>(0h1000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_44 = cvt(_T_43)
node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000)))
node _T_46 = asSInt(_T_45)
node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<18>(0h2f000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_54 = cvt(_T_53)
node _T_55 = and(_T_54, asSInt(UInt<17>(0h10000)))
node _T_56 = asSInt(_T_55)
node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0)))
node _T_58 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_64 = cvt(_T_63)
node _T_65 = and(_T_64, asSInt(UInt<27>(0h4000000)))
node _T_66 = asSInt(_T_65)
node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0)))
node _T_68 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_69 = cvt(_T_68)
node _T_70 = and(_T_69, asSInt(UInt<13>(0h1000)))
node _T_71 = asSInt(_T_70)
node _T_72 = eq(_T_71, asSInt(UInt<1>(0h0)))
node _T_73 = or(_T_37, _T_42)
node _T_74 = or(_T_73, _T_47)
node _T_75 = or(_T_74, _T_52)
node _T_76 = or(_T_75, _T_57)
node _T_77 = or(_T_76, _T_62)
node _T_78 = or(_T_77, _T_67)
node _T_79 = or(_T_78, _T_72)
node _T_80 = and(_T_32, _T_79)
node _T_81 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_82 = or(UInt<1>(0h0), _T_81)
node _T_83 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_84 = cvt(_T_83)
node _T_85 = and(_T_84, asSInt(UInt<17>(0h10000)))
node _T_86 = asSInt(_T_85)
node _T_87 = eq(_T_86, asSInt(UInt<1>(0h0)))
node _T_88 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_89 = cvt(_T_88)
node _T_90 = and(_T_89, asSInt(UInt<29>(0h10000000)))
node _T_91 = asSInt(_T_90)
node _T_92 = eq(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = or(_T_87, _T_92)
node _T_94 = and(_T_82, _T_93)
node _T_95 = or(UInt<1>(0h0), _T_80)
node _T_96 = or(_T_95, _T_94)
node _T_97 = and(_T_31, _T_96)
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_97, UInt<1>(0h1), "") : assert_2
node _T_101 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_102 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_103 = and(_T_101, _T_102)
node _T_104 = or(UInt<1>(0h0), _T_103)
node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_106 = cvt(_T_105)
node _T_107 = and(_T_106, asSInt(UInt<14>(0h2000)))
node _T_108 = asSInt(_T_107)
node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0)))
node _T_110 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_116 = cvt(_T_115)
node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000)))
node _T_118 = asSInt(_T_117)
node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0)))
node _T_120 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_121 = cvt(_T_120)
node _T_122 = and(_T_121, asSInt(UInt<18>(0h2f000)))
node _T_123 = asSInt(_T_122)
node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0)))
node _T_125 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_126 = cvt(_T_125)
node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000)))
node _T_128 = asSInt(_T_127)
node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0)))
node _T_130 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_131 = cvt(_T_130)
node _T_132 = and(_T_131, asSInt(UInt<13>(0h1000)))
node _T_133 = asSInt(_T_132)
node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0)))
node _T_135 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_136 = cvt(_T_135)
node _T_137 = and(_T_136, asSInt(UInt<17>(0h10000)))
node _T_138 = asSInt(_T_137)
node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0)))
node _T_140 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_141 = cvt(_T_140)
node _T_142 = and(_T_141, asSInt(UInt<27>(0h4000000)))
node _T_143 = asSInt(_T_142)
node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0)))
node _T_145 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_146 = cvt(_T_145)
node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000)))
node _T_148 = asSInt(_T_147)
node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0)))
node _T_150 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_151 = cvt(_T_150)
node _T_152 = and(_T_151, asSInt(UInt<29>(0h10000000)))
node _T_153 = asSInt(_T_152)
node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0)))
node _T_155 = or(_T_109, _T_114)
node _T_156 = or(_T_155, _T_119)
node _T_157 = or(_T_156, _T_124)
node _T_158 = or(_T_157, _T_129)
node _T_159 = or(_T_158, _T_134)
node _T_160 = or(_T_159, _T_139)
node _T_161 = or(_T_160, _T_144)
node _T_162 = or(_T_161, _T_149)
node _T_163 = or(_T_162, _T_154)
node _T_164 = and(_T_104, _T_163)
node _T_165 = or(UInt<1>(0h0), _T_164)
node _T_166 = and(UInt<1>(0h0), _T_165)
node _T_167 = asUInt(reset)
node _T_168 = eq(_T_167, UInt<1>(0h0))
when _T_168 :
node _T_169 = eq(_T_166, UInt<1>(0h0))
when _T_169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_166, UInt<1>(0h1), "") : assert_3
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_173 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_173, UInt<1>(0h1), "") : assert_5
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(is_aligned, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_180 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_181 = asUInt(reset)
node _T_182 = eq(_T_181, UInt<1>(0h0))
when _T_182 :
node _T_183 = eq(_T_180, UInt<1>(0h0))
when _T_183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_180, UInt<1>(0h1), "") : assert_7
node _T_184 = not(io.in.a.bits.mask)
node _T_185 = eq(_T_184, UInt<1>(0h0))
node _T_186 = asUInt(reset)
node _T_187 = eq(_T_186, UInt<1>(0h0))
when _T_187 :
node _T_188 = eq(_T_185, UInt<1>(0h0))
when _T_188 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_185, UInt<1>(0h1), "") : assert_8
node _T_189 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_190 = asUInt(reset)
node _T_191 = eq(_T_190, UInt<1>(0h0))
when _T_191 :
node _T_192 = eq(_T_189, UInt<1>(0h0))
when _T_192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_189, UInt<1>(0h1), "") : assert_9
node _T_193 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_193 :
node _T_194 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_195 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_196 = and(_T_194, _T_195)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0)
node _T_197 = shr(io.in.a.bits.source, 5)
node _T_198 = eq(_T_197, UInt<1>(0h0))
node _T_199 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_200 = and(_T_198, _T_199)
node _T_201 = leq(uncommonBits_2, UInt<5>(0h1f))
node _T_202 = and(_T_200, _T_201)
node _T_203 = and(_T_196, _T_202)
node _T_204 = or(UInt<1>(0h0), _T_203)
node _T_205 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_206 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_207 = cvt(_T_206)
node _T_208 = and(_T_207, asSInt(UInt<14>(0h2000)))
node _T_209 = asSInt(_T_208)
node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0)))
node _T_211 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_217 = cvt(_T_216)
node _T_218 = and(_T_217, asSInt(UInt<17>(0h10000)))
node _T_219 = asSInt(_T_218)
node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0)))
node _T_221 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_222 = cvt(_T_221)
node _T_223 = and(_T_222, asSInt(UInt<18>(0h2f000)))
node _T_224 = asSInt(_T_223)
node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0)))
node _T_226 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_227 = cvt(_T_226)
node _T_228 = and(_T_227, asSInt(UInt<17>(0h10000)))
node _T_229 = asSInt(_T_228)
node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0)))
node _T_231 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_232 = cvt(_T_231)
node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000)))
node _T_234 = asSInt(_T_233)
node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0)))
node _T_236 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_237 = cvt(_T_236)
node _T_238 = and(_T_237, asSInt(UInt<27>(0h4000000)))
node _T_239 = asSInt(_T_238)
node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0)))
node _T_241 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<13>(0h1000)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = or(_T_210, _T_215)
node _T_247 = or(_T_246, _T_220)
node _T_248 = or(_T_247, _T_225)
node _T_249 = or(_T_248, _T_230)
node _T_250 = or(_T_249, _T_235)
node _T_251 = or(_T_250, _T_240)
node _T_252 = or(_T_251, _T_245)
node _T_253 = and(_T_205, _T_252)
node _T_254 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_255 = or(UInt<1>(0h0), _T_254)
node _T_256 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_257 = cvt(_T_256)
node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000)))
node _T_259 = asSInt(_T_258)
node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0)))
node _T_261 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_262 = cvt(_T_261)
node _T_263 = and(_T_262, asSInt(UInt<29>(0h10000000)))
node _T_264 = asSInt(_T_263)
node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0)))
node _T_266 = or(_T_260, _T_265)
node _T_267 = and(_T_255, _T_266)
node _T_268 = or(UInt<1>(0h0), _T_253)
node _T_269 = or(_T_268, _T_267)
node _T_270 = and(_T_204, _T_269)
node _T_271 = asUInt(reset)
node _T_272 = eq(_T_271, UInt<1>(0h0))
when _T_272 :
node _T_273 = eq(_T_270, UInt<1>(0h0))
when _T_273 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_270, UInt<1>(0h1), "") : assert_10
node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_276 = and(_T_274, _T_275)
node _T_277 = or(UInt<1>(0h0), _T_276)
node _T_278 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_279 = cvt(_T_278)
node _T_280 = and(_T_279, asSInt(UInt<14>(0h2000)))
node _T_281 = asSInt(_T_280)
node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0)))
node _T_283 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_284 = cvt(_T_283)
node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000)))
node _T_286 = asSInt(_T_285)
node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0)))
node _T_288 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<18>(0h2f000)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_299 = cvt(_T_298)
node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000)))
node _T_301 = asSInt(_T_300)
node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0)))
node _T_303 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_304 = cvt(_T_303)
node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000)))
node _T_306 = asSInt(_T_305)
node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0)))
node _T_308 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_309 = cvt(_T_308)
node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000)))
node _T_311 = asSInt(_T_310)
node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0)))
node _T_313 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_314 = cvt(_T_313)
node _T_315 = and(_T_314, asSInt(UInt<27>(0h4000000)))
node _T_316 = asSInt(_T_315)
node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0)))
node _T_318 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_319 = cvt(_T_318)
node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000)))
node _T_321 = asSInt(_T_320)
node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0)))
node _T_323 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_324 = cvt(_T_323)
node _T_325 = and(_T_324, asSInt(UInt<29>(0h10000000)))
node _T_326 = asSInt(_T_325)
node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0)))
node _T_328 = or(_T_282, _T_287)
node _T_329 = or(_T_328, _T_292)
node _T_330 = or(_T_329, _T_297)
node _T_331 = or(_T_330, _T_302)
node _T_332 = or(_T_331, _T_307)
node _T_333 = or(_T_332, _T_312)
node _T_334 = or(_T_333, _T_317)
node _T_335 = or(_T_334, _T_322)
node _T_336 = or(_T_335, _T_327)
node _T_337 = and(_T_277, _T_336)
node _T_338 = or(UInt<1>(0h0), _T_337)
node _T_339 = and(UInt<1>(0h0), _T_338)
node _T_340 = asUInt(reset)
node _T_341 = eq(_T_340, UInt<1>(0h0))
when _T_341 :
node _T_342 = eq(_T_339, UInt<1>(0h0))
when _T_342 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_339, UInt<1>(0h1), "") : assert_11
node _T_343 = asUInt(reset)
node _T_344 = eq(_T_343, UInt<1>(0h0))
when _T_344 :
node _T_345 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_346 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_347 = asUInt(reset)
node _T_348 = eq(_T_347, UInt<1>(0h0))
when _T_348 :
node _T_349 = eq(_T_346, UInt<1>(0h0))
when _T_349 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_346, UInt<1>(0h1), "") : assert_13
node _T_350 = asUInt(reset)
node _T_351 = eq(_T_350, UInt<1>(0h0))
when _T_351 :
node _T_352 = eq(is_aligned, UInt<1>(0h0))
when _T_352 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_353 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_354 = asUInt(reset)
node _T_355 = eq(_T_354, UInt<1>(0h0))
when _T_355 :
node _T_356 = eq(_T_353, UInt<1>(0h0))
when _T_356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_353, UInt<1>(0h1), "") : assert_15
node _T_357 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_358 = asUInt(reset)
node _T_359 = eq(_T_358, UInt<1>(0h0))
when _T_359 :
node _T_360 = eq(_T_357, UInt<1>(0h0))
when _T_360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_357, UInt<1>(0h1), "") : assert_16
node _T_361 = not(io.in.a.bits.mask)
node _T_362 = eq(_T_361, UInt<1>(0h0))
node _T_363 = asUInt(reset)
node _T_364 = eq(_T_363, UInt<1>(0h0))
when _T_364 :
node _T_365 = eq(_T_362, UInt<1>(0h0))
when _T_365 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_362, UInt<1>(0h1), "") : assert_17
node _T_366 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_366, UInt<1>(0h1), "") : assert_18
node _T_370 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_370 :
node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_373 = and(_T_371, _T_372)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0)
node _T_374 = shr(io.in.a.bits.source, 5)
node _T_375 = eq(_T_374, UInt<1>(0h0))
node _T_376 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_377 = and(_T_375, _T_376)
node _T_378 = leq(uncommonBits_3, UInt<5>(0h1f))
node _T_379 = and(_T_377, _T_378)
node _T_380 = and(_T_373, _T_379)
node _T_381 = or(UInt<1>(0h0), _T_380)
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(_T_381, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_381, UInt<1>(0h1), "") : assert_19
node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_386 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_387 = and(_T_385, _T_386)
node _T_388 = or(UInt<1>(0h0), _T_387)
node _T_389 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = and(_T_388, _T_393)
node _T_395 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_396 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_397 = and(_T_395, _T_396)
node _T_398 = or(UInt<1>(0h0), _T_397)
node _T_399 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<14>(0h2000)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<18>(0h2f000)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<17>(0h10000)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_420 = cvt(_T_419)
node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000)))
node _T_422 = asSInt(_T_421)
node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0)))
node _T_424 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_425 = cvt(_T_424)
node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000)))
node _T_427 = asSInt(_T_426)
node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0)))
node _T_429 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_430 = cvt(_T_429)
node _T_431 = and(_T_430, asSInt(UInt<27>(0h4000000)))
node _T_432 = asSInt(_T_431)
node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0)))
node _T_434 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_435 = cvt(_T_434)
node _T_436 = and(_T_435, asSInt(UInt<13>(0h1000)))
node _T_437 = asSInt(_T_436)
node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0)))
node _T_439 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_440 = cvt(_T_439)
node _T_441 = and(_T_440, asSInt(UInt<29>(0h10000000)))
node _T_442 = asSInt(_T_441)
node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0)))
node _T_444 = or(_T_403, _T_408)
node _T_445 = or(_T_444, _T_413)
node _T_446 = or(_T_445, _T_418)
node _T_447 = or(_T_446, _T_423)
node _T_448 = or(_T_447, _T_428)
node _T_449 = or(_T_448, _T_433)
node _T_450 = or(_T_449, _T_438)
node _T_451 = or(_T_450, _T_443)
node _T_452 = and(_T_398, _T_451)
node _T_453 = or(UInt<1>(0h0), _T_394)
node _T_454 = or(_T_453, _T_452)
node _T_455 = asUInt(reset)
node _T_456 = eq(_T_455, UInt<1>(0h0))
when _T_456 :
node _T_457 = eq(_T_454, UInt<1>(0h0))
when _T_457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_454, UInt<1>(0h1), "") : assert_20
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(is_aligned, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_464 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_464, UInt<1>(0h1), "") : assert_23
node _T_468 = eq(io.in.a.bits.mask, mask)
node _T_469 = asUInt(reset)
node _T_470 = eq(_T_469, UInt<1>(0h0))
when _T_470 :
node _T_471 = eq(_T_468, UInt<1>(0h0))
when _T_471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_468, UInt<1>(0h1), "") : assert_24
node _T_472 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_473 = asUInt(reset)
node _T_474 = eq(_T_473, UInt<1>(0h0))
when _T_474 :
node _T_475 = eq(_T_472, UInt<1>(0h0))
when _T_475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_472, UInt<1>(0h1), "") : assert_25
node _T_476 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_476 :
node _T_477 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_478 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_479 = and(_T_477, _T_478)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0)
node _T_480 = shr(io.in.a.bits.source, 5)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_483 = and(_T_481, _T_482)
node _T_484 = leq(uncommonBits_4, UInt<5>(0h1f))
node _T_485 = and(_T_483, _T_484)
node _T_486 = and(_T_479, _T_485)
node _T_487 = or(UInt<1>(0h0), _T_486)
node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_489 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_490 = and(_T_488, _T_489)
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_493 = cvt(_T_492)
node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000)))
node _T_495 = asSInt(_T_494)
node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0)))
node _T_497 = and(_T_491, _T_496)
node _T_498 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_499 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_500 = and(_T_498, _T_499)
node _T_501 = or(UInt<1>(0h0), _T_500)
node _T_502 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_503 = cvt(_T_502)
node _T_504 = and(_T_503, asSInt(UInt<14>(0h2000)))
node _T_505 = asSInt(_T_504)
node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0)))
node _T_507 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_508 = cvt(_T_507)
node _T_509 = and(_T_508, asSInt(UInt<18>(0h2f000)))
node _T_510 = asSInt(_T_509)
node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0)))
node _T_512 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_513 = cvt(_T_512)
node _T_514 = and(_T_513, asSInt(UInt<17>(0h10000)))
node _T_515 = asSInt(_T_514)
node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0)))
node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_518 = cvt(_T_517)
node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000)))
node _T_520 = asSInt(_T_519)
node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0)))
node _T_522 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_523 = cvt(_T_522)
node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000)))
node _T_525 = asSInt(_T_524)
node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0)))
node _T_527 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_528 = cvt(_T_527)
node _T_529 = and(_T_528, asSInt(UInt<27>(0h4000000)))
node _T_530 = asSInt(_T_529)
node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0)))
node _T_532 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_533 = cvt(_T_532)
node _T_534 = and(_T_533, asSInt(UInt<13>(0h1000)))
node _T_535 = asSInt(_T_534)
node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0)))
node _T_537 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_538 = cvt(_T_537)
node _T_539 = and(_T_538, asSInt(UInt<29>(0h10000000)))
node _T_540 = asSInt(_T_539)
node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0)))
node _T_542 = or(_T_506, _T_511)
node _T_543 = or(_T_542, _T_516)
node _T_544 = or(_T_543, _T_521)
node _T_545 = or(_T_544, _T_526)
node _T_546 = or(_T_545, _T_531)
node _T_547 = or(_T_546, _T_536)
node _T_548 = or(_T_547, _T_541)
node _T_549 = and(_T_501, _T_548)
node _T_550 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_551 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_552 = cvt(_T_551)
node _T_553 = and(_T_552, asSInt(UInt<17>(0h10000)))
node _T_554 = asSInt(_T_553)
node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0)))
node _T_556 = and(_T_550, _T_555)
node _T_557 = or(UInt<1>(0h0), _T_497)
node _T_558 = or(_T_557, _T_549)
node _T_559 = or(_T_558, _T_556)
node _T_560 = and(_T_487, _T_559)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_560, UInt<1>(0h1), "") : assert_26
node _T_564 = asUInt(reset)
node _T_565 = eq(_T_564, UInt<1>(0h0))
when _T_565 :
node _T_566 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_567 = asUInt(reset)
node _T_568 = eq(_T_567, UInt<1>(0h0))
when _T_568 :
node _T_569 = eq(is_aligned, UInt<1>(0h0))
when _T_569 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_570 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_571 = asUInt(reset)
node _T_572 = eq(_T_571, UInt<1>(0h0))
when _T_572 :
node _T_573 = eq(_T_570, UInt<1>(0h0))
when _T_573 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_570, UInt<1>(0h1), "") : assert_29
node _T_574 = eq(io.in.a.bits.mask, mask)
node _T_575 = asUInt(reset)
node _T_576 = eq(_T_575, UInt<1>(0h0))
when _T_576 :
node _T_577 = eq(_T_574, UInt<1>(0h0))
when _T_577 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_574, UInt<1>(0h1), "") : assert_30
node _T_578 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_578 :
node _T_579 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_580 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_581 = and(_T_579, _T_580)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0)
node _T_582 = shr(io.in.a.bits.source, 5)
node _T_583 = eq(_T_582, UInt<1>(0h0))
node _T_584 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_585 = and(_T_583, _T_584)
node _T_586 = leq(uncommonBits_5, UInt<5>(0h1f))
node _T_587 = and(_T_585, _T_586)
node _T_588 = and(_T_581, _T_587)
node _T_589 = or(UInt<1>(0h0), _T_588)
node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_592 = and(_T_590, _T_591)
node _T_593 = or(UInt<1>(0h0), _T_592)
node _T_594 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_595 = cvt(_T_594)
node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000)))
node _T_597 = asSInt(_T_596)
node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0)))
node _T_599 = and(_T_593, _T_598)
node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_601 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_602 = and(_T_600, _T_601)
node _T_603 = or(UInt<1>(0h0), _T_602)
node _T_604 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_605 = cvt(_T_604)
node _T_606 = and(_T_605, asSInt(UInt<14>(0h2000)))
node _T_607 = asSInt(_T_606)
node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0)))
node _T_609 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_610 = cvt(_T_609)
node _T_611 = and(_T_610, asSInt(UInt<18>(0h2f000)))
node _T_612 = asSInt(_T_611)
node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0)))
node _T_614 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_615 = cvt(_T_614)
node _T_616 = and(_T_615, asSInt(UInt<17>(0h10000)))
node _T_617 = asSInt(_T_616)
node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0)))
node _T_619 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_620 = cvt(_T_619)
node _T_621 = and(_T_620, asSInt(UInt<13>(0h1000)))
node _T_622 = asSInt(_T_621)
node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0)))
node _T_624 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_625 = cvt(_T_624)
node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000)))
node _T_627 = asSInt(_T_626)
node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0)))
node _T_629 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_630 = cvt(_T_629)
node _T_631 = and(_T_630, asSInt(UInt<27>(0h4000000)))
node _T_632 = asSInt(_T_631)
node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0)))
node _T_634 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_635 = cvt(_T_634)
node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000)))
node _T_637 = asSInt(_T_636)
node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0)))
node _T_639 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_640 = cvt(_T_639)
node _T_641 = and(_T_640, asSInt(UInt<29>(0h10000000)))
node _T_642 = asSInt(_T_641)
node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0)))
node _T_644 = or(_T_608, _T_613)
node _T_645 = or(_T_644, _T_618)
node _T_646 = or(_T_645, _T_623)
node _T_647 = or(_T_646, _T_628)
node _T_648 = or(_T_647, _T_633)
node _T_649 = or(_T_648, _T_638)
node _T_650 = or(_T_649, _T_643)
node _T_651 = and(_T_603, _T_650)
node _T_652 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_653 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_654 = cvt(_T_653)
node _T_655 = and(_T_654, asSInt(UInt<17>(0h10000)))
node _T_656 = asSInt(_T_655)
node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0)))
node _T_658 = and(_T_652, _T_657)
node _T_659 = or(UInt<1>(0h0), _T_599)
node _T_660 = or(_T_659, _T_651)
node _T_661 = or(_T_660, _T_658)
node _T_662 = and(_T_589, _T_661)
node _T_663 = asUInt(reset)
node _T_664 = eq(_T_663, UInt<1>(0h0))
when _T_664 :
node _T_665 = eq(_T_662, UInt<1>(0h0))
when _T_665 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_662, UInt<1>(0h1), "") : assert_31
node _T_666 = asUInt(reset)
node _T_667 = eq(_T_666, UInt<1>(0h0))
when _T_667 :
node _T_668 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(is_aligned, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_672 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_673 = asUInt(reset)
node _T_674 = eq(_T_673, UInt<1>(0h0))
when _T_674 :
node _T_675 = eq(_T_672, UInt<1>(0h0))
when _T_675 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_672, UInt<1>(0h1), "") : assert_34
node _T_676 = not(mask)
node _T_677 = and(io.in.a.bits.mask, _T_676)
node _T_678 = eq(_T_677, UInt<1>(0h0))
node _T_679 = asUInt(reset)
node _T_680 = eq(_T_679, UInt<1>(0h0))
when _T_680 :
node _T_681 = eq(_T_678, UInt<1>(0h0))
when _T_681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_678, UInt<1>(0h1), "") : assert_35
node _T_682 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_682 :
node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_684 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_685 = and(_T_683, _T_684)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0)
node _T_686 = shr(io.in.a.bits.source, 5)
node _T_687 = eq(_T_686, UInt<1>(0h0))
node _T_688 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_689 = and(_T_687, _T_688)
node _T_690 = leq(uncommonBits_6, UInt<5>(0h1f))
node _T_691 = and(_T_689, _T_690)
node _T_692 = and(_T_685, _T_691)
node _T_693 = or(UInt<1>(0h0), _T_692)
node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_695 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_696 = and(_T_694, _T_695)
node _T_697 = or(UInt<1>(0h0), _T_696)
node _T_698 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_699 = cvt(_T_698)
node _T_700 = and(_T_699, asSInt(UInt<14>(0h2000)))
node _T_701 = asSInt(_T_700)
node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0)))
node _T_703 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_704 = cvt(_T_703)
node _T_705 = and(_T_704, asSInt(UInt<13>(0h1000)))
node _T_706 = asSInt(_T_705)
node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0)))
node _T_708 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_709 = cvt(_T_708)
node _T_710 = and(_T_709, asSInt(UInt<18>(0h2f000)))
node _T_711 = asSInt(_T_710)
node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0)))
node _T_713 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_714 = cvt(_T_713)
node _T_715 = and(_T_714, asSInt(UInt<17>(0h10000)))
node _T_716 = asSInt(_T_715)
node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0)))
node _T_718 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_719 = cvt(_T_718)
node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000)))
node _T_721 = asSInt(_T_720)
node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0)))
node _T_723 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_724 = cvt(_T_723)
node _T_725 = and(_T_724, asSInt(UInt<17>(0h10000)))
node _T_726 = asSInt(_T_725)
node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0)))
node _T_728 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_729 = cvt(_T_728)
node _T_730 = and(_T_729, asSInt(UInt<27>(0h4000000)))
node _T_731 = asSInt(_T_730)
node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0)))
node _T_733 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_734 = cvt(_T_733)
node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000)))
node _T_736 = asSInt(_T_735)
node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0)))
node _T_738 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_739 = cvt(_T_738)
node _T_740 = and(_T_739, asSInt(UInt<29>(0h10000000)))
node _T_741 = asSInt(_T_740)
node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0)))
node _T_743 = or(_T_702, _T_707)
node _T_744 = or(_T_743, _T_712)
node _T_745 = or(_T_744, _T_717)
node _T_746 = or(_T_745, _T_722)
node _T_747 = or(_T_746, _T_727)
node _T_748 = or(_T_747, _T_732)
node _T_749 = or(_T_748, _T_737)
node _T_750 = or(_T_749, _T_742)
node _T_751 = and(_T_697, _T_750)
node _T_752 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_753 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_754 = cvt(_T_753)
node _T_755 = and(_T_754, asSInt(UInt<17>(0h10000)))
node _T_756 = asSInt(_T_755)
node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0)))
node _T_758 = and(_T_752, _T_757)
node _T_759 = or(UInt<1>(0h0), _T_751)
node _T_760 = or(_T_759, _T_758)
node _T_761 = and(_T_693, _T_760)
node _T_762 = asUInt(reset)
node _T_763 = eq(_T_762, UInt<1>(0h0))
when _T_763 :
node _T_764 = eq(_T_761, UInt<1>(0h0))
when _T_764 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_761, UInt<1>(0h1), "") : assert_36
node _T_765 = asUInt(reset)
node _T_766 = eq(_T_765, UInt<1>(0h0))
when _T_766 :
node _T_767 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_767 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(is_aligned, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_771 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_772 = asUInt(reset)
node _T_773 = eq(_T_772, UInt<1>(0h0))
when _T_773 :
node _T_774 = eq(_T_771, UInt<1>(0h0))
when _T_774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_771, UInt<1>(0h1), "") : assert_39
node _T_775 = eq(io.in.a.bits.mask, mask)
node _T_776 = asUInt(reset)
node _T_777 = eq(_T_776, UInt<1>(0h0))
when _T_777 :
node _T_778 = eq(_T_775, UInt<1>(0h0))
when _T_778 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_775, UInt<1>(0h1), "") : assert_40
node _T_779 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_779 :
node _T_780 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_781 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_782 = and(_T_780, _T_781)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0)
node _T_783 = shr(io.in.a.bits.source, 5)
node _T_784 = eq(_T_783, UInt<1>(0h0))
node _T_785 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_786 = and(_T_784, _T_785)
node _T_787 = leq(uncommonBits_7, UInt<5>(0h1f))
node _T_788 = and(_T_786, _T_787)
node _T_789 = and(_T_782, _T_788)
node _T_790 = or(UInt<1>(0h0), _T_789)
node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_792 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_793 = and(_T_791, _T_792)
node _T_794 = or(UInt<1>(0h0), _T_793)
node _T_795 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_796 = cvt(_T_795)
node _T_797 = and(_T_796, asSInt(UInt<14>(0h2000)))
node _T_798 = asSInt(_T_797)
node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0)))
node _T_800 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_801 = cvt(_T_800)
node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000)))
node _T_803 = asSInt(_T_802)
node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0)))
node _T_805 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_806 = cvt(_T_805)
node _T_807 = and(_T_806, asSInt(UInt<18>(0h2f000)))
node _T_808 = asSInt(_T_807)
node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0)))
node _T_810 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_811 = cvt(_T_810)
node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000)))
node _T_813 = asSInt(_T_812)
node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0)))
node _T_815 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_816 = cvt(_T_815)
node _T_817 = and(_T_816, asSInt(UInt<13>(0h1000)))
node _T_818 = asSInt(_T_817)
node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0)))
node _T_820 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_821 = cvt(_T_820)
node _T_822 = and(_T_821, asSInt(UInt<17>(0h10000)))
node _T_823 = asSInt(_T_822)
node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0)))
node _T_825 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_826 = cvt(_T_825)
node _T_827 = and(_T_826, asSInt(UInt<27>(0h4000000)))
node _T_828 = asSInt(_T_827)
node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0)))
node _T_830 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_831 = cvt(_T_830)
node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000)))
node _T_833 = asSInt(_T_832)
node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0)))
node _T_835 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_836 = cvt(_T_835)
node _T_837 = and(_T_836, asSInt(UInt<29>(0h10000000)))
node _T_838 = asSInt(_T_837)
node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0)))
node _T_840 = or(_T_799, _T_804)
node _T_841 = or(_T_840, _T_809)
node _T_842 = or(_T_841, _T_814)
node _T_843 = or(_T_842, _T_819)
node _T_844 = or(_T_843, _T_824)
node _T_845 = or(_T_844, _T_829)
node _T_846 = or(_T_845, _T_834)
node _T_847 = or(_T_846, _T_839)
node _T_848 = and(_T_794, _T_847)
node _T_849 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_850 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_851 = cvt(_T_850)
node _T_852 = and(_T_851, asSInt(UInt<17>(0h10000)))
node _T_853 = asSInt(_T_852)
node _T_854 = eq(_T_853, asSInt(UInt<1>(0h0)))
node _T_855 = and(_T_849, _T_854)
node _T_856 = or(UInt<1>(0h0), _T_848)
node _T_857 = or(_T_856, _T_855)
node _T_858 = and(_T_790, _T_857)
node _T_859 = asUInt(reset)
node _T_860 = eq(_T_859, UInt<1>(0h0))
when _T_860 :
node _T_861 = eq(_T_858, UInt<1>(0h0))
when _T_861 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_858, UInt<1>(0h1), "") : assert_41
node _T_862 = asUInt(reset)
node _T_863 = eq(_T_862, UInt<1>(0h0))
when _T_863 :
node _T_864 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_864 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_865 = asUInt(reset)
node _T_866 = eq(_T_865, UInt<1>(0h0))
when _T_866 :
node _T_867 = eq(is_aligned, UInt<1>(0h0))
when _T_867 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_868 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_869 = asUInt(reset)
node _T_870 = eq(_T_869, UInt<1>(0h0))
when _T_870 :
node _T_871 = eq(_T_868, UInt<1>(0h0))
when _T_871 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_868, UInt<1>(0h1), "") : assert_44
node _T_872 = eq(io.in.a.bits.mask, mask)
node _T_873 = asUInt(reset)
node _T_874 = eq(_T_873, UInt<1>(0h0))
when _T_874 :
node _T_875 = eq(_T_872, UInt<1>(0h0))
when _T_875 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_872, UInt<1>(0h1), "") : assert_45
node _T_876 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_876 :
node _T_877 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_878 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_879 = and(_T_877, _T_878)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0)
node _T_880 = shr(io.in.a.bits.source, 5)
node _T_881 = eq(_T_880, UInt<1>(0h0))
node _T_882 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_883 = and(_T_881, _T_882)
node _T_884 = leq(uncommonBits_8, UInt<5>(0h1f))
node _T_885 = and(_T_883, _T_884)
node _T_886 = and(_T_879, _T_885)
node _T_887 = or(UInt<1>(0h0), _T_886)
node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_889 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_890 = and(_T_888, _T_889)
node _T_891 = or(UInt<1>(0h0), _T_890)
node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_893 = cvt(_T_892)
node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000)))
node _T_895 = asSInt(_T_894)
node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0)))
node _T_897 = and(_T_891, _T_896)
node _T_898 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_899 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_900 = cvt(_T_899)
node _T_901 = and(_T_900, asSInt(UInt<14>(0h2000)))
node _T_902 = asSInt(_T_901)
node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0)))
node _T_904 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_905 = cvt(_T_904)
node _T_906 = and(_T_905, asSInt(UInt<17>(0h10000)))
node _T_907 = asSInt(_T_906)
node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0)))
node _T_909 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_910 = cvt(_T_909)
node _T_911 = and(_T_910, asSInt(UInt<18>(0h2f000)))
node _T_912 = asSInt(_T_911)
node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0)))
node _T_914 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_915 = cvt(_T_914)
node _T_916 = and(_T_915, asSInt(UInt<17>(0h10000)))
node _T_917 = asSInt(_T_916)
node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0)))
node _T_919 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_920 = cvt(_T_919)
node _T_921 = and(_T_920, asSInt(UInt<13>(0h1000)))
node _T_922 = asSInt(_T_921)
node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0)))
node _T_924 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_925 = cvt(_T_924)
node _T_926 = and(_T_925, asSInt(UInt<27>(0h4000000)))
node _T_927 = asSInt(_T_926)
node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0)))
node _T_929 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_930 = cvt(_T_929)
node _T_931 = and(_T_930, asSInt(UInt<13>(0h1000)))
node _T_932 = asSInt(_T_931)
node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0)))
node _T_934 = or(_T_903, _T_908)
node _T_935 = or(_T_934, _T_913)
node _T_936 = or(_T_935, _T_918)
node _T_937 = or(_T_936, _T_923)
node _T_938 = or(_T_937, _T_928)
node _T_939 = or(_T_938, _T_933)
node _T_940 = and(_T_898, _T_939)
node _T_941 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_942 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_943 = and(_T_941, _T_942)
node _T_944 = or(UInt<1>(0h0), _T_943)
node _T_945 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_946 = cvt(_T_945)
node _T_947 = and(_T_946, asSInt(UInt<17>(0h10000)))
node _T_948 = asSInt(_T_947)
node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0)))
node _T_950 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_951 = cvt(_T_950)
node _T_952 = and(_T_951, asSInt(UInt<29>(0h10000000)))
node _T_953 = asSInt(_T_952)
node _T_954 = eq(_T_953, asSInt(UInt<1>(0h0)))
node _T_955 = or(_T_949, _T_954)
node _T_956 = and(_T_944, _T_955)
node _T_957 = or(UInt<1>(0h0), _T_897)
node _T_958 = or(_T_957, _T_940)
node _T_959 = or(_T_958, _T_956)
node _T_960 = and(_T_887, _T_959)
node _T_961 = asUInt(reset)
node _T_962 = eq(_T_961, UInt<1>(0h0))
when _T_962 :
node _T_963 = eq(_T_960, UInt<1>(0h0))
when _T_963 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_960, UInt<1>(0h1), "") : assert_46
node _T_964 = asUInt(reset)
node _T_965 = eq(_T_964, UInt<1>(0h0))
when _T_965 :
node _T_966 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_966 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_967 = asUInt(reset)
node _T_968 = eq(_T_967, UInt<1>(0h0))
when _T_968 :
node _T_969 = eq(is_aligned, UInt<1>(0h0))
when _T_969 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_970 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_971 = asUInt(reset)
node _T_972 = eq(_T_971, UInt<1>(0h0))
when _T_972 :
node _T_973 = eq(_T_970, UInt<1>(0h0))
when _T_973 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_970, UInt<1>(0h1), "") : assert_49
node _T_974 = eq(io.in.a.bits.mask, mask)
node _T_975 = asUInt(reset)
node _T_976 = eq(_T_975, UInt<1>(0h0))
when _T_976 :
node _T_977 = eq(_T_974, UInt<1>(0h0))
when _T_977 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_974, UInt<1>(0h1), "") : assert_50
node _T_978 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_979 = asUInt(reset)
node _T_980 = eq(_T_979, UInt<1>(0h0))
when _T_980 :
node _T_981 = eq(_T_978, UInt<1>(0h0))
when _T_981 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_978, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_982 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_983 = asUInt(reset)
node _T_984 = eq(_T_983, UInt<1>(0h0))
when _T_984 :
node _T_985 = eq(_T_982, UInt<1>(0h0))
when _T_985 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_982, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 5)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h1f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_986 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_986 :
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_990 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_991 = asUInt(reset)
node _T_992 = eq(_T_991, UInt<1>(0h0))
when _T_992 :
node _T_993 = eq(_T_990, UInt<1>(0h0))
when _T_993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_990, UInt<1>(0h1), "") : assert_54
node _T_994 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_995 = asUInt(reset)
node _T_996 = eq(_T_995, UInt<1>(0h0))
when _T_996 :
node _T_997 = eq(_T_994, UInt<1>(0h0))
when _T_997 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_994, UInt<1>(0h1), "") : assert_55
node _T_998 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_999 = asUInt(reset)
node _T_1000 = eq(_T_999, UInt<1>(0h0))
when _T_1000 :
node _T_1001 = eq(_T_998, UInt<1>(0h0))
when _T_1001 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_998, UInt<1>(0h1), "") : assert_56
node _T_1002 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1003 = asUInt(reset)
node _T_1004 = eq(_T_1003, UInt<1>(0h0))
when _T_1004 :
node _T_1005 = eq(_T_1002, UInt<1>(0h0))
when _T_1005 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1002, UInt<1>(0h1), "") : assert_57
node _T_1006 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1006 :
node _T_1007 = asUInt(reset)
node _T_1008 = eq(_T_1007, UInt<1>(0h0))
when _T_1008 :
node _T_1009 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1009 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_1010 = asUInt(reset)
node _T_1011 = eq(_T_1010, UInt<1>(0h0))
when _T_1011 :
node _T_1012 = eq(sink_ok, UInt<1>(0h0))
when _T_1012 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1013 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1014 = asUInt(reset)
node _T_1015 = eq(_T_1014, UInt<1>(0h0))
when _T_1015 :
node _T_1016 = eq(_T_1013, UInt<1>(0h0))
when _T_1016 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1013, UInt<1>(0h1), "") : assert_60
node _T_1017 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1018 = asUInt(reset)
node _T_1019 = eq(_T_1018, UInt<1>(0h0))
when _T_1019 :
node _T_1020 = eq(_T_1017, UInt<1>(0h0))
when _T_1020 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1017, UInt<1>(0h1), "") : assert_61
node _T_1021 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1022 = asUInt(reset)
node _T_1023 = eq(_T_1022, UInt<1>(0h0))
when _T_1023 :
node _T_1024 = eq(_T_1021, UInt<1>(0h0))
when _T_1024 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1021, UInt<1>(0h1), "") : assert_62
node _T_1025 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1026 = asUInt(reset)
node _T_1027 = eq(_T_1026, UInt<1>(0h0))
when _T_1027 :
node _T_1028 = eq(_T_1025, UInt<1>(0h0))
when _T_1028 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1025, UInt<1>(0h1), "") : assert_63
node _T_1029 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1030 = or(UInt<1>(0h1), _T_1029)
node _T_1031 = asUInt(reset)
node _T_1032 = eq(_T_1031, UInt<1>(0h0))
when _T_1032 :
node _T_1033 = eq(_T_1030, UInt<1>(0h0))
when _T_1033 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1030, UInt<1>(0h1), "") : assert_64
node _T_1034 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1034 :
node _T_1035 = asUInt(reset)
node _T_1036 = eq(_T_1035, UInt<1>(0h0))
when _T_1036 :
node _T_1037 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1037 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_1038 = asUInt(reset)
node _T_1039 = eq(_T_1038, UInt<1>(0h0))
when _T_1039 :
node _T_1040 = eq(sink_ok, UInt<1>(0h0))
when _T_1040 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1041 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(_T_1041, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1041, UInt<1>(0h1), "") : assert_67
node _T_1045 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1046 = asUInt(reset)
node _T_1047 = eq(_T_1046, UInt<1>(0h0))
when _T_1047 :
node _T_1048 = eq(_T_1045, UInt<1>(0h0))
when _T_1048 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1045, UInt<1>(0h1), "") : assert_68
node _T_1049 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1050 = asUInt(reset)
node _T_1051 = eq(_T_1050, UInt<1>(0h0))
when _T_1051 :
node _T_1052 = eq(_T_1049, UInt<1>(0h0))
when _T_1052 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1049, UInt<1>(0h1), "") : assert_69
node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1054 = or(_T_1053, io.in.d.bits.corrupt)
node _T_1055 = asUInt(reset)
node _T_1056 = eq(_T_1055, UInt<1>(0h0))
when _T_1056 :
node _T_1057 = eq(_T_1054, UInt<1>(0h0))
when _T_1057 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1054, UInt<1>(0h1), "") : assert_70
node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1059 = or(UInt<1>(0h1), _T_1058)
node _T_1060 = asUInt(reset)
node _T_1061 = eq(_T_1060, UInt<1>(0h0))
when _T_1061 :
node _T_1062 = eq(_T_1059, UInt<1>(0h0))
when _T_1062 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1059, UInt<1>(0h1), "") : assert_71
node _T_1063 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1063 :
node _T_1064 = asUInt(reset)
node _T_1065 = eq(_T_1064, UInt<1>(0h0))
when _T_1065 :
node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1066 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1068 = asUInt(reset)
node _T_1069 = eq(_T_1068, UInt<1>(0h0))
when _T_1069 :
node _T_1070 = eq(_T_1067, UInt<1>(0h0))
when _T_1070 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1067, UInt<1>(0h1), "") : assert_73
node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1072 = asUInt(reset)
node _T_1073 = eq(_T_1072, UInt<1>(0h0))
when _T_1073 :
node _T_1074 = eq(_T_1071, UInt<1>(0h0))
when _T_1074 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1071, UInt<1>(0h1), "") : assert_74
node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1076 = or(UInt<1>(0h1), _T_1075)
node _T_1077 = asUInt(reset)
node _T_1078 = eq(_T_1077, UInt<1>(0h0))
when _T_1078 :
node _T_1079 = eq(_T_1076, UInt<1>(0h0))
when _T_1079 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1076, UInt<1>(0h1), "") : assert_75
node _T_1080 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1080 :
node _T_1081 = asUInt(reset)
node _T_1082 = eq(_T_1081, UInt<1>(0h0))
when _T_1082 :
node _T_1083 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1083 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_1084 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(_T_1084, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1084, UInt<1>(0h1), "") : assert_77
node _T_1088 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1089 = or(_T_1088, io.in.d.bits.corrupt)
node _T_1090 = asUInt(reset)
node _T_1091 = eq(_T_1090, UInt<1>(0h0))
when _T_1091 :
node _T_1092 = eq(_T_1089, UInt<1>(0h0))
when _T_1092 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1089, UInt<1>(0h1), "") : assert_78
node _T_1093 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1094 = or(UInt<1>(0h1), _T_1093)
node _T_1095 = asUInt(reset)
node _T_1096 = eq(_T_1095, UInt<1>(0h0))
when _T_1096 :
node _T_1097 = eq(_T_1094, UInt<1>(0h0))
when _T_1097 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1094, UInt<1>(0h1), "") : assert_79
node _T_1098 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1098 :
node _T_1099 = asUInt(reset)
node _T_1100 = eq(_T_1099, UInt<1>(0h0))
when _T_1100 :
node _T_1101 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1101 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_1102 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1103 = asUInt(reset)
node _T_1104 = eq(_T_1103, UInt<1>(0h0))
when _T_1104 :
node _T_1105 = eq(_T_1102, UInt<1>(0h0))
when _T_1105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1102, UInt<1>(0h1), "") : assert_81
node _T_1106 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1107 = asUInt(reset)
node _T_1108 = eq(_T_1107, UInt<1>(0h0))
when _T_1108 :
node _T_1109 = eq(_T_1106, UInt<1>(0h0))
when _T_1109 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1106, UInt<1>(0h1), "") : assert_82
node _T_1110 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1111 = or(UInt<1>(0h1), _T_1110)
node _T_1112 = asUInt(reset)
node _T_1113 = eq(_T_1112, UInt<1>(0h0))
when _T_1113 :
node _T_1114 = eq(_T_1111, UInt<1>(0h0))
when _T_1114 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1111, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1115 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1116 = asUInt(reset)
node _T_1117 = eq(_T_1116, UInt<1>(0h0))
when _T_1117 :
node _T_1118 = eq(_T_1115, UInt<1>(0h0))
when _T_1118 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1115, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1119 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1120 = asUInt(reset)
node _T_1121 = eq(_T_1120, UInt<1>(0h0))
when _T_1121 :
node _T_1122 = eq(_T_1119, UInt<1>(0h0))
when _T_1122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1119, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_4.bits.sink, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1123 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1124 = asUInt(reset)
node _T_1125 = eq(_T_1124, UInt<1>(0h0))
when _T_1125 :
node _T_1126 = eq(_T_1123, UInt<1>(0h0))
when _T_1126 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1123, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1127 = eq(a_first, UInt<1>(0h0))
node _T_1128 = and(io.in.a.valid, _T_1127)
when _T_1128 :
node _T_1129 = eq(io.in.a.bits.opcode, opcode)
node _T_1130 = asUInt(reset)
node _T_1131 = eq(_T_1130, UInt<1>(0h0))
when _T_1131 :
node _T_1132 = eq(_T_1129, UInt<1>(0h0))
when _T_1132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1129, UInt<1>(0h1), "") : assert_87
node _T_1133 = eq(io.in.a.bits.param, param)
node _T_1134 = asUInt(reset)
node _T_1135 = eq(_T_1134, UInt<1>(0h0))
when _T_1135 :
node _T_1136 = eq(_T_1133, UInt<1>(0h0))
when _T_1136 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1133, UInt<1>(0h1), "") : assert_88
node _T_1137 = eq(io.in.a.bits.size, size)
node _T_1138 = asUInt(reset)
node _T_1139 = eq(_T_1138, UInt<1>(0h0))
when _T_1139 :
node _T_1140 = eq(_T_1137, UInt<1>(0h0))
when _T_1140 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1137, UInt<1>(0h1), "") : assert_89
node _T_1141 = eq(io.in.a.bits.source, source)
node _T_1142 = asUInt(reset)
node _T_1143 = eq(_T_1142, UInt<1>(0h0))
when _T_1143 :
node _T_1144 = eq(_T_1141, UInt<1>(0h0))
when _T_1144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1141, UInt<1>(0h1), "") : assert_90
node _T_1145 = eq(io.in.a.bits.address, address)
node _T_1146 = asUInt(reset)
node _T_1147 = eq(_T_1146, UInt<1>(0h0))
when _T_1147 :
node _T_1148 = eq(_T_1145, UInt<1>(0h0))
when _T_1148 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1145, UInt<1>(0h1), "") : assert_91
node _T_1149 = and(io.in.a.ready, io.in.a.valid)
node _T_1150 = and(_T_1149, a_first)
when _T_1150 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1151 = eq(d_first, UInt<1>(0h0))
node _T_1152 = and(io.in.d.valid, _T_1151)
when _T_1152 :
node _T_1153 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1154 = asUInt(reset)
node _T_1155 = eq(_T_1154, UInt<1>(0h0))
when _T_1155 :
node _T_1156 = eq(_T_1153, UInt<1>(0h0))
when _T_1156 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1153, UInt<1>(0h1), "") : assert_92
node _T_1157 = eq(io.in.d.bits.param, param_1)
node _T_1158 = asUInt(reset)
node _T_1159 = eq(_T_1158, UInt<1>(0h0))
when _T_1159 :
node _T_1160 = eq(_T_1157, UInt<1>(0h0))
when _T_1160 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1157, UInt<1>(0h1), "") : assert_93
node _T_1161 = eq(io.in.d.bits.size, size_1)
node _T_1162 = asUInt(reset)
node _T_1163 = eq(_T_1162, UInt<1>(0h0))
when _T_1163 :
node _T_1164 = eq(_T_1161, UInt<1>(0h0))
when _T_1164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1161, UInt<1>(0h1), "") : assert_94
node _T_1165 = eq(io.in.d.bits.source, source_1)
node _T_1166 = asUInt(reset)
node _T_1167 = eq(_T_1166, UInt<1>(0h0))
when _T_1167 :
node _T_1168 = eq(_T_1165, UInt<1>(0h0))
when _T_1168 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1165, UInt<1>(0h1), "") : assert_95
node _T_1169 = eq(io.in.d.bits.sink, sink)
node _T_1170 = asUInt(reset)
node _T_1171 = eq(_T_1170, UInt<1>(0h0))
when _T_1171 :
node _T_1172 = eq(_T_1169, UInt<1>(0h0))
when _T_1172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1169, UInt<1>(0h1), "") : assert_96
node _T_1173 = eq(io.in.d.bits.denied, denied)
node _T_1174 = asUInt(reset)
node _T_1175 = eq(_T_1174, UInt<1>(0h0))
when _T_1175 :
node _T_1176 = eq(_T_1173, UInt<1>(0h0))
when _T_1176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1173, UInt<1>(0h1), "") : assert_97
node _T_1177 = and(io.in.d.ready, io.in.d.valid)
node _T_1178 = and(_T_1177, d_first)
when _T_1178 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<32>, clock, reset, UInt<32>(0h0)
regreset inflight_opcodes : UInt<128>, clock, reset, UInt<128>(0h0)
regreset inflight_sizes : UInt<256>, clock, reset, UInt<256>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<32>
connect a_set, UInt<32>(0h0)
wire a_set_wo_ready : UInt<32>
connect a_set_wo_ready, UInt<32>(0h0)
wire a_opcodes_set : UInt<128>
connect a_opcodes_set, UInt<128>(0h0)
wire a_sizes_set : UInt<256>
connect a_sizes_set, UInt<256>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1179 = and(io.in.a.valid, a_first_1)
node _T_1180 = and(_T_1179, UInt<1>(0h1))
when _T_1180 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1181 = and(io.in.a.ready, io.in.a.valid)
node _T_1182 = and(_T_1181, a_first_1)
node _T_1183 = and(_T_1182, UInt<1>(0h1))
when _T_1183 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1184 = dshr(inflight, io.in.a.bits.source)
node _T_1185 = bits(_T_1184, 0, 0)
node _T_1186 = eq(_T_1185, UInt<1>(0h0))
node _T_1187 = asUInt(reset)
node _T_1188 = eq(_T_1187, UInt<1>(0h0))
when _T_1188 :
node _T_1189 = eq(_T_1186, UInt<1>(0h0))
when _T_1189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1186, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<32>
connect d_clr, UInt<32>(0h0)
wire d_clr_wo_ready : UInt<32>
connect d_clr_wo_ready, UInt<32>(0h0)
wire d_opcodes_clr : UInt<128>
connect d_opcodes_clr, UInt<128>(0h0)
wire d_sizes_clr : UInt<256>
connect d_sizes_clr, UInt<256>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1190 = and(io.in.d.valid, d_first_1)
node _T_1191 = and(_T_1190, UInt<1>(0h1))
node _T_1192 = eq(d_release_ack, UInt<1>(0h0))
node _T_1193 = and(_T_1191, _T_1192)
when _T_1193 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1194 = and(io.in.d.ready, io.in.d.valid)
node _T_1195 = and(_T_1194, d_first_1)
node _T_1196 = and(_T_1195, UInt<1>(0h1))
node _T_1197 = eq(d_release_ack, UInt<1>(0h0))
node _T_1198 = and(_T_1196, _T_1197)
when _T_1198 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1199 = and(io.in.d.valid, d_first_1)
node _T_1200 = and(_T_1199, UInt<1>(0h1))
node _T_1201 = eq(d_release_ack, UInt<1>(0h0))
node _T_1202 = and(_T_1200, _T_1201)
when _T_1202 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1203 = dshr(inflight, io.in.d.bits.source)
node _T_1204 = bits(_T_1203, 0, 0)
node _T_1205 = or(_T_1204, same_cycle_resp)
node _T_1206 = asUInt(reset)
node _T_1207 = eq(_T_1206, UInt<1>(0h0))
when _T_1207 :
node _T_1208 = eq(_T_1205, UInt<1>(0h0))
when _T_1208 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1205, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1209 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1210 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1211 = or(_T_1209, _T_1210)
node _T_1212 = asUInt(reset)
node _T_1213 = eq(_T_1212, UInt<1>(0h0))
when _T_1213 :
node _T_1214 = eq(_T_1211, UInt<1>(0h0))
when _T_1214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1211, UInt<1>(0h1), "") : assert_100
node _T_1215 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1216 = asUInt(reset)
node _T_1217 = eq(_T_1216, UInt<1>(0h0))
when _T_1217 :
node _T_1218 = eq(_T_1215, UInt<1>(0h0))
when _T_1218 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1215, UInt<1>(0h1), "") : assert_101
else :
node _T_1219 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1220 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1221 = or(_T_1219, _T_1220)
node _T_1222 = asUInt(reset)
node _T_1223 = eq(_T_1222, UInt<1>(0h0))
when _T_1223 :
node _T_1224 = eq(_T_1221, UInt<1>(0h0))
when _T_1224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1221, UInt<1>(0h1), "") : assert_102
node _T_1225 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1226 = asUInt(reset)
node _T_1227 = eq(_T_1226, UInt<1>(0h0))
when _T_1227 :
node _T_1228 = eq(_T_1225, UInt<1>(0h0))
when _T_1228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1225, UInt<1>(0h1), "") : assert_103
node _T_1229 = and(io.in.d.valid, d_first_1)
node _T_1230 = and(_T_1229, a_first_1)
node _T_1231 = and(_T_1230, io.in.a.valid)
node _T_1232 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1233 = and(_T_1231, _T_1232)
node _T_1234 = eq(d_release_ack, UInt<1>(0h0))
node _T_1235 = and(_T_1233, _T_1234)
when _T_1235 :
node _T_1236 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1237 = or(_T_1236, io.in.a.ready)
node _T_1238 = asUInt(reset)
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
when _T_1239 :
node _T_1240 = eq(_T_1237, UInt<1>(0h0))
when _T_1240 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1237, UInt<1>(0h1), "") : assert_104
node _T_1241 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1242 = orr(a_set_wo_ready)
node _T_1243 = eq(_T_1242, UInt<1>(0h0))
node _T_1244 = or(_T_1241, _T_1243)
node _T_1245 = asUInt(reset)
node _T_1246 = eq(_T_1245, UInt<1>(0h0))
when _T_1246 :
node _T_1247 = eq(_T_1244, UInt<1>(0h0))
when _T_1247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1244, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_22
node _T_1248 = orr(inflight)
node _T_1249 = eq(_T_1248, UInt<1>(0h0))
node _T_1250 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1251 = or(_T_1249, _T_1250)
node _T_1252 = lt(watchdog, plusarg_reader.out)
node _T_1253 = or(_T_1251, _T_1252)
node _T_1254 = asUInt(reset)
node _T_1255 = eq(_T_1254, UInt<1>(0h0))
when _T_1255 :
node _T_1256 = eq(_T_1253, UInt<1>(0h0))
when _T_1256 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1253, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1257 = and(io.in.a.ready, io.in.a.valid)
node _T_1258 = and(io.in.d.ready, io.in.d.valid)
node _T_1259 = or(_T_1257, _T_1258)
when _T_1259 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<32>, clock, reset, UInt<32>(0h0)
regreset inflight_opcodes_1 : UInt<128>, clock, reset, UInt<128>(0h0)
regreset inflight_sizes_1 : UInt<256>, clock, reset, UInt<256>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<5>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<32>
connect c_set, UInt<32>(0h0)
wire c_set_wo_ready : UInt<32>
connect c_set_wo_ready, UInt<32>(0h0)
wire c_opcodes_set : UInt<128>
connect c_opcodes_set, UInt<128>(0h0)
wire c_sizes_set : UInt<256>
connect c_sizes_set, UInt<256>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1260 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1261 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1262 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1263 = and(_T_1261, _T_1262)
node _T_1264 = and(_T_1260, _T_1263)
when _T_1264 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<5>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1265 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1266 = and(_T_1265, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<5>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1267 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1268 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1269 = and(_T_1267, _T_1268)
node _T_1270 = and(_T_1266, _T_1269)
when _T_1270 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<5>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1271 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1272 = bits(_T_1271, 0, 0)
node _T_1273 = eq(_T_1272, UInt<1>(0h0))
node _T_1274 = asUInt(reset)
node _T_1275 = eq(_T_1274, UInt<1>(0h0))
when _T_1275 :
node _T_1276 = eq(_T_1273, UInt<1>(0h0))
when _T_1276 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1273, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<32>
connect d_clr_1, UInt<32>(0h0)
wire d_clr_wo_ready_1 : UInt<32>
connect d_clr_wo_ready_1, UInt<32>(0h0)
wire d_opcodes_clr_1 : UInt<128>
connect d_opcodes_clr_1, UInt<128>(0h0)
wire d_sizes_clr_1 : UInt<256>
connect d_sizes_clr_1, UInt<256>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1277 = and(io.in.d.valid, d_first_2)
node _T_1278 = and(_T_1277, UInt<1>(0h1))
node _T_1279 = and(_T_1278, d_release_ack_1)
when _T_1279 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1280 = and(io.in.d.ready, io.in.d.valid)
node _T_1281 = and(_T_1280, d_first_2)
node _T_1282 = and(_T_1281, UInt<1>(0h1))
node _T_1283 = and(_T_1282, d_release_ack_1)
when _T_1283 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1284 = and(io.in.d.valid, d_first_2)
node _T_1285 = and(_T_1284, UInt<1>(0h1))
node _T_1286 = and(_T_1285, d_release_ack_1)
when _T_1286 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1287 = dshr(inflight_1, io.in.d.bits.source)
node _T_1288 = bits(_T_1287, 0, 0)
node _T_1289 = or(_T_1288, same_cycle_resp_1)
node _T_1290 = asUInt(reset)
node _T_1291 = eq(_T_1290, UInt<1>(0h0))
when _T_1291 :
node _T_1292 = eq(_T_1289, UInt<1>(0h0))
when _T_1292 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1289, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<5>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1293 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1294 = asUInt(reset)
node _T_1295 = eq(_T_1294, UInt<1>(0h0))
when _T_1295 :
node _T_1296 = eq(_T_1293, UInt<1>(0h0))
when _T_1296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1293, UInt<1>(0h1), "") : assert_109
else :
node _T_1297 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1298 = asUInt(reset)
node _T_1299 = eq(_T_1298, UInt<1>(0h0))
when _T_1299 :
node _T_1300 = eq(_T_1297, UInt<1>(0h0))
when _T_1300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1297, UInt<1>(0h1), "") : assert_110
node _T_1301 = and(io.in.d.valid, d_first_2)
node _T_1302 = and(_T_1301, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<5>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1303 = and(_T_1302, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<5>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1304 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1305 = and(_T_1303, _T_1304)
node _T_1306 = and(_T_1305, d_release_ack_1)
node _T_1307 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1308 = and(_T_1306, _T_1307)
when _T_1308 :
node _T_1309 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<5>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1310 = or(_T_1309, _WIRE_23.ready)
node _T_1311 = asUInt(reset)
node _T_1312 = eq(_T_1311, UInt<1>(0h0))
when _T_1312 :
node _T_1313 = eq(_T_1310, UInt<1>(0h0))
when _T_1313 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1310, UInt<1>(0h1), "") : assert_111
node _T_1314 = orr(c_set_wo_ready)
when _T_1314 :
node _T_1315 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1316 = asUInt(reset)
node _T_1317 = eq(_T_1316, UInt<1>(0h0))
when _T_1317 :
node _T_1318 = eq(_T_1315, UInt<1>(0h0))
when _T_1318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1315, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_23
node _T_1319 = orr(inflight_1)
node _T_1320 = eq(_T_1319, UInt<1>(0h0))
node _T_1321 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1322 = or(_T_1320, _T_1321)
node _T_1323 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1324 = or(_T_1322, _T_1323)
node _T_1325 = asUInt(reset)
node _T_1326 = eq(_T_1325, UInt<1>(0h0))
when _T_1326 :
node _T_1327 = eq(_T_1324, UInt<1>(0h0))
when _T_1327 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1324, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<5>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1328 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1329 = and(io.in.d.ready, io.in.d.valid)
node _T_1330 = or(_T_1328, _T_1329)
when _T_1330 :
connect watchdog_1, UInt<1>(0h0)
extmodule plusarg_reader_24 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_25 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_11( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] c_set = 32'h0; // @[Monitor.scala:738:34]
wire [31:0] c_set_wo_ready = 32'h0; // @[Monitor.scala:739:34]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52]
wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77]
wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35]
wire [255:0] c_sizes_set = 256'h0; // @[Monitor.scala:741:34]
wire [127:0] c_opcodes_set = 128'h0; // @[Monitor.scala:740:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [31:0] inflight; // @[Monitor.scala:614:27]
reg [127:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [255:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [31:0] a_set; // @[Monitor.scala:626:34]
wire [31:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [127:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [255:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [127:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [127:0] _a_opcode_lookup_T_6 = {124'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [127:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [255:0] _a_size_lookup_T_6 = {248'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[255:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_3 = {27'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [31:0] _GEN_4 = 32'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 32'h0; // @[OneHot.scala:58:35]
wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1183 ? _a_set_T : 32'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [31:0] d_clr; // @[Monitor.scala:664:34]
wire [31:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [127:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [255:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_6 = {27'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [31:0] _GEN_7 = 32'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 32'h0; // @[OneHot.scala:58:35]
wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1198 ? _d_clr_T : 32'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [31:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [31:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [31:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [127:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [127:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [127:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [31:0] inflight_1; // @[Monitor.scala:726:35]
wire [31:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [127:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [127:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [255:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [127:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [127:0] _c_opcode_lookup_T_6 = {124'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [127:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [255:0] _c_size_lookup_T_6 = {248'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[255:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [31:0] d_clr_1; // @[Monitor.scala:774:34]
wire [31:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [127:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [255:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 32'h0; // @[OneHot.scala:58:35]
wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 32'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113]
wire [31:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [31:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [127:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [127:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_31 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_31( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_63 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_63( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module BootROMClockSinkDomain :
output auto : { flip bootrom_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst bootrom of TLROM
connect bootrom.clock, childClock
connect bootrom.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
connect clockNodeIn, auto.clock_in
connect bootrom.auto.in, auto.bootrom_in
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset | module BootROMClockSinkDomain( // @[ClockDomain.scala:14:9]
output auto_bootrom_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_bootrom_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_bootrom_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_bootrom_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_bootrom_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [12:0] auto_bootrom_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [16:0] auto_bootrom_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_bootrom_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_bootrom_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_bootrom_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_bootrom_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_bootrom_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_bootrom_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [12:0] auto_bootrom_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_bootrom_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
wire auto_bootrom_in_a_valid_0 = auto_bootrom_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_bootrom_in_a_bits_opcode_0 = auto_bootrom_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_bootrom_in_a_bits_param_0 = auto_bootrom_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [1:0] auto_bootrom_in_a_bits_size_0 = auto_bootrom_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [12:0] auto_bootrom_in_a_bits_source_0 = auto_bootrom_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [16:0] auto_bootrom_in_a_bits_address_0 = auto_bootrom_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_bootrom_in_a_bits_mask_0 = auto_bootrom_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_bootrom_in_a_bits_data_0 = auto_bootrom_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_bootrom_in_a_bits_corrupt_0 = auto_bootrom_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_bootrom_in_d_ready_0 = auto_bootrom_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire [2:0] auto_bootrom_in_d_bits_opcode = 3'h1; // @[ClockDomain.scala:14:9]
wire [1:0] auto_bootrom_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9]
wire auto_bootrom_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_bootrom_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_bootrom_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9]
wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9]
wire auto_bootrom_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_bootrom_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [12:0] auto_bootrom_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_bootrom_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_bootrom_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17]
TLROM bootrom ( // @[BootROM.scala:86:17]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (auto_bootrom_in_a_ready_0),
.auto_in_a_valid (auto_bootrom_in_a_valid_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_opcode (auto_bootrom_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_param (auto_bootrom_in_a_bits_param_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_size (auto_bootrom_in_a_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_source (auto_bootrom_in_a_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_address (auto_bootrom_in_a_bits_address_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_mask (auto_bootrom_in_a_bits_mask_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_data (auto_bootrom_in_a_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_corrupt (auto_bootrom_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9]
.auto_in_d_ready (auto_bootrom_in_d_ready_0), // @[ClockDomain.scala:14:9]
.auto_in_d_valid (auto_bootrom_in_d_valid_0),
.auto_in_d_bits_size (auto_bootrom_in_d_bits_size_0),
.auto_in_d_bits_source (auto_bootrom_in_d_bits_source_0),
.auto_in_d_bits_data (auto_bootrom_in_d_bits_data_0)
); // @[BootROM.scala:86:17]
assign auto_bootrom_in_a_ready = auto_bootrom_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_bootrom_in_d_valid = auto_bootrom_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_bootrom_in_d_bits_size = auto_bootrom_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_bootrom_in_d_bits_source = auto_bootrom_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_bootrom_in_d_bits_data = auto_bootrom_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_83 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<5>, vc_free : UInt<5>}}
wire _in_flight_WIRE : UInt<1>[5]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
connect _in_flight_WIRE[3], UInt<1>(0h0)
connect _in_flight_WIRE[4], UInt<1>(0h0)
regreset in_flight : UInt<1>[5], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = or(_T_5, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_13 = and(_T_11, _T_12)
node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_17 = and(_T_15, _T_16)
node _T_18 = or(_T_10, _T_17)
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
node _T_21 = eq(_T_18, UInt<1>(0h0))
when _T_21 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_18, UInt<1>(0h1), "") : assert_2
node _T_22 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_23 = or(_T_22, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_23, UInt<1>(0h1), "") : assert_3
node _T_27 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_28 = or(_T_27, UInt<1>(0h0))
node _T_29 = asUInt(reset)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
node _T_31 = eq(_T_28, UInt<1>(0h0))
when _T_31 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4
assert(clock, _T_28, UInt<1>(0h1), "") : assert_4
node _T_32 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4))
node _T_33 = or(_T_32, UInt<1>(0h0))
node _T_34 = asUInt(reset)
node _T_35 = eq(_T_34, UInt<1>(0h0))
when _T_35 :
node _T_36 = eq(_T_33, UInt<1>(0h0))
when _T_36 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5
assert(clock, _T_33, UInt<1>(0h1), "") : assert_5 | module NoCMonitor_83( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46]
wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 3'h2; // @[Monitor.scala:21:46]
wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 3'h3; // @[Monitor.scala:21:46]
wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 3'h4; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_48 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_65
connect io_out_source_valid_0.clock, clock
connect io_out_source_valid_0.reset, reset
connect io_out_source_valid_0.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid_0.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_48( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_65 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_3 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 3)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<3>(0h4))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h2a))
wire _source_ok_WIRE : UInt<1>[9]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_31
connect _source_ok_WIRE[7], _source_ok_T_32
connect _source_ok_WIRE[8], _source_ok_T_33
node _source_ok_T_34 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[2])
node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[3])
node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[4])
node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[5])
node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[6])
node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[7])
node source_ok = or(_source_ok_T_40, _source_ok_WIRE[8])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4))
node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3)
node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3)
node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit)
node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2)
node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T)
node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit)
node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2)
node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1)
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2)
node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2)
node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit)
node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2)
node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4)
node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit)
node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2)
node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5)
node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit)
node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2)
node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6)
node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit)
node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2)
node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_eq_8 = and(mask_sub_4_2, mask_nbit)
node _mask_acc_T_8 = and(mask_size, mask_eq_8)
node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_4_2, mask_bit)
node _mask_acc_T_9 = and(mask_size, mask_eq_9)
node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_5_2, mask_nbit)
node _mask_acc_T_10 = and(mask_size, mask_eq_10)
node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_5_2, mask_bit)
node _mask_acc_T_11 = and(mask_size, mask_eq_11)
node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_6_2, mask_nbit)
node _mask_acc_T_12 = and(mask_size, mask_eq_12)
node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_6_2, mask_bit)
node _mask_acc_T_13 = and(mask_size, mask_eq_13)
node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_7_2, mask_nbit)
node _mask_acc_T_14 = and(mask_size, mask_eq_14)
node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_7_2, mask_bit)
node _mask_acc_T_15 = and(mask_size, mask_eq_15)
node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15)
node mask_lo_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo)
node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8)
node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10)
node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo)
node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14)
node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0)
node _T_64 = shr(io.in.a.bits.source, 3)
node _T_65 = eq(_T_64, UInt<3>(0h4))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<3>(0h7))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_80 = cvt(_T_79)
node _T_81 = and(_T_80, asSInt(UInt<1>(0h0)))
node _T_82 = asSInt(_T_81)
node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0)))
node _T_84 = or(_T_78, _T_83)
node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_88 = cvt(_T_87)
node _T_89 = and(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = asSInt(_T_89)
node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0)))
node _T_92 = or(_T_86, _T_91)
node _T_93 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_94 = eq(_T_93, UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<1>(0h0)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = or(_T_94, _T_99)
node _T_101 = and(_T_11, _T_24)
node _T_102 = and(_T_101, _T_37)
node _T_103 = and(_T_102, _T_50)
node _T_104 = and(_T_103, _T_63)
node _T_105 = and(_T_104, _T_76)
node _T_106 = and(_T_105, _T_84)
node _T_107 = and(_T_106, _T_92)
node _T_108 = and(_T_107, _T_100)
node _T_109 = asUInt(reset)
node _T_110 = eq(_T_109, UInt<1>(0h0))
when _T_110 :
node _T_111 = eq(_T_108, UInt<1>(0h0))
when _T_111 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_108, UInt<1>(0h1), "") : assert_1
node _T_112 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_112 :
node _T_113 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_114 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_115 = and(_T_113, _T_114)
node _T_116 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_117 = shr(io.in.a.bits.source, 2)
node _T_118 = eq(_T_117, UInt<1>(0h0))
node _T_119 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_120 = and(_T_118, _T_119)
node _T_121 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_122 = and(_T_120, _T_121)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_123 = shr(io.in.a.bits.source, 2)
node _T_124 = eq(_T_123, UInt<1>(0h1))
node _T_125 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_126 = and(_T_124, _T_125)
node _T_127 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_128 = and(_T_126, _T_127)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_129 = shr(io.in.a.bits.source, 2)
node _T_130 = eq(_T_129, UInt<2>(0h2))
node _T_131 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_132 = and(_T_130, _T_131)
node _T_133 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_134 = and(_T_132, _T_133)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_135 = shr(io.in.a.bits.source, 2)
node _T_136 = eq(_T_135, UInt<2>(0h3))
node _T_137 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_138 = and(_T_136, _T_137)
node _T_139 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_140 = and(_T_138, _T_139)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0)
node _T_141 = shr(io.in.a.bits.source, 3)
node _T_142 = eq(_T_141, UInt<3>(0h4))
node _T_143 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_144 = and(_T_142, _T_143)
node _T_145 = leq(uncommonBits_9, UInt<3>(0h7))
node _T_146 = and(_T_144, _T_145)
node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_149 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_150 = or(_T_116, _T_122)
node _T_151 = or(_T_150, _T_128)
node _T_152 = or(_T_151, _T_134)
node _T_153 = or(_T_152, _T_140)
node _T_154 = or(_T_153, _T_146)
node _T_155 = or(_T_154, _T_147)
node _T_156 = or(_T_155, _T_148)
node _T_157 = or(_T_156, _T_149)
node _T_158 = and(_T_115, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_161 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_162 = cvt(_T_161)
node _T_163 = and(_T_162, asSInt(UInt<14>(0h2000)))
node _T_164 = asSInt(_T_163)
node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0)))
node _T_166 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_167 = cvt(_T_166)
node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000)))
node _T_169 = asSInt(_T_168)
node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0)))
node _T_171 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_172 = cvt(_T_171)
node _T_173 = and(_T_172, asSInt(UInt<17>(0h10000)))
node _T_174 = asSInt(_T_173)
node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0)))
node _T_176 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_177 = cvt(_T_176)
node _T_178 = and(_T_177, asSInt(UInt<18>(0h2f000)))
node _T_179 = asSInt(_T_178)
node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0)))
node _T_181 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_182 = cvt(_T_181)
node _T_183 = and(_T_182, asSInt(UInt<17>(0h10000)))
node _T_184 = asSInt(_T_183)
node _T_185 = eq(_T_184, asSInt(UInt<1>(0h0)))
node _T_186 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_187 = cvt(_T_186)
node _T_188 = and(_T_187, asSInt(UInt<13>(0h1000)))
node _T_189 = asSInt(_T_188)
node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0)))
node _T_191 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_192 = cvt(_T_191)
node _T_193 = and(_T_192, asSInt(UInt<27>(0h4000000)))
node _T_194 = asSInt(_T_193)
node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0)))
node _T_196 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_197 = cvt(_T_196)
node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000)))
node _T_199 = asSInt(_T_198)
node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0)))
node _T_201 = or(_T_165, _T_170)
node _T_202 = or(_T_201, _T_175)
node _T_203 = or(_T_202, _T_180)
node _T_204 = or(_T_203, _T_185)
node _T_205 = or(_T_204, _T_190)
node _T_206 = or(_T_205, _T_195)
node _T_207 = or(_T_206, _T_200)
node _T_208 = and(_T_160, _T_207)
node _T_209 = or(UInt<1>(0h0), _T_208)
node _T_210 = and(_T_159, _T_209)
node _T_211 = asUInt(reset)
node _T_212 = eq(_T_211, UInt<1>(0h0))
when _T_212 :
node _T_213 = eq(_T_210, UInt<1>(0h0))
when _T_213 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_210, UInt<1>(0h1), "") : assert_2
node _T_214 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_215 = shr(io.in.a.bits.source, 2)
node _T_216 = eq(_T_215, UInt<1>(0h0))
node _T_217 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_218 = and(_T_216, _T_217)
node _T_219 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_220 = and(_T_218, _T_219)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_221 = shr(io.in.a.bits.source, 2)
node _T_222 = eq(_T_221, UInt<1>(0h1))
node _T_223 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_224 = and(_T_222, _T_223)
node _T_225 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_226 = and(_T_224, _T_225)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_227 = shr(io.in.a.bits.source, 2)
node _T_228 = eq(_T_227, UInt<2>(0h2))
node _T_229 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_230 = and(_T_228, _T_229)
node _T_231 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_232 = and(_T_230, _T_231)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_233 = shr(io.in.a.bits.source, 2)
node _T_234 = eq(_T_233, UInt<2>(0h3))
node _T_235 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_236 = and(_T_234, _T_235)
node _T_237 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_238 = and(_T_236, _T_237)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0)
node _T_239 = shr(io.in.a.bits.source, 3)
node _T_240 = eq(_T_239, UInt<3>(0h4))
node _T_241 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_242 = and(_T_240, _T_241)
node _T_243 = leq(uncommonBits_14, UInt<3>(0h7))
node _T_244 = and(_T_242, _T_243)
node _T_245 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_246 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_247 = eq(io.in.a.bits.source, UInt<6>(0h2a))
wire _WIRE : UInt<1>[9]
connect _WIRE[0], _T_214
connect _WIRE[1], _T_220
connect _WIRE[2], _T_226
connect _WIRE[3], _T_232
connect _WIRE[4], _T_238
connect _WIRE[5], _T_244
connect _WIRE[6], _T_245
connect _WIRE[7], _T_246
connect _WIRE[8], _T_247
node _T_248 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_249 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_250 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_251 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_252 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_253 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_254 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_255 = mux(_WIRE[6], _T_248, UInt<1>(0h0))
node _T_256 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_257 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_258 = or(_T_249, _T_250)
node _T_259 = or(_T_258, _T_251)
node _T_260 = or(_T_259, _T_252)
node _T_261 = or(_T_260, _T_253)
node _T_262 = or(_T_261, _T_254)
node _T_263 = or(_T_262, _T_255)
node _T_264 = or(_T_263, _T_256)
node _T_265 = or(_T_264, _T_257)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_265
node _T_266 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_267 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_268 = and(_T_266, _T_267)
node _T_269 = or(UInt<1>(0h0), _T_268)
node _T_270 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_271 = cvt(_T_270)
node _T_272 = and(_T_271, asSInt(UInt<14>(0h2000)))
node _T_273 = asSInt(_T_272)
node _T_274 = eq(_T_273, asSInt(UInt<1>(0h0)))
node _T_275 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_276 = cvt(_T_275)
node _T_277 = and(_T_276, asSInt(UInt<13>(0h1000)))
node _T_278 = asSInt(_T_277)
node _T_279 = eq(_T_278, asSInt(UInt<1>(0h0)))
node _T_280 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_281 = cvt(_T_280)
node _T_282 = and(_T_281, asSInt(UInt<17>(0h10000)))
node _T_283 = asSInt(_T_282)
node _T_284 = eq(_T_283, asSInt(UInt<1>(0h0)))
node _T_285 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_286 = cvt(_T_285)
node _T_287 = and(_T_286, asSInt(UInt<18>(0h2f000)))
node _T_288 = asSInt(_T_287)
node _T_289 = eq(_T_288, asSInt(UInt<1>(0h0)))
node _T_290 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_291 = cvt(_T_290)
node _T_292 = and(_T_291, asSInt(UInt<17>(0h10000)))
node _T_293 = asSInt(_T_292)
node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0)))
node _T_295 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_296 = cvt(_T_295)
node _T_297 = and(_T_296, asSInt(UInt<13>(0h1000)))
node _T_298 = asSInt(_T_297)
node _T_299 = eq(_T_298, asSInt(UInt<1>(0h0)))
node _T_300 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_301 = cvt(_T_300)
node _T_302 = and(_T_301, asSInt(UInt<27>(0h4000000)))
node _T_303 = asSInt(_T_302)
node _T_304 = eq(_T_303, asSInt(UInt<1>(0h0)))
node _T_305 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_306 = cvt(_T_305)
node _T_307 = and(_T_306, asSInt(UInt<13>(0h1000)))
node _T_308 = asSInt(_T_307)
node _T_309 = eq(_T_308, asSInt(UInt<1>(0h0)))
node _T_310 = or(_T_274, _T_279)
node _T_311 = or(_T_310, _T_284)
node _T_312 = or(_T_311, _T_289)
node _T_313 = or(_T_312, _T_294)
node _T_314 = or(_T_313, _T_299)
node _T_315 = or(_T_314, _T_304)
node _T_316 = or(_T_315, _T_309)
node _T_317 = and(_T_269, _T_316)
node _T_318 = or(UInt<1>(0h0), _T_317)
node _T_319 = and(_WIRE_1, _T_318)
node _T_320 = asUInt(reset)
node _T_321 = eq(_T_320, UInt<1>(0h0))
when _T_321 :
node _T_322 = eq(_T_319, UInt<1>(0h0))
when _T_322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_319, UInt<1>(0h1), "") : assert_3
node _T_323 = asUInt(reset)
node _T_324 = eq(_T_323, UInt<1>(0h0))
when _T_324 :
node _T_325 = eq(source_ok, UInt<1>(0h0))
when _T_325 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_326 = geq(io.in.a.bits.size, UInt<3>(0h4))
node _T_327 = asUInt(reset)
node _T_328 = eq(_T_327, UInt<1>(0h0))
when _T_328 :
node _T_329 = eq(_T_326, UInt<1>(0h0))
when _T_329 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_326, UInt<1>(0h1), "") : assert_5
node _T_330 = asUInt(reset)
node _T_331 = eq(_T_330, UInt<1>(0h0))
when _T_331 :
node _T_332 = eq(is_aligned, UInt<1>(0h0))
when _T_332 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_333 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_334 = asUInt(reset)
node _T_335 = eq(_T_334, UInt<1>(0h0))
when _T_335 :
node _T_336 = eq(_T_333, UInt<1>(0h0))
when _T_336 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_333, UInt<1>(0h1), "") : assert_7
node _T_337 = not(io.in.a.bits.mask)
node _T_338 = eq(_T_337, UInt<1>(0h0))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_338, UInt<1>(0h1), "") : assert_8
node _T_342 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_343 = asUInt(reset)
node _T_344 = eq(_T_343, UInt<1>(0h0))
when _T_344 :
node _T_345 = eq(_T_342, UInt<1>(0h0))
when _T_345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_342, UInt<1>(0h1), "") : assert_9
node _T_346 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_346 :
node _T_347 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_348 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_349 = and(_T_347, _T_348)
node _T_350 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_351 = shr(io.in.a.bits.source, 2)
node _T_352 = eq(_T_351, UInt<1>(0h0))
node _T_353 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_354 = and(_T_352, _T_353)
node _T_355 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_356 = and(_T_354, _T_355)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_357 = shr(io.in.a.bits.source, 2)
node _T_358 = eq(_T_357, UInt<1>(0h1))
node _T_359 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_360 = and(_T_358, _T_359)
node _T_361 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_362 = and(_T_360, _T_361)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_363 = shr(io.in.a.bits.source, 2)
node _T_364 = eq(_T_363, UInt<2>(0h2))
node _T_365 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_366 = and(_T_364, _T_365)
node _T_367 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_368 = and(_T_366, _T_367)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_369 = shr(io.in.a.bits.source, 2)
node _T_370 = eq(_T_369, UInt<2>(0h3))
node _T_371 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_372 = and(_T_370, _T_371)
node _T_373 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_374 = and(_T_372, _T_373)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0)
node _T_375 = shr(io.in.a.bits.source, 3)
node _T_376 = eq(_T_375, UInt<3>(0h4))
node _T_377 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_378 = and(_T_376, _T_377)
node _T_379 = leq(uncommonBits_19, UInt<3>(0h7))
node _T_380 = and(_T_378, _T_379)
node _T_381 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_382 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_383 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_384 = or(_T_350, _T_356)
node _T_385 = or(_T_384, _T_362)
node _T_386 = or(_T_385, _T_368)
node _T_387 = or(_T_386, _T_374)
node _T_388 = or(_T_387, _T_380)
node _T_389 = or(_T_388, _T_381)
node _T_390 = or(_T_389, _T_382)
node _T_391 = or(_T_390, _T_383)
node _T_392 = and(_T_349, _T_391)
node _T_393 = or(UInt<1>(0h0), _T_392)
node _T_394 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_395 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_396 = cvt(_T_395)
node _T_397 = and(_T_396, asSInt(UInt<14>(0h2000)))
node _T_398 = asSInt(_T_397)
node _T_399 = eq(_T_398, asSInt(UInt<1>(0h0)))
node _T_400 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_401 = cvt(_T_400)
node _T_402 = and(_T_401, asSInt(UInt<13>(0h1000)))
node _T_403 = asSInt(_T_402)
node _T_404 = eq(_T_403, asSInt(UInt<1>(0h0)))
node _T_405 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_406 = cvt(_T_405)
node _T_407 = and(_T_406, asSInt(UInt<17>(0h10000)))
node _T_408 = asSInt(_T_407)
node _T_409 = eq(_T_408, asSInt(UInt<1>(0h0)))
node _T_410 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_411 = cvt(_T_410)
node _T_412 = and(_T_411, asSInt(UInt<18>(0h2f000)))
node _T_413 = asSInt(_T_412)
node _T_414 = eq(_T_413, asSInt(UInt<1>(0h0)))
node _T_415 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_416 = cvt(_T_415)
node _T_417 = and(_T_416, asSInt(UInt<17>(0h10000)))
node _T_418 = asSInt(_T_417)
node _T_419 = eq(_T_418, asSInt(UInt<1>(0h0)))
node _T_420 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_421 = cvt(_T_420)
node _T_422 = and(_T_421, asSInt(UInt<13>(0h1000)))
node _T_423 = asSInt(_T_422)
node _T_424 = eq(_T_423, asSInt(UInt<1>(0h0)))
node _T_425 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_426 = cvt(_T_425)
node _T_427 = and(_T_426, asSInt(UInt<27>(0h4000000)))
node _T_428 = asSInt(_T_427)
node _T_429 = eq(_T_428, asSInt(UInt<1>(0h0)))
node _T_430 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_431 = cvt(_T_430)
node _T_432 = and(_T_431, asSInt(UInt<13>(0h1000)))
node _T_433 = asSInt(_T_432)
node _T_434 = eq(_T_433, asSInt(UInt<1>(0h0)))
node _T_435 = or(_T_399, _T_404)
node _T_436 = or(_T_435, _T_409)
node _T_437 = or(_T_436, _T_414)
node _T_438 = or(_T_437, _T_419)
node _T_439 = or(_T_438, _T_424)
node _T_440 = or(_T_439, _T_429)
node _T_441 = or(_T_440, _T_434)
node _T_442 = and(_T_394, _T_441)
node _T_443 = or(UInt<1>(0h0), _T_442)
node _T_444 = and(_T_393, _T_443)
node _T_445 = asUInt(reset)
node _T_446 = eq(_T_445, UInt<1>(0h0))
when _T_446 :
node _T_447 = eq(_T_444, UInt<1>(0h0))
when _T_447 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_444, UInt<1>(0h1), "") : assert_10
node _T_448 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_449 = shr(io.in.a.bits.source, 2)
node _T_450 = eq(_T_449, UInt<1>(0h0))
node _T_451 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_452 = and(_T_450, _T_451)
node _T_453 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_454 = and(_T_452, _T_453)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_455 = shr(io.in.a.bits.source, 2)
node _T_456 = eq(_T_455, UInt<1>(0h1))
node _T_457 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_458 = and(_T_456, _T_457)
node _T_459 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_460 = and(_T_458, _T_459)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_461 = shr(io.in.a.bits.source, 2)
node _T_462 = eq(_T_461, UInt<2>(0h2))
node _T_463 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_464 = and(_T_462, _T_463)
node _T_465 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_466 = and(_T_464, _T_465)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_467 = shr(io.in.a.bits.source, 2)
node _T_468 = eq(_T_467, UInt<2>(0h3))
node _T_469 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_470 = and(_T_468, _T_469)
node _T_471 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_472 = and(_T_470, _T_471)
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0)
node _T_473 = shr(io.in.a.bits.source, 3)
node _T_474 = eq(_T_473, UInt<3>(0h4))
node _T_475 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_476 = and(_T_474, _T_475)
node _T_477 = leq(uncommonBits_24, UInt<3>(0h7))
node _T_478 = and(_T_476, _T_477)
node _T_479 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_480 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_481 = eq(io.in.a.bits.source, UInt<6>(0h2a))
wire _WIRE_2 : UInt<1>[9]
connect _WIRE_2[0], _T_448
connect _WIRE_2[1], _T_454
connect _WIRE_2[2], _T_460
connect _WIRE_2[3], _T_466
connect _WIRE_2[4], _T_472
connect _WIRE_2[5], _T_478
connect _WIRE_2[6], _T_479
connect _WIRE_2[7], _T_480
connect _WIRE_2[8], _T_481
node _T_482 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_483 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_484 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_485 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_486 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_487 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_488 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_489 = mux(_WIRE_2[6], _T_482, UInt<1>(0h0))
node _T_490 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_491 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_492 = or(_T_483, _T_484)
node _T_493 = or(_T_492, _T_485)
node _T_494 = or(_T_493, _T_486)
node _T_495 = or(_T_494, _T_487)
node _T_496 = or(_T_495, _T_488)
node _T_497 = or(_T_496, _T_489)
node _T_498 = or(_T_497, _T_490)
node _T_499 = or(_T_498, _T_491)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_499
node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_501 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_502 = and(_T_500, _T_501)
node _T_503 = or(UInt<1>(0h0), _T_502)
node _T_504 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_505 = cvt(_T_504)
node _T_506 = and(_T_505, asSInt(UInt<14>(0h2000)))
node _T_507 = asSInt(_T_506)
node _T_508 = eq(_T_507, asSInt(UInt<1>(0h0)))
node _T_509 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_510 = cvt(_T_509)
node _T_511 = and(_T_510, asSInt(UInt<13>(0h1000)))
node _T_512 = asSInt(_T_511)
node _T_513 = eq(_T_512, asSInt(UInt<1>(0h0)))
node _T_514 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_515 = cvt(_T_514)
node _T_516 = and(_T_515, asSInt(UInt<17>(0h10000)))
node _T_517 = asSInt(_T_516)
node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0)))
node _T_519 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_520 = cvt(_T_519)
node _T_521 = and(_T_520, asSInt(UInt<18>(0h2f000)))
node _T_522 = asSInt(_T_521)
node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0)))
node _T_524 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_525 = cvt(_T_524)
node _T_526 = and(_T_525, asSInt(UInt<17>(0h10000)))
node _T_527 = asSInt(_T_526)
node _T_528 = eq(_T_527, asSInt(UInt<1>(0h0)))
node _T_529 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_530 = cvt(_T_529)
node _T_531 = and(_T_530, asSInt(UInt<13>(0h1000)))
node _T_532 = asSInt(_T_531)
node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0)))
node _T_534 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_535 = cvt(_T_534)
node _T_536 = and(_T_535, asSInt(UInt<27>(0h4000000)))
node _T_537 = asSInt(_T_536)
node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0)))
node _T_539 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_540 = cvt(_T_539)
node _T_541 = and(_T_540, asSInt(UInt<13>(0h1000)))
node _T_542 = asSInt(_T_541)
node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0)))
node _T_544 = or(_T_508, _T_513)
node _T_545 = or(_T_544, _T_518)
node _T_546 = or(_T_545, _T_523)
node _T_547 = or(_T_546, _T_528)
node _T_548 = or(_T_547, _T_533)
node _T_549 = or(_T_548, _T_538)
node _T_550 = or(_T_549, _T_543)
node _T_551 = and(_T_503, _T_550)
node _T_552 = or(UInt<1>(0h0), _T_551)
node _T_553 = and(_WIRE_3, _T_552)
node _T_554 = asUInt(reset)
node _T_555 = eq(_T_554, UInt<1>(0h0))
when _T_555 :
node _T_556 = eq(_T_553, UInt<1>(0h0))
when _T_556 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_553, UInt<1>(0h1), "") : assert_11
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(source_ok, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_560 = geq(io.in.a.bits.size, UInt<3>(0h4))
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_560, UInt<1>(0h1), "") : assert_13
node _T_564 = asUInt(reset)
node _T_565 = eq(_T_564, UInt<1>(0h0))
when _T_565 :
node _T_566 = eq(is_aligned, UInt<1>(0h0))
when _T_566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_567 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_568 = asUInt(reset)
node _T_569 = eq(_T_568, UInt<1>(0h0))
when _T_569 :
node _T_570 = eq(_T_567, UInt<1>(0h0))
when _T_570 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_567, UInt<1>(0h1), "") : assert_15
node _T_571 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_572 = asUInt(reset)
node _T_573 = eq(_T_572, UInt<1>(0h0))
when _T_573 :
node _T_574 = eq(_T_571, UInt<1>(0h0))
when _T_574 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_571, UInt<1>(0h1), "") : assert_16
node _T_575 = not(io.in.a.bits.mask)
node _T_576 = eq(_T_575, UInt<1>(0h0))
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_576, UInt<1>(0h1), "") : assert_17
node _T_580 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_580, UInt<1>(0h1), "") : assert_18
node _T_584 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_584 :
node _T_585 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_586 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_587 = and(_T_585, _T_586)
node _T_588 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_589 = shr(io.in.a.bits.source, 2)
node _T_590 = eq(_T_589, UInt<1>(0h0))
node _T_591 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_592 = and(_T_590, _T_591)
node _T_593 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_594 = and(_T_592, _T_593)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_595 = shr(io.in.a.bits.source, 2)
node _T_596 = eq(_T_595, UInt<1>(0h1))
node _T_597 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_598 = and(_T_596, _T_597)
node _T_599 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_600 = and(_T_598, _T_599)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_601 = shr(io.in.a.bits.source, 2)
node _T_602 = eq(_T_601, UInt<2>(0h2))
node _T_603 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_604 = and(_T_602, _T_603)
node _T_605 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_606 = and(_T_604, _T_605)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_607 = shr(io.in.a.bits.source, 2)
node _T_608 = eq(_T_607, UInt<2>(0h3))
node _T_609 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_610 = and(_T_608, _T_609)
node _T_611 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_612 = and(_T_610, _T_611)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0)
node _T_613 = shr(io.in.a.bits.source, 3)
node _T_614 = eq(_T_613, UInt<3>(0h4))
node _T_615 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_616 = and(_T_614, _T_615)
node _T_617 = leq(uncommonBits_29, UInt<3>(0h7))
node _T_618 = and(_T_616, _T_617)
node _T_619 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_620 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_621 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_622 = or(_T_588, _T_594)
node _T_623 = or(_T_622, _T_600)
node _T_624 = or(_T_623, _T_606)
node _T_625 = or(_T_624, _T_612)
node _T_626 = or(_T_625, _T_618)
node _T_627 = or(_T_626, _T_619)
node _T_628 = or(_T_627, _T_620)
node _T_629 = or(_T_628, _T_621)
node _T_630 = and(_T_587, _T_629)
node _T_631 = or(UInt<1>(0h0), _T_630)
node _T_632 = asUInt(reset)
node _T_633 = eq(_T_632, UInt<1>(0h0))
when _T_633 :
node _T_634 = eq(_T_631, UInt<1>(0h0))
when _T_634 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_631, UInt<1>(0h1), "") : assert_19
node _T_635 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_636 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_637 = and(_T_635, _T_636)
node _T_638 = or(UInt<1>(0h0), _T_637)
node _T_639 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_640 = cvt(_T_639)
node _T_641 = and(_T_640, asSInt(UInt<13>(0h1000)))
node _T_642 = asSInt(_T_641)
node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0)))
node _T_644 = and(_T_638, _T_643)
node _T_645 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_646 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_647 = and(_T_645, _T_646)
node _T_648 = or(UInt<1>(0h0), _T_647)
node _T_649 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_650 = cvt(_T_649)
node _T_651 = and(_T_650, asSInt(UInt<14>(0h2000)))
node _T_652 = asSInt(_T_651)
node _T_653 = eq(_T_652, asSInt(UInt<1>(0h0)))
node _T_654 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_655 = cvt(_T_654)
node _T_656 = and(_T_655, asSInt(UInt<17>(0h10000)))
node _T_657 = asSInt(_T_656)
node _T_658 = eq(_T_657, asSInt(UInt<1>(0h0)))
node _T_659 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_660 = cvt(_T_659)
node _T_661 = and(_T_660, asSInt(UInt<18>(0h2f000)))
node _T_662 = asSInt(_T_661)
node _T_663 = eq(_T_662, asSInt(UInt<1>(0h0)))
node _T_664 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_665 = cvt(_T_664)
node _T_666 = and(_T_665, asSInt(UInt<17>(0h10000)))
node _T_667 = asSInt(_T_666)
node _T_668 = eq(_T_667, asSInt(UInt<1>(0h0)))
node _T_669 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_670 = cvt(_T_669)
node _T_671 = and(_T_670, asSInt(UInt<13>(0h1000)))
node _T_672 = asSInt(_T_671)
node _T_673 = eq(_T_672, asSInt(UInt<1>(0h0)))
node _T_674 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_675 = cvt(_T_674)
node _T_676 = and(_T_675, asSInt(UInt<27>(0h4000000)))
node _T_677 = asSInt(_T_676)
node _T_678 = eq(_T_677, asSInt(UInt<1>(0h0)))
node _T_679 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_680 = cvt(_T_679)
node _T_681 = and(_T_680, asSInt(UInt<13>(0h1000)))
node _T_682 = asSInt(_T_681)
node _T_683 = eq(_T_682, asSInt(UInt<1>(0h0)))
node _T_684 = or(_T_653, _T_658)
node _T_685 = or(_T_684, _T_663)
node _T_686 = or(_T_685, _T_668)
node _T_687 = or(_T_686, _T_673)
node _T_688 = or(_T_687, _T_678)
node _T_689 = or(_T_688, _T_683)
node _T_690 = and(_T_648, _T_689)
node _T_691 = or(UInt<1>(0h0), _T_644)
node _T_692 = or(_T_691, _T_690)
node _T_693 = asUInt(reset)
node _T_694 = eq(_T_693, UInt<1>(0h0))
when _T_694 :
node _T_695 = eq(_T_692, UInt<1>(0h0))
when _T_695 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_692, UInt<1>(0h1), "") : assert_20
node _T_696 = asUInt(reset)
node _T_697 = eq(_T_696, UInt<1>(0h0))
when _T_697 :
node _T_698 = eq(source_ok, UInt<1>(0h0))
when _T_698 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_699 = asUInt(reset)
node _T_700 = eq(_T_699, UInt<1>(0h0))
when _T_700 :
node _T_701 = eq(is_aligned, UInt<1>(0h0))
when _T_701 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_702 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_703 = asUInt(reset)
node _T_704 = eq(_T_703, UInt<1>(0h0))
when _T_704 :
node _T_705 = eq(_T_702, UInt<1>(0h0))
when _T_705 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_702, UInt<1>(0h1), "") : assert_23
node _T_706 = eq(io.in.a.bits.mask, mask)
node _T_707 = asUInt(reset)
node _T_708 = eq(_T_707, UInt<1>(0h0))
when _T_708 :
node _T_709 = eq(_T_706, UInt<1>(0h0))
when _T_709 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_706, UInt<1>(0h1), "") : assert_24
node _T_710 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_711 = asUInt(reset)
node _T_712 = eq(_T_711, UInt<1>(0h0))
when _T_712 :
node _T_713 = eq(_T_710, UInt<1>(0h0))
when _T_713 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_710, UInt<1>(0h1), "") : assert_25
node _T_714 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_714 :
node _T_715 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_716 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_717 = and(_T_715, _T_716)
node _T_718 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_719 = shr(io.in.a.bits.source, 2)
node _T_720 = eq(_T_719, UInt<1>(0h0))
node _T_721 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_722 = and(_T_720, _T_721)
node _T_723 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_724 = and(_T_722, _T_723)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_725 = shr(io.in.a.bits.source, 2)
node _T_726 = eq(_T_725, UInt<1>(0h1))
node _T_727 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_728 = and(_T_726, _T_727)
node _T_729 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_730 = and(_T_728, _T_729)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_731 = shr(io.in.a.bits.source, 2)
node _T_732 = eq(_T_731, UInt<2>(0h2))
node _T_733 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_734 = and(_T_732, _T_733)
node _T_735 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_736 = and(_T_734, _T_735)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_737 = shr(io.in.a.bits.source, 2)
node _T_738 = eq(_T_737, UInt<2>(0h3))
node _T_739 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_740 = and(_T_738, _T_739)
node _T_741 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_742 = and(_T_740, _T_741)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0)
node _T_743 = shr(io.in.a.bits.source, 3)
node _T_744 = eq(_T_743, UInt<3>(0h4))
node _T_745 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_746 = and(_T_744, _T_745)
node _T_747 = leq(uncommonBits_34, UInt<3>(0h7))
node _T_748 = and(_T_746, _T_747)
node _T_749 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_750 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_751 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_752 = or(_T_718, _T_724)
node _T_753 = or(_T_752, _T_730)
node _T_754 = or(_T_753, _T_736)
node _T_755 = or(_T_754, _T_742)
node _T_756 = or(_T_755, _T_748)
node _T_757 = or(_T_756, _T_749)
node _T_758 = or(_T_757, _T_750)
node _T_759 = or(_T_758, _T_751)
node _T_760 = and(_T_717, _T_759)
node _T_761 = or(UInt<1>(0h0), _T_760)
node _T_762 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_763 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_764 = and(_T_762, _T_763)
node _T_765 = or(UInt<1>(0h0), _T_764)
node _T_766 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_767 = cvt(_T_766)
node _T_768 = and(_T_767, asSInt(UInt<13>(0h1000)))
node _T_769 = asSInt(_T_768)
node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0)))
node _T_771 = and(_T_765, _T_770)
node _T_772 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_773 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_774 = and(_T_772, _T_773)
node _T_775 = or(UInt<1>(0h0), _T_774)
node _T_776 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_777 = cvt(_T_776)
node _T_778 = and(_T_777, asSInt(UInt<14>(0h2000)))
node _T_779 = asSInt(_T_778)
node _T_780 = eq(_T_779, asSInt(UInt<1>(0h0)))
node _T_781 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_782 = cvt(_T_781)
node _T_783 = and(_T_782, asSInt(UInt<18>(0h2f000)))
node _T_784 = asSInt(_T_783)
node _T_785 = eq(_T_784, asSInt(UInt<1>(0h0)))
node _T_786 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_787 = cvt(_T_786)
node _T_788 = and(_T_787, asSInt(UInt<17>(0h10000)))
node _T_789 = asSInt(_T_788)
node _T_790 = eq(_T_789, asSInt(UInt<1>(0h0)))
node _T_791 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_792 = cvt(_T_791)
node _T_793 = and(_T_792, asSInt(UInt<13>(0h1000)))
node _T_794 = asSInt(_T_793)
node _T_795 = eq(_T_794, asSInt(UInt<1>(0h0)))
node _T_796 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_797 = cvt(_T_796)
node _T_798 = and(_T_797, asSInt(UInt<27>(0h4000000)))
node _T_799 = asSInt(_T_798)
node _T_800 = eq(_T_799, asSInt(UInt<1>(0h0)))
node _T_801 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_802 = cvt(_T_801)
node _T_803 = and(_T_802, asSInt(UInt<13>(0h1000)))
node _T_804 = asSInt(_T_803)
node _T_805 = eq(_T_804, asSInt(UInt<1>(0h0)))
node _T_806 = or(_T_780, _T_785)
node _T_807 = or(_T_806, _T_790)
node _T_808 = or(_T_807, _T_795)
node _T_809 = or(_T_808, _T_800)
node _T_810 = or(_T_809, _T_805)
node _T_811 = and(_T_775, _T_810)
node _T_812 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_813 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_814 = cvt(_T_813)
node _T_815 = and(_T_814, asSInt(UInt<17>(0h10000)))
node _T_816 = asSInt(_T_815)
node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0)))
node _T_818 = and(_T_812, _T_817)
node _T_819 = or(UInt<1>(0h0), _T_771)
node _T_820 = or(_T_819, _T_811)
node _T_821 = or(_T_820, _T_818)
node _T_822 = and(_T_761, _T_821)
node _T_823 = asUInt(reset)
node _T_824 = eq(_T_823, UInt<1>(0h0))
when _T_824 :
node _T_825 = eq(_T_822, UInt<1>(0h0))
when _T_825 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_822, UInt<1>(0h1), "") : assert_26
node _T_826 = asUInt(reset)
node _T_827 = eq(_T_826, UInt<1>(0h0))
when _T_827 :
node _T_828 = eq(source_ok, UInt<1>(0h0))
when _T_828 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_829 = asUInt(reset)
node _T_830 = eq(_T_829, UInt<1>(0h0))
when _T_830 :
node _T_831 = eq(is_aligned, UInt<1>(0h0))
when _T_831 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_832 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_833 = asUInt(reset)
node _T_834 = eq(_T_833, UInt<1>(0h0))
when _T_834 :
node _T_835 = eq(_T_832, UInt<1>(0h0))
when _T_835 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_832, UInt<1>(0h1), "") : assert_29
node _T_836 = eq(io.in.a.bits.mask, mask)
node _T_837 = asUInt(reset)
node _T_838 = eq(_T_837, UInt<1>(0h0))
when _T_838 :
node _T_839 = eq(_T_836, UInt<1>(0h0))
when _T_839 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_836, UInt<1>(0h1), "") : assert_30
node _T_840 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_840 :
node _T_841 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_842 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_843 = and(_T_841, _T_842)
node _T_844 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_845 = shr(io.in.a.bits.source, 2)
node _T_846 = eq(_T_845, UInt<1>(0h0))
node _T_847 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_848 = and(_T_846, _T_847)
node _T_849 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_850 = and(_T_848, _T_849)
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_851 = shr(io.in.a.bits.source, 2)
node _T_852 = eq(_T_851, UInt<1>(0h1))
node _T_853 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_854 = and(_T_852, _T_853)
node _T_855 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_856 = and(_T_854, _T_855)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_857 = shr(io.in.a.bits.source, 2)
node _T_858 = eq(_T_857, UInt<2>(0h2))
node _T_859 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_860 = and(_T_858, _T_859)
node _T_861 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_862 = and(_T_860, _T_861)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_863 = shr(io.in.a.bits.source, 2)
node _T_864 = eq(_T_863, UInt<2>(0h3))
node _T_865 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_866 = and(_T_864, _T_865)
node _T_867 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_868 = and(_T_866, _T_867)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0)
node _T_869 = shr(io.in.a.bits.source, 3)
node _T_870 = eq(_T_869, UInt<3>(0h4))
node _T_871 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_872 = and(_T_870, _T_871)
node _T_873 = leq(uncommonBits_39, UInt<3>(0h7))
node _T_874 = and(_T_872, _T_873)
node _T_875 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_876 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_877 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_878 = or(_T_844, _T_850)
node _T_879 = or(_T_878, _T_856)
node _T_880 = or(_T_879, _T_862)
node _T_881 = or(_T_880, _T_868)
node _T_882 = or(_T_881, _T_874)
node _T_883 = or(_T_882, _T_875)
node _T_884 = or(_T_883, _T_876)
node _T_885 = or(_T_884, _T_877)
node _T_886 = and(_T_843, _T_885)
node _T_887 = or(UInt<1>(0h0), _T_886)
node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_889 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_890 = and(_T_888, _T_889)
node _T_891 = or(UInt<1>(0h0), _T_890)
node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_893 = cvt(_T_892)
node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000)))
node _T_895 = asSInt(_T_894)
node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0)))
node _T_897 = and(_T_891, _T_896)
node _T_898 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_899 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_900 = and(_T_898, _T_899)
node _T_901 = or(UInt<1>(0h0), _T_900)
node _T_902 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_903 = cvt(_T_902)
node _T_904 = and(_T_903, asSInt(UInt<14>(0h2000)))
node _T_905 = asSInt(_T_904)
node _T_906 = eq(_T_905, asSInt(UInt<1>(0h0)))
node _T_907 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_908 = cvt(_T_907)
node _T_909 = and(_T_908, asSInt(UInt<18>(0h2f000)))
node _T_910 = asSInt(_T_909)
node _T_911 = eq(_T_910, asSInt(UInt<1>(0h0)))
node _T_912 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_913 = cvt(_T_912)
node _T_914 = and(_T_913, asSInt(UInt<17>(0h10000)))
node _T_915 = asSInt(_T_914)
node _T_916 = eq(_T_915, asSInt(UInt<1>(0h0)))
node _T_917 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_918 = cvt(_T_917)
node _T_919 = and(_T_918, asSInt(UInt<13>(0h1000)))
node _T_920 = asSInt(_T_919)
node _T_921 = eq(_T_920, asSInt(UInt<1>(0h0)))
node _T_922 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_923 = cvt(_T_922)
node _T_924 = and(_T_923, asSInt(UInt<27>(0h4000000)))
node _T_925 = asSInt(_T_924)
node _T_926 = eq(_T_925, asSInt(UInt<1>(0h0)))
node _T_927 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_928 = cvt(_T_927)
node _T_929 = and(_T_928, asSInt(UInt<13>(0h1000)))
node _T_930 = asSInt(_T_929)
node _T_931 = eq(_T_930, asSInt(UInt<1>(0h0)))
node _T_932 = or(_T_906, _T_911)
node _T_933 = or(_T_932, _T_916)
node _T_934 = or(_T_933, _T_921)
node _T_935 = or(_T_934, _T_926)
node _T_936 = or(_T_935, _T_931)
node _T_937 = and(_T_901, _T_936)
node _T_938 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_939 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_940 = cvt(_T_939)
node _T_941 = and(_T_940, asSInt(UInt<17>(0h10000)))
node _T_942 = asSInt(_T_941)
node _T_943 = eq(_T_942, asSInt(UInt<1>(0h0)))
node _T_944 = and(_T_938, _T_943)
node _T_945 = or(UInt<1>(0h0), _T_897)
node _T_946 = or(_T_945, _T_937)
node _T_947 = or(_T_946, _T_944)
node _T_948 = and(_T_887, _T_947)
node _T_949 = asUInt(reset)
node _T_950 = eq(_T_949, UInt<1>(0h0))
when _T_950 :
node _T_951 = eq(_T_948, UInt<1>(0h0))
when _T_951 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_948, UInt<1>(0h1), "") : assert_31
node _T_952 = asUInt(reset)
node _T_953 = eq(_T_952, UInt<1>(0h0))
when _T_953 :
node _T_954 = eq(source_ok, UInt<1>(0h0))
when _T_954 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_955 = asUInt(reset)
node _T_956 = eq(_T_955, UInt<1>(0h0))
when _T_956 :
node _T_957 = eq(is_aligned, UInt<1>(0h0))
when _T_957 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_958 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_959 = asUInt(reset)
node _T_960 = eq(_T_959, UInt<1>(0h0))
when _T_960 :
node _T_961 = eq(_T_958, UInt<1>(0h0))
when _T_961 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_958, UInt<1>(0h1), "") : assert_34
node _T_962 = not(mask)
node _T_963 = and(io.in.a.bits.mask, _T_962)
node _T_964 = eq(_T_963, UInt<1>(0h0))
node _T_965 = asUInt(reset)
node _T_966 = eq(_T_965, UInt<1>(0h0))
when _T_966 :
node _T_967 = eq(_T_964, UInt<1>(0h0))
when _T_967 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_964, UInt<1>(0h1), "") : assert_35
node _T_968 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_968 :
node _T_969 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_970 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_971 = and(_T_969, _T_970)
node _T_972 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_973 = shr(io.in.a.bits.source, 2)
node _T_974 = eq(_T_973, UInt<1>(0h0))
node _T_975 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_976 = and(_T_974, _T_975)
node _T_977 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_978 = and(_T_976, _T_977)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_979 = shr(io.in.a.bits.source, 2)
node _T_980 = eq(_T_979, UInt<1>(0h1))
node _T_981 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_982 = and(_T_980, _T_981)
node _T_983 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_984 = and(_T_982, _T_983)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_985 = shr(io.in.a.bits.source, 2)
node _T_986 = eq(_T_985, UInt<2>(0h2))
node _T_987 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_988 = and(_T_986, _T_987)
node _T_989 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_990 = and(_T_988, _T_989)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_991 = shr(io.in.a.bits.source, 2)
node _T_992 = eq(_T_991, UInt<2>(0h3))
node _T_993 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_994 = and(_T_992, _T_993)
node _T_995 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_996 = and(_T_994, _T_995)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 2, 0)
node _T_997 = shr(io.in.a.bits.source, 3)
node _T_998 = eq(_T_997, UInt<3>(0h4))
node _T_999 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_1000 = and(_T_998, _T_999)
node _T_1001 = leq(uncommonBits_44, UInt<3>(0h7))
node _T_1002 = and(_T_1000, _T_1001)
node _T_1003 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1004 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1005 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1006 = or(_T_972, _T_978)
node _T_1007 = or(_T_1006, _T_984)
node _T_1008 = or(_T_1007, _T_990)
node _T_1009 = or(_T_1008, _T_996)
node _T_1010 = or(_T_1009, _T_1002)
node _T_1011 = or(_T_1010, _T_1003)
node _T_1012 = or(_T_1011, _T_1004)
node _T_1013 = or(_T_1012, _T_1005)
node _T_1014 = and(_T_971, _T_1013)
node _T_1015 = or(UInt<1>(0h0), _T_1014)
node _T_1016 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1017 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1018 = and(_T_1016, _T_1017)
node _T_1019 = or(UInt<1>(0h0), _T_1018)
node _T_1020 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1021 = cvt(_T_1020)
node _T_1022 = and(_T_1021, asSInt(UInt<14>(0h2000)))
node _T_1023 = asSInt(_T_1022)
node _T_1024 = eq(_T_1023, asSInt(UInt<1>(0h0)))
node _T_1025 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1026 = cvt(_T_1025)
node _T_1027 = and(_T_1026, asSInt(UInt<13>(0h1000)))
node _T_1028 = asSInt(_T_1027)
node _T_1029 = eq(_T_1028, asSInt(UInt<1>(0h0)))
node _T_1030 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1031 = cvt(_T_1030)
node _T_1032 = and(_T_1031, asSInt(UInt<18>(0h2f000)))
node _T_1033 = asSInt(_T_1032)
node _T_1034 = eq(_T_1033, asSInt(UInt<1>(0h0)))
node _T_1035 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1036 = cvt(_T_1035)
node _T_1037 = and(_T_1036, asSInt(UInt<17>(0h10000)))
node _T_1038 = asSInt(_T_1037)
node _T_1039 = eq(_T_1038, asSInt(UInt<1>(0h0)))
node _T_1040 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1041 = cvt(_T_1040)
node _T_1042 = and(_T_1041, asSInt(UInt<13>(0h1000)))
node _T_1043 = asSInt(_T_1042)
node _T_1044 = eq(_T_1043, asSInt(UInt<1>(0h0)))
node _T_1045 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1046 = cvt(_T_1045)
node _T_1047 = and(_T_1046, asSInt(UInt<27>(0h4000000)))
node _T_1048 = asSInt(_T_1047)
node _T_1049 = eq(_T_1048, asSInt(UInt<1>(0h0)))
node _T_1050 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1051 = cvt(_T_1050)
node _T_1052 = and(_T_1051, asSInt(UInt<13>(0h1000)))
node _T_1053 = asSInt(_T_1052)
node _T_1054 = eq(_T_1053, asSInt(UInt<1>(0h0)))
node _T_1055 = or(_T_1024, _T_1029)
node _T_1056 = or(_T_1055, _T_1034)
node _T_1057 = or(_T_1056, _T_1039)
node _T_1058 = or(_T_1057, _T_1044)
node _T_1059 = or(_T_1058, _T_1049)
node _T_1060 = or(_T_1059, _T_1054)
node _T_1061 = and(_T_1019, _T_1060)
node _T_1062 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1063 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1064 = cvt(_T_1063)
node _T_1065 = and(_T_1064, asSInt(UInt<17>(0h10000)))
node _T_1066 = asSInt(_T_1065)
node _T_1067 = eq(_T_1066, asSInt(UInt<1>(0h0)))
node _T_1068 = and(_T_1062, _T_1067)
node _T_1069 = or(UInt<1>(0h0), _T_1061)
node _T_1070 = or(_T_1069, _T_1068)
node _T_1071 = and(_T_1015, _T_1070)
node _T_1072 = asUInt(reset)
node _T_1073 = eq(_T_1072, UInt<1>(0h0))
when _T_1073 :
node _T_1074 = eq(_T_1071, UInt<1>(0h0))
when _T_1074 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1071, UInt<1>(0h1), "") : assert_36
node _T_1075 = asUInt(reset)
node _T_1076 = eq(_T_1075, UInt<1>(0h0))
when _T_1076 :
node _T_1077 = eq(source_ok, UInt<1>(0h0))
when _T_1077 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1078 = asUInt(reset)
node _T_1079 = eq(_T_1078, UInt<1>(0h0))
when _T_1079 :
node _T_1080 = eq(is_aligned, UInt<1>(0h0))
when _T_1080 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1081 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1082 = asUInt(reset)
node _T_1083 = eq(_T_1082, UInt<1>(0h0))
when _T_1083 :
node _T_1084 = eq(_T_1081, UInt<1>(0h0))
when _T_1084 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1081, UInt<1>(0h1), "") : assert_39
node _T_1085 = eq(io.in.a.bits.mask, mask)
node _T_1086 = asUInt(reset)
node _T_1087 = eq(_T_1086, UInt<1>(0h0))
when _T_1087 :
node _T_1088 = eq(_T_1085, UInt<1>(0h0))
when _T_1088 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1085, UInt<1>(0h1), "") : assert_40
node _T_1089 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1089 :
node _T_1090 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1091 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1092 = and(_T_1090, _T_1091)
node _T_1093 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_1094 = shr(io.in.a.bits.source, 2)
node _T_1095 = eq(_T_1094, UInt<1>(0h0))
node _T_1096 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_1097 = and(_T_1095, _T_1096)
node _T_1098 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_1099 = and(_T_1097, _T_1098)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0)
node _T_1100 = shr(io.in.a.bits.source, 2)
node _T_1101 = eq(_T_1100, UInt<1>(0h1))
node _T_1102 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_1103 = and(_T_1101, _T_1102)
node _T_1104 = leq(uncommonBits_46, UInt<2>(0h3))
node _T_1105 = and(_T_1103, _T_1104)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0)
node _T_1106 = shr(io.in.a.bits.source, 2)
node _T_1107 = eq(_T_1106, UInt<2>(0h2))
node _T_1108 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_1109 = and(_T_1107, _T_1108)
node _T_1110 = leq(uncommonBits_47, UInt<2>(0h3))
node _T_1111 = and(_T_1109, _T_1110)
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_1112 = shr(io.in.a.bits.source, 2)
node _T_1113 = eq(_T_1112, UInt<2>(0h3))
node _T_1114 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_1115 = and(_T_1113, _T_1114)
node _T_1116 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_1117 = and(_T_1115, _T_1116)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0)
node _T_1118 = shr(io.in.a.bits.source, 3)
node _T_1119 = eq(_T_1118, UInt<3>(0h4))
node _T_1120 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_1121 = and(_T_1119, _T_1120)
node _T_1122 = leq(uncommonBits_49, UInt<3>(0h7))
node _T_1123 = and(_T_1121, _T_1122)
node _T_1124 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1125 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1126 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1127 = or(_T_1093, _T_1099)
node _T_1128 = or(_T_1127, _T_1105)
node _T_1129 = or(_T_1128, _T_1111)
node _T_1130 = or(_T_1129, _T_1117)
node _T_1131 = or(_T_1130, _T_1123)
node _T_1132 = or(_T_1131, _T_1124)
node _T_1133 = or(_T_1132, _T_1125)
node _T_1134 = or(_T_1133, _T_1126)
node _T_1135 = and(_T_1092, _T_1134)
node _T_1136 = or(UInt<1>(0h0), _T_1135)
node _T_1137 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1138 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1139 = and(_T_1137, _T_1138)
node _T_1140 = or(UInt<1>(0h0), _T_1139)
node _T_1141 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1142 = cvt(_T_1141)
node _T_1143 = and(_T_1142, asSInt(UInt<14>(0h2000)))
node _T_1144 = asSInt(_T_1143)
node _T_1145 = eq(_T_1144, asSInt(UInt<1>(0h0)))
node _T_1146 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1147 = cvt(_T_1146)
node _T_1148 = and(_T_1147, asSInt(UInt<13>(0h1000)))
node _T_1149 = asSInt(_T_1148)
node _T_1150 = eq(_T_1149, asSInt(UInt<1>(0h0)))
node _T_1151 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1152 = cvt(_T_1151)
node _T_1153 = and(_T_1152, asSInt(UInt<18>(0h2f000)))
node _T_1154 = asSInt(_T_1153)
node _T_1155 = eq(_T_1154, asSInt(UInt<1>(0h0)))
node _T_1156 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1157 = cvt(_T_1156)
node _T_1158 = and(_T_1157, asSInt(UInt<17>(0h10000)))
node _T_1159 = asSInt(_T_1158)
node _T_1160 = eq(_T_1159, asSInt(UInt<1>(0h0)))
node _T_1161 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1162 = cvt(_T_1161)
node _T_1163 = and(_T_1162, asSInt(UInt<13>(0h1000)))
node _T_1164 = asSInt(_T_1163)
node _T_1165 = eq(_T_1164, asSInt(UInt<1>(0h0)))
node _T_1166 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1167 = cvt(_T_1166)
node _T_1168 = and(_T_1167, asSInt(UInt<27>(0h4000000)))
node _T_1169 = asSInt(_T_1168)
node _T_1170 = eq(_T_1169, asSInt(UInt<1>(0h0)))
node _T_1171 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1172 = cvt(_T_1171)
node _T_1173 = and(_T_1172, asSInt(UInt<13>(0h1000)))
node _T_1174 = asSInt(_T_1173)
node _T_1175 = eq(_T_1174, asSInt(UInt<1>(0h0)))
node _T_1176 = or(_T_1145, _T_1150)
node _T_1177 = or(_T_1176, _T_1155)
node _T_1178 = or(_T_1177, _T_1160)
node _T_1179 = or(_T_1178, _T_1165)
node _T_1180 = or(_T_1179, _T_1170)
node _T_1181 = or(_T_1180, _T_1175)
node _T_1182 = and(_T_1140, _T_1181)
node _T_1183 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1184 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1185 = cvt(_T_1184)
node _T_1186 = and(_T_1185, asSInt(UInt<17>(0h10000)))
node _T_1187 = asSInt(_T_1186)
node _T_1188 = eq(_T_1187, asSInt(UInt<1>(0h0)))
node _T_1189 = and(_T_1183, _T_1188)
node _T_1190 = or(UInt<1>(0h0), _T_1182)
node _T_1191 = or(_T_1190, _T_1189)
node _T_1192 = and(_T_1136, _T_1191)
node _T_1193 = asUInt(reset)
node _T_1194 = eq(_T_1193, UInt<1>(0h0))
when _T_1194 :
node _T_1195 = eq(_T_1192, UInt<1>(0h0))
when _T_1195 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1192, UInt<1>(0h1), "") : assert_41
node _T_1196 = asUInt(reset)
node _T_1197 = eq(_T_1196, UInt<1>(0h0))
when _T_1197 :
node _T_1198 = eq(source_ok, UInt<1>(0h0))
when _T_1198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1199 = asUInt(reset)
node _T_1200 = eq(_T_1199, UInt<1>(0h0))
when _T_1200 :
node _T_1201 = eq(is_aligned, UInt<1>(0h0))
when _T_1201 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1202 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1203 = asUInt(reset)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
when _T_1204 :
node _T_1205 = eq(_T_1202, UInt<1>(0h0))
when _T_1205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1202, UInt<1>(0h1), "") : assert_44
node _T_1206 = eq(io.in.a.bits.mask, mask)
node _T_1207 = asUInt(reset)
node _T_1208 = eq(_T_1207, UInt<1>(0h0))
when _T_1208 :
node _T_1209 = eq(_T_1206, UInt<1>(0h0))
when _T_1209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1206, UInt<1>(0h1), "") : assert_45
node _T_1210 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1210 :
node _T_1211 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1212 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1213 = and(_T_1211, _T_1212)
node _T_1214 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_1215 = shr(io.in.a.bits.source, 2)
node _T_1216 = eq(_T_1215, UInt<1>(0h0))
node _T_1217 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_1218 = and(_T_1216, _T_1217)
node _T_1219 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_1220 = and(_T_1218, _T_1219)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_1221 = shr(io.in.a.bits.source, 2)
node _T_1222 = eq(_T_1221, UInt<1>(0h1))
node _T_1223 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_1224 = and(_T_1222, _T_1223)
node _T_1225 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_1226 = and(_T_1224, _T_1225)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0)
node _T_1227 = shr(io.in.a.bits.source, 2)
node _T_1228 = eq(_T_1227, UInt<2>(0h2))
node _T_1229 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_1230 = and(_T_1228, _T_1229)
node _T_1231 = leq(uncommonBits_52, UInt<2>(0h3))
node _T_1232 = and(_T_1230, _T_1231)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0)
node _T_1233 = shr(io.in.a.bits.source, 2)
node _T_1234 = eq(_T_1233, UInt<2>(0h3))
node _T_1235 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_1236 = and(_T_1234, _T_1235)
node _T_1237 = leq(uncommonBits_53, UInt<2>(0h3))
node _T_1238 = and(_T_1236, _T_1237)
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0)
node _T_1239 = shr(io.in.a.bits.source, 3)
node _T_1240 = eq(_T_1239, UInt<3>(0h4))
node _T_1241 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_1242 = and(_T_1240, _T_1241)
node _T_1243 = leq(uncommonBits_54, UInt<3>(0h7))
node _T_1244 = and(_T_1242, _T_1243)
node _T_1245 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1246 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1247 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1248 = or(_T_1214, _T_1220)
node _T_1249 = or(_T_1248, _T_1226)
node _T_1250 = or(_T_1249, _T_1232)
node _T_1251 = or(_T_1250, _T_1238)
node _T_1252 = or(_T_1251, _T_1244)
node _T_1253 = or(_T_1252, _T_1245)
node _T_1254 = or(_T_1253, _T_1246)
node _T_1255 = or(_T_1254, _T_1247)
node _T_1256 = and(_T_1213, _T_1255)
node _T_1257 = or(UInt<1>(0h0), _T_1256)
node _T_1258 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1259 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1260 = and(_T_1258, _T_1259)
node _T_1261 = or(UInt<1>(0h0), _T_1260)
node _T_1262 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1263 = cvt(_T_1262)
node _T_1264 = and(_T_1263, asSInt(UInt<13>(0h1000)))
node _T_1265 = asSInt(_T_1264)
node _T_1266 = eq(_T_1265, asSInt(UInt<1>(0h0)))
node _T_1267 = and(_T_1261, _T_1266)
node _T_1268 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1269 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1270 = cvt(_T_1269)
node _T_1271 = and(_T_1270, asSInt(UInt<14>(0h2000)))
node _T_1272 = asSInt(_T_1271)
node _T_1273 = eq(_T_1272, asSInt(UInt<1>(0h0)))
node _T_1274 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1275 = cvt(_T_1274)
node _T_1276 = and(_T_1275, asSInt(UInt<17>(0h10000)))
node _T_1277 = asSInt(_T_1276)
node _T_1278 = eq(_T_1277, asSInt(UInt<1>(0h0)))
node _T_1279 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1280 = cvt(_T_1279)
node _T_1281 = and(_T_1280, asSInt(UInt<18>(0h2f000)))
node _T_1282 = asSInt(_T_1281)
node _T_1283 = eq(_T_1282, asSInt(UInt<1>(0h0)))
node _T_1284 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1285 = cvt(_T_1284)
node _T_1286 = and(_T_1285, asSInt(UInt<17>(0h10000)))
node _T_1287 = asSInt(_T_1286)
node _T_1288 = eq(_T_1287, asSInt(UInt<1>(0h0)))
node _T_1289 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1290 = cvt(_T_1289)
node _T_1291 = and(_T_1290, asSInt(UInt<13>(0h1000)))
node _T_1292 = asSInt(_T_1291)
node _T_1293 = eq(_T_1292, asSInt(UInt<1>(0h0)))
node _T_1294 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1295 = cvt(_T_1294)
node _T_1296 = and(_T_1295, asSInt(UInt<27>(0h4000000)))
node _T_1297 = asSInt(_T_1296)
node _T_1298 = eq(_T_1297, asSInt(UInt<1>(0h0)))
node _T_1299 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1300 = cvt(_T_1299)
node _T_1301 = and(_T_1300, asSInt(UInt<13>(0h1000)))
node _T_1302 = asSInt(_T_1301)
node _T_1303 = eq(_T_1302, asSInt(UInt<1>(0h0)))
node _T_1304 = or(_T_1273, _T_1278)
node _T_1305 = or(_T_1304, _T_1283)
node _T_1306 = or(_T_1305, _T_1288)
node _T_1307 = or(_T_1306, _T_1293)
node _T_1308 = or(_T_1307, _T_1298)
node _T_1309 = or(_T_1308, _T_1303)
node _T_1310 = and(_T_1268, _T_1309)
node _T_1311 = or(UInt<1>(0h0), _T_1267)
node _T_1312 = or(_T_1311, _T_1310)
node _T_1313 = and(_T_1257, _T_1312)
node _T_1314 = asUInt(reset)
node _T_1315 = eq(_T_1314, UInt<1>(0h0))
when _T_1315 :
node _T_1316 = eq(_T_1313, UInt<1>(0h0))
when _T_1316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1313, UInt<1>(0h1), "") : assert_46
node _T_1317 = asUInt(reset)
node _T_1318 = eq(_T_1317, UInt<1>(0h0))
when _T_1318 :
node _T_1319 = eq(source_ok, UInt<1>(0h0))
when _T_1319 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1320 = asUInt(reset)
node _T_1321 = eq(_T_1320, UInt<1>(0h0))
when _T_1321 :
node _T_1322 = eq(is_aligned, UInt<1>(0h0))
when _T_1322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1323 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1324 = asUInt(reset)
node _T_1325 = eq(_T_1324, UInt<1>(0h0))
when _T_1325 :
node _T_1326 = eq(_T_1323, UInt<1>(0h0))
when _T_1326 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1323, UInt<1>(0h1), "") : assert_49
node _T_1327 = eq(io.in.a.bits.mask, mask)
node _T_1328 = asUInt(reset)
node _T_1329 = eq(_T_1328, UInt<1>(0h0))
when _T_1329 :
node _T_1330 = eq(_T_1327, UInt<1>(0h0))
when _T_1330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1327, UInt<1>(0h1), "") : assert_50
node _T_1331 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1332 = asUInt(reset)
node _T_1333 = eq(_T_1332, UInt<1>(0h0))
when _T_1333 :
node _T_1334 = eq(_T_1331, UInt<1>(0h0))
when _T_1334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1331, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1335 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1336 = asUInt(reset)
node _T_1337 = eq(_T_1336, UInt<1>(0h0))
when _T_1337 :
node _T_1338 = eq(_T_1335, UInt<1>(0h0))
when _T_1338 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1335, UInt<1>(0h1), "") : assert_52
node _source_ok_T_41 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_42 = shr(io.in.d.bits.source, 2)
node _source_ok_T_43 = eq(_source_ok_T_42, UInt<1>(0h0))
node _source_ok_T_44 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44)
node _source_ok_T_46 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_48 = shr(io.in.d.bits.source, 2)
node _source_ok_T_49 = eq(_source_ok_T_48, UInt<1>(0h1))
node _source_ok_T_50 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50)
node _source_ok_T_52 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_53 = and(_source_ok_T_51, _source_ok_T_52)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_54 = shr(io.in.d.bits.source, 2)
node _source_ok_T_55 = eq(_source_ok_T_54, UInt<2>(0h2))
node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56)
node _source_ok_T_58 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_60 = shr(io.in.d.bits.source, 2)
node _source_ok_T_61 = eq(_source_ok_T_60, UInt<2>(0h3))
node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62)
node _source_ok_T_64 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 2, 0)
node _source_ok_T_66 = shr(io.in.d.bits.source, 3)
node _source_ok_T_67 = eq(_source_ok_T_66, UInt<3>(0h4))
node _source_ok_T_68 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68)
node _source_ok_T_70 = leq(source_ok_uncommonBits_9, UInt<3>(0h7))
node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70)
node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h28))
node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<6>(0h29))
node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<6>(0h2a))
wire _source_ok_WIRE_1 : UInt<1>[9]
connect _source_ok_WIRE_1[0], _source_ok_T_41
connect _source_ok_WIRE_1[1], _source_ok_T_47
connect _source_ok_WIRE_1[2], _source_ok_T_53
connect _source_ok_WIRE_1[3], _source_ok_T_59
connect _source_ok_WIRE_1[4], _source_ok_T_65
connect _source_ok_WIRE_1[5], _source_ok_T_71
connect _source_ok_WIRE_1[6], _source_ok_T_72
connect _source_ok_WIRE_1[7], _source_ok_T_73
connect _source_ok_WIRE_1[8], _source_ok_T_74
node _source_ok_T_75 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[2])
node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[3])
node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[4])
node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[5])
node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[6])
node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[7])
node source_ok_1 = or(_source_ok_T_81, _source_ok_WIRE_1[8])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1339 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1339 :
node _T_1340 = asUInt(reset)
node _T_1341 = eq(_T_1340, UInt<1>(0h0))
when _T_1341 :
node _T_1342 = eq(source_ok_1, UInt<1>(0h0))
when _T_1342 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1343 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1344 = asUInt(reset)
node _T_1345 = eq(_T_1344, UInt<1>(0h0))
when _T_1345 :
node _T_1346 = eq(_T_1343, UInt<1>(0h0))
when _T_1346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1343, UInt<1>(0h1), "") : assert_54
node _T_1347 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1348 = asUInt(reset)
node _T_1349 = eq(_T_1348, UInt<1>(0h0))
when _T_1349 :
node _T_1350 = eq(_T_1347, UInt<1>(0h0))
when _T_1350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1347, UInt<1>(0h1), "") : assert_55
node _T_1351 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1352 = asUInt(reset)
node _T_1353 = eq(_T_1352, UInt<1>(0h0))
when _T_1353 :
node _T_1354 = eq(_T_1351, UInt<1>(0h0))
when _T_1354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1351, UInt<1>(0h1), "") : assert_56
node _T_1355 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1356 = asUInt(reset)
node _T_1357 = eq(_T_1356, UInt<1>(0h0))
when _T_1357 :
node _T_1358 = eq(_T_1355, UInt<1>(0h0))
when _T_1358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1355, UInt<1>(0h1), "") : assert_57
node _T_1359 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1359 :
node _T_1360 = asUInt(reset)
node _T_1361 = eq(_T_1360, UInt<1>(0h0))
when _T_1361 :
node _T_1362 = eq(source_ok_1, UInt<1>(0h0))
when _T_1362 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1363 = asUInt(reset)
node _T_1364 = eq(_T_1363, UInt<1>(0h0))
when _T_1364 :
node _T_1365 = eq(sink_ok, UInt<1>(0h0))
when _T_1365 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1366 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1367 = asUInt(reset)
node _T_1368 = eq(_T_1367, UInt<1>(0h0))
when _T_1368 :
node _T_1369 = eq(_T_1366, UInt<1>(0h0))
when _T_1369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1366, UInt<1>(0h1), "") : assert_60
node _T_1370 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1371 = asUInt(reset)
node _T_1372 = eq(_T_1371, UInt<1>(0h0))
when _T_1372 :
node _T_1373 = eq(_T_1370, UInt<1>(0h0))
when _T_1373 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1370, UInt<1>(0h1), "") : assert_61
node _T_1374 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1375 = asUInt(reset)
node _T_1376 = eq(_T_1375, UInt<1>(0h0))
when _T_1376 :
node _T_1377 = eq(_T_1374, UInt<1>(0h0))
when _T_1377 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1374, UInt<1>(0h1), "") : assert_62
node _T_1378 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1379 = asUInt(reset)
node _T_1380 = eq(_T_1379, UInt<1>(0h0))
when _T_1380 :
node _T_1381 = eq(_T_1378, UInt<1>(0h0))
when _T_1381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1378, UInt<1>(0h1), "") : assert_63
node _T_1382 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1383 = or(UInt<1>(0h1), _T_1382)
node _T_1384 = asUInt(reset)
node _T_1385 = eq(_T_1384, UInt<1>(0h0))
when _T_1385 :
node _T_1386 = eq(_T_1383, UInt<1>(0h0))
when _T_1386 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1383, UInt<1>(0h1), "") : assert_64
node _T_1387 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1387 :
node _T_1388 = asUInt(reset)
node _T_1389 = eq(_T_1388, UInt<1>(0h0))
when _T_1389 :
node _T_1390 = eq(source_ok_1, UInt<1>(0h0))
when _T_1390 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1391 = asUInt(reset)
node _T_1392 = eq(_T_1391, UInt<1>(0h0))
when _T_1392 :
node _T_1393 = eq(sink_ok, UInt<1>(0h0))
when _T_1393 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1394 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1395 = asUInt(reset)
node _T_1396 = eq(_T_1395, UInt<1>(0h0))
when _T_1396 :
node _T_1397 = eq(_T_1394, UInt<1>(0h0))
when _T_1397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1394, UInt<1>(0h1), "") : assert_67
node _T_1398 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1399 = asUInt(reset)
node _T_1400 = eq(_T_1399, UInt<1>(0h0))
when _T_1400 :
node _T_1401 = eq(_T_1398, UInt<1>(0h0))
when _T_1401 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1398, UInt<1>(0h1), "") : assert_68
node _T_1402 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1403 = asUInt(reset)
node _T_1404 = eq(_T_1403, UInt<1>(0h0))
when _T_1404 :
node _T_1405 = eq(_T_1402, UInt<1>(0h0))
when _T_1405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1402, UInt<1>(0h1), "") : assert_69
node _T_1406 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1407 = or(_T_1406, io.in.d.bits.corrupt)
node _T_1408 = asUInt(reset)
node _T_1409 = eq(_T_1408, UInt<1>(0h0))
when _T_1409 :
node _T_1410 = eq(_T_1407, UInt<1>(0h0))
when _T_1410 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1407, UInt<1>(0h1), "") : assert_70
node _T_1411 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1412 = or(UInt<1>(0h1), _T_1411)
node _T_1413 = asUInt(reset)
node _T_1414 = eq(_T_1413, UInt<1>(0h0))
when _T_1414 :
node _T_1415 = eq(_T_1412, UInt<1>(0h0))
when _T_1415 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1412, UInt<1>(0h1), "") : assert_71
node _T_1416 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1416 :
node _T_1417 = asUInt(reset)
node _T_1418 = eq(_T_1417, UInt<1>(0h0))
when _T_1418 :
node _T_1419 = eq(source_ok_1, UInt<1>(0h0))
when _T_1419 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1420 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1421 = asUInt(reset)
node _T_1422 = eq(_T_1421, UInt<1>(0h0))
when _T_1422 :
node _T_1423 = eq(_T_1420, UInt<1>(0h0))
when _T_1423 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1420, UInt<1>(0h1), "") : assert_73
node _T_1424 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1425 = asUInt(reset)
node _T_1426 = eq(_T_1425, UInt<1>(0h0))
when _T_1426 :
node _T_1427 = eq(_T_1424, UInt<1>(0h0))
when _T_1427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1424, UInt<1>(0h1), "") : assert_74
node _T_1428 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1429 = or(UInt<1>(0h1), _T_1428)
node _T_1430 = asUInt(reset)
node _T_1431 = eq(_T_1430, UInt<1>(0h0))
when _T_1431 :
node _T_1432 = eq(_T_1429, UInt<1>(0h0))
when _T_1432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1429, UInt<1>(0h1), "") : assert_75
node _T_1433 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1433 :
node _T_1434 = asUInt(reset)
node _T_1435 = eq(_T_1434, UInt<1>(0h0))
when _T_1435 :
node _T_1436 = eq(source_ok_1, UInt<1>(0h0))
when _T_1436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1437 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1438 = asUInt(reset)
node _T_1439 = eq(_T_1438, UInt<1>(0h0))
when _T_1439 :
node _T_1440 = eq(_T_1437, UInt<1>(0h0))
when _T_1440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1437, UInt<1>(0h1), "") : assert_77
node _T_1441 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1442 = or(_T_1441, io.in.d.bits.corrupt)
node _T_1443 = asUInt(reset)
node _T_1444 = eq(_T_1443, UInt<1>(0h0))
when _T_1444 :
node _T_1445 = eq(_T_1442, UInt<1>(0h0))
when _T_1445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1442, UInt<1>(0h1), "") : assert_78
node _T_1446 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1447 = or(UInt<1>(0h1), _T_1446)
node _T_1448 = asUInt(reset)
node _T_1449 = eq(_T_1448, UInt<1>(0h0))
when _T_1449 :
node _T_1450 = eq(_T_1447, UInt<1>(0h0))
when _T_1450 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1447, UInt<1>(0h1), "") : assert_79
node _T_1451 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1451 :
node _T_1452 = asUInt(reset)
node _T_1453 = eq(_T_1452, UInt<1>(0h0))
when _T_1453 :
node _T_1454 = eq(source_ok_1, UInt<1>(0h0))
when _T_1454 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1455 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1456 = asUInt(reset)
node _T_1457 = eq(_T_1456, UInt<1>(0h0))
when _T_1457 :
node _T_1458 = eq(_T_1455, UInt<1>(0h0))
when _T_1458 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1455, UInt<1>(0h1), "") : assert_81
node _T_1459 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1460 = asUInt(reset)
node _T_1461 = eq(_T_1460, UInt<1>(0h0))
when _T_1461 :
node _T_1462 = eq(_T_1459, UInt<1>(0h0))
when _T_1462 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1459, UInt<1>(0h1), "") : assert_82
node _T_1463 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1464 = or(UInt<1>(0h1), _T_1463)
node _T_1465 = asUInt(reset)
node _T_1466 = eq(_T_1465, UInt<1>(0h0))
when _T_1466 :
node _T_1467 = eq(_T_1464, UInt<1>(0h0))
when _T_1467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1464, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<128>(0h0)
connect _WIRE_4.bits.mask, UInt<16>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<6>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1468 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1469 = asUInt(reset)
node _T_1470 = eq(_T_1469, UInt<1>(0h0))
when _T_1470 :
node _T_1471 = eq(_T_1468, UInt<1>(0h0))
when _T_1471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1468, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<128>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<6>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1472 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1473 = asUInt(reset)
node _T_1474 = eq(_T_1473, UInt<1>(0h0))
when _T_1474 :
node _T_1475 = eq(_T_1472, UInt<1>(0h0))
when _T_1475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1472, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1476 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1477 = asUInt(reset)
node _T_1478 = eq(_T_1477, UInt<1>(0h0))
when _T_1478 :
node _T_1479 = eq(_T_1476, UInt<1>(0h0))
when _T_1479 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1476, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1480 = eq(a_first, UInt<1>(0h0))
node _T_1481 = and(io.in.a.valid, _T_1480)
when _T_1481 :
node _T_1482 = eq(io.in.a.bits.opcode, opcode)
node _T_1483 = asUInt(reset)
node _T_1484 = eq(_T_1483, UInt<1>(0h0))
when _T_1484 :
node _T_1485 = eq(_T_1482, UInt<1>(0h0))
when _T_1485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1482, UInt<1>(0h1), "") : assert_87
node _T_1486 = eq(io.in.a.bits.param, param)
node _T_1487 = asUInt(reset)
node _T_1488 = eq(_T_1487, UInt<1>(0h0))
when _T_1488 :
node _T_1489 = eq(_T_1486, UInt<1>(0h0))
when _T_1489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1486, UInt<1>(0h1), "") : assert_88
node _T_1490 = eq(io.in.a.bits.size, size)
node _T_1491 = asUInt(reset)
node _T_1492 = eq(_T_1491, UInt<1>(0h0))
when _T_1492 :
node _T_1493 = eq(_T_1490, UInt<1>(0h0))
when _T_1493 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1490, UInt<1>(0h1), "") : assert_89
node _T_1494 = eq(io.in.a.bits.source, source)
node _T_1495 = asUInt(reset)
node _T_1496 = eq(_T_1495, UInt<1>(0h0))
when _T_1496 :
node _T_1497 = eq(_T_1494, UInt<1>(0h0))
when _T_1497 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1494, UInt<1>(0h1), "") : assert_90
node _T_1498 = eq(io.in.a.bits.address, address)
node _T_1499 = asUInt(reset)
node _T_1500 = eq(_T_1499, UInt<1>(0h0))
when _T_1500 :
node _T_1501 = eq(_T_1498, UInt<1>(0h0))
when _T_1501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1498, UInt<1>(0h1), "") : assert_91
node _T_1502 = and(io.in.a.ready, io.in.a.valid)
node _T_1503 = and(_T_1502, a_first)
when _T_1503 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1504 = eq(d_first, UInt<1>(0h0))
node _T_1505 = and(io.in.d.valid, _T_1504)
when _T_1505 :
node _T_1506 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1507 = asUInt(reset)
node _T_1508 = eq(_T_1507, UInt<1>(0h0))
when _T_1508 :
node _T_1509 = eq(_T_1506, UInt<1>(0h0))
when _T_1509 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1506, UInt<1>(0h1), "") : assert_92
node _T_1510 = eq(io.in.d.bits.param, param_1)
node _T_1511 = asUInt(reset)
node _T_1512 = eq(_T_1511, UInt<1>(0h0))
when _T_1512 :
node _T_1513 = eq(_T_1510, UInt<1>(0h0))
when _T_1513 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1510, UInt<1>(0h1), "") : assert_93
node _T_1514 = eq(io.in.d.bits.size, size_1)
node _T_1515 = asUInt(reset)
node _T_1516 = eq(_T_1515, UInt<1>(0h0))
when _T_1516 :
node _T_1517 = eq(_T_1514, UInt<1>(0h0))
when _T_1517 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1514, UInt<1>(0h1), "") : assert_94
node _T_1518 = eq(io.in.d.bits.source, source_1)
node _T_1519 = asUInt(reset)
node _T_1520 = eq(_T_1519, UInt<1>(0h0))
when _T_1520 :
node _T_1521 = eq(_T_1518, UInt<1>(0h0))
when _T_1521 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1518, UInt<1>(0h1), "") : assert_95
node _T_1522 = eq(io.in.d.bits.sink, sink)
node _T_1523 = asUInt(reset)
node _T_1524 = eq(_T_1523, UInt<1>(0h0))
when _T_1524 :
node _T_1525 = eq(_T_1522, UInt<1>(0h0))
when _T_1525 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1522, UInt<1>(0h1), "") : assert_96
node _T_1526 = eq(io.in.d.bits.denied, denied)
node _T_1527 = asUInt(reset)
node _T_1528 = eq(_T_1527, UInt<1>(0h0))
when _T_1528 :
node _T_1529 = eq(_T_1526, UInt<1>(0h0))
when _T_1529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1526, UInt<1>(0h1), "") : assert_97
node _T_1530 = and(io.in.d.ready, io.in.d.valid)
node _T_1531 = and(_T_1530, d_first)
when _T_1531 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<43>, clock, reset, UInt<43>(0h0)
regreset inflight_opcodes : UInt<172>, clock, reset, UInt<172>(0h0)
regreset inflight_sizes : UInt<344>, clock, reset, UInt<344>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<43>
connect a_set, UInt<43>(0h0)
wire a_set_wo_ready : UInt<43>
connect a_set_wo_ready, UInt<43>(0h0)
wire a_opcodes_set : UInt<172>
connect a_opcodes_set, UInt<172>(0h0)
wire a_sizes_set : UInt<344>
connect a_sizes_set, UInt<344>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1532 = and(io.in.a.valid, a_first_1)
node _T_1533 = and(_T_1532, UInt<1>(0h1))
when _T_1533 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1534 = and(io.in.a.ready, io.in.a.valid)
node _T_1535 = and(_T_1534, a_first_1)
node _T_1536 = and(_T_1535, UInt<1>(0h1))
when _T_1536 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1537 = dshr(inflight, io.in.a.bits.source)
node _T_1538 = bits(_T_1537, 0, 0)
node _T_1539 = eq(_T_1538, UInt<1>(0h0))
node _T_1540 = asUInt(reset)
node _T_1541 = eq(_T_1540, UInt<1>(0h0))
when _T_1541 :
node _T_1542 = eq(_T_1539, UInt<1>(0h0))
when _T_1542 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1539, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<43>
connect d_clr, UInt<43>(0h0)
wire d_clr_wo_ready : UInt<43>
connect d_clr_wo_ready, UInt<43>(0h0)
wire d_opcodes_clr : UInt<172>
connect d_opcodes_clr, UInt<172>(0h0)
wire d_sizes_clr : UInt<344>
connect d_sizes_clr, UInt<344>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1543 = and(io.in.d.valid, d_first_1)
node _T_1544 = and(_T_1543, UInt<1>(0h1))
node _T_1545 = eq(d_release_ack, UInt<1>(0h0))
node _T_1546 = and(_T_1544, _T_1545)
when _T_1546 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1547 = and(io.in.d.ready, io.in.d.valid)
node _T_1548 = and(_T_1547, d_first_1)
node _T_1549 = and(_T_1548, UInt<1>(0h1))
node _T_1550 = eq(d_release_ack, UInt<1>(0h0))
node _T_1551 = and(_T_1549, _T_1550)
when _T_1551 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1552 = and(io.in.d.valid, d_first_1)
node _T_1553 = and(_T_1552, UInt<1>(0h1))
node _T_1554 = eq(d_release_ack, UInt<1>(0h0))
node _T_1555 = and(_T_1553, _T_1554)
when _T_1555 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1556 = dshr(inflight, io.in.d.bits.source)
node _T_1557 = bits(_T_1556, 0, 0)
node _T_1558 = or(_T_1557, same_cycle_resp)
node _T_1559 = asUInt(reset)
node _T_1560 = eq(_T_1559, UInt<1>(0h0))
when _T_1560 :
node _T_1561 = eq(_T_1558, UInt<1>(0h0))
when _T_1561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1558, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1562 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1563 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1564 = or(_T_1562, _T_1563)
node _T_1565 = asUInt(reset)
node _T_1566 = eq(_T_1565, UInt<1>(0h0))
when _T_1566 :
node _T_1567 = eq(_T_1564, UInt<1>(0h0))
when _T_1567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1564, UInt<1>(0h1), "") : assert_100
node _T_1568 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1569 = asUInt(reset)
node _T_1570 = eq(_T_1569, UInt<1>(0h0))
when _T_1570 :
node _T_1571 = eq(_T_1568, UInt<1>(0h0))
when _T_1571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1568, UInt<1>(0h1), "") : assert_101
else :
node _T_1572 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1573 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1574 = or(_T_1572, _T_1573)
node _T_1575 = asUInt(reset)
node _T_1576 = eq(_T_1575, UInt<1>(0h0))
when _T_1576 :
node _T_1577 = eq(_T_1574, UInt<1>(0h0))
when _T_1577 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1574, UInt<1>(0h1), "") : assert_102
node _T_1578 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1579 = asUInt(reset)
node _T_1580 = eq(_T_1579, UInt<1>(0h0))
when _T_1580 :
node _T_1581 = eq(_T_1578, UInt<1>(0h0))
when _T_1581 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1578, UInt<1>(0h1), "") : assert_103
node _T_1582 = and(io.in.d.valid, d_first_1)
node _T_1583 = and(_T_1582, a_first_1)
node _T_1584 = and(_T_1583, io.in.a.valid)
node _T_1585 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1586 = and(_T_1584, _T_1585)
node _T_1587 = eq(d_release_ack, UInt<1>(0h0))
node _T_1588 = and(_T_1586, _T_1587)
when _T_1588 :
node _T_1589 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1590 = or(_T_1589, io.in.a.ready)
node _T_1591 = asUInt(reset)
node _T_1592 = eq(_T_1591, UInt<1>(0h0))
when _T_1592 :
node _T_1593 = eq(_T_1590, UInt<1>(0h0))
when _T_1593 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1590, UInt<1>(0h1), "") : assert_104
node _T_1594 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1595 = orr(a_set_wo_ready)
node _T_1596 = eq(_T_1595, UInt<1>(0h0))
node _T_1597 = or(_T_1594, _T_1596)
node _T_1598 = asUInt(reset)
node _T_1599 = eq(_T_1598, UInt<1>(0h0))
when _T_1599 :
node _T_1600 = eq(_T_1597, UInt<1>(0h0))
when _T_1600 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1597, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_6
node _T_1601 = orr(inflight)
node _T_1602 = eq(_T_1601, UInt<1>(0h0))
node _T_1603 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1604 = or(_T_1602, _T_1603)
node _T_1605 = lt(watchdog, plusarg_reader.out)
node _T_1606 = or(_T_1604, _T_1605)
node _T_1607 = asUInt(reset)
node _T_1608 = eq(_T_1607, UInt<1>(0h0))
when _T_1608 :
node _T_1609 = eq(_T_1606, UInt<1>(0h0))
when _T_1609 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1606, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1610 = and(io.in.a.ready, io.in.a.valid)
node _T_1611 = and(io.in.d.ready, io.in.d.valid)
node _T_1612 = or(_T_1610, _T_1611)
when _T_1612 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<43>, clock, reset, UInt<43>(0h0)
regreset inflight_opcodes_1 : UInt<172>, clock, reset, UInt<172>(0h0)
regreset inflight_sizes_1 : UInt<344>, clock, reset, UInt<344>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<128>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<6>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<128>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<6>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<43>
connect c_set, UInt<43>(0h0)
wire c_set_wo_ready : UInt<43>
connect c_set_wo_ready, UInt<43>(0h0)
wire c_opcodes_set : UInt<172>
connect c_opcodes_set, UInt<172>(0h0)
wire c_sizes_set : UInt<344>
connect c_sizes_set, UInt<344>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<128>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<6>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1613 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<128>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<6>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1614 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1615 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1616 = and(_T_1614, _T_1615)
node _T_1617 = and(_T_1613, _T_1616)
when _T_1617 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<128>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<6>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<128>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<6>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1618 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1619 = and(_T_1618, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<128>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<6>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1620 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1621 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1622 = and(_T_1620, _T_1621)
node _T_1623 = and(_T_1619, _T_1622)
when _T_1623 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<128>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<6>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<128>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<6>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<128>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<6>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<128>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<6>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<128>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<6>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<128>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<6>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1624 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1625 = bits(_T_1624, 0, 0)
node _T_1626 = eq(_T_1625, UInt<1>(0h0))
node _T_1627 = asUInt(reset)
node _T_1628 = eq(_T_1627, UInt<1>(0h0))
when _T_1628 :
node _T_1629 = eq(_T_1626, UInt<1>(0h0))
when _T_1629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1626, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<128>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<6>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<128>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<6>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<43>
connect d_clr_1, UInt<43>(0h0)
wire d_clr_wo_ready_1 : UInt<43>
connect d_clr_wo_ready_1, UInt<43>(0h0)
wire d_opcodes_clr_1 : UInt<172>
connect d_opcodes_clr_1, UInt<172>(0h0)
wire d_sizes_clr_1 : UInt<344>
connect d_sizes_clr_1, UInt<344>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1630 = and(io.in.d.valid, d_first_2)
node _T_1631 = and(_T_1630, UInt<1>(0h1))
node _T_1632 = and(_T_1631, d_release_ack_1)
when _T_1632 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1633 = and(io.in.d.ready, io.in.d.valid)
node _T_1634 = and(_T_1633, d_first_2)
node _T_1635 = and(_T_1634, UInt<1>(0h1))
node _T_1636 = and(_T_1635, d_release_ack_1)
when _T_1636 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1637 = and(io.in.d.valid, d_first_2)
node _T_1638 = and(_T_1637, UInt<1>(0h1))
node _T_1639 = and(_T_1638, d_release_ack_1)
when _T_1639 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<128>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<6>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<128>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<6>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<128>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<6>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1640 = dshr(inflight_1, io.in.d.bits.source)
node _T_1641 = bits(_T_1640, 0, 0)
node _T_1642 = or(_T_1641, same_cycle_resp_1)
node _T_1643 = asUInt(reset)
node _T_1644 = eq(_T_1643, UInt<1>(0h0))
when _T_1644 :
node _T_1645 = eq(_T_1642, UInt<1>(0h0))
when _T_1645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1642, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<128>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<6>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1646 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1647 = asUInt(reset)
node _T_1648 = eq(_T_1647, UInt<1>(0h0))
when _T_1648 :
node _T_1649 = eq(_T_1646, UInt<1>(0h0))
when _T_1649 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1646, UInt<1>(0h1), "") : assert_109
else :
node _T_1650 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1651 = asUInt(reset)
node _T_1652 = eq(_T_1651, UInt<1>(0h0))
when _T_1652 :
node _T_1653 = eq(_T_1650, UInt<1>(0h0))
when _T_1653 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1650, UInt<1>(0h1), "") : assert_110
node _T_1654 = and(io.in.d.valid, d_first_2)
node _T_1655 = and(_T_1654, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<128>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<6>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1656 = and(_T_1655, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<128>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<6>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1657 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1658 = and(_T_1656, _T_1657)
node _T_1659 = and(_T_1658, d_release_ack_1)
node _T_1660 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1661 = and(_T_1659, _T_1660)
when _T_1661 :
node _T_1662 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<128>(0h0)
connect _WIRE_26.bits.address, UInt<29>(0h0)
connect _WIRE_26.bits.source, UInt<6>(0h0)
connect _WIRE_26.bits.size, UInt<4>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1663 = or(_T_1662, _WIRE_27.ready)
node _T_1664 = asUInt(reset)
node _T_1665 = eq(_T_1664, UInt<1>(0h0))
when _T_1665 :
node _T_1666 = eq(_T_1663, UInt<1>(0h0))
when _T_1666 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1663, UInt<1>(0h1), "") : assert_111
node _T_1667 = orr(c_set_wo_ready)
when _T_1667 :
node _T_1668 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1669 = asUInt(reset)
node _T_1670 = eq(_T_1669, UInt<1>(0h0))
when _T_1670 :
node _T_1671 = eq(_T_1668, UInt<1>(0h0))
when _T_1671 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1668, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_7
node _T_1672 = orr(inflight_1)
node _T_1673 = eq(_T_1672, UInt<1>(0h0))
node _T_1674 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1675 = or(_T_1673, _T_1674)
node _T_1676 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1677 = or(_T_1675, _T_1676)
node _T_1678 = asUInt(reset)
node _T_1679 = eq(_T_1678, UInt<1>(0h0))
when _T_1679 :
node _T_1680 = eq(_T_1677, UInt<1>(0h0))
when _T_1680 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1677, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<128>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<6>(0h0)
connect _WIRE_28.bits.size, UInt<4>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1681 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1682 = and(io.in.d.ready, io.in.d.valid)
node _T_1683 = or(_T_1681, _T_1682)
when _T_1683 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_3( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59]
wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14]
wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27]
wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25]
wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_70 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28]
wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28]
wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_first_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_first_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_first_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_first_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_set_wo_ready_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_set_wo_ready_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_opcodes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_opcodes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_sizes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_sizes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_opcodes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_opcodes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_sizes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_sizes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_probe_ack_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_probe_ack_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_probe_ack_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_probe_ack_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _same_cycle_resp_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _same_cycle_resp_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _same_cycle_resp_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _same_cycle_resp_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _same_cycle_resp_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _same_cycle_resp_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [515:0] _c_sizes_set_T_1 = 516'h0; // @[Monitor.scala:768:52]
wire [8:0] _c_opcodes_set_T = 9'h0; // @[Monitor.scala:767:79]
wire [8:0] _c_sizes_set_T = 9'h0; // @[Monitor.scala:768:77]
wire [514:0] _c_opcodes_set_T_1 = 515'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [63:0] _c_set_wo_ready_T = 64'h1; // @[OneHot.scala:58:35]
wire [63:0] _c_set_T = 64'h1; // @[OneHot.scala:58:35]
wire [343:0] c_sizes_set = 344'h0; // @[Monitor.scala:741:34]
wire [171:0] c_opcodes_set = 172'h0; // @[Monitor.scala:740:34]
wire [42:0] c_set = 43'h0; // @[Monitor.scala:738:34]
wire [42:0] c_set_wo_ready = 43'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_25 = io_in_a_bits_source_0[5:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 3'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire _source_ok_T_31 = io_in_a_bits_source_0 == 6'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire _source_ok_T_32 = io_in_a_bits_source_0 == 6'h29; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire _source_ok_T_33 = io_in_a_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31]
wire _source_ok_T_34 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_40 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}]
wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_sub_0_1 = |(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21]
wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_44 = _uncommonBits_T_44[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_41 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_42 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_48 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_54 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_60 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_43 = _source_ok_T_42 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_49 = _source_ok_T_48 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_55 = _source_ok_T_54 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_61 = _source_ok_T_60 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_66 = io_in_d_bits_source_0[5:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_67 = _source_ok_T_66 == 3'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_71 = _source_ok_T_69; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31]
wire _source_ok_T_72 = io_in_d_bits_source_0 == 6'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31]
wire _source_ok_T_73 = io_in_d_bits_source_0 == 6'h29; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31]
wire _source_ok_T_74 = io_in_d_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire _source_ok_T_75 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_81 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1610 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1610; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1610; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [7:0] a_first_counter; // @[Edges.scala:229:27]
wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [5:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1683 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1683; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1683; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1683; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [5:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [42:0] inflight; // @[Monitor.scala:614:27]
reg [171:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [343:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [7:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46]
wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [42:0] a_set; // @[Monitor.scala:626:34]
wire [42:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [171:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [343:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [8:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [171:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [171:0] _a_opcode_lookup_T_6 = {168'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [171:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[171:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [8:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [343:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [343:0] _a_size_lookup_T_6 = {336'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [343:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[343:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [63:0] _GEN_3 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [63:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[42:0] : 43'h0; // @[OneHot.scala:58:35]
wire _T_1536 = _T_1610 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1536 ? _a_set_T[42:0] : 43'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1536 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1536 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [8:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1536 ? _a_opcodes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [8:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [515:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1536 ? _a_sizes_set_T_1[343:0] : 344'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [42:0] d_clr; // @[Monitor.scala:664:34]
wire [42:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [171:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [343:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1582 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [63:0] _GEN_5 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1582 & ~d_release_ack ? _d_clr_wo_ready_T[42:0] : 43'h0; // @[OneHot.scala:58:35]
wire _T_1551 = _T_1683 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1551 ? _d_clr_T[42:0] : 43'h0; // @[OneHot.scala:58:35]
wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1551 ? _d_opcodes_clr_T_5[171:0] : 172'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [526:0] _d_sizes_clr_T_5 = 527'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1551 ? _d_sizes_clr_T_5[343:0] : 344'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [42:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [42:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [42:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [171:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [171:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [171:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [343:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [343:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [343:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [42:0] inflight_1; // @[Monitor.scala:726:35]
wire [42:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [171:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [171:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [343:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [343:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46]
wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [171:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [171:0] _c_opcode_lookup_T_6 = {168'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [171:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[171:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [343:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [343:0] _c_size_lookup_T_6 = {336'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [343:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[343:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [42:0] d_clr_1; // @[Monitor.scala:774:34]
wire [42:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [171:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [343:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1654 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1654 & d_release_ack_1 ? _d_clr_wo_ready_T_1[42:0] : 43'h0; // @[OneHot.scala:58:35]
wire _T_1636 = _T_1683 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1636 ? _d_clr_T_1[42:0] : 43'h0; // @[OneHot.scala:58:35]
wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1636 ? _d_opcodes_clr_T_11[171:0] : 172'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [526:0] _d_sizes_clr_T_11 = 527'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1636 ? _d_sizes_clr_T_11[343:0] : 344'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 6'h0; // @[Monitor.scala:36:7, :795:113]
wire [42:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [42:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [171:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [171:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [343:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [343:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_150 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_150( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_183 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_183( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module PE_155 :
input clock : Clock
input reset : Reset
output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>}
node _reg_T = eq(io.dir, UInt<1>(0h0))
node _reg_T_1 = mux(_reg_T, io.inR, io.inD)
reg reg : SInt<8>, clock
when io.en :
connect reg, _reg_T_1
connect io.outU, reg
connect io.outL, reg | module PE_155( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_20 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_20( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLNoC_router_24ClockSinkDomain :
output auto : { routers_debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, routers_source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, routers_source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, routers_source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip routers_dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip routers_dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip routers_dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst routers of Router_22
connect routers.clock, childClock
connect routers.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
connect clockNodeIn, auto.clock_in
connect routers.auto.dest_nodes_in_0, auto.routers_dest_nodes_in_0
connect routers.auto.dest_nodes_in_1, auto.routers_dest_nodes_in_1
connect routers.auto.dest_nodes_in_2, auto.routers_dest_nodes_in_2
connect routers.auto.source_nodes_out_0.vc_free, auto.routers_source_nodes_out_0.vc_free
connect routers.auto.source_nodes_out_0.credit_return, auto.routers_source_nodes_out_0.credit_return
connect auto.routers_source_nodes_out_0.flit, routers.auto.source_nodes_out_0.flit
connect routers.auto.source_nodes_out_1.vc_free, auto.routers_source_nodes_out_1.vc_free
connect routers.auto.source_nodes_out_1.credit_return, auto.routers_source_nodes_out_1.credit_return
connect auto.routers_source_nodes_out_1.flit, routers.auto.source_nodes_out_1.flit
connect routers.auto.source_nodes_out_2.vc_free, auto.routers_source_nodes_out_2.vc_free
connect routers.auto.source_nodes_out_2.credit_return, auto.routers_source_nodes_out_2.credit_return
connect auto.routers_source_nodes_out_2.flit, routers.auto.source_nodes_out_2.flit
connect auto.routers_debug_out, routers.auto.debug_out
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset | module TLNoC_router_24ClockSinkDomain( // @[ClockDomain.scala:14:9]
output [2:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_routers_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_routers_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_routers_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_routers_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_routers_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_routers_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_routers_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_routers_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_routers_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_routers_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_routers_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_routers_dest_nodes_in_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
Router_22 routers ( // @[NoC.scala:67:22]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0),
.auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1),
.auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2),
.auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0),
.auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1),
.auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2),
.auto_source_nodes_out_2_flit_0_valid (auto_routers_source_nodes_out_2_flit_0_valid),
.auto_source_nodes_out_2_flit_0_bits_head (auto_routers_source_nodes_out_2_flit_0_bits_head),
.auto_source_nodes_out_2_flit_0_bits_tail (auto_routers_source_nodes_out_2_flit_0_bits_tail),
.auto_source_nodes_out_2_flit_0_bits_payload (auto_routers_source_nodes_out_2_flit_0_bits_payload),
.auto_source_nodes_out_2_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_2_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_2_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_2_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_2_credit_return (auto_routers_source_nodes_out_2_credit_return),
.auto_source_nodes_out_2_vc_free (auto_routers_source_nodes_out_2_vc_free),
.auto_source_nodes_out_1_flit_0_valid (auto_routers_source_nodes_out_1_flit_0_valid),
.auto_source_nodes_out_1_flit_0_bits_head (auto_routers_source_nodes_out_1_flit_0_bits_head),
.auto_source_nodes_out_1_flit_0_bits_tail (auto_routers_source_nodes_out_1_flit_0_bits_tail),
.auto_source_nodes_out_1_flit_0_bits_payload (auto_routers_source_nodes_out_1_flit_0_bits_payload),
.auto_source_nodes_out_1_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_1_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_1_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_1_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_1_credit_return (auto_routers_source_nodes_out_1_credit_return),
.auto_source_nodes_out_1_vc_free (auto_routers_source_nodes_out_1_vc_free),
.auto_source_nodes_out_0_flit_0_valid (auto_routers_source_nodes_out_0_flit_0_valid),
.auto_source_nodes_out_0_flit_0_bits_head (auto_routers_source_nodes_out_0_flit_0_bits_head),
.auto_source_nodes_out_0_flit_0_bits_tail (auto_routers_source_nodes_out_0_flit_0_bits_tail),
.auto_source_nodes_out_0_flit_0_bits_payload (auto_routers_source_nodes_out_0_flit_0_bits_payload),
.auto_source_nodes_out_0_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_0_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_0_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_0_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_0_credit_return (auto_routers_source_nodes_out_0_credit_return),
.auto_source_nodes_out_0_vc_free (auto_routers_source_nodes_out_0_vc_free),
.auto_dest_nodes_in_2_flit_0_valid (auto_routers_dest_nodes_in_2_flit_0_valid),
.auto_dest_nodes_in_2_flit_0_bits_head (auto_routers_dest_nodes_in_2_flit_0_bits_head),
.auto_dest_nodes_in_2_flit_0_bits_tail (auto_routers_dest_nodes_in_2_flit_0_bits_tail),
.auto_dest_nodes_in_2_flit_0_bits_payload (auto_routers_dest_nodes_in_2_flit_0_bits_payload),
.auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_2_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_2_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_2_credit_return (auto_routers_dest_nodes_in_2_credit_return),
.auto_dest_nodes_in_2_vc_free (auto_routers_dest_nodes_in_2_vc_free),
.auto_dest_nodes_in_1_flit_0_valid (auto_routers_dest_nodes_in_1_flit_0_valid),
.auto_dest_nodes_in_1_flit_0_bits_head (auto_routers_dest_nodes_in_1_flit_0_bits_head),
.auto_dest_nodes_in_1_flit_0_bits_tail (auto_routers_dest_nodes_in_1_flit_0_bits_tail),
.auto_dest_nodes_in_1_flit_0_bits_payload (auto_routers_dest_nodes_in_1_flit_0_bits_payload),
.auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_1_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_1_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_1_credit_return (auto_routers_dest_nodes_in_1_credit_return),
.auto_dest_nodes_in_1_vc_free (auto_routers_dest_nodes_in_1_vc_free),
.auto_dest_nodes_in_0_flit_0_valid (auto_routers_dest_nodes_in_0_flit_0_valid),
.auto_dest_nodes_in_0_flit_0_bits_head (auto_routers_dest_nodes_in_0_flit_0_bits_head),
.auto_dest_nodes_in_0_flit_0_bits_tail (auto_routers_dest_nodes_in_0_flit_0_bits_tail),
.auto_dest_nodes_in_0_flit_0_bits_payload (auto_routers_dest_nodes_in_0_flit_0_bits_payload),
.auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_0_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_0_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_0_credit_return (auto_routers_dest_nodes_in_0_credit_return),
.auto_dest_nodes_in_0_vc_free (auto_routers_dest_nodes_in_0_vc_free)
); // @[NoC.scala:67:22]
endmodule |
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